Unnamed: 0 int64 0 350k | level_0 int64 0 351k | ApplicationNumber int64 9.75M 96.1M | ArtUnit int64 1.6k 3.99k | Abstract stringlengths 1 8.37k | Claims stringlengths 3 292k | abstract-claims stringlengths 68 293k | TechCenter int64 1.6k 3.9k |
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11,800 | 11,800 | 13,367,870 | 2,865 | A system may include determination of a spatial power map associated with an integrated circuit based on an architecture of the circuit, generation of a spatial thermal map associated with the integrated circuit based on the spatial power map, and determination of a spatial leakage power map based on the spatial thermal map. In some aspects, a system includes determination of a temperature of an integrated circuit, comparison of the temperature with a thermal divergence temperature, determination that the temperature of the integrated circuit is primarily due to leakage power, and disabling of power to the integrated circuit. | 1. An integrated circuit comprising:
a processing core; a temperature sensor to determine a temperature of the processing core; a lookup table to store a temperature value; and a comparator to compare the temperature of the processing core with the stored temperature value. 2. The integrated circuit of claim 1, wherein the temperature sensor comprises a digital thermometer. 3. The integrated circuit of claim 1, wherein the temperature sensor is positioned at a location where leakage power is higher than other locations in the processing core. 4. The integrated circuit of claim 1, wherein the temperature value stored in the lookup table is a thermal divergence temperature. 5. The integrated circuit of claim 1, wherein the look-up table is operable to store a plurality of temperature values, wherein at least one of the temperature value from the plurality of temperature values is flagged to indicate applicability of the temperature value to the integrated circuit. 6. The integrated circuit of claim 1, wherein the comparator is positioned in the processing core. 7. The integrated circuit of claim 1 further comprises a power regulator which is operable to reduce power supply level to the processing core or eliminate power supply to the processing core according to an output signal from the comparator. 8. The integrated circuit of claim 7, wherein the power regulator is operable to eliminate power supply to the processing core when an off-chip voltage regulator instructs the power regulator to stop power delivery. 9. The integrated circuit of claim 1, wherein the temperature sensor is to determine the temperature of processing core due to leakage power when the processing core is inactive. 10. The integrated circuit of claim 9, wherein the determination that the processing core is inactive is made via an operating system. 11. The integrated circuit of claim 1, wherein temperature sensor to determine a second temperature of the processing core after it is determined that the temperature of the processing core is due to leakage power, and wherein the integrated circuit is further to determine that the second temperature is greater than the temperature value. 12. A system comprising:
a memory; an integrated circuit, coupled to the memory, comprises:
a processing core;
a temperature sensor to determine a temperature of the processing core;
a lookup table to store a temperature value; and
a comparator to compare the temperature of the processing core with the stored temperature value; and
an operating system to indicate whether the processing core in the integrated circuit is active. 13. The system of claim 12, wherein the memory is at least one of:
Double Data Rate (DDR) Random Access Memory (RAM); Single Data Rate (SDR) RAM; or Programmable Read Only Memory (PROM). 14. The system of claim 12, wherein the processing core comprises an execution engine to illicit behavior of the integrated circuit. 15. The system of claim 12, wherein the temperature sensor comprises a digital thermometer. 16. The system of claim 12, wherein the temperature sensor is positioned at a location where leakage power is higher than other locations in the processing core. 17. The system of claim 12, wherein the temperature value stored in the lookup table is a thermal divergence temperature. 18. The system of claim 12, wherein the comparator is positioned in the processing core. 19. The system of claim 12, wherein the integrated circuit further comprises a power regulator which is operable to reduce power supply level to the processing core or eliminate power supply to the processing core according to an output signal from the comparator. 20. The system of claim 19 further comprises a voltage regulator external to the integrated circuit which is operable to instruct the power regulator to stop power delivery according to the output signal from the comparator. | A system may include determination of a spatial power map associated with an integrated circuit based on an architecture of the circuit, generation of a spatial thermal map associated with the integrated circuit based on the spatial power map, and determination of a spatial leakage power map based on the spatial thermal map. In some aspects, a system includes determination of a temperature of an integrated circuit, comparison of the temperature with a thermal divergence temperature, determination that the temperature of the integrated circuit is primarily due to leakage power, and disabling of power to the integrated circuit.1. An integrated circuit comprising:
a processing core; a temperature sensor to determine a temperature of the processing core; a lookup table to store a temperature value; and a comparator to compare the temperature of the processing core with the stored temperature value. 2. The integrated circuit of claim 1, wherein the temperature sensor comprises a digital thermometer. 3. The integrated circuit of claim 1, wherein the temperature sensor is positioned at a location where leakage power is higher than other locations in the processing core. 4. The integrated circuit of claim 1, wherein the temperature value stored in the lookup table is a thermal divergence temperature. 5. The integrated circuit of claim 1, wherein the look-up table is operable to store a plurality of temperature values, wherein at least one of the temperature value from the plurality of temperature values is flagged to indicate applicability of the temperature value to the integrated circuit. 6. The integrated circuit of claim 1, wherein the comparator is positioned in the processing core. 7. The integrated circuit of claim 1 further comprises a power regulator which is operable to reduce power supply level to the processing core or eliminate power supply to the processing core according to an output signal from the comparator. 8. The integrated circuit of claim 7, wherein the power regulator is operable to eliminate power supply to the processing core when an off-chip voltage regulator instructs the power regulator to stop power delivery. 9. The integrated circuit of claim 1, wherein the temperature sensor is to determine the temperature of processing core due to leakage power when the processing core is inactive. 10. The integrated circuit of claim 9, wherein the determination that the processing core is inactive is made via an operating system. 11. The integrated circuit of claim 1, wherein temperature sensor to determine a second temperature of the processing core after it is determined that the temperature of the processing core is due to leakage power, and wherein the integrated circuit is further to determine that the second temperature is greater than the temperature value. 12. A system comprising:
a memory; an integrated circuit, coupled to the memory, comprises:
a processing core;
a temperature sensor to determine a temperature of the processing core;
a lookup table to store a temperature value; and
a comparator to compare the temperature of the processing core with the stored temperature value; and
an operating system to indicate whether the processing core in the integrated circuit is active. 13. The system of claim 12, wherein the memory is at least one of:
Double Data Rate (DDR) Random Access Memory (RAM); Single Data Rate (SDR) RAM; or Programmable Read Only Memory (PROM). 14. The system of claim 12, wherein the processing core comprises an execution engine to illicit behavior of the integrated circuit. 15. The system of claim 12, wherein the temperature sensor comprises a digital thermometer. 16. The system of claim 12, wherein the temperature sensor is positioned at a location where leakage power is higher than other locations in the processing core. 17. The system of claim 12, wherein the temperature value stored in the lookup table is a thermal divergence temperature. 18. The system of claim 12, wherein the comparator is positioned in the processing core. 19. The system of claim 12, wherein the integrated circuit further comprises a power regulator which is operable to reduce power supply level to the processing core or eliminate power supply to the processing core according to an output signal from the comparator. 20. The system of claim 19 further comprises a voltage regulator external to the integrated circuit which is operable to instruct the power regulator to stop power delivery according to the output signal from the comparator. | 2,800 |
11,801 | 11,801 | 14,731,955 | 2,848 | A cable separator includes a body, and the body includes a polycarbonate-based material that is at least a partially foamed. Cables and methods of manufacturing such cables having a separator are also provided. | 1. A cable separator comprising a body, wherein the body comprises a polycarbonate-based material, and wherein the polycarbonate-based material is at least partially foamed. 2. The cable separator of claim 1, wherein the at least partially foamed polycarbonate-based material has a foam rate of about 25% to about 75%. 3. The cable separator of claim 1, wherein the polycarbonate-based material comprises polycarbonate resin, a polycarbonate copolymer, and at least one of a flame retardant and a smoke suppressant. 4. The cable separator of claim 3, wherein the polycarbonate resin comprises polycarbonate polymer, and wherein the polycarbonate polymer is at least 50% of the total weight of the polycarbonate-based material. 5. The cable separator of claim 3, wherein the polycarbonate copolymer comprises at least one of polycarbonate-siloxane copolymer and brominated polycarbonate. 6. The cable separator of claim 5, wherein siloxane in the polycarbonate-siloxane copolymer comprises about 0.5% to about 5% by weight of the polycarbonate-based material. 7. The cable separator of claim 1 is substantially halogen-free. 8. The cable separator of claim 1, wherein the body is formed via extrusion. 9. The cable separator of claim 3, wherein the flame retardant is selected from the group consisting of a metal sulfonate, a polymeric char former, a halogenated flame retardant, fire retardant filler, and an anti-drip additive. 10. The cable separator of claim 9, wherein the metal sulfonate is selected from the group consisting of potassium diphenylsulfon-3-sulphonate, potassium-perfluorobutane-sulphonate, and combinations thereof. 11. The cable separator of claim 9, wherein at least one of the anti-drip additive and fire retardant filler is selected from the group consisting of polytetrafluoroethylene and styrene-acrylonitrile treated polytetrafluoroethylene. 12. The cable separator of claim 1, wherein the body includes one or more projections extending in an outward direction. 13. The cable separator of claim 12, wherein the body is a cross-web or is a substantially flat member. 14. The cable separator of claim 1 exhibits a Limiting Oxygen Index (LOI) of about 30% or more. 15. A communication cable having a cable separator of claim 1. 16. The communication cable of claim 15 passes the flame test according to NFPA 262. 17. The communications cable of claim 15, further comprising a plurality of conductors and a jacket layer; and
wherein the jacket layer surrounds the plurality of conductors and the separator along the length of the cable. 18. A cable separator comprising a body, wherein the body comprises a polycarbonate polymer, a polycarbonate-siloxane copolymer and a metal sulfonate, and wherein the body is at least partially foamed. 19. A cable separator comprising a body, wherein the body comprises a polycarbonate polymer, a polycarbonate-siloxane copolymer and one or more of a halogenated flame retardant and an anti-drip additive, and wherein the body is at least partially foamed. 20. The cable separator of claim 19, wherein the halogenated flame retardant is a brominated polycarbonate and the anti-drip additive comprises a styrene-acrylonitrile treated polytetrafluoroethylene. | A cable separator includes a body, and the body includes a polycarbonate-based material that is at least a partially foamed. Cables and methods of manufacturing such cables having a separator are also provided.1. A cable separator comprising a body, wherein the body comprises a polycarbonate-based material, and wherein the polycarbonate-based material is at least partially foamed. 2. The cable separator of claim 1, wherein the at least partially foamed polycarbonate-based material has a foam rate of about 25% to about 75%. 3. The cable separator of claim 1, wherein the polycarbonate-based material comprises polycarbonate resin, a polycarbonate copolymer, and at least one of a flame retardant and a smoke suppressant. 4. The cable separator of claim 3, wherein the polycarbonate resin comprises polycarbonate polymer, and wherein the polycarbonate polymer is at least 50% of the total weight of the polycarbonate-based material. 5. The cable separator of claim 3, wherein the polycarbonate copolymer comprises at least one of polycarbonate-siloxane copolymer and brominated polycarbonate. 6. The cable separator of claim 5, wherein siloxane in the polycarbonate-siloxane copolymer comprises about 0.5% to about 5% by weight of the polycarbonate-based material. 7. The cable separator of claim 1 is substantially halogen-free. 8. The cable separator of claim 1, wherein the body is formed via extrusion. 9. The cable separator of claim 3, wherein the flame retardant is selected from the group consisting of a metal sulfonate, a polymeric char former, a halogenated flame retardant, fire retardant filler, and an anti-drip additive. 10. The cable separator of claim 9, wherein the metal sulfonate is selected from the group consisting of potassium diphenylsulfon-3-sulphonate, potassium-perfluorobutane-sulphonate, and combinations thereof. 11. The cable separator of claim 9, wherein at least one of the anti-drip additive and fire retardant filler is selected from the group consisting of polytetrafluoroethylene and styrene-acrylonitrile treated polytetrafluoroethylene. 12. The cable separator of claim 1, wherein the body includes one or more projections extending in an outward direction. 13. The cable separator of claim 12, wherein the body is a cross-web or is a substantially flat member. 14. The cable separator of claim 1 exhibits a Limiting Oxygen Index (LOI) of about 30% or more. 15. A communication cable having a cable separator of claim 1. 16. The communication cable of claim 15 passes the flame test according to NFPA 262. 17. The communications cable of claim 15, further comprising a plurality of conductors and a jacket layer; and
wherein the jacket layer surrounds the plurality of conductors and the separator along the length of the cable. 18. A cable separator comprising a body, wherein the body comprises a polycarbonate polymer, a polycarbonate-siloxane copolymer and a metal sulfonate, and wherein the body is at least partially foamed. 19. A cable separator comprising a body, wherein the body comprises a polycarbonate polymer, a polycarbonate-siloxane copolymer and one or more of a halogenated flame retardant and an anti-drip additive, and wherein the body is at least partially foamed. 20. The cable separator of claim 19, wherein the halogenated flame retardant is a brominated polycarbonate and the anti-drip additive comprises a styrene-acrylonitrile treated polytetrafluoroethylene. | 2,800 |
11,802 | 11,802 | 13,859,286 | 2,839 | Circuits and methods for converting a current to an output voltage are disclosed herein. An embodiment of the circuit includes a first switch connected between a source of current and a first node and a second switch connected between the first node and a common voltage. The circuit also includes a first controller for controlling the state of the first switch and a second controller for controlling the state of the second switch. A capacitor is coupled to the first node; the voltage on the capacitor is the output voltage. When the second switch is open, the capacitor charges, and when the second switch is closed, the capacitor does not charge. The current flows through the primary inductance of a transformer. | 1. A circuit for converting a current to an output voltage, the circuit comprising:
a first switch connected between a source of current and a first node; a second switch connected between the first node and a common voltage; a first controller for controlling the state of the first switch; a second controller for controlling the state of the second switch; and a capacitor coupled to the first node, the voltage on the capacitor being the output voltage; wherein when the second switch is open, the capacitor charges, and wherein when the second switch is closed, the capacitor does not charge; and wherein the current flows through the primary inductance of a transformer. 2. The circuit of claim 1, wherein the first switch is a FET. 3. The circuit of claim 1, wherein the second switch is a FET. 4. The circuit of claim 1, wherein the first controller comprises a current source. 5. The circuit of claim 1, wherein the transformer is a component in a flyback converter. 6. The circuit of claim 1, wherein a diode is connected between the first node and the capacitor. 7. The circuit of claim 1, wherein a switch is connected between the first node and the capacitor. 8. The circuit of claim 1, wherein the source of current comprises the transformer connected in series with a voltage source. 9. The circuit of claim 1, wherein the circuit comprises:
a first mode of operation wherein the current through the first switch increases and passes through the second switch; a second mode of operation wherein second switch is open and the current passing through the first switch and charges the capacitor; and a third mode of operation wherein the current through first switch decreases. 10. The circuit of claim 9, wherein the current flow during the first mode of operation is controlled by the first controller. 11. The circuit of claim 9, wherein the current flow during the third mode of operation is controlled by the second controller. 12. A circuit for converting a current to an output voltage, the circuit comprising:
a source of current comprising a side of a transformer, wherein the current charges the side of the transformer; a first FET connected between the source of current and a first node; a second FET connected between the first node and a ground node; a first controller connected to the gate of the first FET, the first controller regulating the current flow through the first FET; a second controller connected between the gate of the second FET and the ground node, the second controller regulating the current flow through the second FET; a capacitor coupled to the first node, the voltage on the capacitor being the output voltage; wherein when the second FET is off, the capacitor charges, and wherein when the second FET is on, the capacitor does not charge. 13. The circuit of claim 12, wherein the transformer is a component in a flyback converter. 14. The circuit of claim 12, wherein the first FET and the first controller control the slope of the drain voltage on the first FET during switching of the first FET. 15. The circuit of claim 12 wherein the first controller comprises a current source. 16. The circuit of claim 12 and further comprising a switch connected between the current source the gate of the first FET. 17. The circuit of claim 12, wherein the circuit comprises:
a first mode of operation wherein the current through the first FET increases and passes through the second FET; a second mode of operation wherein second FET is off and the current passing through the first FET charges the capacitor; and a third mode of operation wherein the current in first FET decreases. 18. The circuit of claim 17, wherein the current flow during the first mode of operation is controlled by the first current controller. 19. The circuit of claim 17, wherein the current flow during the third mode of operation is controlled by the second controller. 20. A method for generating an output voltage from a current, the current used to magnetize a winding of a transformer used in a flyback converter, the method comprising:
operating a circuit in a first mode wherein the current passes through a first switch and a second switch connected in series, the switches being connected at a node, and wherein the current increases during the first mode; operating the circuit in a second mode, wherein the second switch is turned off and current flows through the first switch and into a capacitor, the voltage on the capacitor being the output voltage; and operating the circuit in a third mode, wherein the current is regulated by the first switch, and wherein the current decreases during the third mode. 21. A circuit for converting a current to an output voltage, the circuit comprising:
a source of current comprising a side of a transformer used in a flyback converter circuit, wherein the current charges the side of the transformer; a first FET connected between the source of current and a first node; a second FET connected between the first node and a ground node; a first controller connected to the gate of the first FET, the first controller regulating the current flow through the first FET by way of at least one current source; a second controller connected between the gate of the second FET and the ground node, the second controller regulating the current flow through the second FET; a capacitor coupled to the first node, the voltage on the capacitor being the output voltage; a switch located between the first node and the capacitor, the switch being controlled by a controller; wherein when the second FET is off, the capacitor charges, and wherein when the second FET is on, the capacitor does not charge; and wherein the circuit has:
a first mode of operation wherein the current through the first FET increases and passes through the second FET;
a second mode of operation wherein second FET is off and the current passing through the first FET charges the capacitor; and
a third mode of operation wherein the current in first FET decreases. | Circuits and methods for converting a current to an output voltage are disclosed herein. An embodiment of the circuit includes a first switch connected between a source of current and a first node and a second switch connected between the first node and a common voltage. The circuit also includes a first controller for controlling the state of the first switch and a second controller for controlling the state of the second switch. A capacitor is coupled to the first node; the voltage on the capacitor is the output voltage. When the second switch is open, the capacitor charges, and when the second switch is closed, the capacitor does not charge. The current flows through the primary inductance of a transformer.1. A circuit for converting a current to an output voltage, the circuit comprising:
a first switch connected between a source of current and a first node; a second switch connected between the first node and a common voltage; a first controller for controlling the state of the first switch; a second controller for controlling the state of the second switch; and a capacitor coupled to the first node, the voltage on the capacitor being the output voltage; wherein when the second switch is open, the capacitor charges, and wherein when the second switch is closed, the capacitor does not charge; and wherein the current flows through the primary inductance of a transformer. 2. The circuit of claim 1, wherein the first switch is a FET. 3. The circuit of claim 1, wherein the second switch is a FET. 4. The circuit of claim 1, wherein the first controller comprises a current source. 5. The circuit of claim 1, wherein the transformer is a component in a flyback converter. 6. The circuit of claim 1, wherein a diode is connected between the first node and the capacitor. 7. The circuit of claim 1, wherein a switch is connected between the first node and the capacitor. 8. The circuit of claim 1, wherein the source of current comprises the transformer connected in series with a voltage source. 9. The circuit of claim 1, wherein the circuit comprises:
a first mode of operation wherein the current through the first switch increases and passes through the second switch; a second mode of operation wherein second switch is open and the current passing through the first switch and charges the capacitor; and a third mode of operation wherein the current through first switch decreases. 10. The circuit of claim 9, wherein the current flow during the first mode of operation is controlled by the first controller. 11. The circuit of claim 9, wherein the current flow during the third mode of operation is controlled by the second controller. 12. A circuit for converting a current to an output voltage, the circuit comprising:
a source of current comprising a side of a transformer, wherein the current charges the side of the transformer; a first FET connected between the source of current and a first node; a second FET connected between the first node and a ground node; a first controller connected to the gate of the first FET, the first controller regulating the current flow through the first FET; a second controller connected between the gate of the second FET and the ground node, the second controller regulating the current flow through the second FET; a capacitor coupled to the first node, the voltage on the capacitor being the output voltage; wherein when the second FET is off, the capacitor charges, and wherein when the second FET is on, the capacitor does not charge. 13. The circuit of claim 12, wherein the transformer is a component in a flyback converter. 14. The circuit of claim 12, wherein the first FET and the first controller control the slope of the drain voltage on the first FET during switching of the first FET. 15. The circuit of claim 12 wherein the first controller comprises a current source. 16. The circuit of claim 12 and further comprising a switch connected between the current source the gate of the first FET. 17. The circuit of claim 12, wherein the circuit comprises:
a first mode of operation wherein the current through the first FET increases and passes through the second FET; a second mode of operation wherein second FET is off and the current passing through the first FET charges the capacitor; and a third mode of operation wherein the current in first FET decreases. 18. The circuit of claim 17, wherein the current flow during the first mode of operation is controlled by the first current controller. 19. The circuit of claim 17, wherein the current flow during the third mode of operation is controlled by the second controller. 20. A method for generating an output voltage from a current, the current used to magnetize a winding of a transformer used in a flyback converter, the method comprising:
operating a circuit in a first mode wherein the current passes through a first switch and a second switch connected in series, the switches being connected at a node, and wherein the current increases during the first mode; operating the circuit in a second mode, wherein the second switch is turned off and current flows through the first switch and into a capacitor, the voltage on the capacitor being the output voltage; and operating the circuit in a third mode, wherein the current is regulated by the first switch, and wherein the current decreases during the third mode. 21. A circuit for converting a current to an output voltage, the circuit comprising:
a source of current comprising a side of a transformer used in a flyback converter circuit, wherein the current charges the side of the transformer; a first FET connected between the source of current and a first node; a second FET connected between the first node and a ground node; a first controller connected to the gate of the first FET, the first controller regulating the current flow through the first FET by way of at least one current source; a second controller connected between the gate of the second FET and the ground node, the second controller regulating the current flow through the second FET; a capacitor coupled to the first node, the voltage on the capacitor being the output voltage; a switch located between the first node and the capacitor, the switch being controlled by a controller; wherein when the second FET is off, the capacitor charges, and wherein when the second FET is on, the capacitor does not charge; and wherein the circuit has:
a first mode of operation wherein the current through the first FET increases and passes through the second FET;
a second mode of operation wherein second FET is off and the current passing through the first FET charges the capacitor; and
a third mode of operation wherein the current in first FET decreases. | 2,800 |
11,803 | 11,803 | 14,686,565 | 2,836 | The present invention relates to an alternative power generation system, comprising a portable electricity harvesting device for generating electrical power, a power unit coupled to said portable electricity harvesting device including circuitry for processing electrical power generated by said portable electricity harvesting device and storing said electrical power in a battery within said power unit, and a plurality of distribution components in electrical communication with said power unit and a plurality of devices to be electrically powered. | 1. An alternative power generation system, comprising:
a portable electricity harvesting device for generating electrical power; a power unit coupled to said portable electricity harvesting device including circuitry for processing electrical power generated by said portable electricity harvesting device and storing said electrical power in a battery within said power unit; and a plurality of distribution components in electrical communication with said power unit and a plurality of devices to be electrically powered. 2. The alternative power generation system of claim 1, further comprising a carrying unit to house at least the harvesting device for storage or transportation. 3. The alternative power generation system of claim 1, further comprising a power skin. 4. The alternative power generation system of claim 1, wherein the power unit is connectable to a plurality of power units. 5. The alternative power generation system of claim 1, further comprising:
a layer of substrate; a first layer formed on the substrate and including battery electronics therein; a second layer formed on the first layer and including power electronics therein; and a third layer formed on the second layer and including materials for generating electricity. 6. The alternative power generation system of claim 5, wherein the first layer, second layer, and third layer are laminated. 7. The alternative power generation system of claim 5, wherein the first layer, second layer, and third layer are laminated with laminates that comprise layers of moisture resistant translucent film with electronic connection capabilities embedded in each layer. 8. The alternative power generation system of claim 5, wherein the first layer, second layer, and third layer are printed using conductive inks. 9. The alternative power generation system of claim 5, wherein the first layer, second layer, and third layer have interstitial wiring in between. 10. The alternative power generation system of claim 1, further comprising one or more wireless devices. 11. The alternative power generation system of claim 10, wherein the one or more wireless devices includes Bluetooth technology. 12. The alternative power generation system of claim 10, wherein the one or more wireless devices includes Zigbee technology. 13. The alternative power generation system of claim 10, wherein the one or more wireless devices includes devices capable of wirelessly transmitting power. 14. The alternative power generation system of claim 1, wherein the alternative power generation system is in electrical communication with wireless devices for home automation. 15. The alternative power generation system of claim 1, further comprising a monitoring system. 16. The alternative power generation system of claim 1, further comprising one or more sensors, one or more transducers, and one or more piezoelectric devices. 17. The alternative power generation system of claim 16, wherein the transducers harvest at least one of steady state vibration, scavenged vibration, linear motion, waste energy, and electromagnetic fields. 18. The alternative power generation system of claim 1, wherein the portable electricity harvesting device harvests electricity from a human being. 19. The alternative power generation system of claim 1, wherein the portable electricity harvesting device is in electrical communication with a wireless sensor network. 20. The alternative power generation system of claim 1, wherein the portable electricity harvesting device can harvest electricity from one or more systems of the human body. 21. The alternative power generation system of claim 20, wherein the portable electricity harvesting device includes one or more sensors, transducers, or piezoelectric devices. 22. The alternative power generation system of claim 1, wherein the portable electricity harvesting device harvests electricity from oscillations and/or vibrations of objects. | The present invention relates to an alternative power generation system, comprising a portable electricity harvesting device for generating electrical power, a power unit coupled to said portable electricity harvesting device including circuitry for processing electrical power generated by said portable electricity harvesting device and storing said electrical power in a battery within said power unit, and a plurality of distribution components in electrical communication with said power unit and a plurality of devices to be electrically powered.1. An alternative power generation system, comprising:
a portable electricity harvesting device for generating electrical power; a power unit coupled to said portable electricity harvesting device including circuitry for processing electrical power generated by said portable electricity harvesting device and storing said electrical power in a battery within said power unit; and a plurality of distribution components in electrical communication with said power unit and a plurality of devices to be electrically powered. 2. The alternative power generation system of claim 1, further comprising a carrying unit to house at least the harvesting device for storage or transportation. 3. The alternative power generation system of claim 1, further comprising a power skin. 4. The alternative power generation system of claim 1, wherein the power unit is connectable to a plurality of power units. 5. The alternative power generation system of claim 1, further comprising:
a layer of substrate; a first layer formed on the substrate and including battery electronics therein; a second layer formed on the first layer and including power electronics therein; and a third layer formed on the second layer and including materials for generating electricity. 6. The alternative power generation system of claim 5, wherein the first layer, second layer, and third layer are laminated. 7. The alternative power generation system of claim 5, wherein the first layer, second layer, and third layer are laminated with laminates that comprise layers of moisture resistant translucent film with electronic connection capabilities embedded in each layer. 8. The alternative power generation system of claim 5, wherein the first layer, second layer, and third layer are printed using conductive inks. 9. The alternative power generation system of claim 5, wherein the first layer, second layer, and third layer have interstitial wiring in between. 10. The alternative power generation system of claim 1, further comprising one or more wireless devices. 11. The alternative power generation system of claim 10, wherein the one or more wireless devices includes Bluetooth technology. 12. The alternative power generation system of claim 10, wherein the one or more wireless devices includes Zigbee technology. 13. The alternative power generation system of claim 10, wherein the one or more wireless devices includes devices capable of wirelessly transmitting power. 14. The alternative power generation system of claim 1, wherein the alternative power generation system is in electrical communication with wireless devices for home automation. 15. The alternative power generation system of claim 1, further comprising a monitoring system. 16. The alternative power generation system of claim 1, further comprising one or more sensors, one or more transducers, and one or more piezoelectric devices. 17. The alternative power generation system of claim 16, wherein the transducers harvest at least one of steady state vibration, scavenged vibration, linear motion, waste energy, and electromagnetic fields. 18. The alternative power generation system of claim 1, wherein the portable electricity harvesting device harvests electricity from a human being. 19. The alternative power generation system of claim 1, wherein the portable electricity harvesting device is in electrical communication with a wireless sensor network. 20. The alternative power generation system of claim 1, wherein the portable electricity harvesting device can harvest electricity from one or more systems of the human body. 21. The alternative power generation system of claim 20, wherein the portable electricity harvesting device includes one or more sensors, transducers, or piezoelectric devices. 22. The alternative power generation system of claim 1, wherein the portable electricity harvesting device harvests electricity from oscillations and/or vibrations of objects. | 2,800 |
11,804 | 11,804 | 15,810,275 | 2,848 | An electronic component includes a first external electrode disposed on a first end surface and a second external electrode disposed on a second end surface. The first external electrode includes a first conductive layer including ceramic particles. The second external electrode includes a second conductive layer including ceramic particles. An end portion of a first internal electrode is located inside the first conductive layer. The electronic component includes little or no cracks and has a low equivalent series resistance (ESR). | 1. An electronic component comprising:
an electronic component main body including ceramic particles and including a first principal surface and a second principal surface extending along a length direction and a width direction, a first side surface and a second side surface extending along the length direction and a laminating direction, and a first end surface and a second end surface extending along the width direction and the laminating direction; a first internal electrode disposed within the electronic component main body; a second internal electrode disposed within the electronic component main body and opposed to the first internal electrode in the laminating direction with a ceramic layer interposed therebetween; a first auxiliary electrode opposed to the first internal electrode in the length direction and disposed at a distance from the first internal electrode; a second auxiliary electrode opposed to the second internal electrode in the length direction and disposed at a distance from the second internal electrode; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface; the first external electrode including a first conductive layer including ceramic particles; the second external electrode including a second conductive layer including ceramic particles; and an end portion of the first internal electrode is located inside the first conductive layer. 2. The electronic component according to claim 1, wherein an end portion of the second auxiliary electrode is located inside the first conductive layer. 3. The electronic component according to claim 1, wherein an end portion of the second internal electrode is located inside the second conductive layer. 4. The electronic component according to claim 1, wherein an end portion of the first auxiliary electrode is located inside the second conductive layer. 5. The electronic component according to claim 1, wherein
the first external electrode includes a third conductive layer disposed on the first conductive layer; and a content of the ceramic particles in the first conductive layer is higher than a content of the ceramic particles in the third conductive layer. 6. The electronic component according to claim 5, wherein
the second external electrode includes a fourth conductive layer disposed on the second conductive layer; and a content of the ceramic particles in the second conductive layer is higher than a content of the ceramic particles in the fourth conductive layer. 7. The electronic component according to claim 5, wherein the third conductive layer is spaced away from the electronic component main body by the first conductive layer. 8. The electronic component according to claim 6, wherein the fourth conductive layer is spaced away from the electronic component main body by the second conductive layer. 9. The electronic component according to claim 1, wherein a portion of the first internal electrode which is located inside the first conductive layer has a curved shape when viewing a cross-section along the length direction and the laminating direction from the width direction. 10. The electronic component according to claim 2, wherein a portion of the first auxiliary electrode which is located inside the second conductive layer has a curved shape. 11. The electronic component according to claim 3, wherein a portion of the second internal electrode which is located inside the second conductive layer has a curved shape when viewing a cross-section along the length direction and the laminating direction from the width direction. 12. The electronic component according to claim 4, wherein a portion of the second auxiliary electrode which is located inside the first conductive layer has a curved shape. 13. A method for manufacturing an electronic component including an electronic component main body including a first principal surface and a second principal surface extending along a length direction and a width direction, a first side surface and a second side surface extending along the length direction and a laminating direction, and a first end surface and a second end surface extending along the width direction and the laminating direction, a first internal electrode disposed within the electronic component main body, a second internal electrode disposed within the electronic component main body and opposed to the first internal electrode in the laminating direction with a ceramic layer interposed therebetween, a first auxiliary electrode opposed to the first internal electrode in the length direction and disposed at a distance from the first internal electrode, a second auxiliary electrode opposed to the second internal electrode in the length direction and disposed at a distance from the second internal electrode, a first external electrode disposed on the first end surface, and a second external electrode disposed on the second end surface, the first external electrode including a first conductive layer including ceramic particles, the second external electrode including a second conductive layer including ceramic particles, and an end portion of the first internal electrode is located inside the first conductive layer, the method for manufacturing an electronic component comprising:
(A) forming a first green sheet including:
a first ceramic paste layer to form the ceramic layer;
a first conductive paste layer to form the first conductive layer; and
a second conductive paste layer to form the second conductive layer;
(B) forming on the first green sheet:
a third conductive paste layer to form the first internal electrode, which is positioned above the first ceramic paste layer and above a portion of the first conductive paste layer excluding an outer end portion of the first conductive paste layer in the length direction; and
a fourth conductive paste layer to form the first auxiliary electrode, which is positioned above the first ceramic paste layer and above a portion of the second conductive paste layer excluding an outer end portion of the second conductive paste layer in the length direction;
(C) forming a second green sheet including:
a fifth conductive paste layer to form the first conductive layer, which is positioned above the first conductive paste layer;
a second ceramic paste layer to form the ceramic layer, which is positioned above the first ceramic paste layer; and
a sixth conductive paste layer to form the second conductive layer, which is positioned above the second conductive paste layer;
(D) forming on the second green sheet:
a seventh conductive paste layer to form the second internal electrode, which is positioned above the second ceramic paste layer and above a portion of the sixth conductive paste layer excluding an outer end portion of the sixth conductive paste layer in the length direction; and
an eighth conductive paste layer to form the second auxiliary electrode, which is positioned above the second ceramic paste layer and above a portion of the fifth conductive paste layer excluding an outer end portion of the fifth conductive paste layer in the length direction; and
(E) forming a third green sheet including:
a ninth conductive paste layer to form the first conductive layer, which is positioned above the fifth conductive paste layer;
a third ceramic paste layer to form the ceramic layer, which is positioned above the second ceramic paste layer; and
a tenth conductive paste layer to form the second conductive layer, which is positioned above the sixth conductive paste layer. 14. The method for manufacturing an electronic component according to claim 13, wherein an end portion of the second auxiliary electrode is located inside the first conductive layer. 15. The method for manufacturing an electronic component according to claim 14, wherein the ceramic paste layer and the conductive paste layer are formed by an ink-jet method. 16. The electronic component according to claim 5, wherein
the first external electrode further includes a fifth conductive layer disposed on the first conductive layer and the third conductive layer; and the fifth conductive layer extends from above the first end surface on which the first conductive layer and the third conductive layer are located to the first principal surface and the second principal surface and the first side surface and the second side surface. 17. The electronic component according to claim 6, wherein
the second external electrode further includes a sixth conductive layer disposed on the second conductive layer and the fourth conductive layer; and the sixth conductive layer extends from above the second end surface on which the second conductive layer and the fourth conductive layer are located to the first principal surface and the second principal surface and the first side surface and the second side surface. 18. The electronic component according to claim 6, wherein
the first external electrode includes only the first conductive layer including the ceramic particles; the second external electrode includes only the second conductive layer including ceramic particles; and plating layers are provided over the first external electrode and the second external electrode. 19. The method for manufacturing an electronic component according to claim 13, wherein a portion of the first auxiliary electrode which is located inside the second conductive layer is formed with a curved shape. 20. The method for manufacturing an electronic component according to claim 13, wherein a portion of the second auxiliary electrode which is located inside the first conductive layer is formed with a curved shape. | An electronic component includes a first external electrode disposed on a first end surface and a second external electrode disposed on a second end surface. The first external electrode includes a first conductive layer including ceramic particles. The second external electrode includes a second conductive layer including ceramic particles. An end portion of a first internal electrode is located inside the first conductive layer. The electronic component includes little or no cracks and has a low equivalent series resistance (ESR).1. An electronic component comprising:
an electronic component main body including ceramic particles and including a first principal surface and a second principal surface extending along a length direction and a width direction, a first side surface and a second side surface extending along the length direction and a laminating direction, and a first end surface and a second end surface extending along the width direction and the laminating direction; a first internal electrode disposed within the electronic component main body; a second internal electrode disposed within the electronic component main body and opposed to the first internal electrode in the laminating direction with a ceramic layer interposed therebetween; a first auxiliary electrode opposed to the first internal electrode in the length direction and disposed at a distance from the first internal electrode; a second auxiliary electrode opposed to the second internal electrode in the length direction and disposed at a distance from the second internal electrode; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface; the first external electrode including a first conductive layer including ceramic particles; the second external electrode including a second conductive layer including ceramic particles; and an end portion of the first internal electrode is located inside the first conductive layer. 2. The electronic component according to claim 1, wherein an end portion of the second auxiliary electrode is located inside the first conductive layer. 3. The electronic component according to claim 1, wherein an end portion of the second internal electrode is located inside the second conductive layer. 4. The electronic component according to claim 1, wherein an end portion of the first auxiliary electrode is located inside the second conductive layer. 5. The electronic component according to claim 1, wherein
the first external electrode includes a third conductive layer disposed on the first conductive layer; and a content of the ceramic particles in the first conductive layer is higher than a content of the ceramic particles in the third conductive layer. 6. The electronic component according to claim 5, wherein
the second external electrode includes a fourth conductive layer disposed on the second conductive layer; and a content of the ceramic particles in the second conductive layer is higher than a content of the ceramic particles in the fourth conductive layer. 7. The electronic component according to claim 5, wherein the third conductive layer is spaced away from the electronic component main body by the first conductive layer. 8. The electronic component according to claim 6, wherein the fourth conductive layer is spaced away from the electronic component main body by the second conductive layer. 9. The electronic component according to claim 1, wherein a portion of the first internal electrode which is located inside the first conductive layer has a curved shape when viewing a cross-section along the length direction and the laminating direction from the width direction. 10. The electronic component according to claim 2, wherein a portion of the first auxiliary electrode which is located inside the second conductive layer has a curved shape. 11. The electronic component according to claim 3, wherein a portion of the second internal electrode which is located inside the second conductive layer has a curved shape when viewing a cross-section along the length direction and the laminating direction from the width direction. 12. The electronic component according to claim 4, wherein a portion of the second auxiliary electrode which is located inside the first conductive layer has a curved shape. 13. A method for manufacturing an electronic component including an electronic component main body including a first principal surface and a second principal surface extending along a length direction and a width direction, a first side surface and a second side surface extending along the length direction and a laminating direction, and a first end surface and a second end surface extending along the width direction and the laminating direction, a first internal electrode disposed within the electronic component main body, a second internal electrode disposed within the electronic component main body and opposed to the first internal electrode in the laminating direction with a ceramic layer interposed therebetween, a first auxiliary electrode opposed to the first internal electrode in the length direction and disposed at a distance from the first internal electrode, a second auxiliary electrode opposed to the second internal electrode in the length direction and disposed at a distance from the second internal electrode, a first external electrode disposed on the first end surface, and a second external electrode disposed on the second end surface, the first external electrode including a first conductive layer including ceramic particles, the second external electrode including a second conductive layer including ceramic particles, and an end portion of the first internal electrode is located inside the first conductive layer, the method for manufacturing an electronic component comprising:
(A) forming a first green sheet including:
a first ceramic paste layer to form the ceramic layer;
a first conductive paste layer to form the first conductive layer; and
a second conductive paste layer to form the second conductive layer;
(B) forming on the first green sheet:
a third conductive paste layer to form the first internal electrode, which is positioned above the first ceramic paste layer and above a portion of the first conductive paste layer excluding an outer end portion of the first conductive paste layer in the length direction; and
a fourth conductive paste layer to form the first auxiliary electrode, which is positioned above the first ceramic paste layer and above a portion of the second conductive paste layer excluding an outer end portion of the second conductive paste layer in the length direction;
(C) forming a second green sheet including:
a fifth conductive paste layer to form the first conductive layer, which is positioned above the first conductive paste layer;
a second ceramic paste layer to form the ceramic layer, which is positioned above the first ceramic paste layer; and
a sixth conductive paste layer to form the second conductive layer, which is positioned above the second conductive paste layer;
(D) forming on the second green sheet:
a seventh conductive paste layer to form the second internal electrode, which is positioned above the second ceramic paste layer and above a portion of the sixth conductive paste layer excluding an outer end portion of the sixth conductive paste layer in the length direction; and
an eighth conductive paste layer to form the second auxiliary electrode, which is positioned above the second ceramic paste layer and above a portion of the fifth conductive paste layer excluding an outer end portion of the fifth conductive paste layer in the length direction; and
(E) forming a third green sheet including:
a ninth conductive paste layer to form the first conductive layer, which is positioned above the fifth conductive paste layer;
a third ceramic paste layer to form the ceramic layer, which is positioned above the second ceramic paste layer; and
a tenth conductive paste layer to form the second conductive layer, which is positioned above the sixth conductive paste layer. 14. The method for manufacturing an electronic component according to claim 13, wherein an end portion of the second auxiliary electrode is located inside the first conductive layer. 15. The method for manufacturing an electronic component according to claim 14, wherein the ceramic paste layer and the conductive paste layer are formed by an ink-jet method. 16. The electronic component according to claim 5, wherein
the first external electrode further includes a fifth conductive layer disposed on the first conductive layer and the third conductive layer; and the fifth conductive layer extends from above the first end surface on which the first conductive layer and the third conductive layer are located to the first principal surface and the second principal surface and the first side surface and the second side surface. 17. The electronic component according to claim 6, wherein
the second external electrode further includes a sixth conductive layer disposed on the second conductive layer and the fourth conductive layer; and the sixth conductive layer extends from above the second end surface on which the second conductive layer and the fourth conductive layer are located to the first principal surface and the second principal surface and the first side surface and the second side surface. 18. The electronic component according to claim 6, wherein
the first external electrode includes only the first conductive layer including the ceramic particles; the second external electrode includes only the second conductive layer including ceramic particles; and plating layers are provided over the first external electrode and the second external electrode. 19. The method for manufacturing an electronic component according to claim 13, wherein a portion of the first auxiliary electrode which is located inside the second conductive layer is formed with a curved shape. 20. The method for manufacturing an electronic component according to claim 13, wherein a portion of the second auxiliary electrode which is located inside the first conductive layer is formed with a curved shape. | 2,800 |
11,805 | 11,805 | 15,868,557 | 2,842 | A capacitively-driven tunable coupler includes a coupling capacitor connecting an open end of a quantum object (i.e., an end of the object that cannot have a DC path to a low-voltage rail, such as a ground node, without breaking the functionality of the object) to an RF SQUID having a Josephson element capable of providing variable inductance and therefore variable coupling to another quantum object. | 1. A superconducting capacitively-driven tunable coupler system comprising:
first and second quantum objects each having a ground end required to be connected to a DC path to a low-voltage rail and an open end required not to be connected to a DC path to the low-voltage rail; a coupler comprising:
a first coupling capacitor connected between the open end of the first quantum object and a first connecting node;
a radio-frequency superconducting quantum interference device (RF SQUID) connected between the first connecting node and a second connecting node, the RF SQUID comprising a Josephson element connected between the first connecting node and the second connecting node, wherein the entirety of a path between the first coupling capacitor and the Josephson element is electrically short; and
at least one flux injection element configured to bias the Josephson element to variably weaken the strength of coupling between the first and second quantum objects,
wherein the objects are coupled together to pass signals between them in the absence of injected flux. 2. The system of claim 1, wherein the ground end of the second quantum object is coupled to the second connecting node either galvanically or through a flux transformer. 3. The system of claim 1, further comprising a coupler controller configured to control the setting of the coupler between coupled and uncoupled states by adjusting the amount of the injected flux and thereby varying the inductance of the Josephson element. 4. The system of claim 3, wherein the coupler controller controls an amount and polarity of current through at least one flux bias control line inductively coupled to the RF SQUID. 5. The system of claim 1, wherein the RF SQUID further comprises a first inductor connected between the first connecting node and the low-voltage rail and a second inductor between the second connecting node and the low-voltage rail. 6. The system of claim 5, wherein the Josephson element consists of exactly one Josephson junction. 7. The system of claim 5, wherein the at least one flux injection element is a flux bias line that is transformer-coupled to at least one of the first and second inductors. 8. The system of claim 5, wherein the Josephson element comprises a compound Josephson junction comprising two Josephson junctions arranged in parallel. 9. The system of claim 8, wherein the at least one flux injection element is a flux bias line that is transformer-coupled to an inductance in the compound Josephson junction. 10. The system of claim 1, wherein the coupler further comprises a second coupling capacitor connected between the second connecting node and the open end of the second quantum object. 11. A superconducting capacitively-driven tunable coupler system comprising:
first and second quantum objects each having a ground end required to be connected to a DC path to a low-voltage rail and an open end required not to be connected to a DC path to the low-voltage rail, wherein the ground end of the second quantum object is connected to a second connecting node; a coupling capacitor connected between the open end of the first quantum object and a first connecting node; a first inductor connected between the first connecting node and the low-voltage rail; a Josephson element connected between the first connecting node and the second connecting node; and a second inductor connected between the second connecting node and the low-voltage rail. 12. The system of claim 11, wherein the Josephson element is a single Josephson junction. 13. The system of claim 12, further comprising at least one flux bias line transformer-coupled to at least one of the first and second inductor to bias the Josephson element to variably weaken the strength of coupling between the first and second quantum objects. 14. The system of claim 11, wherein the Josephson element is a compound Josephson junction comprising two Josephson junctions arranged in parallel. 15. The system of claim 14, further comprising at least one flux bias line transformer-coupled to the compound Josephson junction to bias the compound Josephson junction to variably weaken the strength of coupling between the first and second quantum objects. 16. A superconducting capacitively-driven tunable coupler system comprising:
first and second quantum objects each having a ground end required to be connected to a DC path to a low-voltage rail and an open end required not to be connected to a DC path to the low-voltage rail; a first coupling capacitor connected between the open end of the first quantum object and a first connecting node; a first inductor connected between the first connecting node and the low-voltage rail; a Josephson element connected between the first connecting node and a second connecting node; a second inductor connected between the second connecting node and the low-voltage rail; and a second coupling capacitor connected between the second connecting node and the open end of the second quantum object. 17. The system of claim 16, wherein the Josephson element is a single Josephson junction. 18. The system of claim 17, further comprising at least one flux bias line transformer-coupled to at least one of the first and second inductor to bias the Josephson element to variably weaken the strength of coupling between the first and second quantum objects. 19. The system of claim 16, wherein the Josephson element is a compound Josephson junction comprising two Josephson junctions arranged in parallel. 20. The system of claim 19, further comprising at least one flux bias line transformer-coupled to the compound Josephson junction to bias the compound Josephson junction to variably weaken the strength of coupling between the first and second quantum objects. | A capacitively-driven tunable coupler includes a coupling capacitor connecting an open end of a quantum object (i.e., an end of the object that cannot have a DC path to a low-voltage rail, such as a ground node, without breaking the functionality of the object) to an RF SQUID having a Josephson element capable of providing variable inductance and therefore variable coupling to another quantum object.1. A superconducting capacitively-driven tunable coupler system comprising:
first and second quantum objects each having a ground end required to be connected to a DC path to a low-voltage rail and an open end required not to be connected to a DC path to the low-voltage rail; a coupler comprising:
a first coupling capacitor connected between the open end of the first quantum object and a first connecting node;
a radio-frequency superconducting quantum interference device (RF SQUID) connected between the first connecting node and a second connecting node, the RF SQUID comprising a Josephson element connected between the first connecting node and the second connecting node, wherein the entirety of a path between the first coupling capacitor and the Josephson element is electrically short; and
at least one flux injection element configured to bias the Josephson element to variably weaken the strength of coupling between the first and second quantum objects,
wherein the objects are coupled together to pass signals between them in the absence of injected flux. 2. The system of claim 1, wherein the ground end of the second quantum object is coupled to the second connecting node either galvanically or through a flux transformer. 3. The system of claim 1, further comprising a coupler controller configured to control the setting of the coupler between coupled and uncoupled states by adjusting the amount of the injected flux and thereby varying the inductance of the Josephson element. 4. The system of claim 3, wherein the coupler controller controls an amount and polarity of current through at least one flux bias control line inductively coupled to the RF SQUID. 5. The system of claim 1, wherein the RF SQUID further comprises a first inductor connected between the first connecting node and the low-voltage rail and a second inductor between the second connecting node and the low-voltage rail. 6. The system of claim 5, wherein the Josephson element consists of exactly one Josephson junction. 7. The system of claim 5, wherein the at least one flux injection element is a flux bias line that is transformer-coupled to at least one of the first and second inductors. 8. The system of claim 5, wherein the Josephson element comprises a compound Josephson junction comprising two Josephson junctions arranged in parallel. 9. The system of claim 8, wherein the at least one flux injection element is a flux bias line that is transformer-coupled to an inductance in the compound Josephson junction. 10. The system of claim 1, wherein the coupler further comprises a second coupling capacitor connected between the second connecting node and the open end of the second quantum object. 11. A superconducting capacitively-driven tunable coupler system comprising:
first and second quantum objects each having a ground end required to be connected to a DC path to a low-voltage rail and an open end required not to be connected to a DC path to the low-voltage rail, wherein the ground end of the second quantum object is connected to a second connecting node; a coupling capacitor connected between the open end of the first quantum object and a first connecting node; a first inductor connected between the first connecting node and the low-voltage rail; a Josephson element connected between the first connecting node and the second connecting node; and a second inductor connected between the second connecting node and the low-voltage rail. 12. The system of claim 11, wherein the Josephson element is a single Josephson junction. 13. The system of claim 12, further comprising at least one flux bias line transformer-coupled to at least one of the first and second inductor to bias the Josephson element to variably weaken the strength of coupling between the first and second quantum objects. 14. The system of claim 11, wherein the Josephson element is a compound Josephson junction comprising two Josephson junctions arranged in parallel. 15. The system of claim 14, further comprising at least one flux bias line transformer-coupled to the compound Josephson junction to bias the compound Josephson junction to variably weaken the strength of coupling between the first and second quantum objects. 16. A superconducting capacitively-driven tunable coupler system comprising:
first and second quantum objects each having a ground end required to be connected to a DC path to a low-voltage rail and an open end required not to be connected to a DC path to the low-voltage rail; a first coupling capacitor connected between the open end of the first quantum object and a first connecting node; a first inductor connected between the first connecting node and the low-voltage rail; a Josephson element connected between the first connecting node and a second connecting node; a second inductor connected between the second connecting node and the low-voltage rail; and a second coupling capacitor connected between the second connecting node and the open end of the second quantum object. 17. The system of claim 16, wherein the Josephson element is a single Josephson junction. 18. The system of claim 17, further comprising at least one flux bias line transformer-coupled to at least one of the first and second inductor to bias the Josephson element to variably weaken the strength of coupling between the first and second quantum objects. 19. The system of claim 16, wherein the Josephson element is a compound Josephson junction comprising two Josephson junctions arranged in parallel. 20. The system of claim 19, further comprising at least one flux bias line transformer-coupled to the compound Josephson junction to bias the compound Josephson junction to variably weaken the strength of coupling between the first and second quantum objects. | 2,800 |
11,806 | 11,806 | 15,622,570 | 2,875 | A planar light unit is provided that suppresses appearance of a bright line when viewed from the side of the emission surface of the light guide plate. The planar light unit includes a light source, and a light guide plate including an incident surface for receiving light emitted from the light source, an emission surface from which the light introduced through the incident surface is emitted, an opposing surface disposed so as to oppose the emission surface, and a side surface disposed along an outer periphery of the emission surface and the opposing surface. The emission surface has a non-rectangular outer shape, and at least a part of the side surface is formed as a diffusing surface. | 1. A planar light unit comprising:
a light source; and a light guide plate including an incident surface for receiving light emitted from the light source, an emission surface from which the light introduced through the incident surface is emitted, an opposing surface disposed so as to oppose the emission surface, and a side surface disposed along an outer periphery of the emission surface and the opposing surface, wherein the emission surface has a non-rectangular outer shape, and at least a part of the side surface is formed as a diffusing surface. 2. The planar light unit according to claim 1, wherein the light guide plate has a circular disk shape with a cutaway portion, and the incident surface is located in the cutaway portion. 3. The planar light unit according to claim 1, wherein the diffusing surface is formed by an electrical discharge processing method. 4. The planar light unit according to claim 1, wherein the diffusing surface is formed through a die machining process. 5. The planar light unit according to claim 1, wherein the diffusing surface is a prism surface or a concave-convex surface. 6. The planar light unit according to claim 4, wherein the diffusing surface is formed with the die having an inner surface subjected to an electrical discharge processing. 7. The planar light unit according to claim 1, wherein
the incident surface includes a first incident surface and a second incident surface located beside the first incident surface, the light source includes a first light source opposed to the first incident surface and a second light source opposed to the second incident surface, the first incident surface includes a first prism having a ridgeline oriented in a thickness direction of the light guide plate, the second incident surface includes a second prism having a ridgeline oriented in a thickness direction of the light guide plate, the first prism has an asymmetrical horizontal cross-sectional shape parallel to the emission surface, the cross-section including a first side located on the side of the side surface and a second side located on the side of the second incident surface, the second prism has an asymmetrical horizontal cross-sectional shape parallel to the emission surface, the cross-section including a third side located on the side of the first incident surface and a fourth side located on the side of the side surface, a first average value of angles defined between a first optical axis from the first light source to the first incident surface and the first side is larger than a second average value of angles defined between the first optical axis and the second side, and a fourth average value of angles defined between a second optical axis from the second light source to the second incident surface and the fourth side is larger than a third average value of angles defined between the second optical axis and the third side. 8. The planar light unit according to claim 7, wherein the first prism and the second prism each include, in the horizontal cross-section parallel to the emission surface, a plurality of scalene triangles each having an apex of right angle or an acute angle, and a plurality of scalene triangles each having an apex of an obtuse angle, the former scalene triangles and the latter scalene triangles being alternately aligned. 9. The planar light unit according to claim 7, wherein the first prism and the second prism each include a plurality of prisms, and a planar portion formed between the prisms. 10. The planar light unit according to claim 1, wherein at least one of the opposing surface and the emission surface includes a projection or a recess for emitting the light introduced through the incident surface to outside through the emission surface. 11. The planar light unit according to claim 1, wherein the emission surface has a non-rectangular outer shape including a curved portion. 12. The planar light unit according to claim 11, wherein a surface roughness of the diffusing surface formed on a portion of the side surface where the curved portion has larger curvature is higher than a surface roughness of the diffusing surface formed on a portion of the side surface where the curved portion has smaller curvature. 13. The planar light unit according to claim 1, wherein the emission surface has a non-rectangular outer shape solely composed of a plurality of linear portions. 14. The planar light unit according to claim 13, wherein a surface roughness of the diffusing surface formed on the side surface corresponding to a portion in a vicinity of a vertex defined by the linear portions is higher than a surface roughness of the diffusing surface formed on the side surface corresponding to a portion other than the vicinity of the vertex defined by the linear portions. | A planar light unit is provided that suppresses appearance of a bright line when viewed from the side of the emission surface of the light guide plate. The planar light unit includes a light source, and a light guide plate including an incident surface for receiving light emitted from the light source, an emission surface from which the light introduced through the incident surface is emitted, an opposing surface disposed so as to oppose the emission surface, and a side surface disposed along an outer periphery of the emission surface and the opposing surface. The emission surface has a non-rectangular outer shape, and at least a part of the side surface is formed as a diffusing surface.1. A planar light unit comprising:
a light source; and a light guide plate including an incident surface for receiving light emitted from the light source, an emission surface from which the light introduced through the incident surface is emitted, an opposing surface disposed so as to oppose the emission surface, and a side surface disposed along an outer periphery of the emission surface and the opposing surface, wherein the emission surface has a non-rectangular outer shape, and at least a part of the side surface is formed as a diffusing surface. 2. The planar light unit according to claim 1, wherein the light guide plate has a circular disk shape with a cutaway portion, and the incident surface is located in the cutaway portion. 3. The planar light unit according to claim 1, wherein the diffusing surface is formed by an electrical discharge processing method. 4. The planar light unit according to claim 1, wherein the diffusing surface is formed through a die machining process. 5. The planar light unit according to claim 1, wherein the diffusing surface is a prism surface or a concave-convex surface. 6. The planar light unit according to claim 4, wherein the diffusing surface is formed with the die having an inner surface subjected to an electrical discharge processing. 7. The planar light unit according to claim 1, wherein
the incident surface includes a first incident surface and a second incident surface located beside the first incident surface, the light source includes a first light source opposed to the first incident surface and a second light source opposed to the second incident surface, the first incident surface includes a first prism having a ridgeline oriented in a thickness direction of the light guide plate, the second incident surface includes a second prism having a ridgeline oriented in a thickness direction of the light guide plate, the first prism has an asymmetrical horizontal cross-sectional shape parallel to the emission surface, the cross-section including a first side located on the side of the side surface and a second side located on the side of the second incident surface, the second prism has an asymmetrical horizontal cross-sectional shape parallel to the emission surface, the cross-section including a third side located on the side of the first incident surface and a fourth side located on the side of the side surface, a first average value of angles defined between a first optical axis from the first light source to the first incident surface and the first side is larger than a second average value of angles defined between the first optical axis and the second side, and a fourth average value of angles defined between a second optical axis from the second light source to the second incident surface and the fourth side is larger than a third average value of angles defined between the second optical axis and the third side. 8. The planar light unit according to claim 7, wherein the first prism and the second prism each include, in the horizontal cross-section parallel to the emission surface, a plurality of scalene triangles each having an apex of right angle or an acute angle, and a plurality of scalene triangles each having an apex of an obtuse angle, the former scalene triangles and the latter scalene triangles being alternately aligned. 9. The planar light unit according to claim 7, wherein the first prism and the second prism each include a plurality of prisms, and a planar portion formed between the prisms. 10. The planar light unit according to claim 1, wherein at least one of the opposing surface and the emission surface includes a projection or a recess for emitting the light introduced through the incident surface to outside through the emission surface. 11. The planar light unit according to claim 1, wherein the emission surface has a non-rectangular outer shape including a curved portion. 12. The planar light unit according to claim 11, wherein a surface roughness of the diffusing surface formed on a portion of the side surface where the curved portion has larger curvature is higher than a surface roughness of the diffusing surface formed on a portion of the side surface where the curved portion has smaller curvature. 13. The planar light unit according to claim 1, wherein the emission surface has a non-rectangular outer shape solely composed of a plurality of linear portions. 14. The planar light unit according to claim 13, wherein a surface roughness of the diffusing surface formed on the side surface corresponding to a portion in a vicinity of a vertex defined by the linear portions is higher than a surface roughness of the diffusing surface formed on the side surface corresponding to a portion other than the vicinity of the vertex defined by the linear portions. | 2,800 |
11,807 | 11,807 | 15,401,258 | 2,819 | OLEDs containing a stacked hybrid architecture including a phosphorescent organic emissive unit and two fluorescent organic emissive units are disclosed. The stacked hybrid architecture includes a plurality of electrodes and a hybrid emissive stacked disposed between at least two of the electrodes. The stack contains at least three emissive units and at least two charge generation layers. At least one of the three emissive units is a phosphorescent organic emissive unit and at least two of the three emissive units are fluorescent organic emissive units. More specifically, the two fluorescent organic emissive units may be blue organic emissive units that emit light from the same or different color regions. | 1. A device comprising: a first electrode;
a second electrode; and a hybrid emissive stack disposed between the first electrode and the second electrode, the stack comprising at least three emissive units and at least two charge generation layers, wherein: a first emissive unit of the at least three emissive units is disposed over the first electrode; a first charge generation layer of the at least two charge generation layers is disposed over the first emissive unit; a second emissive unit of the at least three emissive units is disposed over the first charge generation layer; a second charge generation layer of the at least two charge generation layers is disposed over the second emissive unit; and a third emissive unit of the at least three emissive units is disposed over the second charge generation layer, wherein the second emissive unit is a phosphorescent organic emissive unit, and wherein the first emissive unit and the third emissive unit are fluorescent organic emissive units. 2. The device of claim 1, wherein the phosphorescent organic emissive unit is selected from the group consisting of: a red organic emissive unit, a green organic emissive unit, and a yellow organic emissive unit. 3. The device of claim 1, wherein the first emissive unit and the third emissive unit are blue organic emissive units. 4. The device of claim 3, wherein the two blue fluorescent organic emissive units emit light in different color regions. 5. The device of claim 3, wherein the two blue fluorescent organic emissive units emit light in the same color region. 6. The device of claim 1, wherein the phosphorescent organic emissive unit comprises a plurality of emissive materials, each having a different emission spectrum. 7. The device of claim 1, further comprising a blocking layer disposed between the phosphorescent organic emissive unit and the first electrode. 8. The device of claim 1, further comprising a blocking layer disposed between the phosphorescent organic emissive unit and the second electrode. 9. The device of claim 1, further comprising:
a first blocking layer disposed between the phosphorescent organic emissive unit and the first electrode; and a second blocking layer disposed between the phosphorescent organic emissive unit and the second electrode. 10. The device of claim 1, further comprising a color filter. 11. The device of claim 1, wherein at least one of the first, second, and third organic emissive units comprises at least one layer selected from the group consisting of: an electron blocking layer, an electron transport layer, a hole blocking layer, a hole transport layer, an electron injection layer, and a hole injection layer. 12. A device comprising:
a first electrode; a fluorescent blue first organic emissive layer disposed over the first electrode; a first charge generation layer disposed over the fluorescent blue first organic emissive layer; a phosphorescent second organic emissive layer disposed over the first charge generation layer; a second charge generation layer disposed over the phosphorescent second organic emissive layer; a fluorescent blue third organic emissive layer disposed over the second charge generation layer; and a second electrode disposed over the fluorescent blue third organic emissive layer. 13. The device of claim 12, wherein the phosphorescent second organic emissive layer is selected from the group consisting of: a red organic emissive unit, a green organic emissive unit, and a yellow organic emissive unit. 14. The device of claim 12, wherein the fluorescent blue first organic emissive layer and the fluorescent blue third organic emissive layer emit light in different color regions. 15. The device of claim 12, wherein the fluorescent blue first organic emissive layer and the fluorescent blue third organic emissive layer emit light in the same color region. 16. The device of claim 12, further comprising a blocking layer disposed between the phosphorescent second organic emissive layer and the first electrode. 17. The device of claim 12, further comprising a blocking layer disposed between the phosphorescent second organic emissive layer and the second electrode. 18. The device of claim 12, further comprising:
a first blocking layer disposed between the phosphorescent second organic emissive layer and the first electrode; and a second blocking layer disposed between the phosphorescent second organic emissive layer and the second electrode. 19. The device of claim 12, further comprising a color filter. 20. The device of claim 12, wherein at least one of the fluorescent blue first organic emissive layer, phosphorescent second organic emissive layer, and the fluorescent blue third organic emissive layer comprises at least one layer selected from the group consisting of: an electron blocking layer, an electron transport layer, a hole blocking layer, a hole transport layer, an electron injection layer, and a hole injection layer. | OLEDs containing a stacked hybrid architecture including a phosphorescent organic emissive unit and two fluorescent organic emissive units are disclosed. The stacked hybrid architecture includes a plurality of electrodes and a hybrid emissive stacked disposed between at least two of the electrodes. The stack contains at least three emissive units and at least two charge generation layers. At least one of the three emissive units is a phosphorescent organic emissive unit and at least two of the three emissive units are fluorescent organic emissive units. More specifically, the two fluorescent organic emissive units may be blue organic emissive units that emit light from the same or different color regions.1. A device comprising: a first electrode;
a second electrode; and a hybrid emissive stack disposed between the first electrode and the second electrode, the stack comprising at least three emissive units and at least two charge generation layers, wherein: a first emissive unit of the at least three emissive units is disposed over the first electrode; a first charge generation layer of the at least two charge generation layers is disposed over the first emissive unit; a second emissive unit of the at least three emissive units is disposed over the first charge generation layer; a second charge generation layer of the at least two charge generation layers is disposed over the second emissive unit; and a third emissive unit of the at least three emissive units is disposed over the second charge generation layer, wherein the second emissive unit is a phosphorescent organic emissive unit, and wherein the first emissive unit and the third emissive unit are fluorescent organic emissive units. 2. The device of claim 1, wherein the phosphorescent organic emissive unit is selected from the group consisting of: a red organic emissive unit, a green organic emissive unit, and a yellow organic emissive unit. 3. The device of claim 1, wherein the first emissive unit and the third emissive unit are blue organic emissive units. 4. The device of claim 3, wherein the two blue fluorescent organic emissive units emit light in different color regions. 5. The device of claim 3, wherein the two blue fluorescent organic emissive units emit light in the same color region. 6. The device of claim 1, wherein the phosphorescent organic emissive unit comprises a plurality of emissive materials, each having a different emission spectrum. 7. The device of claim 1, further comprising a blocking layer disposed between the phosphorescent organic emissive unit and the first electrode. 8. The device of claim 1, further comprising a blocking layer disposed between the phosphorescent organic emissive unit and the second electrode. 9. The device of claim 1, further comprising:
a first blocking layer disposed between the phosphorescent organic emissive unit and the first electrode; and a second blocking layer disposed between the phosphorescent organic emissive unit and the second electrode. 10. The device of claim 1, further comprising a color filter. 11. The device of claim 1, wherein at least one of the first, second, and third organic emissive units comprises at least one layer selected from the group consisting of: an electron blocking layer, an electron transport layer, a hole blocking layer, a hole transport layer, an electron injection layer, and a hole injection layer. 12. A device comprising:
a first electrode; a fluorescent blue first organic emissive layer disposed over the first electrode; a first charge generation layer disposed over the fluorescent blue first organic emissive layer; a phosphorescent second organic emissive layer disposed over the first charge generation layer; a second charge generation layer disposed over the phosphorescent second organic emissive layer; a fluorescent blue third organic emissive layer disposed over the second charge generation layer; and a second electrode disposed over the fluorescent blue third organic emissive layer. 13. The device of claim 12, wherein the phosphorescent second organic emissive layer is selected from the group consisting of: a red organic emissive unit, a green organic emissive unit, and a yellow organic emissive unit. 14. The device of claim 12, wherein the fluorescent blue first organic emissive layer and the fluorescent blue third organic emissive layer emit light in different color regions. 15. The device of claim 12, wherein the fluorescent blue first organic emissive layer and the fluorescent blue third organic emissive layer emit light in the same color region. 16. The device of claim 12, further comprising a blocking layer disposed between the phosphorescent second organic emissive layer and the first electrode. 17. The device of claim 12, further comprising a blocking layer disposed between the phosphorescent second organic emissive layer and the second electrode. 18. The device of claim 12, further comprising:
a first blocking layer disposed between the phosphorescent second organic emissive layer and the first electrode; and a second blocking layer disposed between the phosphorescent second organic emissive layer and the second electrode. 19. The device of claim 12, further comprising a color filter. 20. The device of claim 12, wherein at least one of the fluorescent blue first organic emissive layer, phosphorescent second organic emissive layer, and the fluorescent blue third organic emissive layer comprises at least one layer selected from the group consisting of: an electron blocking layer, an electron transport layer, a hole blocking layer, a hole transport layer, an electron injection layer, and a hole injection layer. | 2,800 |
11,808 | 11,808 | 15,711,939 | 2,884 | In accordance with the present approach, a kV switched X-ray source, such as a kV switched X-ray tube, is used in conjunction with a dual-layer detector. In such approaches, the dual-layer detector may be operated so as to ignore or discard signal attributable to low-energy photons generated during a high kV emission interval or view. | 1. A method of acquiring and processing dual-energy X-ray transmission data, comprising:
alternately emitting from an X-ray source a first X-ray beam having a first keV distribution and a second X-ray beam having a second keV distribution different than the first keV distribution; in response to each emitted first X-ray beam, reading out at least a low-energy scintillator signal from a first layer of a dual-layer detector; in response to each emitted second X-ray beam, reading out at least a high-energy scintillator signal from a second layer of the dual layer detector; and processing at least the low-energy scintillator signals and the high-energy scintillator signals to generate an image. 2. The method of claim 1, wherein processing at least the low-energy scintillator signals and the high-energy scintillator signals to generate an image further comprises acquiring an additional high-energy scintillator signal for each emitted first X-ray beam and combining the additional high-energy scintillator signal with the low energy scintillator signal to generate an aggregate low-energy signal used to generate the image. 3. The method of claim 1, wherein the first keV distribution is a lower energy spectrum than the second keV distribution. 4. The method of claim 1, wherein the image is a tissue-type or material decomposition image. 5. The method of claim 1, wherein the X-ray source is a fast kV switched X-ray source. 6. The method of claim 1, further comprising:
rotating the X-ray source and dual-layer detector about an imaged volume during operation. 7. The method of claim 1, wherein the first layer of the dual-layer detector comprises:
a first scintillator material having a first thickness; and a first readout circuitry configured to detect photons generated by the first scintillator material and to generate the low-energy scintillator signals in response. 8. The method of claim 7, wherein the second layer of the dual-layer detector comprises:
a second scintillator material different from the first scintillator material; and a second readout circuitry configured to detect photons generated by the second scintillator material and to generate the high-energy scintillator signals in response. 9. The method of claim 7, wherein the second layer of the dual-layer detector comprises:
a second scintillator material or the first scintillator material at a second thickness different from the first thickness; and a second readout circuitry configured to detect photons generated by the scintillator material of the second layer and to generate the high-energy scintillator signals in response. 10. An imaging system, comprising:
an X-ray source configured to be switched during operation between a first operating voltage corresponding to a first emission spectrum and a second operating voltage corresponding to a second emission spectrum; a dual-layer X-ray detector having a first layer and a second layer; a data acquisition system configured to read out at least the first layer when the X-ray source is operated at the first operating voltage and to read out at least the second layer when the X-ray source is operated at the second operating voltage; and image processing circuitry configured to generate an image using signals acquired from at least the first layer when the X-ray source is operated at the first operating voltage and using signals acquired from only the second layer when the X-ray source is operated at the second operating voltage. 11. The imaging system of claim 10, wherein the first operating voltage and the second operating voltage are in a range between about 70 kVp and about 150 kVp. 12. The imaging system of claim 10, wherein the image is a tissue-type or material decomposition image. 13. The imaging system of claim 10, wherein the first emission spectrum is a lower energy spectrum than the second emission spectrum 14. The imaging system of claim 10, wherein the X-ray source is a fast kV switched X-ray source. 15. The imaging system of claim 10, further comprising a rotational structure on which the X-ray source and dual-layer X-ray detector are mounted. 16. The imaging system of claim 10, wherein the first layer of the dual-layer X-ray detector comprises:
a first scintillator material having a first thickness; and a first readout circuitry configured to detect photons generated by the first scintillator material and to generate low-energy signals in response. 17. The imaging system of claim 10, wherein the second layer of the dual-layer X-ray detector comprises:
a second scintillator material different from the first scintillator material; and a second readout circuitry configured to detect photons generated by the second scintillator material and to generate high-energy signals in response. 18. The imaging system of claim 10, wherein the second layer of the dual-layer X-ray detector comprises:
a second scintillator material or the first scintillator material at a second thickness different from the first thickness; and a second readout circuitry configured to detect photons generated by the scintillator material of the second layer and to generate high-energy signals in response. 19. A method for acquiring dual-energy X-ray data, comprising:
reading out at least a low-energy scintillator layer of a dual-layer detector to generate first signals when the dual-energy detector is irradiated by an X-ray source operated at a first operating voltage; reading out a high-energy scintillator layer of the dual-layer detector to generate second signals when the dual-energy detector is irradiated by the X-ray source operated at a second operating voltage; and generating a tissue-type or material decomposition image using the first signals and the second signals. 20. The method of claim 20, wherein the first operating voltage corresponds to a first X-ray emission spectrum and the second operating voltage corresponding to a second X-ray emission spectrum. | In accordance with the present approach, a kV switched X-ray source, such as a kV switched X-ray tube, is used in conjunction with a dual-layer detector. In such approaches, the dual-layer detector may be operated so as to ignore or discard signal attributable to low-energy photons generated during a high kV emission interval or view.1. A method of acquiring and processing dual-energy X-ray transmission data, comprising:
alternately emitting from an X-ray source a first X-ray beam having a first keV distribution and a second X-ray beam having a second keV distribution different than the first keV distribution; in response to each emitted first X-ray beam, reading out at least a low-energy scintillator signal from a first layer of a dual-layer detector; in response to each emitted second X-ray beam, reading out at least a high-energy scintillator signal from a second layer of the dual layer detector; and processing at least the low-energy scintillator signals and the high-energy scintillator signals to generate an image. 2. The method of claim 1, wherein processing at least the low-energy scintillator signals and the high-energy scintillator signals to generate an image further comprises acquiring an additional high-energy scintillator signal for each emitted first X-ray beam and combining the additional high-energy scintillator signal with the low energy scintillator signal to generate an aggregate low-energy signal used to generate the image. 3. The method of claim 1, wherein the first keV distribution is a lower energy spectrum than the second keV distribution. 4. The method of claim 1, wherein the image is a tissue-type or material decomposition image. 5. The method of claim 1, wherein the X-ray source is a fast kV switched X-ray source. 6. The method of claim 1, further comprising:
rotating the X-ray source and dual-layer detector about an imaged volume during operation. 7. The method of claim 1, wherein the first layer of the dual-layer detector comprises:
a first scintillator material having a first thickness; and a first readout circuitry configured to detect photons generated by the first scintillator material and to generate the low-energy scintillator signals in response. 8. The method of claim 7, wherein the second layer of the dual-layer detector comprises:
a second scintillator material different from the first scintillator material; and a second readout circuitry configured to detect photons generated by the second scintillator material and to generate the high-energy scintillator signals in response. 9. The method of claim 7, wherein the second layer of the dual-layer detector comprises:
a second scintillator material or the first scintillator material at a second thickness different from the first thickness; and a second readout circuitry configured to detect photons generated by the scintillator material of the second layer and to generate the high-energy scintillator signals in response. 10. An imaging system, comprising:
an X-ray source configured to be switched during operation between a first operating voltage corresponding to a first emission spectrum and a second operating voltage corresponding to a second emission spectrum; a dual-layer X-ray detector having a first layer and a second layer; a data acquisition system configured to read out at least the first layer when the X-ray source is operated at the first operating voltage and to read out at least the second layer when the X-ray source is operated at the second operating voltage; and image processing circuitry configured to generate an image using signals acquired from at least the first layer when the X-ray source is operated at the first operating voltage and using signals acquired from only the second layer when the X-ray source is operated at the second operating voltage. 11. The imaging system of claim 10, wherein the first operating voltage and the second operating voltage are in a range between about 70 kVp and about 150 kVp. 12. The imaging system of claim 10, wherein the image is a tissue-type or material decomposition image. 13. The imaging system of claim 10, wherein the first emission spectrum is a lower energy spectrum than the second emission spectrum 14. The imaging system of claim 10, wherein the X-ray source is a fast kV switched X-ray source. 15. The imaging system of claim 10, further comprising a rotational structure on which the X-ray source and dual-layer X-ray detector are mounted. 16. The imaging system of claim 10, wherein the first layer of the dual-layer X-ray detector comprises:
a first scintillator material having a first thickness; and a first readout circuitry configured to detect photons generated by the first scintillator material and to generate low-energy signals in response. 17. The imaging system of claim 10, wherein the second layer of the dual-layer X-ray detector comprises:
a second scintillator material different from the first scintillator material; and a second readout circuitry configured to detect photons generated by the second scintillator material and to generate high-energy signals in response. 18. The imaging system of claim 10, wherein the second layer of the dual-layer X-ray detector comprises:
a second scintillator material or the first scintillator material at a second thickness different from the first thickness; and a second readout circuitry configured to detect photons generated by the scintillator material of the second layer and to generate high-energy signals in response. 19. A method for acquiring dual-energy X-ray data, comprising:
reading out at least a low-energy scintillator layer of a dual-layer detector to generate first signals when the dual-energy detector is irradiated by an X-ray source operated at a first operating voltage; reading out a high-energy scintillator layer of the dual-layer detector to generate second signals when the dual-energy detector is irradiated by the X-ray source operated at a second operating voltage; and generating a tissue-type or material decomposition image using the first signals and the second signals. 20. The method of claim 20, wherein the first operating voltage corresponds to a first X-ray emission spectrum and the second operating voltage corresponding to a second X-ray emission spectrum. | 2,800 |
11,809 | 11,809 | 15,456,033 | 2,895 | According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer, a first electrode, first to third layers, and nitride portions of nitride molecules. The first layer is provided between the semiconductor layer and the first electrode. The second layer is provided between the first layer and the first electrode. The second energy of a conduction band edge of the second layer is lower than a first energy of a conduction band edge of the first layer. The second layer includes a first region and a second region. The first region is provided between the first layer and the second region. The third layer is provided between the second layer and the first electrode. The third energy of a conduction band edge of the third layer is higher than the second energy. | 1. A nonvolatile semiconductor memory device, comprising:
a semiconductor layer; a first electrode; a first layer provided between the semiconductor layer and the first electrode; a second layer provided between the first layer and the first electrode, a second energy of a conduction band edge of the second layer being lower than a first energy of a conduction band edge of the first layer, the second layer including a first region and a second region, the first region being provided between the first layer and the second region; a third layer provided between the second layer and the first electrode, a third energy of a conduction band edge of the third layer being higher than the second energy; and a plurality of nitride portions of nitride molecules, the plurality of nitride portions being provided at one of between the first region and the second region, between the first layer and the second layer, or between the second layer and the third layer, the first layer being a tunneling insulating layer, the second layer being a charge storage layer, the third layer being a blocking insulating layer, the nitride molecule including at least one of TiN, ZrN, HfN, VN, NbN, TaN, CrN, MoN, WN, BN, AlN, GaN or InN, a length in a first direction of the plurality of nitride portions being not more than a maximum value of a size of the nitride molecule, the first direction being from the semiconductor layer toward the first electrode. 2. The device according to claim 1, wherein a density of the plurality of nitride portions in a surface perpendicular to the first direction is not less than 1×1013 cm−2 and not more than 1×1015 cm−2. 3. A nonvolatile semiconductor memory device, comprising:
a semiconductor layer; a first electrode; a first layer provided between the semiconductor layer and the first electrode; a second layer provided between the first layer and the first electrode, a second energy of a conduction band edge of the second layer being lower than a first energy of a conduction band edge of the first layer, the second layer including a first region and a second region, the first region being provided between the first layer and the second region; a third layer provided between the second layer and the first electrode, a third energy of a conduction band edge of the third layer being higher than the second energy; and a plurality of nitride portions of nitride molecules, the plurality of nitride portions being provided at one of between the first region and the second region, between the first layer and the second layer, or between the second layer and the third layer, the nitride molecule includes nitrogen and e first element of one of Group 4, Group 5, Group 6, or Group 13, a density of the plurality of nitride portions in a surface crossing a first direction being not less than 1×1013 cm−2 and not more than 1×1015 cm−2, the first direction being from the semiconductor layer toward the first electrode. 4. The device according to claim 1, wherein the plurality of nitride portions are arranged along a first surface of the semiconductor layer opposing the first layer. 5. The device according to claim 1, wherein the plurality of nitride portions are arranged along a second surface of the first electrode opposing the third layer. 6. The device according to claim 1, further comprising a particle of the first element provided at the one of between the first region and the second region, between the first layer and the second layer, or between the second layer and the third layer. 7. The device according to claim 1, further comprising:
a second electrode arranged with the first electrode in a second direction, the second direction crossing the first direction; and an insulating film provided between the first electrode and the second electrode, the first layer being further provided between the second electrode and the semiconductor layer, the second layer being further provided between the second electrode and the first layer, the third layer being further provided between the second electrode and the second layer. 8. The device according to claim, wherein the semiconductor layer extends along the second direction through a stacked body, the stacked body including the first electrode, the insulating film, and the second electrode 9. A method for manufacturing a nonvolatile semiconductor memory device, the device including a semiconductor layer, a first electrode, a first layer, a second layer, and a third layer, the first layer being provided between the semiconductor layer and the first electrode, the second layer being provided between the first layer and the first electrode, a second energy of a conduction band edge of the second layer being lower than a first energy of a conduction band edge of the first layer, the third layer being provided between the second layer and the first electrode, a third energy of a conduction band edge of the third layer being higher than the second energy, the method comprising:
forming a plurality of nitride portions of nitride molecules at one of between one portion of the second layer and one other portion of the second layer, between the first region and the second region, between the first layer and the second layer, or between the second layer and the third layer, the nitride molecule including nitrogen and a first element of one of Group 4, Group 5, Group 6, or Group 13, a length in a first direction of the plurality of nitride portions being not more than a maximum value of a size of the nitride molecule, the first direction being from the semiconductor layer toward the first electrode. 10. The method according to claim 9, wherein a density of the plurality of nitride portions in a surface crossing the first direction is not less than 1×1013 cm−2 and not more than 1×1015 cm−2. 11. The method according to claim 9, wherein the plurality of nitride portions is formed by atomic layer deposition using a gas including the first element and a gas in nitrogen. 12. The method according to claim 9, further comprising:
forming the first layer; forming the second layer; and forming the third layer, the forming of the plurality of nitride portions being implemented after the forming of the third layer, the forming of the second layer being implemented after the forming of the plurality of nitride portions, the forming of the first layer being implemented after the forming of the second layer. 13. The method according to claim 9, further comprising
forming the first layer; forming the second layer; and forming the third layer, the forming of the part of the second layer being implemented after the forming of the third layer, the forming of the plurality of nitride portions being implemented after the forming of the part of the second layer, the forming of the one other portion of the second layer being implemented after the forming of the plurality of nitride portions, the forming the first layer being implemented after the forming of the one other portion of the second layer, 14. The method according to claim 9, further comprising:
forming the first layer; forming the second layer; and forming the third layer, the forming of the second layer being implemented after the forming of the third layer, the forming of the plurality of nitride portions being implemented after the forming of the second layer, the forming of the first layer being implemented after the forming of the plurality of nitride portions. 15. The method according to claim 12, further comprising:
forming the first electrode after the forming of the third layer; and forming the semiconductor layer after the forming of the first layer. 16. The method according to claim 12, further comprising:
forming a sacrificial layer; removing the sacrificial layer; and forming the first electrode, the forming of the third layer including the forming of the third layer in a face of the sacrificial layer, the forming of the semiconductor layer being implemented after the forming of the first layer, the removing the sacrificial layer being implemented after the forming of the semiconductor layer, the forming the first electrode including forming the first electrode in a face of the third exposed by the removing the sacrificial layer. 17. The method according to claim 9, further comprising:
forming the first layer on the semiconductor layer; forming the second layer after the forming of the first layer; forming the third layer after the forming of the second layer; and forming the first electrode after the forming of the third layer, the forming of the plurality of nitride portions being implemented between the forming of the first layer and the forming the third layer. | According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer, a first electrode, first to third layers, and nitride portions of nitride molecules. The first layer is provided between the semiconductor layer and the first electrode. The second layer is provided between the first layer and the first electrode. The second energy of a conduction band edge of the second layer is lower than a first energy of a conduction band edge of the first layer. The second layer includes a first region and a second region. The first region is provided between the first layer and the second region. The third layer is provided between the second layer and the first electrode. The third energy of a conduction band edge of the third layer is higher than the second energy.1. A nonvolatile semiconductor memory device, comprising:
a semiconductor layer; a first electrode; a first layer provided between the semiconductor layer and the first electrode; a second layer provided between the first layer and the first electrode, a second energy of a conduction band edge of the second layer being lower than a first energy of a conduction band edge of the first layer, the second layer including a first region and a second region, the first region being provided between the first layer and the second region; a third layer provided between the second layer and the first electrode, a third energy of a conduction band edge of the third layer being higher than the second energy; and a plurality of nitride portions of nitride molecules, the plurality of nitride portions being provided at one of between the first region and the second region, between the first layer and the second layer, or between the second layer and the third layer, the first layer being a tunneling insulating layer, the second layer being a charge storage layer, the third layer being a blocking insulating layer, the nitride molecule including at least one of TiN, ZrN, HfN, VN, NbN, TaN, CrN, MoN, WN, BN, AlN, GaN or InN, a length in a first direction of the plurality of nitride portions being not more than a maximum value of a size of the nitride molecule, the first direction being from the semiconductor layer toward the first electrode. 2. The device according to claim 1, wherein a density of the plurality of nitride portions in a surface perpendicular to the first direction is not less than 1×1013 cm−2 and not more than 1×1015 cm−2. 3. A nonvolatile semiconductor memory device, comprising:
a semiconductor layer; a first electrode; a first layer provided between the semiconductor layer and the first electrode; a second layer provided between the first layer and the first electrode, a second energy of a conduction band edge of the second layer being lower than a first energy of a conduction band edge of the first layer, the second layer including a first region and a second region, the first region being provided between the first layer and the second region; a third layer provided between the second layer and the first electrode, a third energy of a conduction band edge of the third layer being higher than the second energy; and a plurality of nitride portions of nitride molecules, the plurality of nitride portions being provided at one of between the first region and the second region, between the first layer and the second layer, or between the second layer and the third layer, the nitride molecule includes nitrogen and e first element of one of Group 4, Group 5, Group 6, or Group 13, a density of the plurality of nitride portions in a surface crossing a first direction being not less than 1×1013 cm−2 and not more than 1×1015 cm−2, the first direction being from the semiconductor layer toward the first electrode. 4. The device according to claim 1, wherein the plurality of nitride portions are arranged along a first surface of the semiconductor layer opposing the first layer. 5. The device according to claim 1, wherein the plurality of nitride portions are arranged along a second surface of the first electrode opposing the third layer. 6. The device according to claim 1, further comprising a particle of the first element provided at the one of between the first region and the second region, between the first layer and the second layer, or between the second layer and the third layer. 7. The device according to claim 1, further comprising:
a second electrode arranged with the first electrode in a second direction, the second direction crossing the first direction; and an insulating film provided between the first electrode and the second electrode, the first layer being further provided between the second electrode and the semiconductor layer, the second layer being further provided between the second electrode and the first layer, the third layer being further provided between the second electrode and the second layer. 8. The device according to claim, wherein the semiconductor layer extends along the second direction through a stacked body, the stacked body including the first electrode, the insulating film, and the second electrode 9. A method for manufacturing a nonvolatile semiconductor memory device, the device including a semiconductor layer, a first electrode, a first layer, a second layer, and a third layer, the first layer being provided between the semiconductor layer and the first electrode, the second layer being provided between the first layer and the first electrode, a second energy of a conduction band edge of the second layer being lower than a first energy of a conduction band edge of the first layer, the third layer being provided between the second layer and the first electrode, a third energy of a conduction band edge of the third layer being higher than the second energy, the method comprising:
forming a plurality of nitride portions of nitride molecules at one of between one portion of the second layer and one other portion of the second layer, between the first region and the second region, between the first layer and the second layer, or between the second layer and the third layer, the nitride molecule including nitrogen and a first element of one of Group 4, Group 5, Group 6, or Group 13, a length in a first direction of the plurality of nitride portions being not more than a maximum value of a size of the nitride molecule, the first direction being from the semiconductor layer toward the first electrode. 10. The method according to claim 9, wherein a density of the plurality of nitride portions in a surface crossing the first direction is not less than 1×1013 cm−2 and not more than 1×1015 cm−2. 11. The method according to claim 9, wherein the plurality of nitride portions is formed by atomic layer deposition using a gas including the first element and a gas in nitrogen. 12. The method according to claim 9, further comprising:
forming the first layer; forming the second layer; and forming the third layer, the forming of the plurality of nitride portions being implemented after the forming of the third layer, the forming of the second layer being implemented after the forming of the plurality of nitride portions, the forming of the first layer being implemented after the forming of the second layer. 13. The method according to claim 9, further comprising
forming the first layer; forming the second layer; and forming the third layer, the forming of the part of the second layer being implemented after the forming of the third layer, the forming of the plurality of nitride portions being implemented after the forming of the part of the second layer, the forming of the one other portion of the second layer being implemented after the forming of the plurality of nitride portions, the forming the first layer being implemented after the forming of the one other portion of the second layer, 14. The method according to claim 9, further comprising:
forming the first layer; forming the second layer; and forming the third layer, the forming of the second layer being implemented after the forming of the third layer, the forming of the plurality of nitride portions being implemented after the forming of the second layer, the forming of the first layer being implemented after the forming of the plurality of nitride portions. 15. The method according to claim 12, further comprising:
forming the first electrode after the forming of the third layer; and forming the semiconductor layer after the forming of the first layer. 16. The method according to claim 12, further comprising:
forming a sacrificial layer; removing the sacrificial layer; and forming the first electrode, the forming of the third layer including the forming of the third layer in a face of the sacrificial layer, the forming of the semiconductor layer being implemented after the forming of the first layer, the removing the sacrificial layer being implemented after the forming of the semiconductor layer, the forming the first electrode including forming the first electrode in a face of the third exposed by the removing the sacrificial layer. 17. The method according to claim 9, further comprising:
forming the first layer on the semiconductor layer; forming the second layer after the forming of the first layer; forming the third layer after the forming of the second layer; and forming the first electrode after the forming of the third layer, the forming of the plurality of nitride portions being implemented between the forming of the first layer and the forming the third layer. | 2,800 |
11,810 | 11,810 | 16,488,044 | 2,853 | There is described a printing press ( 100***; 100 ****) adapted to carry out printing on a sheet-like or web-like substrate (S), in particular for the production of security documents such as banknotes, comprising a printing unit ( 2*; 2**; 2***; 2 ****) designed to print a first side (I) and/or a second side (II) of the substrate (S). The printing press ( 100***; 100 ****) further comprises an in-line casting device ( 80; 80*; 80**; 80 ***) adapted to apply a layer of material acting as an optical medium on a portion of a first side (I, II) of the substrate (S) and to replicate and form a micro-optical structure (L) in the layer of material acting as optical medium. The printing unit ( 2*; 2**; 2***; 2 ****) is furthermore adapted to print at least one printed pattern on the first or second side (I, II) of the substrate (S) in register with the micro-optical structure (L), wherein the printing unit ( 2*; 2**; 2***; 2 ****) comprises at least a first printing group ( 93 ) being adapted to print at least one printed pattern on the second side (II) of the substrate (S) in register with the micro-optical structure (L) and wherein the in-line casting device ( 80; 80*; 80**; 80 ***) comprises at least one embossing cylinder ( 85 ), which embossing cylinder ( 85 ) also is acting as counter-pressure cylinder and cooperates with a printing cylinder ( 8 ) of the at least first printing group ( 93 ) and/or whereas the in-line casting device ( 80; 80*; 80**; 80 ***) and the at least a first printing group ( 93 ) being arranged at the Substrate transport path such way, that in-line casting of the micro-optical structure, on one side of the sheets S, and printing of the associated pattern, on the other side of the sheets S, are performed in a same step, without this involving any sheet transfer operation. | 1-27. (canceled) 28. A printing press adapted to carry out printing on a sheet-like substrate, in particular for the production of security documents such as banknotes, comprising a printing unit designed to print a first side and/or a second side of the substrate,
wherein the printing press further comprises an in-line casting device adapted to apply a layer of material acting as an optical medium on a portion of the first side of the substrate and to replicate and form a micro-optical structure in the layer of material acting as optical medium, which in-line casting device comprises at least an embossing tool, wherein the printing unit comprises at least a first printing group being adapted to print at least one printed pattern on the second side of the substrate in register with the micro-optical structure, and wherein the at least one embossing tool is designed as an embossing cylinder, which embossing cylinder is acting as counter-pressure cylinder and cooperates with a printing cylinder of the at least first printing group. 29. The printing press according to claim 28, wherein the in-line casting device comprises at least an application unit for applying at least a part of the layer of material acting as optical medium. 30. The printing press according to claim 29, wherein a screen-printing unit or flexographic-printing unit is acting as application unit for applying at least a part of the layer of material acting as optical medium. 31. The printing press according to claim 30, wherein the embossing tool is located in the substrate path immediately after the application unit. 32. The printing press according to claim 28, wherein the at least one embossing tool acts as carrier supporting a replicating medium designed to replicate and form the micro-optical structure in the layer of material acting as optical medium and/or is designed as embossing cylinder acting as a conveying cylinder carrying and/or supporting the substrate over an angle range. 33. The printing press according to claim 28, wherein the in-line casting device further comprises at least one pressure cylinder or roller cooperating with the embossing tool to press the substrate against the replicating medium and/or a washing device that can selectively be brought in contact with the embossing tool during maintenance operations to clean the surface of the embossing tool. 34. The printing press according to claim 28, wherein the cylinder of the first printing group cooperating with the embossing tool is acting as blanket cylinder and cooperating with one or more associated plate cylinders to apply the at least one printed pattern on a side of the substrate which is opposite to the side of the substrate where the micro-optical structure is replicated and/or wherein the first printing group is designed as a collect printing group for at least two imprints to be collected before printed onto the substrate. 35. The printing press according to claim 28, wherein the printing press is a sheet-fed printing press adapted to carry out printing on individual sheets as substrate, wherein transfer of the sheets to and/or within the in-line casting device is carried out exclusively from cylinder to cylinder via cooperating cylinder grippers and/or wherein transfer of the sheets between the in-line casting device and one or more downstream printing groups is carried out exclusively from cylinder to cylinder via cooperating cylinder grippers. 36. The printing press according to claim 28, wherein the in-line casting device comprises at least one drying/curing unit advantageously a UV-curing unit, preferably as a UV-LED curing unit, to dry or cure the layer of material acting as optical medium during and/or following replication of the micro-optical structure in the layer of material acting as optical medium and wherein the drying/curing unit is located to dry or cure the layer of material acting as optical medium from the side of the substrate which is opposite to the side of the substrate where the micro-optical structure is replicated or from the side of the substrate where the micro-optical structure is replicated. 37. The printing press according to claim 28, wherein the first printing group comprises one or more plate cylinders and associated inking apparatuses designed to enable indirect printing, preferably offset or relief printing. 38. The printing press according to claim 28, wherein the printing unit comprises a second printing group in the substrate path to print the substrate on one side, preferably on the side opposing the side which being provided with the micro-optical structure. 39. The printing press according to claim 38, wherein the second printing group comprises one or more plate cylinders and associated inking apparatuses designed to enable or carry out indirect printing, preferably offset or relief printing, and/or is designed as collect printing group for at least two imprints to be collected before printed onto the substrate. 40. The printing press according to claim 38, wherein the printing unit comprises a third printing group in the substrate path cooperating with the second printing group in order to build a common nip as double-sided printing group for the simultaneous recto-verso printing of the substrate. 41. The printing press according to claim 40, wherein the third printing group comprises one or more plate cylinders and associated inking apparatuses designed to enable or carry out indirect printing, preferably offset or relief printing, and/or is designed as collect printing group for at least two imprints to be collected before printed onto the substrate. 42. The printing press according to claim 28, wherein the micro-optical structure is replicated by the in-line casting device upstream of a location where the printed pattern is printed by the first printing group of the printing unit. 43. The printing press according to claim 28, wherein the in-line casting device is adapted to apply a layer of material acting as an optical medium on a portion of the first side of the substrate and to replicate and form a micro-optical structure in the layer of material acting as optical medium by firstly applying the material acting as optical medium onto the substrate onto the first side and downstream being brought into contact with the embossing tool to form the micro-optical structure. 44. The printing press according to claim 28, wherein the in-line casting device is adapted to apply a layer of material acting as an optical medium on a portion of the first side of the substrate and to replicate and form a micro-optical structure in the layer of material acting as optical medium by firstly applying the material acting as optical medium directly onto a circumferential surface of the embossing tool in an angular segment not yet being covered by the substrate to be applied with the material. | There is described a printing press ( 100***; 100 ****) adapted to carry out printing on a sheet-like or web-like substrate (S), in particular for the production of security documents such as banknotes, comprising a printing unit ( 2*; 2**; 2***; 2 ****) designed to print a first side (I) and/or a second side (II) of the substrate (S). The printing press ( 100***; 100 ****) further comprises an in-line casting device ( 80; 80*; 80**; 80 ***) adapted to apply a layer of material acting as an optical medium on a portion of a first side (I, II) of the substrate (S) and to replicate and form a micro-optical structure (L) in the layer of material acting as optical medium. The printing unit ( 2*; 2**; 2***; 2 ****) is furthermore adapted to print at least one printed pattern on the first or second side (I, II) of the substrate (S) in register with the micro-optical structure (L), wherein the printing unit ( 2*; 2**; 2***; 2 ****) comprises at least a first printing group ( 93 ) being adapted to print at least one printed pattern on the second side (II) of the substrate (S) in register with the micro-optical structure (L) and wherein the in-line casting device ( 80; 80*; 80**; 80 ***) comprises at least one embossing cylinder ( 85 ), which embossing cylinder ( 85 ) also is acting as counter-pressure cylinder and cooperates with a printing cylinder ( 8 ) of the at least first printing group ( 93 ) and/or whereas the in-line casting device ( 80; 80*; 80**; 80 ***) and the at least a first printing group ( 93 ) being arranged at the Substrate transport path such way, that in-line casting of the micro-optical structure, on one side of the sheets S, and printing of the associated pattern, on the other side of the sheets S, are performed in a same step, without this involving any sheet transfer operation.1-27. (canceled) 28. A printing press adapted to carry out printing on a sheet-like substrate, in particular for the production of security documents such as banknotes, comprising a printing unit designed to print a first side and/or a second side of the substrate,
wherein the printing press further comprises an in-line casting device adapted to apply a layer of material acting as an optical medium on a portion of the first side of the substrate and to replicate and form a micro-optical structure in the layer of material acting as optical medium, which in-line casting device comprises at least an embossing tool, wherein the printing unit comprises at least a first printing group being adapted to print at least one printed pattern on the second side of the substrate in register with the micro-optical structure, and wherein the at least one embossing tool is designed as an embossing cylinder, which embossing cylinder is acting as counter-pressure cylinder and cooperates with a printing cylinder of the at least first printing group. 29. The printing press according to claim 28, wherein the in-line casting device comprises at least an application unit for applying at least a part of the layer of material acting as optical medium. 30. The printing press according to claim 29, wherein a screen-printing unit or flexographic-printing unit is acting as application unit for applying at least a part of the layer of material acting as optical medium. 31. The printing press according to claim 30, wherein the embossing tool is located in the substrate path immediately after the application unit. 32. The printing press according to claim 28, wherein the at least one embossing tool acts as carrier supporting a replicating medium designed to replicate and form the micro-optical structure in the layer of material acting as optical medium and/or is designed as embossing cylinder acting as a conveying cylinder carrying and/or supporting the substrate over an angle range. 33. The printing press according to claim 28, wherein the in-line casting device further comprises at least one pressure cylinder or roller cooperating with the embossing tool to press the substrate against the replicating medium and/or a washing device that can selectively be brought in contact with the embossing tool during maintenance operations to clean the surface of the embossing tool. 34. The printing press according to claim 28, wherein the cylinder of the first printing group cooperating with the embossing tool is acting as blanket cylinder and cooperating with one or more associated plate cylinders to apply the at least one printed pattern on a side of the substrate which is opposite to the side of the substrate where the micro-optical structure is replicated and/or wherein the first printing group is designed as a collect printing group for at least two imprints to be collected before printed onto the substrate. 35. The printing press according to claim 28, wherein the printing press is a sheet-fed printing press adapted to carry out printing on individual sheets as substrate, wherein transfer of the sheets to and/or within the in-line casting device is carried out exclusively from cylinder to cylinder via cooperating cylinder grippers and/or wherein transfer of the sheets between the in-line casting device and one or more downstream printing groups is carried out exclusively from cylinder to cylinder via cooperating cylinder grippers. 36. The printing press according to claim 28, wherein the in-line casting device comprises at least one drying/curing unit advantageously a UV-curing unit, preferably as a UV-LED curing unit, to dry or cure the layer of material acting as optical medium during and/or following replication of the micro-optical structure in the layer of material acting as optical medium and wherein the drying/curing unit is located to dry or cure the layer of material acting as optical medium from the side of the substrate which is opposite to the side of the substrate where the micro-optical structure is replicated or from the side of the substrate where the micro-optical structure is replicated. 37. The printing press according to claim 28, wherein the first printing group comprises one or more plate cylinders and associated inking apparatuses designed to enable indirect printing, preferably offset or relief printing. 38. The printing press according to claim 28, wherein the printing unit comprises a second printing group in the substrate path to print the substrate on one side, preferably on the side opposing the side which being provided with the micro-optical structure. 39. The printing press according to claim 38, wherein the second printing group comprises one or more plate cylinders and associated inking apparatuses designed to enable or carry out indirect printing, preferably offset or relief printing, and/or is designed as collect printing group for at least two imprints to be collected before printed onto the substrate. 40. The printing press according to claim 38, wherein the printing unit comprises a third printing group in the substrate path cooperating with the second printing group in order to build a common nip as double-sided printing group for the simultaneous recto-verso printing of the substrate. 41. The printing press according to claim 40, wherein the third printing group comprises one or more plate cylinders and associated inking apparatuses designed to enable or carry out indirect printing, preferably offset or relief printing, and/or is designed as collect printing group for at least two imprints to be collected before printed onto the substrate. 42. The printing press according to claim 28, wherein the micro-optical structure is replicated by the in-line casting device upstream of a location where the printed pattern is printed by the first printing group of the printing unit. 43. The printing press according to claim 28, wherein the in-line casting device is adapted to apply a layer of material acting as an optical medium on a portion of the first side of the substrate and to replicate and form a micro-optical structure in the layer of material acting as optical medium by firstly applying the material acting as optical medium onto the substrate onto the first side and downstream being brought into contact with the embossing tool to form the micro-optical structure. 44. The printing press according to claim 28, wherein the in-line casting device is adapted to apply a layer of material acting as an optical medium on a portion of the first side of the substrate and to replicate and form a micro-optical structure in the layer of material acting as optical medium by firstly applying the material acting as optical medium directly onto a circumferential surface of the embossing tool in an angular segment not yet being covered by the substrate to be applied with the material. | 2,800 |
11,811 | 11,811 | 15,782,298 | 2,864 | A mechanism is described for provisioning remote desktops in a cloud based infrastructure while maintaining user personalization. In cloud based systems, a user may not always reconnect to the same VM endpoint. In one embodiment, the virtual hard disk assigned to a user is mounted to the endpoint assigned to the user. The virtual hard disk includes the user's personal data and personalization information (e.g., settings, profiles, files, etc.). When the user disconnects from the remote desktop, the virtual hard disk is demounted from the endpoint. The virtual hard disk thus provides information regarding the user's state when the user is disconnected. | 1. A method comprising:
instantiating one or more remote desktop configurations comprising an operating environment and software applications to be included in the operating environment; in response to a request for a first remote desktop session conforming to one of the one or more remote desktop configurations, assigning a virtual machine endpoint to the requested remote desktop session, the virtual machine endpoint selected from a pool of available resources that store user configuration profile information separately from an operating system of the virtual machine endpoint; loading, by a computing device, previously saved user state data associated with the requested first remote desktop session, the previously saved user state data saved as a virtual profile comprising user preference and personal data indicative of a standard desktop configuration for a user role; and updating, by the computing device, the saved state data during the first remote desktop session. 2. The method of claim 1, wherein the previously saved user state is saved independently of the requested remote desktop session. 3. The method of claim 1, wherein the virtual machine endpoint and the virtual profile initially comprises data operable to initially configure a user's desktop in accordance with the standard desktop configuration for the user role. 4. The method of claim 1, further comprising in response to a request for a second remote desktop session, assigning a second virtual machine endpoint to the second remote desktop session from a pool of available virtual machine endpoints. 5. The method of claim 1, further comprising instantiating the requested first remote desktop session when previously saved user state data is not available. 6. The method of claim 5, wherein said instantiating comprises mounting a virtual profile to the endpoint. 7. The method of claim 6, further comprising demounting the virtual profile from the endpoint upon ending the remote desktop session. 8. The method of claim 1, further comprising persisting the saved state data for a subsequent remote desktop session. 9. The method of claim 1, further comprising updating the saved state data when the instantiated remote desktop session is terminated. 10. A cloud computing system comprising: a computing device
comprising at least one processor;
a memory communicatively coupled to said processor when said system is operational; said memory having stored therein computer instructions that upon execution by the at least one processor cause:
instantiating one or more remote desktop configurations comprising an operating environment and software applications to be included in the operating environment;
in response to a request for a first remote desktop session conforming to one of the one or more remote desktop configurations, assigning a virtual machine endpoint to the requested remote desktop session, the virtual machine endpoint selected from a pool of available resources that store user configuration profile information separately from an operating system of the virtual machine endpoint;
loading, by a computing device, previously saved user state data associated with the requested first remote desktop session, the previously saved user state data saved as a virtual profile comprising user preference and personal data indicative of a standard desktop configuration for a user role; and
updating, by the computing device, the saved state data during the first remote desktop session. 10. The system of claim 10, wherein the previously saved user state is saved independently of the requested remote desktop session. 11. The system of claim 10, wherein the virtual machine endpoint and the virtual profile initially comprises data operable to initially configure a user's desktop in accordance with the standard desktop configuration for the user role. 12. The system of claim 10, further comprising mounting the saved state data to the endpoint. 13. The system of claim 10, further comprising in response to a request for a second remote desktop session, assigning a second virtual machine endpoint to the second remote desktop session from a pool of available virtual machine endpoints. 14. The system of claim 10, further comprising instantiating the requested first remote desktop session when previously saved user state data is not available. 15. The system of claim 10, further comprising persisting the saved state data for a subsequent remote desktop session. 16. The system of claim 10, wherein the virtual profile is implemented as a virtual hard disk. 17. A computer readable storage device storing thereon computer executable instructions, the computer readable storage device comprising instructions for:
instantiating one or more remote desktop configurations comprising an operating environment and software applications to be included in the operating environment; in response to a request for a first remote desktop session conforming to one of the one or more remote desktop configurations, assigning a virtual machine endpoint to the requested remote desktop session, the virtual machine endpoint selected from a pool of available resources that store user configuration profile information separately from an operating system of the virtual machine endpoint; loading, by a computing device, previously saved user state data associated with the requested first remote desktop session, the previously saved user state data saved as a virtual profile comprising user preference and personal data indicative of a standard desktop configuration for a user role; and updating, by the computing device, the saved state data during the first remote desktop session. 18. The computer readable storage device of claim 17, further comprising instructions for instantiating the requested first remote desktop session when previously saved user state data is not available. 19. The computer readable storage device of claim 18, wherein said instantiating comprises mounting the virtual profile to the endpoint. 20. The computer readable device of claim 19, further comprising instructions for demounting the virtual profile from the endpoint upon ending the remote desktop session. | A mechanism is described for provisioning remote desktops in a cloud based infrastructure while maintaining user personalization. In cloud based systems, a user may not always reconnect to the same VM endpoint. In one embodiment, the virtual hard disk assigned to a user is mounted to the endpoint assigned to the user. The virtual hard disk includes the user's personal data and personalization information (e.g., settings, profiles, files, etc.). When the user disconnects from the remote desktop, the virtual hard disk is demounted from the endpoint. The virtual hard disk thus provides information regarding the user's state when the user is disconnected.1. A method comprising:
instantiating one or more remote desktop configurations comprising an operating environment and software applications to be included in the operating environment; in response to a request for a first remote desktop session conforming to one of the one or more remote desktop configurations, assigning a virtual machine endpoint to the requested remote desktop session, the virtual machine endpoint selected from a pool of available resources that store user configuration profile information separately from an operating system of the virtual machine endpoint; loading, by a computing device, previously saved user state data associated with the requested first remote desktop session, the previously saved user state data saved as a virtual profile comprising user preference and personal data indicative of a standard desktop configuration for a user role; and updating, by the computing device, the saved state data during the first remote desktop session. 2. The method of claim 1, wherein the previously saved user state is saved independently of the requested remote desktop session. 3. The method of claim 1, wherein the virtual machine endpoint and the virtual profile initially comprises data operable to initially configure a user's desktop in accordance with the standard desktop configuration for the user role. 4. The method of claim 1, further comprising in response to a request for a second remote desktop session, assigning a second virtual machine endpoint to the second remote desktop session from a pool of available virtual machine endpoints. 5. The method of claim 1, further comprising instantiating the requested first remote desktop session when previously saved user state data is not available. 6. The method of claim 5, wherein said instantiating comprises mounting a virtual profile to the endpoint. 7. The method of claim 6, further comprising demounting the virtual profile from the endpoint upon ending the remote desktop session. 8. The method of claim 1, further comprising persisting the saved state data for a subsequent remote desktop session. 9. The method of claim 1, further comprising updating the saved state data when the instantiated remote desktop session is terminated. 10. A cloud computing system comprising: a computing device
comprising at least one processor;
a memory communicatively coupled to said processor when said system is operational; said memory having stored therein computer instructions that upon execution by the at least one processor cause:
instantiating one or more remote desktop configurations comprising an operating environment and software applications to be included in the operating environment;
in response to a request for a first remote desktop session conforming to one of the one or more remote desktop configurations, assigning a virtual machine endpoint to the requested remote desktop session, the virtual machine endpoint selected from a pool of available resources that store user configuration profile information separately from an operating system of the virtual machine endpoint;
loading, by a computing device, previously saved user state data associated with the requested first remote desktop session, the previously saved user state data saved as a virtual profile comprising user preference and personal data indicative of a standard desktop configuration for a user role; and
updating, by the computing device, the saved state data during the first remote desktop session. 10. The system of claim 10, wherein the previously saved user state is saved independently of the requested remote desktop session. 11. The system of claim 10, wherein the virtual machine endpoint and the virtual profile initially comprises data operable to initially configure a user's desktop in accordance with the standard desktop configuration for the user role. 12. The system of claim 10, further comprising mounting the saved state data to the endpoint. 13. The system of claim 10, further comprising in response to a request for a second remote desktop session, assigning a second virtual machine endpoint to the second remote desktop session from a pool of available virtual machine endpoints. 14. The system of claim 10, further comprising instantiating the requested first remote desktop session when previously saved user state data is not available. 15. The system of claim 10, further comprising persisting the saved state data for a subsequent remote desktop session. 16. The system of claim 10, wherein the virtual profile is implemented as a virtual hard disk. 17. A computer readable storage device storing thereon computer executable instructions, the computer readable storage device comprising instructions for:
instantiating one or more remote desktop configurations comprising an operating environment and software applications to be included in the operating environment; in response to a request for a first remote desktop session conforming to one of the one or more remote desktop configurations, assigning a virtual machine endpoint to the requested remote desktop session, the virtual machine endpoint selected from a pool of available resources that store user configuration profile information separately from an operating system of the virtual machine endpoint; loading, by a computing device, previously saved user state data associated with the requested first remote desktop session, the previously saved user state data saved as a virtual profile comprising user preference and personal data indicative of a standard desktop configuration for a user role; and updating, by the computing device, the saved state data during the first remote desktop session. 18. The computer readable storage device of claim 17, further comprising instructions for instantiating the requested first remote desktop session when previously saved user state data is not available. 19. The computer readable storage device of claim 18, wherein said instantiating comprises mounting the virtual profile to the endpoint. 20. The computer readable device of claim 19, further comprising instructions for demounting the virtual profile from the endpoint upon ending the remote desktop session. | 2,800 |
11,812 | 11,812 | 13,223,475 | 2,811 | To provide a highly reliable semiconductor device including an oxide semiconductor. Further to provide a highly reliable light-emitting device including an oxide semiconductor. A second electrode sealed together with a semiconductor element including an oxide semiconductor hardly becomes inactive. A hydrogen ion and/or a hydrogen molecule produced by reaction of the active second electrode with moisture remaining in the semiconductor device and/or moisture entering from the outside of the device increase the carrier concentration in the oxide semiconductor, which causes a reduction in the reliability of the semiconductor device. An adsorption layer of a hydrogen ion and/or a hydrogen molecule may be provided on the other surface side of the second electrode having one surface in contact with the organic layer. Further, an opening which a hydrogen ion and/or a hydrogen molecule passes through may be provided for the second electrode. | 1. A semiconductor device comprising:
a first substrate; a transistor over the first substrate; a light-emitting element over the first substrate, the light-emitting element including:
a first electrode electrically connected to a source electrode or a drain electrode of the transistor;
a second electrode overlapping with the first electrode; and
an organic layer containing a light-emitting substance between the first electrode and the second electrode;
a sealant surrounding the transistor and the light-emitting element; a second substrate facing the first substrate and fixed to the first substrate with the sealant; and an adsorption layer between the first substrate and the second substrate, wherein the adsorption layer is capable of adsorbing at least one of a hydrogen ion and a hydrogen molecule, and wherein a channel formation region of the transistor includes an oxide semiconductor. 2. The semiconductor device according to claim 1, wherein the adsorption layer includes zeolite. 3. The semiconductor device according to claim 1, wherein the adsorption layer includes palladium. 4. The semiconductor device according to claim 1, wherein the transistor is an enhancement transistor. 5. The semiconductor device according to claim 1, wherein the second substrate has a depression portion. 6. The semiconductor device according to claim 1, further comprising a hydrogen-transmitting film provided between the light-emitting element and the adsorption layer. 7. A semiconductor device comprising:
a first substrate; a transistor over the first substrate; a light-emitting element over the first substrate, the light-emitting element including:
a first electrode electrically connected to a source electrode or a drain electrode of the transistor;
a second electrode overlapping with the first electrode, the second electrode has an opening; and
an organic layer containing a light-emitting substance between the first electrode and the second electrode;
a sealant surrounding the transistor and the light-emitting element; a second substrate facing the first substrate and fixed to the first substrate with the sealant; and an adsorption layer between the first substrate and the second substrate, wherein the adsorption layer is capable of adsorbing at least one of a hydrogen ion and a hydrogen molecule, and wherein a channel formation region of the transistor includes an oxide semiconductor. 8. The semiconductor device according to claim 7, wherein the adsorption layer includes zeolite. 9. The semiconductor device according to claim 7, wherein the adsorption layer includes palladium. 10. The semiconductor device according to claim 7, wherein the transistor is an enhancement transistor. 11. The semiconductor device according to claim 7, wherein the second substrate has a depression portion. 12. The semiconductor device according to claim 7, further comprising a hydrogen-transmitting film provided between the light-emitting element and the adsorption layer. 13. A manufacturing method of a semiconductor device comprising the steps of:
forming a transistor over a first substrate, wherein the transistor includes a channel formation region, a source electrode and a drain electrode; forming a first electrode electrically connected to the source electrode or the drain electrode of the transistor; forming an organic layer containing a light-emitting substance over the first electrode; forming a second electrode over the organic layer to form a light-emitting element; and providing an adsorption layer between the first substrate and a second substrate by fixing the second substrate with a sealant so that the second substrate faces the first substrate, wherein the sealant surrounds the transistor and the light-emitting element, wherein the adsorption layer is capable of adsorbing at least one of a hydrogen ion and a hydrogen molecule, and wherein the channel formation region includes an oxide semiconductor. 14. The manufacturing method of the semiconductor device according to claim 13, wherein the adsorption layer includes zeolite. 15. The manufacturing method of the semiconductor device according to claim 13, wherein the adsorption layer includes palladium. 16. The manufacturing method of the semiconductor device according to claim 13, wherein the transistor is an enhancement transistor. 17. The manufacturing method of the semiconductor device according to claim 13, further comprising the step of forming a depression portion in the second substrate. 18. The manufacturing method of the semiconductor device according to claim 13, further comprising the step of forming a hydrogen-transmitting film between the light-emitting element and the adsorption layer. 10 19. A manufacturing method of a semiconductor device comprising the steps of:
forming a transistor over a first substrate, wherein the transistor includes a channel formation region, a source electrode and a drain electrode; forming a first electrode electrically connected to the source electrode or the drain electrode of the transistor; forming an organic layer containing a light-emitting substance over the first electrode; forming a second electrode over the organic layer to form a light-emitting element; forming an opening in the second electrode; and providing an adsorption layer between the first substrate and a second substrate by fixing the second substrate with a sealant so that the second substrate faces the first substrate, wherein the sealant surrounds the transistor and the light-emitting element, wherein the adsorption layer is capable of adsorbing at least one of a hydrogen ion and a hydrogen molecule, and wherein the channel formation region includes an oxide semiconductor. 20. The manufacturing method of the semiconductor device according to claim 19, wherein the adsorption layer includes zeolite. 21. The manufacturing method of the semiconductor device according to claim 19, wherein the adsorption layer includes palladium. 22. The manufacturing method of the semiconductor device according to claim 19, wherein the transistor is an enhancement transistor. 23. The manufacturing method of the semiconductor device according to claim 19, wherein the second substrate has a depression portion. 24. The manufacturing method of the semiconductor device according to claim 19, further comprising the step of forming a hydrogen-transmitting film between the light-emitting element and the adsorption layer. | To provide a highly reliable semiconductor device including an oxide semiconductor. Further to provide a highly reliable light-emitting device including an oxide semiconductor. A second electrode sealed together with a semiconductor element including an oxide semiconductor hardly becomes inactive. A hydrogen ion and/or a hydrogen molecule produced by reaction of the active second electrode with moisture remaining in the semiconductor device and/or moisture entering from the outside of the device increase the carrier concentration in the oxide semiconductor, which causes a reduction in the reliability of the semiconductor device. An adsorption layer of a hydrogen ion and/or a hydrogen molecule may be provided on the other surface side of the second electrode having one surface in contact with the organic layer. Further, an opening which a hydrogen ion and/or a hydrogen molecule passes through may be provided for the second electrode.1. A semiconductor device comprising:
a first substrate; a transistor over the first substrate; a light-emitting element over the first substrate, the light-emitting element including:
a first electrode electrically connected to a source electrode or a drain electrode of the transistor;
a second electrode overlapping with the first electrode; and
an organic layer containing a light-emitting substance between the first electrode and the second electrode;
a sealant surrounding the transistor and the light-emitting element; a second substrate facing the first substrate and fixed to the first substrate with the sealant; and an adsorption layer between the first substrate and the second substrate, wherein the adsorption layer is capable of adsorbing at least one of a hydrogen ion and a hydrogen molecule, and wherein a channel formation region of the transistor includes an oxide semiconductor. 2. The semiconductor device according to claim 1, wherein the adsorption layer includes zeolite. 3. The semiconductor device according to claim 1, wherein the adsorption layer includes palladium. 4. The semiconductor device according to claim 1, wherein the transistor is an enhancement transistor. 5. The semiconductor device according to claim 1, wherein the second substrate has a depression portion. 6. The semiconductor device according to claim 1, further comprising a hydrogen-transmitting film provided between the light-emitting element and the adsorption layer. 7. A semiconductor device comprising:
a first substrate; a transistor over the first substrate; a light-emitting element over the first substrate, the light-emitting element including:
a first electrode electrically connected to a source electrode or a drain electrode of the transistor;
a second electrode overlapping with the first electrode, the second electrode has an opening; and
an organic layer containing a light-emitting substance between the first electrode and the second electrode;
a sealant surrounding the transistor and the light-emitting element; a second substrate facing the first substrate and fixed to the first substrate with the sealant; and an adsorption layer between the first substrate and the second substrate, wherein the adsorption layer is capable of adsorbing at least one of a hydrogen ion and a hydrogen molecule, and wherein a channel formation region of the transistor includes an oxide semiconductor. 8. The semiconductor device according to claim 7, wherein the adsorption layer includes zeolite. 9. The semiconductor device according to claim 7, wherein the adsorption layer includes palladium. 10. The semiconductor device according to claim 7, wherein the transistor is an enhancement transistor. 11. The semiconductor device according to claim 7, wherein the second substrate has a depression portion. 12. The semiconductor device according to claim 7, further comprising a hydrogen-transmitting film provided between the light-emitting element and the adsorption layer. 13. A manufacturing method of a semiconductor device comprising the steps of:
forming a transistor over a first substrate, wherein the transistor includes a channel formation region, a source electrode and a drain electrode; forming a first electrode electrically connected to the source electrode or the drain electrode of the transistor; forming an organic layer containing a light-emitting substance over the first electrode; forming a second electrode over the organic layer to form a light-emitting element; and providing an adsorption layer between the first substrate and a second substrate by fixing the second substrate with a sealant so that the second substrate faces the first substrate, wherein the sealant surrounds the transistor and the light-emitting element, wherein the adsorption layer is capable of adsorbing at least one of a hydrogen ion and a hydrogen molecule, and wherein the channel formation region includes an oxide semiconductor. 14. The manufacturing method of the semiconductor device according to claim 13, wherein the adsorption layer includes zeolite. 15. The manufacturing method of the semiconductor device according to claim 13, wherein the adsorption layer includes palladium. 16. The manufacturing method of the semiconductor device according to claim 13, wherein the transistor is an enhancement transistor. 17. The manufacturing method of the semiconductor device according to claim 13, further comprising the step of forming a depression portion in the second substrate. 18. The manufacturing method of the semiconductor device according to claim 13, further comprising the step of forming a hydrogen-transmitting film between the light-emitting element and the adsorption layer. 10 19. A manufacturing method of a semiconductor device comprising the steps of:
forming a transistor over a first substrate, wherein the transistor includes a channel formation region, a source electrode and a drain electrode; forming a first electrode electrically connected to the source electrode or the drain electrode of the transistor; forming an organic layer containing a light-emitting substance over the first electrode; forming a second electrode over the organic layer to form a light-emitting element; forming an opening in the second electrode; and providing an adsorption layer between the first substrate and a second substrate by fixing the second substrate with a sealant so that the second substrate faces the first substrate, wherein the sealant surrounds the transistor and the light-emitting element, wherein the adsorption layer is capable of adsorbing at least one of a hydrogen ion and a hydrogen molecule, and wherein the channel formation region includes an oxide semiconductor. 20. The manufacturing method of the semiconductor device according to claim 19, wherein the adsorption layer includes zeolite. 21. The manufacturing method of the semiconductor device according to claim 19, wherein the adsorption layer includes palladium. 22. The manufacturing method of the semiconductor device according to claim 19, wherein the transistor is an enhancement transistor. 23. The manufacturing method of the semiconductor device according to claim 19, wherein the second substrate has a depression portion. 24. The manufacturing method of the semiconductor device according to claim 19, further comprising the step of forming a hydrogen-transmitting film between the light-emitting element and the adsorption layer. | 2,800 |
11,813 | 11,813 | 15,189,176 | 2,875 | An accent lighting system is configured to provide accented light onto a desired location. The accent lighting system includes an accent adapter assembly that is configured to securely couple to a light source. The accent adapter assembly includes an accenting plate that is configured to accent light that is emitted from the light source. A method of securing an accent lighting system within an internal cabin of a vehicle includes removing an existing light source from an aperture of a composite panel, securing an accent adapter assembly to the existing light source to form the accent lighting system, and securing the accent lighting system in the aperture of the composite panel. | 1. An accent lighting system that is configured to provide accented light onto a desired location, the accent lighting system comprising:
an accent adapter assembly that is configured to securely couple to a light source, wherein the accent adapter assembly comprises an accenting plate that is configured to accent light that is emitted from the light source. 2. The accent lighting system of claim 1, wherein the accent adapter assembly further comprises a lens that is configured to capture the light emitted from the light source and direct the light into the accenting plate. 3. The accent lighting system of claim 1, wherein the accent adapter assembly further comprises a lens that is configured to focus accented light that passes through the accenting plate onto the desired location. 4. The accent lighting system of claim 1, wherein the accent adapter assembly further comprises:
a sleeve that is configured to securely couple to the light source, wherein the sleeve includes a base that is configured to securely couple to the light source, and a mounting tube; an adjustment housing having first and second ends, wherein the first end is secured to the mounting tube; and a bezel comprising a securing base coupled to the second end of the adjustment housing, and an outer flange that is configured to be positioned over an aperture of a panel. 5. The accent lighting system of claim 4, further comprising a coupling ring that is configured to secure to the light source, wherein the sleeve secures to the coupling ring. 6. The accent lighting system of claim 5, wherein the coupling ring defines a central passage that has a diameter that is substantially the same as a diameter of an aperture of a panel into which the light source is sized to secure into, and wherein the coupling ring has a thickness that is substantially the same as a thickness of the panel. 7. The accent lighting system of claim 4, wherein the accent adapter assembly further comprises:
a first lens disposed within the sleeve, wherein the accenting plate is disposed within the sleeve; and a second lens disposed within the adjustment housing. 8. The accent light system of claim 7, wherein a distance between the first and second lenses is adjustable. 9. The accent lighting system of claim 4, wherein the first end of the adjustment housing is adjustably secured to the mounting tube. 10. The accent lighting system of claim 4, wherein the adjustment housing includes a semi-spherical main body, and wherein the securing base of the bezel is pivotally secured to the semi-spherical main body. 11. The accent lighting system of claim 1, wherein the accent adapter assembly further comprises one or both of a reflector or beam splitter within a light path. 12. The accent lighting system of claim 1, wherein the light source comprises an existing light source within an internal cabin of a vehicle, wherein the light source is removed from a panel within the internal cabin and coupled to the accent adapter assembly to form the accent lighting system, and wherein the accent lighting system is secured to the panel. 13. A method of securing an accent lighting system within an internal cabin of a vehicle, the method comprising:
expanding an aperture of a composite panel within the internal cabin of the vehicle; securing an accent adapter assembly to a light source to form the accent lighting system; and securing the accent lighting system in the expanded aperture of the composite panel. 14. The method of claim 13, further comprising removing an existing light source from the aperture of the composite panel before the expanding, and wherein the securing the adapter assembly to the light source comprises securing the accent adapter assembly to the existing light source that was removed from the aperture. 15. The method of claim 13, further comprising:
securing an accenting plate within the accent adapter assembly. securing a first lens within the accent adapter assembly, wherein the first lens is configured to capture light emitted from the light source and direct the light into the accenting plate; and securing a second lens within the accent adapter assembly, wherein the second lens that is configured to focus accented light that passes through the accenting plate onto a desired location. 16. The method of claim 13, wherein the securing the accent adapter assembly to the light source comprises securely coupling a sleeve of the accent adapter assembly to the light source, and wherein the method further comprises coupling an adjustment housing to the sleeve, and pivotally securing a bezel to the adjustment housing. 17. The method of claim 16, wherein the securely coupling a sleeve of the accent adapter assembly to the light source comprises further comprises:
securing a coupling ring to the light source; and securing the sleeve to the coupling ring, wherein the coupling ring defines a central passage that has a diameter that is substantially the same as a diameter of an aperture of a panel into which the light source is sized to secure into, and wherein the coupling ring has a thickness that is substantially the same as a thickness of the panel. 18. The method of claim 13, further comprising disposing one or both of a reflector or beam splitter within a light path of the accent adapter assembly. 19. A vehicle comprising:
an internal cabin; a composite panel within the internal cabin, wherein the composite panel comprises an aperture; and an accent lighting system that is secured within the aperture of the composite panel and is configured to provide accented light onto a desired location within the internal cabin, the accent lighting system comprising:
a light source; and
an accent adapter assembly that securely couples to the light source, wherein the accent adapter assembly comprises: (a) an accenting plate that is configured to accent light that is emitted from the light source, (b) a first lens that is configured to capture the light emitted from the light source and direct the light into the accenting plate, and (c) a second lens that is configured to focus accented light that passes through the accenting plate onto the desired location, wherein a distance between the first and second lenses is adjustable. 20. The accent lighting system of claim 19, further comprising a coupling ring that secures to the light source, wherein the coupling ring defines a central passage that has a diameter that is substantially the same as a diameter of the aperture of the composite panel, and wherein the coupling ring has a thickness that is substantially the same as a thickness of the composite panel, and wherein the accent adapter assembly further comprises:
a sleeve that is configured to securely couple to the light source, wherein the sleeve includes a base that is configured to securely couple to the light source, and a mounting tube, wherein the sleeve secures to the coupling ring; an adjustment housing having first and second ends, wherein the first end is secured to the mounting tube; and a bezel comprising a securing base pivotally coupled to the second end of the adjustment housing, and an outer flange that is configured to be positioned over an aperture of a panel. | An accent lighting system is configured to provide accented light onto a desired location. The accent lighting system includes an accent adapter assembly that is configured to securely couple to a light source. The accent adapter assembly includes an accenting plate that is configured to accent light that is emitted from the light source. A method of securing an accent lighting system within an internal cabin of a vehicle includes removing an existing light source from an aperture of a composite panel, securing an accent adapter assembly to the existing light source to form the accent lighting system, and securing the accent lighting system in the aperture of the composite panel.1. An accent lighting system that is configured to provide accented light onto a desired location, the accent lighting system comprising:
an accent adapter assembly that is configured to securely couple to a light source, wherein the accent adapter assembly comprises an accenting plate that is configured to accent light that is emitted from the light source. 2. The accent lighting system of claim 1, wherein the accent adapter assembly further comprises a lens that is configured to capture the light emitted from the light source and direct the light into the accenting plate. 3. The accent lighting system of claim 1, wherein the accent adapter assembly further comprises a lens that is configured to focus accented light that passes through the accenting plate onto the desired location. 4. The accent lighting system of claim 1, wherein the accent adapter assembly further comprises:
a sleeve that is configured to securely couple to the light source, wherein the sleeve includes a base that is configured to securely couple to the light source, and a mounting tube; an adjustment housing having first and second ends, wherein the first end is secured to the mounting tube; and a bezel comprising a securing base coupled to the second end of the adjustment housing, and an outer flange that is configured to be positioned over an aperture of a panel. 5. The accent lighting system of claim 4, further comprising a coupling ring that is configured to secure to the light source, wherein the sleeve secures to the coupling ring. 6. The accent lighting system of claim 5, wherein the coupling ring defines a central passage that has a diameter that is substantially the same as a diameter of an aperture of a panel into which the light source is sized to secure into, and wherein the coupling ring has a thickness that is substantially the same as a thickness of the panel. 7. The accent lighting system of claim 4, wherein the accent adapter assembly further comprises:
a first lens disposed within the sleeve, wherein the accenting plate is disposed within the sleeve; and a second lens disposed within the adjustment housing. 8. The accent light system of claim 7, wherein a distance between the first and second lenses is adjustable. 9. The accent lighting system of claim 4, wherein the first end of the adjustment housing is adjustably secured to the mounting tube. 10. The accent lighting system of claim 4, wherein the adjustment housing includes a semi-spherical main body, and wherein the securing base of the bezel is pivotally secured to the semi-spherical main body. 11. The accent lighting system of claim 1, wherein the accent adapter assembly further comprises one or both of a reflector or beam splitter within a light path. 12. The accent lighting system of claim 1, wherein the light source comprises an existing light source within an internal cabin of a vehicle, wherein the light source is removed from a panel within the internal cabin and coupled to the accent adapter assembly to form the accent lighting system, and wherein the accent lighting system is secured to the panel. 13. A method of securing an accent lighting system within an internal cabin of a vehicle, the method comprising:
expanding an aperture of a composite panel within the internal cabin of the vehicle; securing an accent adapter assembly to a light source to form the accent lighting system; and securing the accent lighting system in the expanded aperture of the composite panel. 14. The method of claim 13, further comprising removing an existing light source from the aperture of the composite panel before the expanding, and wherein the securing the adapter assembly to the light source comprises securing the accent adapter assembly to the existing light source that was removed from the aperture. 15. The method of claim 13, further comprising:
securing an accenting plate within the accent adapter assembly. securing a first lens within the accent adapter assembly, wherein the first lens is configured to capture light emitted from the light source and direct the light into the accenting plate; and securing a second lens within the accent adapter assembly, wherein the second lens that is configured to focus accented light that passes through the accenting plate onto a desired location. 16. The method of claim 13, wherein the securing the accent adapter assembly to the light source comprises securely coupling a sleeve of the accent adapter assembly to the light source, and wherein the method further comprises coupling an adjustment housing to the sleeve, and pivotally securing a bezel to the adjustment housing. 17. The method of claim 16, wherein the securely coupling a sleeve of the accent adapter assembly to the light source comprises further comprises:
securing a coupling ring to the light source; and securing the sleeve to the coupling ring, wherein the coupling ring defines a central passage that has a diameter that is substantially the same as a diameter of an aperture of a panel into which the light source is sized to secure into, and wherein the coupling ring has a thickness that is substantially the same as a thickness of the panel. 18. The method of claim 13, further comprising disposing one or both of a reflector or beam splitter within a light path of the accent adapter assembly. 19. A vehicle comprising:
an internal cabin; a composite panel within the internal cabin, wherein the composite panel comprises an aperture; and an accent lighting system that is secured within the aperture of the composite panel and is configured to provide accented light onto a desired location within the internal cabin, the accent lighting system comprising:
a light source; and
an accent adapter assembly that securely couples to the light source, wherein the accent adapter assembly comprises: (a) an accenting plate that is configured to accent light that is emitted from the light source, (b) a first lens that is configured to capture the light emitted from the light source and direct the light into the accenting plate, and (c) a second lens that is configured to focus accented light that passes through the accenting plate onto the desired location, wherein a distance between the first and second lenses is adjustable. 20. The accent lighting system of claim 19, further comprising a coupling ring that secures to the light source, wherein the coupling ring defines a central passage that has a diameter that is substantially the same as a diameter of the aperture of the composite panel, and wherein the coupling ring has a thickness that is substantially the same as a thickness of the composite panel, and wherein the accent adapter assembly further comprises:
a sleeve that is configured to securely couple to the light source, wherein the sleeve includes a base that is configured to securely couple to the light source, and a mounting tube, wherein the sleeve secures to the coupling ring; an adjustment housing having first and second ends, wherein the first end is secured to the mounting tube; and a bezel comprising a securing base pivotally coupled to the second end of the adjustment housing, and an outer flange that is configured to be positioned over an aperture of a panel. | 2,800 |
11,814 | 11,814 | 15,737,343 | 2,875 | Systems and methods are provided for lighting systems that are compact and portable, and adaptable to various lighting requirements simultaneously when opened and used in an intended use environment. | 1. A lighting system, comprising:
a lighting apparatus being configured to exist in at least two states, the lighting apparatus including a head, a body, and a base in adjustable relationship with each other; wherein the lighting apparatus, in a first state, is expanded such that the body is disposed between the head and the base, the head being disposed apart from the base and including a cap having at least two light panels rotatably attached from a first juncture of the cap, each of the two light panels being rotatable relative to each other and being movable in at least two axes relative to the cap, and wherein, the lighting apparatus, in a second state, is tubular in shape, the body being collapsed such that the head and the base are proximate each other and closed about respective portions of the body. 2. (canceled) 3. The lighting system as in claim 1, wherein each of the light panels has a cover disposed on a first side and a light element disposed on an opposing second side. 4. The lighting system as in claim 1, further comprising a third light panel rotatably attached to the cap at a second juncture apart from the first juncture, the two light panels at the first juncture being movable in at least two axes relative to the third light panel at the second juncture. 5. The lighting system as in claim 1, wherein the cap includes a gap configured to receive a portion of the light panels in the second state. 6. The lighting system as in claim 1, wherein the body includes a first rod and a second rod, the first rod being smaller than the second rod such that a portion of the first rod is slidable into the second rod to cause the second state. 7. A lighting system, comprising:
a light head having a plurality of light panels, at least two of the light panels depending in parallel from a first juncture of the light head and a third light panel depending from a second juncture of the light head, the panels being adjustable relative to each other; a body having at least two rods, the rods being configured to telescope relative to each other; a base having a plurality of feet; and a quick release mechanism for adjusting the body. 8. The lighting system as in claim 7, wherein each light panel is configured to adjust in at least three axes. 9. The lighting system as in claim 7, wherein the quick release mechanism includes a ring and a handle, the handle being configured to apply pressure to the ring to render the rods stationary. 10. The lighting system as in claim 7, further comprising a collar configured to move about one of the rods and to adjust the feet. 11. The lighting system as in claim 7, wherein the body further comprises a stand having a space defined therein, and further comprising an anchor disposed in the space, the anchor being configured to extend from the body to stabilize the system. 12-16. (canceled) 17. A lighting system, comprising:
a lighting apparatus being configured to exist in at least two states, the lighting apparatus including a head, a body, and a base in adjustable relationship with each other; wherein the lighting apparatus, in a first state, is expanded such that the body is disposed between the head and the base, the head including a cap having a first pair of light panels depending from a first juncture of the cap and a second pair of light panels depending from a second juncture of the cap, the light panels of each pair being rotatable relative to each other and being movable in at least two axes relative to the cap, and wherein, the lighting apparatus, in a second state, is tubular in shape, the body being collapsible such that the head and the base are proximate each other and closed about respective portions of the body. | Systems and methods are provided for lighting systems that are compact and portable, and adaptable to various lighting requirements simultaneously when opened and used in an intended use environment.1. A lighting system, comprising:
a lighting apparatus being configured to exist in at least two states, the lighting apparatus including a head, a body, and a base in adjustable relationship with each other; wherein the lighting apparatus, in a first state, is expanded such that the body is disposed between the head and the base, the head being disposed apart from the base and including a cap having at least two light panels rotatably attached from a first juncture of the cap, each of the two light panels being rotatable relative to each other and being movable in at least two axes relative to the cap, and wherein, the lighting apparatus, in a second state, is tubular in shape, the body being collapsed such that the head and the base are proximate each other and closed about respective portions of the body. 2. (canceled) 3. The lighting system as in claim 1, wherein each of the light panels has a cover disposed on a first side and a light element disposed on an opposing second side. 4. The lighting system as in claim 1, further comprising a third light panel rotatably attached to the cap at a second juncture apart from the first juncture, the two light panels at the first juncture being movable in at least two axes relative to the third light panel at the second juncture. 5. The lighting system as in claim 1, wherein the cap includes a gap configured to receive a portion of the light panels in the second state. 6. The lighting system as in claim 1, wherein the body includes a first rod and a second rod, the first rod being smaller than the second rod such that a portion of the first rod is slidable into the second rod to cause the second state. 7. A lighting system, comprising:
a light head having a plurality of light panels, at least two of the light panels depending in parallel from a first juncture of the light head and a third light panel depending from a second juncture of the light head, the panels being adjustable relative to each other; a body having at least two rods, the rods being configured to telescope relative to each other; a base having a plurality of feet; and a quick release mechanism for adjusting the body. 8. The lighting system as in claim 7, wherein each light panel is configured to adjust in at least three axes. 9. The lighting system as in claim 7, wherein the quick release mechanism includes a ring and a handle, the handle being configured to apply pressure to the ring to render the rods stationary. 10. The lighting system as in claim 7, further comprising a collar configured to move about one of the rods and to adjust the feet. 11. The lighting system as in claim 7, wherein the body further comprises a stand having a space defined therein, and further comprising an anchor disposed in the space, the anchor being configured to extend from the body to stabilize the system. 12-16. (canceled) 17. A lighting system, comprising:
a lighting apparatus being configured to exist in at least two states, the lighting apparatus including a head, a body, and a base in adjustable relationship with each other; wherein the lighting apparatus, in a first state, is expanded such that the body is disposed between the head and the base, the head including a cap having a first pair of light panels depending from a first juncture of the cap and a second pair of light panels depending from a second juncture of the cap, the light panels of each pair being rotatable relative to each other and being movable in at least two axes relative to the cap, and wherein, the lighting apparatus, in a second state, is tubular in shape, the body being collapsible such that the head and the base are proximate each other and closed about respective portions of the body. | 2,800 |
11,815 | 11,815 | 15,784,066 | 2,816 | Described examples include an apparatus, including: a substrate having a first surface configured to mount at least one integrated circuit and having a second surface opposite the first surface, the second surface having a plurality of terminals arranged in rows and columns, and at least one row of the plurality of terminals disposed adjacent a first side and extending generally along the length of the substrate arranged in a pattern extending along a longitudinal line, the pattern including a first group of consecutive terminals extending in a first direction at a first angle to the longitudinal line and directed towards an interior of the substrate, a second group of consecutive terminals extending in a second direction at a second angle and extending towards the periphery of the substrate, and a third group of consecutive ones of the terminals extending from the second group in the first direction. | 1. An apparatus, comprising:
a substrate having a first surface configured to include at least one integrated circuit, and having a second surface opposite the first surface, the second surface having a plurality of terminals, the substrate having a a first, second, third, and fourth sides forming a periphery of the substrate; and at least a first set of the plurality of terminals disposed adjacent the first side of the substrate and forming a periphery of the plurality of terminals adjacent to the first side of the substrate, the first set of the plurality of terminals arranged in a pattern, the pattern comprising a first group of consecutive ones of the terminals extending in a first direction at a first angle to a longitudinal line parallel to the first side and directed towards an interior of the substrate, a second group of consecutive terminals extending in a second direction at a second angle with respect to the first direction and extending towards the periphery of the substrate, and a third group of consecutive ones of the of the terminals extending from the second group and extending in the first direction at a third angle to the second direction and away from the periphery of the substrate, wherein the plurality of terminals is electrically connected to the integrated circuit. 2. The apparatus of claim 1, in which the first angle is an angle of forty five degrees with respect to the longitudinal line. 3. The apparatus of claim 2, in which the second angle is ninety degrees with respect to the first direction. 4. The apparatus of claim 3, in which the third angle is an angle of ninety degrees with respect to the second direction. 5. (canceled) 6. The apparatus of claim 1, in which the terminals are solder balls. 7. The apparatus of claim 6, in which the apparatus forms a ball grid array (BGA) package for the integrated circuit. 8. The apparatus of claim 1, in which the plurality of terminals include signal terminals for at least one of transmitting and receiving communication signals interspersed with ground terminals for coupling to a ground potential. 9. The apparatus of claim 8 in which the signal terminals include pairs of differential signal terminals disposed adjacent one another, the pairs spaced apart by ground terminals. 10. The apparatus of claim 9 in which the pairs of signal terminals are configured to transmit or receive PCI-Express signals. 11. (canceled) 12. The apparatus of claim 1, and further including at least one additional terminal placed between the first set of the plurality of terminals and the periphery of the substrate, wherein the at least one additional terminal is not electrically connected to the integrated circuit. 13. A ball grid array package, comprising:
a substrate having an integrated circuit device mounted on a first surface and electrically connected to the substrate, and having an array of solder balls mounted on an opposing second surface, the substrate having a first side and an opposite third side extending along a length of the substrate, and having a third side and an opposite fourth side in parallel with the third side and extending along a width of the substrate, the first, second, third and fourth side forming a periphery of the substrate; and at least one row of the array of solder balls extending along the length of the substrate and disposed proximate to the first side of the substrate and being the outermost row with respect to the periphery of the substrate, the at least one row of the array of solder balls forming a repeating zig-zag pattern that extends in a lengthwise direction across the substrate. 14. The ball grid array package of claim 13, in which:
the at least one row of the array of solder balls includes a first group of consecutive solder balls in the at least one row extending in a first direction away from the periphery of the substrate, the first direction at a first angle with respect to a longitudinal direction extending across the substrate; a second group of consecutive solder balls of the at least one row extending from a terminal at an end of the first group, the second group extending in a second direction at a second angle with respect to the first direction; and a third group of consecutive solder balls extending from a terminal at an end of the second group, the third group extending in the first direction at a third angle with respect to the second direction. 15. The ball grid array package of claim 13, in which the solder balls of the array of solder balls on the substrate are spaced at a uniform pitch distance from one another. 16. The ball grid array package of claim 13, in which the integrated circuit device is electrically coupled to the substrate with wire bonds. 17. The ball grid array package of claim 13, in which the integrated circuit device is electrically coupled to the substrate with die bumps in a flip chip arrangement. 18. The ball grid array package of claim 13, in which the at least one row of the array of solder balls includes solder balls for differential pairs of signals. 19. An apparatus, comprising:
a printed circuit board having a land pattern for mounting a semiconductor device including an array of conductive pads, the land pattern having a length and width, the land pattern having at least one row of the array of conductive pads extending along in a lengthwise direction across the land pattern and disposed proximate to a first side of the land pattern and being an outermost row of the array of pads with respect to a periphery of the land pattern, the at least one row of the array of pads forming a repeating zig-zag pattern that extends in the lengthwise direction across the land pattern. 20. The apparatus of claim 19, in which the repeating zig-zag pattern includes a first group of pads in the at least one row of conductive pads that extends in a first direction from the periphery of the land pattern towards an interior portion of the land pattern, the first direction forming a first angle with respect to a longitudinal line that is parallel to the periphery of the land pattern, a second group of pads consecutive to the first group of pads in the at least one row of pads and extending in a second direction, the second direction being from the interior portion towards the periphery of the land pattern, and the second direction forming a second angle with respect to the first direction, and a third group of conductive pads in the at least one row of pads, the third group consecutive to the second group, the third group extending in a third direction parallel to the first direction and extending from the periphery towards the interior portion of the land pattern, the third direction intersecting the second direction at a third angle. 21. The apparatus of claim 1 further comprising:
a second set of the plurality of terminals disposed adjacent the second side of the substrate and forming a periphery of the plurality of terminals adjacent to the second side of the substrate;
a third set of the plurality of terminals disposed adjacent the third side of the substrate and forming a periphery of the plurality of terminals adjacent to the third side of the substrate; and
a fourth set of the plurality of terminals disposed adjacent the fourth side of the substrate and forming a periphery of the plurality of terminals adjacent to the fourth side of the substrate. 22. The apparatus of claim 21, in which the first set of the plurality of terminals, the first set of the plurality of terminals, the first set of the plurality of terminals, and the first set of the plurality of terminals together form a periphery of the plurality of terminals from a bottom view of the apparatus. | Described examples include an apparatus, including: a substrate having a first surface configured to mount at least one integrated circuit and having a second surface opposite the first surface, the second surface having a plurality of terminals arranged in rows and columns, and at least one row of the plurality of terminals disposed adjacent a first side and extending generally along the length of the substrate arranged in a pattern extending along a longitudinal line, the pattern including a first group of consecutive terminals extending in a first direction at a first angle to the longitudinal line and directed towards an interior of the substrate, a second group of consecutive terminals extending in a second direction at a second angle and extending towards the periphery of the substrate, and a third group of consecutive ones of the terminals extending from the second group in the first direction.1. An apparatus, comprising:
a substrate having a first surface configured to include at least one integrated circuit, and having a second surface opposite the first surface, the second surface having a plurality of terminals, the substrate having a a first, second, third, and fourth sides forming a periphery of the substrate; and at least a first set of the plurality of terminals disposed adjacent the first side of the substrate and forming a periphery of the plurality of terminals adjacent to the first side of the substrate, the first set of the plurality of terminals arranged in a pattern, the pattern comprising a first group of consecutive ones of the terminals extending in a first direction at a first angle to a longitudinal line parallel to the first side and directed towards an interior of the substrate, a second group of consecutive terminals extending in a second direction at a second angle with respect to the first direction and extending towards the periphery of the substrate, and a third group of consecutive ones of the of the terminals extending from the second group and extending in the first direction at a third angle to the second direction and away from the periphery of the substrate, wherein the plurality of terminals is electrically connected to the integrated circuit. 2. The apparatus of claim 1, in which the first angle is an angle of forty five degrees with respect to the longitudinal line. 3. The apparatus of claim 2, in which the second angle is ninety degrees with respect to the first direction. 4. The apparatus of claim 3, in which the third angle is an angle of ninety degrees with respect to the second direction. 5. (canceled) 6. The apparatus of claim 1, in which the terminals are solder balls. 7. The apparatus of claim 6, in which the apparatus forms a ball grid array (BGA) package for the integrated circuit. 8. The apparatus of claim 1, in which the plurality of terminals include signal terminals for at least one of transmitting and receiving communication signals interspersed with ground terminals for coupling to a ground potential. 9. The apparatus of claim 8 in which the signal terminals include pairs of differential signal terminals disposed adjacent one another, the pairs spaced apart by ground terminals. 10. The apparatus of claim 9 in which the pairs of signal terminals are configured to transmit or receive PCI-Express signals. 11. (canceled) 12. The apparatus of claim 1, and further including at least one additional terminal placed between the first set of the plurality of terminals and the periphery of the substrate, wherein the at least one additional terminal is not electrically connected to the integrated circuit. 13. A ball grid array package, comprising:
a substrate having an integrated circuit device mounted on a first surface and electrically connected to the substrate, and having an array of solder balls mounted on an opposing second surface, the substrate having a first side and an opposite third side extending along a length of the substrate, and having a third side and an opposite fourth side in parallel with the third side and extending along a width of the substrate, the first, second, third and fourth side forming a periphery of the substrate; and at least one row of the array of solder balls extending along the length of the substrate and disposed proximate to the first side of the substrate and being the outermost row with respect to the periphery of the substrate, the at least one row of the array of solder balls forming a repeating zig-zag pattern that extends in a lengthwise direction across the substrate. 14. The ball grid array package of claim 13, in which:
the at least one row of the array of solder balls includes a first group of consecutive solder balls in the at least one row extending in a first direction away from the periphery of the substrate, the first direction at a first angle with respect to a longitudinal direction extending across the substrate; a second group of consecutive solder balls of the at least one row extending from a terminal at an end of the first group, the second group extending in a second direction at a second angle with respect to the first direction; and a third group of consecutive solder balls extending from a terminal at an end of the second group, the third group extending in the first direction at a third angle with respect to the second direction. 15. The ball grid array package of claim 13, in which the solder balls of the array of solder balls on the substrate are spaced at a uniform pitch distance from one another. 16. The ball grid array package of claim 13, in which the integrated circuit device is electrically coupled to the substrate with wire bonds. 17. The ball grid array package of claim 13, in which the integrated circuit device is electrically coupled to the substrate with die bumps in a flip chip arrangement. 18. The ball grid array package of claim 13, in which the at least one row of the array of solder balls includes solder balls for differential pairs of signals. 19. An apparatus, comprising:
a printed circuit board having a land pattern for mounting a semiconductor device including an array of conductive pads, the land pattern having a length and width, the land pattern having at least one row of the array of conductive pads extending along in a lengthwise direction across the land pattern and disposed proximate to a first side of the land pattern and being an outermost row of the array of pads with respect to a periphery of the land pattern, the at least one row of the array of pads forming a repeating zig-zag pattern that extends in the lengthwise direction across the land pattern. 20. The apparatus of claim 19, in which the repeating zig-zag pattern includes a first group of pads in the at least one row of conductive pads that extends in a first direction from the periphery of the land pattern towards an interior portion of the land pattern, the first direction forming a first angle with respect to a longitudinal line that is parallel to the periphery of the land pattern, a second group of pads consecutive to the first group of pads in the at least one row of pads and extending in a second direction, the second direction being from the interior portion towards the periphery of the land pattern, and the second direction forming a second angle with respect to the first direction, and a third group of conductive pads in the at least one row of pads, the third group consecutive to the second group, the third group extending in a third direction parallel to the first direction and extending from the periphery towards the interior portion of the land pattern, the third direction intersecting the second direction at a third angle. 21. The apparatus of claim 1 further comprising:
a second set of the plurality of terminals disposed adjacent the second side of the substrate and forming a periphery of the plurality of terminals adjacent to the second side of the substrate;
a third set of the plurality of terminals disposed adjacent the third side of the substrate and forming a periphery of the plurality of terminals adjacent to the third side of the substrate; and
a fourth set of the plurality of terminals disposed adjacent the fourth side of the substrate and forming a periphery of the plurality of terminals adjacent to the fourth side of the substrate. 22. The apparatus of claim 21, in which the first set of the plurality of terminals, the first set of the plurality of terminals, the first set of the plurality of terminals, and the first set of the plurality of terminals together form a periphery of the plurality of terminals from a bottom view of the apparatus. | 2,800 |
11,816 | 11,816 | 14,784,579 | 2,827 | The invention relates to a measuring device and a measurement method for the display of a measurement signal connected to the measuring device. The measuring device comprises a measurement-signal input, a measurement-parameter input, a calculation unit and a display unit for the display of calculated statistical signals. The measuring device is set up to display a plurality of statistical signals in parallel on the display unit in real-time. | 1-15. (canceled) 16. A measuring device comprising:
an input configured to receive an measurement-signal; a calculation unit configured to calculate a plurality of statistical signals based on the measurement signal; and a display unit configured to display the plurality of calculated statistical signals in parallel. 17. The measuring device according to claim 16, wherein the display unit is configured display the plurality of calculated statistical signals in parallel within different respective display regions. 18. The measuring device according to claim 17, wherein:
the calculation unit is configured to calculate the statistical signals based on an overall measurement range of the measurement signal; and each display region reflects a region of interest within the overall measurement range. 19. The measuring device according to claim 18, wherein:
the overall measurement range includes one or more regions of non-interest along with the regions of interest; and the measuring device is configured to display only the regions of interest on the display unit. 20. The measuring device according to claim 17, further comprising:
a parameter input configured to receive a measurement parameter for the display of each statistical signal in the respective display region; and wherein the statistical signal displayed within each display region is adjusted via individual parametrization based on the respective measurement parameter. 21. The measuring device according to claim 17, wherein each of the statistical signals is displayed within the respective display region based on a respective mask trigger. 22. The measuring device according to claim 18, wherein a first region of interest is adjusted based on a first resolution bandwidth, and a second region of interest is adjusted based on a second resolution bandwidth. 23. The measuring device according to claim 22, wherein the first resolution bandwidth differs from the second resolution bandwidth. 24. The measuring device according to claim 18, wherein a first region of interest is adjusted based on a first measurement level, and a second region of interest is adjusted based on a second measurement level. 25. The measuring device according to claim 24, wherein the first measurement level differs from the second measurement level. 26. The measuring device according to claim 18, wherein a first region of interest is adjusted based on a first trigger condition, and a second region of interest is adjusted based on a second trigger condition. 27. The measuring device according to claim 26, wherein the first trigger condition differs from the second trigger condition. 28. A measurement method comprising:
receiving, by a measuring device, a measurement signal; determining a plurality of statistical signals based on the measurement signal; and displaying the plurality of calculated statistical signals in parallel. 29. The measurement method according to claim 28, wherein the plurality of statistical signals are displayed in parallel, each within a different respective display region. 30. The measurement method according to claim 29, wherein:
the statistical signals are determined based on an overall measurement range of the measurement signal; and each display region reflects a region of interest within the overall measurement range. 31. The measurement method according to claim 30, wherein:
the overall measurement range includes one or more regions of non-interest along with the regions of interest; and only the regions of interest are displayed. 32. The measurement method according to claim 29, further comprising:
receiving a measurement parameter for the display of each statistical signal in the respective display region; and wherein the statistical signal displayed within each display region is adjusted via individual parametrization based on the respective measurement parameter. 33. The measurement method according to claim 30, wherein one or more of a trigger condition, a resolution bandwidth and a measurement level is adjusted for each region of interest. | The invention relates to a measuring device and a measurement method for the display of a measurement signal connected to the measuring device. The measuring device comprises a measurement-signal input, a measurement-parameter input, a calculation unit and a display unit for the display of calculated statistical signals. The measuring device is set up to display a plurality of statistical signals in parallel on the display unit in real-time.1-15. (canceled) 16. A measuring device comprising:
an input configured to receive an measurement-signal; a calculation unit configured to calculate a plurality of statistical signals based on the measurement signal; and a display unit configured to display the plurality of calculated statistical signals in parallel. 17. The measuring device according to claim 16, wherein the display unit is configured display the plurality of calculated statistical signals in parallel within different respective display regions. 18. The measuring device according to claim 17, wherein:
the calculation unit is configured to calculate the statistical signals based on an overall measurement range of the measurement signal; and each display region reflects a region of interest within the overall measurement range. 19. The measuring device according to claim 18, wherein:
the overall measurement range includes one or more regions of non-interest along with the regions of interest; and the measuring device is configured to display only the regions of interest on the display unit. 20. The measuring device according to claim 17, further comprising:
a parameter input configured to receive a measurement parameter for the display of each statistical signal in the respective display region; and wherein the statistical signal displayed within each display region is adjusted via individual parametrization based on the respective measurement parameter. 21. The measuring device according to claim 17, wherein each of the statistical signals is displayed within the respective display region based on a respective mask trigger. 22. The measuring device according to claim 18, wherein a first region of interest is adjusted based on a first resolution bandwidth, and a second region of interest is adjusted based on a second resolution bandwidth. 23. The measuring device according to claim 22, wherein the first resolution bandwidth differs from the second resolution bandwidth. 24. The measuring device according to claim 18, wherein a first region of interest is adjusted based on a first measurement level, and a second region of interest is adjusted based on a second measurement level. 25. The measuring device according to claim 24, wherein the first measurement level differs from the second measurement level. 26. The measuring device according to claim 18, wherein a first region of interest is adjusted based on a first trigger condition, and a second region of interest is adjusted based on a second trigger condition. 27. The measuring device according to claim 26, wherein the first trigger condition differs from the second trigger condition. 28. A measurement method comprising:
receiving, by a measuring device, a measurement signal; determining a plurality of statistical signals based on the measurement signal; and displaying the plurality of calculated statistical signals in parallel. 29. The measurement method according to claim 28, wherein the plurality of statistical signals are displayed in parallel, each within a different respective display region. 30. The measurement method according to claim 29, wherein:
the statistical signals are determined based on an overall measurement range of the measurement signal; and each display region reflects a region of interest within the overall measurement range. 31. The measurement method according to claim 30, wherein:
the overall measurement range includes one or more regions of non-interest along with the regions of interest; and only the regions of interest are displayed. 32. The measurement method according to claim 29, further comprising:
receiving a measurement parameter for the display of each statistical signal in the respective display region; and wherein the statistical signal displayed within each display region is adjusted via individual parametrization based on the respective measurement parameter. 33. The measurement method according to claim 30, wherein one or more of a trigger condition, a resolution bandwidth and a measurement level is adjusted for each region of interest. | 2,800 |
11,817 | 11,817 | 13,934,517 | 2,865 | A arrangement for calibrating at least two sensors in parallel, including a data processing unit, especially a measurement transmitter for a multisensor system or a computer, wherein the data processing unit has an interface, via which the at least two sensors are connected via separate transmission lines for transmission of data, and wherein the data processing unit is embodied to perform calibrations of the at least two sensors in parallel and independently of one another. | 1-12. (canceled) 13. An arrangement for calibrating at least two sensors in parallel, comprising:
a data processing unit, embodied to perform calibrations of the at least two sensors in parallel and independently of one another, wherein: said data processing unit is a measurement transmitter or a computer for a multisensor system; and said data processing unit has an interface, via which the at least two sensors are connected via separate transmission lines for transmission of data. 14. The arrangement as claimed in claim 13, wherein:
said data processing unit has a processor, which is connected with the interface for processing in- and output signals; and an operating program for the at least two sensors is associated with said data processing unit and executable by said processor. 15. The arrangement as claimed in claim 13, wherein:
each of the sensors connected with said data processing unit has its own measurement channel; and the operating program is embodied to operate said measurement channels in parallel and independently of one another. 16. The arrangement as claimed in claim 15, wherein:
the operating program is instantiable multiple times and each instance of the operating program is associated uniquely with one of the sensors connected to said data processing unit and is executable by the processor in parallel with and independently of other instances, in order to calibrate the sensors in parallel and independently of one another. 17. The arrangement as claimed in claim 15, wherein:
the operating program is embodied to display measured values registered by the sensors during the calibrating simultaneously by means of a display system of said data processing unit. 18. The arrangement as claimed in claim 13, wherein:
the at least two sensors are embodied for measuring one and the same parameter, especially a pH-value. 19. The arrangement as claimed in claim 13, wherein:
at least two sensors of the arrangement are embodied for measuring different parameters. 20. The arrangement as claimed in claim 13, wherein:
the sensors include on-site electronics, which has a memory, which said data processing unit can access for executing the operating program. 21. The arrangement as claimed in claim 20, wherein:
the operating program is embodied to store currently ascertained calibration data in said memory. 22. A method for calibrating at least two sensors in parallel, comprising the steps of:
connecting the at least two sensors via separate transmission lines for transmission of data to an interface of a data processing unit, especially a measurement transmitter or a computer, for a multisensor system; and calibrating the at least two sensors in parallel and independently of one another by means of the data processing unit, especially the measurement transmitter. 23. The method as claimed in claim 22, wherein:
the at least two sensors are embodied for measuring one and the same parameter; and the at least two sensors are placed simultaneously in contact with a calibration medium and the measured values registered by the sensors are output to the data processing unit and used by the data processing unit for calibration. 24. The method as claimed in claim 22, wherein:
the calibration measured values registered by the sensors in the case of the calibrating are recorded by the operating program and displayed by means of a display system of the data processing unit, especially in a shared presentation. | A arrangement for calibrating at least two sensors in parallel, including a data processing unit, especially a measurement transmitter for a multisensor system or a computer, wherein the data processing unit has an interface, via which the at least two sensors are connected via separate transmission lines for transmission of data, and wherein the data processing unit is embodied to perform calibrations of the at least two sensors in parallel and independently of one another.1-12. (canceled) 13. An arrangement for calibrating at least two sensors in parallel, comprising:
a data processing unit, embodied to perform calibrations of the at least two sensors in parallel and independently of one another, wherein: said data processing unit is a measurement transmitter or a computer for a multisensor system; and said data processing unit has an interface, via which the at least two sensors are connected via separate transmission lines for transmission of data. 14. The arrangement as claimed in claim 13, wherein:
said data processing unit has a processor, which is connected with the interface for processing in- and output signals; and an operating program for the at least two sensors is associated with said data processing unit and executable by said processor. 15. The arrangement as claimed in claim 13, wherein:
each of the sensors connected with said data processing unit has its own measurement channel; and the operating program is embodied to operate said measurement channels in parallel and independently of one another. 16. The arrangement as claimed in claim 15, wherein:
the operating program is instantiable multiple times and each instance of the operating program is associated uniquely with one of the sensors connected to said data processing unit and is executable by the processor in parallel with and independently of other instances, in order to calibrate the sensors in parallel and independently of one another. 17. The arrangement as claimed in claim 15, wherein:
the operating program is embodied to display measured values registered by the sensors during the calibrating simultaneously by means of a display system of said data processing unit. 18. The arrangement as claimed in claim 13, wherein:
the at least two sensors are embodied for measuring one and the same parameter, especially a pH-value. 19. The arrangement as claimed in claim 13, wherein:
at least two sensors of the arrangement are embodied for measuring different parameters. 20. The arrangement as claimed in claim 13, wherein:
the sensors include on-site electronics, which has a memory, which said data processing unit can access for executing the operating program. 21. The arrangement as claimed in claim 20, wherein:
the operating program is embodied to store currently ascertained calibration data in said memory. 22. A method for calibrating at least two sensors in parallel, comprising the steps of:
connecting the at least two sensors via separate transmission lines for transmission of data to an interface of a data processing unit, especially a measurement transmitter or a computer, for a multisensor system; and calibrating the at least two sensors in parallel and independently of one another by means of the data processing unit, especially the measurement transmitter. 23. The method as claimed in claim 22, wherein:
the at least two sensors are embodied for measuring one and the same parameter; and the at least two sensors are placed simultaneously in contact with a calibration medium and the measured values registered by the sensors are output to the data processing unit and used by the data processing unit for calibration. 24. The method as claimed in claim 22, wherein:
the calibration measured values registered by the sensors in the case of the calibrating are recorded by the operating program and displayed by means of a display system of the data processing unit, especially in a shared presentation. | 2,800 |
11,818 | 11,818 | 15,094,469 | 2,836 | The present invention relates to a semiconductor device and it is an object of the present invention to provide a semiconductor device that makes it easy to change a specification on driving of a power semiconductor element or control of a protection operation thereof. The semiconductor device includes a power semiconductor element, a main electrode terminal of the power semiconductor element, a sensor section that emits a signal corresponding to a physical state of the power semiconductor element, a sensor signal terminal connected to the sensor section, a drive terminal that supplies power to drive the power semiconductor element and a case that accommodates the power semiconductor element, the main electrode terminal, the sensor section, the sensor signal terminal and the drive terminal, and the sensor signal terminal and the drive terminal are provided so as to be connectable from outside the case. | 1. A semiconductor device comprising:
a power semiconductor element; a main electrode terminal of the power semiconductor element; a sensor section that emits a signal corresponding to a physical state of the power semiconductor element; a sensor signal terminal connected to the sensor section; a drive terminal that supplies power to drive the power semiconductor element; and a case that accommodates the power semiconductor element, the main electrode terminal, the sensor section, the sensor signal terminal and the drive terminal, wherein the sensor signal terminal and the drive terminal are provided so as to be connectable from outside the case. 2. The semiconductor device according to claim 1, wherein the physical state is a temperature. 3. The semiconductor device according to claim 1, wherein the physical state is a current. 4. The semiconductor device according to claims 1, wherein the physical state is a voltage. 5. The semiconductor device according to claims 1, wherein the sensor signal terminal and the drive terminal are disposed inside the case and top ends of the sensor signal terminal and the drive terminal are lower than a top surface portion of the case. 6. The semiconductor device according to claims 1, wherein top ends of the sensor signal terminal and the drive terminal are higher than a top surface portion of the case. 7. The semiconductor device according to claims 1, wherein the sensor signal terminal and the drive terminal comprise a terminal whose top end is lower than a top surface portion of the case and a terminal whose top end is higher than the top surface portion of the case. 8. The semiconductor device according to claims 1, wherein the sensor signal terminal comprises a terminal that outputs a signal extracted from a wiring pattern on which the power semiconductor element is mounted. 9. The semiconductor device according to claims 1, wherein the sensor signal terminal and the drive terminal are disposed on a wiring pattern. 10. The semiconductor device according to claims 1, wherein the power semiconductor element is formed of a wide bandgap semiconductor. 11. The semiconductor device according to claim 10, wherein the wide bandgap semiconductor is silicon carbide, nitride gallium-based material or diamond. 12. The semiconductor device according to claims 1, wherein the sensor signal terminal and the drive terminal comprise a press-fit terminal. 13. The semiconductor device according to claims 1, wherein the sensor signal terminal and the drive terminal are female type terminals. 14. The semiconductor device according to claims 1, wherein the inside of the case is filled with sealing resin. 15. An intelligent power module comprising:
the semiconductor device according to claims 1; and a control substrate connected to the sensor signal terminal and the drive terminal, wherein the control substrate comprises: an external input/output control signal terminal; and an integrated circuit, and the integrated circuit is connected to the external input/output control signal terminal, the sensor signal terminal and the drive terminal, and controls driving of the power semiconductor element and controls a protection operation of the power semiconductor element corresponding to a signal outputted from the sensor signal terminal. 16. A power conversion apparatus comprising the semiconductor device according to claims 1. | The present invention relates to a semiconductor device and it is an object of the present invention to provide a semiconductor device that makes it easy to change a specification on driving of a power semiconductor element or control of a protection operation thereof. The semiconductor device includes a power semiconductor element, a main electrode terminal of the power semiconductor element, a sensor section that emits a signal corresponding to a physical state of the power semiconductor element, a sensor signal terminal connected to the sensor section, a drive terminal that supplies power to drive the power semiconductor element and a case that accommodates the power semiconductor element, the main electrode terminal, the sensor section, the sensor signal terminal and the drive terminal, and the sensor signal terminal and the drive terminal are provided so as to be connectable from outside the case.1. A semiconductor device comprising:
a power semiconductor element; a main electrode terminal of the power semiconductor element; a sensor section that emits a signal corresponding to a physical state of the power semiconductor element; a sensor signal terminal connected to the sensor section; a drive terminal that supplies power to drive the power semiconductor element; and a case that accommodates the power semiconductor element, the main electrode terminal, the sensor section, the sensor signal terminal and the drive terminal, wherein the sensor signal terminal and the drive terminal are provided so as to be connectable from outside the case. 2. The semiconductor device according to claim 1, wherein the physical state is a temperature. 3. The semiconductor device according to claim 1, wherein the physical state is a current. 4. The semiconductor device according to claims 1, wherein the physical state is a voltage. 5. The semiconductor device according to claims 1, wherein the sensor signal terminal and the drive terminal are disposed inside the case and top ends of the sensor signal terminal and the drive terminal are lower than a top surface portion of the case. 6. The semiconductor device according to claims 1, wherein top ends of the sensor signal terminal and the drive terminal are higher than a top surface portion of the case. 7. The semiconductor device according to claims 1, wherein the sensor signal terminal and the drive terminal comprise a terminal whose top end is lower than a top surface portion of the case and a terminal whose top end is higher than the top surface portion of the case. 8. The semiconductor device according to claims 1, wherein the sensor signal terminal comprises a terminal that outputs a signal extracted from a wiring pattern on which the power semiconductor element is mounted. 9. The semiconductor device according to claims 1, wherein the sensor signal terminal and the drive terminal are disposed on a wiring pattern. 10. The semiconductor device according to claims 1, wherein the power semiconductor element is formed of a wide bandgap semiconductor. 11. The semiconductor device according to claim 10, wherein the wide bandgap semiconductor is silicon carbide, nitride gallium-based material or diamond. 12. The semiconductor device according to claims 1, wherein the sensor signal terminal and the drive terminal comprise a press-fit terminal. 13. The semiconductor device according to claims 1, wherein the sensor signal terminal and the drive terminal are female type terminals. 14. The semiconductor device according to claims 1, wherein the inside of the case is filled with sealing resin. 15. An intelligent power module comprising:
the semiconductor device according to claims 1; and a control substrate connected to the sensor signal terminal and the drive terminal, wherein the control substrate comprises: an external input/output control signal terminal; and an integrated circuit, and the integrated circuit is connected to the external input/output control signal terminal, the sensor signal terminal and the drive terminal, and controls driving of the power semiconductor element and controls a protection operation of the power semiconductor element corresponding to a signal outputted from the sensor signal terminal. 16. A power conversion apparatus comprising the semiconductor device according to claims 1. | 2,800 |
11,819 | 11,819 | 15,873,758 | 2,842 | In some examples, a device comprises a first driver coupled to a first node, the first node to couple to a first load external to the device. The device comprises a second driver coupled to a second node, the second node coupled to a second load internal to the device. The device comprises a comparison circuit having an inverting input coupled to the first node and a non-inverting input coupled to the second node. Sizes of the second driver and the second load are configured proportionately to sizes of the first driver and the first load, respectively. | 1. A device comprising:
a first driver coupled to a first node, the first node to couple to a first load external to the device; a second driver coupled to a second node, the second node coupled to a second load internal to the device; and a comparison circuit having an inverting input coupled to the first node and a non-inverting input coupled to the second node, wherein sizes of the second driver and the second load are configured proportionately to sizes of the first driver and the first load, respectively. 2. The device of claim 1 further comprising a voltage offset circuit coupled to the first node. 3. The device of claim 1 further comprising a de-glitch circuit coupled to an output of the comparison circuit. 4. The device of claim 1, wherein the first and second drivers include first and second transistors, respectively, and wherein a sizing ratio between the first and second transistors is inversely proportional to an impedance ratio between the first and second loads. 5. The device of claim 4 further comprising an amplifier having an output coupled to gates of the first and second transistors and having a first input coupled to drains of the first and second transistors and a second input coupled to a third transistor. 6. The device of claim 5 further comprising a fourth transistor having a gate coupled to a gate of the third transistor and having a drain coupled to a drain of the third transistor, a source of the fourth transistor coupled to the drains of the first and second transistors. 7. The device of claim 6 further comprising a power supply rail coupled to the drains of the third and fourth transistors. 8. The device of claim 1, wherein the device includes an IC package and wherein the first node is on a pin of the IC package. 9. A device comprising:
a first transistor having a terminal coupled to a first node, the first node to couple to a first load external to the device; a second transistor having a terminal coupled to a second node, the second node coupled to a second load internal to the device, wherein gates of the first and second transistors couple to each other; a voltage offset circuit coupled to at least one of the first and second nodes; a comparison circuit coupled to the voltage offset circuit and to one of the first and second nodes; and a de-glitch circuit coupled to an output of the comparison circuit. 10. The device of claim 9 further comprising an amplifier having an output coupled to the gates of the first and second transistors. 11. The device of claim 10, wherein a first input of the amplifier couples to a drain of the first transistor and wherein a second input of the amplifier couples to a source of a third transistor. 12. The device of claim 11 further comprising a fourth transistor having a gate tied to a gate of the third transistor and having drain tied to a drain of the third transistor. 13. The device of claim 9, wherein the de-glitch circuit provides a time delay of the output of the comparison circuit of at least 50 microseconds. 14. The device of claim 9, wherein an impedance ratio of the first and second loads is inversely proportional to a sizing ratio of the first and second transistors. 15. The device of claim 9, wherein the device comprises an integrated circuit (IC) package and wherein the first node is on a pin of the IC package. 16. An integrated circuit (IC) package, comprising:
a first field effect transistor (FET) coupled to a pin of the IC package; a load; a second FET coupled to the load via a node, the first and second FETs having common gate potentials; a comparison circuit having inputs coupled to the first and second FETs, at least one of the comparison circuit inputs having a voltage offset circuit coupled thereto; a de-glitch circuit coupled to an output of the comparison circuit; an amplifier having an output coupled to gates of the first and second FETs and having a first input coupled to non-gate terminals of the first and second FETs and having a second input; and third and fourth FETs having common gate potentials and having a pair of non-gate terminals coupled to each other, the third FET coupled to the second input of the amplifier and the fourth FET coupled to the first input of the amplifier. 17. The package of claim 16, wherein the third and fourth FETs have common drain potentials. 18. The package of claim 16, wherein the first and second FETs have common drain potentials. 19. The package of claim 16, wherein the pin is to couple to another load external to the package, and wherein an impedance ratio of the load and the another load is inversely proportional to a sizing ratio of the first and second FETs. 20. The package of claim 16, wherein the first, second, third and fourth FETs are n-type metal oxide semiconductor field effect transistors (MOSFETs). 21. A device comprising:
a first driver coupled to a first node, the first node to couple to a first load external to the device; a second driver coupled to a second node, the second node coupled to a second load internal to the device; and a comparison circuit coupled to the first and second nodes and configured to generate an alert signal in response to a voltage at the first node dropping below a voltage at the second node, wherein the second driver and the second load are configured proportionately to the first driver and the first load, respectively, such that the voltage at the second node is within a predetermined range of the voltage at the first node during a non-short circuit condition at the first node. 22. The device of claim 21, wherein the comparison circuit comprises a comparator. 23. The device of claim 21, wherein the comparison circuit comprises an amplifier coupled to an analog-to-digital converter. 24. The device of claim 21, further comprising a voltage offset circuit coupled to the comparison circuit, the voltage offset circuit comprising a resistor coupled to one or more current sources. | In some examples, a device comprises a first driver coupled to a first node, the first node to couple to a first load external to the device. The device comprises a second driver coupled to a second node, the second node coupled to a second load internal to the device. The device comprises a comparison circuit having an inverting input coupled to the first node and a non-inverting input coupled to the second node. Sizes of the second driver and the second load are configured proportionately to sizes of the first driver and the first load, respectively.1. A device comprising:
a first driver coupled to a first node, the first node to couple to a first load external to the device; a second driver coupled to a second node, the second node coupled to a second load internal to the device; and a comparison circuit having an inverting input coupled to the first node and a non-inverting input coupled to the second node, wherein sizes of the second driver and the second load are configured proportionately to sizes of the first driver and the first load, respectively. 2. The device of claim 1 further comprising a voltage offset circuit coupled to the first node. 3. The device of claim 1 further comprising a de-glitch circuit coupled to an output of the comparison circuit. 4. The device of claim 1, wherein the first and second drivers include first and second transistors, respectively, and wherein a sizing ratio between the first and second transistors is inversely proportional to an impedance ratio between the first and second loads. 5. The device of claim 4 further comprising an amplifier having an output coupled to gates of the first and second transistors and having a first input coupled to drains of the first and second transistors and a second input coupled to a third transistor. 6. The device of claim 5 further comprising a fourth transistor having a gate coupled to a gate of the third transistor and having a drain coupled to a drain of the third transistor, a source of the fourth transistor coupled to the drains of the first and second transistors. 7. The device of claim 6 further comprising a power supply rail coupled to the drains of the third and fourth transistors. 8. The device of claim 1, wherein the device includes an IC package and wherein the first node is on a pin of the IC package. 9. A device comprising:
a first transistor having a terminal coupled to a first node, the first node to couple to a first load external to the device; a second transistor having a terminal coupled to a second node, the second node coupled to a second load internal to the device, wherein gates of the first and second transistors couple to each other; a voltage offset circuit coupled to at least one of the first and second nodes; a comparison circuit coupled to the voltage offset circuit and to one of the first and second nodes; and a de-glitch circuit coupled to an output of the comparison circuit. 10. The device of claim 9 further comprising an amplifier having an output coupled to the gates of the first and second transistors. 11. The device of claim 10, wherein a first input of the amplifier couples to a drain of the first transistor and wherein a second input of the amplifier couples to a source of a third transistor. 12. The device of claim 11 further comprising a fourth transistor having a gate tied to a gate of the third transistor and having drain tied to a drain of the third transistor. 13. The device of claim 9, wherein the de-glitch circuit provides a time delay of the output of the comparison circuit of at least 50 microseconds. 14. The device of claim 9, wherein an impedance ratio of the first and second loads is inversely proportional to a sizing ratio of the first and second transistors. 15. The device of claim 9, wherein the device comprises an integrated circuit (IC) package and wherein the first node is on a pin of the IC package. 16. An integrated circuit (IC) package, comprising:
a first field effect transistor (FET) coupled to a pin of the IC package; a load; a second FET coupled to the load via a node, the first and second FETs having common gate potentials; a comparison circuit having inputs coupled to the first and second FETs, at least one of the comparison circuit inputs having a voltage offset circuit coupled thereto; a de-glitch circuit coupled to an output of the comparison circuit; an amplifier having an output coupled to gates of the first and second FETs and having a first input coupled to non-gate terminals of the first and second FETs and having a second input; and third and fourth FETs having common gate potentials and having a pair of non-gate terminals coupled to each other, the third FET coupled to the second input of the amplifier and the fourth FET coupled to the first input of the amplifier. 17. The package of claim 16, wherein the third and fourth FETs have common drain potentials. 18. The package of claim 16, wherein the first and second FETs have common drain potentials. 19. The package of claim 16, wherein the pin is to couple to another load external to the package, and wherein an impedance ratio of the load and the another load is inversely proportional to a sizing ratio of the first and second FETs. 20. The package of claim 16, wherein the first, second, third and fourth FETs are n-type metal oxide semiconductor field effect transistors (MOSFETs). 21. A device comprising:
a first driver coupled to a first node, the first node to couple to a first load external to the device; a second driver coupled to a second node, the second node coupled to a second load internal to the device; and a comparison circuit coupled to the first and second nodes and configured to generate an alert signal in response to a voltage at the first node dropping below a voltage at the second node, wherein the second driver and the second load are configured proportionately to the first driver and the first load, respectively, such that the voltage at the second node is within a predetermined range of the voltage at the first node during a non-short circuit condition at the first node. 22. The device of claim 21, wherein the comparison circuit comprises a comparator. 23. The device of claim 21, wherein the comparison circuit comprises an amplifier coupled to an analog-to-digital converter. 24. The device of claim 21, further comprising a voltage offset circuit coupled to the comparison circuit, the voltage offset circuit comprising a resistor coupled to one or more current sources. | 2,800 |
11,820 | 11,820 | 15,972,318 | 2,876 | An opt-in system includes a point-of-sale device including a payment device reader. The point-of-sale device is configured to receive, from a payment device associated with a user, payment device information for conducting a transaction, present, through at least one user interface, at least one offer to opt-in to a rewards or loyalty program associated with a commercial entity, receive a user response to the at least one offer to opt-in to the rewards or loyalty program, in response to receiving the user response, automatically fill out an application for the rewards or loyalty program based on the payment device information received from the payment device, and generate a transaction authorization request message based on the user response and transaction information associated with the transaction. | 1. An opt-in system comprising a point-of-sale device including a payment device reader, the point-of-sale device configured to:
receive, from a payment device associated with a user, payment device information for conducting a transaction; present, through at least one user interface, at least one offer to opt-in to a rewards or loyalty program associated with a commercial entity; receive a user response to the at least one offer to opt-in to the rewards or loyalty program; in response to receiving the user response, automatically fill out an application for the rewards or loyalty program based on the payment device information received from the payment device; and generate a transaction authorization request message based on the user response and transaction information associated with the transaction. 2. The opt-in system of claim 1, further comprising printing a receipt for the transaction and a coupon based on the user response. 3. The opt-in system of claim 1, wherein generating the transaction authorization request message comprises:
combining and formatting the transaction information and the user response into formatted information; and including the formatted information in the transaction authorization request message. 4. The opt-in system of claim 1, wherein the payment device information comprises a customer exclusive data field. 5. The opt-in system of claim 4, wherein the customer exclusive data field comprises at least one of the following: loyalty or rewards program information, promotional deal information, or any combination thereof. 6. The opt-in system of claim 4, wherein the customer exclusive data field on the payment device is configured by the payment device reader. 7. The opt-in system of claim 4, wherein generating the transaction authorization request message comprises embedding the user response in the customer exclusive data field. 8. The opt-in system of claim 4, wherein the user response is embedded in the transaction authorization request message. 9. A computer-implemented method for opting-in to a rewards or loyalty program through a point-of-sale device, the point-of-sale device including a payment device reader, comprising:
receiving, from a payment device associated with a user, payment device information for conducting a transaction; presenting, by the point-of-sale device through at least one user interface, at least one offer to opt-in to the rewards or loyalty program; receiving a user response to the at least one offer to opt-in to the rewards or loyalty program; in response to receiving the user response, automatically filling out, by the point-of-sale device, an application for the rewards or loyalty program based on the payment device information received from the payment device; and generating a transaction authorization request message based on the user response and transaction information associated with the transaction. 10. The computer-implemented method of claim 9, further comprising printing a receipt for the transaction and a coupon based on the user response. 11. The computer-implemented method of claim 9, wherein generating the transaction authorization request message comprises:
combining and formatting the transaction information and the user response into formatted information; and including the formatted information in the transaction authorization request message. 12. The computer-implemented method of claim 9, wherein the payment device information comprises a customer exclusive data field. 13. The computer-implemented method of claim 12, wherein the customer exclusive data field comprises at least one of the following: loyalty or rewards program information, promotional deal information, or any combination thereof. 14. The computer-implemented method of claim 12, wherein the customer exclusive data field on the payment device is configured by the payment device reader. 15. The computer-implemented method of claim 12, wherein generating the transaction authorization request message comprises embedding the user response in the customer exclusive data field. 16. The computer-implemented method of claim 12, wherein the user response is embedded in the transaction authorization request message. 17. A point-of-sale device comprising:
a user interface; and a payment device reader in communication with the user interface, the payment device reader configured to:
receive payment device information from a payment device associated with a user conducting a transaction with a merchant;
present, through the user interface, at least one offer to opt-in to a rewards or loyalty program associated with a commercial entity;
receive a user response to the at least one offer to opt-in to the rewards or loyalty program;
in response to receiving the user response, automatically fill out an application for the rewards or loyalty program based on the payment device information received from the payment device; and
generate a transaction authorization request message based on the user response and transaction information associated with the transaction. 18. The point-of-sale device of claim 17, wherein generating the transaction authorization request message comprises:
combining and formatting the transaction information and the user response into formatted information; and including the formatted information in the transaction authorization request message. 19. The point-of-sale device of claim 17, wherein the payment device information comprises a customer exclusive data field. 20. The point-of-sale device of claim 19, wherein generating the transaction authorization request message comprises embedding the user response in the customer exclusive data field. | An opt-in system includes a point-of-sale device including a payment device reader. The point-of-sale device is configured to receive, from a payment device associated with a user, payment device information for conducting a transaction, present, through at least one user interface, at least one offer to opt-in to a rewards or loyalty program associated with a commercial entity, receive a user response to the at least one offer to opt-in to the rewards or loyalty program, in response to receiving the user response, automatically fill out an application for the rewards or loyalty program based on the payment device information received from the payment device, and generate a transaction authorization request message based on the user response and transaction information associated with the transaction.1. An opt-in system comprising a point-of-sale device including a payment device reader, the point-of-sale device configured to:
receive, from a payment device associated with a user, payment device information for conducting a transaction; present, through at least one user interface, at least one offer to opt-in to a rewards or loyalty program associated with a commercial entity; receive a user response to the at least one offer to opt-in to the rewards or loyalty program; in response to receiving the user response, automatically fill out an application for the rewards or loyalty program based on the payment device information received from the payment device; and generate a transaction authorization request message based on the user response and transaction information associated with the transaction. 2. The opt-in system of claim 1, further comprising printing a receipt for the transaction and a coupon based on the user response. 3. The opt-in system of claim 1, wherein generating the transaction authorization request message comprises:
combining and formatting the transaction information and the user response into formatted information; and including the formatted information in the transaction authorization request message. 4. The opt-in system of claim 1, wherein the payment device information comprises a customer exclusive data field. 5. The opt-in system of claim 4, wherein the customer exclusive data field comprises at least one of the following: loyalty or rewards program information, promotional deal information, or any combination thereof. 6. The opt-in system of claim 4, wherein the customer exclusive data field on the payment device is configured by the payment device reader. 7. The opt-in system of claim 4, wherein generating the transaction authorization request message comprises embedding the user response in the customer exclusive data field. 8. The opt-in system of claim 4, wherein the user response is embedded in the transaction authorization request message. 9. A computer-implemented method for opting-in to a rewards or loyalty program through a point-of-sale device, the point-of-sale device including a payment device reader, comprising:
receiving, from a payment device associated with a user, payment device information for conducting a transaction; presenting, by the point-of-sale device through at least one user interface, at least one offer to opt-in to the rewards or loyalty program; receiving a user response to the at least one offer to opt-in to the rewards or loyalty program; in response to receiving the user response, automatically filling out, by the point-of-sale device, an application for the rewards or loyalty program based on the payment device information received from the payment device; and generating a transaction authorization request message based on the user response and transaction information associated with the transaction. 10. The computer-implemented method of claim 9, further comprising printing a receipt for the transaction and a coupon based on the user response. 11. The computer-implemented method of claim 9, wherein generating the transaction authorization request message comprises:
combining and formatting the transaction information and the user response into formatted information; and including the formatted information in the transaction authorization request message. 12. The computer-implemented method of claim 9, wherein the payment device information comprises a customer exclusive data field. 13. The computer-implemented method of claim 12, wherein the customer exclusive data field comprises at least one of the following: loyalty or rewards program information, promotional deal information, or any combination thereof. 14. The computer-implemented method of claim 12, wherein the customer exclusive data field on the payment device is configured by the payment device reader. 15. The computer-implemented method of claim 12, wherein generating the transaction authorization request message comprises embedding the user response in the customer exclusive data field. 16. The computer-implemented method of claim 12, wherein the user response is embedded in the transaction authorization request message. 17. A point-of-sale device comprising:
a user interface; and a payment device reader in communication with the user interface, the payment device reader configured to:
receive payment device information from a payment device associated with a user conducting a transaction with a merchant;
present, through the user interface, at least one offer to opt-in to a rewards or loyalty program associated with a commercial entity;
receive a user response to the at least one offer to opt-in to the rewards or loyalty program;
in response to receiving the user response, automatically fill out an application for the rewards or loyalty program based on the payment device information received from the payment device; and
generate a transaction authorization request message based on the user response and transaction information associated with the transaction. 18. The point-of-sale device of claim 17, wherein generating the transaction authorization request message comprises:
combining and formatting the transaction information and the user response into formatted information; and including the formatted information in the transaction authorization request message. 19. The point-of-sale device of claim 17, wherein the payment device information comprises a customer exclusive data field. 20. The point-of-sale device of claim 19, wherein generating the transaction authorization request message comprises embedding the user response in the customer exclusive data field. | 2,800 |
11,821 | 11,821 | 15,209,842 | 2,884 | When designing detector arrays for diagnostic imaging devices, such as PET or SPECT devices, a virtual detector, or pixel, combines scintillator crystals with photodetectors in ratios that deviate from the conventional 1:1 ratio. For instance, multiple photodetectors can be glued to a single crystal to create a virtual pixel which can be software-based or hardware-based. Light energy and time stamp information for a gamma ray hit on the crystal can be calculated using a virtualizer processor or using a trigger line network and time-to-digital converter logic. Additionally or alternatively, multiple crystals can be associated with each of a plurality of photodetectors. A gamma ray hit on a specific crystal is then determined by a table lookup of adjacent photodetectors that register equal light intensities, and the crystal common to such photodetectors is identified as the location of the hit. | 1. A virtual pixel array for a diagnostic imaging system, including:
a virtual pixel comprising at least one scintillator crystal; a plurality of photodetectors optically coupled to the at least one scintillator crystal, which generate output signals in response to scintillations in the crystal, wherein the plurality of photodetectors includes 4 photodetectors arranged in a 2×2 array; and a virtualizer that processes the output signals associated with a gamma ray hit on the scintillator crystal as detected by the plurality of photodetectors and calculates a time stamp for the gamma ray hit; a plurality of scintillator crystals, including the at least one scintillator crystal, arranged in a rectangular grid; a plurality of the 2×2 arrays of photodetectors optically coupled to the scintillator crystals in an offset relationship such that in each 2×2 array, one of the photodetectors is optically coupled to only one scintillator crystal, one of the photodetectors is optically coupled to two of the scintillator crystals, and two of the photodetectors are optically coupled to four of the scintillator crystals. 2. The virtual pixel array according to claim 1, wherein the length of each side of each scintillator crystal is approximately ½ the length of each side of each photodetector, such that each photodetector is associated with nine scintillator crystals. 3. A method of identifying a scintillator crystal in the virtual pixel array of claim 1, including:
detecting light registration from a gamma ray at a first photodetector; determining whether at least a second photodetector, adjacent to the first photodetector, has registered an amount of light equal to the amount of light registered at the first photodetector; performing a table lookup of photodetectors registering substantially equal amounts of light; and identifying a scintillator crystal overlapping all photodetectors registering the substantially equal amount of light as the scintillator crystal that was hit by the gamma ray. 4. The virtual pixel array according to claim 1, further including:
one or more of: at least one 4×4 array of photodetectors optically coupled to the scintillator crystals in an offset relationship; and at least one 1×1 array of photodetectors optically coupled to the scintillator crystals in an offset relationship. 5. A method of calculating a time stamp for a virtual pixel, including:
arranging a plurality of scintillator crystals, including the at least one scintillator crystal, in a rectangular grid; optically coupling a plurality of 2×2 arrays of photodetectors to the scintillator crystals in an offset relationship such that in each 2×2 array, one of the photodetectors is optically coupled to only one scintillator crystal, one of the photodetectors is optically coupled to two of the scintillator crystals, and two of the photodetectors are optically coupled to four of the scintillator crystals receiving a gamma ray hit on at least one scintillator crystal of the virtual pixel; evaluating output signals from each of a plurality of photodetectors optically coupled to the at least one scintillator crystal to determine an energy and a photodetector time stamp for each photodetector associated with the gamma ray hit; calculating a total energy of the gamma ray hit by combining the energies detected by the plurality of photodetectors associated with the gamma ray hit; and calculating a time stamp for the gamma ray hit as a function of the photodetector time stamp registered by at least one photodetector in the plurality of photodetectors. 6. The method according to claim 5, wherein the length of each side of each scintillator crystal is approximately ½ the length of each side of each photodetector, such that each photodetector is associated with nine scintillator crystals. 7. The method according to claim 5, further comprising:
detecting light registration from a gamma ray at a first photodetector; determining whether at least a second photodetector, adjacent to the first photodetector, has registered an amount of light equal to the amount of light registered at the first photodetector; performing a table lookup of photodetectors registering substantially equal amounts of light; and identifying a scintillator crystal overlapping all photodetectors registering the substantially equal amount of light as the scintillator crystal that was hit by the gamma ray. 8. The method according to claim 5, further including:
one or more of: optically coupling at least one 4×4 array of photodetectors to the scintillator crystals in an offset relationship; and optically coupling at least one 1×1 array of photodetectors to the scintillator crystals in an offset relationship. 9. A detector array for a diagnostic imaging device, including:
a plurality of photodetectors arranged in an array; a plurality of scintillator crystals arranged in an array and optically coupled to the plurality of photodetectors, the photodetector array and the scintillator array being offset from each other such that some of the scintillator crystals are coupled to a different number of photodetectors than other scintillator crystals; and a processor that identifies a scintillator crystal that has been hit by a gamma ray based on an output signal generated by one or more of the plurality of photodetectors optically coupled to the scintillator crystal hit by the gamma ray. 10. The detector array according to claim 9, wherein the length of each side of each scintillator crystal is approximately ½ the length of each side of each photodetector, such that each photodetector is associated with nine scintillator crystals. 11. The detector array according to claim 9, further including:
a plurality of the scintillator crystals arranged in a rectangular grid; a plurality of 2×2 arrays of photodetectors optically coupled to the scintillator crystals in an offset relationship such that in each 2×2 array, such that one of the photodetectors is optically coupled to only one scintillator crystal, one of the photodetectors is optically coupled to two of the scintillator crystals, and two of the photodetectors are optically coupled to four of the scintillator crystals. 12. A method of identifying a scintillator crystal in the detector array of claim 9, including:
detecting light registration from a gamma ray at a first photodetector; determining whether at least a second photodetector, adjacent to the first photodetector, has registered an amount of light equal to the amount of light registered at the first photodetector; performing a table lookup of photodetectors registering substantially equal amounts of light; and identifying a scintillator crystal overlapping all photodetectors registering the substantially equal amount of light as the scintillator crystal that was hit by the gamma ray. 13. A method of identifying a gamma ray hit location on a detector array of claim 9, including:
arranging a plurality of the scintillator crystals in a rectangular grid; optically coupling a plurality of the 2×2 arrays of photodetectors to the scintillator crystals in an offset relationship such that in each 2×2 array, one of the photodetectors is optically coupled to only one scintillator crystal, one of the photodetectors is optically coupled to two of the scintillator crystals, and two of the photodetectors are optically coupled to four of the scintillator crystals. 14. The detector array according to claim 9, further including:
a plurality of the scintillator crystals arranged in a rectangular grid; a plurality of 4×4 arrays of photodetectors optically coupled to the scintillator crystals in an offset relationship. 15. The detector array according to claim 14, further including:
wherein the photodetectors are 1×1 mm2 photodetectors. 16. The detector array according to claim 9, further including:
a plurality of the scintillator crystals arranged in a rectangular grid; and two or more of:
a 4×4 array of photodetectors optically coupled to the scintillator crystals in an offset relationship;
a 2×2 array of photodetectors optically coupled to the scintillator crystals in an offset relationship; and
a 1×1 array of photodetectors optically coupled to the scintillator crystals in an offset relationship. 17. The detector array according to claim 16, further including:
wherein the photodetectors are 1×1 mm2 photodetectors. | When designing detector arrays for diagnostic imaging devices, such as PET or SPECT devices, a virtual detector, or pixel, combines scintillator crystals with photodetectors in ratios that deviate from the conventional 1:1 ratio. For instance, multiple photodetectors can be glued to a single crystal to create a virtual pixel which can be software-based or hardware-based. Light energy and time stamp information for a gamma ray hit on the crystal can be calculated using a virtualizer processor or using a trigger line network and time-to-digital converter logic. Additionally or alternatively, multiple crystals can be associated with each of a plurality of photodetectors. A gamma ray hit on a specific crystal is then determined by a table lookup of adjacent photodetectors that register equal light intensities, and the crystal common to such photodetectors is identified as the location of the hit.1. A virtual pixel array for a diagnostic imaging system, including:
a virtual pixel comprising at least one scintillator crystal; a plurality of photodetectors optically coupled to the at least one scintillator crystal, which generate output signals in response to scintillations in the crystal, wherein the plurality of photodetectors includes 4 photodetectors arranged in a 2×2 array; and a virtualizer that processes the output signals associated with a gamma ray hit on the scintillator crystal as detected by the plurality of photodetectors and calculates a time stamp for the gamma ray hit; a plurality of scintillator crystals, including the at least one scintillator crystal, arranged in a rectangular grid; a plurality of the 2×2 arrays of photodetectors optically coupled to the scintillator crystals in an offset relationship such that in each 2×2 array, one of the photodetectors is optically coupled to only one scintillator crystal, one of the photodetectors is optically coupled to two of the scintillator crystals, and two of the photodetectors are optically coupled to four of the scintillator crystals. 2. The virtual pixel array according to claim 1, wherein the length of each side of each scintillator crystal is approximately ½ the length of each side of each photodetector, such that each photodetector is associated with nine scintillator crystals. 3. A method of identifying a scintillator crystal in the virtual pixel array of claim 1, including:
detecting light registration from a gamma ray at a first photodetector; determining whether at least a second photodetector, adjacent to the first photodetector, has registered an amount of light equal to the amount of light registered at the first photodetector; performing a table lookup of photodetectors registering substantially equal amounts of light; and identifying a scintillator crystal overlapping all photodetectors registering the substantially equal amount of light as the scintillator crystal that was hit by the gamma ray. 4. The virtual pixel array according to claim 1, further including:
one or more of: at least one 4×4 array of photodetectors optically coupled to the scintillator crystals in an offset relationship; and at least one 1×1 array of photodetectors optically coupled to the scintillator crystals in an offset relationship. 5. A method of calculating a time stamp for a virtual pixel, including:
arranging a plurality of scintillator crystals, including the at least one scintillator crystal, in a rectangular grid; optically coupling a plurality of 2×2 arrays of photodetectors to the scintillator crystals in an offset relationship such that in each 2×2 array, one of the photodetectors is optically coupled to only one scintillator crystal, one of the photodetectors is optically coupled to two of the scintillator crystals, and two of the photodetectors are optically coupled to four of the scintillator crystals receiving a gamma ray hit on at least one scintillator crystal of the virtual pixel; evaluating output signals from each of a plurality of photodetectors optically coupled to the at least one scintillator crystal to determine an energy and a photodetector time stamp for each photodetector associated with the gamma ray hit; calculating a total energy of the gamma ray hit by combining the energies detected by the plurality of photodetectors associated with the gamma ray hit; and calculating a time stamp for the gamma ray hit as a function of the photodetector time stamp registered by at least one photodetector in the plurality of photodetectors. 6. The method according to claim 5, wherein the length of each side of each scintillator crystal is approximately ½ the length of each side of each photodetector, such that each photodetector is associated with nine scintillator crystals. 7. The method according to claim 5, further comprising:
detecting light registration from a gamma ray at a first photodetector; determining whether at least a second photodetector, adjacent to the first photodetector, has registered an amount of light equal to the amount of light registered at the first photodetector; performing a table lookup of photodetectors registering substantially equal amounts of light; and identifying a scintillator crystal overlapping all photodetectors registering the substantially equal amount of light as the scintillator crystal that was hit by the gamma ray. 8. The method according to claim 5, further including:
one or more of: optically coupling at least one 4×4 array of photodetectors to the scintillator crystals in an offset relationship; and optically coupling at least one 1×1 array of photodetectors to the scintillator crystals in an offset relationship. 9. A detector array for a diagnostic imaging device, including:
a plurality of photodetectors arranged in an array; a plurality of scintillator crystals arranged in an array and optically coupled to the plurality of photodetectors, the photodetector array and the scintillator array being offset from each other such that some of the scintillator crystals are coupled to a different number of photodetectors than other scintillator crystals; and a processor that identifies a scintillator crystal that has been hit by a gamma ray based on an output signal generated by one or more of the plurality of photodetectors optically coupled to the scintillator crystal hit by the gamma ray. 10. The detector array according to claim 9, wherein the length of each side of each scintillator crystal is approximately ½ the length of each side of each photodetector, such that each photodetector is associated with nine scintillator crystals. 11. The detector array according to claim 9, further including:
a plurality of the scintillator crystals arranged in a rectangular grid; a plurality of 2×2 arrays of photodetectors optically coupled to the scintillator crystals in an offset relationship such that in each 2×2 array, such that one of the photodetectors is optically coupled to only one scintillator crystal, one of the photodetectors is optically coupled to two of the scintillator crystals, and two of the photodetectors are optically coupled to four of the scintillator crystals. 12. A method of identifying a scintillator crystal in the detector array of claim 9, including:
detecting light registration from a gamma ray at a first photodetector; determining whether at least a second photodetector, adjacent to the first photodetector, has registered an amount of light equal to the amount of light registered at the first photodetector; performing a table lookup of photodetectors registering substantially equal amounts of light; and identifying a scintillator crystal overlapping all photodetectors registering the substantially equal amount of light as the scintillator crystal that was hit by the gamma ray. 13. A method of identifying a gamma ray hit location on a detector array of claim 9, including:
arranging a plurality of the scintillator crystals in a rectangular grid; optically coupling a plurality of the 2×2 arrays of photodetectors to the scintillator crystals in an offset relationship such that in each 2×2 array, one of the photodetectors is optically coupled to only one scintillator crystal, one of the photodetectors is optically coupled to two of the scintillator crystals, and two of the photodetectors are optically coupled to four of the scintillator crystals. 14. The detector array according to claim 9, further including:
a plurality of the scintillator crystals arranged in a rectangular grid; a plurality of 4×4 arrays of photodetectors optically coupled to the scintillator crystals in an offset relationship. 15. The detector array according to claim 14, further including:
wherein the photodetectors are 1×1 mm2 photodetectors. 16. The detector array according to claim 9, further including:
a plurality of the scintillator crystals arranged in a rectangular grid; and two or more of:
a 4×4 array of photodetectors optically coupled to the scintillator crystals in an offset relationship;
a 2×2 array of photodetectors optically coupled to the scintillator crystals in an offset relationship; and
a 1×1 array of photodetectors optically coupled to the scintillator crystals in an offset relationship. 17. The detector array according to claim 16, further including:
wherein the photodetectors are 1×1 mm2 photodetectors. | 2,800 |
11,822 | 11,822 | 15,348,459 | 2,814 | A method for forming trench capacitors includes forming a silicon nitride layer over a first region of a semiconductor surface doped a first type and over a second region doped a second type. A patterned photoresist layer is directly formed on the silicon nitride layer. An etch forms a plurality of deep trenches (DTs) within the first region. A liner oxide is formed that lines the DTs. The silicon nitride layer is etched forming an opening through the silicon nitride layer that is at least as large in area as the area of an opening in the semiconductor surface of the DT below the silicon nitride layer. The liner oxide is removed, a dielectric layer(s) on a surface of the DTs is formed, a top plate material layer is deposited to fill the DTs, and the top plate material layer is removed beyond the DT to form a top plate. | 1. A method for forming trench capacitors in a semiconductor surface of an integrated circuit (IC), comprising:
forming a silicon nitride layer over a first region of said semiconductor surface that has a doping of a first type and over a second region having a doping of a second type; forming a patterned photoresist layer directly on said silicon nitride layer; etching within said first region to form a plurality of deep trenches (DTs); forming a liner oxide that lines said DTs; wet etching said silicon nitride layer, wherein after said wet etching, an opening through said silicon nitride layer is at least as large in area as an area of an opening in said semiconductor surface of said DT below said silicon nitride layer; removing said liner oxide; forming at least one dielectric layer on a surface of said DTs; depositing a top plate material layer on said dielectric layer to fill said DTs, and removing said top plate material layer beyond said DTs to form a top plate. 2. The method of claim 1, wherein said top plate material layer comprises polysilicon. 3. The method of claim 2, wherein said depositing comprises in-situ doped (ISD) depositing. 4. The method of claim 1, wherein said removing said top plate material layer comprises chemical mechanical polishing (CMP). 5. The method of claim 1, wherein said top plate material layer comprises polysilicon, and wherein said top plate is exclusive of any polysilicon interface. 6. The method of claim 5, wherein a percentage of voids at a surface of said top plate with a size larger than 0.1 μm is less than or equal to 1%. 7. The method of claim 1, wherein a depth of said DTs is between 5 μm and 20 μm. 8. The method of claim 1, further comprising forming shallow trench isolation (STI) or local oxidation of silicon (LOCOS) regions at an upper surface of said semiconductor surface where said dielectric layer intersects said upper surface. 9. The method of claim 1, wherein said trench capacitors have an area on said IC only sufficient to provide a single contact for connection to said top plate. 10. The method of claim 1, wherein said dielectric layer comprises silicon nitride. 11. A trench capacitor formed in a semiconductor surface of an integrated circuit (IC), said trench capacitor comprising:
a deep well structure formed in said semiconductor surface doped with a first type of dopant, said deep well structure forming a first plate of said trench capacitor; a plurality of deep trenches (DTs) formed in said deep well structure and filled with a top plate material layer that provides a top plate; at least one dielectric layer between said top plate material layer and said deep well structure, and wherein a percentage of voids in a surface of said top plate with a size larger than 0.1 μm is 1% or less. 12. The trench capacitor of claim 11, wherein said top plate material layer comprises doped polysilicon. 13. The trench capacitor of claim 12, wherein said top plate is exclusive of any polysilicon interface. 14. The trench capacitor of claim 11, wherein a depth of said DTs is between 5 μm and 20 μm. 15. The trench capacitor of claim 11, further comprising shallow trench isolation (STI) or local oxidation of silicon (LOCOS) regions at an upper surface of said semiconductor surface where said dielectric layer intersects said upper surface. 16. The trench capacitor of claim 11, wherein said top plate of said trench capacitors each has a single contact for connection thereto. 17. The trench capacitor of claim 11, wherein said dielectric layer comprises silicon nitride. | A method for forming trench capacitors includes forming a silicon nitride layer over a first region of a semiconductor surface doped a first type and over a second region doped a second type. A patterned photoresist layer is directly formed on the silicon nitride layer. An etch forms a plurality of deep trenches (DTs) within the first region. A liner oxide is formed that lines the DTs. The silicon nitride layer is etched forming an opening through the silicon nitride layer that is at least as large in area as the area of an opening in the semiconductor surface of the DT below the silicon nitride layer. The liner oxide is removed, a dielectric layer(s) on a surface of the DTs is formed, a top plate material layer is deposited to fill the DTs, and the top plate material layer is removed beyond the DT to form a top plate.1. A method for forming trench capacitors in a semiconductor surface of an integrated circuit (IC), comprising:
forming a silicon nitride layer over a first region of said semiconductor surface that has a doping of a first type and over a second region having a doping of a second type; forming a patterned photoresist layer directly on said silicon nitride layer; etching within said first region to form a plurality of deep trenches (DTs); forming a liner oxide that lines said DTs; wet etching said silicon nitride layer, wherein after said wet etching, an opening through said silicon nitride layer is at least as large in area as an area of an opening in said semiconductor surface of said DT below said silicon nitride layer; removing said liner oxide; forming at least one dielectric layer on a surface of said DTs; depositing a top plate material layer on said dielectric layer to fill said DTs, and removing said top plate material layer beyond said DTs to form a top plate. 2. The method of claim 1, wherein said top plate material layer comprises polysilicon. 3. The method of claim 2, wherein said depositing comprises in-situ doped (ISD) depositing. 4. The method of claim 1, wherein said removing said top plate material layer comprises chemical mechanical polishing (CMP). 5. The method of claim 1, wherein said top plate material layer comprises polysilicon, and wherein said top plate is exclusive of any polysilicon interface. 6. The method of claim 5, wherein a percentage of voids at a surface of said top plate with a size larger than 0.1 μm is less than or equal to 1%. 7. The method of claim 1, wherein a depth of said DTs is between 5 μm and 20 μm. 8. The method of claim 1, further comprising forming shallow trench isolation (STI) or local oxidation of silicon (LOCOS) regions at an upper surface of said semiconductor surface where said dielectric layer intersects said upper surface. 9. The method of claim 1, wherein said trench capacitors have an area on said IC only sufficient to provide a single contact for connection to said top plate. 10. The method of claim 1, wherein said dielectric layer comprises silicon nitride. 11. A trench capacitor formed in a semiconductor surface of an integrated circuit (IC), said trench capacitor comprising:
a deep well structure formed in said semiconductor surface doped with a first type of dopant, said deep well structure forming a first plate of said trench capacitor; a plurality of deep trenches (DTs) formed in said deep well structure and filled with a top plate material layer that provides a top plate; at least one dielectric layer between said top plate material layer and said deep well structure, and wherein a percentage of voids in a surface of said top plate with a size larger than 0.1 μm is 1% or less. 12. The trench capacitor of claim 11, wherein said top plate material layer comprises doped polysilicon. 13. The trench capacitor of claim 12, wherein said top plate is exclusive of any polysilicon interface. 14. The trench capacitor of claim 11, wherein a depth of said DTs is between 5 μm and 20 μm. 15. The trench capacitor of claim 11, further comprising shallow trench isolation (STI) or local oxidation of silicon (LOCOS) regions at an upper surface of said semiconductor surface where said dielectric layer intersects said upper surface. 16. The trench capacitor of claim 11, wherein said top plate of said trench capacitors each has a single contact for connection thereto. 17. The trench capacitor of claim 11, wherein said dielectric layer comprises silicon nitride. | 2,800 |
11,823 | 11,823 | 15,871,586 | 2,816 | A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer. | 1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including an edge support ring around a perimeter of the semiconductor wafer; forming a conductive layer over a surface of the semiconductor wafer; providing a first stencil including a plurality of first openings; and disposing the first stencil over the edge support ring with the first openings extending below a top surface of the edge support ring to align with the conductive layer 2. The method of claim 1, further including dispersing a plurality of bumps over the first stencil to occupy the first openings over the conductive layer. 3. The method of claim 2, further including:
bonding the bumps to the conductive layer; and removing the first stencil. 4. The method of claim 1, wherein the first stencil includes a horizontal portion containing the first openings and a vertical extension disposed over the edge support ring and extending to the horizontal portion of the first stencil. 5. The method of claim 1, further including:
providing a second stencil including a plurality of second openings; disposing a second stencil over the edge support ring with the second openings extending to and aligned with the conductive layer; and depositing a flux material in the second openings over the conductive layer. 6. The method of claim 1, wherein the first stencil includes a notch disposed over the edge support ring. 7. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including a conductive layer formed over a surface of the semiconductor wafer and an edge support ring around a perimeter of the semiconductor wafer; providing a first stencil including a plurality of first openings; and disposing the first stencil over the edge support ring with the first openings extending to the conductive layer. 8. The method of claim 7, further including dispersing a plurality of bumps over the first stencil to occupy the first openings over the conductive layer. 9. The method of claim 8, further including:
bonding the bumps to the conductive layer; and removing the first stencil. 10. The method of claim 7, wherein the first stencil includes a horizontal portion containing the first openings and a vertical extension disposed over the edge support ring and extending to the horizontal portion of the first stencil. 11. The method of claim 7, further including:
providing a second stencil including a plurality of second openings; disposing a second stencil over the edge support ring with the second openings extending to and aligned with the conductive layer; and depositing a flux material in the second openings over the conductive layer. 12. The method of claim 7, wherein the first stencil includes a notch disposed over the edge support ring. 13. The method of claim 7, wherein the first stencil includes a horizontal portion and a step-down portion extending from a top surface of the edge support ring to the horizontal portion of the first stencil. 14. A semiconductor wafer, comprising:
a semiconductor wafer including an edge support ring around a perimeter of the semiconductor wafer and a conductive layer formed over a surface of the semiconductor wafer; and a first stencil including a plurality of first openings, wherein the first stencil is disposed over the edge support ring with the first openings extending to the conductive layer. 15. The semiconductor wafer of claim 14, further including a plurality of bumps disposed over the first stencil to occupy the first openings over the conductive layer. 16. The semiconductor wafer of claim 14, wherein the first stencil includes a horizontal portion containing the first openings and a vertical extension disposed over the edge support ring and extending to the horizontal portion of the first stencil. 17. The semiconductor wafer of claim 14, further including:
a second stencil including a plurality of second openings, wherein the second stencil is disposed over the edge support ring with the second openings extending to and aligned with the conductive layer; and a flux material deposited in the second openings over the conductive layer. 18. The semiconductor wafer of claim 14, wherein the second stencil includes a horizontal portion and a sloped portion extending from a top surface of the edge support ring to the horizontal portion of the second stencil. 19. The semiconductor wafer of claim 14, wherein the first stencil includes a notch disposed over the edge support ring. 20. The semiconductor wafer of claim 14, wherein the first stencil includes a horizontal portion and a step-down portion extending from a top surface of the edge support ring to the horizontal portion of the first stencil. | A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including an edge support ring around a perimeter of the semiconductor wafer; forming a conductive layer over a surface of the semiconductor wafer; providing a first stencil including a plurality of first openings; and disposing the first stencil over the edge support ring with the first openings extending below a top surface of the edge support ring to align with the conductive layer 2. The method of claim 1, further including dispersing a plurality of bumps over the first stencil to occupy the first openings over the conductive layer. 3. The method of claim 2, further including:
bonding the bumps to the conductive layer; and removing the first stencil. 4. The method of claim 1, wherein the first stencil includes a horizontal portion containing the first openings and a vertical extension disposed over the edge support ring and extending to the horizontal portion of the first stencil. 5. The method of claim 1, further including:
providing a second stencil including a plurality of second openings; disposing a second stencil over the edge support ring with the second openings extending to and aligned with the conductive layer; and depositing a flux material in the second openings over the conductive layer. 6. The method of claim 1, wherein the first stencil includes a notch disposed over the edge support ring. 7. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including a conductive layer formed over a surface of the semiconductor wafer and an edge support ring around a perimeter of the semiconductor wafer; providing a first stencil including a plurality of first openings; and disposing the first stencil over the edge support ring with the first openings extending to the conductive layer. 8. The method of claim 7, further including dispersing a plurality of bumps over the first stencil to occupy the first openings over the conductive layer. 9. The method of claim 8, further including:
bonding the bumps to the conductive layer; and removing the first stencil. 10. The method of claim 7, wherein the first stencil includes a horizontal portion containing the first openings and a vertical extension disposed over the edge support ring and extending to the horizontal portion of the first stencil. 11. The method of claim 7, further including:
providing a second stencil including a plurality of second openings; disposing a second stencil over the edge support ring with the second openings extending to and aligned with the conductive layer; and depositing a flux material in the second openings over the conductive layer. 12. The method of claim 7, wherein the first stencil includes a notch disposed over the edge support ring. 13. The method of claim 7, wherein the first stencil includes a horizontal portion and a step-down portion extending from a top surface of the edge support ring to the horizontal portion of the first stencil. 14. A semiconductor wafer, comprising:
a semiconductor wafer including an edge support ring around a perimeter of the semiconductor wafer and a conductive layer formed over a surface of the semiconductor wafer; and a first stencil including a plurality of first openings, wherein the first stencil is disposed over the edge support ring with the first openings extending to the conductive layer. 15. The semiconductor wafer of claim 14, further including a plurality of bumps disposed over the first stencil to occupy the first openings over the conductive layer. 16. The semiconductor wafer of claim 14, wherein the first stencil includes a horizontal portion containing the first openings and a vertical extension disposed over the edge support ring and extending to the horizontal portion of the first stencil. 17. The semiconductor wafer of claim 14, further including:
a second stencil including a plurality of second openings, wherein the second stencil is disposed over the edge support ring with the second openings extending to and aligned with the conductive layer; and a flux material deposited in the second openings over the conductive layer. 18. The semiconductor wafer of claim 14, wherein the second stencil includes a horizontal portion and a sloped portion extending from a top surface of the edge support ring to the horizontal portion of the second stencil. 19. The semiconductor wafer of claim 14, wherein the first stencil includes a notch disposed over the edge support ring. 20. The semiconductor wafer of claim 14, wherein the first stencil includes a horizontal portion and a step-down portion extending from a top surface of the edge support ring to the horizontal portion of the first stencil. | 2,800 |
11,824 | 11,824 | 15,358,441 | 2,838 | The present disclosure is directed to an electrosurgical generator including a resonant inverter having an H-bridge and a tank. A sensor array measures at least one property of the tank. A pulse width modulation (PWM) controller outputs a first PWM timing signal and a second PWM timing signal to the H-bridge. The PWM controller controls a dead-time between the first PWM timing signal and the second PWM timing signal based on the at least one property measured by the sensor array. | 1. An electrosurgical generator comprising:
a resonant inverter including an H-bridge and a tank; a sensor array configured to measure at least one property of the tank; a pulse width modulation (PWM) controller configured to output a first PWM timing signal and a second PWM timing signal to the H-bridge, wherein the PWM controller controls a dead-time between the first PWM timing signal and the second PWM timing signal based on the at least one property measured by the sensor array. 2. The electrosurgical generator of claim 1, wherein the sensor array measures an input voltage, an output voltage and an output current and the PWM controller uses the input voltage, the output voltage, and the output current to determine the dead-time. 3. The electrosurgical generator of claim 2, wherein the PWM controller calculates an efficiency measurement based on the input voltage and the output voltage. 4. The electrosurgical generator of claim 2, wherein the PWM controller calculates a load measurement based on the output voltage and the output current. 5. The electrosurgical generator of claim 3, wherein the PWM controller controls the dead-time based on the efficiency measurement. 6. The electrosurgical generator of claim 1, wherein the PWM controller includes a memory having a look-up table stored thereon. 7. The electrosurgical generator of claim 6, wherein the PWM controller determines a phase-shift of the H-bridge. 8. The electrosurgical generator of claim 7, wherein the sensor array measures an output voltage and an output current and the processor determines a load measurement based the output voltage and the output current. 9. The electrosurgical generator of claim 8, wherein the PWM controller determines the dead-time by comparing the phase-shift and the load measurement to data in the look-up table. 10. A method for optimizing a dead-time for a field effect transistor (FET) transition in a resonant inverter, the method comprising:
initializing a dead-time for the FET transition; determining a first efficiency measurement of the resonant inverter; increasing a dead-time of the FET transition; determining a second efficiency measurement of the resonant inverter; and adjusting the dead-time based on a comparison between the first efficiency measurement and the second efficiency measurement. 11. The method according to claim 10, wherein if the second efficiency measurement is greater than the first efficiency measurement by a predetermined percentage, the dead time is increased. 12. The method according to claim 10, wherein if the second efficiency measurement is less than the first efficiency measurement by a predetermined percentage, the dead time is decreased. 13. A method for optimizing a dead-time for a field effect transistor (FET) transition in a resonant inverter including an H-bridge and a tank, the method comprising:
determining a phase shift between a plurality of pulse width modulated signals applied to the H-bridge; determining a load measurement of the tank; comparing the phase shift and the load measurement to a look-up table; determining an optimal dead-time based on a result of the comparison between the phase shift and the load measurement to the look-up table; and adjusting the dead-time for the FET transition based on the optimal dead-time. | The present disclosure is directed to an electrosurgical generator including a resonant inverter having an H-bridge and a tank. A sensor array measures at least one property of the tank. A pulse width modulation (PWM) controller outputs a first PWM timing signal and a second PWM timing signal to the H-bridge. The PWM controller controls a dead-time between the first PWM timing signal and the second PWM timing signal based on the at least one property measured by the sensor array.1. An electrosurgical generator comprising:
a resonant inverter including an H-bridge and a tank; a sensor array configured to measure at least one property of the tank; a pulse width modulation (PWM) controller configured to output a first PWM timing signal and a second PWM timing signal to the H-bridge, wherein the PWM controller controls a dead-time between the first PWM timing signal and the second PWM timing signal based on the at least one property measured by the sensor array. 2. The electrosurgical generator of claim 1, wherein the sensor array measures an input voltage, an output voltage and an output current and the PWM controller uses the input voltage, the output voltage, and the output current to determine the dead-time. 3. The electrosurgical generator of claim 2, wherein the PWM controller calculates an efficiency measurement based on the input voltage and the output voltage. 4. The electrosurgical generator of claim 2, wherein the PWM controller calculates a load measurement based on the output voltage and the output current. 5. The electrosurgical generator of claim 3, wherein the PWM controller controls the dead-time based on the efficiency measurement. 6. The electrosurgical generator of claim 1, wherein the PWM controller includes a memory having a look-up table stored thereon. 7. The electrosurgical generator of claim 6, wherein the PWM controller determines a phase-shift of the H-bridge. 8. The electrosurgical generator of claim 7, wherein the sensor array measures an output voltage and an output current and the processor determines a load measurement based the output voltage and the output current. 9. The electrosurgical generator of claim 8, wherein the PWM controller determines the dead-time by comparing the phase-shift and the load measurement to data in the look-up table. 10. A method for optimizing a dead-time for a field effect transistor (FET) transition in a resonant inverter, the method comprising:
initializing a dead-time for the FET transition; determining a first efficiency measurement of the resonant inverter; increasing a dead-time of the FET transition; determining a second efficiency measurement of the resonant inverter; and adjusting the dead-time based on a comparison between the first efficiency measurement and the second efficiency measurement. 11. The method according to claim 10, wherein if the second efficiency measurement is greater than the first efficiency measurement by a predetermined percentage, the dead time is increased. 12. The method according to claim 10, wherein if the second efficiency measurement is less than the first efficiency measurement by a predetermined percentage, the dead time is decreased. 13. A method for optimizing a dead-time for a field effect transistor (FET) transition in a resonant inverter including an H-bridge and a tank, the method comprising:
determining a phase shift between a plurality of pulse width modulated signals applied to the H-bridge; determining a load measurement of the tank; comparing the phase shift and the load measurement to a look-up table; determining an optimal dead-time based on a result of the comparison between the phase shift and the load measurement to the look-up table; and adjusting the dead-time for the FET transition based on the optimal dead-time. | 2,800 |
11,825 | 11,825 | 15,651,295 | 2,844 | The invention relates to a pivot arbor comprising a metal pivot ( 3 ) at each of its ends. The metal is a non-magnetic aluminium alloy in order to limit its sensitivity to magnetic fields, and at least the outer surface ( 5 ) of one of the two pivots ( 3 ) is deep-hardened to a predetermined depth with respect to the rest of the arbor to harden the pivot or pivots ( 3 ). | 1. A pivot arbor for a timepiece movement comprising at least one metal pivot at at least one of the ends thereof, wherein the metal is a non-magnetic aluminium alloy so as to limit the sensitivity of the pivot to magnetic fields, and wherein at least the outer surface of said pivot is deep-hardened to a predetermined depth relative to the core of the pivot arbor. 2. The pivot arbor according to claim 1, wherein the predetermined depth represents between 5% and 40% of the total diameter (d) of the pivot. 3. The pivot arbor according to claim 1, wherein the deep-hardened outer surface comprises diffused atoms of at least one chemical element. 4. The pivot arbor according to claim 1, wherein the deep-hardened outer surface has a hardness of more than 600 HV. 5. The pivot arbor according to claim 1, wherein the non-magnetic aluminium alloy is chosen from the group consisting of an aluminium-copper-lead alloy, an aluminium-silicon-magnesium-manganese alloy, and an aluminium-zinc-magnesium-copper alloy. 6. The pivot arbor according to claim 1, wherein said outer surface of said pivot has no hardening layer directly deposited on said outer surface. 7. The pivot arbor according to claim 1, wherein at least the outer surface of said pivot is rolled. 8. The pivot arbor according to claim 1, wherein the pivot arbor has two pivots. 9. A movement for a timepiece comprising a pivot arbor, wherein said pivot arbor comprises at least one metal pivot at at least one of the ends thereof, the metal being a non-magnetic aluminium alloy so as to limit the sensitivity of the pivot to magnetic fields, and wherein at least the outer surface of said pivot is deep-hardened to a predetermined depth relative to the core of the pivot arbor. 10. A movement for a timepiece wherein the movement comprises a balance staff, a pallet staff and/or an escape pinion comprising a pivot arbor comprising at least one metal pivot at at least one of the ends thereof, the metal being a non-magnetic aluminium alloy so as to limit the sensitivity of the pivot to magnetic fields, and wherein at least the outer surface of said pivot is deep-hardened to a predetermined depth relative to the core of the pivot arbor. 11. A method for fabricating a pivot arbor for a timepiece movement comprising the following steps:
a) forming a pivot arbor comprising at least one metal pivot at one of the ends thereof, said metal being a non-magnetic aluminium alloy, to limit the sensitivity thereof to magnetic fields; b) diffusing atoms by an ion implantation process to a predetermined depth in at least the outer surface of said pivot in order to deep-harden the pivot arbor in the main areas of stress while maintaining a high tenacity. 12. The method according to claim 11, wherein the predetermined depth represents between 5% and 40% of the total diameter (d) of the pivot. 13. The method according to claim 11, wherein the diffusion step comprises the diffusion of atoms of at least one chemical element. 14. The method according to claim 11, wherein the method does not comprise any step of depositing a hardening layer directly on the outer surface of the pivot. 15. The method according to claim 11, wherein the pivot is subjected to a rolling/polishing step after step b). | The invention relates to a pivot arbor comprising a metal pivot ( 3 ) at each of its ends. The metal is a non-magnetic aluminium alloy in order to limit its sensitivity to magnetic fields, and at least the outer surface ( 5 ) of one of the two pivots ( 3 ) is deep-hardened to a predetermined depth with respect to the rest of the arbor to harden the pivot or pivots ( 3 ).1. A pivot arbor for a timepiece movement comprising at least one metal pivot at at least one of the ends thereof, wherein the metal is a non-magnetic aluminium alloy so as to limit the sensitivity of the pivot to magnetic fields, and wherein at least the outer surface of said pivot is deep-hardened to a predetermined depth relative to the core of the pivot arbor. 2. The pivot arbor according to claim 1, wherein the predetermined depth represents between 5% and 40% of the total diameter (d) of the pivot. 3. The pivot arbor according to claim 1, wherein the deep-hardened outer surface comprises diffused atoms of at least one chemical element. 4. The pivot arbor according to claim 1, wherein the deep-hardened outer surface has a hardness of more than 600 HV. 5. The pivot arbor according to claim 1, wherein the non-magnetic aluminium alloy is chosen from the group consisting of an aluminium-copper-lead alloy, an aluminium-silicon-magnesium-manganese alloy, and an aluminium-zinc-magnesium-copper alloy. 6. The pivot arbor according to claim 1, wherein said outer surface of said pivot has no hardening layer directly deposited on said outer surface. 7. The pivot arbor according to claim 1, wherein at least the outer surface of said pivot is rolled. 8. The pivot arbor according to claim 1, wherein the pivot arbor has two pivots. 9. A movement for a timepiece comprising a pivot arbor, wherein said pivot arbor comprises at least one metal pivot at at least one of the ends thereof, the metal being a non-magnetic aluminium alloy so as to limit the sensitivity of the pivot to magnetic fields, and wherein at least the outer surface of said pivot is deep-hardened to a predetermined depth relative to the core of the pivot arbor. 10. A movement for a timepiece wherein the movement comprises a balance staff, a pallet staff and/or an escape pinion comprising a pivot arbor comprising at least one metal pivot at at least one of the ends thereof, the metal being a non-magnetic aluminium alloy so as to limit the sensitivity of the pivot to magnetic fields, and wherein at least the outer surface of said pivot is deep-hardened to a predetermined depth relative to the core of the pivot arbor. 11. A method for fabricating a pivot arbor for a timepiece movement comprising the following steps:
a) forming a pivot arbor comprising at least one metal pivot at one of the ends thereof, said metal being a non-magnetic aluminium alloy, to limit the sensitivity thereof to magnetic fields; b) diffusing atoms by an ion implantation process to a predetermined depth in at least the outer surface of said pivot in order to deep-harden the pivot arbor in the main areas of stress while maintaining a high tenacity. 12. The method according to claim 11, wherein the predetermined depth represents between 5% and 40% of the total diameter (d) of the pivot. 13. The method according to claim 11, wherein the diffusion step comprises the diffusion of atoms of at least one chemical element. 14. The method according to claim 11, wherein the method does not comprise any step of depositing a hardening layer directly on the outer surface of the pivot. 15. The method according to claim 11, wherein the pivot is subjected to a rolling/polishing step after step b). | 2,800 |
11,826 | 11,826 | 15,261,978 | 2,833 | A switch assembly includes a switch body defining a switch opening, a dome switch positioned in the switch opening, a film attached to a surface of the switch body and covering the switch opening, and a protrusion extending from the film in an area above the switch opening. The protrusion is configured to transfer a force from a keycap of a key to the dome switch when the keycap is depressed. The dome switch may include an upper dome below the film and a lower dome below the upper dome. | 1. A switch assembly, comprising:
a switch body defining a switch opening; a dome switch positioned in the switch opening; a film attached to the switch body and covering the switch opening; and a protrusion extending from the film in an area above the switch opening; wherein the protrusion is configured to transfer a force from a keycap of a key to the dome switch when the keycap is depressed. 2. The switch assembly of claim 1, wherein:
the switch assembly is one of a group of switch assemblies of a keyboard, the keyboard comprising:
a keyboard base; and
a group of keycaps movably supported relative to the keyboard base, wherein the keycap is one of the group of keycaps;
each respective switch assembly of the group of switch assemblies is coupled to the keyboard base and is positioned under a respective keycap of the group of keycaps. 3. The switch assembly of claim 2, wherein:
the switch body is configured to receive light from a light source; the switch body transmits the light to the film; and the film disperses the light toward the respective keycap of the keyboard. 4. The switch assembly of claim 3, wherein the film is substantially light transmissive for light received from below the film from the switch body and substantially reflective for light received from above the film. 5. The switch assembly of claim 1, further comprising a support mechanism movably supporting the keycap relative to the keyboard base. 6. The switch assembly of claim 1, wherein:
the film is formed from an elastomeric material; and the protrusion is formed from a material that is different from the elastomeric material. 7. The switch assembly of claim 6, wherein the protrusion is fused to the film. 8. The switch assembly of claim 1, wherein the film is directly adjacent to a top of the dome switch. 9. A key, comprising:
a switch assembly, comprising:
a body defining a switch opening:
a flexible cover joined to the body; and
an actuation pad on a surface of the flexible cover; and
a keycap positioned above the switch assembly and operative to move from a first position to a second position; wherein in the first position, the flexible cover is in a substantially undeformed state; and in the second position, the flexible cover is deformed by the keycap. 10. The key of claim 9, wherein the keycap comprises a contact protrusion configured to contact the actuation pad when the keycap is in the second position. 11. The key of claim 9, wherein the switch opening includes a recess formed into a wall of the switch opening. 12. The key of claim 11, further comprising:
a dome switch positioned within the switch opening; wherein a portion of the dome switch is received in the recess. 13. The key of claim 12, wherein the dome switch comprises:
an upper dome positioned adjacent the actuation pad; and a lower dome disposed below the upper dome; wherein the actuation pad deforms the upper dome when the keycap is in the second position. 14. The key of claim 13, wherein the upper dome completes an electrical connection with the lower dome when the keycap is in the second position. 15. The key of claim 12, wherein the dome switch comprises a dome protrusion on a surface of the dome switch. 16. The key of claim 15, wherein:
the actuation pad is configured to deform the dome switch when the keycap is moved to the second position; and the dome protrusion is configured to contact an electrical terminal below the dome switch when the dome switch is deformed. 17. A method of forming a switch, comprising:
attaching a cover member comprising an actuation pad to a switch body that defines a switch opening; and positioning a dome switch within the switch opening such that the actuation pad is aligned with an input surface of the dome switch. 18. The method of claim 17, further comprising forming the cover member, wherein forming the cover member comprises attaching the actuation pad to a film. 19. The method of claim 18, wherein the operation of attaching the actuation pad to the film comprises laser welding the actuation pad to the film. 20. The method of claim 18, wherein the operation of attaching the cover member to the switch body comprises laser welding the film to the switch body around a perimeter of the switch body. | A switch assembly includes a switch body defining a switch opening, a dome switch positioned in the switch opening, a film attached to a surface of the switch body and covering the switch opening, and a protrusion extending from the film in an area above the switch opening. The protrusion is configured to transfer a force from a keycap of a key to the dome switch when the keycap is depressed. The dome switch may include an upper dome below the film and a lower dome below the upper dome.1. A switch assembly, comprising:
a switch body defining a switch opening; a dome switch positioned in the switch opening; a film attached to the switch body and covering the switch opening; and a protrusion extending from the film in an area above the switch opening; wherein the protrusion is configured to transfer a force from a keycap of a key to the dome switch when the keycap is depressed. 2. The switch assembly of claim 1, wherein:
the switch assembly is one of a group of switch assemblies of a keyboard, the keyboard comprising:
a keyboard base; and
a group of keycaps movably supported relative to the keyboard base, wherein the keycap is one of the group of keycaps;
each respective switch assembly of the group of switch assemblies is coupled to the keyboard base and is positioned under a respective keycap of the group of keycaps. 3. The switch assembly of claim 2, wherein:
the switch body is configured to receive light from a light source; the switch body transmits the light to the film; and the film disperses the light toward the respective keycap of the keyboard. 4. The switch assembly of claim 3, wherein the film is substantially light transmissive for light received from below the film from the switch body and substantially reflective for light received from above the film. 5. The switch assembly of claim 1, further comprising a support mechanism movably supporting the keycap relative to the keyboard base. 6. The switch assembly of claim 1, wherein:
the film is formed from an elastomeric material; and the protrusion is formed from a material that is different from the elastomeric material. 7. The switch assembly of claim 6, wherein the protrusion is fused to the film. 8. The switch assembly of claim 1, wherein the film is directly adjacent to a top of the dome switch. 9. A key, comprising:
a switch assembly, comprising:
a body defining a switch opening:
a flexible cover joined to the body; and
an actuation pad on a surface of the flexible cover; and
a keycap positioned above the switch assembly and operative to move from a first position to a second position; wherein in the first position, the flexible cover is in a substantially undeformed state; and in the second position, the flexible cover is deformed by the keycap. 10. The key of claim 9, wherein the keycap comprises a contact protrusion configured to contact the actuation pad when the keycap is in the second position. 11. The key of claim 9, wherein the switch opening includes a recess formed into a wall of the switch opening. 12. The key of claim 11, further comprising:
a dome switch positioned within the switch opening; wherein a portion of the dome switch is received in the recess. 13. The key of claim 12, wherein the dome switch comprises:
an upper dome positioned adjacent the actuation pad; and a lower dome disposed below the upper dome; wherein the actuation pad deforms the upper dome when the keycap is in the second position. 14. The key of claim 13, wherein the upper dome completes an electrical connection with the lower dome when the keycap is in the second position. 15. The key of claim 12, wherein the dome switch comprises a dome protrusion on a surface of the dome switch. 16. The key of claim 15, wherein:
the actuation pad is configured to deform the dome switch when the keycap is moved to the second position; and the dome protrusion is configured to contact an electrical terminal below the dome switch when the dome switch is deformed. 17. A method of forming a switch, comprising:
attaching a cover member comprising an actuation pad to a switch body that defines a switch opening; and positioning a dome switch within the switch opening such that the actuation pad is aligned with an input surface of the dome switch. 18. The method of claim 17, further comprising forming the cover member, wherein forming the cover member comprises attaching the actuation pad to a film. 19. The method of claim 18, wherein the operation of attaching the actuation pad to the film comprises laser welding the actuation pad to the film. 20. The method of claim 18, wherein the operation of attaching the cover member to the switch body comprises laser welding the film to the switch body around a perimeter of the switch body. | 2,800 |
11,827 | 11,827 | 14,905,400 | 2,872 | A translucent construction element comprising a layer of translucent substrate, which contains a surface structured with nanoplanes of inclined angle relative to the substrate plane, and coated with an interrupted metallic layer covering at least a part of said nanoplanes, is characterized by a high density of interruptions in the metallic layer of low thickness; the periodicity of interruptions in the metallic layer generally is from the range 50 to 1000 nm and the thickness of the metallic layer typically is from the range 1 to 50 nm. The construction element may be integrated, for example, into windows, plastic films or sheets or glazings, especially for the purpose of light management. | 1.-16. (canceled) 17. A translucent construction element comprising a layer of translucent substrate, which contains a surface structured with nanoplanes of inclined angle relative to the substrate plane, and coated with an interrupted metallic layer covering at least a part of said nanoplanes, characterized in that the thickness of the metallic layer is from the range 1 to 50 nm and the periodicity of interruptions in the metallic layer is from the range 50 to 1000 nm 18. A translucent construction element comprising a layer of translucent substrate, which contains a surface structured with nanoplanes of inclined angle relative to the substrate plane, and coated with an interrupted metallic layer covering at least a part of said nanoplanes, characterized in that the periodicity of interruptions in the metallic layer is from the range 50 to less than 500 nm, and the thickness of the metallic layer is from the range 1 to 75 nm. 19. The translucent construction element of claim 17, wherein the element is a facade element, or is transparent and is a window pane. 20. The translucent construction element of claim 17, wherein the nanoplanes on the substrate surface are provided in form of a grating of depth from the range 30 to 1000 nm, which grating is of sinusoidal, trapezoidal, triangular or rectangular cross section. 21. The translucent construction element of claim 20, wherein the element is integrated in a building or vehicle with its grating lines aligned horizontally. 22. A device comprising an interrupted metallic layer on the surface of a transparent substrate, characterized in that the surface is structured with nanoplanes of inclined angle relative to the substrate plane and carrying a metal coating on at least a part of said nanoplanes, where the periodicity of interruptions in the metallic layer is from the range 50 to 1000 nm and the thickness of the metal coating is from the range 1 to 50 nm. 23. The device of claim 22, wherein the inclined angle relative to the substrate plane is from the range 10 to 90°. 24. Device of claim 22, wherein the nanoplanes of inclined angle relative to the substrate plane are provided in form of a grating of periodicity from the range 50 to 1000 nm and of depth from the range 30 to 1000 nm, which grating is of sinusoidal, trapezoidal, triangular or rectangular cross section. 25. The translucent construction element according to claim 17, wherein the metallic layer is covered by a transparent medium in form of an encapsulating layer. 26. The translucent construction element according to claim 17, comprising between substrate and metallic layer and/or between the metallic layer and encapsulating layer one or more further layers selected from underlayers of enhancement materials and cover layers. 27. The translucent construction element according to claim 17, wherein the metallic layer contains a metal selected from the group consisting of silver, aluminum, gold, copper, and platinum. 28. The translucent construction element according to claim 17, wherein the substrate, an optional encapsulating layer(s) and an optional cover layer(s) are glass or polymeric materials selected from the group consisting of thermoplastic polymers and UV-cured polymers such as acrylic polymers, polycarbonates, polyesters, polyvinylbutyrate, polyolefines, polyetherimides, polyetherketones, polyethylene naphthalates, polyimides, polystyrenes, polyoxymethylene, polyvinylchloride, low refractive index composite materials, hybrid polymers, radiation-curable compositions, and combinations thereof. 29. A window pane comprising the translucent construction element according to claim 17, wherein the substrate comprises a flat or bent polymer film or sheet, or glass sheet, or a polymer film or sheet and a glass sheet. 30. The window pane of claim 29 comprising a glass sheet carrying the element including the interrupted metallic layer on at least a part of its surface, wherein the metallic structures are directly attached to the glass surface or are embedded in a transparent medium comprising the substrate and the encapsulating medium, where substrate and the encapsulating medium are selected from the group consisting of thermoplastic polymers, UV-cured polymers such as acrylic polymers, polycarbonates, polyesters, polyvinylbutyrate, polyolefines, polyetherimides, polyetherketones, polyethylene naphthalates, polyimides, polystyrenes, polyoxymethylene, polyvinylchloride, low refractive index composite materials, hybrid polymers, radiation-curable compositions, and combinations thereof. 31. A method for reducing the transmission of solar light through a transparent element, which method comprises integrating the translucent construction element according to claim 17 into said transparent element. 32. A method for seasonal heat and/or light management, comprising incorporating the translucent construction element according to claim 17into a window into the interior space of a building or vehicle. | A translucent construction element comprising a layer of translucent substrate, which contains a surface structured with nanoplanes of inclined angle relative to the substrate plane, and coated with an interrupted metallic layer covering at least a part of said nanoplanes, is characterized by a high density of interruptions in the metallic layer of low thickness; the periodicity of interruptions in the metallic layer generally is from the range 50 to 1000 nm and the thickness of the metallic layer typically is from the range 1 to 50 nm. The construction element may be integrated, for example, into windows, plastic films or sheets or glazings, especially for the purpose of light management.1.-16. (canceled) 17. A translucent construction element comprising a layer of translucent substrate, which contains a surface structured with nanoplanes of inclined angle relative to the substrate plane, and coated with an interrupted metallic layer covering at least a part of said nanoplanes, characterized in that the thickness of the metallic layer is from the range 1 to 50 nm and the periodicity of interruptions in the metallic layer is from the range 50 to 1000 nm 18. A translucent construction element comprising a layer of translucent substrate, which contains a surface structured with nanoplanes of inclined angle relative to the substrate plane, and coated with an interrupted metallic layer covering at least a part of said nanoplanes, characterized in that the periodicity of interruptions in the metallic layer is from the range 50 to less than 500 nm, and the thickness of the metallic layer is from the range 1 to 75 nm. 19. The translucent construction element of claim 17, wherein the element is a facade element, or is transparent and is a window pane. 20. The translucent construction element of claim 17, wherein the nanoplanes on the substrate surface are provided in form of a grating of depth from the range 30 to 1000 nm, which grating is of sinusoidal, trapezoidal, triangular or rectangular cross section. 21. The translucent construction element of claim 20, wherein the element is integrated in a building or vehicle with its grating lines aligned horizontally. 22. A device comprising an interrupted metallic layer on the surface of a transparent substrate, characterized in that the surface is structured with nanoplanes of inclined angle relative to the substrate plane and carrying a metal coating on at least a part of said nanoplanes, where the periodicity of interruptions in the metallic layer is from the range 50 to 1000 nm and the thickness of the metal coating is from the range 1 to 50 nm. 23. The device of claim 22, wherein the inclined angle relative to the substrate plane is from the range 10 to 90°. 24. Device of claim 22, wherein the nanoplanes of inclined angle relative to the substrate plane are provided in form of a grating of periodicity from the range 50 to 1000 nm and of depth from the range 30 to 1000 nm, which grating is of sinusoidal, trapezoidal, triangular or rectangular cross section. 25. The translucent construction element according to claim 17, wherein the metallic layer is covered by a transparent medium in form of an encapsulating layer. 26. The translucent construction element according to claim 17, comprising between substrate and metallic layer and/or between the metallic layer and encapsulating layer one or more further layers selected from underlayers of enhancement materials and cover layers. 27. The translucent construction element according to claim 17, wherein the metallic layer contains a metal selected from the group consisting of silver, aluminum, gold, copper, and platinum. 28. The translucent construction element according to claim 17, wherein the substrate, an optional encapsulating layer(s) and an optional cover layer(s) are glass or polymeric materials selected from the group consisting of thermoplastic polymers and UV-cured polymers such as acrylic polymers, polycarbonates, polyesters, polyvinylbutyrate, polyolefines, polyetherimides, polyetherketones, polyethylene naphthalates, polyimides, polystyrenes, polyoxymethylene, polyvinylchloride, low refractive index composite materials, hybrid polymers, radiation-curable compositions, and combinations thereof. 29. A window pane comprising the translucent construction element according to claim 17, wherein the substrate comprises a flat or bent polymer film or sheet, or glass sheet, or a polymer film or sheet and a glass sheet. 30. The window pane of claim 29 comprising a glass sheet carrying the element including the interrupted metallic layer on at least a part of its surface, wherein the metallic structures are directly attached to the glass surface or are embedded in a transparent medium comprising the substrate and the encapsulating medium, where substrate and the encapsulating medium are selected from the group consisting of thermoplastic polymers, UV-cured polymers such as acrylic polymers, polycarbonates, polyesters, polyvinylbutyrate, polyolefines, polyetherimides, polyetherketones, polyethylene naphthalates, polyimides, polystyrenes, polyoxymethylene, polyvinylchloride, low refractive index composite materials, hybrid polymers, radiation-curable compositions, and combinations thereof. 31. A method for reducing the transmission of solar light through a transparent element, which method comprises integrating the translucent construction element according to claim 17 into said transparent element. 32. A method for seasonal heat and/or light management, comprising incorporating the translucent construction element according to claim 17into a window into the interior space of a building or vehicle. | 2,800 |
11,828 | 11,828 | 15,190,038 | 2,894 | A method of fabricating a semiconductor structure includes: grinding a backside surface of a semiconductor substrate such that the backside surface has a relatively high average roughness (Ra) (when compared with a backside surface subjected to chemical mechanical polishing (CMP)), and then, forming a backside metal structure on the backside surface while the backside surface has the relatively high average roughness. The backside surface can have an average roughness in the range of about 5 to 100 nanometers (or alternately, in the range of about 20 to 40 nanometers) when the backside metal structure is formed. The backside metal structure may be electrically coupled to through silicon vias (TSVs), which supply ground to semiconductor devices fabricated on a front side of the semiconductor substrate. | 1. A semiconductor structure comprising:
a semiconductor substrate having a front side and a back side surface, wherein one or more semiconductor devices are fabricated at the front side, and wherein the back side surface has an average roughness in the range of about 5 to 100 nanometers; and a backside metal structure formed on the back side surface of the semiconductor substrate. 2. The semiconductor structure of claim 1, wherein the back side surface has an average roughness in the range of about 20 to 40 nanometers. 3. The semiconductor structure of claim 1, wherein the backside metal structure comprises a seed layer deposited on the back side surface of the semiconductor substrate. 4. The semiconductor structure of claim 3, wherein the seed layer comprises titanium. 5. The semiconductor structure of claim 3, wherein the seed layer comprises titanium-tungsten. 6. The semiconductor structure of claim 3, wherein the seed layer has a thickness of about 50-500 Angstroms. 7. The semiconductor structure of claim 3, wherein the backside metal structure further comprises a barrier layer formed on the seed layer. 8. The semiconductor structure of claim 7, wherein the barrier layer comprises nickel-vanadium. 9. The semiconductor structure of claim 7, wherein the barrier layer comprises titanium-tungsten. 10. The semiconductor structure of claim 7, wherein the barrier layer has a thickness of about 100-500 Angstroms. 11. The semiconductor structure of claim 7, wherein the backside metal structure further comprises a metal layer formed on the barrier layer. 12. The semiconductor structure of claim 12, wherein the metal layer comprises at least one of copper, aluminum or gold. 13. The semiconductor structure of claim 12, wherein the metal layer has a thickness of at least about 1000 Angstroms. 14. The semiconductor structure of claim 1, further comprising one or more through substrate vias (TSVs) that extend through the semiconductor substrate, wherein the TSVs electrically couple the backside metal structure to at least one of the one or more semiconductor devices. 15. A method of fabricating a semiconductor structure comprising:
grinding a backside surface of a semiconductor substrate such that the backside surface has an average roughness in the range of about 5 to 100 nanometers; and then forming a backside metal structure on the backside surface while the backside surface has an average roughness in the range of about 5 to 100 nanometers. 16. The method of claim 15, further comprising performing a wet clean of the backside surface after grinding the backside surface, and before forming the backside metal structure. 17. The method of claim 16, further comprising performing a sputter clean of the backside surface after performing the wet clean, and before forming the backside metal structure. 18. The method of claim 15, wherein forming the backside metal structure comprises forming a seed layer on the backside surface while the backside surface has an average roughness in the range of about 5 to 100 nanometers. 19. The method of claim 18, wherein forming the seed layer comprises depositing titanium or titanium-tungsten on the backside surface. 20. The method of claim 18, wherein forming the metal backside metal structure further comprises forming a barrier layer on the seed layer. 21. The method of claim 20, wherein forming the barrier layer comprises depositing vanadium-nickel or titanium-tungsten on the seed layer. 22. The method of claim 20, further comprising forming a metal layer on the barrier layer. 23. The method of claim 22, wherein forming the metal layer comprises depositing copper, aluminum or gold on the barrier layer. 24. The method of claim 15, wherein grinding the backside surface of the semiconductor substrate comprises:
performing a coarse grind on the backside of the semiconductor substrate; and then performing a fine grind on the backside of the semiconductor substrate. 25. The method of claim 15, further comprising:
forming one or more through substrate vias (TSVs) that extend through the semiconductor substrate, wherein the TSVs electrically couple the backside metal structure to a semiconductor device at a front side of the semiconductor substrate. 26. The method of claim 15, wherein the grinding results in the backside surface having an average roughness in the range of about 20 to 40 nanometers, and wherein the backside metal structure is formed while the backside surface has an average roughness of about 20 to 40 nanometers. | A method of fabricating a semiconductor structure includes: grinding a backside surface of a semiconductor substrate such that the backside surface has a relatively high average roughness (Ra) (when compared with a backside surface subjected to chemical mechanical polishing (CMP)), and then, forming a backside metal structure on the backside surface while the backside surface has the relatively high average roughness. The backside surface can have an average roughness in the range of about 5 to 100 nanometers (or alternately, in the range of about 20 to 40 nanometers) when the backside metal structure is formed. The backside metal structure may be electrically coupled to through silicon vias (TSVs), which supply ground to semiconductor devices fabricated on a front side of the semiconductor substrate.1. A semiconductor structure comprising:
a semiconductor substrate having a front side and a back side surface, wherein one or more semiconductor devices are fabricated at the front side, and wherein the back side surface has an average roughness in the range of about 5 to 100 nanometers; and a backside metal structure formed on the back side surface of the semiconductor substrate. 2. The semiconductor structure of claim 1, wherein the back side surface has an average roughness in the range of about 20 to 40 nanometers. 3. The semiconductor structure of claim 1, wherein the backside metal structure comprises a seed layer deposited on the back side surface of the semiconductor substrate. 4. The semiconductor structure of claim 3, wherein the seed layer comprises titanium. 5. The semiconductor structure of claim 3, wherein the seed layer comprises titanium-tungsten. 6. The semiconductor structure of claim 3, wherein the seed layer has a thickness of about 50-500 Angstroms. 7. The semiconductor structure of claim 3, wherein the backside metal structure further comprises a barrier layer formed on the seed layer. 8. The semiconductor structure of claim 7, wherein the barrier layer comprises nickel-vanadium. 9. The semiconductor structure of claim 7, wherein the barrier layer comprises titanium-tungsten. 10. The semiconductor structure of claim 7, wherein the barrier layer has a thickness of about 100-500 Angstroms. 11. The semiconductor structure of claim 7, wherein the backside metal structure further comprises a metal layer formed on the barrier layer. 12. The semiconductor structure of claim 12, wherein the metal layer comprises at least one of copper, aluminum or gold. 13. The semiconductor structure of claim 12, wherein the metal layer has a thickness of at least about 1000 Angstroms. 14. The semiconductor structure of claim 1, further comprising one or more through substrate vias (TSVs) that extend through the semiconductor substrate, wherein the TSVs electrically couple the backside metal structure to at least one of the one or more semiconductor devices. 15. A method of fabricating a semiconductor structure comprising:
grinding a backside surface of a semiconductor substrate such that the backside surface has an average roughness in the range of about 5 to 100 nanometers; and then forming a backside metal structure on the backside surface while the backside surface has an average roughness in the range of about 5 to 100 nanometers. 16. The method of claim 15, further comprising performing a wet clean of the backside surface after grinding the backside surface, and before forming the backside metal structure. 17. The method of claim 16, further comprising performing a sputter clean of the backside surface after performing the wet clean, and before forming the backside metal structure. 18. The method of claim 15, wherein forming the backside metal structure comprises forming a seed layer on the backside surface while the backside surface has an average roughness in the range of about 5 to 100 nanometers. 19. The method of claim 18, wherein forming the seed layer comprises depositing titanium or titanium-tungsten on the backside surface. 20. The method of claim 18, wherein forming the metal backside metal structure further comprises forming a barrier layer on the seed layer. 21. The method of claim 20, wherein forming the barrier layer comprises depositing vanadium-nickel or titanium-tungsten on the seed layer. 22. The method of claim 20, further comprising forming a metal layer on the barrier layer. 23. The method of claim 22, wherein forming the metal layer comprises depositing copper, aluminum or gold on the barrier layer. 24. The method of claim 15, wherein grinding the backside surface of the semiconductor substrate comprises:
performing a coarse grind on the backside of the semiconductor substrate; and then performing a fine grind on the backside of the semiconductor substrate. 25. The method of claim 15, further comprising:
forming one or more through substrate vias (TSVs) that extend through the semiconductor substrate, wherein the TSVs electrically couple the backside metal structure to a semiconductor device at a front side of the semiconductor substrate. 26. The method of claim 15, wherein the grinding results in the backside surface having an average roughness in the range of about 20 to 40 nanometers, and wherein the backside metal structure is formed while the backside surface has an average roughness of about 20 to 40 nanometers. | 2,800 |
11,829 | 11,829 | 14,851,887 | 2,884 | A system and method for inspecting a surface of a wafer. The system includes a source generating an optical beam at a deep ultraviolet wavelength; a solid immersion lens, receiving the optical beam, positioned such that the air gap between the lens and the wafer surface is less than the wavelength, an enhanced electric field being generated at the wafer surface, at least one particle on the wafer receiving the enhanced electric field generating scattered light; a detector receiving the scattered light and generating a corresponding electrical signal; and a processor receiving and analyzing the electrical signal. | 1. A system for inspecting a surface of a wafer comprising:
a source generating an optical beam at a deep ultraviolet wavelength; a solid immersion lens, receiving the optical beam, positioned such that the air gap between the lens and the wafer surface is less than the wavelength, an enhanced electric field being generated at the wafer surface, at least one particle on the wafer receiving the enhanced electric field generating scattered light; a detector receiving the scattered light and generating a corresponding electrical signal; and a processor receiving and analyzing the electrical signal. 2. The system as recited in claim 1, when the wafer is silicon, wherein the deep ultraviolet wavelength ranges from 150 nm to 355 nm. 3. The system as recited in claim 1, at least one objective lens interposing the solid immersion lens and the detector for collecting the scattered light. 4. The system as recited in claim 1, wherein the solid immersion lens is selected from a group including hemispherical, spherical, and aspherical lenses having a flat surface. 5. The system as recited in claim 4, including a metal coating on the surface of the lens proximate to the wafer. 6. The system as recited in claim 5, wherein the metal coating is selected from a group including silver and gold. 7. The system as recited in claim 4, including a grating on the surface of the lens proximate to the wafer. 8. The system as recited in claim 1, further including a first and a second lens interposing the solid immersion lens and detector, wherein the first lens collimates scattered light and the second lens focuses the scattered light on the detector. 9. A method for inspecting a surface of a wafer comprising:
generating an optical beam at a deep ultraviolet wavelength, wherein an air gap separating the wafer and a lens is less than the wavelength; at the wafer surface, generating an enhanced electric field from the optical beam; generating a scattered light signal when particles on the wafer receive the enhanced electric field; detecting the scattered light signal; generating a corresponding electrical signal; and analyzing the electrical signal. 10. The method recited in claim 9, wherein the deep ultraviolet wavelength ranges from 150 nm to 355 nm. 11. The method recited in claim 9, further comprising scanning the wafer for large particles prior to generating optical signal. 12. The method recited in claim 9, further comprising analyzing the electrical signal including comparing the electrical signal to a threshold, wherein the threshold is indicative of wafer quality. 13. The method recited in claim 9, further comprising:
collimating the scattered light; and focusing the scattered light on a detector. | A system and method for inspecting a surface of a wafer. The system includes a source generating an optical beam at a deep ultraviolet wavelength; a solid immersion lens, receiving the optical beam, positioned such that the air gap between the lens and the wafer surface is less than the wavelength, an enhanced electric field being generated at the wafer surface, at least one particle on the wafer receiving the enhanced electric field generating scattered light; a detector receiving the scattered light and generating a corresponding electrical signal; and a processor receiving and analyzing the electrical signal.1. A system for inspecting a surface of a wafer comprising:
a source generating an optical beam at a deep ultraviolet wavelength; a solid immersion lens, receiving the optical beam, positioned such that the air gap between the lens and the wafer surface is less than the wavelength, an enhanced electric field being generated at the wafer surface, at least one particle on the wafer receiving the enhanced electric field generating scattered light; a detector receiving the scattered light and generating a corresponding electrical signal; and a processor receiving and analyzing the electrical signal. 2. The system as recited in claim 1, when the wafer is silicon, wherein the deep ultraviolet wavelength ranges from 150 nm to 355 nm. 3. The system as recited in claim 1, at least one objective lens interposing the solid immersion lens and the detector for collecting the scattered light. 4. The system as recited in claim 1, wherein the solid immersion lens is selected from a group including hemispherical, spherical, and aspherical lenses having a flat surface. 5. The system as recited in claim 4, including a metal coating on the surface of the lens proximate to the wafer. 6. The system as recited in claim 5, wherein the metal coating is selected from a group including silver and gold. 7. The system as recited in claim 4, including a grating on the surface of the lens proximate to the wafer. 8. The system as recited in claim 1, further including a first and a second lens interposing the solid immersion lens and detector, wherein the first lens collimates scattered light and the second lens focuses the scattered light on the detector. 9. A method for inspecting a surface of a wafer comprising:
generating an optical beam at a deep ultraviolet wavelength, wherein an air gap separating the wafer and a lens is less than the wavelength; at the wafer surface, generating an enhanced electric field from the optical beam; generating a scattered light signal when particles on the wafer receive the enhanced electric field; detecting the scattered light signal; generating a corresponding electrical signal; and analyzing the electrical signal. 10. The method recited in claim 9, wherein the deep ultraviolet wavelength ranges from 150 nm to 355 nm. 11. The method recited in claim 9, further comprising scanning the wafer for large particles prior to generating optical signal. 12. The method recited in claim 9, further comprising analyzing the electrical signal including comparing the electrical signal to a threshold, wherein the threshold is indicative of wafer quality. 13. The method recited in claim 9, further comprising:
collimating the scattered light; and focusing the scattered light on a detector. | 2,800 |
11,830 | 11,830 | 15,986,460 | 2,813 | Implementations of a method of forming a plurality of semiconductor devices on a semiconductor substrate may include: providing a semiconductor substrate having a first surface, a second surface, a size, and a thickness where the second surface opposes the first surface and the thickness is between the first surface and the second surface. The method may include processing the semiconductor substrate through a plurality of semiconductor device fabrication processes to form a plurality of semiconductor devices on the first surface. The thickness may be between 100 microns and 575 microns and the size may be 150 mm. The semiconductor substrate may not be coupled with a carrier or support. | 1. A method of forming a plurality of semiconductor devices on a semiconductor substrate, the method comprising:
providing a semiconductor substrate comprising a first surface, a second surface, a size, and a thickness where the second surface opposes the first surface and the thickness is between the first surface and the second surface; and processing the semiconductor substrate through a plurality of semiconductor device fabrication processes to form a plurality of semiconductor devices on the first surface; wherein the thickness is between 70 microns and 500 microns and the size is 100 millimeters; and wherein the semiconductor substrate is not coupled with one of a carrier and a support. 2. The method of claim 1, further comprising backgrinding the second surface of the semiconductor substrate to reduce the thickness to a desired value. 3. The method of claim 1, further comprising singulating the semiconductor substrate to singulate the plurality of semiconductor devices. 4. The method of claim 1, further comprising not backgrinding the second surface of the semiconductor substrate. 5. The method of claim 1, wherein providing the semiconductor substrate further comprises:
forming the semiconductor substrate from a boule; and one of grinding and polishing one of the first surface and the second surface of the semiconductor substrate to thin the thickness to between 70 microns and 500 microns. 6. The method of claim 1, wherein providing the semiconductor substrate further comprises:
forming the semiconductor substrate from a boule with the thickness between 70 microns and 500 microns; and one of grinding and polishing one of the first surface and the second surface to not substantially thin the thickness. 7. The method of claim 1, wherein the thickness is between 70 microns and 500 microns during each of the plurality of semiconductor device fabrication processes. 8. A method of forming a plurality of semiconductor devices on a semiconductor substrate, the method comprising:
providing a semiconductor substrate comprising a first surface, a second surface, a size, and a thickness where the second surface opposes the first surface and the thickness is between the first surface and the second surface; and processing the semiconductor substrate through a plurality of semiconductor device fabrication processes to form a plurality of semiconductor devices on the first surface; wherein the thickness is between 100 microns and 575 microns and the size is 150 millimeters; and wherein the semiconductor substrate is not coupled with one of a carrier and a support. 9. The method of claim 8, further comprising backgrinding the second surface of the semiconductor substrate to reduce the thickness to a desired value. 10. The method of claim 8, further comprising singulating the semiconductor substrate to singulate the plurality of semiconductor devices. 11. The method of claim 8, further comprising not backgrinding the second surface of the semiconductor substrate. 12. The method of claim 8, wherein providing the semiconductor substrate further comprises:
forming the semiconductor substrate from a boule; and one of grinding and polishing one of the first surface and the second surface of the semiconductor substrate to thin the thickness to between 100 microns and 575 microns. 13. The method of claim 8, wherein providing the semiconductor substrate further comprises:
forming the semiconductor substrate from a boule with the thickness between 100 microns and 575 microns; and one of grinding and polishing one of the first surface and the second surface to not substantially thin the thickness. 14. The method of claim 8, wherein the thickness is between 100 microns and 575 microns during each of the plurality of semiconductor device fabrication processes. 15. A method of forming a plurality of semiconductor devices on a semiconductor substrate, the method comprising:
providing a semiconductor substrate comprising a first surface, a second surface, a size, and a thickness where the second surface opposes the first surface and the thickness is between the first surface and the second surface; and processing the semiconductor substrate through a plurality of semiconductor device fabrication processes to form a plurality of semiconductor devices on the first surface; wherein the thickness is between 120 microns and 600 microns and the size is 200 millimeters; and wherein the semiconductor substrate is not coupled with one of a carrier and a support. 16. The method of claim 15, further comprising backgrinding the second surface of the semiconductor substrate to reduce the thickness to a desired value. 17. The method of claim 15, further comprising singulating the semiconductor substrate to singulate the plurality of semiconductor devices. 18. The method of claim 15, further comprising not backgrinding the second surface of the semiconductor substrate. 19. The method of claim 15, wherein providing the semiconductor substrate further comprises:
forming the semiconductor substrate from a boule; and one of grinding and polishing one of the first surface and the second surface of the semiconductor substrate to thin the thickness to between 120 microns and 600 microns. 20. The method of claim 15, wherein the thickness is between 120 microns and 600 microns during each of the plurality of semiconductor device fabrication processes. | Implementations of a method of forming a plurality of semiconductor devices on a semiconductor substrate may include: providing a semiconductor substrate having a first surface, a second surface, a size, and a thickness where the second surface opposes the first surface and the thickness is between the first surface and the second surface. The method may include processing the semiconductor substrate through a plurality of semiconductor device fabrication processes to form a plurality of semiconductor devices on the first surface. The thickness may be between 100 microns and 575 microns and the size may be 150 mm. The semiconductor substrate may not be coupled with a carrier or support.1. A method of forming a plurality of semiconductor devices on a semiconductor substrate, the method comprising:
providing a semiconductor substrate comprising a first surface, a second surface, a size, and a thickness where the second surface opposes the first surface and the thickness is between the first surface and the second surface; and processing the semiconductor substrate through a plurality of semiconductor device fabrication processes to form a plurality of semiconductor devices on the first surface; wherein the thickness is between 70 microns and 500 microns and the size is 100 millimeters; and wherein the semiconductor substrate is not coupled with one of a carrier and a support. 2. The method of claim 1, further comprising backgrinding the second surface of the semiconductor substrate to reduce the thickness to a desired value. 3. The method of claim 1, further comprising singulating the semiconductor substrate to singulate the plurality of semiconductor devices. 4. The method of claim 1, further comprising not backgrinding the second surface of the semiconductor substrate. 5. The method of claim 1, wherein providing the semiconductor substrate further comprises:
forming the semiconductor substrate from a boule; and one of grinding and polishing one of the first surface and the second surface of the semiconductor substrate to thin the thickness to between 70 microns and 500 microns. 6. The method of claim 1, wherein providing the semiconductor substrate further comprises:
forming the semiconductor substrate from a boule with the thickness between 70 microns and 500 microns; and one of grinding and polishing one of the first surface and the second surface to not substantially thin the thickness. 7. The method of claim 1, wherein the thickness is between 70 microns and 500 microns during each of the plurality of semiconductor device fabrication processes. 8. A method of forming a plurality of semiconductor devices on a semiconductor substrate, the method comprising:
providing a semiconductor substrate comprising a first surface, a second surface, a size, and a thickness where the second surface opposes the first surface and the thickness is between the first surface and the second surface; and processing the semiconductor substrate through a plurality of semiconductor device fabrication processes to form a plurality of semiconductor devices on the first surface; wherein the thickness is between 100 microns and 575 microns and the size is 150 millimeters; and wherein the semiconductor substrate is not coupled with one of a carrier and a support. 9. The method of claim 8, further comprising backgrinding the second surface of the semiconductor substrate to reduce the thickness to a desired value. 10. The method of claim 8, further comprising singulating the semiconductor substrate to singulate the plurality of semiconductor devices. 11. The method of claim 8, further comprising not backgrinding the second surface of the semiconductor substrate. 12. The method of claim 8, wherein providing the semiconductor substrate further comprises:
forming the semiconductor substrate from a boule; and one of grinding and polishing one of the first surface and the second surface of the semiconductor substrate to thin the thickness to between 100 microns and 575 microns. 13. The method of claim 8, wherein providing the semiconductor substrate further comprises:
forming the semiconductor substrate from a boule with the thickness between 100 microns and 575 microns; and one of grinding and polishing one of the first surface and the second surface to not substantially thin the thickness. 14. The method of claim 8, wherein the thickness is between 100 microns and 575 microns during each of the plurality of semiconductor device fabrication processes. 15. A method of forming a plurality of semiconductor devices on a semiconductor substrate, the method comprising:
providing a semiconductor substrate comprising a first surface, a second surface, a size, and a thickness where the second surface opposes the first surface and the thickness is between the first surface and the second surface; and processing the semiconductor substrate through a plurality of semiconductor device fabrication processes to form a plurality of semiconductor devices on the first surface; wherein the thickness is between 120 microns and 600 microns and the size is 200 millimeters; and wherein the semiconductor substrate is not coupled with one of a carrier and a support. 16. The method of claim 15, further comprising backgrinding the second surface of the semiconductor substrate to reduce the thickness to a desired value. 17. The method of claim 15, further comprising singulating the semiconductor substrate to singulate the plurality of semiconductor devices. 18. The method of claim 15, further comprising not backgrinding the second surface of the semiconductor substrate. 19. The method of claim 15, wherein providing the semiconductor substrate further comprises:
forming the semiconductor substrate from a boule; and one of grinding and polishing one of the first surface and the second surface of the semiconductor substrate to thin the thickness to between 120 microns and 600 microns. 20. The method of claim 15, wherein the thickness is between 120 microns and 600 microns during each of the plurality of semiconductor device fabrication processes. | 2,800 |
11,831 | 11,831 | 15,419,385 | 2,896 | Systems and methods for reconstructing MR parameter maps of a subject from magnetic resonance fingerprinting (MRF) data acquired using a magnetic resonance imaging (MRI) system. The method includes providing MRF data acquired from a subject using an MRI system and reconstructing the MRF data by solving a constrained optimization problem using a low-rank model, for which an input to the optimization problem is the MRF data and an output from the optimization problem is the MRF time-series images. | 1. A magnetic resonance imaging (MRI) system comprising:
a magnet system configured to generate a polarizing magnetic field about at least a portion of a subject arranged in the MRI system; a plurality of gradient coils configured to apply a gradient field to the polarizing magnetic field; a radio frequency (RF) system configured to apply an excitation field to the subject and acquire MR image data from a ROI; a computer system programmed to:
control the plurality of gradient coils and the RF system to acquire magnetic resonance fingerprinting (MRF) data from a subject;
reconstruct an MRF time series of images from the MRF data by solving a constrained optimization problem using a low-rank model, for which an input to the optimization problem is the MRF data and an output from the optimization problem is the MRF time-series images; and
estimate the MR parameter maps from the reconstructed time series of images. 2. The system of claim 1 wherein the computer is further programmed to perform an augmented Lagrangian-based method to solve the optimization problem. 3. The system of claim 1 wherein the computer is further programmed to perform a dictionary matching process to generate the MR parameter maps. 4. The system of claim 1 wherein the computer is further programmed to apply a subspace constraint associated with the low-rank model by estimating a temporal subspace structure of the low-lank model from an ensemble of magnetization dynamics. 5. The system of claim 4 wherein the computer is further programmed to use principal component analysis or singular value decomposition to estimate the temporal subspace structure. 6. The system of claim 1 wherein the computer is further programmed to combine a joint sparsity constraint that captures correlated edge structure of co-registered MRF time-series images. 7. A method for reconstructing MR parameter maps from magnetic resonance fingerprinting (MRF) data acquired using a magnetic resonance imaging (MRI) system, the steps of the method comprising:
providing MRF data acquired from a subject using an MRI system; reconstructing the MRF data by solving a constrained optimization problem using a low-rank model, for which an input to the optimization problem is the MRF data and an output from the optimization problem is the MRF time-series images. 8. The method of claim 7 further comprising performing an augmented Lagrangian-based method to solve the optimization problem. 9. The method of claim 7 further comprising performing a dictionary matching process to generate MR parameter maps from the MRF data. 10. The method of claim 7 further comprising applying a subspace constraint associated with the low-rank model by estimating a temporal subspace of the low-lank model from an ensemble of magnetization dynamics. 11. The method of claim 10 further comprising using principal component analysis to estimate the temporal subspace structure. 12. The method of claim 7 further comprising incorporating a joint sparsity constraint to capture correlated edge structure of co-registered MRF time-series images from the MRF data. 13. The method of claim 7 wherein the constrained optimization problem is formed as:
C=UV;
where C represents the collection of MRF time-series images, U∈ N×L and V∈ L×M respectively represent spatial and temporal subspaces of C, L denotes a rank value, and M and N respectively represent the row and column dimensions of the matrix C. 14. The method of claim 13 wherein, to solve the constrained optimization problem, the spatial subspace, Û is found by:
U
^
=
arg
min
U
∑
c
=
1
N
C
d
c
-
F
u
S
c
U
V
^
2
2
+
λ
DU
V
^
1
,
2
;
where dc represents MRF data from the cth coil, Fu represents an undersampled Fourier encoding matrix, c represents coil sensitivities associated with the cth coil, D represents a spatial finite difference matrix, and λ represents a regularization parameter. 15. A method for reconstructing an image of a subject from magnetic resonance fingerprinting (MRF) data acquired using a magnetic resonance imaging (MRI) system, the steps of the method comprising:
providing MRF data acquired from a subject using an MRI system; reconstructing the MRF data by solving a constrained optimization problem using a low-rank model that represents the MRF data as a function of a spatial subspace and temporal subspace. 16. The method of claim 15 further comprising performing an augmented Lagrangian-based method to solve the optimization problem. 17. The method of claim 15 further comprising performing a dictionary matching process to generate MRF parameter maps from the MRF data. 18. The method of claim 15 further comprising applying a subspace constraint associated with the low-rank model by estimating the temporal subspace of the low-lank model from an ensemble of magnetization dynamics. 19. The method of claim 18 further comprising using principal component analysis to estimate the temporal subspace structure. 20. The method of claim 15 further comprising incorporating a joint sparsity constraint to capture correlated edge structure of co-registered MRF time-series images from the MRF data. | Systems and methods for reconstructing MR parameter maps of a subject from magnetic resonance fingerprinting (MRF) data acquired using a magnetic resonance imaging (MRI) system. The method includes providing MRF data acquired from a subject using an MRI system and reconstructing the MRF data by solving a constrained optimization problem using a low-rank model, for which an input to the optimization problem is the MRF data and an output from the optimization problem is the MRF time-series images.1. A magnetic resonance imaging (MRI) system comprising:
a magnet system configured to generate a polarizing magnetic field about at least a portion of a subject arranged in the MRI system; a plurality of gradient coils configured to apply a gradient field to the polarizing magnetic field; a radio frequency (RF) system configured to apply an excitation field to the subject and acquire MR image data from a ROI; a computer system programmed to:
control the plurality of gradient coils and the RF system to acquire magnetic resonance fingerprinting (MRF) data from a subject;
reconstruct an MRF time series of images from the MRF data by solving a constrained optimization problem using a low-rank model, for which an input to the optimization problem is the MRF data and an output from the optimization problem is the MRF time-series images; and
estimate the MR parameter maps from the reconstructed time series of images. 2. The system of claim 1 wherein the computer is further programmed to perform an augmented Lagrangian-based method to solve the optimization problem. 3. The system of claim 1 wherein the computer is further programmed to perform a dictionary matching process to generate the MR parameter maps. 4. The system of claim 1 wherein the computer is further programmed to apply a subspace constraint associated with the low-rank model by estimating a temporal subspace structure of the low-lank model from an ensemble of magnetization dynamics. 5. The system of claim 4 wherein the computer is further programmed to use principal component analysis or singular value decomposition to estimate the temporal subspace structure. 6. The system of claim 1 wherein the computer is further programmed to combine a joint sparsity constraint that captures correlated edge structure of co-registered MRF time-series images. 7. A method for reconstructing MR parameter maps from magnetic resonance fingerprinting (MRF) data acquired using a magnetic resonance imaging (MRI) system, the steps of the method comprising:
providing MRF data acquired from a subject using an MRI system; reconstructing the MRF data by solving a constrained optimization problem using a low-rank model, for which an input to the optimization problem is the MRF data and an output from the optimization problem is the MRF time-series images. 8. The method of claim 7 further comprising performing an augmented Lagrangian-based method to solve the optimization problem. 9. The method of claim 7 further comprising performing a dictionary matching process to generate MR parameter maps from the MRF data. 10. The method of claim 7 further comprising applying a subspace constraint associated with the low-rank model by estimating a temporal subspace of the low-lank model from an ensemble of magnetization dynamics. 11. The method of claim 10 further comprising using principal component analysis to estimate the temporal subspace structure. 12. The method of claim 7 further comprising incorporating a joint sparsity constraint to capture correlated edge structure of co-registered MRF time-series images from the MRF data. 13. The method of claim 7 wherein the constrained optimization problem is formed as:
C=UV;
where C represents the collection of MRF time-series images, U∈ N×L and V∈ L×M respectively represent spatial and temporal subspaces of C, L denotes a rank value, and M and N respectively represent the row and column dimensions of the matrix C. 14. The method of claim 13 wherein, to solve the constrained optimization problem, the spatial subspace, Û is found by:
U
^
=
arg
min
U
∑
c
=
1
N
C
d
c
-
F
u
S
c
U
V
^
2
2
+
λ
DU
V
^
1
,
2
;
where dc represents MRF data from the cth coil, Fu represents an undersampled Fourier encoding matrix, c represents coil sensitivities associated with the cth coil, D represents a spatial finite difference matrix, and λ represents a regularization parameter. 15. A method for reconstructing an image of a subject from magnetic resonance fingerprinting (MRF) data acquired using a magnetic resonance imaging (MRI) system, the steps of the method comprising:
providing MRF data acquired from a subject using an MRI system; reconstructing the MRF data by solving a constrained optimization problem using a low-rank model that represents the MRF data as a function of a spatial subspace and temporal subspace. 16. The method of claim 15 further comprising performing an augmented Lagrangian-based method to solve the optimization problem. 17. The method of claim 15 further comprising performing a dictionary matching process to generate MRF parameter maps from the MRF data. 18. The method of claim 15 further comprising applying a subspace constraint associated with the low-rank model by estimating the temporal subspace of the low-lank model from an ensemble of magnetization dynamics. 19. The method of claim 18 further comprising using principal component analysis to estimate the temporal subspace structure. 20. The method of claim 15 further comprising incorporating a joint sparsity constraint to capture correlated edge structure of co-registered MRF time-series images from the MRF data. | 2,800 |
11,832 | 11,832 | 15,291,323 | 2,883 | Polymeric coated optical elements are described herein, which exhibit good optical properties, e.g., low attenuation. Some such coated optical elements comprise an optical element (e.g., an optical fiber) having an outer surface and a thermoplastic polymeric tight buffer coating on at least a portion of the outer surface of the optical element, wherein the polymer-coated optical element exhibits a first attenuation at room temperature of plus or minus about 50 % the attenuation of a comparable optical element with no thermoplastic polymeric tight buffer coating thereon, and a second attenuation at room temperature after thermal cycling to a temperature of at least 170 ° C. that is about 2 times the first attenuation or less. | 1. A thermoplastic polymer-coated optical element comprising:
an optical element, wherein the optical element comprises an optical fiber having a core, a cladding on at least a portion of an outer surface of the core, and a polymeric primary buffer coating on at least a portion of an outer surface of the cladding; and a thermoplastic polymeric tight buffer coating on at least a portion of an outer surface of the polymeric primary buffer coating of the optical element, wherein the polymer-coated optical element exhibits a first attenuation at room temperature of plus or minus 50% the attenuation of a comparable optical element with no thermoplastic polymeric tight buffer coating thereon, and wherein the polymer-coated optical element exhibits a second attenuation at room temperature after thermal cycling to a temperature of at least 170° C. that is about 2 times the first attenuation or less. 2. The polymer-coated optical element of claim 1, wherein the thermoplastic polymeric tight buffer coating comprises one or more of a polyaryletherketone (PAEK), a liquid crystal polymer, a polyamide-imide, and a polybenzimidazole. 3. The polymer-coated optical element of claim 1, wherein the thermoplastic polymeric tight buffer coating is selected from the group consisting of polyetherketone (PEK), polyetheretherketone (PEEK), polyetherketoneketone (PEKK), polyetheretherketoneketone (PEEKK), polyetherketoneetherketoneketone (PEKEKK), and combinations thereof. 4. The polymer-coated optical element of claim 1, wherein the thermoplastic polymeric tight buffer coating comprises polyetheretherketone (PEEK). 5. The polymer-coated optical element of claim 1, wherein the thermoplastic polymeric tight buffer coating consists essentially of the thermoplastic polymer. 6. The polymer-coated optical element of claim 1, wherein the thermoplastic polymeric tight buffer coating comprises less than about 30% by weight of components other than the thermoplastic polymer. 7. The polymer-coated optical element of claim 1, wherein the optical element is an optical fiber. 8. The polymer-coated optical element of claim 1, wherein the core and cladding consist essentially of silica. 9. The polymer-coated optical element of claim 1, wherein the primary buffer coating comprises a polyimide. 10. The polymer-coated optical element of claim 1, wherein the optical element is a fiber optic cable. 11. The polymer-coated optical element of claim 1, wherein the thermoplastic polymeric tight buffer coating is in direct contact with the primary buffer coating. 12. The polymer-coated optical element of claim 1, wherein the first attenuation is plus or minus 20% the attenuation of a comparable optical element with no thermoplastic polymeric tight buffer coating thereon. 13. The polymer-coated optical element of claim 1, wherein the first attenuation is less than or equal to the attenuation of a comparable optical element with no thermoplastic polymeric tight buffer coating thereon. 14. The polymer-coated optical element of claim 1, wherein the first attenuation is less than 1.0 dB/km. 15. The polymer-coated optical element of claim 1, wherein the second attenuation is about 1.5 times the first attenuation or less. 16. A thermoplastic polymer-coated optical element comprising:
an optical element, wherein the optical element comprises an optical fiber comprising a core and a cladding on at least a portion of an outer surface of the core, having no primary buffer coating thereon; and a thermoplastic polymeric tight buffer coating on at least a portion of an outer surface of the optical element, wherein the thermoplastic polymeric tight buffer coating has an average thickness of at least 50 microns, and wherein the polymer-coated optical element exhibits a first attenuation at room temperature of plus or minus 50% the attenuation of a comparable optical element with no thermoplastic polymeric tight buffer coating thereon, and wherein the polymer-coated optical element exhibits a second attenuation at room temperature after thermal cycling to a temperature of at least 170° C. that is about 2 times the first attenuation or less. 17. The polymer-coated optical element of claim 16, wherein the thermoplastic polymeric tight buffer coating comprises one or more of a polyaryletherketone (PAEK), a liquid crystal polymer, a polyamide-imide, and a polybenzimidazole. 18. The polymer-coated optical element of claim 16, wherein the thermoplastic polymeric tight buffer coating is selected from the group consisting of polyetherketone (PEK), polyetheretherketone (PEEK), polyetherketoneketone (PEKK), polyetheretherketoneketone (PEEKK), polyetherketoneetherketoneketone (PEKEKK), and combinations thereof. 19. The polymer-coated optical element of claim 16, wherein the thermoplastic polymeric tight buffer coating comprises polyetheretherketone (PEEK). 20. The polymer-coated optical element of claim 16, wherein the thermoplastic polymeric tight buffer coating consists essentially of the thermoplastic polymer. 21. The polymer-coated optical element of claim 16, wherein the thermoplastic polymeric tight buffer coating comprises less than about 30% by weight of components other than the thermoplastic polymer. 22. The polymer-coated optical element of claim 16, wherein the optical element is an optical fiber. 23. The polymer-coated optical element of claim 16, wherein the core and cladding consist essentially of silica. 24. The polymer-coated optical element of claim 16, wherein the optical element is a fiber optic cable. 25. The polymer-coated optical element of claim 16, wherein the optical element comprises a core and a cladding with no primary buffer coating thereon. 26. The polymer-coated optical element of claim 16, wherein the thermoplastic polymeric tight buffer coating is in direct contact with the cladding. 27. The polymer-coated optical element of claim 16, wherein the first attenuation is plus or minus 20% the attenuation of a comparable optical element with no thermoplastic polymeric tight buffer coating thereon. 28. The polymer-coated optical element of claim 16, wherein the first attenuation is less than or equal to the attenuation of a comparable optical element with no thermoplastic polymeric tight buffer coating thereon. 29. The polymer-coated optical element of claim 16, wherein the first attenuation is less than 1.0 dB/km. 30. The polymer-coated optical element of claim 16, wherein the second attenuation is about 1.5 times the first attenuation or less. 31. A thermoplastic polymer-coated optical element comprising:
an optical element, wherein the optical element comprises an optical fiber comprising a core and a cladding on at least a portion of an outer surface of the core; and a thermoplastic polymeric tight buffer coating on at least a portion of an outer surface of the cladding of the optical element, wherein the thermoplastic polymeric tight buffer coating has an average thickness of at least 50 microns. | Polymeric coated optical elements are described herein, which exhibit good optical properties, e.g., low attenuation. Some such coated optical elements comprise an optical element (e.g., an optical fiber) having an outer surface and a thermoplastic polymeric tight buffer coating on at least a portion of the outer surface of the optical element, wherein the polymer-coated optical element exhibits a first attenuation at room temperature of plus or minus about 50 % the attenuation of a comparable optical element with no thermoplastic polymeric tight buffer coating thereon, and a second attenuation at room temperature after thermal cycling to a temperature of at least 170 ° C. that is about 2 times the first attenuation or less.1. A thermoplastic polymer-coated optical element comprising:
an optical element, wherein the optical element comprises an optical fiber having a core, a cladding on at least a portion of an outer surface of the core, and a polymeric primary buffer coating on at least a portion of an outer surface of the cladding; and a thermoplastic polymeric tight buffer coating on at least a portion of an outer surface of the polymeric primary buffer coating of the optical element, wherein the polymer-coated optical element exhibits a first attenuation at room temperature of plus or minus 50% the attenuation of a comparable optical element with no thermoplastic polymeric tight buffer coating thereon, and wherein the polymer-coated optical element exhibits a second attenuation at room temperature after thermal cycling to a temperature of at least 170° C. that is about 2 times the first attenuation or less. 2. The polymer-coated optical element of claim 1, wherein the thermoplastic polymeric tight buffer coating comprises one or more of a polyaryletherketone (PAEK), a liquid crystal polymer, a polyamide-imide, and a polybenzimidazole. 3. The polymer-coated optical element of claim 1, wherein the thermoplastic polymeric tight buffer coating is selected from the group consisting of polyetherketone (PEK), polyetheretherketone (PEEK), polyetherketoneketone (PEKK), polyetheretherketoneketone (PEEKK), polyetherketoneetherketoneketone (PEKEKK), and combinations thereof. 4. The polymer-coated optical element of claim 1, wherein the thermoplastic polymeric tight buffer coating comprises polyetheretherketone (PEEK). 5. The polymer-coated optical element of claim 1, wherein the thermoplastic polymeric tight buffer coating consists essentially of the thermoplastic polymer. 6. The polymer-coated optical element of claim 1, wherein the thermoplastic polymeric tight buffer coating comprises less than about 30% by weight of components other than the thermoplastic polymer. 7. The polymer-coated optical element of claim 1, wherein the optical element is an optical fiber. 8. The polymer-coated optical element of claim 1, wherein the core and cladding consist essentially of silica. 9. The polymer-coated optical element of claim 1, wherein the primary buffer coating comprises a polyimide. 10. The polymer-coated optical element of claim 1, wherein the optical element is a fiber optic cable. 11. The polymer-coated optical element of claim 1, wherein the thermoplastic polymeric tight buffer coating is in direct contact with the primary buffer coating. 12. The polymer-coated optical element of claim 1, wherein the first attenuation is plus or minus 20% the attenuation of a comparable optical element with no thermoplastic polymeric tight buffer coating thereon. 13. The polymer-coated optical element of claim 1, wherein the first attenuation is less than or equal to the attenuation of a comparable optical element with no thermoplastic polymeric tight buffer coating thereon. 14. The polymer-coated optical element of claim 1, wherein the first attenuation is less than 1.0 dB/km. 15. The polymer-coated optical element of claim 1, wherein the second attenuation is about 1.5 times the first attenuation or less. 16. A thermoplastic polymer-coated optical element comprising:
an optical element, wherein the optical element comprises an optical fiber comprising a core and a cladding on at least a portion of an outer surface of the core, having no primary buffer coating thereon; and a thermoplastic polymeric tight buffer coating on at least a portion of an outer surface of the optical element, wherein the thermoplastic polymeric tight buffer coating has an average thickness of at least 50 microns, and wherein the polymer-coated optical element exhibits a first attenuation at room temperature of plus or minus 50% the attenuation of a comparable optical element with no thermoplastic polymeric tight buffer coating thereon, and wherein the polymer-coated optical element exhibits a second attenuation at room temperature after thermal cycling to a temperature of at least 170° C. that is about 2 times the first attenuation or less. 17. The polymer-coated optical element of claim 16, wherein the thermoplastic polymeric tight buffer coating comprises one or more of a polyaryletherketone (PAEK), a liquid crystal polymer, a polyamide-imide, and a polybenzimidazole. 18. The polymer-coated optical element of claim 16, wherein the thermoplastic polymeric tight buffer coating is selected from the group consisting of polyetherketone (PEK), polyetheretherketone (PEEK), polyetherketoneketone (PEKK), polyetheretherketoneketone (PEEKK), polyetherketoneetherketoneketone (PEKEKK), and combinations thereof. 19. The polymer-coated optical element of claim 16, wherein the thermoplastic polymeric tight buffer coating comprises polyetheretherketone (PEEK). 20. The polymer-coated optical element of claim 16, wherein the thermoplastic polymeric tight buffer coating consists essentially of the thermoplastic polymer. 21. The polymer-coated optical element of claim 16, wherein the thermoplastic polymeric tight buffer coating comprises less than about 30% by weight of components other than the thermoplastic polymer. 22. The polymer-coated optical element of claim 16, wherein the optical element is an optical fiber. 23. The polymer-coated optical element of claim 16, wherein the core and cladding consist essentially of silica. 24. The polymer-coated optical element of claim 16, wherein the optical element is a fiber optic cable. 25. The polymer-coated optical element of claim 16, wherein the optical element comprises a core and a cladding with no primary buffer coating thereon. 26. The polymer-coated optical element of claim 16, wherein the thermoplastic polymeric tight buffer coating is in direct contact with the cladding. 27. The polymer-coated optical element of claim 16, wherein the first attenuation is plus or minus 20% the attenuation of a comparable optical element with no thermoplastic polymeric tight buffer coating thereon. 28. The polymer-coated optical element of claim 16, wherein the first attenuation is less than or equal to the attenuation of a comparable optical element with no thermoplastic polymeric tight buffer coating thereon. 29. The polymer-coated optical element of claim 16, wherein the first attenuation is less than 1.0 dB/km. 30. The polymer-coated optical element of claim 16, wherein the second attenuation is about 1.5 times the first attenuation or less. 31. A thermoplastic polymer-coated optical element comprising:
an optical element, wherein the optical element comprises an optical fiber comprising a core and a cladding on at least a portion of an outer surface of the core; and a thermoplastic polymeric tight buffer coating on at least a portion of an outer surface of the cladding of the optical element, wherein the thermoplastic polymeric tight buffer coating has an average thickness of at least 50 microns. | 2,800 |
11,833 | 11,833 | 14,744,417 | 2,829 | Embodiments include method, systems and computer program products for adjusting a hardness of a floor covering. Aspects include monitoring a user on the floor covering and detecting a triggering event associated with the user. Aspects also include adjusting a parameter of the floor covering, wherein the adjustment decreases the hardness of the floor covering. | 1-7. (canceled) 8. A computer program product for adjusting a hardness of a floor covering, the computer program product comprising:
a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: monitoring a user on the floor covering; detecting a triggering event associated with the user; adjusting a parameter of the floor covering, wherein the adjustment decreases the hardness of the floor covering. 9. The computer program product of claim 8, wherein the parameter of the floor covering is a viscosity of one or more of a magnetorheological fluid and electrorheological fluid disposed within the floor covering. 10. The computer program product of claim 8, wherein monitoring the user on the floor covering is performed with one or more sensors disposed within the floor covering. 11. The computer program product of claim 8, wherein monitoring the user on the floor covering is performed with one or more sensors that are disposed on the user. 12. The computer program product of claim 8, wherein the detection of a triggering event includes calculating a confidence level that the user is about to fall and determining if the confidence level exceeds a threshold value. 13. The computer program product of claim 12, wherein at least one of the confidence level and the threshold value are based on an individual profile of the user. 14. The computer program product of claim 12, wherein at least one of the confidence level and the threshold value are based on a characteristic of the user. 15. A system for adjusting a hardness of a floor covering, comprising:
a processor in communication with the floor covering, the processor configured to: monitor a user on the floor covering; detect a triggering event associated with the user; adjust a parameter of the floor covering, wherein the adjustment decreases the hardness of the floor covering. 16. The system of claim 15, wherein the parameter of the floor covering is a viscosity of one or more of a magnetorheological fluid and electrorheological fluid disposed within the floor covering. 17. The system of claim 15, wherein monitoring the user on the floor covering is performed with one or more sensors disposed within the floor covering. 18. The system of claim 15, wherein the detection of a triggering event includes calculating a confidence level that the user is about to fall and determining if the confidence level exceeds a threshold value. 19. The system of claim 18, wherein at least one of the confidence level and the threshold value are based on an individual profile of the user. 20. The system of claim 18, wherein at least one of the confidence level and the threshold value are based on a characteristic of the user. | Embodiments include method, systems and computer program products for adjusting a hardness of a floor covering. Aspects include monitoring a user on the floor covering and detecting a triggering event associated with the user. Aspects also include adjusting a parameter of the floor covering, wherein the adjustment decreases the hardness of the floor covering.1-7. (canceled) 8. A computer program product for adjusting a hardness of a floor covering, the computer program product comprising:
a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: monitoring a user on the floor covering; detecting a triggering event associated with the user; adjusting a parameter of the floor covering, wherein the adjustment decreases the hardness of the floor covering. 9. The computer program product of claim 8, wherein the parameter of the floor covering is a viscosity of one or more of a magnetorheological fluid and electrorheological fluid disposed within the floor covering. 10. The computer program product of claim 8, wherein monitoring the user on the floor covering is performed with one or more sensors disposed within the floor covering. 11. The computer program product of claim 8, wherein monitoring the user on the floor covering is performed with one or more sensors that are disposed on the user. 12. The computer program product of claim 8, wherein the detection of a triggering event includes calculating a confidence level that the user is about to fall and determining if the confidence level exceeds a threshold value. 13. The computer program product of claim 12, wherein at least one of the confidence level and the threshold value are based on an individual profile of the user. 14. The computer program product of claim 12, wherein at least one of the confidence level and the threshold value are based on a characteristic of the user. 15. A system for adjusting a hardness of a floor covering, comprising:
a processor in communication with the floor covering, the processor configured to: monitor a user on the floor covering; detect a triggering event associated with the user; adjust a parameter of the floor covering, wherein the adjustment decreases the hardness of the floor covering. 16. The system of claim 15, wherein the parameter of the floor covering is a viscosity of one or more of a magnetorheological fluid and electrorheological fluid disposed within the floor covering. 17. The system of claim 15, wherein monitoring the user on the floor covering is performed with one or more sensors disposed within the floor covering. 18. The system of claim 15, wherein the detection of a triggering event includes calculating a confidence level that the user is about to fall and determining if the confidence level exceeds a threshold value. 19. The system of claim 18, wherein at least one of the confidence level and the threshold value are based on an individual profile of the user. 20. The system of claim 18, wherein at least one of the confidence level and the threshold value are based on a characteristic of the user. | 2,800 |
11,834 | 11,834 | 14,395,424 | 2,872 | A reflective diffraction grating includes a substrate and a reflection-enhancing interference layer system. The reflection-enhancing interference layer system has alternating low refractive index dielectric layers having a refractive index n1 and high refractive index dielectric layers having a refractive index n2>n1. The reflective diffraction grating also includes a grating containing a grating structure, which is formed in the topmost low refractive index layer on a side of the interference layer system facing away from the substrate, and a cover layer, which conformally covers the grating structure. The cover layer has a refractive index n3>n1. | 1-15. (canceled) 16. A reflective diffraction grating, comprising:
a substrate; a reflection-enhancing interference layer system, which has alternating low refractive index dielectric layers having a refractive index n1 and high refractive index dielectric layers having a refractive index n2, where n2>n1; and a grating, comprising a grating structure, which is formed in a topmost low refractive index layer on a side of the interference layer system facing away from the substrate, and a cover layer, which conformally covers the grating structure, wherein the cover layer has a refractive index n3, where n3>n1. 17. The reflective diffraction grating according to claim 16, wherein n3>1.6. 18. The reflective diffraction grating according to claim 16, wherein the cover layer comprises a dielectric layer. 19. The reflective diffraction grating according to claim 16, wherein the cover layer is formed from the same material as the high refractive index layers of the interference layer system. 20. The reflective diffraction grating according to claim 16, wherein n3−n1>0.4. 21. The reflective diffraction grating according to claim 16, wherein n2−n1>0.4. 22. The reflective diffraction grating according to claim 16, wherein the low refractive index layers comprise silicon dioxide. 23. The reflective diffraction grating according to claim 16, wherein the high refractive index layers comprise titanium dioxide, tantalum pentoxide or hafnium dioxide. 24. The reflective diffraction grating according to claim 23, wherein the cover layer is formed from the same material as the high refractive index layers of the interference layer system. 25. The reflective diffraction grating according to claim 16, wherein the low refractive index layers comprise silicon dioxide and wherein the high refractive index layers comprise titanium dioxide, tantalum pentoxide or hafnium dioxide. 26. The reflective diffraction grating according to claim 16, wherein the cover layer comprises titanium dioxide, tantalum pentoxide or hafnium dioxide. 27. The reflective diffraction grating according to claim 16, wherein the cover layer has a thickness of between 10 nm and 150 nm. 28. The reflective diffraction grating according to claim 16, wherein the grating has a thickness of between 20 nm and 1000 nm. 29. The reflective diffraction grating according to claim 16, wherein the grating has a period length of less than 5 μm. 30. A method for producing a reflective diffraction grating, the method comprising:
depositing a reflection-enhancing interference layer system over a substrate, reflection-enhancing interference layer system having alternating low refractive index dielectric layers having a refractive index n1 and high refractive index dielectric layers having a refractive index n2>n1; forming a grating structure in a topmost low refractive index layer of the interference layer system; and applying a cover layer to the grating structure in such a way that the cover layer conformally covers the grating structure. 31. The method according to claim 30, wherein the cover layer is applied to the grating structure using anatomic layer deposition (ALD) process. 32. The method according to claim 30, wherein the grating structure is produced using an electron beam lithography process. | A reflective diffraction grating includes a substrate and a reflection-enhancing interference layer system. The reflection-enhancing interference layer system has alternating low refractive index dielectric layers having a refractive index n1 and high refractive index dielectric layers having a refractive index n2>n1. The reflective diffraction grating also includes a grating containing a grating structure, which is formed in the topmost low refractive index layer on a side of the interference layer system facing away from the substrate, and a cover layer, which conformally covers the grating structure. The cover layer has a refractive index n3>n1.1-15. (canceled) 16. A reflective diffraction grating, comprising:
a substrate; a reflection-enhancing interference layer system, which has alternating low refractive index dielectric layers having a refractive index n1 and high refractive index dielectric layers having a refractive index n2, where n2>n1; and a grating, comprising a grating structure, which is formed in a topmost low refractive index layer on a side of the interference layer system facing away from the substrate, and a cover layer, which conformally covers the grating structure, wherein the cover layer has a refractive index n3, where n3>n1. 17. The reflective diffraction grating according to claim 16, wherein n3>1.6. 18. The reflective diffraction grating according to claim 16, wherein the cover layer comprises a dielectric layer. 19. The reflective diffraction grating according to claim 16, wherein the cover layer is formed from the same material as the high refractive index layers of the interference layer system. 20. The reflective diffraction grating according to claim 16, wherein n3−n1>0.4. 21. The reflective diffraction grating according to claim 16, wherein n2−n1>0.4. 22. The reflective diffraction grating according to claim 16, wherein the low refractive index layers comprise silicon dioxide. 23. The reflective diffraction grating according to claim 16, wherein the high refractive index layers comprise titanium dioxide, tantalum pentoxide or hafnium dioxide. 24. The reflective diffraction grating according to claim 23, wherein the cover layer is formed from the same material as the high refractive index layers of the interference layer system. 25. The reflective diffraction grating according to claim 16, wherein the low refractive index layers comprise silicon dioxide and wherein the high refractive index layers comprise titanium dioxide, tantalum pentoxide or hafnium dioxide. 26. The reflective diffraction grating according to claim 16, wherein the cover layer comprises titanium dioxide, tantalum pentoxide or hafnium dioxide. 27. The reflective diffraction grating according to claim 16, wherein the cover layer has a thickness of between 10 nm and 150 nm. 28. The reflective diffraction grating according to claim 16, wherein the grating has a thickness of between 20 nm and 1000 nm. 29. The reflective diffraction grating according to claim 16, wherein the grating has a period length of less than 5 μm. 30. A method for producing a reflective diffraction grating, the method comprising:
depositing a reflection-enhancing interference layer system over a substrate, reflection-enhancing interference layer system having alternating low refractive index dielectric layers having a refractive index n1 and high refractive index dielectric layers having a refractive index n2>n1; forming a grating structure in a topmost low refractive index layer of the interference layer system; and applying a cover layer to the grating structure in such a way that the cover layer conformally covers the grating structure. 31. The method according to claim 30, wherein the cover layer is applied to the grating structure using anatomic layer deposition (ALD) process. 32. The method according to claim 30, wherein the grating structure is produced using an electron beam lithography process. | 2,800 |
11,835 | 11,835 | 15,521,647 | 2,864 | Computing device, computer instructions and method for processing input seismic data d. The method includes receiving the input seismic data d recorded in a data domain, solving a linear inversion problem constrained by input seismic data d to obtain a model domain and its energy, wherein the linear inversion problem is dependent on sparseness weights that are simultaneously a function of both time and frequency, reverse transforming the model domain energy to the data domain, and generating an image of a surveyed subsurface based on the reverse transformed model domain energy. | 1. A method for processing input seismic data d, the method comprising:
receiving the input seismic data d recorded in a data domain; solving a linear inversion problem constrained by input seismic data d to obtain a model domain and its energy, wherein the linear inversion problem is dependent on sparseness weights that are simultaneously a function of both time and frequency; reverse transforming the model domain energy to the data domain; and generating an image of a surveyed subsurface based on the reverse transformed model domain energy. 2. The method of claim 1, wherein the sparseness weights are model or data domain sparseness weights. 3. The method of claim 1, wherein the sparseness weights are joint data-model domain sparseness weights and the joint data-model domain sparseness weights enable different data domain samples to be constrained by different model domain sparseness weights. 4. The method of claim 1, wherein more than one model domain is computed at the same time within a single inversion and an input trace is dependent on more than one model domain. 5. The method of claim 1, wherein sparseness weights derived based on the input data are used to derive another model domain representing a sub-set of the input dataset. 6. The method of claim 5, wherein the seismic dataset is spatially more densely sampled than the sub-set of the input seismic dataset. 7. The method of claim 5, wherein the seismic dataset has been recorded with more seismic sensor types that the sub-set of the input seismic dataset. 8. The method of claim 1, wherein the linear inverse problem uses an iterative approach that repeatedly applies operator L to a calculated model domain and an adjoint operator LT to estimated data. 9. The method of claim 1, further comprising:
calculating a highest non-aliased frequency range; and using the sparseness weights from the highest non-aliased frequency range to define sparseness weights at higher frequencies. 10. The method of claim 1, where the linear inversion problem derives a Radon domain. 11. The method of claim 1, wherein the linear inversion problem derives a convolutional filter. 12. The method of claim 1, wherein the linear inversion problem derives an output trace. 13. The method of claim 1, wherein the sparseness weights are iteratively updated during a solution of the model domain. 14. The method of claim 1, wherein the sparseness weights are calculated by estimating an envelope of a corresponding trace in the model domain. 15. A computing device for processing input seismic data d, the computing device comprising:
an interface that receives the input seismic data d recorded in a data domain; and a processor connected to the interface and configured to, solve a linear inversion problem constrained by input seismic data d to obtain a model domain and its energy, wherein the linear inversion problem is dependent on sparseness weights that are simultaneously a function of both time and frequency, reverse transform the model domain energy to the data domain, and generate an image of a surveyed subsurface based on the reverse transformed model domain energy. 16. The computing device of claim 15, wherein the sparseness weights are model or data domain sparseness weights. 17. The computing device of claim 15, wherein the sparseness weights are joint data-model domain sparseness weights and the joint data-model domain sparseness weights enable different data domain samples to be constrained by different model domain sparseness weights. 18. The computing device of claim 15, wherein more than one model domain is computed at the same time within a single inversion and an input trace is dependent on more than one model domain. 19. The computing device of claim 15, wherein sparseness weights derived based on the input data are used to derive another model domain representing a sub-set of the input dataset. 20. A non-transitory computer readable medium storing executable codes which, when executed on a computer, makes the computer perform a method for processing input seismic data d, the instructions comprising:
receiving the input seismic data d recorded in a data domain; solving a linear inversion problem constrained by input seismic data d to obtain a model domain and its energy, wherein the linear inversion problem is dependent on sparseness weights that are simultaneously a function of both time and frequency; reverse transforming the model domain energy to the data domain; and generating an image of a surveyed subsurface based on the reverse transformed model domain energy. | Computing device, computer instructions and method for processing input seismic data d. The method includes receiving the input seismic data d recorded in a data domain, solving a linear inversion problem constrained by input seismic data d to obtain a model domain and its energy, wherein the linear inversion problem is dependent on sparseness weights that are simultaneously a function of both time and frequency, reverse transforming the model domain energy to the data domain, and generating an image of a surveyed subsurface based on the reverse transformed model domain energy.1. A method for processing input seismic data d, the method comprising:
receiving the input seismic data d recorded in a data domain; solving a linear inversion problem constrained by input seismic data d to obtain a model domain and its energy, wherein the linear inversion problem is dependent on sparseness weights that are simultaneously a function of both time and frequency; reverse transforming the model domain energy to the data domain; and generating an image of a surveyed subsurface based on the reverse transformed model domain energy. 2. The method of claim 1, wherein the sparseness weights are model or data domain sparseness weights. 3. The method of claim 1, wherein the sparseness weights are joint data-model domain sparseness weights and the joint data-model domain sparseness weights enable different data domain samples to be constrained by different model domain sparseness weights. 4. The method of claim 1, wherein more than one model domain is computed at the same time within a single inversion and an input trace is dependent on more than one model domain. 5. The method of claim 1, wherein sparseness weights derived based on the input data are used to derive another model domain representing a sub-set of the input dataset. 6. The method of claim 5, wherein the seismic dataset is spatially more densely sampled than the sub-set of the input seismic dataset. 7. The method of claim 5, wherein the seismic dataset has been recorded with more seismic sensor types that the sub-set of the input seismic dataset. 8. The method of claim 1, wherein the linear inverse problem uses an iterative approach that repeatedly applies operator L to a calculated model domain and an adjoint operator LT to estimated data. 9. The method of claim 1, further comprising:
calculating a highest non-aliased frequency range; and using the sparseness weights from the highest non-aliased frequency range to define sparseness weights at higher frequencies. 10. The method of claim 1, where the linear inversion problem derives a Radon domain. 11. The method of claim 1, wherein the linear inversion problem derives a convolutional filter. 12. The method of claim 1, wherein the linear inversion problem derives an output trace. 13. The method of claim 1, wherein the sparseness weights are iteratively updated during a solution of the model domain. 14. The method of claim 1, wherein the sparseness weights are calculated by estimating an envelope of a corresponding trace in the model domain. 15. A computing device for processing input seismic data d, the computing device comprising:
an interface that receives the input seismic data d recorded in a data domain; and a processor connected to the interface and configured to, solve a linear inversion problem constrained by input seismic data d to obtain a model domain and its energy, wherein the linear inversion problem is dependent on sparseness weights that are simultaneously a function of both time and frequency, reverse transform the model domain energy to the data domain, and generate an image of a surveyed subsurface based on the reverse transformed model domain energy. 16. The computing device of claim 15, wherein the sparseness weights are model or data domain sparseness weights. 17. The computing device of claim 15, wherein the sparseness weights are joint data-model domain sparseness weights and the joint data-model domain sparseness weights enable different data domain samples to be constrained by different model domain sparseness weights. 18. The computing device of claim 15, wherein more than one model domain is computed at the same time within a single inversion and an input trace is dependent on more than one model domain. 19. The computing device of claim 15, wherein sparseness weights derived based on the input data are used to derive another model domain representing a sub-set of the input dataset. 20. A non-transitory computer readable medium storing executable codes which, when executed on a computer, makes the computer perform a method for processing input seismic data d, the instructions comprising:
receiving the input seismic data d recorded in a data domain; solving a linear inversion problem constrained by input seismic data d to obtain a model domain and its energy, wherein the linear inversion problem is dependent on sparseness weights that are simultaneously a function of both time and frequency; reverse transforming the model domain energy to the data domain; and generating an image of a surveyed subsurface based on the reverse transformed model domain energy. | 2,800 |
11,836 | 11,836 | 14,847,756 | 2,856 | An actuator system includes a piston-cylinder arrangement including a piston that is movable with respect to a cylinder. A first flow path is in fluid communication with the piston-cylinder arrangement and a second flow path is in fluid communication with the piston-cylinder arrangement. A control system is operable to fluidly connect the first flow path to a source of high-pressure fluid and to connect the second flow path to a drain to move the piston in a first direction. A pressure sensor is fluidly connected to the first flow path and is operable to measure sufficient pressure data during the movement of the piston to generate a pressure versus time curve. The control system is operable to compare the generated pressure versus time curve to a known standard pressure versus time curve stored in the control system to determine the condition of the piston-cylinder arrangement. | 1. An actuator system comprising:
a piston-cylinder arrangement including a piston that is movable with respect to a cylinder; a first flow path in fluid communication with the piston-cylinder arrangement; a second flow path in fluid communication with the piston-cylinder arrangement; a control system operable to fluidly connect the first flow path to a source of high-pressure fluid and to connect the second flow path to a drain to move the piston in a first direction; a pressure sensor fluidly connected to the first flow path and operable to measure sufficient pressure data during the movement of the piston to generate a pressure versus time curve, the control system operable to compare the generated pressure versus time curve to a known standard pressure versus time curve stored in the control system to determine the condition of the piston-cylinder arrangement. 2. The actuator system of claim 1, wherein the cylinder defines an internal space and wherein the piston divides the internal space into a first side in fluid communication with the first flow path and a second side in fluid communication with the second flow path. 3. The actuator system of claim 1, further comprising a piston seal coupled to the piston to inhibit fluid flow between the piston and the cylinder, the control system operable to predict a failure of the piston seal based on the comparison of the generated pressure versus time curve to the known standard pressure versus time curve stored in the control system. 4. The actuator system of claim 1, further comprising a shaft coupled to the piston and including a shaft seal that inhibits fluid flow between the shaft and the cylinder, the control system operable to predict a failure of the shaft seal based on the comparison of the generated pressure versus time curve to the known standard pressure versus time curve stored in the control system. 5. The actuator system of claim 1, wherein the pressure sensor is operable to measure data at a rate of at least 1000 data points per second. 6. The actuator system of claim 1, wherein the pressure sensor is operable to measure pressure data with an accuracy of plus or minus 0.01 psi. 7. The actuator system of claim 1, wherein the piston-cylinder arrangement is a pneumatic piston-cylinder arrangement. 8. The actuator system of claim 1, wherein the control system includes a microprocessor and a memory device, and wherein the known standard pressure versus time curve is generated for the piston-cylinder arrangement during one or more initial operating cycles and is stored in the memory device. 9. An actuator system comprising:
a cylinder defining an internal space and including a first fluid port disposed adjacent a first end of the space and a second fluid port adjacent the second end of the space; a piston disposed within the internal space and operable to divide the space into a first side and a second side, the first side in fluid communication with the first fluid port and the second side in fluid communication with the second fluid port; a working member coupled to the piston and operable to perform work in response to movement of the piston; a control system operable to selectively fluidly connect the first fluid port to one of a pressure source and a drain and to connect the second fluid port to the other of the drain and the pressure source to selectively move the piston away from the first port and toward the first port; and a pressure sensor in fluid communication with the first side and operable to measure pressure data during movement of the piston, the control system being operable to compare the measured pressure data to a known standard to determine the condition of the system. 10. The actuator system of claim 9, wherein the measured pressure data is compiled into a generated pressure versus time curve and the known standard includes a known standard pressure versus time curve that is stored in the control system. 11. The actuator system of claim 9, further comprising a piston seal coupled to the piston to inhibit fluid flow between the piston and the cylinder, the control system operable to predict a failure of the piston seal based on the comparison of the measured pressure data to the known standard. 12. The actuator system of claim 9, wherein the working member includes a shaft that extends through the cylinder and a shaft seal that inhibits fluid flow between the shaft and the cylinder, the control system operable to predict a failure of the shaft seal based on the comparison of the measured pressure data to the known standard. 13. The actuator system of claim 9, wherein the pressure sensor is operable to measure data at a rate of at least 1000 data points per second. 14. The actuator system of claim 9, wherein the pressure sensor is operable to measure pressure data with an accuracy of plus or minus 0.01 psi. 15. The actuator system of claim 9, wherein the piston and cylinder define a pneumatic piston-cylinder arrangement. 16. The actuator system of claim 9, wherein the control system includes a microprocessor and a memory device, and wherein the known standard is generated during one or more initial operating cycles and is stored in the memory device. 17. The actuator system of claim 9, further comprising a second pressure sensor in fluid communication with the second side and operable to measure a second set of pressure data during movement of the piston, the control system being operable to compare the second set of measured pressure data to a second known standard to determine the condition of the system. 18. A method of predicting a failure in an actuator system, the method comprising:
porting a high-pressure fluid to a first side of a piston-cylinder arrangement; draining a low-pressure fluid from a second side of the piston-cylinder arrangement to allow the piston to move with respect to the cylinder toward the second side; taking a plurality of pressure measurements of the fluid adjacent the first side during the movement of the piston; comparing the plurality of pressure measurements to a known set of pressure values; and determining if a failure is likely based on the comparison of the plurality of pressure measurements to the known set of pressure values. 19. The method of claim 18, further comprising generating the known set of pressure values during one or more initial operating cycles of the actuator system and storing the known set of pressure values in a control system. 20. The method of claim 18, further comprising taking the plurality of pressure measurements at a frequency of at least 1000 data points per second. | An actuator system includes a piston-cylinder arrangement including a piston that is movable with respect to a cylinder. A first flow path is in fluid communication with the piston-cylinder arrangement and a second flow path is in fluid communication with the piston-cylinder arrangement. A control system is operable to fluidly connect the first flow path to a source of high-pressure fluid and to connect the second flow path to a drain to move the piston in a first direction. A pressure sensor is fluidly connected to the first flow path and is operable to measure sufficient pressure data during the movement of the piston to generate a pressure versus time curve. The control system is operable to compare the generated pressure versus time curve to a known standard pressure versus time curve stored in the control system to determine the condition of the piston-cylinder arrangement.1. An actuator system comprising:
a piston-cylinder arrangement including a piston that is movable with respect to a cylinder; a first flow path in fluid communication with the piston-cylinder arrangement; a second flow path in fluid communication with the piston-cylinder arrangement; a control system operable to fluidly connect the first flow path to a source of high-pressure fluid and to connect the second flow path to a drain to move the piston in a first direction; a pressure sensor fluidly connected to the first flow path and operable to measure sufficient pressure data during the movement of the piston to generate a pressure versus time curve, the control system operable to compare the generated pressure versus time curve to a known standard pressure versus time curve stored in the control system to determine the condition of the piston-cylinder arrangement. 2. The actuator system of claim 1, wherein the cylinder defines an internal space and wherein the piston divides the internal space into a first side in fluid communication with the first flow path and a second side in fluid communication with the second flow path. 3. The actuator system of claim 1, further comprising a piston seal coupled to the piston to inhibit fluid flow between the piston and the cylinder, the control system operable to predict a failure of the piston seal based on the comparison of the generated pressure versus time curve to the known standard pressure versus time curve stored in the control system. 4. The actuator system of claim 1, further comprising a shaft coupled to the piston and including a shaft seal that inhibits fluid flow between the shaft and the cylinder, the control system operable to predict a failure of the shaft seal based on the comparison of the generated pressure versus time curve to the known standard pressure versus time curve stored in the control system. 5. The actuator system of claim 1, wherein the pressure sensor is operable to measure data at a rate of at least 1000 data points per second. 6. The actuator system of claim 1, wherein the pressure sensor is operable to measure pressure data with an accuracy of plus or minus 0.01 psi. 7. The actuator system of claim 1, wherein the piston-cylinder arrangement is a pneumatic piston-cylinder arrangement. 8. The actuator system of claim 1, wherein the control system includes a microprocessor and a memory device, and wherein the known standard pressure versus time curve is generated for the piston-cylinder arrangement during one or more initial operating cycles and is stored in the memory device. 9. An actuator system comprising:
a cylinder defining an internal space and including a first fluid port disposed adjacent a first end of the space and a second fluid port adjacent the second end of the space; a piston disposed within the internal space and operable to divide the space into a first side and a second side, the first side in fluid communication with the first fluid port and the second side in fluid communication with the second fluid port; a working member coupled to the piston and operable to perform work in response to movement of the piston; a control system operable to selectively fluidly connect the first fluid port to one of a pressure source and a drain and to connect the second fluid port to the other of the drain and the pressure source to selectively move the piston away from the first port and toward the first port; and a pressure sensor in fluid communication with the first side and operable to measure pressure data during movement of the piston, the control system being operable to compare the measured pressure data to a known standard to determine the condition of the system. 10. The actuator system of claim 9, wherein the measured pressure data is compiled into a generated pressure versus time curve and the known standard includes a known standard pressure versus time curve that is stored in the control system. 11. The actuator system of claim 9, further comprising a piston seal coupled to the piston to inhibit fluid flow between the piston and the cylinder, the control system operable to predict a failure of the piston seal based on the comparison of the measured pressure data to the known standard. 12. The actuator system of claim 9, wherein the working member includes a shaft that extends through the cylinder and a shaft seal that inhibits fluid flow between the shaft and the cylinder, the control system operable to predict a failure of the shaft seal based on the comparison of the measured pressure data to the known standard. 13. The actuator system of claim 9, wherein the pressure sensor is operable to measure data at a rate of at least 1000 data points per second. 14. The actuator system of claim 9, wherein the pressure sensor is operable to measure pressure data with an accuracy of plus or minus 0.01 psi. 15. The actuator system of claim 9, wherein the piston and cylinder define a pneumatic piston-cylinder arrangement. 16. The actuator system of claim 9, wherein the control system includes a microprocessor and a memory device, and wherein the known standard is generated during one or more initial operating cycles and is stored in the memory device. 17. The actuator system of claim 9, further comprising a second pressure sensor in fluid communication with the second side and operable to measure a second set of pressure data during movement of the piston, the control system being operable to compare the second set of measured pressure data to a second known standard to determine the condition of the system. 18. A method of predicting a failure in an actuator system, the method comprising:
porting a high-pressure fluid to a first side of a piston-cylinder arrangement; draining a low-pressure fluid from a second side of the piston-cylinder arrangement to allow the piston to move with respect to the cylinder toward the second side; taking a plurality of pressure measurements of the fluid adjacent the first side during the movement of the piston; comparing the plurality of pressure measurements to a known set of pressure values; and determining if a failure is likely based on the comparison of the plurality of pressure measurements to the known set of pressure values. 19. The method of claim 18, further comprising generating the known set of pressure values during one or more initial operating cycles of the actuator system and storing the known set of pressure values in a control system. 20. The method of claim 18, further comprising taking the plurality of pressure measurements at a frequency of at least 1000 data points per second. | 2,800 |
11,837 | 11,837 | 14,889,955 | 2,862 | A measurement device and method for determining the density and viscosity of a fluid in a downhole environment from vibration frequencies of a sample cavity. | 1. A method for determining the density and viscosity of a fluid, comprising:
receiving a fluid sample into a sample tube of a measurement device; determining a resonant frequency and Q value of the tube containing fluid; calculating a density of the fluid using the resonant frequency; calculating a viscosity of the fluid based on the density and Q value. 2. The method of claim 1, wherein the measurement device is a vibrating tube densitometer. 3. The method of claim 2, wherein the vibrating tube densitometer contains vibration source circuits that induce oscillation within a vibrating tube. 4. The method of claim 3, wherein the density and the viscosity of the fluid are calculated utilizing vibration detector circuits that measure oscillation in the vibrating tube densitometer. 5. The method of claim 4, wherein the vibration source circuits comprise electromechanical circuits. 6. The method of claim 4, wherein the vibration source circuits comprise electrical circuits. 7. The method of claim 4, wherein the vibration source circuits induce a time decaying oscillation that the vibration detector circuits record as a function of time and transform into frequency domain to yield a power spectral density from which resonance frequency and the Q value are determined. 8. The method of claim 4, wherein the vibration source circuits induce a variable frequency signal to excite the tube containing fluid into oscillation that the vibration detector circuits record as a function of the induced frequency signal, yielding a power spectral density as a function of the induced frequency signal, from which the resonance frequency and the Q value can be determined. 9. The method of claim 3, wherein a varying frequency drive signal from the vibration source circuits is used to drive the vibrating tube densitometer and a measured response allows a frequency and bandwidth of a resonant peak to be measured. 10. The method of claim 2, wherein a time varying frequency signal from the vibrating tube densitometer allows the resonant frequency to be measured and the Q value to be determined. 11. The method of claim 1, further comprising measuring Q of the fluid and calculating the viscosity of the fluid based on the relationship between Q of the fluid and density of the fluid. 12. The method of claim 1, wherein viscosity (η) of the fluid is determined by using the equation
Q
ρ
∝
1
ρη
such that
η
=
B
2
(
Q
-
A
ρ
)
2
,
where ρ is density of the fluid and A and B are the intercept and slope of the linear fit of Q/ρ plotted against 1/√{square root over (ρη)}. 13. A downhole tool comprising:
a tube that receives a sample fluid having a density; a rigid pressure housing enclosing said tube and forming an annular area between said tube and said pressure housing; a vibration source attached to said tube; at least one vibration detector; and a measurement module electrically coupled to said vibration source and said vibration detector, wherein the measurement module is configured to measure resonance frequency and Q to determine a density and a viscosity of the sample fluid using frequency and amplitude measurements of the tube; wherein said vibration source excites the tube containing fluid into oscillation; and wherein said vibration detector measures such oscillation. 14. The downhole tool of claim 13, wherein the downhole tool is a vibrating tube densitometer. 15. The downhole tool of claim 13, wherein the vibration source comprises circuits that induce oscillation within a vibrating tube. 16. The downhole tool of claim 15, wherein the circuits induce a time decaying oscillation that is recorded as a function of time and transformed into frequency domain to yield a power spectral density from which the Q value can be determined. 17. The downhole tool of claim 15, wherein the circuits induce a variable frequency signal to excite the tube containing fluid into oscillation and the response of the tube is recorded as a function of the induced frequency signal, yielding a power spectral density as a function of the induced frequency signal, from which the Q value is determined. 18. The downhole tool of claim 14, wherein a varying frequency drive signal from the vibrating tube densitometer allows the bandwidth of the resonant peak to be measured. 19. The downhole tool of claim 14, wherein a time decaying amplitude signal allows viscosity to be determined from the measured resonant frequency and Q value of a vibrating tube. 20. The downhole tool of claim 19, wherein viscosity (η) of the fluid is determined by using the equation
Q
ρ
∝
1
ρη
such that
η
=
B
2
(
Q
-
A
ρ
)
2
,
where ρ is density of the fluid and A and B are the intercept and slope of the linear fit of Q/ρ plotted against 1/√{square root over (ρη)}. | A measurement device and method for determining the density and viscosity of a fluid in a downhole environment from vibration frequencies of a sample cavity.1. A method for determining the density and viscosity of a fluid, comprising:
receiving a fluid sample into a sample tube of a measurement device; determining a resonant frequency and Q value of the tube containing fluid; calculating a density of the fluid using the resonant frequency; calculating a viscosity of the fluid based on the density and Q value. 2. The method of claim 1, wherein the measurement device is a vibrating tube densitometer. 3. The method of claim 2, wherein the vibrating tube densitometer contains vibration source circuits that induce oscillation within a vibrating tube. 4. The method of claim 3, wherein the density and the viscosity of the fluid are calculated utilizing vibration detector circuits that measure oscillation in the vibrating tube densitometer. 5. The method of claim 4, wherein the vibration source circuits comprise electromechanical circuits. 6. The method of claim 4, wherein the vibration source circuits comprise electrical circuits. 7. The method of claim 4, wherein the vibration source circuits induce a time decaying oscillation that the vibration detector circuits record as a function of time and transform into frequency domain to yield a power spectral density from which resonance frequency and the Q value are determined. 8. The method of claim 4, wherein the vibration source circuits induce a variable frequency signal to excite the tube containing fluid into oscillation that the vibration detector circuits record as a function of the induced frequency signal, yielding a power spectral density as a function of the induced frequency signal, from which the resonance frequency and the Q value can be determined. 9. The method of claim 3, wherein a varying frequency drive signal from the vibration source circuits is used to drive the vibrating tube densitometer and a measured response allows a frequency and bandwidth of a resonant peak to be measured. 10. The method of claim 2, wherein a time varying frequency signal from the vibrating tube densitometer allows the resonant frequency to be measured and the Q value to be determined. 11. The method of claim 1, further comprising measuring Q of the fluid and calculating the viscosity of the fluid based on the relationship between Q of the fluid and density of the fluid. 12. The method of claim 1, wherein viscosity (η) of the fluid is determined by using the equation
Q
ρ
∝
1
ρη
such that
η
=
B
2
(
Q
-
A
ρ
)
2
,
where ρ is density of the fluid and A and B are the intercept and slope of the linear fit of Q/ρ plotted against 1/√{square root over (ρη)}. 13. A downhole tool comprising:
a tube that receives a sample fluid having a density; a rigid pressure housing enclosing said tube and forming an annular area between said tube and said pressure housing; a vibration source attached to said tube; at least one vibration detector; and a measurement module electrically coupled to said vibration source and said vibration detector, wherein the measurement module is configured to measure resonance frequency and Q to determine a density and a viscosity of the sample fluid using frequency and amplitude measurements of the tube; wherein said vibration source excites the tube containing fluid into oscillation; and wherein said vibration detector measures such oscillation. 14. The downhole tool of claim 13, wherein the downhole tool is a vibrating tube densitometer. 15. The downhole tool of claim 13, wherein the vibration source comprises circuits that induce oscillation within a vibrating tube. 16. The downhole tool of claim 15, wherein the circuits induce a time decaying oscillation that is recorded as a function of time and transformed into frequency domain to yield a power spectral density from which the Q value can be determined. 17. The downhole tool of claim 15, wherein the circuits induce a variable frequency signal to excite the tube containing fluid into oscillation and the response of the tube is recorded as a function of the induced frequency signal, yielding a power spectral density as a function of the induced frequency signal, from which the Q value is determined. 18. The downhole tool of claim 14, wherein a varying frequency drive signal from the vibrating tube densitometer allows the bandwidth of the resonant peak to be measured. 19. The downhole tool of claim 14, wherein a time decaying amplitude signal allows viscosity to be determined from the measured resonant frequency and Q value of a vibrating tube. 20. The downhole tool of claim 19, wherein viscosity (η) of the fluid is determined by using the equation
Q
ρ
∝
1
ρη
such that
η
=
B
2
(
Q
-
A
ρ
)
2
,
where ρ is density of the fluid and A and B are the intercept and slope of the linear fit of Q/ρ plotted against 1/√{square root over (ρη)}. | 2,800 |
11,838 | 11,838 | 15,403,811 | 2,853 | Device for measuring the viscosity of a solution whose viscosity is unstable under aerobic conditions, the device being intended to be connected to a source containing the solution and including: a viscometer including a viscometer head wherefrom a module emerges; a container into which the module is immersed, mechanism for placing the interior of the container in contact with an inert gas, a purging mechanism, characterized in that the container has inlet mechanism for the solution intended to be connected to the source. | 1. A device for measuring the viscosity of a solution whose viscosity is unstable under aerobic conditions, said device being adapted to be connected to a source containing the solution and comprising:
a Brookfield viscometer comprising a viscometer head wherefrom a module emerges, the viscometer head designating an assembly containing means for rotating the module and at least one display device together with a control mechanism for the device; a container into which the module is immersed, a purging means,
characterized in that said device further comprises means for placing an interior of the container in contact with an inert gas and in that the container has inlet means for the solution adapted to be connected to the source. 2. The device according to claim 1, characterized in that the inlet means for the solution is in the form of a tube opening into one of the walls of the container. 3. The device according to claim 1, characterized in that the means for placing the interior of the container in contact with an inert gas is in the form of a sealed closure means separating the viscometer head from the opening of the container in combination with a means for supplying inert gas to the volume, separating the viscometer head at a solution level. 4. The device according to claim 3, characterized in that the sealing means is in the form of an o-ring or sleeve. 5. The device according to claim 1, characterized in that the purging means is arranged in a side wall of the container. 6. The device according to claim 1, characterized in that the means for placing the interior of the container in contact with an inert gas is in the form of a sealed enclosure within which are located the constituent module of the viscometer and the container, and into which open:
a pipe supplied with inert gas, the inlet means for the solution adapted to be connected to the source, the purging means. 7. The device according to claim 6, characterized in that the enclosure has an access door for the hands of the operator. 8. A method of analysis, in an inert atmosphere, of the viscosity of a solution whose viscosity is unstable under aerobic conditions, characterized in that the method implements the device of claim 1 and comprises the following steps:
a) Rendering inert the inside of at least the container;
b) Injecting the solution to be analyzed into the container;
c) Measuring the viscosity of the solution to be analyzed. 9. The method of analysis according to claim 8, characterized in that an oxygen content of the inert atmosphere is measured using a probe between step a) and step b). 10. A use of the device of claim 1 for measuring the viscosity of an aqueous solution of water-soluble polymer, said solution originating from a main circuit of an oil recovery installation. 11. The use of the device according to claim 10, characterized in that the device is connected directly to the main circuit of the installation within which circulates the polymer solution the viscosity of which is to be measured. 12. The use of the device according to claim 10, characterized in that the device is connected to an outlet of a discharge pipe of a sampling tank of a polymer solution sampling device, the sampling device itself being connected to the main circuit of the installation, said sampling device comprising:
A first tank, referred to as the sampling tank, for containing the collected sample, comprising:
An inlet for the aqueous polymer solution to be sampled, and a sampling line connected to said input, said sampling line being provided with a no-shear sampling valve and being designed to be connected to the main circuit and
An outlet and an outlet pipe equipped with an outlet valve and connected to the output
A second tank, referred to as the treatment tank, for containing a stabilizing solution, having an output for the stabilizing solution, a connecting pipe connected to the outlet for the stabilizing solution and equipped with a treatment valve and allowing, at least in part, for a connection between the treatment tank and the sampling tank. 13. The use of the device according to claim 12, characterized in that the device is connected to the outlet of the sampling tank discharge pipe, previously detached from the sampling device. 14. The device according to claim 2, characterized in that the inlet means for the solution is in the form of a tube opening into one of the walls of the container at the bottom of the container. | Device for measuring the viscosity of a solution whose viscosity is unstable under aerobic conditions, the device being intended to be connected to a source containing the solution and including: a viscometer including a viscometer head wherefrom a module emerges; a container into which the module is immersed, mechanism for placing the interior of the container in contact with an inert gas, a purging mechanism, characterized in that the container has inlet mechanism for the solution intended to be connected to the source.1. A device for measuring the viscosity of a solution whose viscosity is unstable under aerobic conditions, said device being adapted to be connected to a source containing the solution and comprising:
a Brookfield viscometer comprising a viscometer head wherefrom a module emerges, the viscometer head designating an assembly containing means for rotating the module and at least one display device together with a control mechanism for the device; a container into which the module is immersed, a purging means,
characterized in that said device further comprises means for placing an interior of the container in contact with an inert gas and in that the container has inlet means for the solution adapted to be connected to the source. 2. The device according to claim 1, characterized in that the inlet means for the solution is in the form of a tube opening into one of the walls of the container. 3. The device according to claim 1, characterized in that the means for placing the interior of the container in contact with an inert gas is in the form of a sealed closure means separating the viscometer head from the opening of the container in combination with a means for supplying inert gas to the volume, separating the viscometer head at a solution level. 4. The device according to claim 3, characterized in that the sealing means is in the form of an o-ring or sleeve. 5. The device according to claim 1, characterized in that the purging means is arranged in a side wall of the container. 6. The device according to claim 1, characterized in that the means for placing the interior of the container in contact with an inert gas is in the form of a sealed enclosure within which are located the constituent module of the viscometer and the container, and into which open:
a pipe supplied with inert gas, the inlet means for the solution adapted to be connected to the source, the purging means. 7. The device according to claim 6, characterized in that the enclosure has an access door for the hands of the operator. 8. A method of analysis, in an inert atmosphere, of the viscosity of a solution whose viscosity is unstable under aerobic conditions, characterized in that the method implements the device of claim 1 and comprises the following steps:
a) Rendering inert the inside of at least the container;
b) Injecting the solution to be analyzed into the container;
c) Measuring the viscosity of the solution to be analyzed. 9. The method of analysis according to claim 8, characterized in that an oxygen content of the inert atmosphere is measured using a probe between step a) and step b). 10. A use of the device of claim 1 for measuring the viscosity of an aqueous solution of water-soluble polymer, said solution originating from a main circuit of an oil recovery installation. 11. The use of the device according to claim 10, characterized in that the device is connected directly to the main circuit of the installation within which circulates the polymer solution the viscosity of which is to be measured. 12. The use of the device according to claim 10, characterized in that the device is connected to an outlet of a discharge pipe of a sampling tank of a polymer solution sampling device, the sampling device itself being connected to the main circuit of the installation, said sampling device comprising:
A first tank, referred to as the sampling tank, for containing the collected sample, comprising:
An inlet for the aqueous polymer solution to be sampled, and a sampling line connected to said input, said sampling line being provided with a no-shear sampling valve and being designed to be connected to the main circuit and
An outlet and an outlet pipe equipped with an outlet valve and connected to the output
A second tank, referred to as the treatment tank, for containing a stabilizing solution, having an output for the stabilizing solution, a connecting pipe connected to the outlet for the stabilizing solution and equipped with a treatment valve and allowing, at least in part, for a connection between the treatment tank and the sampling tank. 13. The use of the device according to claim 12, characterized in that the device is connected to the outlet of the sampling tank discharge pipe, previously detached from the sampling device. 14. The device according to claim 2, characterized in that the inlet means for the solution is in the form of a tube opening into one of the walls of the container at the bottom of the container. | 2,800 |
11,839 | 11,839 | 15,975,582 | 2,812 | An integrated circuit comprising: a source comprising an output port; a set of serially-connected resistors electrically coupled to the output port of the source; a comparator comprising a first input port, a second input port, and an output port; a set of switches, each switch in the set of switches comprising a first terminal electrically coupled to the first input port of the comparator, and a second terminal electrically coupled to the set of serially-connected resistors; a current source comprising an output port electrically coupled to the second input port of the comparator; and a pin electrically coupled to the output port of the current source. | 1. An integrated circuit comprising:
a source comprising an output port; a set of serially-connected resistors electrically coupled to the output port of the source; a comparator comprising a first input port, a second input port, and an output port; a set of switches, each switch in the set of switches comprising a first terminal electrically coupled to the first input port of the comparator, and a second terminal electrically coupled to the set of serially-connected resistors; a current source comprising an output port electrically coupled to the second input port of the comparator; and a pin electrically coupled to the output port of the current source. 2. The integrated circuit of claim 1, wherein the source is a second current source, wherein the current source is matched to the source. 3. The integrated circuit of claim 2, further comprising:
a controller electrically coupled to the set of switches to switch on and off switches in the set of switches. 4. The integrated circuit of claim 3, the controller to switch on and off switches in the set of switches to increase a voltage developed at the first input port of the comparator when the source provides current to the set of serially-connected resistors. 5. The integrated circuit of claim 3, the controller to switch on and off switches in the set of switches to decrease a voltage developed at the first input port of the comparator when the source provides current to the set of serially-connected resistors. 6. The integrated circuit of claim 1, wherein the current source is a variable current source. 7. The integrated circuit of claim 6, further comprising:
a controller electrically coupled to the set of switches and to the current source, the controller to switch on and off switches in the set of switches. 8. The integrated circuit of claim 7, the controller to:
switch on and off switches in the set of switches to increase a voltage developed at the first input port of the comparator when the source provides current to the set of serially-connected resistors; and vary the current source. 9. The integrated circuit of claim 7, the controller to:
switch on and off switches in the set of switches to decrease a voltage developed at the first input port of the comparator when the source provides current to the set of serially-connected resistors; and vary the current source. 10. An integrated circuit comprising:
a set of serially-connected resistors, the set of serially-connected resistors having a set of nodes; a source to provide a first current to the set of serially-connected resistors; a comparator comprising a first input port, a second input port, and an output port; a set of switches to couple the first input port of the comparator to the set of nodes; a pin; and a current source comprising an output port electrically coupled to the second input port of the comparator, the current source to provide a second current to the pin. 11. The integrated circuit of claim 10, wherein the source is a second current source, wherein current source is matched to the source. 12. The integrated circuit of claim 11, further comprising:
a controller to switch on and off switches in the set of switches to increase a voltage developed at the first input port of the comparator when the source provides the first current to the set of serially-connected resistors. 13. The integrated circuit of claim 11, further comprising:
a controller to switch on and off switches in the set of switches to decrease a voltage developed at the first input port of the comparator when the source provides the first current to the set of serially-connected resistors. 14. The integrated circuit of claim 10, wherein the current source is a variable current source. 15. The integrated circuit of claim 14, further comprising:
a controller electrically coupled to switch on and off switches in the set of switches to increase a voltage developed at the first input port of the comparator when the source provides current to the set of serially-connected resistors; and vary the current source. 16. The integrated circuit of claim 15, the controller to:
switch on and off switches in the set of switches to decrease a voltage developed at the first input port of the comparator when the source provides current to the set of serially-connected resistors; and vary the current source. 17. A system comprising:
an integrated circuit; a package containing the integrated circuit; and a pin mechanically coupled to the package and electrically coupled to the integrated circuit; wherein the integrated circuit comprises:
a source comprising an output port;
a set of serially-connected resistors electrically coupled to the output port of the source;
a comparator comprising a first input port, a second input port, and an output port;
a set of switches, each switch in the set of switches comprising a first terminal electrically coupled to the first input port of the comparator, and a second terminal electrically coupled to the set of serially-connected resistors; and
a current source comprising an output port electrically coupled to the second input port of the comparator and to the pin. 18. The system of claim 17, further comprising:
a controller electrically coupled to the set of switches to couple the first input port of the comparator to the set of serially-connected resistors. 19. The system of claim 18, wherein the current source is variable, the controller to vary the current source. 20. The system of claim 18, further comprising:
an external resistor electrically coupled to the pin. | An integrated circuit comprising: a source comprising an output port; a set of serially-connected resistors electrically coupled to the output port of the source; a comparator comprising a first input port, a second input port, and an output port; a set of switches, each switch in the set of switches comprising a first terminal electrically coupled to the first input port of the comparator, and a second terminal electrically coupled to the set of serially-connected resistors; a current source comprising an output port electrically coupled to the second input port of the comparator; and a pin electrically coupled to the output port of the current source.1. An integrated circuit comprising:
a source comprising an output port; a set of serially-connected resistors electrically coupled to the output port of the source; a comparator comprising a first input port, a second input port, and an output port; a set of switches, each switch in the set of switches comprising a first terminal electrically coupled to the first input port of the comparator, and a second terminal electrically coupled to the set of serially-connected resistors; a current source comprising an output port electrically coupled to the second input port of the comparator; and a pin electrically coupled to the output port of the current source. 2. The integrated circuit of claim 1, wherein the source is a second current source, wherein the current source is matched to the source. 3. The integrated circuit of claim 2, further comprising:
a controller electrically coupled to the set of switches to switch on and off switches in the set of switches. 4. The integrated circuit of claim 3, the controller to switch on and off switches in the set of switches to increase a voltage developed at the first input port of the comparator when the source provides current to the set of serially-connected resistors. 5. The integrated circuit of claim 3, the controller to switch on and off switches in the set of switches to decrease a voltage developed at the first input port of the comparator when the source provides current to the set of serially-connected resistors. 6. The integrated circuit of claim 1, wherein the current source is a variable current source. 7. The integrated circuit of claim 6, further comprising:
a controller electrically coupled to the set of switches and to the current source, the controller to switch on and off switches in the set of switches. 8. The integrated circuit of claim 7, the controller to:
switch on and off switches in the set of switches to increase a voltage developed at the first input port of the comparator when the source provides current to the set of serially-connected resistors; and vary the current source. 9. The integrated circuit of claim 7, the controller to:
switch on and off switches in the set of switches to decrease a voltage developed at the first input port of the comparator when the source provides current to the set of serially-connected resistors; and vary the current source. 10. An integrated circuit comprising:
a set of serially-connected resistors, the set of serially-connected resistors having a set of nodes; a source to provide a first current to the set of serially-connected resistors; a comparator comprising a first input port, a second input port, and an output port; a set of switches to couple the first input port of the comparator to the set of nodes; a pin; and a current source comprising an output port electrically coupled to the second input port of the comparator, the current source to provide a second current to the pin. 11. The integrated circuit of claim 10, wherein the source is a second current source, wherein current source is matched to the source. 12. The integrated circuit of claim 11, further comprising:
a controller to switch on and off switches in the set of switches to increase a voltage developed at the first input port of the comparator when the source provides the first current to the set of serially-connected resistors. 13. The integrated circuit of claim 11, further comprising:
a controller to switch on and off switches in the set of switches to decrease a voltage developed at the first input port of the comparator when the source provides the first current to the set of serially-connected resistors. 14. The integrated circuit of claim 10, wherein the current source is a variable current source. 15. The integrated circuit of claim 14, further comprising:
a controller electrically coupled to switch on and off switches in the set of switches to increase a voltage developed at the first input port of the comparator when the source provides current to the set of serially-connected resistors; and vary the current source. 16. The integrated circuit of claim 15, the controller to:
switch on and off switches in the set of switches to decrease a voltage developed at the first input port of the comparator when the source provides current to the set of serially-connected resistors; and vary the current source. 17. A system comprising:
an integrated circuit; a package containing the integrated circuit; and a pin mechanically coupled to the package and electrically coupled to the integrated circuit; wherein the integrated circuit comprises:
a source comprising an output port;
a set of serially-connected resistors electrically coupled to the output port of the source;
a comparator comprising a first input port, a second input port, and an output port;
a set of switches, each switch in the set of switches comprising a first terminal electrically coupled to the first input port of the comparator, and a second terminal electrically coupled to the set of serially-connected resistors; and
a current source comprising an output port electrically coupled to the second input port of the comparator and to the pin. 18. The system of claim 17, further comprising:
a controller electrically coupled to the set of switches to couple the first input port of the comparator to the set of serially-connected resistors. 19. The system of claim 18, wherein the current source is variable, the controller to vary the current source. 20. The system of claim 18, further comprising:
an external resistor electrically coupled to the pin. | 2,800 |
11,840 | 11,840 | 15,974,031 | 2,859 | Portable power bank system. In one embodiment, a portable power bank system may include a portable power bank and a software application. The portable power bank may include a power bank housing, one or more batteries internal to the power bank housing, and one or more electrical receptacles that are defined by the power bank housing. Each of the one or more electrical receptacles may be configured to selectively provide electrical power from the one or more batteries. The software application may include one or more computer-readable instructions that are configured, when executed by one or more processors of a portable computing device, to cause the portable computing device to communicate with the portable power bank over a wireless network to receive information regarding a current state of the portable power bank and to present the current state of the portable power bank on the portable computing device. | 1. A portable power bank system comprising:
a portable power bank including a power bank housing, one or more batteries internal to the power bank housing, and one or more electrical receptacles that are defined by and integral to the power bank housing, each of the one or more electrical receptacles configured to selectively provide electrical power from the one or more batteries to any plug that is plugged into the electrical receptacle; and a software application including one or more computer-readable instructions that are configured, when executed by one or more processors of a portable computing device, to cause the portable computing device to:
communicate with the portable power bank over a wireless network to receive information regarding a current state of the portable power bank and to present the current state of the portable power bank on the portable computing device. 2. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to control functionality of the portable power bank. 3. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to cause the portable power bank to connect to the Internet over a wireless cell phone network and then function as a mobile WiFi hotspot for other wireless devices. 4. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to turn power flow to the one or more electrical receptacles of the portable power bank on or off. 5. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
automatically communicate with the portable power bank at a preset time over the wireless network to turn power flow to the one or more electrical receptacles of the portable power bank on or off on a preset schedule. 6. The portable power bank system of claim 5, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
automatically communicate with the portable power bank at a preset time over the wireless network to present an alert on the portable computing device when the preset schedule begins and/or to present an alert on the portable computing device when the preset schedule ends. 7. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to allow a user to selectively turn off power flow to one of the one or more electrical receptacles of the portable power bank while power flow remains turned on to another one of the one or more electrical receptacles of the portable power bank. 8. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to turn power flow to the one or more electrical receptacles of the portable power bank off once a charge percentage of the portable power bank reaches or drops below a preset charge threshold. 9. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to allow a user to turn the portable power bank on or off. 10. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to present an alert on the portable computing device when a geographic position of the portable power bank changes. 11. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to present an alert on the portable computing device when the portable power bank is moved without a noticeable change in a geographic position of the portable power bank. 12. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to receive information regarding a real-time geographic position of the portable power bank as the portable power bank is moved and to present the real-time geographic position of the portable power bank on the portable computing device as the portable power bank is moved. 13. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to receive information regarding a real-time geographic position of the portable power bank as the portable power bank is moved and to present the real-time geographic position of the portable power bank on the portable computing device as the portable power bank is moved. 14. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with a remote server to remotely disable the portable power bank. 15. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with a remote server to remotely track a real-time geographic position of the portable power bank as the portable power bank is moved and to present the real-time geographic position of the portable power bank on the portable computing device as the power bank is moved. 16. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with a remote server to remotely track a real-time geographic position of the portable power bank if a person in possession of the portable power bank is missing and to present the real-time geographic position of the portable power bank on the portable computing device as the portable power bank is moved with the missing person. 17. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with a remote server to allow a user to remotely share information with other users related to a real-time geographical location of the portable power bank. 18. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with a remote server to allow a user to remotely send permission to other users over a wireless network. 19. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to present an alert on the portable computing device when a charging of the portable power bank completes. 20. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to present an alert on the portable computing device when a portable electronic device connected to the portable power bank, and being charged by the portable power bank, completes charging. | Portable power bank system. In one embodiment, a portable power bank system may include a portable power bank and a software application. The portable power bank may include a power bank housing, one or more batteries internal to the power bank housing, and one or more electrical receptacles that are defined by the power bank housing. Each of the one or more electrical receptacles may be configured to selectively provide electrical power from the one or more batteries. The software application may include one or more computer-readable instructions that are configured, when executed by one or more processors of a portable computing device, to cause the portable computing device to communicate with the portable power bank over a wireless network to receive information regarding a current state of the portable power bank and to present the current state of the portable power bank on the portable computing device.1. A portable power bank system comprising:
a portable power bank including a power bank housing, one or more batteries internal to the power bank housing, and one or more electrical receptacles that are defined by and integral to the power bank housing, each of the one or more electrical receptacles configured to selectively provide electrical power from the one or more batteries to any plug that is plugged into the electrical receptacle; and a software application including one or more computer-readable instructions that are configured, when executed by one or more processors of a portable computing device, to cause the portable computing device to:
communicate with the portable power bank over a wireless network to receive information regarding a current state of the portable power bank and to present the current state of the portable power bank on the portable computing device. 2. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to control functionality of the portable power bank. 3. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to cause the portable power bank to connect to the Internet over a wireless cell phone network and then function as a mobile WiFi hotspot for other wireless devices. 4. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to turn power flow to the one or more electrical receptacles of the portable power bank on or off. 5. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
automatically communicate with the portable power bank at a preset time over the wireless network to turn power flow to the one or more electrical receptacles of the portable power bank on or off on a preset schedule. 6. The portable power bank system of claim 5, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
automatically communicate with the portable power bank at a preset time over the wireless network to present an alert on the portable computing device when the preset schedule begins and/or to present an alert on the portable computing device when the preset schedule ends. 7. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to allow a user to selectively turn off power flow to one of the one or more electrical receptacles of the portable power bank while power flow remains turned on to another one of the one or more electrical receptacles of the portable power bank. 8. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to turn power flow to the one or more electrical receptacles of the portable power bank off once a charge percentage of the portable power bank reaches or drops below a preset charge threshold. 9. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to allow a user to turn the portable power bank on or off. 10. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to present an alert on the portable computing device when a geographic position of the portable power bank changes. 11. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to present an alert on the portable computing device when the portable power bank is moved without a noticeable change in a geographic position of the portable power bank. 12. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to receive information regarding a real-time geographic position of the portable power bank as the portable power bank is moved and to present the real-time geographic position of the portable power bank on the portable computing device as the portable power bank is moved. 13. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to receive information regarding a real-time geographic position of the portable power bank as the portable power bank is moved and to present the real-time geographic position of the portable power bank on the portable computing device as the portable power bank is moved. 14. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with a remote server to remotely disable the portable power bank. 15. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with a remote server to remotely track a real-time geographic position of the portable power bank as the portable power bank is moved and to present the real-time geographic position of the portable power bank on the portable computing device as the power bank is moved. 16. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with a remote server to remotely track a real-time geographic position of the portable power bank if a person in possession of the portable power bank is missing and to present the real-time geographic position of the portable power bank on the portable computing device as the portable power bank is moved with the missing person. 17. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with a remote server to allow a user to remotely share information with other users related to a real-time geographical location of the portable power bank. 18. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with a remote server to allow a user to remotely send permission to other users over a wireless network. 19. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to present an alert on the portable computing device when a charging of the portable power bank completes. 20. The portable power bank system of claim 1, wherein the one or more computer-readable instructions are further configured, when executed by the one or more processors of the portable computing device, to cause the portable computing device to:
communicate with the portable power bank over the wireless network to present an alert on the portable computing device when a portable electronic device connected to the portable power bank, and being charged by the portable power bank, completes charging. | 2,800 |
11,841 | 11,841 | 15,756,393 | 2,831 | The disclosure relates to a holding frame for retaining plug connector modules and for installing in plug connector housings or for screwing onto wall surfaces, wherein the plug connector modules are inserted into the holding frame and retention means on the plug connector modules interact with recesses or cut-outs provided on opposite wall parts (side parts) of the holding frame. The holding frame is formed of two halves, which are articulated to each other, and the recesses or cut-outs for retaining the plug connector modules are formed in the side parts of the holding frame as openings closed on all sides. The holding frame is folded open in order to insert the plug connector modules and then closed, wherein the plug connector modules are then interlockingly held in the holding frame by the retention means. | 1. A holding frame for retaining plug type connector modules and for installing in plug type connector housings or for screwing to wall faces,
wherein the holding frame has opposing side portions which have recesses which cooperate in order to receive the plug type connector modules, wherein the holding frame comprises two halves which are connected to each other in an articulated manner and which each include a respective one of the side portions and which are connected by two articulations, wherein the two articulations form a longitudinal axis which is orientated parallel with the side portions and about which the side portions can be rotated, and wherein securing ends are arranged with respect to the side portions of the holding frame in such a manner that, when the holding frame is screwed onto a securing face, the halves are orientated in such a manner that the side portions of the holding frame are orientated at an angle greater than 90° with respect to the securing face. 2. The holding frame as claimed in claim 1, wherein, when the holding frame is screwed onto the securing face, the side portions are orientated at an angle between 160° and 180°. 3. The holding frame as claimed in claim 1, wherein the side portions in regions which are arranged closer to the securing ends have a greater spacing with respect to each other than in regions which are arranged further from the securing ends. 4. The holding frame as claimed in claim 1, wherein the side portions are arranged at an angle greater than 90° with respect to the securing ends. 5. The holding frame as claimed in claim 1, wherein the recesses are constructed as openings which are closed at all sides in the side portions of the holding frame. | The disclosure relates to a holding frame for retaining plug connector modules and for installing in plug connector housings or for screwing onto wall surfaces, wherein the plug connector modules are inserted into the holding frame and retention means on the plug connector modules interact with recesses or cut-outs provided on opposite wall parts (side parts) of the holding frame. The holding frame is formed of two halves, which are articulated to each other, and the recesses or cut-outs for retaining the plug connector modules are formed in the side parts of the holding frame as openings closed on all sides. The holding frame is folded open in order to insert the plug connector modules and then closed, wherein the plug connector modules are then interlockingly held in the holding frame by the retention means.1. A holding frame for retaining plug type connector modules and for installing in plug type connector housings or for screwing to wall faces,
wherein the holding frame has opposing side portions which have recesses which cooperate in order to receive the plug type connector modules, wherein the holding frame comprises two halves which are connected to each other in an articulated manner and which each include a respective one of the side portions and which are connected by two articulations, wherein the two articulations form a longitudinal axis which is orientated parallel with the side portions and about which the side portions can be rotated, and wherein securing ends are arranged with respect to the side portions of the holding frame in such a manner that, when the holding frame is screwed onto a securing face, the halves are orientated in such a manner that the side portions of the holding frame are orientated at an angle greater than 90° with respect to the securing face. 2. The holding frame as claimed in claim 1, wherein, when the holding frame is screwed onto the securing face, the side portions are orientated at an angle between 160° and 180°. 3. The holding frame as claimed in claim 1, wherein the side portions in regions which are arranged closer to the securing ends have a greater spacing with respect to each other than in regions which are arranged further from the securing ends. 4. The holding frame as claimed in claim 1, wherein the side portions are arranged at an angle greater than 90° with respect to the securing ends. 5. The holding frame as claimed in claim 1, wherein the recesses are constructed as openings which are closed at all sides in the side portions of the holding frame. | 2,800 |
11,842 | 11,842 | 16,270,936 | 2,822 | A light emitting diode (LED) with a melanopic emission spectrum can comprise a primary light source and a phosphor. The primary light source can comprise an emission spectrum comprising a first peak centered at a wavelength from 480 nm to 500 nm. The phosphor, when excited, can comprise an emission spectrum with a second peak centered at a wavelength from 640 nm to 750 nm, and the intensity of the first peak is greater than the intensity of the second peak. A light emitting apparatus can comprise a first LED with a traditional white light emission spectrum, and a second LED with a melanopic emission spectrum. The light emitted from the apparatus can comprise chromaticity coordinates, in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, that are within a one-step MacAdam ellipse from the black body locus with chromaticity coordinate x from 0.34 to 0.45. | 1. A light emitting diode (LED) with a melanopic emission spectrum comprising:
a primary light source; and a phosphor, wherein: the primary light source has an emission spectrum comprising a first peak centered at a wavelength from 480 nm to 500 nm; the phosphor has an emission spectrum, when excited by the light from the primary light source, comprising a second peak centered at a wavelength from 640 nm to 750 nm; an intensity of the first peak is greater than an intensity of the second peak; and the light emitted from the LED comprises light emitted from the primary light source and the phosphor. 2. The light emitting diode of claim 1, wherein:
chromaticity coordinates (x,y) of the emission spectrum from the primary light source, in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, comprise x from 0.06 to 0.08, and y from 0.36 to 0.53; and chromaticity coordinates (x,y) of the emission spectrum from the phosphor, in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, comprise x from 0.55 to 0.68, and y from 0.31 to 0.4. 3. The light emitting diode of claim 1, wherein:
chromaticity coordinates (x,y) of the light emitted from the light emitting diode (LED), in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, comprise x from 0.22 to 0.43, and y from 0.34 to 0.47. 4. The light emitting diode of claim 1, wherein:
chromaticity coordinates (x,y) of the light emitted from the light emitting diode (LED), in the CIE 1931 color space diagram, shift in the negative x direction and the positive y direction from the chromaticity coordinates using the 1931 2° Standard Observer to the chromaticity coordinates using the 1964 10° Supplementary Standard Observer. 5. The light emitting diode of claim 4, wherein:
the shift in the chromaticity coordinates (x,y) of the light emitted from the light emitting diode (LED) between the chromaticity coordinates using the 1931 2° Standard Observer and the chromaticity coordinates using the 1964 10° Supplementary Standard Observer, in the CIE 1931 color space diagram, comprise a shift in the x-coordinate from −0.025 to −0.01, and a shift in the y-coordinate from 0.04 to 0.09. 6. The light emitting diode of claim 4, wherein:
the shift in the chromaticity coordinates (x,y) of the light emitted from the light emitting diode (LED) between the chromaticity coordinates using the 1931 2° Standard Observer and the chromaticity coordinates using the 1964 10° Supplementary Standard Observer, in the CIE 1931 color space diagram, has a magnitude greater than 0.04. 7. The light emitting diode of claim 1, wherein:
the chromaticity coordinates (x,y) of the light emitted from the light emitting diode (LED), in the CIE 1931 color space diagram, are below the black body locus using the 1931 2° Standard Observer and above the black body locus using the 1964 10° Supplementary Standard Observer. 8. The light emitting diode of claim 1, wherein:
the primary light source further comprises InGaN light emitting material; and the first peak is centered at a wavelength of 490 nm. 9. The light emitting diode of claim 1, wherein:
the phosphor further comprises CaAlSiN3:Eu2 + material. 10. A light emitting apparatus, comprising:
a first light emitting diode (LED) with an emission spectrum comprising a traditional white light emission spectrum; and a second LED with a melanopic emission spectrum comprising: a first peak centered at a wavelength from 480 nm to 500 nm; and a second peak centered at a wavelength from 640 nm to 750 nm;
wherein the intensity of the first peak is greater than the intensity of the second peak;
wherein light is emitted from the light emitting apparatus comprising light from the first and second LEDs, and the emitted light comprises chromaticity coordinates (x,y), in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, that are within a one-step MacAdam ellipse from the black body locus in the range of chromaticity coordinate x from 0.34 to 0.45. 11. The light emitting apparatus of claim 10, wherein:
the light emitted from the light emitting apparatus comprising light from the first and second LEDs, and the emitted light comprises chromaticity coordinates (x,y), in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, that are within a region bounded by the four (x,y) coordinates (0.367, 0.358), (0.373, 0.387), (0.390, 0.372), (0.401, 0.404). 12. The light emitting apparatus of claim 10, wherein:
the light emitted from the light emitting apparatus comprising light from the first and second LEDs, and the emitted light comprises chromaticity coordinates (x,y), in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, that are within a region bounded by the four (x,y) coordinates (0.389, 0.370), (0.399, 0.402), (0.415, 0.382), (0.430, 0.415). 13. The light emitting apparatus of claim 10, wherein:
the light emitted from the light emitting apparatus comprising light from the first and second LEDs, and the emitted light comprises chromaticity coordinates (x,y), in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, that are within a region bounded by the four (x,y) coordinates (0.415, 0.382), (0.437, 0.389), (0.430, 0.416), (0.456, 0.426). 14. The light emitting apparatus of claim 10, wherein:
the light emitted from the light emitting apparatus comprising light from the first and second LEDs, and the emitted light comprises chromaticity coordinates (x,y), in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, that are within a region bounded by the four (x,y) coordinates (0.437, 0.389), (0.456, 0.426), (0.481, 0.432), (0.459, 0.394). 15. The light emitting apparatus of claim 10, wherein:
chromaticity coordinates (x,y) of the first light emitting diode (LED), in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, comprise x from 0.40 to 0.42, and y from 0.38 to 0.40; and chromaticity coordinates (x,y) of the second LED, in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, comprise x from 0.22 to 0.43, and y from 0.34 to 0.47. 16. The light emitting apparatus of claim 10, wherein:
chromaticity coordinates (x,y) of the first light emitting diode (LED), in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, are within the ANSI 3500 K Bin; and chromaticity coordinates (x,y) of the second LED, in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, comprise x from 0.22 to 0.43, and y from 0.34 to 0.47. 17. The light emitting apparatus of claim 10, wherein:
chromaticity coordinates (x,y) of the first light emitting diode (LED), in the CIE 1931 color space diagram using the 1931 2° Standard Observer, are within the ANSI 3500 K Bin; and chromaticity coordinates (x,y) of the second LED, in the CIE 1931 color space diagram using the 1931 2° Standard Observer, comprise x from 0.23 to 0.45, and y from 0.28 to 0.39. 18. The light emitting apparatus of claim 10, wherein:
the second light emitting diode (LED) comprises a primary light source and a phosphor, and wherein: the primary light source has an emission spectrum comprising a peak centered at a wavelength from 480 nm to 500 nm; and the phosphor has an emission spectrum, when excited by the light from the primary light source, comprising a peak centered at a wavelength from 640 nm to 750 nm. 19. The light emitting apparatus of claim 10, wherein:
the second light emitting diode (LED) comprises a primary light source and a phosphor, and wherein: chromaticity coordinates (x,y) of the emission spectrum from the primary light source in the second LED, in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, comprise x from 0.06 to 0.08, and y from 0.36 to 0.53; and chromaticity coordinates (x,y) of the emission spectrum from the phosphor in the second LED, in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, comprise x from 0.55 to 0.68, and y from 0.31 to 0.4. 20. The light emitting apparatus of claim 10, wherein:
chromaticity coordinates (x,y) of the second light emitting diode (LED), in the CIE 1931 color space diagram, shift in the negative x direction and the positive y direction from the chromaticity coordinates using the 1931 2° Standard Observer to the chromaticity coordinates using the 1964 10° Supplementary Standard Observer. 21. The light emitting apparatus of claim 20, wherein:
the shift in the chromaticity coordinates (x,y) of the second light emitting diode (LED) between the chromaticity coordinates using the 1931 2° Standard Observer and the chromaticity coordinates using the 1964 10° Supplementary Standard Observer, in the CIE 1931 color space diagram, comprise a shift in the x-coordinate from −0.025 to −0.01, and a shift in the y-coordinate from 0.04 to 0.09. 22. The light emitting apparatus of claim 20, wherein:
the shift in the chromaticity coordinates (x,y) of the second light emitting diode (LED) between the chromaticity coordinates using the 1931 2° Standard Observer and the chromaticity coordinates using the 1964 10° Supplementary Standard Observer, in the CIE 1931 color space diagram, has a magnitude greater than 0.04. 23. The light emitting apparatus of claim 10, wherein:
the chromaticity coordinates (x,y) of the second light emitting diode (LED), in the CIE 1931 color space diagram, are below the black body locus using the 1931 2° Standard Observer and above the black body locus using the 1964 10° Supplementary Standard Observer. 24. The light emitting apparatus of claim 10, wherein:
the spectrum of the light that is emitted from the light emitting apparatus comprising light from the first and second light emitting diodes (LEDs) further comprises a global maximum from 480 nm to 500 nm. 25. The light emitting apparatus of claim 10, wherein:
the light that is emitted from the light emitting apparatus comprising light from the first and second light emitting diodes (LEDs) further comprises a color rendering index (CRI) greater than 80. 26. The light emitting apparatus of claim 10, wherein:
the light that is emitted from the light emitting apparatus comprising light from the first and second light emitting diodes (LEDs) further comprises a cyanosis observation index (COI) less than 3.3. 27. The light emitting apparatus of claim 10, wherein:
the spectrum of the light that is emitted from the light emitting apparatus comprising light from the first and second light emitting diodes (LEDs) is strongly absorbed by melanopsin and satisfies proper circadian regulation in humans. 28. The light emitting apparatus of claim 10, wherein:
the first light emitting diode (LED) with an emission spectrum comprising a traditional white light emission spectrum and the second LED with a melanopic emission spectrum are contained within a single housing or are connected to the same fixture. 29. The light emitting apparatus of claim 10, wherein:
the first light emitting diode (LED) with an emission spectrum comprising a traditional white light emission spectrum and the second LED with a melanopic emission spectrum are contained in separate housings or are connected to different fixtures. 30. The light emitting apparatus of claim 10, wherein:
the light emitted from the light emitting apparatus comprises a first intensity of light from the first LED and a second intensity of light from the second LED; and a ratio of the first intensity to the second intensity is configured such that a color rendering index (CRI) of the light emitted from the light emitting apparatus is greater than 80 and the melanopic lux equivalent (MLE) is maximized. | A light emitting diode (LED) with a melanopic emission spectrum can comprise a primary light source and a phosphor. The primary light source can comprise an emission spectrum comprising a first peak centered at a wavelength from 480 nm to 500 nm. The phosphor, when excited, can comprise an emission spectrum with a second peak centered at a wavelength from 640 nm to 750 nm, and the intensity of the first peak is greater than the intensity of the second peak. A light emitting apparatus can comprise a first LED with a traditional white light emission spectrum, and a second LED with a melanopic emission spectrum. The light emitted from the apparatus can comprise chromaticity coordinates, in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, that are within a one-step MacAdam ellipse from the black body locus with chromaticity coordinate x from 0.34 to 0.45.1. A light emitting diode (LED) with a melanopic emission spectrum comprising:
a primary light source; and a phosphor, wherein: the primary light source has an emission spectrum comprising a first peak centered at a wavelength from 480 nm to 500 nm; the phosphor has an emission spectrum, when excited by the light from the primary light source, comprising a second peak centered at a wavelength from 640 nm to 750 nm; an intensity of the first peak is greater than an intensity of the second peak; and the light emitted from the LED comprises light emitted from the primary light source and the phosphor. 2. The light emitting diode of claim 1, wherein:
chromaticity coordinates (x,y) of the emission spectrum from the primary light source, in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, comprise x from 0.06 to 0.08, and y from 0.36 to 0.53; and chromaticity coordinates (x,y) of the emission spectrum from the phosphor, in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, comprise x from 0.55 to 0.68, and y from 0.31 to 0.4. 3. The light emitting diode of claim 1, wherein:
chromaticity coordinates (x,y) of the light emitted from the light emitting diode (LED), in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, comprise x from 0.22 to 0.43, and y from 0.34 to 0.47. 4. The light emitting diode of claim 1, wherein:
chromaticity coordinates (x,y) of the light emitted from the light emitting diode (LED), in the CIE 1931 color space diagram, shift in the negative x direction and the positive y direction from the chromaticity coordinates using the 1931 2° Standard Observer to the chromaticity coordinates using the 1964 10° Supplementary Standard Observer. 5. The light emitting diode of claim 4, wherein:
the shift in the chromaticity coordinates (x,y) of the light emitted from the light emitting diode (LED) between the chromaticity coordinates using the 1931 2° Standard Observer and the chromaticity coordinates using the 1964 10° Supplementary Standard Observer, in the CIE 1931 color space diagram, comprise a shift in the x-coordinate from −0.025 to −0.01, and a shift in the y-coordinate from 0.04 to 0.09. 6. The light emitting diode of claim 4, wherein:
the shift in the chromaticity coordinates (x,y) of the light emitted from the light emitting diode (LED) between the chromaticity coordinates using the 1931 2° Standard Observer and the chromaticity coordinates using the 1964 10° Supplementary Standard Observer, in the CIE 1931 color space diagram, has a magnitude greater than 0.04. 7. The light emitting diode of claim 1, wherein:
the chromaticity coordinates (x,y) of the light emitted from the light emitting diode (LED), in the CIE 1931 color space diagram, are below the black body locus using the 1931 2° Standard Observer and above the black body locus using the 1964 10° Supplementary Standard Observer. 8. The light emitting diode of claim 1, wherein:
the primary light source further comprises InGaN light emitting material; and the first peak is centered at a wavelength of 490 nm. 9. The light emitting diode of claim 1, wherein:
the phosphor further comprises CaAlSiN3:Eu2 + material. 10. A light emitting apparatus, comprising:
a first light emitting diode (LED) with an emission spectrum comprising a traditional white light emission spectrum; and a second LED with a melanopic emission spectrum comprising: a first peak centered at a wavelength from 480 nm to 500 nm; and a second peak centered at a wavelength from 640 nm to 750 nm;
wherein the intensity of the first peak is greater than the intensity of the second peak;
wherein light is emitted from the light emitting apparatus comprising light from the first and second LEDs, and the emitted light comprises chromaticity coordinates (x,y), in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, that are within a one-step MacAdam ellipse from the black body locus in the range of chromaticity coordinate x from 0.34 to 0.45. 11. The light emitting apparatus of claim 10, wherein:
the light emitted from the light emitting apparatus comprising light from the first and second LEDs, and the emitted light comprises chromaticity coordinates (x,y), in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, that are within a region bounded by the four (x,y) coordinates (0.367, 0.358), (0.373, 0.387), (0.390, 0.372), (0.401, 0.404). 12. The light emitting apparatus of claim 10, wherein:
the light emitted from the light emitting apparatus comprising light from the first and second LEDs, and the emitted light comprises chromaticity coordinates (x,y), in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, that are within a region bounded by the four (x,y) coordinates (0.389, 0.370), (0.399, 0.402), (0.415, 0.382), (0.430, 0.415). 13. The light emitting apparatus of claim 10, wherein:
the light emitted from the light emitting apparatus comprising light from the first and second LEDs, and the emitted light comprises chromaticity coordinates (x,y), in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, that are within a region bounded by the four (x,y) coordinates (0.415, 0.382), (0.437, 0.389), (0.430, 0.416), (0.456, 0.426). 14. The light emitting apparatus of claim 10, wherein:
the light emitted from the light emitting apparatus comprising light from the first and second LEDs, and the emitted light comprises chromaticity coordinates (x,y), in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, that are within a region bounded by the four (x,y) coordinates (0.437, 0.389), (0.456, 0.426), (0.481, 0.432), (0.459, 0.394). 15. The light emitting apparatus of claim 10, wherein:
chromaticity coordinates (x,y) of the first light emitting diode (LED), in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, comprise x from 0.40 to 0.42, and y from 0.38 to 0.40; and chromaticity coordinates (x,y) of the second LED, in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, comprise x from 0.22 to 0.43, and y from 0.34 to 0.47. 16. The light emitting apparatus of claim 10, wherein:
chromaticity coordinates (x,y) of the first light emitting diode (LED), in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, are within the ANSI 3500 K Bin; and chromaticity coordinates (x,y) of the second LED, in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, comprise x from 0.22 to 0.43, and y from 0.34 to 0.47. 17. The light emitting apparatus of claim 10, wherein:
chromaticity coordinates (x,y) of the first light emitting diode (LED), in the CIE 1931 color space diagram using the 1931 2° Standard Observer, are within the ANSI 3500 K Bin; and chromaticity coordinates (x,y) of the second LED, in the CIE 1931 color space diagram using the 1931 2° Standard Observer, comprise x from 0.23 to 0.45, and y from 0.28 to 0.39. 18. The light emitting apparatus of claim 10, wherein:
the second light emitting diode (LED) comprises a primary light source and a phosphor, and wherein: the primary light source has an emission spectrum comprising a peak centered at a wavelength from 480 nm to 500 nm; and the phosphor has an emission spectrum, when excited by the light from the primary light source, comprising a peak centered at a wavelength from 640 nm to 750 nm. 19. The light emitting apparatus of claim 10, wherein:
the second light emitting diode (LED) comprises a primary light source and a phosphor, and wherein: chromaticity coordinates (x,y) of the emission spectrum from the primary light source in the second LED, in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, comprise x from 0.06 to 0.08, and y from 0.36 to 0.53; and chromaticity coordinates (x,y) of the emission spectrum from the phosphor in the second LED, in the CIE 1931 color space diagram using the 1964 10° Supplementary Standard Observer, comprise x from 0.55 to 0.68, and y from 0.31 to 0.4. 20. The light emitting apparatus of claim 10, wherein:
chromaticity coordinates (x,y) of the second light emitting diode (LED), in the CIE 1931 color space diagram, shift in the negative x direction and the positive y direction from the chromaticity coordinates using the 1931 2° Standard Observer to the chromaticity coordinates using the 1964 10° Supplementary Standard Observer. 21. The light emitting apparatus of claim 20, wherein:
the shift in the chromaticity coordinates (x,y) of the second light emitting diode (LED) between the chromaticity coordinates using the 1931 2° Standard Observer and the chromaticity coordinates using the 1964 10° Supplementary Standard Observer, in the CIE 1931 color space diagram, comprise a shift in the x-coordinate from −0.025 to −0.01, and a shift in the y-coordinate from 0.04 to 0.09. 22. The light emitting apparatus of claim 20, wherein:
the shift in the chromaticity coordinates (x,y) of the second light emitting diode (LED) between the chromaticity coordinates using the 1931 2° Standard Observer and the chromaticity coordinates using the 1964 10° Supplementary Standard Observer, in the CIE 1931 color space diagram, has a magnitude greater than 0.04. 23. The light emitting apparatus of claim 10, wherein:
the chromaticity coordinates (x,y) of the second light emitting diode (LED), in the CIE 1931 color space diagram, are below the black body locus using the 1931 2° Standard Observer and above the black body locus using the 1964 10° Supplementary Standard Observer. 24. The light emitting apparatus of claim 10, wherein:
the spectrum of the light that is emitted from the light emitting apparatus comprising light from the first and second light emitting diodes (LEDs) further comprises a global maximum from 480 nm to 500 nm. 25. The light emitting apparatus of claim 10, wherein:
the light that is emitted from the light emitting apparatus comprising light from the first and second light emitting diodes (LEDs) further comprises a color rendering index (CRI) greater than 80. 26. The light emitting apparatus of claim 10, wherein:
the light that is emitted from the light emitting apparatus comprising light from the first and second light emitting diodes (LEDs) further comprises a cyanosis observation index (COI) less than 3.3. 27. The light emitting apparatus of claim 10, wherein:
the spectrum of the light that is emitted from the light emitting apparatus comprising light from the first and second light emitting diodes (LEDs) is strongly absorbed by melanopsin and satisfies proper circadian regulation in humans. 28. The light emitting apparatus of claim 10, wherein:
the first light emitting diode (LED) with an emission spectrum comprising a traditional white light emission spectrum and the second LED with a melanopic emission spectrum are contained within a single housing or are connected to the same fixture. 29. The light emitting apparatus of claim 10, wherein:
the first light emitting diode (LED) with an emission spectrum comprising a traditional white light emission spectrum and the second LED with a melanopic emission spectrum are contained in separate housings or are connected to different fixtures. 30. The light emitting apparatus of claim 10, wherein:
the light emitted from the light emitting apparatus comprises a first intensity of light from the first LED and a second intensity of light from the second LED; and a ratio of the first intensity to the second intensity is configured such that a color rendering index (CRI) of the light emitted from the light emitting apparatus is greater than 80 and the melanopic lux equivalent (MLE) is maximized. | 2,800 |
11,843 | 11,843 | 15,714,009 | 2,837 | An improved multi-pole circuit interrupter includes an improved trip deck assembly adjacent one pole and further includes an accessory deck adjacent another pole. The accessory deck includes conventional accessory devices such as an auxiliary switch, etc., and the trip deck assembly includes switches and one or more other devices that can interact with a crossbar and a trip bar of the circuit interrupter. Such switches can be easily installed by a technician in the field after manufacture of the circuit interrupter. One switch is held in place by a support, and the other switch is held in place by a retainer, with the support and the retainer holding the switches in a fixed position on the trip deck assembly in order to interact with the crossbar and the trip bar. | 1. A support for a switch that is structured to mount the switch to a platform, the switch having a housing and further having a plunger that is movably situated on the housing, the support comprising:
a base structured to engage the housing, the base having an opening formed therein that is structured to receive therethrough at least a portion of at least one of the housing and the plunger; a number of walls situated on the base; a mounting apparatus that is structured to be usable to affix the number of walls to the platform; and a receptacle that is situated adjacent the base and the number of walls and that is structured to receive the housing therein. 2. The support of claim 1 wherein the mounting apparatus comprises a tab that is situated on the number of walls and that protrudes from the number of walls in a direction generally away from the receptacle. 3. The support of claim 1 wherein the mounting apparatus comprises a pair of tabs that are situated on the number of walls and that protrude away from one another in opposite directions. 4. A trip deck assembly comprising the support of claim 1, the trip deck assembly being structured to be usable with a circuit interrupter having a plurality of poles, a crossbar, and a trip bar, the circuit interrupter being movable among a plurality of conditions that include an ON condition, an OFF condition, and a TRIPPED condition, the trip deck assembly further comprising:
a platform apparatus upon which the mounting apparatus is situated, the platform apparatus being structured to be affixed to the circuit interrupter; a switch disposed on the support and having a housing that is situated on the base, the switch further having a plunger that is movably situated on the housing to change the switch between a first state and a second state, the plunger being structured to be in a first position engaged with the crossbar to cause the switch to be in its first state in the ON condition, the plunger being structured to be in a second position different from first position to cause the switch to be in its second state in the OFF condition and the TRIPPED condition; and another switch disposed on the platform apparatus and having another housing and further having another plunger that is movably situated on the another housing to change the another switch between a first state and a second state, the another plunger being structured to be in a first position engaged with the trip bar to cause the another switch to be in its first state in the ON condition and the OFF condition, the another plunger being structured to be in a second position different from first position to cause the another switch to be in its second state in the TRIPPED condition. 5. The trip deck assembly of claim 4 wherein the platform apparatus comprises a processing system with which the switch and the another switch are electrically connected, the processing system being structured to generate an output depending upon whether the switch is in its first state or its second state and further depending upon whether the another switch is in its first state or its second state. 6. The trip deck assembly of claim 4 wherein the platform apparatus further comprises a trip actuator structured to operatively engaged the trip bar in a number of predetermined conditions. 7. A circuit interrupter comprising the trip deck assembly of claim 4, the circuit interrupter further comprising:
a frame; a plurality of poles situated on the frame and each comprising a set of separable contacts; a crossbar situated on the frame and operatively connected with each set of separable contacts; and a trip bar situated on the frame and operatively connected with the crossbar; the circuit interrupter being movable among a plurality of conditions that include an ON condition, an OFF condition, and a TRIPPED condition; the plunger being in the first position engaged with the crossbar to cause the switch to be in its first state in the ON condition, the plunger being in the second position to cause the switch to be in its second state in the OFF condition and the TRIPPED condition; and the another plunger being in the first position engaged with the trip bar to cause the another switch to be in its first state in the ON condition and the OFF condition, the another plunger being in the second position to cause the another switch to be in its second state in the TRIPPED condition. 8. The circuit interrupter of claim 7, wherein the frame comprises an accessory deck situated adjacent a pole of the plurality of poles, the accessory deck being structured to have a number of accessory devices mounted thereon, and wherein the trip deck assembly is situated on the frame adjacent another pole of the plurality of poles. | An improved multi-pole circuit interrupter includes an improved trip deck assembly adjacent one pole and further includes an accessory deck adjacent another pole. The accessory deck includes conventional accessory devices such as an auxiliary switch, etc., and the trip deck assembly includes switches and one or more other devices that can interact with a crossbar and a trip bar of the circuit interrupter. Such switches can be easily installed by a technician in the field after manufacture of the circuit interrupter. One switch is held in place by a support, and the other switch is held in place by a retainer, with the support and the retainer holding the switches in a fixed position on the trip deck assembly in order to interact with the crossbar and the trip bar.1. A support for a switch that is structured to mount the switch to a platform, the switch having a housing and further having a plunger that is movably situated on the housing, the support comprising:
a base structured to engage the housing, the base having an opening formed therein that is structured to receive therethrough at least a portion of at least one of the housing and the plunger; a number of walls situated on the base; a mounting apparatus that is structured to be usable to affix the number of walls to the platform; and a receptacle that is situated adjacent the base and the number of walls and that is structured to receive the housing therein. 2. The support of claim 1 wherein the mounting apparatus comprises a tab that is situated on the number of walls and that protrudes from the number of walls in a direction generally away from the receptacle. 3. The support of claim 1 wherein the mounting apparatus comprises a pair of tabs that are situated on the number of walls and that protrude away from one another in opposite directions. 4. A trip deck assembly comprising the support of claim 1, the trip deck assembly being structured to be usable with a circuit interrupter having a plurality of poles, a crossbar, and a trip bar, the circuit interrupter being movable among a plurality of conditions that include an ON condition, an OFF condition, and a TRIPPED condition, the trip deck assembly further comprising:
a platform apparatus upon which the mounting apparatus is situated, the platform apparatus being structured to be affixed to the circuit interrupter; a switch disposed on the support and having a housing that is situated on the base, the switch further having a plunger that is movably situated on the housing to change the switch between a first state and a second state, the plunger being structured to be in a first position engaged with the crossbar to cause the switch to be in its first state in the ON condition, the plunger being structured to be in a second position different from first position to cause the switch to be in its second state in the OFF condition and the TRIPPED condition; and another switch disposed on the platform apparatus and having another housing and further having another plunger that is movably situated on the another housing to change the another switch between a first state and a second state, the another plunger being structured to be in a first position engaged with the trip bar to cause the another switch to be in its first state in the ON condition and the OFF condition, the another plunger being structured to be in a second position different from first position to cause the another switch to be in its second state in the TRIPPED condition. 5. The trip deck assembly of claim 4 wherein the platform apparatus comprises a processing system with which the switch and the another switch are electrically connected, the processing system being structured to generate an output depending upon whether the switch is in its first state or its second state and further depending upon whether the another switch is in its first state or its second state. 6. The trip deck assembly of claim 4 wherein the platform apparatus further comprises a trip actuator structured to operatively engaged the trip bar in a number of predetermined conditions. 7. A circuit interrupter comprising the trip deck assembly of claim 4, the circuit interrupter further comprising:
a frame; a plurality of poles situated on the frame and each comprising a set of separable contacts; a crossbar situated on the frame and operatively connected with each set of separable contacts; and a trip bar situated on the frame and operatively connected with the crossbar; the circuit interrupter being movable among a plurality of conditions that include an ON condition, an OFF condition, and a TRIPPED condition; the plunger being in the first position engaged with the crossbar to cause the switch to be in its first state in the ON condition, the plunger being in the second position to cause the switch to be in its second state in the OFF condition and the TRIPPED condition; and the another plunger being in the first position engaged with the trip bar to cause the another switch to be in its first state in the ON condition and the OFF condition, the another plunger being in the second position to cause the another switch to be in its second state in the TRIPPED condition. 8. The circuit interrupter of claim 7, wherein the frame comprises an accessory deck situated adjacent a pole of the plurality of poles, the accessory deck being structured to have a number of accessory devices mounted thereon, and wherein the trip deck assembly is situated on the frame adjacent another pole of the plurality of poles. | 2,800 |
11,844 | 11,844 | 15,679,666 | 2,899 | Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps. | 1. A semiconductor package comprising:
a semiconductor die comprising a first side and a second side; one or more bumps comprised on the first side of the wafer, the bumps comprising a first layer comprising a first metal and a second layer comprising a second metal, wherein the first layer comprises a thickness of 10 microns and the second layer comprises a thickness of 20 microns; and a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps. 2. The semiconductor package of claim 1, wherein the first metal is copper and the second metal is tin. 3. The semiconductor package of claim 1, wherein the first metal is one of silver, gold, copper, cadmium, palladium, rhodium and any combination thereof. 4. The semiconductor package of claim 1, wherein the second metal is one of tin, silver, gold, copper, cadmium, palladium, rhodium and any combination thereof. 5. A method for forming semiconductor packages, the method comprising:
providing a wafer, the wafer comprising a first side and a second side; forming a plurality of bumps on the first side of the wafer, the bumps comprising a first layer and a second layer; forming one or more grooves between the bumps on the first side of the wafer, the one or more grooves having a predetermined depth into the wafer; overmolding the plurality of bumps with a mold compound; grinding the mold compound to expose a face of the plurality of bumps; grinding the second side of the wafer to singulate a plurality of die comprised in the wafer; overmolding the second side of the wafer; and singulating the mold compound between the plurality of die to form a plurality of semiconductor packages, the plurality of die fully encapsulated within the mold compound except for the face of the plurality of bumps. 6. The method of claim 5, wherein the first layer of the bumps comprises a first metal and the second layer of the bump comprises a second metal. 7. The method of claim 5, wherein the first layer of the bumps comprises copper and the second layer of the bump comprises tin. 8. The method of claim 5, wherein the first layer of the bumps is one of silver, gold, copper, cadmium, palladium, rhodium and any combination thereof. 9. The method of claim 5, wherein the second layer of the bumps is one of tin, silver, gold, copper, cadmium, palladium, rhodium and any combination thereof. 10. The method of claim 5, wherein the first layer of the bumps comprises a thickness of 10 microns and the second layer of the bumps comprises a thickness of 20 microns. 11. The method of claim 5, wherein the overmolding comprises one of liquid dispensing, transfer molding, compression molding, and any combination thereof. 12. The method of claim 5, wherein the one or more grooves are formed through one of sawing and etching. 13. The method of claim 5, wherein one of grinding the mold compound and grinding the second side of the wafer each further comprise grinding through one of mechanical polishing and chemical mechanical planarization (CMP). 14. A method for forming semiconductor packages, the method comprising:
providing a wafer, the wafer comprising a first side and a second side; forming a first set of bumps on the first side of the wafer, the first set of bumps comprising a first metal; forming a second set of bumps on the first set of bumps, the second set of bumps comprising a second metal different from the first metal; sawing one or more grooves between the first set of bumps and the second set of bumps on the first side of the wafer; overmolding the first side of the wafer with a mold compound to encapsulate the first set of bumps and the second set of bumps; grinding the mold compound to expose a face of the second set of bumps; grinding the second side of the wafer to singulate a plurality of die comprised in the wafer; overmolding the second side of the wafer; and singulating the mold compound between the plurality of die to form a plurality of semiconductor packages, the plurality of die being fully encapsulated within the mold compound except for the face of the second set of bumps. 15. The method of claim 14, wherein the first set of the bumps comprises copper and the second set of bumps comprises tin. 16. The method of claim 14, wherein the first set of bumps is one of silver, gold, copper, cadmium, palladium, rhodium and any combination thereof. 17. The method of claim 14, wherein the second set of the bumps is one of tin, silver, gold, copper, cadmium, palladium, rhodium and any combination thereof. 18. The method of claim 14, wherein the first set of bumps comprises a thickness of 10 microns and the second set of bumps comprises a thickness of 20 microns. 19. The method of claim 14, wherein the overmolding comprises one of liquid dispensing, transfer molding, compression molding, and any combination thereof. 20. The method of claim 14, wherein one of grinding the mold compound and grinding the second side of the wafer each further comprise grinding through one of mechanical polishing and chemical mechanical planarization (CMP). | Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.1. A semiconductor package comprising:
a semiconductor die comprising a first side and a second side; one or more bumps comprised on the first side of the wafer, the bumps comprising a first layer comprising a first metal and a second layer comprising a second metal, wherein the first layer comprises a thickness of 10 microns and the second layer comprises a thickness of 20 microns; and a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps. 2. The semiconductor package of claim 1, wherein the first metal is copper and the second metal is tin. 3. The semiconductor package of claim 1, wherein the first metal is one of silver, gold, copper, cadmium, palladium, rhodium and any combination thereof. 4. The semiconductor package of claim 1, wherein the second metal is one of tin, silver, gold, copper, cadmium, palladium, rhodium and any combination thereof. 5. A method for forming semiconductor packages, the method comprising:
providing a wafer, the wafer comprising a first side and a second side; forming a plurality of bumps on the first side of the wafer, the bumps comprising a first layer and a second layer; forming one or more grooves between the bumps on the first side of the wafer, the one or more grooves having a predetermined depth into the wafer; overmolding the plurality of bumps with a mold compound; grinding the mold compound to expose a face of the plurality of bumps; grinding the second side of the wafer to singulate a plurality of die comprised in the wafer; overmolding the second side of the wafer; and singulating the mold compound between the plurality of die to form a plurality of semiconductor packages, the plurality of die fully encapsulated within the mold compound except for the face of the plurality of bumps. 6. The method of claim 5, wherein the first layer of the bumps comprises a first metal and the second layer of the bump comprises a second metal. 7. The method of claim 5, wherein the first layer of the bumps comprises copper and the second layer of the bump comprises tin. 8. The method of claim 5, wherein the first layer of the bumps is one of silver, gold, copper, cadmium, palladium, rhodium and any combination thereof. 9. The method of claim 5, wherein the second layer of the bumps is one of tin, silver, gold, copper, cadmium, palladium, rhodium and any combination thereof. 10. The method of claim 5, wherein the first layer of the bumps comprises a thickness of 10 microns and the second layer of the bumps comprises a thickness of 20 microns. 11. The method of claim 5, wherein the overmolding comprises one of liquid dispensing, transfer molding, compression molding, and any combination thereof. 12. The method of claim 5, wherein the one or more grooves are formed through one of sawing and etching. 13. The method of claim 5, wherein one of grinding the mold compound and grinding the second side of the wafer each further comprise grinding through one of mechanical polishing and chemical mechanical planarization (CMP). 14. A method for forming semiconductor packages, the method comprising:
providing a wafer, the wafer comprising a first side and a second side; forming a first set of bumps on the first side of the wafer, the first set of bumps comprising a first metal; forming a second set of bumps on the first set of bumps, the second set of bumps comprising a second metal different from the first metal; sawing one or more grooves between the first set of bumps and the second set of bumps on the first side of the wafer; overmolding the first side of the wafer with a mold compound to encapsulate the first set of bumps and the second set of bumps; grinding the mold compound to expose a face of the second set of bumps; grinding the second side of the wafer to singulate a plurality of die comprised in the wafer; overmolding the second side of the wafer; and singulating the mold compound between the plurality of die to form a plurality of semiconductor packages, the plurality of die being fully encapsulated within the mold compound except for the face of the second set of bumps. 15. The method of claim 14, wherein the first set of the bumps comprises copper and the second set of bumps comprises tin. 16. The method of claim 14, wherein the first set of bumps is one of silver, gold, copper, cadmium, palladium, rhodium and any combination thereof. 17. The method of claim 14, wherein the second set of the bumps is one of tin, silver, gold, copper, cadmium, palladium, rhodium and any combination thereof. 18. The method of claim 14, wherein the first set of bumps comprises a thickness of 10 microns and the second set of bumps comprises a thickness of 20 microns. 19. The method of claim 14, wherein the overmolding comprises one of liquid dispensing, transfer molding, compression molding, and any combination thereof. 20. The method of claim 14, wherein one of grinding the mold compound and grinding the second side of the wafer each further comprise grinding through one of mechanical polishing and chemical mechanical planarization (CMP). | 2,800 |
11,845 | 11,845 | 15,365,689 | 2,884 | The present approaches relate to the fabrication of non-rectangular (e.g., non-square) light imager panels having comparable active areas to rectangular light imager panels but manufactured using fewer c-Si wafers. Such light imager panels may be generally squircle shaped (e.g., a square or rectangle with one or more rounded corners and may be manufactured using conventional crystalline silicon (c-Si) wafers, such as 8″ wafers. | 1. A flat panel X-ray detector comprising:
a scintillator layer that converts X-ray photons into lower energy light photons; a light imager layer comprising a tiled arrangement of imager panels configured to convert the light photons into electrons, wherein at least one imager panel comprises a non-rectangular active area; a readout device that converts the electrons into digitized pixel values, and a communication unit that transfers the pixel values to an imaging system that is connected to the detector. 2. The flat panel X-ray detector of claim 1, wherein the tiled arrangement of light imager panels comprise four wedge-shaped panels tiled with two or more rectangular panels. 3. The flat panel X-ray detector of claim 1, wherein the light imager layer further comprises an electronic contract region formed along alternating quadrants of the tiled arrangement of imager panels. 4. The flat panel X-ray detector of claim 1, wherein the imager panels comprise crystalline silicon. 5. The flat panel detector of claim 4, wherein the imager panels are formed from circular crystalline silicon wafers. 6. The flat panel X-ray detector of claim 1, wherein the imager panels in the tiled arrangement are electrically connected to one another. 7. The flat panel X-ray detector of claim 1, wherein the imager panels in the tiled arrangement are not electrically connected to one another. 8. The flat panel X-ray detector of claim 1, wherein tiled arrangement comprises wherein the tiled arrangement of light imager panels comprise four wedge-shaped panels tiled with four rectangular panels. 9. A method for forming a light imager panel comprising:
dicing a silicon wafer into wedge-shaped quadrant imager tiles; separating the wedge-shaped quadrant tiles along at least one dimension; between the separated wedge-shaped quadrant tiles, positioning at least a pair of rectangular imager tiles to form a non-rectangular light imager panel configured to convert light photons into electrons. 10. The method of claim 9, wherein the non-rectangular light imager panel has a squircle shape. 11. The method of claim 9, comprising alternately forming scan circuitry and data circuitry on quadrants of the light imager panel. 12. The method of claim 9, comprising alternately connecting scan modules and data modules to quadrants of the light imager panel. 13. The method of claim 9, comprising electrically connecting the at least a portion of the wedge-shaped quadrant tiles and rectangular imager tiles. 14. The method of claim 9, wherein:
separating the separating the wedge-shaped quadrant tiles along at least one imension comprises separating the wedge-shaped quadrant tiles along orthogonal two-dimensions; and wherein positioning at least a pair of rectangular imager tiles between the separated wedge-shaped quadrant tiles comprises positioning a respective pair of rectangular imager tiles between the separated wedge-shaped quadrant tiles in each of the two dimensions. 15. A light imager panel for use in a radiation detector, the light imager panel comprising:
four wedge-shaped panels forming the rounded corners of the light imager panel; two or more rectangular panels positioned between the wedge-shaped panels to form straight edges of the light imager panel, wherein the light imager panel is configured to convert light photons into electrons. 16. The light imager panel of claim 15, wherein one or both of the wedge-shaped panels and the rectangular panels comprise an electronics connection region on the periphery of the light imager panel. 17. The light imager panel of claim 15, wherein one or both of scan circuitry or data circuitry is formed on the electronics connection regions. 18. The light imager panel of claim 15, wherein one or both of scan modules or data modules not formed on the light imager panel are connected to the electronics connection regions. 19. The light imager panel of claim 15, wherein the two or more rectangular panels comprise four rectangular panels such that a first pair of rectangular panels is positioned between the wedge-shaped panels in a first direction and a second pair of rectangular panels is positioned between the wedge-shaped panels in a second direction. 20. The light imager panel of claim 15, comprising electrical connections formed between at least a portion of the wedge-shaped panels and rectangular panels. | The present approaches relate to the fabrication of non-rectangular (e.g., non-square) light imager panels having comparable active areas to rectangular light imager panels but manufactured using fewer c-Si wafers. Such light imager panels may be generally squircle shaped (e.g., a square or rectangle with one or more rounded corners and may be manufactured using conventional crystalline silicon (c-Si) wafers, such as 8″ wafers.1. A flat panel X-ray detector comprising:
a scintillator layer that converts X-ray photons into lower energy light photons; a light imager layer comprising a tiled arrangement of imager panels configured to convert the light photons into electrons, wherein at least one imager panel comprises a non-rectangular active area; a readout device that converts the electrons into digitized pixel values, and a communication unit that transfers the pixel values to an imaging system that is connected to the detector. 2. The flat panel X-ray detector of claim 1, wherein the tiled arrangement of light imager panels comprise four wedge-shaped panels tiled with two or more rectangular panels. 3. The flat panel X-ray detector of claim 1, wherein the light imager layer further comprises an electronic contract region formed along alternating quadrants of the tiled arrangement of imager panels. 4. The flat panel X-ray detector of claim 1, wherein the imager panels comprise crystalline silicon. 5. The flat panel detector of claim 4, wherein the imager panels are formed from circular crystalline silicon wafers. 6. The flat panel X-ray detector of claim 1, wherein the imager panels in the tiled arrangement are electrically connected to one another. 7. The flat panel X-ray detector of claim 1, wherein the imager panels in the tiled arrangement are not electrically connected to one another. 8. The flat panel X-ray detector of claim 1, wherein tiled arrangement comprises wherein the tiled arrangement of light imager panels comprise four wedge-shaped panels tiled with four rectangular panels. 9. A method for forming a light imager panel comprising:
dicing a silicon wafer into wedge-shaped quadrant imager tiles; separating the wedge-shaped quadrant tiles along at least one dimension; between the separated wedge-shaped quadrant tiles, positioning at least a pair of rectangular imager tiles to form a non-rectangular light imager panel configured to convert light photons into electrons. 10. The method of claim 9, wherein the non-rectangular light imager panel has a squircle shape. 11. The method of claim 9, comprising alternately forming scan circuitry and data circuitry on quadrants of the light imager panel. 12. The method of claim 9, comprising alternately connecting scan modules and data modules to quadrants of the light imager panel. 13. The method of claim 9, comprising electrically connecting the at least a portion of the wedge-shaped quadrant tiles and rectangular imager tiles. 14. The method of claim 9, wherein:
separating the separating the wedge-shaped quadrant tiles along at least one imension comprises separating the wedge-shaped quadrant tiles along orthogonal two-dimensions; and wherein positioning at least a pair of rectangular imager tiles between the separated wedge-shaped quadrant tiles comprises positioning a respective pair of rectangular imager tiles between the separated wedge-shaped quadrant tiles in each of the two dimensions. 15. A light imager panel for use in a radiation detector, the light imager panel comprising:
four wedge-shaped panels forming the rounded corners of the light imager panel; two or more rectangular panels positioned between the wedge-shaped panels to form straight edges of the light imager panel, wherein the light imager panel is configured to convert light photons into electrons. 16. The light imager panel of claim 15, wherein one or both of the wedge-shaped panels and the rectangular panels comprise an electronics connection region on the periphery of the light imager panel. 17. The light imager panel of claim 15, wherein one or both of scan circuitry or data circuitry is formed on the electronics connection regions. 18. The light imager panel of claim 15, wherein one or both of scan modules or data modules not formed on the light imager panel are connected to the electronics connection regions. 19. The light imager panel of claim 15, wherein the two or more rectangular panels comprise four rectangular panels such that a first pair of rectangular panels is positioned between the wedge-shaped panels in a first direction and a second pair of rectangular panels is positioned between the wedge-shaped panels in a second direction. 20. The light imager panel of claim 15, comprising electrical connections formed between at least a portion of the wedge-shaped panels and rectangular panels. | 2,800 |
11,846 | 11,846 | 15,557,802 | 2,882 | A method includes exposing number of fields on a substrate, obtaining data about a field and correcting exposure of the field in subsequent exposures. The method includes defining one or more sub-fields of the field based on the obtained data. Data relating to each sub-field is processed to produce sub-field correction information. A subsequent exposure of the one or more sub-fields is corrected using the sub-field correction information. By controlling a lithographic apparatus by reference to data of a particular sub-field within a field, overlay error can be reduced or minimized for a critical feature, rather than being averaged over the whole field. By controlling a lithographic apparatus with reference to a sub-field rather than only the whole field, a residual error can be reduced in each sub-field. | 1. A lithographic method comprising:
exposing a number of fields on a substrate; obtaining data about a field; defining a sub-field of the field based on the obtained data; processing data relating to the subfield to produce sub-field correction information; and correcting exposure of the sub-field using the sub-field correction information. 2. A method according to claim 1, wherein the data obtained is a fingerprint for the field. 3. A method according to claim 2, wherein the sub-field is a line of data points in the fingerprint. 4. A method according to claim 1, wherein the data obtained further includes topography, layout, structure or simulation data. 5. A method according to claim 1, wherein the data is obtained separately from exposing or at the same time. 6. A method according to claim 1, wherein exposing involves using a reticle, and the method further comprises obtaining data about the reticle. 7. A method according to claim 1, further comprising processing all or substantially all of the data obtained to produce complete field correction information, and correcting exposure of the complete field using the complete field correction information. 8. A method according to claim 1, wherein the processing comprises applying a model to the data and the correction information comprises a set of corrections from the model. 9. A method according to claim 1, comprising:
processing data relating to a number of sub-fields to produce sub-field correction information for each sub-field; and correcting exposure of each sub-field using correction information for that sub-field. 10. A method according to claim 9, wherein exposure of number of sub-fields is corrected at the same time or one after the other. 11. A lithographic lithographic apparatus configured to perform the method according to claim 1. 12. A non-transitory computer program product containing one or more sequences of machine-readable instructions configured to control a lithographic apparatus system to:
expose a number of fields on a substrate; obtain data about a field; define a sub-field of the field based on the obtained data; process data relating to the sub-field to produce sub-field correction information; and correct exposure of the sub-field using the sub-field correction information. 13. A computer program product according to claim 12, wherein the computer program provides a user interface for use by an operator in defining one or more sub-fields. 14. A computer program product according to claim 13 wherein the user interface provides for the operator to identify one or more portions of the field where performance of the exposure is to be optimized. 15. A computer program product according to claim 13 wherein the user interface is arranged to constrain choices of sub-fields in accordance with responses of specific actuators within the particular lithographic apparatus system. 16. A computer program product according to claim 13, wherein the data obtained is a fingerprint for the field. 17. A computer program product according to claim 13, wherein the data obtained further includes topography, layout, structure or simulation data. 18. A computer program product according to claim 13, wherein exposing involves using a reticle, and the method further comprises obtaining data about the reticle. 19. A computer program product according to claim 13, wherein the instructions are further configured to cause the lithographic apparatus system to process all or substantially all of the data obtained to produce complete field correction information, and correct exposure of the complete field using the complete field correction information. 20. A computer program product according to claim 13, wherein the instructions configured to cause the processing of the data comprises instructions configured to cause application of a model to the data and the correction information comprises a set of corrections from the model. | A method includes exposing number of fields on a substrate, obtaining data about a field and correcting exposure of the field in subsequent exposures. The method includes defining one or more sub-fields of the field based on the obtained data. Data relating to each sub-field is processed to produce sub-field correction information. A subsequent exposure of the one or more sub-fields is corrected using the sub-field correction information. By controlling a lithographic apparatus by reference to data of a particular sub-field within a field, overlay error can be reduced or minimized for a critical feature, rather than being averaged over the whole field. By controlling a lithographic apparatus with reference to a sub-field rather than only the whole field, a residual error can be reduced in each sub-field.1. A lithographic method comprising:
exposing a number of fields on a substrate; obtaining data about a field; defining a sub-field of the field based on the obtained data; processing data relating to the subfield to produce sub-field correction information; and correcting exposure of the sub-field using the sub-field correction information. 2. A method according to claim 1, wherein the data obtained is a fingerprint for the field. 3. A method according to claim 2, wherein the sub-field is a line of data points in the fingerprint. 4. A method according to claim 1, wherein the data obtained further includes topography, layout, structure or simulation data. 5. A method according to claim 1, wherein the data is obtained separately from exposing or at the same time. 6. A method according to claim 1, wherein exposing involves using a reticle, and the method further comprises obtaining data about the reticle. 7. A method according to claim 1, further comprising processing all or substantially all of the data obtained to produce complete field correction information, and correcting exposure of the complete field using the complete field correction information. 8. A method according to claim 1, wherein the processing comprises applying a model to the data and the correction information comprises a set of corrections from the model. 9. A method according to claim 1, comprising:
processing data relating to a number of sub-fields to produce sub-field correction information for each sub-field; and correcting exposure of each sub-field using correction information for that sub-field. 10. A method according to claim 9, wherein exposure of number of sub-fields is corrected at the same time or one after the other. 11. A lithographic lithographic apparatus configured to perform the method according to claim 1. 12. A non-transitory computer program product containing one or more sequences of machine-readable instructions configured to control a lithographic apparatus system to:
expose a number of fields on a substrate; obtain data about a field; define a sub-field of the field based on the obtained data; process data relating to the sub-field to produce sub-field correction information; and correct exposure of the sub-field using the sub-field correction information. 13. A computer program product according to claim 12, wherein the computer program provides a user interface for use by an operator in defining one or more sub-fields. 14. A computer program product according to claim 13 wherein the user interface provides for the operator to identify one or more portions of the field where performance of the exposure is to be optimized. 15. A computer program product according to claim 13 wherein the user interface is arranged to constrain choices of sub-fields in accordance with responses of specific actuators within the particular lithographic apparatus system. 16. A computer program product according to claim 13, wherein the data obtained is a fingerprint for the field. 17. A computer program product according to claim 13, wherein the data obtained further includes topography, layout, structure or simulation data. 18. A computer program product according to claim 13, wherein exposing involves using a reticle, and the method further comprises obtaining data about the reticle. 19. A computer program product according to claim 13, wherein the instructions are further configured to cause the lithographic apparatus system to process all or substantially all of the data obtained to produce complete field correction information, and correct exposure of the complete field using the complete field correction information. 20. A computer program product according to claim 13, wherein the instructions configured to cause the processing of the data comprises instructions configured to cause application of a model to the data and the correction information comprises a set of corrections from the model. | 2,800 |
11,847 | 11,847 | 15,988,718 | 2,813 | Implementations of a method of singulating a plurality of semiconductor die may include: forming a damage layer beneath a surface of a die street where the die street connects a plurality of semiconductor die and the plurality of semiconductor die are formed on a semiconductor substrate. The method may also include sawing the die street after forming the damage layer to singulate the plurality of semiconductor die. | 1. A method of singulating a plurality of semiconductor die, the method comprising:
forming a damage layer beneath a surface of a die street, the die street connecting a plurality of semiconductor die, the plurality of semiconductor die formed on a semiconductor substrate; ablating at least a portion of the material of the die street using a laser; and sawing the die street after forming the damage layer to singulate the plurality of semiconductor die. 2. The method of claim 1, wherein the semiconductor substrate is silicon carbide. 3. The method of claim 1, wherein forming the damage layer further comprises irradiating the die street with a laser beam at a focal point within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street to form the damage layer. 4. The method of claim 1, wherein forming the damage layer further comprises:
irradiating the die street with a laser beam at a focal point at a first depth within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street; and irradiating the die street with a laser beam at a focal point at a second depth within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street. 5. (canceled) 6. The method of claim 1, further comprising before sawing the die street, ablating at least a majority of the material of the die street using a laser. 7. The method of claim 1, further comprising before sawing the die street, scribing a portion of the material of the die street using a stylus. 8. A method of singulating a plurality of semiconductor die, the method comprising:
forming a damage layer beneath a surface of a die street, the die street connecting a plurality of semiconductor die, the plurality of semiconductor die formed on a semiconductor substrate; and sawing the die street while applying sonic energy between 20 kHz to 3 GHz to a spindle coupled with a saw blade performing the sawing of the die street after forming the damage layer to singulate the plurality of semiconductor die. 9. (canceled) 10. The method of claim 8, wherein the semiconductor substrate is silicon carbide. 11. The method of claim 8, wherein forming the damage layer further comprises irradiating the die street with a laser beam at a focal point within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street to form the damage layer. 12. The method of claim 8, wherein forming the damage layer further comprises:
irradiating the die street with a laser beam at a focal point at a first depth within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street; and irradiating the die street with a laser beam at a focal point at a second depth within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street. 13. The method of claim 8, further comprising before sawing the die street, ablating at least a portion of the material of the die street using a laser. 14. The method of claim 8, further comprising before sawing the die street, ablating at least a majority of the material of the die street using a laser. 15. The method of claim 8, further comprising before sawing the die street, scribing a portion of the material of the die street using a stylus. 16. A method of singulating a plurality of semiconductor die, the method comprising:
irradiating the die street with a laser beam at a focal point within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street to form a damage layer beneath a surface of the die street, the die street connecting a plurality of semiconductor die, the plurality of semiconductor die formed on a silicon carbide semiconductor substrate; and sawing the die street using a saw blade while applying sonic energy between 20 kHz to 3 GHz to a spindle coupled with the saw blade to singulate the plurality of semiconductor die. 17. (canceled) 18. The method of claim 16, further comprising before sawing the die street, ablating at least a portion of the material of the die street using a laser. 19. The method of claim 16, further comprising before sawing the die street, scribing a portion of the material of the die street using a stylus. 20. The method of claim 16, wherein irradiating the die street with the laser beam further comprises irradiating the die street with the laser beam at the focal point at a first depth within the semiconductor substrate at the one or more spaced apart locations beneath the surface of the die street; and
irradiating the die street with the laser beam at a focal point at a second depth within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street. | Implementations of a method of singulating a plurality of semiconductor die may include: forming a damage layer beneath a surface of a die street where the die street connects a plurality of semiconductor die and the plurality of semiconductor die are formed on a semiconductor substrate. The method may also include sawing the die street after forming the damage layer to singulate the plurality of semiconductor die.1. A method of singulating a plurality of semiconductor die, the method comprising:
forming a damage layer beneath a surface of a die street, the die street connecting a plurality of semiconductor die, the plurality of semiconductor die formed on a semiconductor substrate; ablating at least a portion of the material of the die street using a laser; and sawing the die street after forming the damage layer to singulate the plurality of semiconductor die. 2. The method of claim 1, wherein the semiconductor substrate is silicon carbide. 3. The method of claim 1, wherein forming the damage layer further comprises irradiating the die street with a laser beam at a focal point within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street to form the damage layer. 4. The method of claim 1, wherein forming the damage layer further comprises:
irradiating the die street with a laser beam at a focal point at a first depth within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street; and irradiating the die street with a laser beam at a focal point at a second depth within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street. 5. (canceled) 6. The method of claim 1, further comprising before sawing the die street, ablating at least a majority of the material of the die street using a laser. 7. The method of claim 1, further comprising before sawing the die street, scribing a portion of the material of the die street using a stylus. 8. A method of singulating a plurality of semiconductor die, the method comprising:
forming a damage layer beneath a surface of a die street, the die street connecting a plurality of semiconductor die, the plurality of semiconductor die formed on a semiconductor substrate; and sawing the die street while applying sonic energy between 20 kHz to 3 GHz to a spindle coupled with a saw blade performing the sawing of the die street after forming the damage layer to singulate the plurality of semiconductor die. 9. (canceled) 10. The method of claim 8, wherein the semiconductor substrate is silicon carbide. 11. The method of claim 8, wherein forming the damage layer further comprises irradiating the die street with a laser beam at a focal point within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street to form the damage layer. 12. The method of claim 8, wherein forming the damage layer further comprises:
irradiating the die street with a laser beam at a focal point at a first depth within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street; and irradiating the die street with a laser beam at a focal point at a second depth within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street. 13. The method of claim 8, further comprising before sawing the die street, ablating at least a portion of the material of the die street using a laser. 14. The method of claim 8, further comprising before sawing the die street, ablating at least a majority of the material of the die street using a laser. 15. The method of claim 8, further comprising before sawing the die street, scribing a portion of the material of the die street using a stylus. 16. A method of singulating a plurality of semiconductor die, the method comprising:
irradiating the die street with a laser beam at a focal point within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street to form a damage layer beneath a surface of the die street, the die street connecting a plurality of semiconductor die, the plurality of semiconductor die formed on a silicon carbide semiconductor substrate; and sawing the die street using a saw blade while applying sonic energy between 20 kHz to 3 GHz to a spindle coupled with the saw blade to singulate the plurality of semiconductor die. 17. (canceled) 18. The method of claim 16, further comprising before sawing the die street, ablating at least a portion of the material of the die street using a laser. 19. The method of claim 16, further comprising before sawing the die street, scribing a portion of the material of the die street using a stylus. 20. The method of claim 16, wherein irradiating the die street with the laser beam further comprises irradiating the die street with the laser beam at the focal point at a first depth within the semiconductor substrate at the one or more spaced apart locations beneath the surface of the die street; and
irradiating the die street with the laser beam at a focal point at a second depth within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street. | 2,800 |
11,848 | 11,848 | 15,119,433 | 2,865 | The present disclosure includes a method for combining controlled and uncontrolled seismic data. The method includes accessing one or more controlled signals, each controlled signal associated with a respective receiver of a plurality of receivers. The method also includes accessing one or more uncontrolled signals, each uncontrolled signal associated with a respective receiver of the plurality of receivers. The method also includes generating one or more reconstructed signals based on the one or more uncontrolled signals. The method also includes generating a composite image based at least on the one or more controlled signals and the one or more reconstructed signals. The present disclosure may also include associated systems and apparatuses. | 1. A method for combining controlled and uncontrolled seismic data, the method comprising:
accessing one or more controlled signals, each controlled signal associated with a respective receiver of a plurality of receivers; accessing one or more uncontrolled signals, each uncontrolled signal associated with a respective receiver of the plurality of receivers; generating one or more reconstructed signals based on the one or more uncontrolled signals; and generating a composite image based at least on the one or more controlled signals and the one or more reconstructed signals. 2. The method of claim 1, wherein generating the composite image comprises:
generating a first seismic image based at least on the one or more controlled signals; generating a second seismic image based at least on the one or more reconstructed signals; and generating the composite image based at least on the first and second seismic images. 3. The method of claim 2, wherein generating the composite image comprises performing one of the following operations on the first and second seismic images:
an averaging operation; a median operation; and a summation operation. 4. The method of claim 1, wherein generating the composite image comprises performing a migration of the one or more controlled signals and the one or more reconstructed signals. 5. The method of claim 4, wherein the migration uses one of the following migration processes:
Kirchhoff migration; F-K migration; F-X migration; controlled beam migration; or reverse time migration. 6. The method of claim 1, wherein generating the one or more reconstructed signals comprises performing interferometry processing techniques on the one or more uncontrolled signals. 7. The method of claim 1, wherein the average amplitude of the one or more uncontrolled signals below a threshold frequency is greater than the average amplitude of the one or more controlled signals below the threshold frequency. 8. A system for combining controlled and uncontrolled seismic data, the system comprising:
a plurality of controlled sources; a plurality of receivers; and a computer system configured to:
access one or more controlled signals, each controlled signal recorded by a respective receiver of the plurality of receivers and associated with a controlled seismic wave generated by one or more of the controlled sources;
access one or more uncontrolled signals, each uncontrolled signal recorded by a respective receiver of the plurality of receivers;
generate one or more reconstructed signals based on the one or more uncontrolled signals; and
generate a composite image based at least on the one or more controlled signals and the one or more reconstructed signals. 9. The system of claim 8, wherein the computer system is configured to generate the composite image by:
generating a first seismic image based at least on the one or more controlled signals; generating a second seismic image based at least on the one or more reconstructed signals; and generating the composite image based at least on the first and second seismic images. 10. The system of claim 9, wherein the computer system is configured to generate the composite image by performing one of the following operations on the first and second seismic images:
an averaging operation; a median operation; or a summation operation. 11. The system of claim 8, wherein the computer system is configured to generate the composite image by performing a migration of the one or more controlled signals and the one or more reconstructed signals. 12. The system of claim 11, wherein the migration uses one of the following migration processes:
Kirchhoff migration; F-K migration; F-X migration; controlled beam migration; or reverse time migration. 13. The system of claim 8, wherein the computer system is configured to generate the one or more reconstructed signals by performing interferometry processing techniques on the one or more uncontrolled signals. 14. The system of claim 8, wherein the average amplitude of the one or more uncontrolled signals below a threshold frequency is greater than the average amplitude of the one or more controlled signals below the threshold frequency. 15. A non-transitory computer-readable medium containing instructions for combining controlled and uncontrolled seismic data, the instructions being operable, when executed by a processor, to:
access one or more controlled signals, each controlled signal recorded by a respective receiver of a plurality of receivers; access one or more uncontrolled signals, each uncontrolled signal recorded by a respective receiver of the plurality of receivers; generate one or more reconstructed signals based on the one or more uncontrolled signals; and generate a composite image based at least on the one or more controlled signals and the one or more reconstructed signals. 16. The medium of claim 15, wherein the instructions are operable to generate the composite image by:
generating a first seismic image based at least on the one or more controlled signals; generating a second seismic image based at least on the one or more reconstructed signals; and generating the composite image based at least on the first and second seismic images. 17. The medium of claim 16, wherein the instructions are operable to generate the composite image by performing one of the following operations on the first and second seismic images:
an averaging operation; a median operation; or a summation operation. 18. The medium of claim 15, wherein the instructions are operable to generate the composite image by performing a migration of the one or more controlled signals and the one or more reconstructed signals. 19. The medium of claim 18, wherein the migration uses one of the following migration processes:
Kirchhoff migration; F-K migration; F-X migration; controlled beam migration; or reverse time migration. 20. The medium of claim 15, wherein the instructions are operable to generate the one or more reconstructed signals by performing interferometry processing techniques on the one or more uncontrolled signals. | The present disclosure includes a method for combining controlled and uncontrolled seismic data. The method includes accessing one or more controlled signals, each controlled signal associated with a respective receiver of a plurality of receivers. The method also includes accessing one or more uncontrolled signals, each uncontrolled signal associated with a respective receiver of the plurality of receivers. The method also includes generating one or more reconstructed signals based on the one or more uncontrolled signals. The method also includes generating a composite image based at least on the one or more controlled signals and the one or more reconstructed signals. The present disclosure may also include associated systems and apparatuses.1. A method for combining controlled and uncontrolled seismic data, the method comprising:
accessing one or more controlled signals, each controlled signal associated with a respective receiver of a plurality of receivers; accessing one or more uncontrolled signals, each uncontrolled signal associated with a respective receiver of the plurality of receivers; generating one or more reconstructed signals based on the one or more uncontrolled signals; and generating a composite image based at least on the one or more controlled signals and the one or more reconstructed signals. 2. The method of claim 1, wherein generating the composite image comprises:
generating a first seismic image based at least on the one or more controlled signals; generating a second seismic image based at least on the one or more reconstructed signals; and generating the composite image based at least on the first and second seismic images. 3. The method of claim 2, wherein generating the composite image comprises performing one of the following operations on the first and second seismic images:
an averaging operation; a median operation; and a summation operation. 4. The method of claim 1, wherein generating the composite image comprises performing a migration of the one or more controlled signals and the one or more reconstructed signals. 5. The method of claim 4, wherein the migration uses one of the following migration processes:
Kirchhoff migration; F-K migration; F-X migration; controlled beam migration; or reverse time migration. 6. The method of claim 1, wherein generating the one or more reconstructed signals comprises performing interferometry processing techniques on the one or more uncontrolled signals. 7. The method of claim 1, wherein the average amplitude of the one or more uncontrolled signals below a threshold frequency is greater than the average amplitude of the one or more controlled signals below the threshold frequency. 8. A system for combining controlled and uncontrolled seismic data, the system comprising:
a plurality of controlled sources; a plurality of receivers; and a computer system configured to:
access one or more controlled signals, each controlled signal recorded by a respective receiver of the plurality of receivers and associated with a controlled seismic wave generated by one or more of the controlled sources;
access one or more uncontrolled signals, each uncontrolled signal recorded by a respective receiver of the plurality of receivers;
generate one or more reconstructed signals based on the one or more uncontrolled signals; and
generate a composite image based at least on the one or more controlled signals and the one or more reconstructed signals. 9. The system of claim 8, wherein the computer system is configured to generate the composite image by:
generating a first seismic image based at least on the one or more controlled signals; generating a second seismic image based at least on the one or more reconstructed signals; and generating the composite image based at least on the first and second seismic images. 10. The system of claim 9, wherein the computer system is configured to generate the composite image by performing one of the following operations on the first and second seismic images:
an averaging operation; a median operation; or a summation operation. 11. The system of claim 8, wherein the computer system is configured to generate the composite image by performing a migration of the one or more controlled signals and the one or more reconstructed signals. 12. The system of claim 11, wherein the migration uses one of the following migration processes:
Kirchhoff migration; F-K migration; F-X migration; controlled beam migration; or reverse time migration. 13. The system of claim 8, wherein the computer system is configured to generate the one or more reconstructed signals by performing interferometry processing techniques on the one or more uncontrolled signals. 14. The system of claim 8, wherein the average amplitude of the one or more uncontrolled signals below a threshold frequency is greater than the average amplitude of the one or more controlled signals below the threshold frequency. 15. A non-transitory computer-readable medium containing instructions for combining controlled and uncontrolled seismic data, the instructions being operable, when executed by a processor, to:
access one or more controlled signals, each controlled signal recorded by a respective receiver of a plurality of receivers; access one or more uncontrolled signals, each uncontrolled signal recorded by a respective receiver of the plurality of receivers; generate one or more reconstructed signals based on the one or more uncontrolled signals; and generate a composite image based at least on the one or more controlled signals and the one or more reconstructed signals. 16. The medium of claim 15, wherein the instructions are operable to generate the composite image by:
generating a first seismic image based at least on the one or more controlled signals; generating a second seismic image based at least on the one or more reconstructed signals; and generating the composite image based at least on the first and second seismic images. 17. The medium of claim 16, wherein the instructions are operable to generate the composite image by performing one of the following operations on the first and second seismic images:
an averaging operation; a median operation; or a summation operation. 18. The medium of claim 15, wherein the instructions are operable to generate the composite image by performing a migration of the one or more controlled signals and the one or more reconstructed signals. 19. The medium of claim 18, wherein the migration uses one of the following migration processes:
Kirchhoff migration; F-K migration; F-X migration; controlled beam migration; or reverse time migration. 20. The medium of claim 15, wherein the instructions are operable to generate the one or more reconstructed signals by performing interferometry processing techniques on the one or more uncontrolled signals. | 2,800 |
11,849 | 11,849 | 15,791,292 | 2,899 | The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package. | 1. A microelectronic package, comprising:
a substrate; a plurality of stacked microelectronic dies above the substrate, the plurality of stacked microelectronic dies having a bottommost microelectronic die proximate the substrate, and a next bottommost microelectronic die above the bottommost microelectronic die, wherein the bottommost microelectronic die has a plurality of front side lands on an active portion facing the substrate and a plurality of backside lands facing the next bottommost microelectronic die with a plurality of through silicon vias (TSVs) electrically coupling the backside lands and the front side lands of the bottommost microelectronic die, wherein the next bottommost microelectronic die has a plurality of front side lands facing the bottommost microelectronic die, wherein the plurality of backside lands of the bottommost microelectronic die is directly coupled to the plurality of front side lands of the next bottommost microelectronic die by a solder layer, and wherein the plurality of front side lands of the bottommost microelectronic die electrically couples the bottommost microelectronic die to the substrate, wherein the TSVs of the bottommost microelectronic die are in direct contact with the backside lands of the bottommost microelectronic die but are not in direct contact with the front side lands of the bottommost microelectronic die; an underfill material layer between the bottommost microelectronic die and the next bottommost microelectronic die; and an encapsulation material over the substrate and laterally adjacent to the bottommost microelectronic die, the next bottommost microelectronic die and the underfill material layer, wherein the encapsulation material is separate and distinct from the underfill material layer 2. The microelectronic package of claim 1, wherein the encapsulation material has an uppermost surface substantially co-planar with an uppermost surface of an uppermost microelectronic die of the plurality of stacked microelectronic dies. 3. The microelectronic package of claim 2, wherein the next bottommost microelectronic die is the uppermost microelectronic die of the plurality of stacked microelectronic dies, and wherein the uppermost surface of the encapsulation material is substantially co-planar with an uppermost surface of the next bottommost microelectronic die distal from the substrate. 4. The microelectronic package of claim 1, wherein the encapsulation material comprises a silica-filled epoxy. 5. A method of fabricating a microelectronic package, the method comprising:
forming a plurality of stacked dies comprising at least a first die and a second die above a carrier, wherein the first die has a plurality of front side lands and has a plurality of backside lands facing the second die with a plurality of through silicon vias (TSVs) electrically coupling the backside lands and the front side lands of the first die, wherein the second die has a plurality of front side lands facing the first die, wherein the plurality of backside lands of the first die is directly coupled to the plurality of front side lands of the second die by a solder layer; subsequent to forming the plurality of stacked dies, forming an underfill material layer between the first die and the second die; subsequent to forming the underfill material layer, forming an encapsulation material over the carrier and laterally adjacent to the first die, the second die and the underfill material layer; subsequent to forming the encapsulation material, forming a substrate over the encapsulation material, wherein the plurality of front side lands of the first die electrically couples the first die to the substrate; and removing the carrier. 6. The method of claim 5, wherein forming the encapsulation material comprises forming a silica-filled epoxy. 7. The method of claim 5, wherein the encapsulation material has a lowermost surface substantially co-planar with a lowermost surface of a lowermost die of the plurality of stacked dies. 8. The method of claim 7, wherein the second die is the lowermost die of the plurality of stacked dies, and wherein the lowermost surface of the encapsulation material is substantially co-planar with lowermost surface of the second die proximate the carrier. 9. The method of claim 5, wherein the TSVs of the first die are in direct contact with the backside lands of the bottommost die but are not in direct contact with the front side lands of the bottommost die. 10. A microelectronic package, comprising:
a substrate; a plurality of stacked dies above the substrate, the plurality of stacked dies having a bottommost die proximate the substrate, and a next bottommost die above the bottommost die, wherein the bottommost die has a plurality of front side lands facing the substrate and a plurality of backside lands facing the next bottommost die with a plurality of through silicon vias (TSVs) electrically coupling the backside lands and the front side lands of the bottommost die, wherein the next bottommost die has a plurality of front side lands facing the bottommost die, wherein the plurality of backside lands of the bottommost die is directly coupled to the plurality of front side lands of the next bottommost die by a solder layer, and wherein the plurality of front side lands of the bottommost die electrically couples the bottommost die to the substrate, wherein the TSVs of the bottommost die are in direct contact with the backside lands of the bottommost die but are not in direct contact with the front side lands of the bottommost die; an underfill material layer between the bottommost die and the next bottommost die; and an encapsulation material over the substrate and laterally adjacent to the bottommost die, the next bottommost die and the underfill material layer, wherein the encapsulation material is separate and distinct from the underfill material layer. | The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.1. A microelectronic package, comprising:
a substrate; a plurality of stacked microelectronic dies above the substrate, the plurality of stacked microelectronic dies having a bottommost microelectronic die proximate the substrate, and a next bottommost microelectronic die above the bottommost microelectronic die, wherein the bottommost microelectronic die has a plurality of front side lands on an active portion facing the substrate and a plurality of backside lands facing the next bottommost microelectronic die with a plurality of through silicon vias (TSVs) electrically coupling the backside lands and the front side lands of the bottommost microelectronic die, wherein the next bottommost microelectronic die has a plurality of front side lands facing the bottommost microelectronic die, wherein the plurality of backside lands of the bottommost microelectronic die is directly coupled to the plurality of front side lands of the next bottommost microelectronic die by a solder layer, and wherein the plurality of front side lands of the bottommost microelectronic die electrically couples the bottommost microelectronic die to the substrate, wherein the TSVs of the bottommost microelectronic die are in direct contact with the backside lands of the bottommost microelectronic die but are not in direct contact with the front side lands of the bottommost microelectronic die; an underfill material layer between the bottommost microelectronic die and the next bottommost microelectronic die; and an encapsulation material over the substrate and laterally adjacent to the bottommost microelectronic die, the next bottommost microelectronic die and the underfill material layer, wherein the encapsulation material is separate and distinct from the underfill material layer 2. The microelectronic package of claim 1, wherein the encapsulation material has an uppermost surface substantially co-planar with an uppermost surface of an uppermost microelectronic die of the plurality of stacked microelectronic dies. 3. The microelectronic package of claim 2, wherein the next bottommost microelectronic die is the uppermost microelectronic die of the plurality of stacked microelectronic dies, and wherein the uppermost surface of the encapsulation material is substantially co-planar with an uppermost surface of the next bottommost microelectronic die distal from the substrate. 4. The microelectronic package of claim 1, wherein the encapsulation material comprises a silica-filled epoxy. 5. A method of fabricating a microelectronic package, the method comprising:
forming a plurality of stacked dies comprising at least a first die and a second die above a carrier, wherein the first die has a plurality of front side lands and has a plurality of backside lands facing the second die with a plurality of through silicon vias (TSVs) electrically coupling the backside lands and the front side lands of the first die, wherein the second die has a plurality of front side lands facing the first die, wherein the plurality of backside lands of the first die is directly coupled to the plurality of front side lands of the second die by a solder layer; subsequent to forming the plurality of stacked dies, forming an underfill material layer between the first die and the second die; subsequent to forming the underfill material layer, forming an encapsulation material over the carrier and laterally adjacent to the first die, the second die and the underfill material layer; subsequent to forming the encapsulation material, forming a substrate over the encapsulation material, wherein the plurality of front side lands of the first die electrically couples the first die to the substrate; and removing the carrier. 6. The method of claim 5, wherein forming the encapsulation material comprises forming a silica-filled epoxy. 7. The method of claim 5, wherein the encapsulation material has a lowermost surface substantially co-planar with a lowermost surface of a lowermost die of the plurality of stacked dies. 8. The method of claim 7, wherein the second die is the lowermost die of the plurality of stacked dies, and wherein the lowermost surface of the encapsulation material is substantially co-planar with lowermost surface of the second die proximate the carrier. 9. The method of claim 5, wherein the TSVs of the first die are in direct contact with the backside lands of the bottommost die but are not in direct contact with the front side lands of the bottommost die. 10. A microelectronic package, comprising:
a substrate; a plurality of stacked dies above the substrate, the plurality of stacked dies having a bottommost die proximate the substrate, and a next bottommost die above the bottommost die, wherein the bottommost die has a plurality of front side lands facing the substrate and a plurality of backside lands facing the next bottommost die with a plurality of through silicon vias (TSVs) electrically coupling the backside lands and the front side lands of the bottommost die, wherein the next bottommost die has a plurality of front side lands facing the bottommost die, wherein the plurality of backside lands of the bottommost die is directly coupled to the plurality of front side lands of the next bottommost die by a solder layer, and wherein the plurality of front side lands of the bottommost die electrically couples the bottommost die to the substrate, wherein the TSVs of the bottommost die are in direct contact with the backside lands of the bottommost die but are not in direct contact with the front side lands of the bottommost die; an underfill material layer between the bottommost die and the next bottommost die; and an encapsulation material over the substrate and laterally adjacent to the bottommost die, the next bottommost die and the underfill material layer, wherein the encapsulation material is separate and distinct from the underfill material layer. | 2,800 |
11,850 | 11,850 | 16,029,444 | 2,896 | A wireless power transmission (WPT) system. Implementations may include a power source coupled with a first wireless power transmission (WPT) system and a load coupled with a second WPT system including a sense circuit. The second WPT system, using the sense circuit, may be configured to dynamically tune a resonance of the second WPT system with the first WPT system to a desired resonance frequency value to allow transfer of a desired voltage or a desired power to the load. The desired resonance frequency value may be less than a maximum possible resonance frequency value. The first WPT system may be capable of transmitting more voltage or more power than the second WPT system or the load can receive without inducing damage to the second WPT system or the load. | 1. A method of wireless power transmission, the method comprising:
providing a power source coupled with a first wireless power transmission (WPT) system; providing a load coupled with a second WPT system; and detuning a resonance of the second WPT system with the first WPT system to a desired resonance frequency value to allow transfer of one of a desired voltage and a desired power to the load without damaging one of the second WPT system and the load. 2. The method of claim 1, wherein tuning the resonance of the second WPT system with the first WPT system further comprises adjusting one of a frequency transmitted by the first WPT system and a frequency received by the second WPT system. 3. The method of claim 1, wherein tuning the resonance of the second WPT system with the first WPT system further comprises adjusting a capacitance of the second WPT system. 4. The method of claim 1, further comprising:
providing a second load coupled with a third WPT system; and detuning a resonance of the third WPT system with the first WPT system to a desired resonance frequency value to allow transfer of one of a desired voltage and a desired power to the second load without damaging one of the third WPT system and the second load. 5. The method of claim 1, further comprising:
providing a second load coupled with a third WPT system wherein the third WPT system and second load are adapted to operate at the maximum possible resonance frequency value without inducing damage to the third WPT system and the second load. 6. The method of claim 1, wherein the second WPT system comprises a sense circuit and tuning the resonance of the second WPT system with the first WPT system further comprises tuning using the sense circuit. 7. The method of claim 6, wherein tuning using the sense circuit further comprises tuning by adjusting one of a frequency transmitted by the first WPT system and a frequency received by the second WPT system using the sense circuit. 8. The method of claim 6, wherein tuning using the sense circuit further comprises tuning by adjusting a capacitance of the second WPT system using the sense circuit. 9. The method of claim 1, wherein the second WPT system comprises a two stage resonator comprising a first coil and a second coil and tuning the resonance of the second WPT system with the first WPT system further comprises detuning of one of the first coil and the second coil to the desired resonance frequency value. 10. The method of claim 1, wherein the second WPT system comprises a single stage resonator comprising a first coil and tuning the resonance of the second WPT system with the first WPT system further comprises detuning of the first coil to the desired resonance frequency value. 11. The method of claim 1, wherein tuning the resonance of the second WPT system with the first WPT system further comprises tuning after completion of an initial wireless power transmission through one of:
transmitting a feedback signal to the first WPT system to tune a resonance of the first WPT system; and tuning the resonance of the second WPT system using a sense circuit comprised in the second WPT system. 12. A method of wireless power transmission, the method comprising:
providing a power source coupled with a first wireless power transmission (WPT) system; providing a load coupled with a second WPT system; and dynamically detuning a resonance of the second WPT system with the first WPT system to a desired resonance frequency value to allow transfer of one of a desired voltage and a desired power to the load without damaging one of the second WPT system and the load. 13. The method of claim 12, wherein dynamically tuning the resonance of the second WPT system with the first WPT system further comprises tuning after completion of an initial wireless power transmission through transmitting a feedback signal from the second WPT system to the first WPT system to tune a resonance of the first WPT system. 14. The method of claim 13, further comprising tuning through adjusting a frequency transmitted by the first WPT system in response to receiving the feedback signal from the second WPT system. 15. The method of claim 12, wherein dynamically tuning the resonance of the second WPT system with the first WPT system further comprises tuning after completion of an initial wireless power transmission through tuning the resonance of the second WPT system using a sense circuit comprised in the second WPT system wherein the sense circuit adjusts one of a frequency received by the second WPT system, a capacitance of the second WPT system; and any combination thereof. 16. A wireless power transmission system comprising:
a power source coupled with a first wireless power transmission (WPT) system; and a load coupled with a second WPT system; wherein the second WPT system is configured to detune a resonance of the second WPT system with the first WPT system to a desired resonance frequency value to allow transfer of one of a desired voltage and a desired power to the load without damaging one of the second WPT system and the load. 17. The system of claim 16, wherein the sense circuit is configured to tune a resonance of the second WPT system with the first WPT system through adjusting one of a frequency transmitted by the first WPT system and a frequency received by the second WPT system. 18. The system of claim 16, further comprising a sense circuit, wherein the sense circuit is configured to dynamically detune a resonance of the second WPT system with the first WPT system. 19. The system of claim 18, wherein the sense circuit is configured to adjust a capacitance of the second WPT system through adjusting a voltage bias of a voltage dependent capacitor comprised in the second WPT system using the sense circuit. 20. The system of claim 16, wherein the second WPT system comprises at least one stage comprising at least a first coil and a sense circuit is configured to tune a resonance of the second WPT system with the first WPT system through detuning of the at least first coil to the desired resonance frequency value. | A wireless power transmission (WPT) system. Implementations may include a power source coupled with a first wireless power transmission (WPT) system and a load coupled with a second WPT system including a sense circuit. The second WPT system, using the sense circuit, may be configured to dynamically tune a resonance of the second WPT system with the first WPT system to a desired resonance frequency value to allow transfer of a desired voltage or a desired power to the load. The desired resonance frequency value may be less than a maximum possible resonance frequency value. The first WPT system may be capable of transmitting more voltage or more power than the second WPT system or the load can receive without inducing damage to the second WPT system or the load.1. A method of wireless power transmission, the method comprising:
providing a power source coupled with a first wireless power transmission (WPT) system; providing a load coupled with a second WPT system; and detuning a resonance of the second WPT system with the first WPT system to a desired resonance frequency value to allow transfer of one of a desired voltage and a desired power to the load without damaging one of the second WPT system and the load. 2. The method of claim 1, wherein tuning the resonance of the second WPT system with the first WPT system further comprises adjusting one of a frequency transmitted by the first WPT system and a frequency received by the second WPT system. 3. The method of claim 1, wherein tuning the resonance of the second WPT system with the first WPT system further comprises adjusting a capacitance of the second WPT system. 4. The method of claim 1, further comprising:
providing a second load coupled with a third WPT system; and detuning a resonance of the third WPT system with the first WPT system to a desired resonance frequency value to allow transfer of one of a desired voltage and a desired power to the second load without damaging one of the third WPT system and the second load. 5. The method of claim 1, further comprising:
providing a second load coupled with a third WPT system wherein the third WPT system and second load are adapted to operate at the maximum possible resonance frequency value without inducing damage to the third WPT system and the second load. 6. The method of claim 1, wherein the second WPT system comprises a sense circuit and tuning the resonance of the second WPT system with the first WPT system further comprises tuning using the sense circuit. 7. The method of claim 6, wherein tuning using the sense circuit further comprises tuning by adjusting one of a frequency transmitted by the first WPT system and a frequency received by the second WPT system using the sense circuit. 8. The method of claim 6, wherein tuning using the sense circuit further comprises tuning by adjusting a capacitance of the second WPT system using the sense circuit. 9. The method of claim 1, wherein the second WPT system comprises a two stage resonator comprising a first coil and a second coil and tuning the resonance of the second WPT system with the first WPT system further comprises detuning of one of the first coil and the second coil to the desired resonance frequency value. 10. The method of claim 1, wherein the second WPT system comprises a single stage resonator comprising a first coil and tuning the resonance of the second WPT system with the first WPT system further comprises detuning of the first coil to the desired resonance frequency value. 11. The method of claim 1, wherein tuning the resonance of the second WPT system with the first WPT system further comprises tuning after completion of an initial wireless power transmission through one of:
transmitting a feedback signal to the first WPT system to tune a resonance of the first WPT system; and tuning the resonance of the second WPT system using a sense circuit comprised in the second WPT system. 12. A method of wireless power transmission, the method comprising:
providing a power source coupled with a first wireless power transmission (WPT) system; providing a load coupled with a second WPT system; and dynamically detuning a resonance of the second WPT system with the first WPT system to a desired resonance frequency value to allow transfer of one of a desired voltage and a desired power to the load without damaging one of the second WPT system and the load. 13. The method of claim 12, wherein dynamically tuning the resonance of the second WPT system with the first WPT system further comprises tuning after completion of an initial wireless power transmission through transmitting a feedback signal from the second WPT system to the first WPT system to tune a resonance of the first WPT system. 14. The method of claim 13, further comprising tuning through adjusting a frequency transmitted by the first WPT system in response to receiving the feedback signal from the second WPT system. 15. The method of claim 12, wherein dynamically tuning the resonance of the second WPT system with the first WPT system further comprises tuning after completion of an initial wireless power transmission through tuning the resonance of the second WPT system using a sense circuit comprised in the second WPT system wherein the sense circuit adjusts one of a frequency received by the second WPT system, a capacitance of the second WPT system; and any combination thereof. 16. A wireless power transmission system comprising:
a power source coupled with a first wireless power transmission (WPT) system; and a load coupled with a second WPT system; wherein the second WPT system is configured to detune a resonance of the second WPT system with the first WPT system to a desired resonance frequency value to allow transfer of one of a desired voltage and a desired power to the load without damaging one of the second WPT system and the load. 17. The system of claim 16, wherein the sense circuit is configured to tune a resonance of the second WPT system with the first WPT system through adjusting one of a frequency transmitted by the first WPT system and a frequency received by the second WPT system. 18. The system of claim 16, further comprising a sense circuit, wherein the sense circuit is configured to dynamically detune a resonance of the second WPT system with the first WPT system. 19. The system of claim 18, wherein the sense circuit is configured to adjust a capacitance of the second WPT system through adjusting a voltage bias of a voltage dependent capacitor comprised in the second WPT system using the sense circuit. 20. The system of claim 16, wherein the second WPT system comprises at least one stage comprising at least a first coil and a sense circuit is configured to tune a resonance of the second WPT system with the first WPT system through detuning of the at least first coil to the desired resonance frequency value. | 2,800 |
11,851 | 11,851 | 15,503,241 | 2,858 | A position sensor for sensing a position of a magnetic object, including: a planar coil; a magnetizable element which covers at least part of the planar coil and can be magnetized by the magnetic object, whereby an impedance of the planar coil can be varied; and a processor for determining the position of the magnetic object in accordance with the impedance for the planar coil. | 1. A position sensor for detecting a position of a magnetic object, comprising:
a planar coil; a magnetizable element which at least partially covers the planar coil and can be magnetized by the magnetic object, as a result of which an impedance of the planar coil can be changed; and a processor for determining the position of the magnetic object on the basis of the impedance of the planar coil. 2. The position sensor as claimed in claim 1, the magnetizable element being arranged between the planar coil and the magnetic object. 3. The position sensor as claimed in claim 1, the planar coil having a meandering shape, a rectangular shape, a trapezoidal shape or a triangular shape. 4. The position sensor as claimed claim 1, the planar coil being arranged on a printed circuit board. 5. The position sensor as claimed in claim 4, the magnetizable element being arranged on the printed circuit board, by solder or an adhesive bond. 6. The position sensor as claimed in claim 1, the processor being designed to detect a resistance or a reactance of the planar coil. 7. The position sensor as claimed in claim 1, the magnetizable element comprising a ferromagnetic portion. 8. The position sensor as claimed in claim 1, the magnetizable element comprising ferrite, steel, transformer laminate or a highly permeable alloy. 9. The position sensor as claimed in claim 1, the magnetizable element having a rectangular shape, a trapezoidal shape or a triangular shape. 10. The position sensor as claimed in claim 1, having an insulation element which is arranged between the planar coil and the magnetizable element in order to electrically insulate the planar coil and the magnetizable element from one another. 11. The position sensor as claimed in claim 1, having a number of distributed magnetizable elements arranged in a row on the planar coil, a distance between two adjacent magnetizable elements of the number of distributed magnetizable elements increasing or decreasing along the row. 12. The position sensor as claimed in claim 1, having a number of distributed magnetizable elements arranged in a row on the planar coil, a length or a width of the magnetizable elements of the number of distributed magnetizable elements increasing or decreasing along the row. 13. The position sensor as claimed in claim 1, having a number of distributed magnetizable elements arranged in a row on the planar coil, the magnetizable elements of the number of distributed magnetizable elements being mechanically connected to one another a web. 14. The position sensor as claimed in claim 1, having a number of distributed magnetizable elements arranged in a row on the planar coil, the number of distributed magnetizable elements being arranged on a carrier film. 15. The position sensor as claimed in claim 1, the processor also being designed to determine the position of the magnetic object on the basis of an eddy current loss value of the planar coil. 16. The position sensor as claimed in claim 2, the planar coil having a meandering shape, a rectangular shape, a trapezoidal shape or a triangular shape. | A position sensor for sensing a position of a magnetic object, including: a planar coil; a magnetizable element which covers at least part of the planar coil and can be magnetized by the magnetic object, whereby an impedance of the planar coil can be varied; and a processor for determining the position of the magnetic object in accordance with the impedance for the planar coil.1. A position sensor for detecting a position of a magnetic object, comprising:
a planar coil; a magnetizable element which at least partially covers the planar coil and can be magnetized by the magnetic object, as a result of which an impedance of the planar coil can be changed; and a processor for determining the position of the magnetic object on the basis of the impedance of the planar coil. 2. The position sensor as claimed in claim 1, the magnetizable element being arranged between the planar coil and the magnetic object. 3. The position sensor as claimed in claim 1, the planar coil having a meandering shape, a rectangular shape, a trapezoidal shape or a triangular shape. 4. The position sensor as claimed claim 1, the planar coil being arranged on a printed circuit board. 5. The position sensor as claimed in claim 4, the magnetizable element being arranged on the printed circuit board, by solder or an adhesive bond. 6. The position sensor as claimed in claim 1, the processor being designed to detect a resistance or a reactance of the planar coil. 7. The position sensor as claimed in claim 1, the magnetizable element comprising a ferromagnetic portion. 8. The position sensor as claimed in claim 1, the magnetizable element comprising ferrite, steel, transformer laminate or a highly permeable alloy. 9. The position sensor as claimed in claim 1, the magnetizable element having a rectangular shape, a trapezoidal shape or a triangular shape. 10. The position sensor as claimed in claim 1, having an insulation element which is arranged between the planar coil and the magnetizable element in order to electrically insulate the planar coil and the magnetizable element from one another. 11. The position sensor as claimed in claim 1, having a number of distributed magnetizable elements arranged in a row on the planar coil, a distance between two adjacent magnetizable elements of the number of distributed magnetizable elements increasing or decreasing along the row. 12. The position sensor as claimed in claim 1, having a number of distributed magnetizable elements arranged in a row on the planar coil, a length or a width of the magnetizable elements of the number of distributed magnetizable elements increasing or decreasing along the row. 13. The position sensor as claimed in claim 1, having a number of distributed magnetizable elements arranged in a row on the planar coil, the magnetizable elements of the number of distributed magnetizable elements being mechanically connected to one another a web. 14. The position sensor as claimed in claim 1, having a number of distributed magnetizable elements arranged in a row on the planar coil, the number of distributed magnetizable elements being arranged on a carrier film. 15. The position sensor as claimed in claim 1, the processor also being designed to determine the position of the magnetic object on the basis of an eddy current loss value of the planar coil. 16. The position sensor as claimed in claim 2, the planar coil having a meandering shape, a rectangular shape, a trapezoidal shape or a triangular shape. | 2,800 |
11,852 | 11,852 | 16,024,601 | 2,898 | The present invention is directed to a memory cell array comprising an array of magnetic memory elements arranged in rows and columns; a plurality of electrodes, each of which is formed adjacent to a respective one of the array of magnetic memory elements; a plurality of first conductive lines, each of which is connected to a respective row of the array of magnetic memory elements along a row direction; and a plurality of composite lines. Each composite line includes a volatile switching layer connected to a respective column of the plurality of electrodes along a column direction; an electrode layer formed adjacent to the volatile switching layer; and a second conductive line formed adjacent to the electrode layer. The dimension of the volatile switching layer may be substantially larger than the size of the magnetic memory element along the row direction. | 1. A magnetic memory array comprising:
an array of magnetic memory elements arranged in rows and columns; a plurality of first conductive lines formed beneath the array of magnetic memory elements, each of the plurality of first conductive lines connected to a respective row of the array of magnetic memory elements along a row direction; and a plurality of composite lines formed above the array of magnetic memory elements, each of the plurality of composite lines including a volatile switching layer connected to a respective column of the array of magnetic memory elements along a column direction and an electrode layer formed on top of the volatile switching layer. 2. The memory array of claim 1, further comprising a plurality of electrodes, each of which is formed between a respective one of the array of magnetic memory elements and a respective one of the volatile switching layers. 3. The memory array of claim 1, wherein each of the array of magnetic memory elements includes two magnetic layers with an insulating tunnel junction layer interposed therebetween. 4. The memory array of claim 1, wherein a dimension of the volatile switching layer along the row direction is substantially larger than a dimension of one of the array of magnetic memory elements along the row direction. 5. A magnetic memory array comprising:
an array of magnetic memory elements arranged in rows and columns; a plurality of first conductive lines formed beneath the array of magnetic memory elements, each of the plurality of first conductive lines connected to a respective row of the array of magnetic memory elements along a row direction; a sheet of volatile switching layer formed on top of the array of magnetic memory elements and covering the array of magnetic memory elements along the row direction and a column direction; and a plurality of electrode lines formed on top of the sheet of volatile switching layer, each of the plurality of electrode lines aligned to a respective column of the array of magnetic memory elements along the column direction. 6. The memory array of claim 5, further comprising a plurality of electrodes, each of which is formed between a respective one of the array of magnetic memory elements and the sheet of volatile switching layer. 7. The memory array of claim 5, wherein each of the array of magnetic memory elements includes two magnetic layers with an insulating tunnel junction layer interposed therebetween. 8. A method for manufacturing a memory array comprising the steps of:
depositing a first conductive film layer on top of a substrate; patterning the first conductive film layer into a plurality of first conductive lines extending along a first direction; forming an array of magnetic memory elements imbedded in an insulating matrix on top of the plurality of first conductive lines; depositing a volatile switching film layer on top of the array of magnetic memory elements; depositing a top electrode film layer and a second conductive film layer on top of the volatile switching film layer; forming an etch mask on top of the second conductive film layer that includes a plurality of parallel lines aligned to the array of magnetic memory elements along a second direction substantially perpendicular to the first direction; and etching at least the second conductive film layer and the top electrode film layer with the etch mask thereon. 9. The method of claim 8 further comprising the step of forming a bottom electrode on top of each of the array of magnetic memory elements. 10. The method of claim 8, wherein each of the array of magnetic memory elements includes two magnetic layers with an insulating tunnel junction layer interposed therebetween 11. The method of claim 8, wherein the step of etching at least the second conductive film layer and the top electrode film layer removes portions of the volatile switching film layer not covered by the etch mask. 12. The method of claim 8, wherein a width of the plurality of parallel lines is substantially larger than a dimension of one of the array of magnetic memory elements along the first direction. 13. The memory array of claim 1, wherein each of the plurality of composite lines further includes a second conductive line formed on top of the electrode layer. 14. The memory array of claim 1, wherein a current path through one of the array of magnetic memory elements at a cross point between a respective one the plurality of first conductive lines and a respective one of the plurality of composite lines is substantially perpendicular to the row and column directions. 15. The memory array of claim 5 further comprising a plurality of second conductive lines formed on top of the plurality of electrode lines. 16. The memory array of claim 5, wherein a current path through one of the array of magnetic memory elements at a cross point between a respective one of the plurality of first conductive lines and a respective one the plurality of electrode lines is substantially perpendicular to the row and column directions. | The present invention is directed to a memory cell array comprising an array of magnetic memory elements arranged in rows and columns; a plurality of electrodes, each of which is formed adjacent to a respective one of the array of magnetic memory elements; a plurality of first conductive lines, each of which is connected to a respective row of the array of magnetic memory elements along a row direction; and a plurality of composite lines. Each composite line includes a volatile switching layer connected to a respective column of the plurality of electrodes along a column direction; an electrode layer formed adjacent to the volatile switching layer; and a second conductive line formed adjacent to the electrode layer. The dimension of the volatile switching layer may be substantially larger than the size of the magnetic memory element along the row direction.1. A magnetic memory array comprising:
an array of magnetic memory elements arranged in rows and columns; a plurality of first conductive lines formed beneath the array of magnetic memory elements, each of the plurality of first conductive lines connected to a respective row of the array of magnetic memory elements along a row direction; and a plurality of composite lines formed above the array of magnetic memory elements, each of the plurality of composite lines including a volatile switching layer connected to a respective column of the array of magnetic memory elements along a column direction and an electrode layer formed on top of the volatile switching layer. 2. The memory array of claim 1, further comprising a plurality of electrodes, each of which is formed between a respective one of the array of magnetic memory elements and a respective one of the volatile switching layers. 3. The memory array of claim 1, wherein each of the array of magnetic memory elements includes two magnetic layers with an insulating tunnel junction layer interposed therebetween. 4. The memory array of claim 1, wherein a dimension of the volatile switching layer along the row direction is substantially larger than a dimension of one of the array of magnetic memory elements along the row direction. 5. A magnetic memory array comprising:
an array of magnetic memory elements arranged in rows and columns; a plurality of first conductive lines formed beneath the array of magnetic memory elements, each of the plurality of first conductive lines connected to a respective row of the array of magnetic memory elements along a row direction; a sheet of volatile switching layer formed on top of the array of magnetic memory elements and covering the array of magnetic memory elements along the row direction and a column direction; and a plurality of electrode lines formed on top of the sheet of volatile switching layer, each of the plurality of electrode lines aligned to a respective column of the array of magnetic memory elements along the column direction. 6. The memory array of claim 5, further comprising a plurality of electrodes, each of which is formed between a respective one of the array of magnetic memory elements and the sheet of volatile switching layer. 7. The memory array of claim 5, wherein each of the array of magnetic memory elements includes two magnetic layers with an insulating tunnel junction layer interposed therebetween. 8. A method for manufacturing a memory array comprising the steps of:
depositing a first conductive film layer on top of a substrate; patterning the first conductive film layer into a plurality of first conductive lines extending along a first direction; forming an array of magnetic memory elements imbedded in an insulating matrix on top of the plurality of first conductive lines; depositing a volatile switching film layer on top of the array of magnetic memory elements; depositing a top electrode film layer and a second conductive film layer on top of the volatile switching film layer; forming an etch mask on top of the second conductive film layer that includes a plurality of parallel lines aligned to the array of magnetic memory elements along a second direction substantially perpendicular to the first direction; and etching at least the second conductive film layer and the top electrode film layer with the etch mask thereon. 9. The method of claim 8 further comprising the step of forming a bottom electrode on top of each of the array of magnetic memory elements. 10. The method of claim 8, wherein each of the array of magnetic memory elements includes two magnetic layers with an insulating tunnel junction layer interposed therebetween 11. The method of claim 8, wherein the step of etching at least the second conductive film layer and the top electrode film layer removes portions of the volatile switching film layer not covered by the etch mask. 12. The method of claim 8, wherein a width of the plurality of parallel lines is substantially larger than a dimension of one of the array of magnetic memory elements along the first direction. 13. The memory array of claim 1, wherein each of the plurality of composite lines further includes a second conductive line formed on top of the electrode layer. 14. The memory array of claim 1, wherein a current path through one of the array of magnetic memory elements at a cross point between a respective one the plurality of first conductive lines and a respective one of the plurality of composite lines is substantially perpendicular to the row and column directions. 15. The memory array of claim 5 further comprising a plurality of second conductive lines formed on top of the plurality of electrode lines. 16. The memory array of claim 5, wherein a current path through one of the array of magnetic memory elements at a cross point between a respective one of the plurality of first conductive lines and a respective one the plurality of electrode lines is substantially perpendicular to the row and column directions. | 2,800 |
11,853 | 11,853 | 15,630,109 | 2,875 | A display device component includes an optical waveguide having a surface; a first material formed on a portion of the surface of the optical waveguide; and a second material formed on a portion of the first material. The first material has light scattering properties. | 1. A display device component comprising:
an optical waveguide having a surface; a first material formed on a portion of said surface of said optical waveguide; and a second material formed on a portion of said first material; said first material having light scattering properties. 2. The display device component as claimed in claim 1, wherein said second material is formed on all of said first material. 3. The display device component as claimed in claim 1, further comprising a third material formed on a portion of said first material, said portion of said first material having said second material formed thereon being distinct from said portion of said first material having said third material formed thereon. 4. The display device component as claimed in claim 1, further comprising a third material formed on a portion of said second material. 5. The display device component as claimed in claim 1, wherein said first material is a marking material and said second material is a marking material. 6. The display device component as claimed in claim 1, wherein said first material is a white marking material. 7. The display device component as claimed in claim 1, wherein said second material is a non-white colored marking material. 8. The display device component as claimed in claim 3, wherein said third material is a non-white colored marking material having a color distinct from a color of said second material. 9. The display device component as claimed in claim 3, wherein said first material is a white marking material; said second material is a first non-white colored marking material; and said third material is a second non-white colored marking material, said first non-white colored marking material having a color distinct from a color of said second non-white colored marking material. 10. The display device component as claimed in claim 1, wherein said first material and said second materials are inks. 11. The display device component as claimed in claim 1, wherein said first material and said second materials are toners. 12. A display device component comprising:
an optical waveguide having a surface; a first material formed on a portion of said surface of said optical waveguide; and a second material formed on a portion of said first material; said first material having light scattering particles embedded therein. 13. The display device component as claimed in claim 12, further comprising a third material formed on a portion of said first material, said portion of said first material having said second material formed thereon being distinct from said portion of said first material having said third material formed thereon. 14. The display device component as claimed in claim 12, further comprising a third material formed on a portion of said second material. 15. The display device component as claimed in claim 12, wherein said first material is a white marking material. 16. The display device component as claimed in claim 12, wherein said second material is a non-white colored marking material. 17. The display device component as claimed in claim 13, wherein said third material is a non-white colored marking material having a color distinct from a color of said second material. 18. The display device component as claimed in claim 13, wherein said first material is a white marking material; said second material is a first non-white colored marking material; and said third material is a second non-white colored marking material, said first non-white colored marking material having a color distinct from a color of said second non-white colored marking material. 19. A display device component comprising:
an optical waveguide having a surface and a light source interface surface; a first material formed on said surface of said optical waveguide; and a second material formed on a portion of said first material; said first material having light scattering particles embedded therein; said first material having a varied light scattering particle volumetric density; said light scattering particle volumetric density increasing proportionally along said surface of said optical waveguide as a distance away from said light source interface surface increases. 20. The display device component as claimed in claim 19, further comprising a third material formed on a portion of said first material, said portion of said first material having said second material formed thereon being distinct from said portion of said first material having said third material formed thereon. 21. A process for making a display device component to enable image specific illumination of an image printed on an optical waveguide, comprising:
(a) forming a first material on a portion of an optical waveguide having a surface, the first material having light scattering properties; and (b) forming a second material on the first material. 22. The process as claimed in claim 21, wherein the optical waveguide has a first index of refraction and the first material has a second index of refraction, the first index of refraction being substantially equal to the second index of refraction. 23. The process as claimed in claim 22, wherein the second material has a third index of refraction, the second index of refraction being substantially equal to the third index of refraction. 24. The process as claimed in claim 21, wherein the first material is a white marking material. 25. The process as claimed in claim 21, wherein the first material is formed by an inkjet printing device. 26. The process as claimed in claim 21, wherein the first material is formed by a xerographic toner printing device. 27. The process as claimed in claim 21, wherein the first material is formed by a solid ink printing device. 28. The process as claimed in claim 21, wherein said second material is a non-white colored marking material. 29. The process as claimed in claim 21, wherein the second material is formed by an inkjet printing device. 30. The process as claimed in claim 21, wherein the second material is formed by a xerographic toner printing device. 31. The process as claimed in claim 21, wherein the second material is formed by a solid ink printing device. 32. A process for making a display device component to enable image specific illumination of an image printed on an optical waveguide, comprising:
(a) forming a first material on a portion of an optical waveguide having a surface, the first material having light scattering particles embedded therein; and (b) forming a second material on the first material. 33. The process as claimed in claim 32, wherein the optical waveguide has a first index of refraction and the first material has a second index of refraction, the first index of refraction being substantially equal to the second index of refraction. 34. The process as claimed in claim 32, wherein the first material is a white marking material. 35. The process as claimed in claim 32, wherein the first material is formed by an inkjet printing device. 36. The process as claimed in claim 32, wherein said second material is a non-white colored marking material. 37. The process as claimed in claim 32, wherein the second material is formed by an inkjet printing device. 38. A process for making a display device component to enable image specific illumination of an image printed on an optical waveguide, comprising:
(a) forming a first material on an optical waveguide having a surface and a light source interface surface, the first material having light scattering particles embedded therein, the first material having a varied light scattering particle volumetric density, the light scattering particle volumetric density increasing proportionally on the surface as a distance away from the light source interface increases; and (b) forming a second material on the first material. 39. The process as claimed in claim 38, wherein the first material is a white marking material. 40. The process as claimed in claim 38, wherein the second material is a non-white colored marking material. 41. A display device component comprising:
an optical waveguide having a surface; a removable transparent layer adhered to said surface of said optical waveguide; a first material formed on a portion of said removable transparent layer; and a second material formed on a portion of said first material; said first material having light scattering particles embedded therein. 42. The display device component as claimed in claim 41, wherein said first material is a UV curable marking material and said second material is a UV curable marking material. 43. A process for making a display device component to enable image specific illumination of an image adhered to an optical waveguide, comprising:
(a) forming a first material on a portion of a removable transparent medium, the first material having light scattering particles embedded therein; (b) forming a second material on the first material; and (c) adhering the removable transparent medium to a surface of an optical waveguide. 44. The process as claimed in claim 43, wherein said first material is a UV curable marking material and said second material is a UV curable marking material. | A display device component includes an optical waveguide having a surface; a first material formed on a portion of the surface of the optical waveguide; and a second material formed on a portion of the first material. The first material has light scattering properties.1. A display device component comprising:
an optical waveguide having a surface; a first material formed on a portion of said surface of said optical waveguide; and a second material formed on a portion of said first material; said first material having light scattering properties. 2. The display device component as claimed in claim 1, wherein said second material is formed on all of said first material. 3. The display device component as claimed in claim 1, further comprising a third material formed on a portion of said first material, said portion of said first material having said second material formed thereon being distinct from said portion of said first material having said third material formed thereon. 4. The display device component as claimed in claim 1, further comprising a third material formed on a portion of said second material. 5. The display device component as claimed in claim 1, wherein said first material is a marking material and said second material is a marking material. 6. The display device component as claimed in claim 1, wherein said first material is a white marking material. 7. The display device component as claimed in claim 1, wherein said second material is a non-white colored marking material. 8. The display device component as claimed in claim 3, wherein said third material is a non-white colored marking material having a color distinct from a color of said second material. 9. The display device component as claimed in claim 3, wherein said first material is a white marking material; said second material is a first non-white colored marking material; and said third material is a second non-white colored marking material, said first non-white colored marking material having a color distinct from a color of said second non-white colored marking material. 10. The display device component as claimed in claim 1, wherein said first material and said second materials are inks. 11. The display device component as claimed in claim 1, wherein said first material and said second materials are toners. 12. A display device component comprising:
an optical waveguide having a surface; a first material formed on a portion of said surface of said optical waveguide; and a second material formed on a portion of said first material; said first material having light scattering particles embedded therein. 13. The display device component as claimed in claim 12, further comprising a third material formed on a portion of said first material, said portion of said first material having said second material formed thereon being distinct from said portion of said first material having said third material formed thereon. 14. The display device component as claimed in claim 12, further comprising a third material formed on a portion of said second material. 15. The display device component as claimed in claim 12, wherein said first material is a white marking material. 16. The display device component as claimed in claim 12, wherein said second material is a non-white colored marking material. 17. The display device component as claimed in claim 13, wherein said third material is a non-white colored marking material having a color distinct from a color of said second material. 18. The display device component as claimed in claim 13, wherein said first material is a white marking material; said second material is a first non-white colored marking material; and said third material is a second non-white colored marking material, said first non-white colored marking material having a color distinct from a color of said second non-white colored marking material. 19. A display device component comprising:
an optical waveguide having a surface and a light source interface surface; a first material formed on said surface of said optical waveguide; and a second material formed on a portion of said first material; said first material having light scattering particles embedded therein; said first material having a varied light scattering particle volumetric density; said light scattering particle volumetric density increasing proportionally along said surface of said optical waveguide as a distance away from said light source interface surface increases. 20. The display device component as claimed in claim 19, further comprising a third material formed on a portion of said first material, said portion of said first material having said second material formed thereon being distinct from said portion of said first material having said third material formed thereon. 21. A process for making a display device component to enable image specific illumination of an image printed on an optical waveguide, comprising:
(a) forming a first material on a portion of an optical waveguide having a surface, the first material having light scattering properties; and (b) forming a second material on the first material. 22. The process as claimed in claim 21, wherein the optical waveguide has a first index of refraction and the first material has a second index of refraction, the first index of refraction being substantially equal to the second index of refraction. 23. The process as claimed in claim 22, wherein the second material has a third index of refraction, the second index of refraction being substantially equal to the third index of refraction. 24. The process as claimed in claim 21, wherein the first material is a white marking material. 25. The process as claimed in claim 21, wherein the first material is formed by an inkjet printing device. 26. The process as claimed in claim 21, wherein the first material is formed by a xerographic toner printing device. 27. The process as claimed in claim 21, wherein the first material is formed by a solid ink printing device. 28. The process as claimed in claim 21, wherein said second material is a non-white colored marking material. 29. The process as claimed in claim 21, wherein the second material is formed by an inkjet printing device. 30. The process as claimed in claim 21, wherein the second material is formed by a xerographic toner printing device. 31. The process as claimed in claim 21, wherein the second material is formed by a solid ink printing device. 32. A process for making a display device component to enable image specific illumination of an image printed on an optical waveguide, comprising:
(a) forming a first material on a portion of an optical waveguide having a surface, the first material having light scattering particles embedded therein; and (b) forming a second material on the first material. 33. The process as claimed in claim 32, wherein the optical waveguide has a first index of refraction and the first material has a second index of refraction, the first index of refraction being substantially equal to the second index of refraction. 34. The process as claimed in claim 32, wherein the first material is a white marking material. 35. The process as claimed in claim 32, wherein the first material is formed by an inkjet printing device. 36. The process as claimed in claim 32, wherein said second material is a non-white colored marking material. 37. The process as claimed in claim 32, wherein the second material is formed by an inkjet printing device. 38. A process for making a display device component to enable image specific illumination of an image printed on an optical waveguide, comprising:
(a) forming a first material on an optical waveguide having a surface and a light source interface surface, the first material having light scattering particles embedded therein, the first material having a varied light scattering particle volumetric density, the light scattering particle volumetric density increasing proportionally on the surface as a distance away from the light source interface increases; and (b) forming a second material on the first material. 39. The process as claimed in claim 38, wherein the first material is a white marking material. 40. The process as claimed in claim 38, wherein the second material is a non-white colored marking material. 41. A display device component comprising:
an optical waveguide having a surface; a removable transparent layer adhered to said surface of said optical waveguide; a first material formed on a portion of said removable transparent layer; and a second material formed on a portion of said first material; said first material having light scattering particles embedded therein. 42. The display device component as claimed in claim 41, wherein said first material is a UV curable marking material and said second material is a UV curable marking material. 43. A process for making a display device component to enable image specific illumination of an image adhered to an optical waveguide, comprising:
(a) forming a first material on a portion of a removable transparent medium, the first material having light scattering particles embedded therein; (b) forming a second material on the first material; and (c) adhering the removable transparent medium to a surface of an optical waveguide. 44. The process as claimed in claim 43, wherein said first material is a UV curable marking material and said second material is a UV curable marking material. | 2,800 |
11,854 | 11,854 | 15,528,531 | 2,875 | A lighting device comprises a light source defining a central axis and comprising at least two mutually independently operable lighting elements. The lighting device further comprises a rotatable deflective member rotatably mounted about said axis, and a fixed deflective member fixedly mounted on said axis and comprising at least two mutually differently deflective portions which each are associated with a respective lighting element. The lighting device of the invention enables various operation modes, like light beam rotation can rotate, jumping of the light beam from one location to another by a sequence of switching on and off one or more of the at least two lighting elements, or in that it can be dimmed or boosted, for example dimmable in steps by a sequence of one by one switching off the lighting elements. | 1. Lighting device comprising:
a light source comprising at least two mutually independently operable lighting elements arranged around a central axis; a fixed deflective member fixedly mounted on said axis and facing the light source and comprising at least two portions which mutually are different in deflection structure and/or orientation of the deflection structure and which each are associated with a respective lighting element; a rotatable deflective member rotatably mounted about said axis and facing the fixed deflective member. wherein the fixed deflective member is positioned in between the light source and the rotatable deflective member, and wherein a main surface of the fixed deflective member comprises concentric ring shaped deflective portions. 2. Lighting device as claimed in claim 1, characterized in that at least two of the lighting elements are simultaneously operable. 3. Lighting device as claimed in claim 1, characterized in that the fixed deflective member is a single piece extending over all the lighting elements. 4. Lighting device as claimed in claim 1, characterized in that the deflective members each are refractive members and preferably each member comprise a prismatically shaped main surface. 5. Lighting device as claimed in claim 1, characterized in that light which incidents parallel to the axis on the fixed deflective member is redirected into a unique direction by a respective deflective portion. 6. Lighting device as claimed in claim 1, characterized in that for all the ring shaped deflective portions the number of lighting elements associated per ring shaped deflective portion is essentially constant. 7. Lighting device as claimed in claim 1, characterized in that, the ring shaped portions have an equal surface area. 8. Lighting device as claimed in claim 1, characterized in that each ring has a unique deflection which is the same over the whole ring. 9. Lighting device as claimed in claim 1, characterized in that each ring is built up by deflective arc segments which are mutually different in deflection. 10. Lighting device as claimed in claim 1, characterized in that in radial direction the degree of deflection for the elevation angle by the fixed deflective member either gradually increases or decreases. 11. Lighting device as claimed claim 1, characterized in that the rotatably deflective member is a round disk with a diameter that is equal or larger than the diameter of a disk shaped fixed deflective member. 12. Lighting system comprising at least one lighting device as claimed in claim 1, characterized in that comprises a control unit for controlling at least the operable lighting elements. 13. Lighting system as claimed in claim 12, characterized in that it further comprises drive means for rotating the rotatable deflective member, preferably said drive means is a motor controlled by the control unit. 14. Lighting system as claimed in claim 12, characterized in that it further comprises a sensor for providing a sensor signal to the control unit. 15. Lighting system as claimed in claim 12, characterized in that it comprises at least two lighting devices, the at least two lighting devices are controlled by the control unit for mutual cooperation. | A lighting device comprises a light source defining a central axis and comprising at least two mutually independently operable lighting elements. The lighting device further comprises a rotatable deflective member rotatably mounted about said axis, and a fixed deflective member fixedly mounted on said axis and comprising at least two mutually differently deflective portions which each are associated with a respective lighting element. The lighting device of the invention enables various operation modes, like light beam rotation can rotate, jumping of the light beam from one location to another by a sequence of switching on and off one or more of the at least two lighting elements, or in that it can be dimmed or boosted, for example dimmable in steps by a sequence of one by one switching off the lighting elements.1. Lighting device comprising:
a light source comprising at least two mutually independently operable lighting elements arranged around a central axis; a fixed deflective member fixedly mounted on said axis and facing the light source and comprising at least two portions which mutually are different in deflection structure and/or orientation of the deflection structure and which each are associated with a respective lighting element; a rotatable deflective member rotatably mounted about said axis and facing the fixed deflective member. wherein the fixed deflective member is positioned in between the light source and the rotatable deflective member, and wherein a main surface of the fixed deflective member comprises concentric ring shaped deflective portions. 2. Lighting device as claimed in claim 1, characterized in that at least two of the lighting elements are simultaneously operable. 3. Lighting device as claimed in claim 1, characterized in that the fixed deflective member is a single piece extending over all the lighting elements. 4. Lighting device as claimed in claim 1, characterized in that the deflective members each are refractive members and preferably each member comprise a prismatically shaped main surface. 5. Lighting device as claimed in claim 1, characterized in that light which incidents parallel to the axis on the fixed deflective member is redirected into a unique direction by a respective deflective portion. 6. Lighting device as claimed in claim 1, characterized in that for all the ring shaped deflective portions the number of lighting elements associated per ring shaped deflective portion is essentially constant. 7. Lighting device as claimed in claim 1, characterized in that, the ring shaped portions have an equal surface area. 8. Lighting device as claimed in claim 1, characterized in that each ring has a unique deflection which is the same over the whole ring. 9. Lighting device as claimed in claim 1, characterized in that each ring is built up by deflective arc segments which are mutually different in deflection. 10. Lighting device as claimed in claim 1, characterized in that in radial direction the degree of deflection for the elevation angle by the fixed deflective member either gradually increases or decreases. 11. Lighting device as claimed claim 1, characterized in that the rotatably deflective member is a round disk with a diameter that is equal or larger than the diameter of a disk shaped fixed deflective member. 12. Lighting system comprising at least one lighting device as claimed in claim 1, characterized in that comprises a control unit for controlling at least the operable lighting elements. 13. Lighting system as claimed in claim 12, characterized in that it further comprises drive means for rotating the rotatable deflective member, preferably said drive means is a motor controlled by the control unit. 14. Lighting system as claimed in claim 12, characterized in that it further comprises a sensor for providing a sensor signal to the control unit. 15. Lighting system as claimed in claim 12, characterized in that it comprises at least two lighting devices, the at least two lighting devices are controlled by the control unit for mutual cooperation. | 2,800 |
11,855 | 11,855 | 14,999,853 | 2,872 | A coated glass article includes a glass substrate. A coating is formed over the glass substrate. The coating includes a first inorganic metal oxide layer deposited over a major surface of the glass substrate. The first inorganic metal oxide layer has a refractive index of 1.6 or more. A second inorganic metal oxide layer is deposited over the first inorganic metal oxide layer. The second inorganic metal oxide layer has a refractive index which is less than the refractive index of the first inorganic metal oxide layer. A third inorganic metal oxide layer is deposited over the second inorganic metal oxide layer. The third inorganic metal oxide layer has a refractive index of 2.2 or more and the refractive index of the third inorganic metal oxide layer is greater than the refractive index of the second inorganic metal oxide layer. A fourth inorganic metal oxide layer is deposited over the third inorganic metal oxide layer. The fourth inorganic metal oxide layer has a refractive index which is less than the refractive index of the third inorganic metal oxide layer. The coated glass article exhibits a total visible light reflectance of less than 6.5%. | 1. A coated glass article comprising:
a glass substrate; and a coating formed over the glass substrate, wherein the coating comprises: i. a first inorganic metal oxide layer deposited over a major surface of the glass substrate, wherein the first inorganic metal oxide layer has a refractive index of 1.6 or more, ii. a second inorganic metal oxide layer deposited over the first inorganic metal oxide layer, wherein the second inorganic metal oxide layer has a refractive index which is less than the refractive index of the first inorganic metal oxide layer, iii. a third inorganic metal oxide layer deposited over the second inorganic metal oxide layer, wherein the third inorganic metal oxide layer has a refractive index of 2.2 or more and wherein the refractive index of the third inorganic metal oxide layer is greater than the refractive index of the second inorganic metal oxide layer, and iv. a fourth inorganic metal oxide layer deposited over the third inorganic metal oxide layer, wherein the fourth inorganic metal oxide layer has a refractive index which is less than the refractive index of the third inorganic metal oxide layer; wherein the coated glass article exhibits a total visible light reflectance of less than 6.5%. 2. The coated glass article of claim 1, wherein the first inorganic metal oxide layer comprises tin oxide or titanium dioxide. 3. The coated glass article of claim 1, wherein the first inorganic metal oxide layer is deposited on the major surface of the glass substrate and the second inorganic metal oxide layer is deposited on the first inorganic metal oxide layer and has a refractive index which is less than 1.6. 4. The coated glass article of claim 1, wherein the third inorganic metal oxide is deposited on the second inorganic metal oxide layer at a thickness of 30 nm or less. 5. The coated glass article of claim 1, wherein the fourth inorganic metal oxide layer is deposited on the third inorganic metal oxide layer and has a refractive index which of 1.5 or less. 6. The coated glass article of claim 1, wherein the fourth inorganic metal oxide layer comprises silicon dioxide and is deposited at a thickness of 80 nm or more. 7. The coated glass article of claim 1, wherein the total visible light reflectance exhibited by the coated glass article is 6.0% or less. 8. The coated glass article of claim 1, wherein the inorganic metal oxide layers are selected so that sheet resistance exhibited by the coated glass article is greater than 1.0×105 ohm/sq. 9. The coated glass article of claim 2, wherein the first inorganic metal oxide layer comprises tin oxide and is deposited at a thickness of 30-50 nm. 10. The coated glass article of claim 2, wherein the first inorganic metal oxide layer comprises titanium dioxide and is deposited at a thickness of 5-25 nm. 11. The coated glass article of claim 6, wherein the fourth inorganic metal oxide layer forms an outer surface of the coated glass article. 12. A coated glass article comprising:
a glass substrate; and a coating formed on the glass substrate, wherein the coating comprises: i. a first inorganic metal oxide layer deposited on a major surface of the glass substrate, wherein the first inorganic metal oxide layer has a refractive index of 1.6 or more and comprises tin oxide or titanium dioxide, ii. a second inorganic metal oxide layer deposited over the first inorganic metal oxide layer, wherein the second inorganic metal oxide layer has a refractive index which is less than the refractive index of the first inorganic metal oxide layer and comprises silicon dioxide, iii. a third inorganic metal oxide layer deposited over the second inorganic metal oxide layer, wherein the third inorganic metal oxide layer comprises titanium dioxide and has a refractive index of 2.2 or more and wherein the refractive index of the third inorganic metal oxide layer is greater than the refractive index of the second inorganic metal oxide layer, and iv. a fourth inorganic metal oxide layer deposited over the third inorganic metal oxide layer, wherein the fourth inorganic metal oxide layer has a refractive index which is less than the refractive index of the third inorganic metal oxide layer and comprises silicon dioxide; wherein the coated glass article exhibits a total visible light reflectance of less than 6.5% and a sheet resistance of greater than 1.0×105 ohm/sq. 13. The coated glass article of claim 12, wherein the first inorganic metal oxide layer comprises tin oxide and is deposited at a thickness of 30-50 nm. 14. The coated glass article of claim 12, wherein the first inorganic metal oxide layer comprises titanium dioxide and is deposited at a thickness of 5-25 nm. 15. The coated glass article of claim 12, wherein the second inorganic metal oxide layer is deposited at a thickness of 20-40 nm and the fourth inorganic metal oxide layer is deposited at a thickness of 80-150 nm. 16. The coated glass article of claim 12, wherein the inorganic metal oxide layers are selected so that sheet resistance exhibited by the coated glass article is 1.0×107 ohm/sq. or more. 17. The coated glass article of claim 12, wherein the total visible light reflectance exhibited by the coated glass article is 6.0% or less. 18. The coated glass article of claim 13, wherein the third inorganic metal oxide layer is deposited at a thickness of 5-25 nm. 19. The coated glass article of claim 14, wherein the third inorganic metal oxide layer is deposited at a thickness of 10-30 nm. 20. A laminated glass unit, comprising:
two coated glass articles as claimed in claim 1, wherein the coated glass articles are in a parallel relationship with each other and each coated glass article comprises a major surface adhesively bonded to a polymeric interlayer provided between the coated glass articles, wherein the laminated glass unit exhibits a total visible light reflectance of 2.5 or less and total visible light transmittance of 95% or more. 21. A laminated glass unit, comprising:
two coated glass articles as claimed in claim 12, wherein the coated glass articles are in a parallel relationship with each other and each coated glass article comprises a major surface adhesively bonded to a polymeric interlayer provided between the coated glass articles, wherein the laminated glass unit exhibits a total visible light reflectance of 2.5 or less and total visible light transmittance of 95% or more. | A coated glass article includes a glass substrate. A coating is formed over the glass substrate. The coating includes a first inorganic metal oxide layer deposited over a major surface of the glass substrate. The first inorganic metal oxide layer has a refractive index of 1.6 or more. A second inorganic metal oxide layer is deposited over the first inorganic metal oxide layer. The second inorganic metal oxide layer has a refractive index which is less than the refractive index of the first inorganic metal oxide layer. A third inorganic metal oxide layer is deposited over the second inorganic metal oxide layer. The third inorganic metal oxide layer has a refractive index of 2.2 or more and the refractive index of the third inorganic metal oxide layer is greater than the refractive index of the second inorganic metal oxide layer. A fourth inorganic metal oxide layer is deposited over the third inorganic metal oxide layer. The fourth inorganic metal oxide layer has a refractive index which is less than the refractive index of the third inorganic metal oxide layer. The coated glass article exhibits a total visible light reflectance of less than 6.5%.1. A coated glass article comprising:
a glass substrate; and a coating formed over the glass substrate, wherein the coating comprises: i. a first inorganic metal oxide layer deposited over a major surface of the glass substrate, wherein the first inorganic metal oxide layer has a refractive index of 1.6 or more, ii. a second inorganic metal oxide layer deposited over the first inorganic metal oxide layer, wherein the second inorganic metal oxide layer has a refractive index which is less than the refractive index of the first inorganic metal oxide layer, iii. a third inorganic metal oxide layer deposited over the second inorganic metal oxide layer, wherein the third inorganic metal oxide layer has a refractive index of 2.2 or more and wherein the refractive index of the third inorganic metal oxide layer is greater than the refractive index of the second inorganic metal oxide layer, and iv. a fourth inorganic metal oxide layer deposited over the third inorganic metal oxide layer, wherein the fourth inorganic metal oxide layer has a refractive index which is less than the refractive index of the third inorganic metal oxide layer; wherein the coated glass article exhibits a total visible light reflectance of less than 6.5%. 2. The coated glass article of claim 1, wherein the first inorganic metal oxide layer comprises tin oxide or titanium dioxide. 3. The coated glass article of claim 1, wherein the first inorganic metal oxide layer is deposited on the major surface of the glass substrate and the second inorganic metal oxide layer is deposited on the first inorganic metal oxide layer and has a refractive index which is less than 1.6. 4. The coated glass article of claim 1, wherein the third inorganic metal oxide is deposited on the second inorganic metal oxide layer at a thickness of 30 nm or less. 5. The coated glass article of claim 1, wherein the fourth inorganic metal oxide layer is deposited on the third inorganic metal oxide layer and has a refractive index which of 1.5 or less. 6. The coated glass article of claim 1, wherein the fourth inorganic metal oxide layer comprises silicon dioxide and is deposited at a thickness of 80 nm or more. 7. The coated glass article of claim 1, wherein the total visible light reflectance exhibited by the coated glass article is 6.0% or less. 8. The coated glass article of claim 1, wherein the inorganic metal oxide layers are selected so that sheet resistance exhibited by the coated glass article is greater than 1.0×105 ohm/sq. 9. The coated glass article of claim 2, wherein the first inorganic metal oxide layer comprises tin oxide and is deposited at a thickness of 30-50 nm. 10. The coated glass article of claim 2, wherein the first inorganic metal oxide layer comprises titanium dioxide and is deposited at a thickness of 5-25 nm. 11. The coated glass article of claim 6, wherein the fourth inorganic metal oxide layer forms an outer surface of the coated glass article. 12. A coated glass article comprising:
a glass substrate; and a coating formed on the glass substrate, wherein the coating comprises: i. a first inorganic metal oxide layer deposited on a major surface of the glass substrate, wherein the first inorganic metal oxide layer has a refractive index of 1.6 or more and comprises tin oxide or titanium dioxide, ii. a second inorganic metal oxide layer deposited over the first inorganic metal oxide layer, wherein the second inorganic metal oxide layer has a refractive index which is less than the refractive index of the first inorganic metal oxide layer and comprises silicon dioxide, iii. a third inorganic metal oxide layer deposited over the second inorganic metal oxide layer, wherein the third inorganic metal oxide layer comprises titanium dioxide and has a refractive index of 2.2 or more and wherein the refractive index of the third inorganic metal oxide layer is greater than the refractive index of the second inorganic metal oxide layer, and iv. a fourth inorganic metal oxide layer deposited over the third inorganic metal oxide layer, wherein the fourth inorganic metal oxide layer has a refractive index which is less than the refractive index of the third inorganic metal oxide layer and comprises silicon dioxide; wherein the coated glass article exhibits a total visible light reflectance of less than 6.5% and a sheet resistance of greater than 1.0×105 ohm/sq. 13. The coated glass article of claim 12, wherein the first inorganic metal oxide layer comprises tin oxide and is deposited at a thickness of 30-50 nm. 14. The coated glass article of claim 12, wherein the first inorganic metal oxide layer comprises titanium dioxide and is deposited at a thickness of 5-25 nm. 15. The coated glass article of claim 12, wherein the second inorganic metal oxide layer is deposited at a thickness of 20-40 nm and the fourth inorganic metal oxide layer is deposited at a thickness of 80-150 nm. 16. The coated glass article of claim 12, wherein the inorganic metal oxide layers are selected so that sheet resistance exhibited by the coated glass article is 1.0×107 ohm/sq. or more. 17. The coated glass article of claim 12, wherein the total visible light reflectance exhibited by the coated glass article is 6.0% or less. 18. The coated glass article of claim 13, wherein the third inorganic metal oxide layer is deposited at a thickness of 5-25 nm. 19. The coated glass article of claim 14, wherein the third inorganic metal oxide layer is deposited at a thickness of 10-30 nm. 20. A laminated glass unit, comprising:
two coated glass articles as claimed in claim 1, wherein the coated glass articles are in a parallel relationship with each other and each coated glass article comprises a major surface adhesively bonded to a polymeric interlayer provided between the coated glass articles, wherein the laminated glass unit exhibits a total visible light reflectance of 2.5 or less and total visible light transmittance of 95% or more. 21. A laminated glass unit, comprising:
two coated glass articles as claimed in claim 12, wherein the coated glass articles are in a parallel relationship with each other and each coated glass article comprises a major surface adhesively bonded to a polymeric interlayer provided between the coated glass articles, wherein the laminated glass unit exhibits a total visible light reflectance of 2.5 or less and total visible light transmittance of 95% or more. | 2,800 |
11,856 | 11,856 | 15,289,683 | 2,811 | A system and method for generating air quality scores for air quality within certain locations are presented. The method includes identifying at least one air pollution source within the predetermined perimeter around the at least one location; extracting an air quality score range based on the at least one location from at least one data source; identifying at least one environmental variable based on the at least one location and the at least one time parameter; simulating at least one air pollution measurement based on the at least one environmental variable and the at least one air pollution source; and generating at least one air quality score respective of the air quality score range, wherein the at least one air quality score is based on the at least one air pollution measurement. | 1. A computerized method for generating air quality scores based on at least one location, a predetermined perimeter, and at least one time parameter, comprising:
identifying at least one air pollution source within the predetermined perimeter around the at least one location; extracting an air quality score range based on the at least one location from at least one data source; identifying at least one environmental variable based on the at least one location and the at least one time parameter; simulating at least one air pollution measurement based on the at least one environmental variable and the at least one air pollution source; and generating at least one air quality score respective of the air quality score range, wherein the at least one air quality score is based on the at least one air pollution measurement. 2. The computerized method of claim 1, wherein the at least one environmental variable is any of: meteorological parameters, topographic parameters, and traffic parameters. 3. The computerized method of claim 1, further comprising:
generating at least one recommendation based on the at least one air quality score. 4. The computerized method of claim 1, wherein the at least one location or the at least one time parameter is received from a user device. 5. The computerized method of claim 3, wherein the at least one recommendation is generated based on a type of the at least one air pollution source. 6. The computerized method of claim 3, further comprising:
generating at least one personalized recommendation based on at least one personal variable related to a user. 7. The computerized method of claim 1, wherein the at least one air pollution source is any of: heavy transportation, generating stations, factories, office buildings, and incineration of garbage. 8. The computerized method of claim 1, further comprising:
generating an air pollution score respective of the at least one air pollution source based on the at least one air quality score. 9. The computerized method of claim 2, wherein the meteorological parameters are any of: wind speed, wind direction, air temperature, air pressure, air humidity, precipitation, haze, contents of the air, solar radiation, and terrestrial radiation. 10. The computerized method of claim 1, further comprising:
generating an air quality map based on the at least one air quality score; and displaying the air quality map. 11. The computerized method of claim 1, further comprising:
storing the at least one air quality score in a database. 12. The computerized method of claim 1, further comprising:
generating future air quality scores based on the at least one air quality score. 13. A system for generating air quality score based on at least one location, a predetermined perimeter, and at least one time parameter, comprising:
a processor; and a memory, the memory containing instructions that, when executed by the processor, configure the system to: identify at least one air pollution source within the predetermined perimeter around the at least one location; extract an air quality score range based on the at least one location from at least one data source; identify at least one environmental variable based on the at least one location and the at least one time parameter; simulate at least one air pollution measurement based on the at least one environmental variable and the at least one air pollution source; and generate at least one air quality score respective of the air quality score range, wherein the at least one air quality score is based on the at least one air pollution measurement. 14. The system of claim 13, wherein the at least one environmental variable is at least one of: meteorological parameters, topographic parameters, and traffic parameters. 15. The system of claim 13, wherein the system is further configured to:
generate at least one recommendation based on the at least one air quality score. 16. The system of claim 13, wherein the at least one location or the at least one time parameter is received from a user device. 17. The system of claim 15, wherein the at least one recommendation is generated based on a type of the at least one air pollution source. 18. The system of claim 13, wherein the system is further configured to:
generate at least one personalized recommendation based on at least one personal variable related to a user. 19. The system of claim 15, wherein the at least one air pollution source is at least one of: heavy transportation, generating stations, factories, office buildings, and incineration of garbage. 20. The system of claim 13, wherein the system is further configured to:
generate an air pollution score respective of the at least one air pollution source based on the at least one air quality score. 21. The system of claim 14, wherein the meteorological parameters include any of: wind speed and direction, air temperature, air pressure, air humidity, precipitation, haze, contents of the air, solar radiation, and terrestrial radiation. 22. The system of claim 13, wherein the system is further configured to:
generate an air quality map based on the at least one air quality score; and display the air quality map. 23. The system of claim 13, wherein the system is further configured to:
store the at least one air quality score in a database. 24. The system of claim 13, wherein the system is further configured to:
generate future air quality scores based on the at least one air quality score. | A system and method for generating air quality scores for air quality within certain locations are presented. The method includes identifying at least one air pollution source within the predetermined perimeter around the at least one location; extracting an air quality score range based on the at least one location from at least one data source; identifying at least one environmental variable based on the at least one location and the at least one time parameter; simulating at least one air pollution measurement based on the at least one environmental variable and the at least one air pollution source; and generating at least one air quality score respective of the air quality score range, wherein the at least one air quality score is based on the at least one air pollution measurement.1. A computerized method for generating air quality scores based on at least one location, a predetermined perimeter, and at least one time parameter, comprising:
identifying at least one air pollution source within the predetermined perimeter around the at least one location; extracting an air quality score range based on the at least one location from at least one data source; identifying at least one environmental variable based on the at least one location and the at least one time parameter; simulating at least one air pollution measurement based on the at least one environmental variable and the at least one air pollution source; and generating at least one air quality score respective of the air quality score range, wherein the at least one air quality score is based on the at least one air pollution measurement. 2. The computerized method of claim 1, wherein the at least one environmental variable is any of: meteorological parameters, topographic parameters, and traffic parameters. 3. The computerized method of claim 1, further comprising:
generating at least one recommendation based on the at least one air quality score. 4. The computerized method of claim 1, wherein the at least one location or the at least one time parameter is received from a user device. 5. The computerized method of claim 3, wherein the at least one recommendation is generated based on a type of the at least one air pollution source. 6. The computerized method of claim 3, further comprising:
generating at least one personalized recommendation based on at least one personal variable related to a user. 7. The computerized method of claim 1, wherein the at least one air pollution source is any of: heavy transportation, generating stations, factories, office buildings, and incineration of garbage. 8. The computerized method of claim 1, further comprising:
generating an air pollution score respective of the at least one air pollution source based on the at least one air quality score. 9. The computerized method of claim 2, wherein the meteorological parameters are any of: wind speed, wind direction, air temperature, air pressure, air humidity, precipitation, haze, contents of the air, solar radiation, and terrestrial radiation. 10. The computerized method of claim 1, further comprising:
generating an air quality map based on the at least one air quality score; and displaying the air quality map. 11. The computerized method of claim 1, further comprising:
storing the at least one air quality score in a database. 12. The computerized method of claim 1, further comprising:
generating future air quality scores based on the at least one air quality score. 13. A system for generating air quality score based on at least one location, a predetermined perimeter, and at least one time parameter, comprising:
a processor; and a memory, the memory containing instructions that, when executed by the processor, configure the system to: identify at least one air pollution source within the predetermined perimeter around the at least one location; extract an air quality score range based on the at least one location from at least one data source; identify at least one environmental variable based on the at least one location and the at least one time parameter; simulate at least one air pollution measurement based on the at least one environmental variable and the at least one air pollution source; and generate at least one air quality score respective of the air quality score range, wherein the at least one air quality score is based on the at least one air pollution measurement. 14. The system of claim 13, wherein the at least one environmental variable is at least one of: meteorological parameters, topographic parameters, and traffic parameters. 15. The system of claim 13, wherein the system is further configured to:
generate at least one recommendation based on the at least one air quality score. 16. The system of claim 13, wherein the at least one location or the at least one time parameter is received from a user device. 17. The system of claim 15, wherein the at least one recommendation is generated based on a type of the at least one air pollution source. 18. The system of claim 13, wherein the system is further configured to:
generate at least one personalized recommendation based on at least one personal variable related to a user. 19. The system of claim 15, wherein the at least one air pollution source is at least one of: heavy transportation, generating stations, factories, office buildings, and incineration of garbage. 20. The system of claim 13, wherein the system is further configured to:
generate an air pollution score respective of the at least one air pollution source based on the at least one air quality score. 21. The system of claim 14, wherein the meteorological parameters include any of: wind speed and direction, air temperature, air pressure, air humidity, precipitation, haze, contents of the air, solar radiation, and terrestrial radiation. 22. The system of claim 13, wherein the system is further configured to:
generate an air quality map based on the at least one air quality score; and display the air quality map. 23. The system of claim 13, wherein the system is further configured to:
store the at least one air quality score in a database. 24. The system of claim 13, wherein the system is further configured to:
generate future air quality scores based on the at least one air quality score. | 2,800 |
11,857 | 11,857 | 15,481,713 | 2,852 | Memory gauge and method for processing recorded raw data acquired with a memory gauge in a well. The method includes selecting a first calibration table (C 1 ), of the memory gauge, that has a highest calibration value for the measured parameter; performing a first analysis of the recorded raw data using the first calibration table (C 1 ) to determine a highest measured value of the measured parameter; comparing the highest measured value of the measured parameter with highest calibration values of the plural calibration tables of the memory gauge; and when a highest calibration value of a second calibration table is closer to the highest measured value of the measured parameter than the highest calibration value of the first calibration table, selecting the second calibration table (C 2 ); and performing a second analysis of the recorded raw data using the second calibration table (C 2 ) to generate measured values of the measured parameter. | 1. A method for processing recorded raw data acquired with a memory gauge in a well, wherein the memory gauge has plural calibration tables for a parameter to be measured with the gauge from the recorded raw data, the method comprising:
selecting a first calibration table (C1), of the memory gauge, that has a highest calibration value for the measured parameter; performing a first analysis of the recorded raw data using the first calibration table (C1) to determine a highest measured value of the measured parameter; comparing the highest measured value of the measured parameter with highest calibration values of the plural calibration tables of the memory gauge; and when a highest calibration value of a second calibration table is closer to the highest measured value of the measured parameter than the highest calibration value of the first calibration table, selecting the second calibration table (C2); and performing a second analysis of the recorded raw data using the second calibration table (C2) to generate measured values of the measured parameter; or when the highest calibration value of the first calibration table is closer to the highest measured value of the measured parameter than a highest calibration value of the second calibration table, outputting a result of the first analysis. 2. The method of claim 1, further comprising:
storing the recorded raw data at a memory in the memory gauge; transferring the recorded raw data from the memory gauge to an external device; and transferring the plural calibration tables (C1, C2) from the memory gauge to the external device. 3. The method of claim 1, further comprising:
storing the plural calibration tables in a memory associated with the memory gauge. 4. The method of claim 1, wherein the measured parameter is temperature. 5. The method of claim 1, wherein the measured parameter is pressure. 6. The method of claim 1, further comprising:
recording the recorded raw data with a sensor located on the memory gauge. 7. The method of claim 1, wherein the step of selecting the first calibration table (C1), the step of performing the first analysis of the recorded raw data, the step of comparing, the step of selecting the second calibration table (C2), and the step of performing the second analysis of the recorded raw data take place in an external computer, after the measured raw data has been transferred from the memory gauge to the external computer. 8. The method of claim 1, wherein the step of selecting the first calibration table (C1), the step of performing the first analysis of the recorded raw data, the step of comparing, the step of selecting the second calibration table (C2), and the step of performing the second analysis of the recorded raw data take place in the memory gauge. 9. The method of claim 1, wherein the first calibration table is different from the second calibration table. 10. A device for processing recorded raw data acquired with a memory gauge in a well, wherein the memory gauge has plural calibration tables associated with a parameter to be measured with the gauge from the recorded raw data, the device comprising:
an interface for receiving the recorded raw data; and a processor configured to, select a first calibration table (C1) of the memory gauge that has a highest calibration value for the measured parameter; perform a first analysis of the recorded raw data using the first calibration table (C1) to determine a highest measured value of the measured parameter; compare the highest measured value of the measured parameter with highest calibration values of the plural calibration tables of the memory gauge; and when a highest calibration value of a second calibration table is closer to the highest measured value of the measured parameter than the highest calibration value of the first calibration table, selecting the second calibration table (C2); and perform a second analysis of the recorded raw data using the second calibration table (C2) to generate measured values of the measured parameter; or when the highest calibration value of the first calibration table is closer to the highest measured value of the measured parameter than a highest calibration value of the second calibration table, output a result of the first analysis. 11. The device of claim 10, wherein the processor is further configured to:
store the recorded raw data at a memory in the memory gauge; transfer the recorded raw data from the memory gauge to an external device; and transfer the plural calibration tables (C1, C2) from the memory gauge to the external device. 12. The device of claim 10, further comprising:
a memory for storing the plural calibration tables. 13. The device of claim 10, wherein the measured parameter is a temperature or a pressure. 14. The device of claim 10, further comprising:
a sensor for recording the recorded raw data. 15. A method for calibrating a memory gauge to be used in a well, the method comprising:
placing the memory gauge in a chamber; varying, in a controlled way, a first parameter inside the chamber, up to a first maximum value; measuring with a sensor located on the memory gauge a second parameter; generating a first calibration table for the sensor for the first and second parameters while varying the first parameter up to the first maximum value; varying again the first parameter inside the chamber, up to a second maximum value, which is different from the first maximum value; measuring with the sensor located on the memory gauge the second parameter; generating a second calibration table for the sensor for the first and second parameters while varying the first parameter up to the second maximum value; and storing the first and second calibration tables in a memory associated with the memory gauge. 16. The method of claim 15, wherein the first parameter is temperature and the second parameter is related to a pressure and the second parameter is measured over a given time interval over a range of temperatures. 17. The method of claim 15, wherein the parameter is related to a flow of a fluid through the well. 18. The method of claim 15, wherein the memory is located at a surface of a well in which the memory gauge is deployed and communicates with the memory gauge. 19. The method of claim 15, further comprising:
collecting recorded raw data; selecting a calibration table (C1) that has a highest calibration value for a measured parameter inside the well; performing a first analysis of the recorded raw data using the first calibration table (C1) to determine a highest measured value of the measured parameter; selecting a second calibration table (C2) that has a highest calibration value closest to the highest measured value of the measured parameter; and performing a second analysis of the recorded raw data using the second calibration table (C2) to determine measured values of the measured parameter. 20. The method of claim 19, further comprising:
storing the recorded raw data at a memory in the memory gauge; transferring the recorded raw data from the memory gauge to an external device; and transferring plural calibration tables (C1, C2) from the memory gauge to the external device. | Memory gauge and method for processing recorded raw data acquired with a memory gauge in a well. The method includes selecting a first calibration table (C 1 ), of the memory gauge, that has a highest calibration value for the measured parameter; performing a first analysis of the recorded raw data using the first calibration table (C 1 ) to determine a highest measured value of the measured parameter; comparing the highest measured value of the measured parameter with highest calibration values of the plural calibration tables of the memory gauge; and when a highest calibration value of a second calibration table is closer to the highest measured value of the measured parameter than the highest calibration value of the first calibration table, selecting the second calibration table (C 2 ); and performing a second analysis of the recorded raw data using the second calibration table (C 2 ) to generate measured values of the measured parameter.1. A method for processing recorded raw data acquired with a memory gauge in a well, wherein the memory gauge has plural calibration tables for a parameter to be measured with the gauge from the recorded raw data, the method comprising:
selecting a first calibration table (C1), of the memory gauge, that has a highest calibration value for the measured parameter; performing a first analysis of the recorded raw data using the first calibration table (C1) to determine a highest measured value of the measured parameter; comparing the highest measured value of the measured parameter with highest calibration values of the plural calibration tables of the memory gauge; and when a highest calibration value of a second calibration table is closer to the highest measured value of the measured parameter than the highest calibration value of the first calibration table, selecting the second calibration table (C2); and performing a second analysis of the recorded raw data using the second calibration table (C2) to generate measured values of the measured parameter; or when the highest calibration value of the first calibration table is closer to the highest measured value of the measured parameter than a highest calibration value of the second calibration table, outputting a result of the first analysis. 2. The method of claim 1, further comprising:
storing the recorded raw data at a memory in the memory gauge; transferring the recorded raw data from the memory gauge to an external device; and transferring the plural calibration tables (C1, C2) from the memory gauge to the external device. 3. The method of claim 1, further comprising:
storing the plural calibration tables in a memory associated with the memory gauge. 4. The method of claim 1, wherein the measured parameter is temperature. 5. The method of claim 1, wherein the measured parameter is pressure. 6. The method of claim 1, further comprising:
recording the recorded raw data with a sensor located on the memory gauge. 7. The method of claim 1, wherein the step of selecting the first calibration table (C1), the step of performing the first analysis of the recorded raw data, the step of comparing, the step of selecting the second calibration table (C2), and the step of performing the second analysis of the recorded raw data take place in an external computer, after the measured raw data has been transferred from the memory gauge to the external computer. 8. The method of claim 1, wherein the step of selecting the first calibration table (C1), the step of performing the first analysis of the recorded raw data, the step of comparing, the step of selecting the second calibration table (C2), and the step of performing the second analysis of the recorded raw data take place in the memory gauge. 9. The method of claim 1, wherein the first calibration table is different from the second calibration table. 10. A device for processing recorded raw data acquired with a memory gauge in a well, wherein the memory gauge has plural calibration tables associated with a parameter to be measured with the gauge from the recorded raw data, the device comprising:
an interface for receiving the recorded raw data; and a processor configured to, select a first calibration table (C1) of the memory gauge that has a highest calibration value for the measured parameter; perform a first analysis of the recorded raw data using the first calibration table (C1) to determine a highest measured value of the measured parameter; compare the highest measured value of the measured parameter with highest calibration values of the plural calibration tables of the memory gauge; and when a highest calibration value of a second calibration table is closer to the highest measured value of the measured parameter than the highest calibration value of the first calibration table, selecting the second calibration table (C2); and perform a second analysis of the recorded raw data using the second calibration table (C2) to generate measured values of the measured parameter; or when the highest calibration value of the first calibration table is closer to the highest measured value of the measured parameter than a highest calibration value of the second calibration table, output a result of the first analysis. 11. The device of claim 10, wherein the processor is further configured to:
store the recorded raw data at a memory in the memory gauge; transfer the recorded raw data from the memory gauge to an external device; and transfer the plural calibration tables (C1, C2) from the memory gauge to the external device. 12. The device of claim 10, further comprising:
a memory for storing the plural calibration tables. 13. The device of claim 10, wherein the measured parameter is a temperature or a pressure. 14. The device of claim 10, further comprising:
a sensor for recording the recorded raw data. 15. A method for calibrating a memory gauge to be used in a well, the method comprising:
placing the memory gauge in a chamber; varying, in a controlled way, a first parameter inside the chamber, up to a first maximum value; measuring with a sensor located on the memory gauge a second parameter; generating a first calibration table for the sensor for the first and second parameters while varying the first parameter up to the first maximum value; varying again the first parameter inside the chamber, up to a second maximum value, which is different from the first maximum value; measuring with the sensor located on the memory gauge the second parameter; generating a second calibration table for the sensor for the first and second parameters while varying the first parameter up to the second maximum value; and storing the first and second calibration tables in a memory associated with the memory gauge. 16. The method of claim 15, wherein the first parameter is temperature and the second parameter is related to a pressure and the second parameter is measured over a given time interval over a range of temperatures. 17. The method of claim 15, wherein the parameter is related to a flow of a fluid through the well. 18. The method of claim 15, wherein the memory is located at a surface of a well in which the memory gauge is deployed and communicates with the memory gauge. 19. The method of claim 15, further comprising:
collecting recorded raw data; selecting a calibration table (C1) that has a highest calibration value for a measured parameter inside the well; performing a first analysis of the recorded raw data using the first calibration table (C1) to determine a highest measured value of the measured parameter; selecting a second calibration table (C2) that has a highest calibration value closest to the highest measured value of the measured parameter; and performing a second analysis of the recorded raw data using the second calibration table (C2) to determine measured values of the measured parameter. 20. The method of claim 19, further comprising:
storing the recorded raw data at a memory in the memory gauge; transferring the recorded raw data from the memory gauge to an external device; and transferring plural calibration tables (C1, C2) from the memory gauge to the external device. | 2,800 |
11,858 | 11,858 | 15,488,345 | 2,851 | Systems and techniques for three-dimension (3D) resist profile aware resolution enhancement techniques are described. 3D resist profile aware resolution enhancement models can be calibrated based on empirical data. Next, the 3D resist profile aware resolution enhancement models can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement. | 1. A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method to determine a set of mask patterns for printing a set of target patterns by using a semiconductor manufacturing process, wherein the semiconductor manufacturing process includes a photolithography process and an etching process, the method comprising:
determining a set of retargeted patterns based on the set of target patterns; and determining the set of mask patterns based on the set of retargeted patterns by optimizing an objective function that comprises a measure of a deviation of a predicted three-dimensional (3D) resist profile with respect to a desired 3D resist profile. 2. The non-transitory computer-readable storage medium of claim 1, wherein the method further comprising creating a photolithography mask containing the set of mask patterns. 3. The non-transitory computer-readable storage medium of claim 1, wherein the measure of the deviation of the predicted 3D resist profile with respect to the desired 3D resist profile includes an inverse of a predicted resist sidewall slope. 4. The non-transitory computer-readable storage medium of claim 1, wherein the measure of the deviation of the predicted 3D resist profile with respect to the desired 3D resist profile includes differences between predicted critical dimensions (CDs) and target CDs at multiple resist heights. 5. The non-transitory computer-readable storage medium of claim 1, wherein determining the set of retargeted patterns based on the set of target patterns comprises:
computing etch biases at a set of evaluation points in the set of target patterns by using an etch-bias model; and determining the set of retargeted patterns by adjusting the set of target patterns based on the computed etch biases. 6. The non-transitory computer-readable storage medium of claim 5, wherein the etch bias model comprises one or more of the following terms:
a constant bias, a short range density function, a long range density function, a visible area function, a blocked area function, and a function of a sidewall slope of a post-development resist layer. 7. A method to determine a set of mask patterns for printing a set of target patterns by using a semiconductor manufacturing process, wherein the semiconductor manufacturing process includes a photolithography process and an etching process, the method comprising:
a computer determining a set of retargeted patterns based on the set of target patterns; and the computer determining the set of mask patterns based on the set of retargeted patterns by optimizing an objective function that comprises a measure of a deviation of a predicted three-dimensional (3D) resist profile with respect to a desired 3D resist profile. 8. The method of claim 7, further comprising creating a photolithography mask containing the set of mask patterns. 9. The method of claim 7, wherein the measure of the deviation of the predicted 3D resist profile with respect to the desired 3D resist profile includes an inverse of a predicted resist sidewall slope. 10. The method of claim 7, wherein the measure of the deviation of the predicted 3D resist profile with respect to the desired 3D resist profile includes differences between predicted critical dimensions (CDs) and target CDs at multiple resist heights. 11. The method of claim 7, wherein determining the set of retargeted patterns based on the set of target patterns comprises:
computing etch biases at a set of evaluation points in the set of target patterns by using an etch-bias model; and determining the set of retargeted patterns by adjusting the set of target patterns based on the computed etch biases. 12. The method of claim 11, wherein the etch bias model comprises one or more of the following terms:
a constant bias, a short range density function, a long range density function, a visible area function, a blocked area function, and a function of a sidewall slope of a post-development resist layer. 13. An apparatus, comprising:
a processor; and a non-transitory computer-readable storage medium storing instructions that, when executed by the processor, cause the apparatus to perform a method to determine a set of mask patterns for printing a set of target patterns by using a semiconductor manufacturing process, wherein the semiconductor manufacturing process includes a photolithography process and an etching process, the method comprising:
determining a set of retargeted patterns based on the set of target patterns; and
determining the set of mask patterns based on the set of retargeted patterns by optimizing an objective function that comprises a measure of a deviation of a predicted three-dimensional (3D) resist profile with respect to a desired 3D resist profile. 14. The apparatus of claim 13, wherein the method further comprising creating a photolithography mask containing the set of mask patterns. 15. The apparatus of claim 13, wherein the measure of the deviation of the predicted 3D resist profile with respect to the desired 3D resist profile includes an inverse of a predicted resist sidewall slope. 16. The apparatus of claim 13, wherein the measure of the deviation of the predicted 3D resist profile with respect to the desired 3D resist profile includes differences between predicted critical dimensions (CDs) and target CDs at multiple resist heights. 17. The apparatus of claim 13, wherein determining the set of retargeted patterns based on the set of target patterns comprises:
computing etch biases at a set of evaluation points in the set of target patterns by using an etch-bias model; and determining the set of retargeted patterns by adjusting the set of target patterns based on the computed etch biases. 18. The apparatus of claim 17, wherein the etch bias model comprises one or more of the following terms:
a constant bias, a short range density function, a long range density function, a visible area function, a blocked area function, and a function of a sidewall slope of a post-development resist layer. | Systems and techniques for three-dimension (3D) resist profile aware resolution enhancement techniques are described. 3D resist profile aware resolution enhancement models can be calibrated based on empirical data. Next, the 3D resist profile aware resolution enhancement models can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.1. A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method to determine a set of mask patterns for printing a set of target patterns by using a semiconductor manufacturing process, wherein the semiconductor manufacturing process includes a photolithography process and an etching process, the method comprising:
determining a set of retargeted patterns based on the set of target patterns; and determining the set of mask patterns based on the set of retargeted patterns by optimizing an objective function that comprises a measure of a deviation of a predicted three-dimensional (3D) resist profile with respect to a desired 3D resist profile. 2. The non-transitory computer-readable storage medium of claim 1, wherein the method further comprising creating a photolithography mask containing the set of mask patterns. 3. The non-transitory computer-readable storage medium of claim 1, wherein the measure of the deviation of the predicted 3D resist profile with respect to the desired 3D resist profile includes an inverse of a predicted resist sidewall slope. 4. The non-transitory computer-readable storage medium of claim 1, wherein the measure of the deviation of the predicted 3D resist profile with respect to the desired 3D resist profile includes differences between predicted critical dimensions (CDs) and target CDs at multiple resist heights. 5. The non-transitory computer-readable storage medium of claim 1, wherein determining the set of retargeted patterns based on the set of target patterns comprises:
computing etch biases at a set of evaluation points in the set of target patterns by using an etch-bias model; and determining the set of retargeted patterns by adjusting the set of target patterns based on the computed etch biases. 6. The non-transitory computer-readable storage medium of claim 5, wherein the etch bias model comprises one or more of the following terms:
a constant bias, a short range density function, a long range density function, a visible area function, a blocked area function, and a function of a sidewall slope of a post-development resist layer. 7. A method to determine a set of mask patterns for printing a set of target patterns by using a semiconductor manufacturing process, wherein the semiconductor manufacturing process includes a photolithography process and an etching process, the method comprising:
a computer determining a set of retargeted patterns based on the set of target patterns; and the computer determining the set of mask patterns based on the set of retargeted patterns by optimizing an objective function that comprises a measure of a deviation of a predicted three-dimensional (3D) resist profile with respect to a desired 3D resist profile. 8. The method of claim 7, further comprising creating a photolithography mask containing the set of mask patterns. 9. The method of claim 7, wherein the measure of the deviation of the predicted 3D resist profile with respect to the desired 3D resist profile includes an inverse of a predicted resist sidewall slope. 10. The method of claim 7, wherein the measure of the deviation of the predicted 3D resist profile with respect to the desired 3D resist profile includes differences between predicted critical dimensions (CDs) and target CDs at multiple resist heights. 11. The method of claim 7, wherein determining the set of retargeted patterns based on the set of target patterns comprises:
computing etch biases at a set of evaluation points in the set of target patterns by using an etch-bias model; and determining the set of retargeted patterns by adjusting the set of target patterns based on the computed etch biases. 12. The method of claim 11, wherein the etch bias model comprises one or more of the following terms:
a constant bias, a short range density function, a long range density function, a visible area function, a blocked area function, and a function of a sidewall slope of a post-development resist layer. 13. An apparatus, comprising:
a processor; and a non-transitory computer-readable storage medium storing instructions that, when executed by the processor, cause the apparatus to perform a method to determine a set of mask patterns for printing a set of target patterns by using a semiconductor manufacturing process, wherein the semiconductor manufacturing process includes a photolithography process and an etching process, the method comprising:
determining a set of retargeted patterns based on the set of target patterns; and
determining the set of mask patterns based on the set of retargeted patterns by optimizing an objective function that comprises a measure of a deviation of a predicted three-dimensional (3D) resist profile with respect to a desired 3D resist profile. 14. The apparatus of claim 13, wherein the method further comprising creating a photolithography mask containing the set of mask patterns. 15. The apparatus of claim 13, wherein the measure of the deviation of the predicted 3D resist profile with respect to the desired 3D resist profile includes an inverse of a predicted resist sidewall slope. 16. The apparatus of claim 13, wherein the measure of the deviation of the predicted 3D resist profile with respect to the desired 3D resist profile includes differences between predicted critical dimensions (CDs) and target CDs at multiple resist heights. 17. The apparatus of claim 13, wherein determining the set of retargeted patterns based on the set of target patterns comprises:
computing etch biases at a set of evaluation points in the set of target patterns by using an etch-bias model; and determining the set of retargeted patterns by adjusting the set of target patterns based on the computed etch biases. 18. The apparatus of claim 17, wherein the etch bias model comprises one or more of the following terms:
a constant bias, a short range density function, a long range density function, a visible area function, a blocked area function, and a function of a sidewall slope of a post-development resist layer. | 2,800 |
11,859 | 11,859 | 15,606,456 | 2,895 | Light-absorbing masks and methods of dicing semiconductor wafers are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits involves forming a mask above the semiconductor wafer. The mask includes a water-soluble matrix based on a solid component and water, and a light-absorber species throughout the water-soluble matrix. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask with gaps and corresponding trenches in the semiconductor wafer in regions between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the patterned mask to extend the trenches and to singulate the integrated circuits. The patterned mask protects the integrated circuits during the plasma etching. | 1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a water-soluble matrix based on a solid component and water, and the mask comprising a light-absorber species throughout the water-soluble matrix; patterning the mask and a portion of the semiconductor wafer with a laser scribing process to provide a patterned mask with gaps and corresponding trenches in the semiconductor wafer in regions between the integrated circuits, wherein patterning the mask with the laser scribing process comprises patterning with a laser beam, wherein the light-absorber species of the mask confines a first portion of the laser beam to the mask during the patterning, and wherein a second portion of the laser beam is confined to the semiconductor wafer during the patterning; and plasma etching the semiconductor wafer through the gaps in the patterned mask to extend the trenches and to singulate the integrated circuits, wherein the patterned mask protects the integrated circuits during the plasma etching. 2. The method of claim 1, wherein the laser beam is a Gaussian beam, wherein the light-absorber species of the mask confines a trailing portion of the Gaussian beam to the mask during the patterning, and wherein a leading portion of the Gaussian beam is confined to the semiconductor wafer during the patterning. 3. The method of claim 1, wherein the light-absorber species is a water soluble dye dissolved in the water-soluble matrix. 4. The method of claim 1, wherein the light-absorber species is a nano-dispersion of pigments throughout the water-soluble matrix. 5. The method of claim 1, wherein the mask further comprises a plurality of particles dispersed throughout the water-soluble matrix, wherein a ratio of weight % of the solid component to weight % of the plurality of particles is in a range of 1:0.1-1:4. 6. The method of claim 5, wherein the plurality of particles has an average diameter in a range of 5-100 nanometers. 7. The method of claim 6, wherein the plurality of particles of the mask does not interfere with the laser scribing process during the patterning of the mask with a laser scribing process. 8. The method of claim 5, wherein plasma etching the semiconductor wafer comprises plasma etching a single crystalline silicon wafer, and wherein a ratio of an etch rate of the single crystalline silicon wafer to an etch rate of the mask is in a range of 15:1-170:1 during the plasma etching. 9. The method of claim 1, wherein forming the mask above the semiconductor wafer comprises spin-coating the mask on the semiconductor wafer. 10. The method of claim 1, further comprising:
subsequent to plasma etching the semiconductor wafer, removing the patterned mask using an aqueous solution. 11. The method of claim 1, further comprising:
subsequent to patterning the mask and prior to plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits, cleaning the trenches in the semiconductor wafer with a plasma cleaning process. 12. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a water-soluble matrix based on a solid component and water, and the mask comprising a light-absorber species throughout the water-soluble matrix; and patterning the mask and singulating the integrated circuits of the semiconductor wafer with a laser scribing process, wherein patterning the mask with the laser scribing process comprises patterning with a laser beam, wherein the light-absorber species of the mask confines a first portion of the laser beam to the mask during the patterning, and wherein a second portion of the laser beam is confined to the semiconductor wafer during the patterning. 13. The method of claim 12, wherein the laser beam is a Gaussian beam, wherein the light-absorber species of the mask confines a trailing portion of the Gaussian beam to the mask during the patterning, and wherein a leading portion of the Gaussian beam is confined to the semiconductor wafer during the patterning. 14. The method of claim 12, wherein the light-absorber species is a water soluble dye dissolved in the water-soluble matrix. 15. The method of claim 12, wherein the light-absorber species is a nano-dispersion of pigments throughout the water-soluble matrix. 16. The method of claim 12, wherein forming the mask above the semiconductor wafer comprises spin-coating the mask on the semiconductor wafer. 17. The method of claim 12, further comprising:
subsequent to patterning the mask and singulating the integrated circuits of the semiconductor wafer with the laser scribing process, removing the patterned mask using an aqueous solution. 18. A mask for a wafer singulation process, the mask comprising:
a water-soluble matrix based on a solid component and water; a light-absorber species throughout the water-soluble matrix; and a plurality of particles dispersed throughout the water-soluble matrix, the plurality of particles different than the light-absorber species. 19. The mask of claim 18, wherein the light-absorber species is selected from the group consisting of a water soluble dye dissolved in the water-soluble matrix, and a nano-dispersion of pigments throughout the water-soluble matrix. 20. The mask of claim 18, wherein the plurality of particles has an average diameter approximately in the range of 5-100 nanometers, and wherein a ratio of weight % of the solid component to weight % of the plurality of particles is approximately in the range of 1:0.1-1:4. | Light-absorbing masks and methods of dicing semiconductor wafers are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits involves forming a mask above the semiconductor wafer. The mask includes a water-soluble matrix based on a solid component and water, and a light-absorber species throughout the water-soluble matrix. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask with gaps and corresponding trenches in the semiconductor wafer in regions between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the patterned mask to extend the trenches and to singulate the integrated circuits. The patterned mask protects the integrated circuits during the plasma etching.1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a water-soluble matrix based on a solid component and water, and the mask comprising a light-absorber species throughout the water-soluble matrix; patterning the mask and a portion of the semiconductor wafer with a laser scribing process to provide a patterned mask with gaps and corresponding trenches in the semiconductor wafer in regions between the integrated circuits, wherein patterning the mask with the laser scribing process comprises patterning with a laser beam, wherein the light-absorber species of the mask confines a first portion of the laser beam to the mask during the patterning, and wherein a second portion of the laser beam is confined to the semiconductor wafer during the patterning; and plasma etching the semiconductor wafer through the gaps in the patterned mask to extend the trenches and to singulate the integrated circuits, wherein the patterned mask protects the integrated circuits during the plasma etching. 2. The method of claim 1, wherein the laser beam is a Gaussian beam, wherein the light-absorber species of the mask confines a trailing portion of the Gaussian beam to the mask during the patterning, and wherein a leading portion of the Gaussian beam is confined to the semiconductor wafer during the patterning. 3. The method of claim 1, wherein the light-absorber species is a water soluble dye dissolved in the water-soluble matrix. 4. The method of claim 1, wherein the light-absorber species is a nano-dispersion of pigments throughout the water-soluble matrix. 5. The method of claim 1, wherein the mask further comprises a plurality of particles dispersed throughout the water-soluble matrix, wherein a ratio of weight % of the solid component to weight % of the plurality of particles is in a range of 1:0.1-1:4. 6. The method of claim 5, wherein the plurality of particles has an average diameter in a range of 5-100 nanometers. 7. The method of claim 6, wherein the plurality of particles of the mask does not interfere with the laser scribing process during the patterning of the mask with a laser scribing process. 8. The method of claim 5, wherein plasma etching the semiconductor wafer comprises plasma etching a single crystalline silicon wafer, and wherein a ratio of an etch rate of the single crystalline silicon wafer to an etch rate of the mask is in a range of 15:1-170:1 during the plasma etching. 9. The method of claim 1, wherein forming the mask above the semiconductor wafer comprises spin-coating the mask on the semiconductor wafer. 10. The method of claim 1, further comprising:
subsequent to plasma etching the semiconductor wafer, removing the patterned mask using an aqueous solution. 11. The method of claim 1, further comprising:
subsequent to patterning the mask and prior to plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits, cleaning the trenches in the semiconductor wafer with a plasma cleaning process. 12. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a water-soluble matrix based on a solid component and water, and the mask comprising a light-absorber species throughout the water-soluble matrix; and patterning the mask and singulating the integrated circuits of the semiconductor wafer with a laser scribing process, wherein patterning the mask with the laser scribing process comprises patterning with a laser beam, wherein the light-absorber species of the mask confines a first portion of the laser beam to the mask during the patterning, and wherein a second portion of the laser beam is confined to the semiconductor wafer during the patterning. 13. The method of claim 12, wherein the laser beam is a Gaussian beam, wherein the light-absorber species of the mask confines a trailing portion of the Gaussian beam to the mask during the patterning, and wherein a leading portion of the Gaussian beam is confined to the semiconductor wafer during the patterning. 14. The method of claim 12, wherein the light-absorber species is a water soluble dye dissolved in the water-soluble matrix. 15. The method of claim 12, wherein the light-absorber species is a nano-dispersion of pigments throughout the water-soluble matrix. 16. The method of claim 12, wherein forming the mask above the semiconductor wafer comprises spin-coating the mask on the semiconductor wafer. 17. The method of claim 12, further comprising:
subsequent to patterning the mask and singulating the integrated circuits of the semiconductor wafer with the laser scribing process, removing the patterned mask using an aqueous solution. 18. A mask for a wafer singulation process, the mask comprising:
a water-soluble matrix based on a solid component and water; a light-absorber species throughout the water-soluble matrix; and a plurality of particles dispersed throughout the water-soluble matrix, the plurality of particles different than the light-absorber species. 19. The mask of claim 18, wherein the light-absorber species is selected from the group consisting of a water soluble dye dissolved in the water-soluble matrix, and a nano-dispersion of pigments throughout the water-soluble matrix. 20. The mask of claim 18, wherein the plurality of particles has an average diameter approximately in the range of 5-100 nanometers, and wherein a ratio of weight % of the solid component to weight % of the plurality of particles is approximately in the range of 1:0.1-1:4. | 2,800 |
11,860 | 11,860 | 16,121,570 | 2,849 | Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input. | 1. A circuit, comprising:
an inverter storage loop for storing state information; first and second p-channel field-effect transistors (PFETs) connected to a first node of the inverter storage loop; and third and fourth PFETs connected to a second node of the inverter storage loop; wherein gate terminals of the first and fourth PFETs are connected to a first control input, and gate terminals of the second and third PFETs are connected to a second control input. 2. The circuit of claim 1, wherein:
a drain terminal of the first PFET and a source terminal of the second PFET are connected to the first node of the inverter storage loop; and a drain terminal of the third PFET and a source terminal of the fourth PFET are connected to the second node of the inverter storage loop. 3. The circuit of claim 2, wherein:
a source terminal of the first PFET and a source terminal of the third PFET are connected to a voltage source; and a drain terminal of the second PFET and a drain terminal of the fourth PFET are connected to a voltage drain. 4. The circuit of claim 1, wherein:
the first control input is a Set control input; and the second control input is a Reset control input. 5. The circuit of claim 4, wherein the Set and Reset control inputs are active low control inputs. 6. The circuit of claim 1, wherein the circuit is implemented in a 16 nm process. 7. The circuit of claim 1, wherein the inverter storage loop includes a cross-coupled first inverter and second inverter. 8. The circuit of claim 7, wherein the cross-coupled first inverter and second inverter each include a PFET and an n-channel field-effect transistor (NFET). 9. The circuit of claim 1, wherein an output at the first node is a Set latch output and an output at the second node is a Reset latch output. 10. The circuit of claim 1, comprising:
a first FET connected between the first node of the inverter storage loop and the first and second PFETs, a gate terminal of the first FET being connected to an Enable B multiplexing control input; and a second FET connected between the second node of the inverter storage loop and the third and fourth PFETs, a gate terminal of the second FET being connected to an Enable multiplexing control input. 11. The circuit of claim 10, wherein the inverter storage loop is a first inverter storage loop, the circuit comprising:
a second inverter storage loop for storing state information; sixth and seventh PFETs connected to a first node of the second inverter storage loop, a gate terminal of the sixth PFET being connected to the first control input and a gate terminal of the seventh PFET being connected to the second control input; eighth and ninth PFETs connected to a second node of the second inverter storage loop, a gate terminal of the eighth PFET being connected to the second control input and a gate terminal of the ninth PFET being connected to the first control input; a third FET connected between the first node of the second inverter storage loop and the sixth and seventh PFETs, a gate terminal of the third FET being connected to the Enable multiplexing control input; and a fourth FET connected between the second node of the second inverter storage loop and the eighth and ninth PFETs, a gate terminal of the fourth FET being connected to the Enable B multiplexing control input; wherein the first node of the first inverter storage loop is connected to the first node of the second inverter storage loop and the second node of the first inverter storage loop is connected to the second node of the second inverter storage loop. 12. The circuit of claim 1, comprising:
a fifth PFET connected between the first PFET and a voltage source; a sixth PFET connected between the third PFET and the voltage source; a first n-channel field-effect transistor (NFET) connected between the second PFET and a voltage drain; and a second NFET connected between the fourth PFET and the voltage drain; wherein gate terminals of the fifth and sixth PFETs are connected to an Enable B multiplexer control input and gate terminals of the first and second NFETs are connected to an Enable multiplexer control input. 13. The circuit of claim 12, wherein the inverter storage loop is a first inverter storage loop, the circuit comprising:
a second inverter storage loop for storing state information; seventh and eighth PFETs connected to a first node of the second inverter storage loop, a gate terminal of the seventh PFET being connected to the first control input and a gate terminal of the eighth PFET being connected to the second control input; ninth and tenth PFETs connected to a second node of the second inverter storage loop, a gate terminal of the ninth PFET being connected to the second control input and a gate terminal of the tenth PFET being connected to the first control input; an eleventh PFET connected between the seventh PFET and the voltage source; a twelfth PFET connected between the ninth PFET and the voltage source; a third NFET connected between the eighth PFET and the voltage drain; and a fourth NFET connected between the tenth PFET and the voltage drain; wherein gate terminals of the eleventh and twelfth PFETs are connected to the Enable multiplexer control input and gate terminals of the third and fourth NFETs are connected to the Enable B multiplexer control input; and wherein the first node of the first inverter storage loop is connected to the first node of the second inverter storage loop and the second node of the first inverter storage loop is connected to the second node of the second inverter storage loop. 14. A set-reset (SR) latch, comprising:
an inverter storage loop for storing state information; first and second n-channel field-effect transistors (NFETs) connected to a first node of the inverter storage loop; and third and fourth NFETs connected to a second node of the inverter storage loop, wherein gate terminals of the first and fourth NFETs are connected to a first control input, and gate terminals of the second and third NFETs are connected to a second control input. 15. The SR latch of claim 14, wherein:
the first control input is a Set control input; and the second control input is a Reset control input. 16. The SR latch of claim 15, wherein the Set and Reset control inputs are active high control inputs. 17. A method for manufacturing a set-reset (SR) latch, comprising:
forming an inverter storage loop for storing state information; forming first and second p-channel field-effect transistors (PFETs) connected to a first node of the inverter storage loop; and forming third and fourth PFETs connected to a second node of the inverter storage loop. 18. The method of claim 17, wherein the inverter storage loop and the first, second, third, and fourth PFETs are formed using a 16 nm process. 19. The method of claim 18, wherein forming the inverter storage loop includes:
forming a cross-coupled first inverter and second inverter, the cross-coupled first inverter and second inverter each including a PFET and an n-channel field-effect transistor (NFET). 20. The method of claim 17, comprising:
connecting gate terminals of the first and fourth PFETs to a first control input; and connecting gate terminals of the second and third PFETs to a second control input. | Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.1. A circuit, comprising:
an inverter storage loop for storing state information; first and second p-channel field-effect transistors (PFETs) connected to a first node of the inverter storage loop; and third and fourth PFETs connected to a second node of the inverter storage loop; wherein gate terminals of the first and fourth PFETs are connected to a first control input, and gate terminals of the second and third PFETs are connected to a second control input. 2. The circuit of claim 1, wherein:
a drain terminal of the first PFET and a source terminal of the second PFET are connected to the first node of the inverter storage loop; and a drain terminal of the third PFET and a source terminal of the fourth PFET are connected to the second node of the inverter storage loop. 3. The circuit of claim 2, wherein:
a source terminal of the first PFET and a source terminal of the third PFET are connected to a voltage source; and a drain terminal of the second PFET and a drain terminal of the fourth PFET are connected to a voltage drain. 4. The circuit of claim 1, wherein:
the first control input is a Set control input; and the second control input is a Reset control input. 5. The circuit of claim 4, wherein the Set and Reset control inputs are active low control inputs. 6. The circuit of claim 1, wherein the circuit is implemented in a 16 nm process. 7. The circuit of claim 1, wherein the inverter storage loop includes a cross-coupled first inverter and second inverter. 8. The circuit of claim 7, wherein the cross-coupled first inverter and second inverter each include a PFET and an n-channel field-effect transistor (NFET). 9. The circuit of claim 1, wherein an output at the first node is a Set latch output and an output at the second node is a Reset latch output. 10. The circuit of claim 1, comprising:
a first FET connected between the first node of the inverter storage loop and the first and second PFETs, a gate terminal of the first FET being connected to an Enable B multiplexing control input; and a second FET connected between the second node of the inverter storage loop and the third and fourth PFETs, a gate terminal of the second FET being connected to an Enable multiplexing control input. 11. The circuit of claim 10, wherein the inverter storage loop is a first inverter storage loop, the circuit comprising:
a second inverter storage loop for storing state information; sixth and seventh PFETs connected to a first node of the second inverter storage loop, a gate terminal of the sixth PFET being connected to the first control input and a gate terminal of the seventh PFET being connected to the second control input; eighth and ninth PFETs connected to a second node of the second inverter storage loop, a gate terminal of the eighth PFET being connected to the second control input and a gate terminal of the ninth PFET being connected to the first control input; a third FET connected between the first node of the second inverter storage loop and the sixth and seventh PFETs, a gate terminal of the third FET being connected to the Enable multiplexing control input; and a fourth FET connected between the second node of the second inverter storage loop and the eighth and ninth PFETs, a gate terminal of the fourth FET being connected to the Enable B multiplexing control input; wherein the first node of the first inverter storage loop is connected to the first node of the second inverter storage loop and the second node of the first inverter storage loop is connected to the second node of the second inverter storage loop. 12. The circuit of claim 1, comprising:
a fifth PFET connected between the first PFET and a voltage source; a sixth PFET connected between the third PFET and the voltage source; a first n-channel field-effect transistor (NFET) connected between the second PFET and a voltage drain; and a second NFET connected between the fourth PFET and the voltage drain; wherein gate terminals of the fifth and sixth PFETs are connected to an Enable B multiplexer control input and gate terminals of the first and second NFETs are connected to an Enable multiplexer control input. 13. The circuit of claim 12, wherein the inverter storage loop is a first inverter storage loop, the circuit comprising:
a second inverter storage loop for storing state information; seventh and eighth PFETs connected to a first node of the second inverter storage loop, a gate terminal of the seventh PFET being connected to the first control input and a gate terminal of the eighth PFET being connected to the second control input; ninth and tenth PFETs connected to a second node of the second inverter storage loop, a gate terminal of the ninth PFET being connected to the second control input and a gate terminal of the tenth PFET being connected to the first control input; an eleventh PFET connected between the seventh PFET and the voltage source; a twelfth PFET connected between the ninth PFET and the voltage source; a third NFET connected between the eighth PFET and the voltage drain; and a fourth NFET connected between the tenth PFET and the voltage drain; wherein gate terminals of the eleventh and twelfth PFETs are connected to the Enable multiplexer control input and gate terminals of the third and fourth NFETs are connected to the Enable B multiplexer control input; and wherein the first node of the first inverter storage loop is connected to the first node of the second inverter storage loop and the second node of the first inverter storage loop is connected to the second node of the second inverter storage loop. 14. A set-reset (SR) latch, comprising:
an inverter storage loop for storing state information; first and second n-channel field-effect transistors (NFETs) connected to a first node of the inverter storage loop; and third and fourth NFETs connected to a second node of the inverter storage loop, wherein gate terminals of the first and fourth NFETs are connected to a first control input, and gate terminals of the second and third NFETs are connected to a second control input. 15. The SR latch of claim 14, wherein:
the first control input is a Set control input; and the second control input is a Reset control input. 16. The SR latch of claim 15, wherein the Set and Reset control inputs are active high control inputs. 17. A method for manufacturing a set-reset (SR) latch, comprising:
forming an inverter storage loop for storing state information; forming first and second p-channel field-effect transistors (PFETs) connected to a first node of the inverter storage loop; and forming third and fourth PFETs connected to a second node of the inverter storage loop. 18. The method of claim 17, wherein the inverter storage loop and the first, second, third, and fourth PFETs are formed using a 16 nm process. 19. The method of claim 18, wherein forming the inverter storage loop includes:
forming a cross-coupled first inverter and second inverter, the cross-coupled first inverter and second inverter each including a PFET and an n-channel field-effect transistor (NFET). 20. The method of claim 17, comprising:
connecting gate terminals of the first and fourth PFETs to a first control input; and connecting gate terminals of the second and third PFETs to a second control input. | 2,800 |
11,861 | 11,861 | 15,213,868 | 2,831 | An arrangement with a connector for at least one electrical cable is indicated, that is surrounded by a cover, having an electrical conductor, which has a plurality of individual wires. The connector has a pipe shaped clamping body composed of metal to receive the conductors of the cables, in the walls of which at least one position with two threads is provided, mounted with interacting throughholes, their axis V-formed extended at an angle, lying between 100° and 180 °. In the mounted position the clamping screws are attached tightly in the throughholes of the conductor, which act in the same area of the conductor. In the mounted position, the clamping screws screwed in the two throughholes are rounded on their points each with a radius lying between 0.15×D and 0.5×D, with the diameter D of the threaded part of the clamping screws. | 1. A connector for connecting one or more electrical cables, the cables being surrounded by a cover and having electrical conductors that are formed from a plurality of individual wires, said connector comprising:
a pipe shaped clamping body made of metal for receiving said electrical conductors of the cables, wherein walls of said clamping body, at at least one position along the length of the clamping body, have two throughholes with threads, said throughholes having longitudinal central axes that extend V-shaped through said walls at an angle relative to one another, the angle lying between 100° and 180°, wherein when said conductor is in a mounted position, two clamping screws are arranged in the throughholes to securely fasten the conductor, wherein when said conductor is in the mounted position, the two clamping screws screwed in the throughholes bear upon a same side of the conductor located in the clamping body at a same longitudinal position along a long axis of the conductor and wherein both of the two clamping screws, on a front peak that contacts the conductor, are rounded, with a radius that lies between 0.15×D and 0.5×D, D being the diameter of a threaded part of the two clamping screws. 2. Connector according to claim 1, wherein the angle enclosed by the axes of the two throughholes is 120°. 3. Connector according to claim 1, wherein the radius of the rounding of the peak for the two clamping screws is 0.28×D. 4. Connector according to claim 1, wherein the clamping body is constructed as the pipe to connect two electrical cables. 5. Connector according to claim 1, wherein the clamping body is locked on one front side and has on the one front side an electrical contact element protruding outwards. 6. Connector according to claim 1, wherein said connector is configured to connect the at least one electrical cable with the plurality of individual wires composed of aluminum or aluminum alloy. | An arrangement with a connector for at least one electrical cable is indicated, that is surrounded by a cover, having an electrical conductor, which has a plurality of individual wires. The connector has a pipe shaped clamping body composed of metal to receive the conductors of the cables, in the walls of which at least one position with two threads is provided, mounted with interacting throughholes, their axis V-formed extended at an angle, lying between 100° and 180 °. In the mounted position the clamping screws are attached tightly in the throughholes of the conductor, which act in the same area of the conductor. In the mounted position, the clamping screws screwed in the two throughholes are rounded on their points each with a radius lying between 0.15×D and 0.5×D, with the diameter D of the threaded part of the clamping screws.1. A connector for connecting one or more electrical cables, the cables being surrounded by a cover and having electrical conductors that are formed from a plurality of individual wires, said connector comprising:
a pipe shaped clamping body made of metal for receiving said electrical conductors of the cables, wherein walls of said clamping body, at at least one position along the length of the clamping body, have two throughholes with threads, said throughholes having longitudinal central axes that extend V-shaped through said walls at an angle relative to one another, the angle lying between 100° and 180°, wherein when said conductor is in a mounted position, two clamping screws are arranged in the throughholes to securely fasten the conductor, wherein when said conductor is in the mounted position, the two clamping screws screwed in the throughholes bear upon a same side of the conductor located in the clamping body at a same longitudinal position along a long axis of the conductor and wherein both of the two clamping screws, on a front peak that contacts the conductor, are rounded, with a radius that lies between 0.15×D and 0.5×D, D being the diameter of a threaded part of the two clamping screws. 2. Connector according to claim 1, wherein the angle enclosed by the axes of the two throughholes is 120°. 3. Connector according to claim 1, wherein the radius of the rounding of the peak for the two clamping screws is 0.28×D. 4. Connector according to claim 1, wherein the clamping body is constructed as the pipe to connect two electrical cables. 5. Connector according to claim 1, wherein the clamping body is locked on one front side and has on the one front side an electrical contact element protruding outwards. 6. Connector according to claim 1, wherein said connector is configured to connect the at least one electrical cable with the plurality of individual wires composed of aluminum or aluminum alloy. | 2,800 |
11,862 | 11,862 | 15,760,154 | 2,853 | An example printing device composing a first printhead and a second printhead is described. In some examples the example printing device comprises a controller. The example printing device is to operate in a first operating mode in which the first printhead is to dispense a first printing substance, the first printing substance to transfer color via a first colorant transfer mechanism, and to operate in a second operating mode in which the second printhead is to dispense a second printing substance, the second printing substance to transfer via a second colorant transfer mechanism different to the first colorant transfer mechanism. An example controller is to cause the example printing device to operate in a selected one of the first and second operating modes. | 1. A printing device comprising a first printhead, a second printhead, and a controller;
wherein the printing device is to operate in a first operating mode in which the first printhead is to dispense a first printing substance, the first printing substance to transfer color via a first colorant transfer mechanism, and to operate in a second operating mode in which the second printhead is to dispense a second printing substance, the second printing substance to transfer color via a second colorant transfer mechanism different to the first colorant transfer mechanism; and wherein the controller is to cause the printing device to operate in a selected one of the first and second operating modes. 2. A printing device according to claim 1, wherein the first printing substance comprises a first ink vehicle and the second printing substance comprises a second ink vehicle different to the first ink vehicle. 3. A printing device according to claim 1, wherein the first printing substance is a latex ink and the second printing substance is a dye sublimation ink. 4. A printing device according to claim 1, wherein the first printing substance is a latex ink and the second printing substance is an ultraviolet-curable ink. 5. A printing device according to claim 1, wherein the first printing substance is an ultraviolet-curable ink and the second printing substance is a dye sublimation ink. 6. A printing device according to claim 1, comprising a curing module to operate in a first curing mode when the printing device is operated in the first operating mode, and to operate in a second curing mode when the printing device is operated in the second operating mode. 7. A printing device according to claim 1, wherein the controller is to cause the printing device to operate in a selected one of the first and second operating modes on the basis of a selected substrate. 8. A printing device according to claim 1, wherein the printing device is to operate in a third operating mode in which the printing device is to perform a printing event in which the first printhead is to dispense the first printing substance and in which the second printhead is to dispense the second printing fluid, and wherein the controller is to cause the printing device to operate in a selected one of the first, second and third operating modes. 9. A printing device comprising:
a first printhead to print a first printing substance to transfer color via a first colorant transfer mechanism; a second printhead to print a second printing substance to transfer color via a second colorant transfer mechanism different to the first colorant transfer mechanism; and a curing module to operate in a first operating mode to fix the first printing substance when the first printhead is used to print the first, printing substance, and to operate in a second operating mode, different to the first operating mode, to fix the second printing substance when the second printhead is used to print the second printing substance. 10. A printing device according to claim 9, wherein, in the first operating mode, the curing module is to heat the first printing substance to a first maximum temperature and, in the second operating mode, the curing module is to heat the second printing substance to a second maximum temperature, different to the first maximum temperature. 11. A printing device according to claim 9, wherein, in the first operating mode, the curing module is to heat the first printing substance to a maximum temperature in the range 80° C.-125° C. and, in the second operating mode, the curing module is to heat the second printing substance to a maximum temperature in the range 150° C.-220° C. 12. A printing device according to claim 9, wherein, in the first curing mode, the curing module is to apply heat to the first printing substance for a first maximum length of time and, in the second operating mode, the curing module is to apply heat to the second printing substance for a second maximum length of time, different to the first maximum length of time. 13. A printing device according to claim 9, wherein, in the first curing mode, the curing module is to direct hot air to the first printing substance and, in the second operating mode, the curing module is to irradiate the second printing substance with electro magnetic radiation. 14. A printing device according to claim 13, wherein the electromagnetic radiation comprises one of infrared radiation and ultraviolet radiation. 15. A method of operating a printing device, the method comprising:
selecting one of a plurality of operating modes of the printing device, the operating modes comprising: a first operating mode in which a first printing substance is dispensed from a first printhead of the printing device, the first printing substance to transfer color via a first colorant transfer mechanism; and a second operating mode in which a second printing substance is dispensed from a second printhead of the printing device, the second printing substance to transfer color via a second colorant transfer mechanism different to the first colorant transfer mechanism; and operating the printing device in accordance with the selected operating mode. | An example printing device composing a first printhead and a second printhead is described. In some examples the example printing device comprises a controller. The example printing device is to operate in a first operating mode in which the first printhead is to dispense a first printing substance, the first printing substance to transfer color via a first colorant transfer mechanism, and to operate in a second operating mode in which the second printhead is to dispense a second printing substance, the second printing substance to transfer via a second colorant transfer mechanism different to the first colorant transfer mechanism. An example controller is to cause the example printing device to operate in a selected one of the first and second operating modes.1. A printing device comprising a first printhead, a second printhead, and a controller;
wherein the printing device is to operate in a first operating mode in which the first printhead is to dispense a first printing substance, the first printing substance to transfer color via a first colorant transfer mechanism, and to operate in a second operating mode in which the second printhead is to dispense a second printing substance, the second printing substance to transfer color via a second colorant transfer mechanism different to the first colorant transfer mechanism; and wherein the controller is to cause the printing device to operate in a selected one of the first and second operating modes. 2. A printing device according to claim 1, wherein the first printing substance comprises a first ink vehicle and the second printing substance comprises a second ink vehicle different to the first ink vehicle. 3. A printing device according to claim 1, wherein the first printing substance is a latex ink and the second printing substance is a dye sublimation ink. 4. A printing device according to claim 1, wherein the first printing substance is a latex ink and the second printing substance is an ultraviolet-curable ink. 5. A printing device according to claim 1, wherein the first printing substance is an ultraviolet-curable ink and the second printing substance is a dye sublimation ink. 6. A printing device according to claim 1, comprising a curing module to operate in a first curing mode when the printing device is operated in the first operating mode, and to operate in a second curing mode when the printing device is operated in the second operating mode. 7. A printing device according to claim 1, wherein the controller is to cause the printing device to operate in a selected one of the first and second operating modes on the basis of a selected substrate. 8. A printing device according to claim 1, wherein the printing device is to operate in a third operating mode in which the printing device is to perform a printing event in which the first printhead is to dispense the first printing substance and in which the second printhead is to dispense the second printing fluid, and wherein the controller is to cause the printing device to operate in a selected one of the first, second and third operating modes. 9. A printing device comprising:
a first printhead to print a first printing substance to transfer color via a first colorant transfer mechanism; a second printhead to print a second printing substance to transfer color via a second colorant transfer mechanism different to the first colorant transfer mechanism; and a curing module to operate in a first operating mode to fix the first printing substance when the first printhead is used to print the first, printing substance, and to operate in a second operating mode, different to the first operating mode, to fix the second printing substance when the second printhead is used to print the second printing substance. 10. A printing device according to claim 9, wherein, in the first operating mode, the curing module is to heat the first printing substance to a first maximum temperature and, in the second operating mode, the curing module is to heat the second printing substance to a second maximum temperature, different to the first maximum temperature. 11. A printing device according to claim 9, wherein, in the first operating mode, the curing module is to heat the first printing substance to a maximum temperature in the range 80° C.-125° C. and, in the second operating mode, the curing module is to heat the second printing substance to a maximum temperature in the range 150° C.-220° C. 12. A printing device according to claim 9, wherein, in the first curing mode, the curing module is to apply heat to the first printing substance for a first maximum length of time and, in the second operating mode, the curing module is to apply heat to the second printing substance for a second maximum length of time, different to the first maximum length of time. 13. A printing device according to claim 9, wherein, in the first curing mode, the curing module is to direct hot air to the first printing substance and, in the second operating mode, the curing module is to irradiate the second printing substance with electro magnetic radiation. 14. A printing device according to claim 13, wherein the electromagnetic radiation comprises one of infrared radiation and ultraviolet radiation. 15. A method of operating a printing device, the method comprising:
selecting one of a plurality of operating modes of the printing device, the operating modes comprising: a first operating mode in which a first printing substance is dispensed from a first printhead of the printing device, the first printing substance to transfer color via a first colorant transfer mechanism; and a second operating mode in which a second printing substance is dispensed from a second printhead of the printing device, the second printing substance to transfer color via a second colorant transfer mechanism different to the first colorant transfer mechanism; and operating the printing device in accordance with the selected operating mode. | 2,800 |
11,863 | 11,863 | 15,638,878 | 2,853 | A method of making a relief image printing element from a photosensitive printing blank is provided. A photosensitive printing blank with a laser ablatable layer disposed on at least one photocurable layer is ablated with a laser to create an in situ mask. The printing blank is then exposed to at least one source of actinic radiation through the in situ mask to selectively cross link and cure portions of the photocurable layer. Diffusion of air into the at least one photocurable layer is limited during the exposing step and preferably at least one of the type, power and incident angle of illumination of the at least one source of actinic radiation is altered during the exposure step. The resulting relief image comprises a plurality of dots and a dot shape of the plurality of dots that provide optimal print performance on various substrates, including corrugated board. | 1. A flexographic relief image printing element comprising at least one photopolymer layer on a backing layer, wherein a plurality of dots in relief are created in the at least one photopolymer layer by selectively exposing the at least one photopolymer layer to actinic radiation to selectively crosslink portions of the at least one photopolymer layer and separating and removing the uncrosslinked portions of the at least one photopolymer layer, and wherein said plurality of dots comprise at least one characteristic selected from the group consisting of:
a) a planarity of a top surface of the dot is such that the radius of curvature of the top surface of the dot, rt, is greater than the total thickness of the at least one photopolymer layer; and b) an edge sharpness of the dots is such that the ratio of the radius of curvature at the intersection of the shoulder and the top surface of the dot, re, to the width of the top of the dot, p, is less than 5%; and wherein the plurality of printing dots exhibit a compound shoulder angle such that an angle nearest the top surface of the dot, θ1, is greater than 70° and an angle nearest a dot floor attachment, θ2, is less than 45°. 2. (canceled) 3. (canceled) 4. (canceled) 5. The flexographic relief image printing element according to claim 1, wherein the ratio of re:p is less than 2%. 6. The flexographic relief image printing element according to claim 1 wherein a dot relief of the printing element is greater than about 9% of the overall plate relief. 7. The flexographic relief image printing element according to claim 6, wherein the dot relief of the printing element is greater than about 12% of the overall plate relief. 8. A plurality of relief dots created in a relief image printing element, wherein the relief image printing element comprises, in order, a laser ablatable mask layer, at least one photopolymer layer, and a backing layer, wherein a plurality of dots in relief are created in the at least one photopolymer layer during a digital platemaking process, the digital platemaking process including the steps of (i) laser ablating a laser ablatable mask layer to create an in situ negative; (ii) selectively exposing the at least one photopolymer layer to actinic radiation through the in situ negative to selectively crosslink portions of the at least one photopolymer layer and (iii) separating and removing uncrosslinked portions of the at least one photopolymer layer, and
wherein said plurality of relief dots comprise at least one geometric characteristic selected from the group consisting of: (a) a planarity of a top surface of the relief dots, measured as the radius of curvature of the top surface of the dot, rt, is greater than the total thickness of the photopolymer layer; (b) a depth of relief between the relief dots, measured as a percentage of the overall plate relief, is greater than about 9%; and (c) an edge sharpness of the dots is such that the ratio of the radius of curvature at the intersection of the shoulder and the top surface of the dot, re, to the width of the top of the dot, p, is less than 5%; and wherein the plurality of printing dots exhibit a compound shoulder angle such that an angle nearest the top surface of the dot, θ1, is greater than 70° and an angle nearest a dot floor attachment, θ2, is less than 45°. 9. The plurality of relief dots according to claim 8, wherein said planarity of the top surface of the relief dots is such that the radius of curvature of the top surface of the dot, rt, is greater than the total thickness of the photopolymer layer. 10. (canceled) 11. (canceled) 12. (canceled) 13. The plurality of relief dots according to claim 8, wherein the depth of relief between the relief dots is greater than about 12% of the overall plate relief. 14. The plurality of relief dots according to claim 8 wherein the edge sharpness of the relief dots is such that the ratio of re:p is less than about 2 percent. 15. (canceled) 16. (canceled) 17. The flexographic relief image printing element according to claim 1, wherein an average surface roughness of the relief image printing element is less than about 100 nm. 18. The flexographic relief image printing element according to claim 1, wherein an average surface roughness of the relief image printing element is between about 700 and about 800 nm. 19. A plurality of relief dots created in a relief image printing element, wherein the relief image printing element (i) laser ablating the laser ablatable mask layer to create an in situ negative; (ii) laminating an oxygen barrier membrane to a top of the relief image printing element; (iii) selectively exposing the at least one photopolymer layer to actinic radiation through the in situ negative and the oxygen barrier membrane to selectively crosslink portions of the at least one photopolymer layer; and (iv) developing the relief image printing element to separate and remove uncrosslinked portions of the at least one photopolymer layer, and
wherein said plurality of relief dots comprise at least one geometric characteristic selected from the group consisting of: (a) a planarity of a top surface of the relief dots, measured as the radius of curvature of the top surface of the dot, rt, is greater than the total thickness of the photopolymer layer; (b) an edge sharpness of the dots is such that the ratio of the radius of curvature at the intersection of the shoulder and the top surface of the dot, re, to the width of the top of the dot, p, is less than 5%; and (c) a depth of relief between the relief dots, measured as a percentage of the overall plate relief, is greater than about 9%; and wherein the plurality of printing dots exhibit a compound shoulder angle such that an angle nearest the top surface of the dot, θ1, is greater than 70° and an angle nearest a dot floor attachment, θ2, is less than 45°. | A method of making a relief image printing element from a photosensitive printing blank is provided. A photosensitive printing blank with a laser ablatable layer disposed on at least one photocurable layer is ablated with a laser to create an in situ mask. The printing blank is then exposed to at least one source of actinic radiation through the in situ mask to selectively cross link and cure portions of the photocurable layer. Diffusion of air into the at least one photocurable layer is limited during the exposing step and preferably at least one of the type, power and incident angle of illumination of the at least one source of actinic radiation is altered during the exposure step. The resulting relief image comprises a plurality of dots and a dot shape of the plurality of dots that provide optimal print performance on various substrates, including corrugated board.1. A flexographic relief image printing element comprising at least one photopolymer layer on a backing layer, wherein a plurality of dots in relief are created in the at least one photopolymer layer by selectively exposing the at least one photopolymer layer to actinic radiation to selectively crosslink portions of the at least one photopolymer layer and separating and removing the uncrosslinked portions of the at least one photopolymer layer, and wherein said plurality of dots comprise at least one characteristic selected from the group consisting of:
a) a planarity of a top surface of the dot is such that the radius of curvature of the top surface of the dot, rt, is greater than the total thickness of the at least one photopolymer layer; and b) an edge sharpness of the dots is such that the ratio of the radius of curvature at the intersection of the shoulder and the top surface of the dot, re, to the width of the top of the dot, p, is less than 5%; and wherein the plurality of printing dots exhibit a compound shoulder angle such that an angle nearest the top surface of the dot, θ1, is greater than 70° and an angle nearest a dot floor attachment, θ2, is less than 45°. 2. (canceled) 3. (canceled) 4. (canceled) 5. The flexographic relief image printing element according to claim 1, wherein the ratio of re:p is less than 2%. 6. The flexographic relief image printing element according to claim 1 wherein a dot relief of the printing element is greater than about 9% of the overall plate relief. 7. The flexographic relief image printing element according to claim 6, wherein the dot relief of the printing element is greater than about 12% of the overall plate relief. 8. A plurality of relief dots created in a relief image printing element, wherein the relief image printing element comprises, in order, a laser ablatable mask layer, at least one photopolymer layer, and a backing layer, wherein a plurality of dots in relief are created in the at least one photopolymer layer during a digital platemaking process, the digital platemaking process including the steps of (i) laser ablating a laser ablatable mask layer to create an in situ negative; (ii) selectively exposing the at least one photopolymer layer to actinic radiation through the in situ negative to selectively crosslink portions of the at least one photopolymer layer and (iii) separating and removing uncrosslinked portions of the at least one photopolymer layer, and
wherein said plurality of relief dots comprise at least one geometric characteristic selected from the group consisting of: (a) a planarity of a top surface of the relief dots, measured as the radius of curvature of the top surface of the dot, rt, is greater than the total thickness of the photopolymer layer; (b) a depth of relief between the relief dots, measured as a percentage of the overall plate relief, is greater than about 9%; and (c) an edge sharpness of the dots is such that the ratio of the radius of curvature at the intersection of the shoulder and the top surface of the dot, re, to the width of the top of the dot, p, is less than 5%; and wherein the plurality of printing dots exhibit a compound shoulder angle such that an angle nearest the top surface of the dot, θ1, is greater than 70° and an angle nearest a dot floor attachment, θ2, is less than 45°. 9. The plurality of relief dots according to claim 8, wherein said planarity of the top surface of the relief dots is such that the radius of curvature of the top surface of the dot, rt, is greater than the total thickness of the photopolymer layer. 10. (canceled) 11. (canceled) 12. (canceled) 13. The plurality of relief dots according to claim 8, wherein the depth of relief between the relief dots is greater than about 12% of the overall plate relief. 14. The plurality of relief dots according to claim 8 wherein the edge sharpness of the relief dots is such that the ratio of re:p is less than about 2 percent. 15. (canceled) 16. (canceled) 17. The flexographic relief image printing element according to claim 1, wherein an average surface roughness of the relief image printing element is less than about 100 nm. 18. The flexographic relief image printing element according to claim 1, wherein an average surface roughness of the relief image printing element is between about 700 and about 800 nm. 19. A plurality of relief dots created in a relief image printing element, wherein the relief image printing element (i) laser ablating the laser ablatable mask layer to create an in situ negative; (ii) laminating an oxygen barrier membrane to a top of the relief image printing element; (iii) selectively exposing the at least one photopolymer layer to actinic radiation through the in situ negative and the oxygen barrier membrane to selectively crosslink portions of the at least one photopolymer layer; and (iv) developing the relief image printing element to separate and remove uncrosslinked portions of the at least one photopolymer layer, and
wherein said plurality of relief dots comprise at least one geometric characteristic selected from the group consisting of: (a) a planarity of a top surface of the relief dots, measured as the radius of curvature of the top surface of the dot, rt, is greater than the total thickness of the photopolymer layer; (b) an edge sharpness of the dots is such that the ratio of the radius of curvature at the intersection of the shoulder and the top surface of the dot, re, to the width of the top of the dot, p, is less than 5%; and (c) a depth of relief between the relief dots, measured as a percentage of the overall plate relief, is greater than about 9%; and wherein the plurality of printing dots exhibit a compound shoulder angle such that an angle nearest the top surface of the dot, θ1, is greater than 70° and an angle nearest a dot floor attachment, θ2, is less than 45°. | 2,800 |
11,864 | 11,864 | 14,168,388 | 2,849 | An electronic apparatus is provided which includes switching elements, resonance suppression resistors which have first ends connected to control terminals of the switching elements and second ends having a common connection, an on-drive circuit which has an on-drive resistor and is connected to a drive power circuit, and which is supplied with voltage from the drive power circuit and applies electric charge to the control terminals of the switching elements via the on-drive resistor to turn on the switching elements, and an off-drive circuit which has an off-drive resistor and releases electric charge from the control terminals of the switching elements via the off-drive resistor to turn off the switching elements. A resistance of the off-drive resistor is set to be smaller than a resistance of the resonance suppression resistors. The off-drive circuit releases electric charge from the control terminals of the switching elements not via the resonance suppression resistors. | 1. An electronic apparatus, comprising:
a plurality of switching elements each of which has an input terminal, an output terminal and a control terminal, the input terminals having a common connection, and the output terminals having a common connection, and each of which is driven by controlling voltage at the control terminal; a plurality of resonance suppression resistors each of which has a first end and a second end, the first ends being connected to the respective control terminals of the switching elements, and the second ends having a common connection; an on-drive circuit which has at least one on-drive resistor and is connected to a drive power circuit, and which is supplied with voltage from the drive power circuit and applies electric charge to the control terminals of the switching elements via the on-drive resistor to turn on the switching elements; and an off-drive circuit which has an off-drive resistor and releases electric charge from the control terminals of the switching elements via the off-drive resistor to turn off the switching elements, wherein a resistance of the off-drive resistor is set to be smaller than a resistance of the resonance suppression resistors, and the off-drive circuit releases electric charge from the control terminals of the switching elements not via the resonance suppression resistors. 2. The electronic apparatus according to claim 1, further comprising a plurality of diodes each of which has an anode and a cathode, the anodes being connected to a switching elements side of the respective resonance suppression resistors, and the cathodes being connected to an opposite side of the switching elements side of the respective resonance suppression resistors, and
the off-drive circuit is connected to a common-connecting point of the resonance suppression resistors and releases electric charge from the control terminals of the switching elements via the diodes. 3. The electronic apparatus according to claim 1, further comprising a plurality of diodes each of which has an anode and a cathode, the anodes being connected to the respective control terminals of the switching elements, and the cathodes having a common connection, and
the off-drive circuit is connected to a common-connecting point of the diodes and releases electric charge from the control terminals of the switching elements via the diodes. 4. The electronic apparatus according to claim 3, further comprising a plurality of resistors connected in parallel with the diodes, respectively. 5. The electronic apparatus according to claim 4, wherein
the resistors have a resistance equal to or more than a resistance of the resonance suppression resistors. 6. The electronic apparatus according to claim 2, further comprising a control circuit which is connected to the diodes and controls the drive power circuit on the basis of forward voltage of the diodes to adjust output voltage of the drive power circuit. 7. The electronic apparatus according to claim 2, wherein
the off-drive circuit has the plural off-drive resistors having mutually different resistances, and the control circuit controls the off-drive circuit on the basis of forward voltage of the diodes to change resistances of the off-drive resistors. 8. The electronic apparatus according to claim 2, wherein
the control circuit controls the on-drive circuit on the basis of forward voltage of the diodes to adjust output voltage of the on-drive circuit. 9. The electronic apparatus according to claim 1, wherein
the off-drive circuit is connected to the control terminals of the switching elements and releases electric charge from the control terminals of the switching elements. 10. An electronic apparatus, comprising:
a plurality of switching elements each of which has an input terminal, an output terminal and a control terminal, the input terminals having a common connection, and the output terminals having a common connection, and each of which is driven by controlling voltage at the control terminal; a plurality of resonance suppression resistors each of which has a first end and a second end, the first ends being connected to the respective control terminals of the switching elements, and the second ends having a common connection; an on-drive circuit which has at least one on-drive resistor and is connected to a drive power circuit, and which is supplied with voltage from the drive power circuit and applies electric charge to the control terminals of the switching elements via the on-drive resistor to turn on the switching elements; and an off-drive circuit which has an off-drive resistor and releases electric charge from the control terminals of the switching elements via the off-drive resistor to turn off the switching elements, wherein a resistance of the on-drive resistor is set to be smaller than a resistance of the resonance suppression resistors, and the on-drive circuit applies electric charge to the control terminals of the switching elements not via the resonance suppression resistors. 11. The electronic apparatus according to claim 10, further comprising a plurality of diodes each of which has an anode and a cathode, the anodes being connected to an opposite side of a switching elements side of the respective resonance suppression resistors, and the cathodes being connected to the switching elements side of the respective resonance suppression resistors, and
the on-drive circuit is connected to a common-connecting point of the resonance suppression resistors and applies electric charge from the control terminals of the switching elements via the diodes. 12. The electronic apparatus according to claim 10, further comprising a plurality of diodes each of which has an anode and a cathode, the anodes having a common connection, and the cathodes being connected to the respective control terminals of the switching elements, and
the on-drive circuit is connected to a common-connecting point of the diodes and applies electric charge to the control terminals of the switching elements via the diodes. 13. The electronic apparatus according to claim 12, further comprising a plurality of resistors connected in parallel with the diodes, respectively. 14. The electronic apparatus according to claim 13, wherein
the resistors have a resistance equal to or more than a resistance of the resonance suppression resistors. 15. The electronic apparatus according to claim 11, further comprising a control circuit which is connected to the diodes and controls the drive power circuit on the basis of forward voltage of the diodes to adjust output voltage of the drive power circuit. 16. The electronic apparatus according to claim 11, wherein
the on-drive circuit has the plural on-drive resistors having mutually different resistances, and the control circuit controls the on-drive circuit on the basis of forward voltage of the diodes to change resistances of the on-drive resistors. 17. The electronic apparatus according to claim 11, wherein
the control circuit controls the on-drive circuit on the basis of forward voltage of the diodes to adjust output voltage of the on-drive circuit. 18. The electronic apparatus according to claim 10, wherein
the on-drive circuit is connected to the control terminals of the switching elements and applies electric charge to the control terminals of the switching elements. | An electronic apparatus is provided which includes switching elements, resonance suppression resistors which have first ends connected to control terminals of the switching elements and second ends having a common connection, an on-drive circuit which has an on-drive resistor and is connected to a drive power circuit, and which is supplied with voltage from the drive power circuit and applies electric charge to the control terminals of the switching elements via the on-drive resistor to turn on the switching elements, and an off-drive circuit which has an off-drive resistor and releases electric charge from the control terminals of the switching elements via the off-drive resistor to turn off the switching elements. A resistance of the off-drive resistor is set to be smaller than a resistance of the resonance suppression resistors. The off-drive circuit releases electric charge from the control terminals of the switching elements not via the resonance suppression resistors.1. An electronic apparatus, comprising:
a plurality of switching elements each of which has an input terminal, an output terminal and a control terminal, the input terminals having a common connection, and the output terminals having a common connection, and each of which is driven by controlling voltage at the control terminal; a plurality of resonance suppression resistors each of which has a first end and a second end, the first ends being connected to the respective control terminals of the switching elements, and the second ends having a common connection; an on-drive circuit which has at least one on-drive resistor and is connected to a drive power circuit, and which is supplied with voltage from the drive power circuit and applies electric charge to the control terminals of the switching elements via the on-drive resistor to turn on the switching elements; and an off-drive circuit which has an off-drive resistor and releases electric charge from the control terminals of the switching elements via the off-drive resistor to turn off the switching elements, wherein a resistance of the off-drive resistor is set to be smaller than a resistance of the resonance suppression resistors, and the off-drive circuit releases electric charge from the control terminals of the switching elements not via the resonance suppression resistors. 2. The electronic apparatus according to claim 1, further comprising a plurality of diodes each of which has an anode and a cathode, the anodes being connected to a switching elements side of the respective resonance suppression resistors, and the cathodes being connected to an opposite side of the switching elements side of the respective resonance suppression resistors, and
the off-drive circuit is connected to a common-connecting point of the resonance suppression resistors and releases electric charge from the control terminals of the switching elements via the diodes. 3. The electronic apparatus according to claim 1, further comprising a plurality of diodes each of which has an anode and a cathode, the anodes being connected to the respective control terminals of the switching elements, and the cathodes having a common connection, and
the off-drive circuit is connected to a common-connecting point of the diodes and releases electric charge from the control terminals of the switching elements via the diodes. 4. The electronic apparatus according to claim 3, further comprising a plurality of resistors connected in parallel with the diodes, respectively. 5. The electronic apparatus according to claim 4, wherein
the resistors have a resistance equal to or more than a resistance of the resonance suppression resistors. 6. The electronic apparatus according to claim 2, further comprising a control circuit which is connected to the diodes and controls the drive power circuit on the basis of forward voltage of the diodes to adjust output voltage of the drive power circuit. 7. The electronic apparatus according to claim 2, wherein
the off-drive circuit has the plural off-drive resistors having mutually different resistances, and the control circuit controls the off-drive circuit on the basis of forward voltage of the diodes to change resistances of the off-drive resistors. 8. The electronic apparatus according to claim 2, wherein
the control circuit controls the on-drive circuit on the basis of forward voltage of the diodes to adjust output voltage of the on-drive circuit. 9. The electronic apparatus according to claim 1, wherein
the off-drive circuit is connected to the control terminals of the switching elements and releases electric charge from the control terminals of the switching elements. 10. An electronic apparatus, comprising:
a plurality of switching elements each of which has an input terminal, an output terminal and a control terminal, the input terminals having a common connection, and the output terminals having a common connection, and each of which is driven by controlling voltage at the control terminal; a plurality of resonance suppression resistors each of which has a first end and a second end, the first ends being connected to the respective control terminals of the switching elements, and the second ends having a common connection; an on-drive circuit which has at least one on-drive resistor and is connected to a drive power circuit, and which is supplied with voltage from the drive power circuit and applies electric charge to the control terminals of the switching elements via the on-drive resistor to turn on the switching elements; and an off-drive circuit which has an off-drive resistor and releases electric charge from the control terminals of the switching elements via the off-drive resistor to turn off the switching elements, wherein a resistance of the on-drive resistor is set to be smaller than a resistance of the resonance suppression resistors, and the on-drive circuit applies electric charge to the control terminals of the switching elements not via the resonance suppression resistors. 11. The electronic apparatus according to claim 10, further comprising a plurality of diodes each of which has an anode and a cathode, the anodes being connected to an opposite side of a switching elements side of the respective resonance suppression resistors, and the cathodes being connected to the switching elements side of the respective resonance suppression resistors, and
the on-drive circuit is connected to a common-connecting point of the resonance suppression resistors and applies electric charge from the control terminals of the switching elements via the diodes. 12. The electronic apparatus according to claim 10, further comprising a plurality of diodes each of which has an anode and a cathode, the anodes having a common connection, and the cathodes being connected to the respective control terminals of the switching elements, and
the on-drive circuit is connected to a common-connecting point of the diodes and applies electric charge to the control terminals of the switching elements via the diodes. 13. The electronic apparatus according to claim 12, further comprising a plurality of resistors connected in parallel with the diodes, respectively. 14. The electronic apparatus according to claim 13, wherein
the resistors have a resistance equal to or more than a resistance of the resonance suppression resistors. 15. The electronic apparatus according to claim 11, further comprising a control circuit which is connected to the diodes and controls the drive power circuit on the basis of forward voltage of the diodes to adjust output voltage of the drive power circuit. 16. The electronic apparatus according to claim 11, wherein
the on-drive circuit has the plural on-drive resistors having mutually different resistances, and the control circuit controls the on-drive circuit on the basis of forward voltage of the diodes to change resistances of the on-drive resistors. 17. The electronic apparatus according to claim 11, wherein
the control circuit controls the on-drive circuit on the basis of forward voltage of the diodes to adjust output voltage of the on-drive circuit. 18. The electronic apparatus according to claim 10, wherein
the on-drive circuit is connected to the control terminals of the switching elements and applies electric charge to the control terminals of the switching elements. | 2,800 |
11,865 | 11,865 | 15,459,488 | 2,811 | A radio frequency (RF) switch includes a plurality of series-connected silicon-on-insulator (SOI) CMOS transistors fabricated in accordance with a semiconductor process having a first minimum line width (e.g., 0.18 microns). While the semiconductor process conventionally implements a polysilicon gate layer having a first thickness (e.g., 2000 Angstroms), each of the plurality of SOI CMOS transistors is fabricated with a polysilicon gate electrode having a second thickness, which is less than the first thickness. The reduced thickness of the polysilicon gate electrodes of the SOI CMOS transistors reduces the on-resistance and the off-capacitance of the associated RF switch. | 1. A radio frequency (RF) switch comprising:
a plurality of silicon-on-insulator (SOI) CMOS transistors, each including a polysilicon gate electrode having a first thickness and a first length, wherein the first length is at least about 0.18 microns and defines a length of a channel of the transistor, and wherein the first thickness is less than 1450 Angstroms. 2. The RF switch of claim 1, wherein the first thickness is about 1150 to 1350 Angstroms. 3. The RF switch of claim 1, wherein the first thickness is about 1250 Angstroms. 4. The RF switch of claim 1, further comprising a pre-metal dielectric layer formed over the plurality of SOI CMOS transistors, wherein the pre-metal dielectric layer has a thickness of about 4,000 to 10,000 Angstroms. 5. (canceled) 6. (canceled) 7. (canceled) 8. (canceled) 9. (canceled) 10. (canceled) 11. A radio frequency (RF) switch comprising:
a plurality of silicon-on-insulator (SOI) CMOS transistors fabricated in accordance with a semiconductor process having a first minimum line width, wherein the semiconductor process conventionally implements a polysilicon gate layer having a first thickness, wherein each of the plurality of SOI CMOS transistors is fabricated with polysilicon gate electrodes having a second thickness, less than the first thickness; and an interconnect structure that couples the plurality of SOI CMOS transistors in series to form the RF switch. 12. The RF switch of claim 11, wherein the second thickness is less than about 70 percent of the first thickness. 13. The RF switch of claim 11, wherein the first minimum line width is 0.18 microns, and the second thickness is less than 1450 Angstroms. 14. The RF switch of claim 13, wherein the first thickness is about 2000 Angstroms. 15. The RF switch of claim 13, wherein the second thickness is about 1150 to 1350 Angstroms. 16. The RF switch of claim 13, wherein the second thickness is about 1250 Angstroms. 17. The RF switch of claim 11, wherein conventional polysilicon gate electrodes fabricated in accordance with the semiconductor process have the first thickness and a first dopant concentration, and wherein the polysilicon gate electrodes having the second thickness have a second dopant concentration, greater than the first dopant concentration. | A radio frequency (RF) switch includes a plurality of series-connected silicon-on-insulator (SOI) CMOS transistors fabricated in accordance with a semiconductor process having a first minimum line width (e.g., 0.18 microns). While the semiconductor process conventionally implements a polysilicon gate layer having a first thickness (e.g., 2000 Angstroms), each of the plurality of SOI CMOS transistors is fabricated with a polysilicon gate electrode having a second thickness, which is less than the first thickness. The reduced thickness of the polysilicon gate electrodes of the SOI CMOS transistors reduces the on-resistance and the off-capacitance of the associated RF switch.1. A radio frequency (RF) switch comprising:
a plurality of silicon-on-insulator (SOI) CMOS transistors, each including a polysilicon gate electrode having a first thickness and a first length, wherein the first length is at least about 0.18 microns and defines a length of a channel of the transistor, and wherein the first thickness is less than 1450 Angstroms. 2. The RF switch of claim 1, wherein the first thickness is about 1150 to 1350 Angstroms. 3. The RF switch of claim 1, wherein the first thickness is about 1250 Angstroms. 4. The RF switch of claim 1, further comprising a pre-metal dielectric layer formed over the plurality of SOI CMOS transistors, wherein the pre-metal dielectric layer has a thickness of about 4,000 to 10,000 Angstroms. 5. (canceled) 6. (canceled) 7. (canceled) 8. (canceled) 9. (canceled) 10. (canceled) 11. A radio frequency (RF) switch comprising:
a plurality of silicon-on-insulator (SOI) CMOS transistors fabricated in accordance with a semiconductor process having a first minimum line width, wherein the semiconductor process conventionally implements a polysilicon gate layer having a first thickness, wherein each of the plurality of SOI CMOS transistors is fabricated with polysilicon gate electrodes having a second thickness, less than the first thickness; and an interconnect structure that couples the plurality of SOI CMOS transistors in series to form the RF switch. 12. The RF switch of claim 11, wherein the second thickness is less than about 70 percent of the first thickness. 13. The RF switch of claim 11, wherein the first minimum line width is 0.18 microns, and the second thickness is less than 1450 Angstroms. 14. The RF switch of claim 13, wherein the first thickness is about 2000 Angstroms. 15. The RF switch of claim 13, wherein the second thickness is about 1150 to 1350 Angstroms. 16. The RF switch of claim 13, wherein the second thickness is about 1250 Angstroms. 17. The RF switch of claim 11, wherein conventional polysilicon gate electrodes fabricated in accordance with the semiconductor process have the first thickness and a first dopant concentration, and wherein the polysilicon gate electrodes having the second thickness have a second dopant concentration, greater than the first dopant concentration. | 2,800 |
11,866 | 11,866 | 16,142,791 | 2,835 | A cooling system is provided for power conversion circuitry. An intake section of a cooling air channeling element is arranged to direct cooling air through an enclosure, and through or around system components to circuit board-mounted circuitry to be cooled. The element has internal structures, such as deflectors that create local pockets of lower velocity and/or higher pressure air to trap airborne particles that can be evacuated through apertures (e.g., in adjacent plates or mounting structures). The intake section leads to a distribution section that is positioned adjacent to the circuit components to be cooled. The element may have an open bottom that cooperates with surrounding structures to channel the cooling air, facilitating molding of a single-piece element that can be easily mounted during system assembly. | 1. A circuit cooling system comprising:
a plate-like mounting surface; a cooling air directing element mounted on the plate-like mounting surface and having an intake section and a distribution section, the intake section positioned to channel an air stream to the distribution section, the distribution section positioned adjacent to power circuitry for cooling the power circuitry with the channeled air stream, the intake section having a plurality of air deflectors creating local pockets of elevated pressure in the channeled air stream; and the plate-like mounting surface having apertures adjacent to the air deflectors that, in operation, allow airborne particulate to drop from the channeled air stream. 2. The system of claim 1, wherein the cooling air directing element comprises a single-piece molded element. 3. The system of claim 1, wherein the cooling air directing element comprises an open side that traps the channeled air stream between the cooling air directing element and the plate-like mounting surface. 4. The system of claim 3, wherein the plate-like mounting surface comprises a circuit housing element. 5. The system of claim 1, wherein the cooling air directing element comprises an intake side diverting surface that extends into a path of forced cooling air to divert a portion of the cooling air into the intake section. 6. The system of claim 1, wherein at least a portion of the intake section comprises a textured interior surface that, in operation, perturbs flow of the cooling air stream. 7. The system of claim 1, wherein at least one of the air deflectors comprises a wall extension having a shape that is concave in a direction opposite the channeled air stream. 8. The system of claim 1, wherein at least two air deflectors extend from alternate sides of the intake section. 9. The system of claim 1, wherein at least one of the intake section and distribution section comprises a side flange facilitating mounting of the cooling air directing element to the plate-like mounting surface. 10. A circuit cooling system comprising:
power conversion circuitry mounted on a printed circuit board in an enclosure having a plate-like mounting surface; a cooling air directing element mounted on the plate-like mounting surface and having an intake section and a distribution section, the intake section positioned to channel an air stream from an intake side of the enclosure to the distribution section, the distribution section positioned at least partially over and surrounding the power conversion circuitry for cooling the power conversion circuitry with the channeled air stream, the intake section having a plurality of air deflectors creating local pockets of elevated pressure in the channeled air stream; and the plate-like mounting surface having apertures adjacent to the air deflectors that, in operation, allow airborne particulate to drop from the channeled air stream. 11. The system of claim 10, wherein the cooling air directing element comprises an open side that traps the channeled air stream between the cooling air directing element and a portion of the enclosure. 12. The system of claim 10, wherein the plate-like mounting surface comprises at least a portion of the enclosure adjacent to the intake side. 13. The system of claim 10, comprising a fan that, in operation, forces cooling air into the enclosure, and wherein the cooling air directing element comprises an intake side diverting surface that extends into a path of forced cooling air from the fan to divert a portion of the cooling air into the intake section. 14. The system of claim 10, wherein at least one of the air deflectors comprises a wall extension having a shape that is concave in a direction opposite the channeled air stream. 15. The system of claim 10, wherein at least two air deflectors extend from alternate sides of the intake section. 16. The system of claim 10, wherein at least one of the intake section and distribution section comprises a side flange facilitating mounting of the cooling air directing element to the plate-like mounting surface. 17. A method of making a circuit cooling system comprising:
mounting printed circuit board power conversion circuitry in an enclosure having a plate-like mounting surface; mounting a cooling air directing element in the enclosure on the plate-like mounting surface, the cooling air directing element having an intake section and a distribution section, the intake section positioned to channel an air stream from an intake side of the enclosure to the distribution section, the distribution section positioned at least partially over and surrounding the power conversion circuitry for cooling the power conversion circuitry with the channeled air stream, the intake section having a plurality of air deflectors creating local pockets of elevated pressure in the channeled air stream; and the plate-like mounting surface having apertures adjacent to the air deflectors that, in operation, allow airborne particulate to drop from the channeled air stream. 18. The method of claim 17, wherein the cooling air directing element comprises an open side that traps the channeled air stream between the cooling air directing element and a portion of the enclosure. 19. The method of claim 17, wherein at least one of the air deflectors comprises a wall extension having a shape that is concave in a direction opposite the channeled air stream, and wherein at least two air deflectors extend from alternate sides of the intake section. 20. The method of claim 17, wherein mounting the cooling air directing element in the enclosure comprises positioning an intake side diverting surface of the intake section into a path of forced cooling air from a fan mounted in the enclosure to divert a portion of the cooling air into the intake section. | A cooling system is provided for power conversion circuitry. An intake section of a cooling air channeling element is arranged to direct cooling air through an enclosure, and through or around system components to circuit board-mounted circuitry to be cooled. The element has internal structures, such as deflectors that create local pockets of lower velocity and/or higher pressure air to trap airborne particles that can be evacuated through apertures (e.g., in adjacent plates or mounting structures). The intake section leads to a distribution section that is positioned adjacent to the circuit components to be cooled. The element may have an open bottom that cooperates with surrounding structures to channel the cooling air, facilitating molding of a single-piece element that can be easily mounted during system assembly.1. A circuit cooling system comprising:
a plate-like mounting surface; a cooling air directing element mounted on the plate-like mounting surface and having an intake section and a distribution section, the intake section positioned to channel an air stream to the distribution section, the distribution section positioned adjacent to power circuitry for cooling the power circuitry with the channeled air stream, the intake section having a plurality of air deflectors creating local pockets of elevated pressure in the channeled air stream; and the plate-like mounting surface having apertures adjacent to the air deflectors that, in operation, allow airborne particulate to drop from the channeled air stream. 2. The system of claim 1, wherein the cooling air directing element comprises a single-piece molded element. 3. The system of claim 1, wherein the cooling air directing element comprises an open side that traps the channeled air stream between the cooling air directing element and the plate-like mounting surface. 4. The system of claim 3, wherein the plate-like mounting surface comprises a circuit housing element. 5. The system of claim 1, wherein the cooling air directing element comprises an intake side diverting surface that extends into a path of forced cooling air to divert a portion of the cooling air into the intake section. 6. The system of claim 1, wherein at least a portion of the intake section comprises a textured interior surface that, in operation, perturbs flow of the cooling air stream. 7. The system of claim 1, wherein at least one of the air deflectors comprises a wall extension having a shape that is concave in a direction opposite the channeled air stream. 8. The system of claim 1, wherein at least two air deflectors extend from alternate sides of the intake section. 9. The system of claim 1, wherein at least one of the intake section and distribution section comprises a side flange facilitating mounting of the cooling air directing element to the plate-like mounting surface. 10. A circuit cooling system comprising:
power conversion circuitry mounted on a printed circuit board in an enclosure having a plate-like mounting surface; a cooling air directing element mounted on the plate-like mounting surface and having an intake section and a distribution section, the intake section positioned to channel an air stream from an intake side of the enclosure to the distribution section, the distribution section positioned at least partially over and surrounding the power conversion circuitry for cooling the power conversion circuitry with the channeled air stream, the intake section having a plurality of air deflectors creating local pockets of elevated pressure in the channeled air stream; and the plate-like mounting surface having apertures adjacent to the air deflectors that, in operation, allow airborne particulate to drop from the channeled air stream. 11. The system of claim 10, wherein the cooling air directing element comprises an open side that traps the channeled air stream between the cooling air directing element and a portion of the enclosure. 12. The system of claim 10, wherein the plate-like mounting surface comprises at least a portion of the enclosure adjacent to the intake side. 13. The system of claim 10, comprising a fan that, in operation, forces cooling air into the enclosure, and wherein the cooling air directing element comprises an intake side diverting surface that extends into a path of forced cooling air from the fan to divert a portion of the cooling air into the intake section. 14. The system of claim 10, wherein at least one of the air deflectors comprises a wall extension having a shape that is concave in a direction opposite the channeled air stream. 15. The system of claim 10, wherein at least two air deflectors extend from alternate sides of the intake section. 16. The system of claim 10, wherein at least one of the intake section and distribution section comprises a side flange facilitating mounting of the cooling air directing element to the plate-like mounting surface. 17. A method of making a circuit cooling system comprising:
mounting printed circuit board power conversion circuitry in an enclosure having a plate-like mounting surface; mounting a cooling air directing element in the enclosure on the plate-like mounting surface, the cooling air directing element having an intake section and a distribution section, the intake section positioned to channel an air stream from an intake side of the enclosure to the distribution section, the distribution section positioned at least partially over and surrounding the power conversion circuitry for cooling the power conversion circuitry with the channeled air stream, the intake section having a plurality of air deflectors creating local pockets of elevated pressure in the channeled air stream; and the plate-like mounting surface having apertures adjacent to the air deflectors that, in operation, allow airborne particulate to drop from the channeled air stream. 18. The method of claim 17, wherein the cooling air directing element comprises an open side that traps the channeled air stream between the cooling air directing element and a portion of the enclosure. 19. The method of claim 17, wherein at least one of the air deflectors comprises a wall extension having a shape that is concave in a direction opposite the channeled air stream, and wherein at least two air deflectors extend from alternate sides of the intake section. 20. The method of claim 17, wherein mounting the cooling air directing element in the enclosure comprises positioning an intake side diverting surface of the intake section into a path of forced cooling air from a fan mounted in the enclosure to divert a portion of the cooling air into the intake section. | 2,800 |
11,867 | 11,867 | 15,261,722 | 2,837 | An elevator brake assembly including an asymmetrical brake comprising at least three brake segments, a brake activating device operably coupled to the asymmetrical brake, the brake activating device comprising a first activation element and a second activation element, wherein the first activation element is configured to activate one of the at least three brake segments, and the second activation element is configured to activate the remaining of the at least three brake segments. | 1. An elevator brake assembly comprising:
an asymmetrical brake comprising at least three brake segments; and a brake activating device operably coupled to the asymmetrical brake, the brake activating device comprising a first activation element and a second activation element; wherein the first activation element is configured to activate one of the at least three brake segments, and the second activation element is configured to activate the remaining of the at least three brake segments. 2. The elevator brake assembly of claim 1, wherein the at least three brake segments are located adjacent to one another and circumferentially disposed around a plate. 3. The elevator brake assembly of claim 1, wherein the at least three brake segments comprises a first brake segment and a second brake segment circumferentially disposed around a third brake segment. 4. The elevator brake assembly of claim 1, wherein the at least three brake segments comprise a first brake segment positioned adjacent to a second brake segment; the first activation element is positioned adjacent to the first brake segment and the second brake segment, a third brake segment positioned adjacent to the first activation element, and the second activation element is positioned adjacent to the third brake segment. 5. The elevator brake assembly of claim 1, the at least three brake segments further comprising a plurality of brake applying portions, wherein a respective one of the plurality of brake applying portions is disposed on each of the at least three brake segments. 6. The elevator brake assembly of claim 5, wherein the plurality of brake applying portions comprises a plurality of shoes. 7. The elevator brake assembly of claim 1, wherein the first activation element comprises a first coil and the second activation element comprises a second coil. 8. An elevator system comprising:
a machine housing; a rotatable output shaft mounted in said machine housing; a sheave mounted on said output shaft and rotatable therewith; and a brake assembly configured for braking said output shaft, the brake assembly comprising:
an asymmetrical brake comprising at least three brake segments; and
a brake activating device operably coupled to the asymmetrical brake, the brake activating device comprising a first activation element and a second activation element;
wherein the first activation element is configured to activate one of the at least three brake segments, and the second activation element is configured to activate the remaining of the at least three brake segments. 9. The elevator system of claim 8, wherein the asymmetrical brake comprises at least three brake segments located adjacent to one another and circumferentially disposed around a plate. 10. The elevator system of claim 8, wherein the asymmetrical brake comprises a first brake segment and a second brake segment circumferentially disposed around a third brake segment. 11. The elevator system of claim 8, wherein the asymmetrical brake comprises a first brake segment positioned adjacent to a second brake segment; the first activation element is positioned adjacent to the first brake segment and the second brake segment, a third brake segment positioned adjacent to the first activation element, and the second activation element is positioned adjacent to the third brake segment 12. The elevator system of claim 8, wherein the asymmetrical brake further comprises a plurality of brake applying portions, wherein a respective one of the plurality of brake applying portions is disposed on each of the at least three brake segments. 13. The elevator system of claim 12, wherein the plurality of brake applying portions comprises a plurality of shoes. 14. The elevator system of claim 8, wherein the first activation element comprises a first coil and the second activation element comprises a second coil. | An elevator brake assembly including an asymmetrical brake comprising at least three brake segments, a brake activating device operably coupled to the asymmetrical brake, the brake activating device comprising a first activation element and a second activation element, wherein the first activation element is configured to activate one of the at least three brake segments, and the second activation element is configured to activate the remaining of the at least three brake segments.1. An elevator brake assembly comprising:
an asymmetrical brake comprising at least three brake segments; and a brake activating device operably coupled to the asymmetrical brake, the brake activating device comprising a first activation element and a second activation element; wherein the first activation element is configured to activate one of the at least three brake segments, and the second activation element is configured to activate the remaining of the at least three brake segments. 2. The elevator brake assembly of claim 1, wherein the at least three brake segments are located adjacent to one another and circumferentially disposed around a plate. 3. The elevator brake assembly of claim 1, wherein the at least three brake segments comprises a first brake segment and a second brake segment circumferentially disposed around a third brake segment. 4. The elevator brake assembly of claim 1, wherein the at least three brake segments comprise a first brake segment positioned adjacent to a second brake segment; the first activation element is positioned adjacent to the first brake segment and the second brake segment, a third brake segment positioned adjacent to the first activation element, and the second activation element is positioned adjacent to the third brake segment. 5. The elevator brake assembly of claim 1, the at least three brake segments further comprising a plurality of brake applying portions, wherein a respective one of the plurality of brake applying portions is disposed on each of the at least three brake segments. 6. The elevator brake assembly of claim 5, wherein the plurality of brake applying portions comprises a plurality of shoes. 7. The elevator brake assembly of claim 1, wherein the first activation element comprises a first coil and the second activation element comprises a second coil. 8. An elevator system comprising:
a machine housing; a rotatable output shaft mounted in said machine housing; a sheave mounted on said output shaft and rotatable therewith; and a brake assembly configured for braking said output shaft, the brake assembly comprising:
an asymmetrical brake comprising at least three brake segments; and
a brake activating device operably coupled to the asymmetrical brake, the brake activating device comprising a first activation element and a second activation element;
wherein the first activation element is configured to activate one of the at least three brake segments, and the second activation element is configured to activate the remaining of the at least three brake segments. 9. The elevator system of claim 8, wherein the asymmetrical brake comprises at least three brake segments located adjacent to one another and circumferentially disposed around a plate. 10. The elevator system of claim 8, wherein the asymmetrical brake comprises a first brake segment and a second brake segment circumferentially disposed around a third brake segment. 11. The elevator system of claim 8, wherein the asymmetrical brake comprises a first brake segment positioned adjacent to a second brake segment; the first activation element is positioned adjacent to the first brake segment and the second brake segment, a third brake segment positioned adjacent to the first activation element, and the second activation element is positioned adjacent to the third brake segment 12. The elevator system of claim 8, wherein the asymmetrical brake further comprises a plurality of brake applying portions, wherein a respective one of the plurality of brake applying portions is disposed on each of the at least three brake segments. 13. The elevator system of claim 12, wherein the plurality of brake applying portions comprises a plurality of shoes. 14. The elevator system of claim 8, wherein the first activation element comprises a first coil and the second activation element comprises a second coil. | 2,800 |
11,868 | 11,868 | 11,693,049 | 2,887 | A hand-held-transceiver identifier device includes a processor device contained in a housing. A port is contained in the housing to receive a transceiver. A display is contained in the housing. Upon insertion of the transceiver in the port, the device interrogates the transceiver to obtain specification information. A computer-implemented method of identifying a transceiver device detects an insertion of the transceiver device, interrogates the transceiver device to obtain specification information, and detects a removal of the transceiver device. | 1. A hand held transceiver identifier device, comprising:
a processor device contained in a housing; a port contained in the housing to receive a transceiver; and a display contained in the housing, wherein, upon insertion of the transceiver in the port, the device interrogates the transceiver to obtain specification information. 2. The device of claim 1, wherein the display includes a liquid crystal display (LCD) display. 3. The device of claim 1, wherein the port is compatible with a gigabit interface converter (GBIC), a small form factor pluggable (SFP), or an XFP standard. 4. The device of claim 1, further including a database module operating on the processor device, wherein the device cross references the specification information obtained from the transceiver with stored data maintained in the database. 5. The device of claim 4, wherein the database module auto-populates a database field shown on the display with the stored data. 6. The device of claim 1, wherein the specification information includes vendor, part number, serial number, supported speed, wavelength, and supported maximum distance. 7. The device of claim 1, further including a selection button integrated into a surface of the housing to perform a menu selection function. 8. A computer-implemented method of identifying a transceiver device, comprising:
detecting an insertion of the transceiver device; interrogating the transceiver device to obtain specification information; and detecting a removal of the transceiver device. 9. The method of claim 8, further initiating a power-on function upon insertion of the transceiver device. 10. The method of claim 8, further including displaying the specification information. 11. The method of claim 8, further including cross referencing the specification information with stored data maintained in a database. 12. The method of claim 11, further including auto-populating a database field with information obtained from the stored data. 13. The method of claim 8, wherein the transceiver device is compatible with a gigabit interface converter (GBIC), a small form factor pluggable (SFP), or an XFP standard. 14. A method of manufacturing a hand held transceiver identifier device, comprising:
providing a processor device contained in a housing; providing a port contained in the housing to receive a transceiver; and providing a display contained in the housing, wherein, upon insertion of the transceiver in the port, the device interrogates the transceiver to obtain specification information. 15. The method of claim 14, wherein the display includes a liquid crystal display (LCD) display. 16. The method of claim 14, wherein the port is compatible with a gigabit interface converter (GBIC), a small form factor pluggable (SFP), or an XFP standard. 17. The method of claim 14, further including a database module operating on the processor device, wherein the device cross references the specification information obtained from the transceiver with stored data maintained in the database. 18. The method of claim 17, wherein the database module auto-populates a database field shown on the display with the stored data. 19. The method of claim 14, wherein the specification information includes vendor, part number, serial number, supported speed, wavelength, and supported maximum distance. 20. The method of claim 14, further including the step of providing a selection button integrated into a surface of the housing to perform a menu selection function. | A hand-held-transceiver identifier device includes a processor device contained in a housing. A port is contained in the housing to receive a transceiver. A display is contained in the housing. Upon insertion of the transceiver in the port, the device interrogates the transceiver to obtain specification information. A computer-implemented method of identifying a transceiver device detects an insertion of the transceiver device, interrogates the transceiver device to obtain specification information, and detects a removal of the transceiver device.1. A hand held transceiver identifier device, comprising:
a processor device contained in a housing; a port contained in the housing to receive a transceiver; and a display contained in the housing, wherein, upon insertion of the transceiver in the port, the device interrogates the transceiver to obtain specification information. 2. The device of claim 1, wherein the display includes a liquid crystal display (LCD) display. 3. The device of claim 1, wherein the port is compatible with a gigabit interface converter (GBIC), a small form factor pluggable (SFP), or an XFP standard. 4. The device of claim 1, further including a database module operating on the processor device, wherein the device cross references the specification information obtained from the transceiver with stored data maintained in the database. 5. The device of claim 4, wherein the database module auto-populates a database field shown on the display with the stored data. 6. The device of claim 1, wherein the specification information includes vendor, part number, serial number, supported speed, wavelength, and supported maximum distance. 7. The device of claim 1, further including a selection button integrated into a surface of the housing to perform a menu selection function. 8. A computer-implemented method of identifying a transceiver device, comprising:
detecting an insertion of the transceiver device; interrogating the transceiver device to obtain specification information; and detecting a removal of the transceiver device. 9. The method of claim 8, further initiating a power-on function upon insertion of the transceiver device. 10. The method of claim 8, further including displaying the specification information. 11. The method of claim 8, further including cross referencing the specification information with stored data maintained in a database. 12. The method of claim 11, further including auto-populating a database field with information obtained from the stored data. 13. The method of claim 8, wherein the transceiver device is compatible with a gigabit interface converter (GBIC), a small form factor pluggable (SFP), or an XFP standard. 14. A method of manufacturing a hand held transceiver identifier device, comprising:
providing a processor device contained in a housing; providing a port contained in the housing to receive a transceiver; and providing a display contained in the housing, wherein, upon insertion of the transceiver in the port, the device interrogates the transceiver to obtain specification information. 15. The method of claim 14, wherein the display includes a liquid crystal display (LCD) display. 16. The method of claim 14, wherein the port is compatible with a gigabit interface converter (GBIC), a small form factor pluggable (SFP), or an XFP standard. 17. The method of claim 14, further including a database module operating on the processor device, wherein the device cross references the specification information obtained from the transceiver with stored data maintained in the database. 18. The method of claim 17, wherein the database module auto-populates a database field shown on the display with the stored data. 19. The method of claim 14, wherein the specification information includes vendor, part number, serial number, supported speed, wavelength, and supported maximum distance. 20. The method of claim 14, further including the step of providing a selection button integrated into a surface of the housing to perform a menu selection function. | 2,800 |
11,869 | 11,869 | 14,859,682 | 2,859 | A method according to an exemplary aspect of the present disclosure includes, among other things, controlling charging of a battery pack of an electrified vehicle including prioritizing charging using a wired charging system over a wireless charging system if power is available from both the wired charging system and the wireless charging system. | 1. A method, comprising:
controlling charging of a battery pack of an electrified vehicle including prioritizing charging using a wired charging system over a wireless charging system if power is available from both the wired charging system and the wireless charging system. 2. The method as recited in claim 1, comprising inhibiting the charging if the electrified vehicle is not in park. 3. The method as recited in claim 1, comprising inhibiting the charging if a parking brake is not applied. 4. The method as recited in claim 1, comprising inhibiting the charging if the electrified vehicle is not in park and a parking brake is not applied. 5. The method as recited in claim 1, comprising switching to wireless charging using the wireless charging system if power from the wired charging system becomes unavailable. 6. The method as recited in claim 1, comprising:
determining whether the electrified vehicle is in PARK; determining whether a parking brake of the electrified vehicle is applied; and inhibiting the charging if the electrified vehicle is not in PARK and the parking brake is not applied. 7. The method as recited in claim 1, wherein the controlling step includes determining whether the wired charging system is available for charging the battery pack. 8. The method as recited in claim 7, comprising charging the battery pack using the wireless charging system if the wired charging system is unavailable. 9. The method as recited in claim 1, wherein the controlling step includes determining whether the wireless charging system is available for charging the battery pack. 10. The method as recited in claim 1, comprising ending the charging if power is unavailable from either the wired charging system or the wireless charging system. 11. The method as recited in claim 1, wherein the controlling step includes determining whether a power cord of the wired charging system is plugged in. 12. The method as recited in claim 1, wherein the controlling step includes determining whether wall power is available for powering the wired charging system. 13. The method as recited in claim 12, comprising:
charging the battery pack using the wired charging system if the wall power is available; or determining whether power is available from the wireless charging system if the wall power is not available. 14. The method as recited in claim 13, charging the battery pack using power from the wireless charging system if the wireless charging system is available. 15. The method as recited in claim 1, comprising permitting the charging only when a mechanical restraint of the electrified vehicle is actuated. 16. A vehicle system, comprising:
a battery pack; a wireless charging system configured to selectively charge said battery pack; a wired charging system configured to selectively charge said battery pack; and a control system configured to prioritize charging of said battery pack using said wired charging system over said wireless charging system when both are available. 17. The vehicle system as recited in claim 16, wherein said wireless charging system is an inductive charging system that includes a transmitter device and a receiver device. 18. The vehicle system as recited in claim 16, wherein said control system includes at least one control module configured to execute a control strategy for charging said battery pack. 19. The vehicle system as recited in claim 16, wherein said wired charging system includes a charging port and a power cord configured to connect between said charging port and a wall receptacle of an external power source. 20. The vehicle system as recited in claim 16, wherein said control system is configured to command charging using said wireless charging system if said wired charging system becomes unavailable. | A method according to an exemplary aspect of the present disclosure includes, among other things, controlling charging of a battery pack of an electrified vehicle including prioritizing charging using a wired charging system over a wireless charging system if power is available from both the wired charging system and the wireless charging system.1. A method, comprising:
controlling charging of a battery pack of an electrified vehicle including prioritizing charging using a wired charging system over a wireless charging system if power is available from both the wired charging system and the wireless charging system. 2. The method as recited in claim 1, comprising inhibiting the charging if the electrified vehicle is not in park. 3. The method as recited in claim 1, comprising inhibiting the charging if a parking brake is not applied. 4. The method as recited in claim 1, comprising inhibiting the charging if the electrified vehicle is not in park and a parking brake is not applied. 5. The method as recited in claim 1, comprising switching to wireless charging using the wireless charging system if power from the wired charging system becomes unavailable. 6. The method as recited in claim 1, comprising:
determining whether the electrified vehicle is in PARK; determining whether a parking brake of the electrified vehicle is applied; and inhibiting the charging if the electrified vehicle is not in PARK and the parking brake is not applied. 7. The method as recited in claim 1, wherein the controlling step includes determining whether the wired charging system is available for charging the battery pack. 8. The method as recited in claim 7, comprising charging the battery pack using the wireless charging system if the wired charging system is unavailable. 9. The method as recited in claim 1, wherein the controlling step includes determining whether the wireless charging system is available for charging the battery pack. 10. The method as recited in claim 1, comprising ending the charging if power is unavailable from either the wired charging system or the wireless charging system. 11. The method as recited in claim 1, wherein the controlling step includes determining whether a power cord of the wired charging system is plugged in. 12. The method as recited in claim 1, wherein the controlling step includes determining whether wall power is available for powering the wired charging system. 13. The method as recited in claim 12, comprising:
charging the battery pack using the wired charging system if the wall power is available; or determining whether power is available from the wireless charging system if the wall power is not available. 14. The method as recited in claim 13, charging the battery pack using power from the wireless charging system if the wireless charging system is available. 15. The method as recited in claim 1, comprising permitting the charging only when a mechanical restraint of the electrified vehicle is actuated. 16. A vehicle system, comprising:
a battery pack; a wireless charging system configured to selectively charge said battery pack; a wired charging system configured to selectively charge said battery pack; and a control system configured to prioritize charging of said battery pack using said wired charging system over said wireless charging system when both are available. 17. The vehicle system as recited in claim 16, wherein said wireless charging system is an inductive charging system that includes a transmitter device and a receiver device. 18. The vehicle system as recited in claim 16, wherein said control system includes at least one control module configured to execute a control strategy for charging said battery pack. 19. The vehicle system as recited in claim 16, wherein said wired charging system includes a charging port and a power cord configured to connect between said charging port and a wall receptacle of an external power source. 20. The vehicle system as recited in claim 16, wherein said control system is configured to command charging using said wireless charging system if said wired charging system becomes unavailable. | 2,800 |
11,870 | 11,870 | 15,338,202 | 2,838 | An apparatus including a substrate, a power conversion circuit coupled to the substrate, a power prong coupled to the power conversion circuit, a device connector to couple to a device, and a device connector cable to couple the device connector to the power conversion circuit is disclosed. | 1. An apparatus comprising:
a substrate having a substrate surface, a substrate thickness, and an edge, the substrate surface including a power prong recess, and the substrate thickness being between about three-tenths of a millimeter and about five millimeters; a power conversion circuit including an alternating current port and a direct current port, the power conversion circuit coupled to the substrate, and the power conversion circuit having a power conversion circuit thickness less than the substrate thickness; a power prong coupled to the alternating current port, the power prong when folded into the power prong recess oriented substantially parallel to the substrate surface and when unfolded oriented substantially perpendicular to the substrate surface; a device connector to couple to a device; and a device connector cable to couple the device connector to the direct current port and to fit into a device connector cable recess. 2. The apparatus of claim 2, wherein the substrate surface has a substantially quadrilateral perimeter including two internal angles of about 90 degrees each, one internal angle of less than about 90 degrees and one internal angle of more than about 90 degrees. 3. The apparatus of claim 1, wherein the device connector cable recess includes a ferromagnetic material and the device connector cable includes one or more magnets to couple the device connector cable to the device connector cable recess. 4. The apparatus of claim 1, wherein the power conversion circuit has a power factor of at least about 0.8. 5. The apparatus of claim 4, wherein the power prong recess includes a finger recess to assist in unfolding the power prong. 6. The apparatus of claim 1, further comprising a rotatable mount coupled to the surface, the rotatable mount to receive the power prong. 7. The apparatus of claim 1, further comprising a spring and a sliding wedge, the spring to hold the power prong in a substantially horizontal position with respect to the surface while the power prong rests in the power prong recess and the sliding wedge to substantially lock the power prong in a vertical position with respect to the surface. 8. The apparatus of claim 1, further comprising a sliding member coupled to the surface and a gear coupled to the power prong, the sliding member including a plurality of teeth and grooves, the teeth to engage the gear to enable movement of the power prong between a substantially horizontal position with respect to the substrate surface and a substantially vertical position with respect to the substrate surface. 9. The apparatus of claim 1, further comprising a tracker coupled to the substrate. 10. An apparatus comprising:
a circuit board; a power conversion circuit mounted on the circuit board, the power conversion circuit including an alternating current input port, a toroid, an alternating current rectifier, a plurality of capacitors, a power circuit, a transformer, a direct current output port, and a feedback controller, the transformer coupled to the direct current output port and the direct current output port to provide a substantially stable voltage, the power conversion circuit having a power factor of at least about 0.8 and the power conversion circuit to operate using a high frequency switching signal, the toroid to couple the alternating current input port to the alternating current rectifier, and the plurality of capacitors to couple the alternating current rectifier to the power circuit, and the transformer to couple the power circuit to the direct current output port, and the feedback controller to couple the direct current output port and the transformer to the power circuit, each of the plurality of capacitors having a capacitor height of less than about 2.8 millimeters. 11. The apparatus of claim 10, further comprising a toroid mounting board mounted on the circuit board and the toroid mounting board having a hole with the toroid mounted in the hole. 12. The apparatus of claim 10, wherein the high frequency switching signal has a frequency of about one megahertz. 13. The apparatus of claim 11, wherein the transformer has a transformer height of between about 1.0 millimeter and about 3.2 millimeters. 14. An apparatus comprising:
a substrate having a substrate surface, a substrate thickness, and an edge, the substrate surface including a power prong recess, and the substrate thickness being between about three-tenths of a millimeter and about five millimeters; a circuit board; a power conversion circuit mounted on the circuit board, the power conversion circuit including an alternating current input port, an alternating current rectifier, a power circuit, a transformer, a feedback controller, and a direct current output port, the transformer coupled to the direct current port and the direct current output port to provide a substantially stable voltage, the power conversion circuit having a power factor of at least about 0.8 and the power conversion circuit to operate using a high frequency switching signal; a toroid to couple the alternating current input port to the alternating current rectifier; a plurality of capacitors to couple the alternating current rectifier to the power circuit, the transformer to couple the power circuit to the direct current output port, and a feedback controller to couple the direct current output port and the transformer to the power circuit, each of the plurality of capacitors having a height of less than about 2.8 millimeters; a power prong coupled to the alternating current port, the power prong when folded into the power prong recess oriented substantially parallel to the surface and when unfolded oriented substantially perpendicular to the surface; a device connector to couple to a device; and a device connector cable to couple the device connector to the direct current port and to fit into a device connector cable recess. 15. The apparatus of claim 14, wherein the substrate has a length of about 85.60 millimeters and a width of about 53.98 millimeters. 16. The apparatus of claim 14, wherein the substrate surface has a substantially quadrilateral shape including two internal angles of about 90 degrees each, a first internal angle of less than about 90 degrees and a second internal angle of more than about 90 degrees. 17. The apparatus of claim 16, the power conversion circuit to receive a signal of between about 120 volts and 240 volts and to provide a signal of about five volts and about two amperes. 18. The apparatus of claim 15, wherein the printed circuit board has a substantially quadrilateral printed circuit board shape including two internal angles of about 90 degrees each, a first internal angle of less than about 90 degrees and a second internal angle of more than about 90 degrees. 19. The apparatus of claim 14, wherein the edge includes the device connector cable recess including a clamp. 20. The apparatus of claim 14, wherein the edge includes a plurality of edge mounted cable connectors. | An apparatus including a substrate, a power conversion circuit coupled to the substrate, a power prong coupled to the power conversion circuit, a device connector to couple to a device, and a device connector cable to couple the device connector to the power conversion circuit is disclosed.1. An apparatus comprising:
a substrate having a substrate surface, a substrate thickness, and an edge, the substrate surface including a power prong recess, and the substrate thickness being between about three-tenths of a millimeter and about five millimeters; a power conversion circuit including an alternating current port and a direct current port, the power conversion circuit coupled to the substrate, and the power conversion circuit having a power conversion circuit thickness less than the substrate thickness; a power prong coupled to the alternating current port, the power prong when folded into the power prong recess oriented substantially parallel to the substrate surface and when unfolded oriented substantially perpendicular to the substrate surface; a device connector to couple to a device; and a device connector cable to couple the device connector to the direct current port and to fit into a device connector cable recess. 2. The apparatus of claim 2, wherein the substrate surface has a substantially quadrilateral perimeter including two internal angles of about 90 degrees each, one internal angle of less than about 90 degrees and one internal angle of more than about 90 degrees. 3. The apparatus of claim 1, wherein the device connector cable recess includes a ferromagnetic material and the device connector cable includes one or more magnets to couple the device connector cable to the device connector cable recess. 4. The apparatus of claim 1, wherein the power conversion circuit has a power factor of at least about 0.8. 5. The apparatus of claim 4, wherein the power prong recess includes a finger recess to assist in unfolding the power prong. 6. The apparatus of claim 1, further comprising a rotatable mount coupled to the surface, the rotatable mount to receive the power prong. 7. The apparatus of claim 1, further comprising a spring and a sliding wedge, the spring to hold the power prong in a substantially horizontal position with respect to the surface while the power prong rests in the power prong recess and the sliding wedge to substantially lock the power prong in a vertical position with respect to the surface. 8. The apparatus of claim 1, further comprising a sliding member coupled to the surface and a gear coupled to the power prong, the sliding member including a plurality of teeth and grooves, the teeth to engage the gear to enable movement of the power prong between a substantially horizontal position with respect to the substrate surface and a substantially vertical position with respect to the substrate surface. 9. The apparatus of claim 1, further comprising a tracker coupled to the substrate. 10. An apparatus comprising:
a circuit board; a power conversion circuit mounted on the circuit board, the power conversion circuit including an alternating current input port, a toroid, an alternating current rectifier, a plurality of capacitors, a power circuit, a transformer, a direct current output port, and a feedback controller, the transformer coupled to the direct current output port and the direct current output port to provide a substantially stable voltage, the power conversion circuit having a power factor of at least about 0.8 and the power conversion circuit to operate using a high frequency switching signal, the toroid to couple the alternating current input port to the alternating current rectifier, and the plurality of capacitors to couple the alternating current rectifier to the power circuit, and the transformer to couple the power circuit to the direct current output port, and the feedback controller to couple the direct current output port and the transformer to the power circuit, each of the plurality of capacitors having a capacitor height of less than about 2.8 millimeters. 11. The apparatus of claim 10, further comprising a toroid mounting board mounted on the circuit board and the toroid mounting board having a hole with the toroid mounted in the hole. 12. The apparatus of claim 10, wherein the high frequency switching signal has a frequency of about one megahertz. 13. The apparatus of claim 11, wherein the transformer has a transformer height of between about 1.0 millimeter and about 3.2 millimeters. 14. An apparatus comprising:
a substrate having a substrate surface, a substrate thickness, and an edge, the substrate surface including a power prong recess, and the substrate thickness being between about three-tenths of a millimeter and about five millimeters; a circuit board; a power conversion circuit mounted on the circuit board, the power conversion circuit including an alternating current input port, an alternating current rectifier, a power circuit, a transformer, a feedback controller, and a direct current output port, the transformer coupled to the direct current port and the direct current output port to provide a substantially stable voltage, the power conversion circuit having a power factor of at least about 0.8 and the power conversion circuit to operate using a high frequency switching signal; a toroid to couple the alternating current input port to the alternating current rectifier; a plurality of capacitors to couple the alternating current rectifier to the power circuit, the transformer to couple the power circuit to the direct current output port, and a feedback controller to couple the direct current output port and the transformer to the power circuit, each of the plurality of capacitors having a height of less than about 2.8 millimeters; a power prong coupled to the alternating current port, the power prong when folded into the power prong recess oriented substantially parallel to the surface and when unfolded oriented substantially perpendicular to the surface; a device connector to couple to a device; and a device connector cable to couple the device connector to the direct current port and to fit into a device connector cable recess. 15. The apparatus of claim 14, wherein the substrate has a length of about 85.60 millimeters and a width of about 53.98 millimeters. 16. The apparatus of claim 14, wherein the substrate surface has a substantially quadrilateral shape including two internal angles of about 90 degrees each, a first internal angle of less than about 90 degrees and a second internal angle of more than about 90 degrees. 17. The apparatus of claim 16, the power conversion circuit to receive a signal of between about 120 volts and 240 volts and to provide a signal of about five volts and about two amperes. 18. The apparatus of claim 15, wherein the printed circuit board has a substantially quadrilateral printed circuit board shape including two internal angles of about 90 degrees each, a first internal angle of less than about 90 degrees and a second internal angle of more than about 90 degrees. 19. The apparatus of claim 14, wherein the edge includes the device connector cable recess including a clamp. 20. The apparatus of claim 14, wherein the edge includes a plurality of edge mounted cable connectors. | 2,800 |
11,871 | 11,871 | 15,214,625 | 2,862 | A composition formula of each precursor ion located on a measured mass spectrum is estimated from the m/z value of the precursor ion (S 11 ). A composition formula of each product ion located on a measured MS/MS spectrum is estimated from the m/z value of the product ion (S 11 ). For each product-ion peak, the assignment of the peak is determined by verifying consistency between the composition formula of the product ion and the composition formula of each of the precursor ions (S 13 -S 14 ). Based on the assignment result, the MS/MS spectrum data are separated and an MS/MS spectrum for each precursor ion is created (S 15 -S 16 ). In this manner, MS/MS spectra which respectively correspond to a plurality of compounds can be created from an MS/MS spectrum in which the product ions originating from those compounds are mixed, and those compounds can be identified. | 1. A tandem mass spectrometry data processing system for processing MSn spectrum data obtained by performing a mass spectrometry for product ions obtained by dissociating ions collectively selected as precursor ions, the precursor ions originating from a plurality of different compounds and having mass-to-charge ratios within a predetermined mass-to-charge-ratio width, the system comprising:
a) a product ion assignment determiner for determining, for each product ion, which precursor ion among the plurality of precursor ions is an origin of the product ion, by verifying consistency between a composition formula estimated from a mass-to-charge ratio of the product ion and each of composition formulae estimated from the mass-to-charge ratios of the precursor ions, or by determining a similarity between a mass defect which is a portion after a decimal point of a mass-to-charge-ratio value of the product ion and a mass defect which is a portion after a decimal point of a mass-to-charge-ratio value of each precursor ion; and b) a data separator for reconstructing MSn spectrum data of product ions for each of the precursor ions, based on a result of a determination by the product ion assignment determiner. 2. The tandem mass spectrometry data processing system according to claim 1, further comprising:
a precursor ion composition formula estimator for obtaining mass-to-charge-ratio values of a plurality of ions selected as the precursor ions from MSn-1 spectrum data obtained by an actual measurement, and for estimating the composition formula of each of the ions from those mass-to-charge-ratio values; and a product ion composition formula estimator for obtaining mass-to-charge-ratio values of the detected product ions from MSn spectrum data obtained by an actual measurement, and for estimating the composition formula of each of the product ions from those mass-to-charge-ratio values,
wherein:
the product ion assignment determiner determines, for each product ion, which precursor ion among the plurality of precursor ions is the origin of the product ion, by verifying the consistency between the composition formula estimated by the product ion composition formula estimator and each of the composition formulae of the precursor ions estimated by the precursor ion composition formula estimator. 3. The tandem mass spectrometry data processing system according to claim 1, further comprising:
a precursor ion mass defect extractor for obtaining the mass-to-charge-ratio values of a plurality of ions selected as the precursor ions from MSn-1 spectrum data obtained by an actual measurement, and for extracting, as the mass defect, the portion after the decimal point of each of the mass-to-charge-ratio values; and a product ion mass defect extractor for obtaining the mass-to-charge-ratio values of the detected product ions from MSn spectrum data obtained by an actual measurement, and for extracting, as the mass defect, the portion after the decimal point of each of the mass-to-charge-ratio values,
wherein:
the product ion assignment determiner determines, for each product ion, which precursor ion among the plurality of precursor ions is the origin of the product ion, by determining the similarity between the mass defect extracted by the product ion mass defect extractor and each of the mass defects of the precursor ions extracted by the precursor ion mass defect extractor. | A composition formula of each precursor ion located on a measured mass spectrum is estimated from the m/z value of the precursor ion (S 11 ). A composition formula of each product ion located on a measured MS/MS spectrum is estimated from the m/z value of the product ion (S 11 ). For each product-ion peak, the assignment of the peak is determined by verifying consistency between the composition formula of the product ion and the composition formula of each of the precursor ions (S 13 -S 14 ). Based on the assignment result, the MS/MS spectrum data are separated and an MS/MS spectrum for each precursor ion is created (S 15 -S 16 ). In this manner, MS/MS spectra which respectively correspond to a plurality of compounds can be created from an MS/MS spectrum in which the product ions originating from those compounds are mixed, and those compounds can be identified.1. A tandem mass spectrometry data processing system for processing MSn spectrum data obtained by performing a mass spectrometry for product ions obtained by dissociating ions collectively selected as precursor ions, the precursor ions originating from a plurality of different compounds and having mass-to-charge ratios within a predetermined mass-to-charge-ratio width, the system comprising:
a) a product ion assignment determiner for determining, for each product ion, which precursor ion among the plurality of precursor ions is an origin of the product ion, by verifying consistency between a composition formula estimated from a mass-to-charge ratio of the product ion and each of composition formulae estimated from the mass-to-charge ratios of the precursor ions, or by determining a similarity between a mass defect which is a portion after a decimal point of a mass-to-charge-ratio value of the product ion and a mass defect which is a portion after a decimal point of a mass-to-charge-ratio value of each precursor ion; and b) a data separator for reconstructing MSn spectrum data of product ions for each of the precursor ions, based on a result of a determination by the product ion assignment determiner. 2. The tandem mass spectrometry data processing system according to claim 1, further comprising:
a precursor ion composition formula estimator for obtaining mass-to-charge-ratio values of a plurality of ions selected as the precursor ions from MSn-1 spectrum data obtained by an actual measurement, and for estimating the composition formula of each of the ions from those mass-to-charge-ratio values; and a product ion composition formula estimator for obtaining mass-to-charge-ratio values of the detected product ions from MSn spectrum data obtained by an actual measurement, and for estimating the composition formula of each of the product ions from those mass-to-charge-ratio values,
wherein:
the product ion assignment determiner determines, for each product ion, which precursor ion among the plurality of precursor ions is the origin of the product ion, by verifying the consistency between the composition formula estimated by the product ion composition formula estimator and each of the composition formulae of the precursor ions estimated by the precursor ion composition formula estimator. 3. The tandem mass spectrometry data processing system according to claim 1, further comprising:
a precursor ion mass defect extractor for obtaining the mass-to-charge-ratio values of a plurality of ions selected as the precursor ions from MSn-1 spectrum data obtained by an actual measurement, and for extracting, as the mass defect, the portion after the decimal point of each of the mass-to-charge-ratio values; and a product ion mass defect extractor for obtaining the mass-to-charge-ratio values of the detected product ions from MSn spectrum data obtained by an actual measurement, and for extracting, as the mass defect, the portion after the decimal point of each of the mass-to-charge-ratio values,
wherein:
the product ion assignment determiner determines, for each product ion, which precursor ion among the plurality of precursor ions is the origin of the product ion, by determining the similarity between the mass defect extracted by the product ion mass defect extractor and each of the mass defects of the precursor ions extracted by the precursor ion mass defect extractor. | 2,800 |
11,872 | 11,872 | 15,866,385 | 2,848 | A capacitor arrangement is disclosed. In an embodiment the arrangement includes a ceramic multilayer capacitor including a main body comprising ceramic layers, first electrode layers and second electrode layers arranged there between and a first external contact and a second external contact on mutually opposite side surfaces, wherein the first external contact is electrically conductively connected to the first electrode layers and the second external contact is electrically conductively connected to the second electrode layers. | 1. A capacitor arrangement comprising:
a ceramic multilayer capacitor comprising:
a main body comprising ceramic layers, first electrode layers and second electrode layers arranged there between; and
a first external contact and a second external contact on mutually opposite side surfaces,
wherein the first external contact is electrically conductively connected to the first electrode layers and the second external contact is electrically conductively connected to the second electrode layers,
wherein the main body has third electrode layers between the ceramic layers, the third electrode layers being electrically conductively connected to no external contact and overlapping with the first and second electrode layers,
wherein each layer of the first, second and third electrode layers comprises a base metal,
wherein the ceramic layers comprise an antiferroelectric dielectric material,
wherein the ceramic layers are arranged along a layer stacking direction to form a stack,
wherein the main body has a width B along a layer stacking direction,
wherein the main body has a height H along a direction perpendicular to side surfaces on which the first and second external contacts are located,
wherein the main body has a length L along a direction perpendicular to the height H and perpendicular to the width B, and
wherein B/H≥1, L/B≥1 and L/H≥1. 2. The capacitor arrangement according to claim 1, wherein the first, second and third electrode layers consist essentially of copper. 3. The capacitor arrangement according to claim 1, wherein the side surfaces on which the first and second external contacts are located are lapped or ground. 4. The capacitor arrangement according to claim 1, further comprising
a first metallic contact plate electrically conductively connected to the first external contact; and a second metallic contact plate electrically conductively connected to the second external contact, and wherein the ceramic multilayer capacitor is arranged between the first metallic contact plate and the second metallic contact plate. 5. The capacitor arrangement according to claim 4, wherein the first metallic contact plate and the second metallic contact plate comprise copper plates or copper plates passivated with gold or silver. 6. The capacitor arrangement according to claim 4, further comprising:
a first metallic grid arranged between the first external contact and the first metallic contact plate; and a second metallic grid is arranged between the second external contact and the second metallic contact plate. 7. The capacitor arrangement according to claim 6, wherein the first metallic grid and the second metallic grid is a copper grid. 8. The capacitor arrangement according to claim 4, further comprising:
a first solder layer arranged between the first external contact and the first metallic contact plate; and a second solder layer arranged between the second external contact and the second metallic contact plate. 9. The capacitor arrangement according to claim 8, wherein each of the first and second solder layers comprises a nanosilver solder layer. 10. The capacitor arrangement according to claim 4, wherein a plurality of ceramic multilayer capacitors are arranged between the first and second metallic contact plates. 11. The capacitor arrangement according to claim 1, wherein each of the first and second external contacts has a sputtering layer comprising a Cr/Cu/Au layer sequence, a Cr/Cu/Ag layer sequence, a Cr/Ni/Au layer sequence or Cr/Ni/Ag layer sequence, and wherein each sputtering layer is in direct contact with a first electrode layer or a second electrode layer. 12. The capacitor arrangement according to claim 1, wherein the ceramic layers comprise a ceramic material according to the following formula:
Pb(1-1.5a-0.5b+1.5d+e+0.5f)AaBb(Zr1-xTix)1-c-d-e-fLidCeFefSicO3 +yPbO,
wherein
A comprises an element selected from the group consisting of La, Nd, Y, Eu, Gd, Tb, Dy, Ho, Er and Yb;
B comprises an element selected from the group consisting of Na, K and Ag;
C comprises an element selected from the group consisting of Ni, Cu, Co and Mn; and
0<a<0.12, 0.05≤x≤0.3, 0≤b≤0.12, 0≤c≤0.12, 0≤d<0.12, 0≤e<0.12, 0≤f<0.12, 0≤y<1 and b+d+e+f>0. 13. The capacitor arrangement according to claim 1, wherein the main body has at least ten ceramic layers. | A capacitor arrangement is disclosed. In an embodiment the arrangement includes a ceramic multilayer capacitor including a main body comprising ceramic layers, first electrode layers and second electrode layers arranged there between and a first external contact and a second external contact on mutually opposite side surfaces, wherein the first external contact is electrically conductively connected to the first electrode layers and the second external contact is electrically conductively connected to the second electrode layers.1. A capacitor arrangement comprising:
a ceramic multilayer capacitor comprising:
a main body comprising ceramic layers, first electrode layers and second electrode layers arranged there between; and
a first external contact and a second external contact on mutually opposite side surfaces,
wherein the first external contact is electrically conductively connected to the first electrode layers and the second external contact is electrically conductively connected to the second electrode layers,
wherein the main body has third electrode layers between the ceramic layers, the third electrode layers being electrically conductively connected to no external contact and overlapping with the first and second electrode layers,
wherein each layer of the first, second and third electrode layers comprises a base metal,
wherein the ceramic layers comprise an antiferroelectric dielectric material,
wherein the ceramic layers are arranged along a layer stacking direction to form a stack,
wherein the main body has a width B along a layer stacking direction,
wherein the main body has a height H along a direction perpendicular to side surfaces on which the first and second external contacts are located,
wherein the main body has a length L along a direction perpendicular to the height H and perpendicular to the width B, and
wherein B/H≥1, L/B≥1 and L/H≥1. 2. The capacitor arrangement according to claim 1, wherein the first, second and third electrode layers consist essentially of copper. 3. The capacitor arrangement according to claim 1, wherein the side surfaces on which the first and second external contacts are located are lapped or ground. 4. The capacitor arrangement according to claim 1, further comprising
a first metallic contact plate electrically conductively connected to the first external contact; and a second metallic contact plate electrically conductively connected to the second external contact, and wherein the ceramic multilayer capacitor is arranged between the first metallic contact plate and the second metallic contact plate. 5. The capacitor arrangement according to claim 4, wherein the first metallic contact plate and the second metallic contact plate comprise copper plates or copper plates passivated with gold or silver. 6. The capacitor arrangement according to claim 4, further comprising:
a first metallic grid arranged between the first external contact and the first metallic contact plate; and a second metallic grid is arranged between the second external contact and the second metallic contact plate. 7. The capacitor arrangement according to claim 6, wherein the first metallic grid and the second metallic grid is a copper grid. 8. The capacitor arrangement according to claim 4, further comprising:
a first solder layer arranged between the first external contact and the first metallic contact plate; and a second solder layer arranged between the second external contact and the second metallic contact plate. 9. The capacitor arrangement according to claim 8, wherein each of the first and second solder layers comprises a nanosilver solder layer. 10. The capacitor arrangement according to claim 4, wherein a plurality of ceramic multilayer capacitors are arranged between the first and second metallic contact plates. 11. The capacitor arrangement according to claim 1, wherein each of the first and second external contacts has a sputtering layer comprising a Cr/Cu/Au layer sequence, a Cr/Cu/Ag layer sequence, a Cr/Ni/Au layer sequence or Cr/Ni/Ag layer sequence, and wherein each sputtering layer is in direct contact with a first electrode layer or a second electrode layer. 12. The capacitor arrangement according to claim 1, wherein the ceramic layers comprise a ceramic material according to the following formula:
Pb(1-1.5a-0.5b+1.5d+e+0.5f)AaBb(Zr1-xTix)1-c-d-e-fLidCeFefSicO3 +yPbO,
wherein
A comprises an element selected from the group consisting of La, Nd, Y, Eu, Gd, Tb, Dy, Ho, Er and Yb;
B comprises an element selected from the group consisting of Na, K and Ag;
C comprises an element selected from the group consisting of Ni, Cu, Co and Mn; and
0<a<0.12, 0.05≤x≤0.3, 0≤b≤0.12, 0≤c≤0.12, 0≤d<0.12, 0≤e<0.12, 0≤f<0.12, 0≤y<1 and b+d+e+f>0. 13. The capacitor arrangement according to claim 1, wherein the main body has at least ten ceramic layers. | 2,800 |
11,873 | 11,873 | 14,318,549 | 2,877 | A system including an optical waveguide having a length extending from an optical interrogator at a first end, a plurality of light-modulating sensor nodes disposed at predetermined locations along the length of the optical waveguide, and (in some embodiments) a plurality of first beam splitters at each of the predetermined locations along the length of the optical waveguide, each of the first beam splitters configured to direct a portion of an optical signal from the optical interrogator to one of the plurality of light-modulating sensor nodes along an optical waveguide path, and return a reflected optical signal to the optical interrogator in an opposite direction along the same optical waveguide path. | 1. A system comprising:
an optical waveguide having a length extending from an optical interrogator at a first end; a plurality of light-modulating sensor nodes disposed at predetermined locations along the length of the optical waveguide; and a plurality of first beam splitters at predetermined locations along the length of the optical waveguide, each of the first beam splitters configured to direct a portion of an optical signal from the optical interrogator to one of the plurality of light-modulating sensor nodes along an optical waveguide path, and return a reflected optical signal to the optical interrogator in an opposite direction along the same optical waveguide path. 2. The system of claim 1, wherein the optical interrogator comprises an optical pulse generator configured to generate the optical signal, wherein the optical signal is an optical pulse. 3. The system of claim 2, wherein the optical pulse is adapted to interrogate each of the plurality of light-modulating sensor nodes. 4. The system of claim 2, wherein each of the plurality of light-modulating sensor nodes further comprises a transducer, the transducer being configured to detect a signal selected from the group consisting of: acoustic, vibration, magnetic, and chemical. 5. The system of claim 4, wherein each of the plurality of light-modulating sensor nodes comprises an optical modulator configured to modulate the optical pulse in response to the transducer detecting the acoustic signal. 6. The system of claim 5, wherein each of the plurality of light-modulating sensor nodes further comprises:
a first reflector; a second reflector; and a second beam splitter between the first beam splitter and the optical modulator, the second beam splitter configured to direct a portion of the optical pulse to the optical modulator and the first reflector, and to direct another portion of the optical pulse to the second reflector, the first reflector configured to reflect the modulated optical pulse back toward the optical interrogator via the first beam splitter. 7. The system of claim 6, wherein the second reflector is configured to reflect the another portion of the optical pulse toward the optical interrogator. 8. The system of claim 5, wherein the optical modulator is in-line with the optical waveguide. 9. The system of claim 5, wherein the optical modulator is an actuator configured to optically modulate the optical pulse by changing physical properties of the optical waveguide from outside of the optical waveguide. 10. The system of claim 9, wherein the actuator is configured to vibrate or squeeze the optical waveguide. 11. The system of claim 5, wherein each of the plurality of light-modulating sensor nodes further comprises:
a reflector; and a semi-transparent reflector between the first beam splitter and the optical modulator, the semi-transparent reflector configured to transmit a portion of the optical pulse to the optical modulator and the reflector, and reflect another portion of the optical pulse to the optical interrogator via the first beam splitter. 12. The system of claim 1, wherein the optical interrogator further comprises an optical receiver configured to receive the reflected optical signal from each of the plurality of light-modulating sensor nodes. 13. The system of claim 12, wherein the receiver is configured to identify the light-modulating sensor node from the plurality of light-modulating sensor nodes from which the received optical signal is reflected. 14. A sensing method comprising:
sending an optical signal along an optical waveguide from an optical interrogator at a first end of the optical waveguide to a plurality of light-modulating sensor nodes disposed at predetermined locations along the optical waveguide; modulating the optical signal at the plurality of light-modulating sensor nodes in response to detecting a signal by a transducer in the plurality of light-modulating sensor nodes; and transmitting the modulated optical signal from the plurality of light-modulating sensor nodes to the optical interrogator along the same optical waveguide. 15. The method of claim 14, wherein the sending of the optical signal comprises directing, by a first beam splitter, a first portion of the optical signal from the optical waveguide to each of the plurality of light-modulating sensor nodes. 16. The method of claim 14, wherein the optical signal is an optical pulse, the optical pulse interrogating the plurality of light-modulating sensor nodes. 17. The method of claim 16, further comprising:
directing, by a second beam splitter, a portion of the first portion of the optical signal to a first reflector; directing, by the second beam splitter, a remainder of the first portion of the optical signal to a second reflector; and reflecting the remainder of the first portion of the optical signal to the optical interrogator by the second reflector, wherein the reflected remainder of the first portion is unmodulated. 18. The method of claim 17, further comprising removing distortion from the modulated optical signal by performing a differential readout between the reflected modulated optical signal and the reflected unmodulated optical signal. 19. The method of claim 16, further comprising:
directing the portion of the first portion of the optical signal to a first reflector through a semi-transparent reflector; and reflecting, by the semi-transparent reflector, the remainder of the first portion of the optical signal to the optical interrogator, wherein the remainder of the first portion is unmodulated. 20. The method of claim 19, further comprising removing distortion from the modulated optical signal by performing a differential readout between the reflected modulated optical signal and the reflected unmodulated optical signal. | A system including an optical waveguide having a length extending from an optical interrogator at a first end, a plurality of light-modulating sensor nodes disposed at predetermined locations along the length of the optical waveguide, and (in some embodiments) a plurality of first beam splitters at each of the predetermined locations along the length of the optical waveguide, each of the first beam splitters configured to direct a portion of an optical signal from the optical interrogator to one of the plurality of light-modulating sensor nodes along an optical waveguide path, and return a reflected optical signal to the optical interrogator in an opposite direction along the same optical waveguide path.1. A system comprising:
an optical waveguide having a length extending from an optical interrogator at a first end; a plurality of light-modulating sensor nodes disposed at predetermined locations along the length of the optical waveguide; and a plurality of first beam splitters at predetermined locations along the length of the optical waveguide, each of the first beam splitters configured to direct a portion of an optical signal from the optical interrogator to one of the plurality of light-modulating sensor nodes along an optical waveguide path, and return a reflected optical signal to the optical interrogator in an opposite direction along the same optical waveguide path. 2. The system of claim 1, wherein the optical interrogator comprises an optical pulse generator configured to generate the optical signal, wherein the optical signal is an optical pulse. 3. The system of claim 2, wherein the optical pulse is adapted to interrogate each of the plurality of light-modulating sensor nodes. 4. The system of claim 2, wherein each of the plurality of light-modulating sensor nodes further comprises a transducer, the transducer being configured to detect a signal selected from the group consisting of: acoustic, vibration, magnetic, and chemical. 5. The system of claim 4, wherein each of the plurality of light-modulating sensor nodes comprises an optical modulator configured to modulate the optical pulse in response to the transducer detecting the acoustic signal. 6. The system of claim 5, wherein each of the plurality of light-modulating sensor nodes further comprises:
a first reflector; a second reflector; and a second beam splitter between the first beam splitter and the optical modulator, the second beam splitter configured to direct a portion of the optical pulse to the optical modulator and the first reflector, and to direct another portion of the optical pulse to the second reflector, the first reflector configured to reflect the modulated optical pulse back toward the optical interrogator via the first beam splitter. 7. The system of claim 6, wherein the second reflector is configured to reflect the another portion of the optical pulse toward the optical interrogator. 8. The system of claim 5, wherein the optical modulator is in-line with the optical waveguide. 9. The system of claim 5, wherein the optical modulator is an actuator configured to optically modulate the optical pulse by changing physical properties of the optical waveguide from outside of the optical waveguide. 10. The system of claim 9, wherein the actuator is configured to vibrate or squeeze the optical waveguide. 11. The system of claim 5, wherein each of the plurality of light-modulating sensor nodes further comprises:
a reflector; and a semi-transparent reflector between the first beam splitter and the optical modulator, the semi-transparent reflector configured to transmit a portion of the optical pulse to the optical modulator and the reflector, and reflect another portion of the optical pulse to the optical interrogator via the first beam splitter. 12. The system of claim 1, wherein the optical interrogator further comprises an optical receiver configured to receive the reflected optical signal from each of the plurality of light-modulating sensor nodes. 13. The system of claim 12, wherein the receiver is configured to identify the light-modulating sensor node from the plurality of light-modulating sensor nodes from which the received optical signal is reflected. 14. A sensing method comprising:
sending an optical signal along an optical waveguide from an optical interrogator at a first end of the optical waveguide to a plurality of light-modulating sensor nodes disposed at predetermined locations along the optical waveguide; modulating the optical signal at the plurality of light-modulating sensor nodes in response to detecting a signal by a transducer in the plurality of light-modulating sensor nodes; and transmitting the modulated optical signal from the plurality of light-modulating sensor nodes to the optical interrogator along the same optical waveguide. 15. The method of claim 14, wherein the sending of the optical signal comprises directing, by a first beam splitter, a first portion of the optical signal from the optical waveguide to each of the plurality of light-modulating sensor nodes. 16. The method of claim 14, wherein the optical signal is an optical pulse, the optical pulse interrogating the plurality of light-modulating sensor nodes. 17. The method of claim 16, further comprising:
directing, by a second beam splitter, a portion of the first portion of the optical signal to a first reflector; directing, by the second beam splitter, a remainder of the first portion of the optical signal to a second reflector; and reflecting the remainder of the first portion of the optical signal to the optical interrogator by the second reflector, wherein the reflected remainder of the first portion is unmodulated. 18. The method of claim 17, further comprising removing distortion from the modulated optical signal by performing a differential readout between the reflected modulated optical signal and the reflected unmodulated optical signal. 19. The method of claim 16, further comprising:
directing the portion of the first portion of the optical signal to a first reflector through a semi-transparent reflector; and reflecting, by the semi-transparent reflector, the remainder of the first portion of the optical signal to the optical interrogator, wherein the remainder of the first portion is unmodulated. 20. The method of claim 19, further comprising removing distortion from the modulated optical signal by performing a differential readout between the reflected modulated optical signal and the reflected unmodulated optical signal. | 2,800 |
11,874 | 11,874 | 15,104,802 | 2,832 | An interconnector having circular conductors for a stator of a polyphase rotary electric machine including a body having a winding provided with a plurality of coils each having input and output ends, the interconnector comprising a first portion including at least three circular conductors having an annular shape stacked axially on top of one another and electrically isolated from one another, and a second portion including at least one electrically insulated circular conductor having an annular shape. The first and second portions are intended for being installed on either side of the body of the stator. The circular conductors of the first portion and the circular conductors of the second portion have, on the inner periphery thereof, tabs projecting inwardly for welding the input ends and the output ends of the coils, respectively. | 1. Interconnector with conductors (31-34) with an annular form for a stator of a polyphase rotary electrical machine comprising a stator (11) body (12) which supports a winding provided with a plurality of coils (19), each of which has input (191) and output (192) ends, wherein it comprises a first part (22 a) comprising at least three conductors (32-34) with an annular form stacked axially on one another and insulated electrically against one another, and a second part (22 b) comprising at least one conductor (31) with an annular form which is insulated electrically, said first and second parts being designed to be implanted on both sides of the stator body (12), and in that the conductors (32-34) with an annular form of the first part (22 a) and the conductor (31) with an annular form of the second part (22 b) support on their inner periphery lugs (36) which extend projecting towards the interior, for welding respectively of the input ends (191) and output ends (192) of the coils. 2. Interconnector according to claim 1, wherein the conductor (31) of the second part (22 b) is a neutral conductor for electrical coupling of the coils (19) in star form. 3. Interconnector according to claim 1, wherein the second part (22 b) of the interconnector comprises two neutral conductors for electrical coupling in parallel of two windings of the coils in star form. 4. Interconnector according to claim 1, wherein the first part (22 a) of the interconnector comprises more than three conductors. 5. Interconnector according to claim 1, wherein the second part (22 b) of the interconnector has a number of conductors which is equal to that of the first part (22 a) of the interconnector for electrical coupling of the coils in star form. 6. Interconnector according to claim 1, wherein the first part (22 a) of the interconnector has support feet in the form of an “L” which are designed to be supported on a rim of a head (17) which belongs to the body (12) of the stator. 7. Interconnector according to claim 6, wherein the second part (22 b) of the interconnector has support feet in the form of an “L” which are designed to be supported on the other rim of a head (17) which belongs to the body (12) of the stator. 8. Interconnector according to claim 1, wherein it is secured on at least one coil insulator. 9. Interconnector according to claim 8, wherein it is secured on at least three insulators. 10. Interconnector according to claim 8, wherein it comprises at least one clip which cooperates with an opening provided in a rear rim of the insulator. 11. Interconnector according to claim 1, wherein the coils are coupled in the form of a triangle. 12. Stator (11) of a rotary electrical machine comprising a stator (11) body (12), supporting a winding provided with a plurality of coils (19) which each have input (191) and output (192) ends, wherein said ends (191, 192) are connected to an interconnector (22 a, 22 b) according to claim 1. 13. Stator according to claim 12, wherein the input (191) and output (192) ends of the coils (19) are implanted respectively at one and the other of the axial ends of the coils. 14. Stator according to claim 12, wherein the ends (191, 192) of the coils are implanted on both sides of the body (12) of the stator. 15. Stator according to claim 12, wherein the ends (191, 192) of the coils (19) are implanted on a circumference which is at least equal to that of the inner periphery of the body (12) of the stator. 16. Interconnector according to claim 2, wherein the first part (22 a) of the interconnector comprises more than three conductors. 17. Interconnector according to claim 3, wherein the first part (22 a) of the interconnector comprises more than three conductors. 18. Interconnector according to claim 2, wherein the second part (22 b) of the interconnector has a number of conductors which is equal to that of the first part (22 a) of the interconnector for electrical coupling of the coils in star form. 19. Interconnector according to claim 3, wherein the second part (22 b) of the interconnector has a number of conductors which is equal to that of the first part (22 a) of the interconnector for electrical coupling of the coils in star form. 20. Interconnector according to claim 4, wherein the second part (22 b) of the interconnector has a number of conductors which is equal to that of the first part (22 a) of the interconnector for electrical coupling of the coils in star form. | An interconnector having circular conductors for a stator of a polyphase rotary electric machine including a body having a winding provided with a plurality of coils each having input and output ends, the interconnector comprising a first portion including at least three circular conductors having an annular shape stacked axially on top of one another and electrically isolated from one another, and a second portion including at least one electrically insulated circular conductor having an annular shape. The first and second portions are intended for being installed on either side of the body of the stator. The circular conductors of the first portion and the circular conductors of the second portion have, on the inner periphery thereof, tabs projecting inwardly for welding the input ends and the output ends of the coils, respectively.1. Interconnector with conductors (31-34) with an annular form for a stator of a polyphase rotary electrical machine comprising a stator (11) body (12) which supports a winding provided with a plurality of coils (19), each of which has input (191) and output (192) ends, wherein it comprises a first part (22 a) comprising at least three conductors (32-34) with an annular form stacked axially on one another and insulated electrically against one another, and a second part (22 b) comprising at least one conductor (31) with an annular form which is insulated electrically, said first and second parts being designed to be implanted on both sides of the stator body (12), and in that the conductors (32-34) with an annular form of the first part (22 a) and the conductor (31) with an annular form of the second part (22 b) support on their inner periphery lugs (36) which extend projecting towards the interior, for welding respectively of the input ends (191) and output ends (192) of the coils. 2. Interconnector according to claim 1, wherein the conductor (31) of the second part (22 b) is a neutral conductor for electrical coupling of the coils (19) in star form. 3. Interconnector according to claim 1, wherein the second part (22 b) of the interconnector comprises two neutral conductors for electrical coupling in parallel of two windings of the coils in star form. 4. Interconnector according to claim 1, wherein the first part (22 a) of the interconnector comprises more than three conductors. 5. Interconnector according to claim 1, wherein the second part (22 b) of the interconnector has a number of conductors which is equal to that of the first part (22 a) of the interconnector for electrical coupling of the coils in star form. 6. Interconnector according to claim 1, wherein the first part (22 a) of the interconnector has support feet in the form of an “L” which are designed to be supported on a rim of a head (17) which belongs to the body (12) of the stator. 7. Interconnector according to claim 6, wherein the second part (22 b) of the interconnector has support feet in the form of an “L” which are designed to be supported on the other rim of a head (17) which belongs to the body (12) of the stator. 8. Interconnector according to claim 1, wherein it is secured on at least one coil insulator. 9. Interconnector according to claim 8, wherein it is secured on at least three insulators. 10. Interconnector according to claim 8, wherein it comprises at least one clip which cooperates with an opening provided in a rear rim of the insulator. 11. Interconnector according to claim 1, wherein the coils are coupled in the form of a triangle. 12. Stator (11) of a rotary electrical machine comprising a stator (11) body (12), supporting a winding provided with a plurality of coils (19) which each have input (191) and output (192) ends, wherein said ends (191, 192) are connected to an interconnector (22 a, 22 b) according to claim 1. 13. Stator according to claim 12, wherein the input (191) and output (192) ends of the coils (19) are implanted respectively at one and the other of the axial ends of the coils. 14. Stator according to claim 12, wherein the ends (191, 192) of the coils are implanted on both sides of the body (12) of the stator. 15. Stator according to claim 12, wherein the ends (191, 192) of the coils (19) are implanted on a circumference which is at least equal to that of the inner periphery of the body (12) of the stator. 16. Interconnector according to claim 2, wherein the first part (22 a) of the interconnector comprises more than three conductors. 17. Interconnector according to claim 3, wherein the first part (22 a) of the interconnector comprises more than three conductors. 18. Interconnector according to claim 2, wherein the second part (22 b) of the interconnector has a number of conductors which is equal to that of the first part (22 a) of the interconnector for electrical coupling of the coils in star form. 19. Interconnector according to claim 3, wherein the second part (22 b) of the interconnector has a number of conductors which is equal to that of the first part (22 a) of the interconnector for electrical coupling of the coils in star form. 20. Interconnector according to claim 4, wherein the second part (22 b) of the interconnector has a number of conductors which is equal to that of the first part (22 a) of the interconnector for electrical coupling of the coils in star form. | 2,800 |
11,875 | 11,875 | 15,425,171 | 2,829 | A semiconductor device has a first substrate with a vertical electrical interconnect structure formed between opposing surfaces of the first substrate. A semiconductor die is embedded within the first substrate. A plurality of semiconductor pellets is disposed over or within the first substrate. A first semiconductor pellet is doped to a first conductivity type, and a second semiconductor pellet is doped to a second conductivity type. A second thermally conductive substrate is disposed over the semiconductor pellets opposite the first substrate. An image sensor is disposed over the first substrate. The image sensor is electrically connected through the vertical electrical interconnect structure of the first substrate. An encapsulant is deposited over the image sensor with an opening in the encapsulant over an active region of the image sensor. Electric current is enabled through the semiconductor pellets for heat dissipation of the image sensor. | 1-6. (canceled) 7. A method of making a semiconductor device with an image sensor, comprising:
providing a first substrate including a vertical electrical interconnect structure formed through the first substrate; disposing a plurality of semiconductor pellets over the first substrate; and disposing an image sensor over the first substrate, wherein the image sensor is electrically connected to the vertical electrical interconnect structure of the first substrate. 8. The method of claim 7, further including disposing a second substrate over the semiconductor pellets opposite the first substrate. 9. The method of claim 8, wherein the second substrate is thermally conductive. 10. The method of claim 7, wherein a first semiconductor pellet of the plurality of semiconductor pellets is doped to a first conductivity type and a second semiconductor pellet of the plurality of semiconductor pellets is doped to a second conductivity type. 11. The method of claim 7, further including depositing an encapsulant over the image sensor with an opening in the encapsulant over an active region of the image sensor. 12. The method of claim 7, further including providing a conduction path through the semiconductor pellets for heat dissipation of the image sensor. 13. The method of claim 7, further including disposing a semiconductor die embedded within the first substrate. 14. An image sensor semiconductor package, comprising:
a first substrate including a vertical electrical interconnect structure formed through the first substrate; a plurality of semiconductor pellets disposed over the first substrate; and an image sensor disposed over the first substrate, wherein the image sensor is electrically connected to the vertical electrical interconnect structure of the first substrate. 15. The image sensor semiconductor package of claim 14, further including a second substrate disposed over the semiconductor pellets opposite the first substrate. 16. The image sensor semiconductor package of claim 15, wherein the second substrate is thermally conductive. 17. The image sensor semiconductor package of claim 14, wherein a first semiconductor pellet of the plurality of semiconductor pellets is doped to a first conductivity type and a second semiconductor pellet of the plurality of semiconductor pellets is doped to a second conductivity type. 18. The image sensor semiconductor package of claim 14, further including an encapsulant deposited over the image sensor with an opening in the encapsulant over an active region of the image sensor. 19. The image sensor semiconductor package of claim 14, further including a conduction path through the semiconductor pellets for heat dissipation of the image sensor. 20. The image sensor semiconductor package of claim 14, further including a semiconductor die embedded within the first substrate. 21. A semiconductor device with an image sensor, comprising:
a first substrate including a vertical electrical interconnect structure formed between opposing surfaces of the first substrate; a first semiconductor pellet disposed over the first substrate; a second semiconductor pellet disposed over the first substrate; and an image sensor disposed over the first substrate, wherein the image sensor is electrically connected through the vertical electrical interconnect structure of the first substrate. 22. The semiconductor device of claim 21, further including a second substrate disposed over the first semiconductor pellet and second semiconductor pellet opposite the first substrate. 23. The semiconductor device of claim 22, wherein the second substrate is thermally conductive. 24. The semiconductor device of claim 21, wherein the first semiconductor pellet is doped to a first conductivity type and the second semiconductor pellet is doped to a second conductivity type. 25. The semiconductor device of claim 21, further including an encapsulant deposited over the image sensor with an opening in the encapsulant over an active region of the image sensor. 26. The semiconductor device of claim 21, further including a semiconductor die embedded within the first substrate. | A semiconductor device has a first substrate with a vertical electrical interconnect structure formed between opposing surfaces of the first substrate. A semiconductor die is embedded within the first substrate. A plurality of semiconductor pellets is disposed over or within the first substrate. A first semiconductor pellet is doped to a first conductivity type, and a second semiconductor pellet is doped to a second conductivity type. A second thermally conductive substrate is disposed over the semiconductor pellets opposite the first substrate. An image sensor is disposed over the first substrate. The image sensor is electrically connected through the vertical electrical interconnect structure of the first substrate. An encapsulant is deposited over the image sensor with an opening in the encapsulant over an active region of the image sensor. Electric current is enabled through the semiconductor pellets for heat dissipation of the image sensor.1-6. (canceled) 7. A method of making a semiconductor device with an image sensor, comprising:
providing a first substrate including a vertical electrical interconnect structure formed through the first substrate; disposing a plurality of semiconductor pellets over the first substrate; and disposing an image sensor over the first substrate, wherein the image sensor is electrically connected to the vertical electrical interconnect structure of the first substrate. 8. The method of claim 7, further including disposing a second substrate over the semiconductor pellets opposite the first substrate. 9. The method of claim 8, wherein the second substrate is thermally conductive. 10. The method of claim 7, wherein a first semiconductor pellet of the plurality of semiconductor pellets is doped to a first conductivity type and a second semiconductor pellet of the plurality of semiconductor pellets is doped to a second conductivity type. 11. The method of claim 7, further including depositing an encapsulant over the image sensor with an opening in the encapsulant over an active region of the image sensor. 12. The method of claim 7, further including providing a conduction path through the semiconductor pellets for heat dissipation of the image sensor. 13. The method of claim 7, further including disposing a semiconductor die embedded within the first substrate. 14. An image sensor semiconductor package, comprising:
a first substrate including a vertical electrical interconnect structure formed through the first substrate; a plurality of semiconductor pellets disposed over the first substrate; and an image sensor disposed over the first substrate, wherein the image sensor is electrically connected to the vertical electrical interconnect structure of the first substrate. 15. The image sensor semiconductor package of claim 14, further including a second substrate disposed over the semiconductor pellets opposite the first substrate. 16. The image sensor semiconductor package of claim 15, wherein the second substrate is thermally conductive. 17. The image sensor semiconductor package of claim 14, wherein a first semiconductor pellet of the plurality of semiconductor pellets is doped to a first conductivity type and a second semiconductor pellet of the plurality of semiconductor pellets is doped to a second conductivity type. 18. The image sensor semiconductor package of claim 14, further including an encapsulant deposited over the image sensor with an opening in the encapsulant over an active region of the image sensor. 19. The image sensor semiconductor package of claim 14, further including a conduction path through the semiconductor pellets for heat dissipation of the image sensor. 20. The image sensor semiconductor package of claim 14, further including a semiconductor die embedded within the first substrate. 21. A semiconductor device with an image sensor, comprising:
a first substrate including a vertical electrical interconnect structure formed between opposing surfaces of the first substrate; a first semiconductor pellet disposed over the first substrate; a second semiconductor pellet disposed over the first substrate; and an image sensor disposed over the first substrate, wherein the image sensor is electrically connected through the vertical electrical interconnect structure of the first substrate. 22. The semiconductor device of claim 21, further including a second substrate disposed over the first semiconductor pellet and second semiconductor pellet opposite the first substrate. 23. The semiconductor device of claim 22, wherein the second substrate is thermally conductive. 24. The semiconductor device of claim 21, wherein the first semiconductor pellet is doped to a first conductivity type and the second semiconductor pellet is doped to a second conductivity type. 25. The semiconductor device of claim 21, further including an encapsulant deposited over the image sensor with an opening in the encapsulant over an active region of the image sensor. 26. The semiconductor device of claim 21, further including a semiconductor die embedded within the first substrate. | 2,800 |
11,876 | 11,876 | 16,025,520 | 2,886 | A device for analysing a product to be analysed which is located in a product space having a probe body arranged in a probe housing and having a peripheral wall, and at least one radiation source and at least one optical receiver. At least one measurement window in the probe body has an entry region and an exit region for measurement radiation. An evaluation unit is also provided. The probe body can be brought into a measurement position, in which at least one part of the probe body in which the measurement window is located penetrates through an opening of the probe housing into the product space for the analysis. In addition, the probe body can be brought into a retracted position, in which the probe body is still located at least partially in the region of the opening of the probe housing and thus covers the opening. | 1. A device for an analysis of a product to be analyzed that is located in a product space, the device comprising:
a probe body with a circumferential wall that is arranged in a probe housing; at least one radiation source; at least one optical receiver; at least one measurement window arranged in the probe body with an entrance region and an exit region for measurement radiation; and an evaluation unit; wherein, in a measurement position of the probe body, at which at least one part of the probe body in which the measurement window is arranged plunges through an opening of the probe housing into the product space for analysis, and wherein, in a retracted position of the probe body, at which the probe body is at least still partly situated in a region of the opening of the probe housing and covers the opening at the same time, wherein the at least one measurement window is an ATR element, and wherein the ATR element is arranged in at least one subregion of the circumferential wall of the probe body in the beam path. 2. The device as claimed in claim 1, wherein the ATR element is a hollow cylinder or hollow sphere or a hollow-cylinder segment or a hollow-sphere segment. 3. The device as claimed in claim 1, wherein the entrance region and/or exit region of the measurement radiation of an ATR element is designed such that the measurement radiation in the ATR element is guided to the exit region in parallel to the longitudinal axis. 4. The device as claimed in claim 1, wherein the entrance region and/or exit region of the measurement radiation is, in a case of a cylindrical ATR element, designed such that the measurement radiation in the ATR element is guided in a circular and circumferential manner to the exit region. 5. The device as claimed in claim 1, wherein the entrance region and/or exit region of the measurement radiation is, in a case of a cylindrical ATR element, designed such that the measurement radiation in the ATR element is guided in a spiral and circumferential manner to the exit region. 6. The device as claimed in claim 1, further comprising at least two ATR elements arranged over the circumferential wall of the probe body. 7. The device as claimed in claim 1, wherein the at least one ATR element is flush with an outer side of the circumferential wall of the probe body. 8. The device as claimed in claim 1, wherein the at least one ATR element is, apart from the entrance region and/or exit region of the measurement radiation, flush with an inner side of the circumferential wall of the probe body. 9. The device as claimed in claim 1, wherein the entrance region and/or exit region of the measurement radiation of the ATR element is designed as a lattice coupler and/or as a prism coupler. 10. The device as claimed in claim 1, wherein the entrance region and/or exit region of the measurement radiation of the ATR element is designed as a notch or in a tapered realization on the inner side of the ATR element. 11. The device as claimed in claim 1, wherein the at least one ATR element is usable for the coupling-in and coupling-out of further optical measurement arrangements. 12. The device as claimed in claim 11, wherein the at least one ATR element is an imaging optical element for further optical measurement arrangements. 13. The device as claimed in claim 1, wherein the at least one ATR element is at least partly coated with a dielectric layer and/or with a metal layer on the inner side and/or outer side. 14. The device as claimed in claim 1, further comprising a mirror via which the measurement radiation, after exit from the ATR element, is coupled again into the ATR element. 15. The device as claimed in claim 1, further comprising a mirror for the simultaneous coupling-in of the measurement radiation into the ATR element at different points. | A device for analysing a product to be analysed which is located in a product space having a probe body arranged in a probe housing and having a peripheral wall, and at least one radiation source and at least one optical receiver. At least one measurement window in the probe body has an entry region and an exit region for measurement radiation. An evaluation unit is also provided. The probe body can be brought into a measurement position, in which at least one part of the probe body in which the measurement window is located penetrates through an opening of the probe housing into the product space for the analysis. In addition, the probe body can be brought into a retracted position, in which the probe body is still located at least partially in the region of the opening of the probe housing and thus covers the opening.1. A device for an analysis of a product to be analyzed that is located in a product space, the device comprising:
a probe body with a circumferential wall that is arranged in a probe housing; at least one radiation source; at least one optical receiver; at least one measurement window arranged in the probe body with an entrance region and an exit region for measurement radiation; and an evaluation unit; wherein, in a measurement position of the probe body, at which at least one part of the probe body in which the measurement window is arranged plunges through an opening of the probe housing into the product space for analysis, and wherein, in a retracted position of the probe body, at which the probe body is at least still partly situated in a region of the opening of the probe housing and covers the opening at the same time, wherein the at least one measurement window is an ATR element, and wherein the ATR element is arranged in at least one subregion of the circumferential wall of the probe body in the beam path. 2. The device as claimed in claim 1, wherein the ATR element is a hollow cylinder or hollow sphere or a hollow-cylinder segment or a hollow-sphere segment. 3. The device as claimed in claim 1, wherein the entrance region and/or exit region of the measurement radiation of an ATR element is designed such that the measurement radiation in the ATR element is guided to the exit region in parallel to the longitudinal axis. 4. The device as claimed in claim 1, wherein the entrance region and/or exit region of the measurement radiation is, in a case of a cylindrical ATR element, designed such that the measurement radiation in the ATR element is guided in a circular and circumferential manner to the exit region. 5. The device as claimed in claim 1, wherein the entrance region and/or exit region of the measurement radiation is, in a case of a cylindrical ATR element, designed such that the measurement radiation in the ATR element is guided in a spiral and circumferential manner to the exit region. 6. The device as claimed in claim 1, further comprising at least two ATR elements arranged over the circumferential wall of the probe body. 7. The device as claimed in claim 1, wherein the at least one ATR element is flush with an outer side of the circumferential wall of the probe body. 8. The device as claimed in claim 1, wherein the at least one ATR element is, apart from the entrance region and/or exit region of the measurement radiation, flush with an inner side of the circumferential wall of the probe body. 9. The device as claimed in claim 1, wherein the entrance region and/or exit region of the measurement radiation of the ATR element is designed as a lattice coupler and/or as a prism coupler. 10. The device as claimed in claim 1, wherein the entrance region and/or exit region of the measurement radiation of the ATR element is designed as a notch or in a tapered realization on the inner side of the ATR element. 11. The device as claimed in claim 1, wherein the at least one ATR element is usable for the coupling-in and coupling-out of further optical measurement arrangements. 12. The device as claimed in claim 11, wherein the at least one ATR element is an imaging optical element for further optical measurement arrangements. 13. The device as claimed in claim 1, wherein the at least one ATR element is at least partly coated with a dielectric layer and/or with a metal layer on the inner side and/or outer side. 14. The device as claimed in claim 1, further comprising a mirror via which the measurement radiation, after exit from the ATR element, is coupled again into the ATR element. 15. The device as claimed in claim 1, further comprising a mirror for the simultaneous coupling-in of the measurement radiation into the ATR element at different points. | 2,800 |
11,877 | 11,877 | 14,634,241 | 2,876 | Exemplary embodiments are disclosed herein for processing one or more sheets of sheet material in a deposit include various systems and processes. The systems and processes include receiving a sheet in a sheet-accepting device. Further, the systems and processes include reading, by a sensor, an identifier on each sheet, detecting anomaly information for the sheet that identifies an anomalous characteristic of the sheet. The systems and processes also include determining, for each sheet, information about the sheet from the identifier on the sheet, including accounting information and deposit information, including a value associated with the deposit. Moreover, the systems and processes include performing a reconciling process when the anomaly information identifies an anomalous characteristic of the sheet, including debiting the account associated with the sheet based on the value associated with the deposit that included the sheet, and crediting the account based on that value. | 1. A system configured to process a plurality of sheets of sheet material, wherein the plurality of sheets of sheet material comprise currency objects, the system comprising:
a sheet-accepting device configured to receive the plurality of sheets; at least one sensor configured to read an identifier on each sheet of the plurality of sheets, wherein one of said at least one sensor is further configured to detect anomaly information for the sheet, the anomaly information identifying an anomalous characteristic of the sheet; a processing system configured to determine, for each sheet of the plurality of sheets, information about the sheet from the identifier on the sheet, the information about the sheet including:
accounting information for the sheet, the accounting information identifying an account associated with the sheet; and
deposit information for the sheet, the deposit information comprising information about a deposit including the sheet, and the information about the deposit including a value associated with the deposit,
wherein, for each sheet of the plurality of sheets, the processing system is further configured to perform a reconciling process when the anomaly information identifies a first anomalous characteristic of the sheet, the reconciling process comprising one or more of:
debiting the account associated with the sheet based on the value associated with the deposit that included the sheet; and
crediting the account associated with the sheet based on the value associated with the deposit including the sheet. 2. The system according to claim 1,
wherein the plurality of sheets are all sheets that have been previously rejected based on the anomalous characteristic of the respective sheet in a previous sheet handling process, and wherein the accounting information for each sheet and the deposit information for each sheet were associated with the identifier on the sheet as part of the previous sheet handling process. 3. The system according to claim 1, further comprising:
a memory, wherein the identifier on each sheet of the plurality of sheets is a serial number of the sheet, and wherein the serial number of each sheet of the plurality of sheets is linked to the accounting information for the sheet and the deposit information for the sheet in the memory. 4. The system according to claim 1,
wherein, for each sheet of the plurality of sheets, the processing system is further configured not to perform the reconciling process when the anomaly information identifies a second anomalous characteristic of the sheet, and wherein the second anomalous characteristic of the sheet is that the sheet is a counterfeit. 5. The system according to claim 1, wherein the system further comprises:
a first container; and a second container, wherein the processing device is further configured to:
sort the sheet into the first container when the anomaly information indicates that the sheet is acceptable for recirculation, and
sort the sheet into the second container when the anomaly information indicates that the sheet is not acceptable for recirculation. 6. The system according to claim 1,
wherein the first anomalous characteristic of the sheet is that the sheet is damaged but is not in condition for destruction, and wherein, for each sheet of the plurality of sheets, the processing system is further configured to identify the sheet for recirculation when the anomaly information identifies the first anomalous characteristic of the sheet. 7. The system according to claim 1,
wherein the first anomalous characteristic of the sheet is that the sheet is damaged, and wherein, for each sheet of the plurality of sheets, the processing system is further configured to identify the sheet for destruction when the anomaly information identifies the first anomalous characteristic of the sheet. 8. A method for processing one or more of a plurality of sheets of sheet material, wherein the plurality of sheets of sheet material comprise currency objects, the method comprising:
receiving one or more sheet of the plurality of sheets in a sheet-accepting device; reading, by at least one sensor, an identifier on each sheet of the plurality of sheets, wherein reading the identifier further comprises detecting anomaly information for the sheet, the anomaly information identifying an anomalous characteristic of the sheet; determining, for each sheet of the plurality of sheets, information about the sheet from the identifier on the sheet, the information about the sheet including:
accounting information for the sheet, the accounting information identifying an account associated with the sheet; and
deposit information for the sheet, the deposit information comprising information about a deposit including the sheet, and the information about the deposit including a value associated with the deposit; and
performing a reconciling process when the anomaly information identifies a first anomalous characteristic of the sheet, the reconciling process comprising one or more of:
debiting the account associated with the sheet based on the value associated with the deposit that included the sheet; and
crediting the account associated with the sheet based on the value associated with the deposit including the sheet. 9. The method according to claim 8,
wherein the plurality of sheets are all sheets that have been previously rejected based on the anomalous characteristic of the respective sheet in a previous sheet handling process, and wherein the accounting information for each sheet and the deposit information for each sheet were associated with the identifier on the sheet as part of the previous sheet handling process. 10. The method according to claim 8,
wherein the identifier on each sheet of the plurality of sheets is a serial number of the sheet, and wherein the serial number of each sheet of the plurality of sheets is linked to the accounting information for the sheet and the deposit information for the sheet in a memory. 11. The method according to claim 8,
wherein, for each sheet of the plurality of sheets, the method further comprises not performing the reconciling process when the anomaly information identifies a second anomalous characteristic of the sheet, and wherein the second anomalous characteristic of the sheet is that the sheet is a counterfeit. 12. The method according to claim 8,
wherein, for each sheet of the plurality of sheets, the method further comprises:
sorting the sheet into a first container when the anomaly information indicates that the sheet is acceptable for recirculation, and
sorting the sheet into a second container when the anomaly information indicates that the sheet is not acceptable for recirculation. 13. The method according to claim 8,
wherein the first anomalous characteristic of the sheet is that the sheet is damaged but is not in condition for destruction, and wherein, for each sheet of the plurality of sheets, the method further comprises identifying the sheet for recirculation when the anomaly information identifies the first anomalous characteristic of the sheet. 14. The method according to claim 8,
wherein the first anomalous characteristic of the sheet is that the sheet is damaged, and wherein, for each sheet of the plurality of sheets, the method further comprises identifying the sheet for destruction when the anomaly information identifies the first anomalous characteristic of the sheet. 15. A non-transitory, computer-readable medium storing computer-readable instructions that, when executed by at least one processor, instruct the at least one processor to control processes for processing one or more of a plurality of sheets of sheet material, wherein the plurality of sheets of sheet material comprise currency objects, the processes comprising:
receiving one or more sheet of the plurality of sheets in a sheet-accepting device; reading, by at least one sensor, an identifier on each sheet of the plurality of sheets, wherein reading the identifier further comprises detecting anomaly information for the sheet, the anomaly information identifying an anomalous characteristic of the sheet; determining, for each sheet of the plurality of sheets, information about the sheet from the identifier on the sheet, the information about the sheet including:
accounting information for the sheet, the accounting information identifying an account associated with the sheet; and
deposit information for the sheet, the deposit information comprising information about a deposit including the sheet, and the information about the deposit including a value associated with the deposit; and
performing a reconciling process when the anomaly information identifies a first anomalous characteristic of the sheet, the reconciling process comprising one or more of:
debiting the account associated with the sheet based on the value associated with the deposit that included the sheet; and
crediting the account associated with the sheet based on the value associated with the deposit including the sheet. 16. The non-transitory, computer-readable medium according to claim 15,
wherein the plurality of sheets are all sheets that have been previously rejected based on the anomalous characteristic of the respective sheet in a previous sheet handling process, and wherein the accounting information for each sheet and the deposit information for each sheet were associated with the identifier on the sheet as part of the previous sheet handling process. 17. The non-transitory, computer-readable medium according to claim 15,
wherein the identifier on each sheet of the plurality of sheets is a serial number of the sheet, and wherein the serial number of each sheet of the plurality of sheets is linked to the accounting information for the sheet and the deposit information for the sheet in a memory. 18. The non-transitory, computer-readable medium according to claim 15,
wherein, for each sheet of the plurality of sheets, the computer-readable instructions, when executed by the at least one processor, further instruct the at least one processor to control processes comprising not performing the reconciling process when the anomaly information identifies a second anomalous characteristic of the sheet, and wherein the second anomalous characteristic of the sheet is that the sheet is a counterfeit. 19. The non-transitory, computer-readable medium according to claim 15,
wherein, for each sheet of the plurality of sheets, the computer-readable instructions, when executed by the at least one processor, further instruct the at least one processor to control processes comprising:
sorting the sheet into a first container when the anomaly information indicates that the sheet is acceptable for recirculation, and
sorting the sheet into a second container when the anomaly information indicates that the sheet is not acceptable for recirculation. 20. The non-transitory, computer-readable medium according to claim 15,
wherein the first anomalous characteristic of the sheet is that the sheet is damaged but is not in condition for destruction, and wherein, for each sheet of the plurality of sheets, the computer-readable instructions, when executed by the at least one processor, further instruct the at least one processor to control processes comprising identifying the sheet for recirculation when the anomaly information identifies the first anomalous characteristic of the sheet. 21. The system according to claim 1, wherein the currency object comprises one of:
currency; a ticket; a ticket-in, ticket-out (TITO) ticket; or a voucher. 22. The method according to claim 8, wherein the currency object comprises one of:
currency; a ticket; a ticket-in, ticket-out (TITO) ticket; or a voucher. 23. The non-transitory, computer-readable medium according to claim 15, wherein the currency object comprises one of:
currency; a ticket; a ticket-in, ticket-out (TITO) ticket; or a voucher. | Exemplary embodiments are disclosed herein for processing one or more sheets of sheet material in a deposit include various systems and processes. The systems and processes include receiving a sheet in a sheet-accepting device. Further, the systems and processes include reading, by a sensor, an identifier on each sheet, detecting anomaly information for the sheet that identifies an anomalous characteristic of the sheet. The systems and processes also include determining, for each sheet, information about the sheet from the identifier on the sheet, including accounting information and deposit information, including a value associated with the deposit. Moreover, the systems and processes include performing a reconciling process when the anomaly information identifies an anomalous characteristic of the sheet, including debiting the account associated with the sheet based on the value associated with the deposit that included the sheet, and crediting the account based on that value.1. A system configured to process a plurality of sheets of sheet material, wherein the plurality of sheets of sheet material comprise currency objects, the system comprising:
a sheet-accepting device configured to receive the plurality of sheets; at least one sensor configured to read an identifier on each sheet of the plurality of sheets, wherein one of said at least one sensor is further configured to detect anomaly information for the sheet, the anomaly information identifying an anomalous characteristic of the sheet; a processing system configured to determine, for each sheet of the plurality of sheets, information about the sheet from the identifier on the sheet, the information about the sheet including:
accounting information for the sheet, the accounting information identifying an account associated with the sheet; and
deposit information for the sheet, the deposit information comprising information about a deposit including the sheet, and the information about the deposit including a value associated with the deposit,
wherein, for each sheet of the plurality of sheets, the processing system is further configured to perform a reconciling process when the anomaly information identifies a first anomalous characteristic of the sheet, the reconciling process comprising one or more of:
debiting the account associated with the sheet based on the value associated with the deposit that included the sheet; and
crediting the account associated with the sheet based on the value associated with the deposit including the sheet. 2. The system according to claim 1,
wherein the plurality of sheets are all sheets that have been previously rejected based on the anomalous characteristic of the respective sheet in a previous sheet handling process, and wherein the accounting information for each sheet and the deposit information for each sheet were associated with the identifier on the sheet as part of the previous sheet handling process. 3. The system according to claim 1, further comprising:
a memory, wherein the identifier on each sheet of the plurality of sheets is a serial number of the sheet, and wherein the serial number of each sheet of the plurality of sheets is linked to the accounting information for the sheet and the deposit information for the sheet in the memory. 4. The system according to claim 1,
wherein, for each sheet of the plurality of sheets, the processing system is further configured not to perform the reconciling process when the anomaly information identifies a second anomalous characteristic of the sheet, and wherein the second anomalous characteristic of the sheet is that the sheet is a counterfeit. 5. The system according to claim 1, wherein the system further comprises:
a first container; and a second container, wherein the processing device is further configured to:
sort the sheet into the first container when the anomaly information indicates that the sheet is acceptable for recirculation, and
sort the sheet into the second container when the anomaly information indicates that the sheet is not acceptable for recirculation. 6. The system according to claim 1,
wherein the first anomalous characteristic of the sheet is that the sheet is damaged but is not in condition for destruction, and wherein, for each sheet of the plurality of sheets, the processing system is further configured to identify the sheet for recirculation when the anomaly information identifies the first anomalous characteristic of the sheet. 7. The system according to claim 1,
wherein the first anomalous characteristic of the sheet is that the sheet is damaged, and wherein, for each sheet of the plurality of sheets, the processing system is further configured to identify the sheet for destruction when the anomaly information identifies the first anomalous characteristic of the sheet. 8. A method for processing one or more of a plurality of sheets of sheet material, wherein the plurality of sheets of sheet material comprise currency objects, the method comprising:
receiving one or more sheet of the plurality of sheets in a sheet-accepting device; reading, by at least one sensor, an identifier on each sheet of the plurality of sheets, wherein reading the identifier further comprises detecting anomaly information for the sheet, the anomaly information identifying an anomalous characteristic of the sheet; determining, for each sheet of the plurality of sheets, information about the sheet from the identifier on the sheet, the information about the sheet including:
accounting information for the sheet, the accounting information identifying an account associated with the sheet; and
deposit information for the sheet, the deposit information comprising information about a deposit including the sheet, and the information about the deposit including a value associated with the deposit; and
performing a reconciling process when the anomaly information identifies a first anomalous characteristic of the sheet, the reconciling process comprising one or more of:
debiting the account associated with the sheet based on the value associated with the deposit that included the sheet; and
crediting the account associated with the sheet based on the value associated with the deposit including the sheet. 9. The method according to claim 8,
wherein the plurality of sheets are all sheets that have been previously rejected based on the anomalous characteristic of the respective sheet in a previous sheet handling process, and wherein the accounting information for each sheet and the deposit information for each sheet were associated with the identifier on the sheet as part of the previous sheet handling process. 10. The method according to claim 8,
wherein the identifier on each sheet of the plurality of sheets is a serial number of the sheet, and wherein the serial number of each sheet of the plurality of sheets is linked to the accounting information for the sheet and the deposit information for the sheet in a memory. 11. The method according to claim 8,
wherein, for each sheet of the plurality of sheets, the method further comprises not performing the reconciling process when the anomaly information identifies a second anomalous characteristic of the sheet, and wherein the second anomalous characteristic of the sheet is that the sheet is a counterfeit. 12. The method according to claim 8,
wherein, for each sheet of the plurality of sheets, the method further comprises:
sorting the sheet into a first container when the anomaly information indicates that the sheet is acceptable for recirculation, and
sorting the sheet into a second container when the anomaly information indicates that the sheet is not acceptable for recirculation. 13. The method according to claim 8,
wherein the first anomalous characteristic of the sheet is that the sheet is damaged but is not in condition for destruction, and wherein, for each sheet of the plurality of sheets, the method further comprises identifying the sheet for recirculation when the anomaly information identifies the first anomalous characteristic of the sheet. 14. The method according to claim 8,
wherein the first anomalous characteristic of the sheet is that the sheet is damaged, and wherein, for each sheet of the plurality of sheets, the method further comprises identifying the sheet for destruction when the anomaly information identifies the first anomalous characteristic of the sheet. 15. A non-transitory, computer-readable medium storing computer-readable instructions that, when executed by at least one processor, instruct the at least one processor to control processes for processing one or more of a plurality of sheets of sheet material, wherein the plurality of sheets of sheet material comprise currency objects, the processes comprising:
receiving one or more sheet of the plurality of sheets in a sheet-accepting device; reading, by at least one sensor, an identifier on each sheet of the plurality of sheets, wherein reading the identifier further comprises detecting anomaly information for the sheet, the anomaly information identifying an anomalous characteristic of the sheet; determining, for each sheet of the plurality of sheets, information about the sheet from the identifier on the sheet, the information about the sheet including:
accounting information for the sheet, the accounting information identifying an account associated with the sheet; and
deposit information for the sheet, the deposit information comprising information about a deposit including the sheet, and the information about the deposit including a value associated with the deposit; and
performing a reconciling process when the anomaly information identifies a first anomalous characteristic of the sheet, the reconciling process comprising one or more of:
debiting the account associated with the sheet based on the value associated with the deposit that included the sheet; and
crediting the account associated with the sheet based on the value associated with the deposit including the sheet. 16. The non-transitory, computer-readable medium according to claim 15,
wherein the plurality of sheets are all sheets that have been previously rejected based on the anomalous characteristic of the respective sheet in a previous sheet handling process, and wherein the accounting information for each sheet and the deposit information for each sheet were associated with the identifier on the sheet as part of the previous sheet handling process. 17. The non-transitory, computer-readable medium according to claim 15,
wherein the identifier on each sheet of the plurality of sheets is a serial number of the sheet, and wherein the serial number of each sheet of the plurality of sheets is linked to the accounting information for the sheet and the deposit information for the sheet in a memory. 18. The non-transitory, computer-readable medium according to claim 15,
wherein, for each sheet of the plurality of sheets, the computer-readable instructions, when executed by the at least one processor, further instruct the at least one processor to control processes comprising not performing the reconciling process when the anomaly information identifies a second anomalous characteristic of the sheet, and wherein the second anomalous characteristic of the sheet is that the sheet is a counterfeit. 19. The non-transitory, computer-readable medium according to claim 15,
wherein, for each sheet of the plurality of sheets, the computer-readable instructions, when executed by the at least one processor, further instruct the at least one processor to control processes comprising:
sorting the sheet into a first container when the anomaly information indicates that the sheet is acceptable for recirculation, and
sorting the sheet into a second container when the anomaly information indicates that the sheet is not acceptable for recirculation. 20. The non-transitory, computer-readable medium according to claim 15,
wherein the first anomalous characteristic of the sheet is that the sheet is damaged but is not in condition for destruction, and wherein, for each sheet of the plurality of sheets, the computer-readable instructions, when executed by the at least one processor, further instruct the at least one processor to control processes comprising identifying the sheet for recirculation when the anomaly information identifies the first anomalous characteristic of the sheet. 21. The system according to claim 1, wherein the currency object comprises one of:
currency; a ticket; a ticket-in, ticket-out (TITO) ticket; or a voucher. 22. The method according to claim 8, wherein the currency object comprises one of:
currency; a ticket; a ticket-in, ticket-out (TITO) ticket; or a voucher. 23. The non-transitory, computer-readable medium according to claim 15, wherein the currency object comprises one of:
currency; a ticket; a ticket-in, ticket-out (TITO) ticket; or a voucher. | 2,800 |
11,878 | 11,878 | 15,949,077 | 2,824 | A memory device includes a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit includes a plurality of memory cells, at least one bit line, and at least one column word line. The plurality of memory cells are arranged along a second direction different from the first direction. The at least one bit line is elongated along the second direction, and configured to transmit data of a selected memory cell. The at least one column word line is elongated along the second direction, and configured to control electrical connections between the memory cells and the at least one bit line, wherein the selected memory cell is selected by a corresponding word line and the at least one column word line. | 1. A memory device, comprising:
a plurality of word lines elongated along a first direction; and at least one memory unit comprising:
a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells;
at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell;
at least one column word line elongated along the second direction;
a plurality of row word lines elongated along the first direction;
a plurality of column switches arranged along the second direction, each of the column switches having a control terminal coupled to the at least one column word line, a first terminal, and a second terminal, each of the column switches configured to control conduction between the first terminal and the second terminal according to signals received from the control terminal; and
a plurality of row switches arranged along the second direction, each of the row switches having a control terminal coupled to a row word line, a first terminal, and a second terminal, each of the row switches configured to control conduction between the first terminal and the second terminal according to signals received from the control terminal;
wherein each of the column switches and each of the row switches are electrically coupled in series between the at least one bit line and the plurality of memory cells of one of the memory cell groups. 2. The memory device of claim 1, wherein the selected memory cell is selected by a corresponding word line, the at least one column word line and a corresponding row word line. 3. The memory device of claim 1, wherein the plurality of column switches and the plurality of row switches are transistors. 4. The memory device of claim 1, wherein the memory device comprises a plurality of the memory units arranged along the first direction, a predetermined number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the column switches of corresponding memory blocks respectively. 5. The memory device of claim 1, wherein in the at least one memory unit, the plurality of memory cell groups arranged along the second direction are electrically isolated from each other by the plurality of row switches. 6. A memory device, comprising:
a plurality of word lines elongated along a first direction; and at least one memory unit comprising:
a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells;
at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell;
at least one column word line elongated along the second direction; and
a plurality of column switches arranged along the second direction, each of the column switches having a control terminal coupled to the at least one column word line, a first terminal coupled to one of the memory cell groups, and a second terminal coupled to the at least one bit line, each of the column switches configured to control conduction between the at least one bit line and one of the memory cell groups;
wherein a plurality of the memory units are arranged along the first direction, a predetermined number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the column switches of corresponding memory blocks respectively. 7. The memory device of claim 6, wherein the selected memory cell is selected by a corresponding word line, the at least one column word line and a corresponding row word line. 8. The memory device of claim 6, wherein the plurality of column switches and the plurality of row switches are transistors. 9. The memory device of claim 6, wherein the at least one memory unit further comprises:
a plurality of row word lines elongated along the first direction; and a plurality of row switches arranged along the second direction, each of the row switches having a control terminal coupled to a corresponding row word line; wherein each of the row switches and a corresponding column switch are coupled between one of the memory cell groups and the at least one bit line in series; wherein in the at least one memory unit, the plurality of memory cell groups arranged along the second direction are electrically isolated from each other by the plurality of row switches. 10. A memory device, comprising:
a plurality of word lines elongated along a first direction; and at least one memory unit comprising:
a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells;
at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell;
at least one column word line elongated along the second direction;
a plurality of row word lines elongated along the first direction;
wherein the selected memory cell is selected by a corresponding word line, the at least one column word line and a corresponding row word line. | A memory device includes a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit includes a plurality of memory cells, at least one bit line, and at least one column word line. The plurality of memory cells are arranged along a second direction different from the first direction. The at least one bit line is elongated along the second direction, and configured to transmit data of a selected memory cell. The at least one column word line is elongated along the second direction, and configured to control electrical connections between the memory cells and the at least one bit line, wherein the selected memory cell is selected by a corresponding word line and the at least one column word line.1. A memory device, comprising:
a plurality of word lines elongated along a first direction; and at least one memory unit comprising:
a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells;
at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell;
at least one column word line elongated along the second direction;
a plurality of row word lines elongated along the first direction;
a plurality of column switches arranged along the second direction, each of the column switches having a control terminal coupled to the at least one column word line, a first terminal, and a second terminal, each of the column switches configured to control conduction between the first terminal and the second terminal according to signals received from the control terminal; and
a plurality of row switches arranged along the second direction, each of the row switches having a control terminal coupled to a row word line, a first terminal, and a second terminal, each of the row switches configured to control conduction between the first terminal and the second terminal according to signals received from the control terminal;
wherein each of the column switches and each of the row switches are electrically coupled in series between the at least one bit line and the plurality of memory cells of one of the memory cell groups. 2. The memory device of claim 1, wherein the selected memory cell is selected by a corresponding word line, the at least one column word line and a corresponding row word line. 3. The memory device of claim 1, wherein the plurality of column switches and the plurality of row switches are transistors. 4. The memory device of claim 1, wherein the memory device comprises a plurality of the memory units arranged along the first direction, a predetermined number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the column switches of corresponding memory blocks respectively. 5. The memory device of claim 1, wherein in the at least one memory unit, the plurality of memory cell groups arranged along the second direction are electrically isolated from each other by the plurality of row switches. 6. A memory device, comprising:
a plurality of word lines elongated along a first direction; and at least one memory unit comprising:
a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells;
at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell;
at least one column word line elongated along the second direction; and
a plurality of column switches arranged along the second direction, each of the column switches having a control terminal coupled to the at least one column word line, a first terminal coupled to one of the memory cell groups, and a second terminal coupled to the at least one bit line, each of the column switches configured to control conduction between the at least one bit line and one of the memory cell groups;
wherein a plurality of the memory units are arranged along the first direction, a predetermined number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the column switches of corresponding memory blocks respectively. 7. The memory device of claim 6, wherein the selected memory cell is selected by a corresponding word line, the at least one column word line and a corresponding row word line. 8. The memory device of claim 6, wherein the plurality of column switches and the plurality of row switches are transistors. 9. The memory device of claim 6, wherein the at least one memory unit further comprises:
a plurality of row word lines elongated along the first direction; and a plurality of row switches arranged along the second direction, each of the row switches having a control terminal coupled to a corresponding row word line; wherein each of the row switches and a corresponding column switch are coupled between one of the memory cell groups and the at least one bit line in series; wherein in the at least one memory unit, the plurality of memory cell groups arranged along the second direction are electrically isolated from each other by the plurality of row switches. 10. A memory device, comprising:
a plurality of word lines elongated along a first direction; and at least one memory unit comprising:
a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells;
at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell;
at least one column word line elongated along the second direction;
a plurality of row word lines elongated along the first direction;
wherein the selected memory cell is selected by a corresponding word line, the at least one column word line and a corresponding row word line. | 2,800 |
11,879 | 11,879 | 15,434,900 | 2,855 | A force measuring system for devices comprising: (a) a tortuous conduit operatively coupled to a transducer; and, (b) a computer communicatively coupled to the transducer, the computer programmed to utilize signals output from the transducer to calculate forces acting on the transducer, the computer programmed to support a graphical user interface for displaying the calculated forces. | 1. An force measuring system comprising:
a tortuous conduit operatively coupled to a transducer; and, a computer communicatively coupled to the transducer, the computer programmed to utilize signals output from the transducer to calculate forces acting on the transducer, the computer programmed to support a graphical user interface for displaying the calculated forces. 2. The measuring system of claim 1, wherein the transducer comprises a load cell. 3. The measuring system of claim 1, wherein:
a first portion of the transducer is mounted to a base; and, a second portion of the transducer is mounted to a sled repositionably mounted to the base. 4. The measuring system of claim 3, wherein:
the tortuous conduit is removably mounted to the sled; and, the sled includes a pair of upstanding arms that cooperatively engage a retention cap to selectively mount the tortuous conduit to the sled. 5. The measuring system of claim 3, wherein the sled is at least one of pivotally repositionable and slidably repositionable with respect to the base. 6. The measuring system of claim 5, wherein:
the sled is pivotally repositionable with respect to the base; and, a lever operatively couples the sled and the base and provides for the sled to pivot with respect to the base. 7. The measuring system of claim 6, wherein the lever comprises a plurality of levers. 8. The measuring system of claim 6, wherein:
at least one of the sled and the base includes a cavity into which the lever is at least partially inserted; the lever includes a pair of hollowed areas configured to receive cylindrical pins; the sled includes a sled opening sized to receive a first one of the cylindrical pins; and, the base includes a base opening sized to receive a second one of the cylindrical pins. 9. The measuring system of claim 5, wherein:
the sled is slidably repositionable with respect to the stationary base; and, a slide operatively couples the sled and the stationary base and provides for the sled to slide with respect to the stationary base. 10. A process for comparing at least one of insertion and withdrawal forces associated with at least two devices, the process comprising:
inserting a first device into a tortuous conduit; recording insertion data indicative of insertion forces applied to the first device traveling in a first direction in the tortuous conduit; withdrawing the first device from the tortuous conduit; recording withdrawal data indicative of withdrawal forces applied to the first device traveling in a second direction in the tortuous conduit, where the second direction is generally opposite the first direction; repeating the foregoing steps by replacing the first device with a second device; and, comparing the insertion data and withdrawal data between at least the first and second devices. 11. The process of claim 10, wherein:
the tortuous conduit is rigidly mounted to a load cell; the load cell is configured to output signals having a magnitude proportional to a force applied to the tortuous conduit; and, the load cell is communicatively coupled to a programmed computer utilizing the signals and calculating the insertion forces and calculating the withdrawal forces. 12. The process of claim 11, wherein:
the programmed computer supports a graphical user interface; and, the graphical user interface displays the insertion forces and the withdrawal forces. 13. The process of claim 12, wherein:
the insertion forces include a maximum insertion force; the withdrawal forces include a maximum withdrawal force; the graphical user interface displays the maximum insertion force and the maximum insertion force as part of a graph depicting force as a function of time; and, the graphical user interface displays a separate graph for the first medical device and a second medical device. 14. The process of claim 13, wherein:
the graphical user interface also displays the maximum insertion force separate from the graph; the graphical user interface also displays the maximum withdrawal force separate from the graph; and, the graphical user interface displays a separate reading for the maximum withdrawal force and the maximum insertion force for the first medical device and a second medical device. 15. The process of claim 13, wherein:
the insertion forces are displayed on the graphical user interface in real-time; and, the withdrawal forces are displayed on the graphical user interface in real-time. 16. The process of claim 12, wherein:
the graphical user interface includes a button to be clicked for initiating recordation of the insertion data; and, the graphical user interface includes a button to be clicked for concluding recordation of the withdrawal data. 17. The process of claim 16, wherein the button initiating recordation of the insertion data is the same as the button concluding recordation of the withdrawal data. 18. The process of claim 16, wherein graphical user interface includes a separate button initiating recordation of the insertion data for first device and a separate button for concluding recordation of the withdrawal data for the second device. 19. The process of claim 10, wherein the tortuous conduit is representative of a bodily conduit the first and second devices would traverse when used during a medical procedure. 20. The process of claim 10, wherein the first and second devices comprise a first catheter and a second catheter. 21.-31. (canceled) | A force measuring system for devices comprising: (a) a tortuous conduit operatively coupled to a transducer; and, (b) a computer communicatively coupled to the transducer, the computer programmed to utilize signals output from the transducer to calculate forces acting on the transducer, the computer programmed to support a graphical user interface for displaying the calculated forces.1. An force measuring system comprising:
a tortuous conduit operatively coupled to a transducer; and, a computer communicatively coupled to the transducer, the computer programmed to utilize signals output from the transducer to calculate forces acting on the transducer, the computer programmed to support a graphical user interface for displaying the calculated forces. 2. The measuring system of claim 1, wherein the transducer comprises a load cell. 3. The measuring system of claim 1, wherein:
a first portion of the transducer is mounted to a base; and, a second portion of the transducer is mounted to a sled repositionably mounted to the base. 4. The measuring system of claim 3, wherein:
the tortuous conduit is removably mounted to the sled; and, the sled includes a pair of upstanding arms that cooperatively engage a retention cap to selectively mount the tortuous conduit to the sled. 5. The measuring system of claim 3, wherein the sled is at least one of pivotally repositionable and slidably repositionable with respect to the base. 6. The measuring system of claim 5, wherein:
the sled is pivotally repositionable with respect to the base; and, a lever operatively couples the sled and the base and provides for the sled to pivot with respect to the base. 7. The measuring system of claim 6, wherein the lever comprises a plurality of levers. 8. The measuring system of claim 6, wherein:
at least one of the sled and the base includes a cavity into which the lever is at least partially inserted; the lever includes a pair of hollowed areas configured to receive cylindrical pins; the sled includes a sled opening sized to receive a first one of the cylindrical pins; and, the base includes a base opening sized to receive a second one of the cylindrical pins. 9. The measuring system of claim 5, wherein:
the sled is slidably repositionable with respect to the stationary base; and, a slide operatively couples the sled and the stationary base and provides for the sled to slide with respect to the stationary base. 10. A process for comparing at least one of insertion and withdrawal forces associated with at least two devices, the process comprising:
inserting a first device into a tortuous conduit; recording insertion data indicative of insertion forces applied to the first device traveling in a first direction in the tortuous conduit; withdrawing the first device from the tortuous conduit; recording withdrawal data indicative of withdrawal forces applied to the first device traveling in a second direction in the tortuous conduit, where the second direction is generally opposite the first direction; repeating the foregoing steps by replacing the first device with a second device; and, comparing the insertion data and withdrawal data between at least the first and second devices. 11. The process of claim 10, wherein:
the tortuous conduit is rigidly mounted to a load cell; the load cell is configured to output signals having a magnitude proportional to a force applied to the tortuous conduit; and, the load cell is communicatively coupled to a programmed computer utilizing the signals and calculating the insertion forces and calculating the withdrawal forces. 12. The process of claim 11, wherein:
the programmed computer supports a graphical user interface; and, the graphical user interface displays the insertion forces and the withdrawal forces. 13. The process of claim 12, wherein:
the insertion forces include a maximum insertion force; the withdrawal forces include a maximum withdrawal force; the graphical user interface displays the maximum insertion force and the maximum insertion force as part of a graph depicting force as a function of time; and, the graphical user interface displays a separate graph for the first medical device and a second medical device. 14. The process of claim 13, wherein:
the graphical user interface also displays the maximum insertion force separate from the graph; the graphical user interface also displays the maximum withdrawal force separate from the graph; and, the graphical user interface displays a separate reading for the maximum withdrawal force and the maximum insertion force for the first medical device and a second medical device. 15. The process of claim 13, wherein:
the insertion forces are displayed on the graphical user interface in real-time; and, the withdrawal forces are displayed on the graphical user interface in real-time. 16. The process of claim 12, wherein:
the graphical user interface includes a button to be clicked for initiating recordation of the insertion data; and, the graphical user interface includes a button to be clicked for concluding recordation of the withdrawal data. 17. The process of claim 16, wherein the button initiating recordation of the insertion data is the same as the button concluding recordation of the withdrawal data. 18. The process of claim 16, wherein graphical user interface includes a separate button initiating recordation of the insertion data for first device and a separate button for concluding recordation of the withdrawal data for the second device. 19. The process of claim 10, wherein the tortuous conduit is representative of a bodily conduit the first and second devices would traverse when used during a medical procedure. 20. The process of claim 10, wherein the first and second devices comprise a first catheter and a second catheter. 21.-31. (canceled) | 2,800 |
11,880 | 11,880 | 15,361,121 | 2,822 | A semiconductor device includes a semiconductor substrate and at least one perovskite layer disposed on the substrate. The semiconductor substrate includes a single-crystal semiconductor and the at least one perovskite layer includes a single-crystal organometallic-halide ionic solid perovskite. | 1. A semiconductor device, comprising:
a substrate comprising a single-crystal semiconductor; and at least one perovskite layer disposed on the substrate, wherein the at least one perovskite layer comprises a single-crystal organometallic-halide ionic solid perovskite disposed on the substrate. 2. The semiconductor device of claim 1 further comprising a first electrical contact and a second electrical contact to be in electrical communication with the substrate, the at least one perovskite layer, or both. 3. The semiconductor device of claim 1, wherein single-crystal organometallic-halide ionic solid perovskite comprises an epitaxially grown single crystal. 4. The semiconductor device of claim 3 further comprising a lattice mismatch of about 5% or less between a crystal structure of the single-crystal semiconductor and a crystal structure of the single-crystal organometallic-halide ionic solid perovskite. 5. The semiconductor device of claim 1, wherein the at least one perovskite layer comprises a thickness of equal to or less than about 10 microns. 6. The semiconductor device of claim 1, wherein the single-crystal organometallic halide ionic solid perovskite is represented by the formula, ABX3, where A comprises methylammonium (MA), formamidine (FA), cesium (Cs), rubidium (Rb), or a combination thereof; B comprises Pb, Sn, or a combination thereof; and X comprises a halide such as Cl, Br, I, or a combinations thereof. 7. The semiconductor device of claim 1, wherein the single-crystal organometallic halide ionic solid perovskite comprises methylammonium lead iodide (CH3NH3PbI3). 8. The semiconductor device of claim 1, wherein the substrate comprises a group III-V semiconductor, a group II-VI semiconductor, a group IV-VI semiconductor, or a group IV semiconductor. 9. The semiconductor device of claim 8, wherein the group III-V semiconductor comprises GaInP, GaAs, InGaAs, InAs, InP, or mixtures thereof. 10. The semiconductor device of claim 9, wherein a top surface of substrate is group-III terminated. 11. The semiconductor device of claim 9, wherein a top surface of the substrate is group-V terminated. 12. The semiconductor device of claim 8, wherein the group II-VI comprises ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, HgSe, HgTe, or mixtures thereof 13. The semiconductor device of claim 12, wherein a top surface of the substrate is group-II terminated. 14. The semiconductor device of claim 12, wherein a top surface of the substrate is group-VI terminated. 15. The semiconductor device of claim 8, wherein the group IV semiconductor comprises C, Si, Ge, Sn, or mixtures thereof. 16. The semiconductor device of claim 1, wherein the substrate comprises a cubic crystal lattice and the single-crystal organometallic-halide ionic solid perovskite comprises a quasi-cubic crystal lattice. 17. The semiconductor device of claim 16, wherein a unit cell of the single-crystal organometallic-halide ionic solid perovskite's quasi-cubic crystal lattice is rotated 45-degrees in plane from a unit cell of the substrate's cubic crystal lattice. 18. The semiconductor device of claim 1, wherein the single-crystal semiconductor comprises a first organometallic-halide ionic solid perovskite, the at least one perovskite layer comprises a second organometallic-halide ionic solid perovskite, and wherein the first organometallic-halide ionic solid perovskite is different than the second organometallic-halide ionic solid perovskite. 19. A method for making a semiconductor device, comprising:
forming at least one perovskite layer on a substrate, wherein the substrate comprises a single-crystal semiconductor and wherein the at least one perovskite layer comprises a single-crystal organometallic-halide ionic solid perovskite; and forming a first electrical contact in electrical communication with the substrate, the at least one perovskite layer or both; and forming a second electrical contact in electrical communication with the substrate, the at least one perovskite layer, or both. 20. The method of claim 19, wherein the forming of the at least one perovskite layer comprises epitaxially growing the at least one perovskite layer. 21. The method of claim 20, wherein the epitaxially growing comprises forming a lattice mismatch of about 5% or less between a crystal structure of the single-crystal semiconductor and a crystal structure of the single-crystal organometallic-halide ionic solid perovskite. 22. The method of claim 19, wherein the substrate comprises a cubic crystal lattice and wherein the organometallic-halide ionic solid perovskite semiconductor comprises a quasi-cubic crystal lattice. 23. The method of claim 19, wherein the substrate comprises a cubic crystal lattice defining a unit cell, wherein the at least one perovskite layer comprises a quasi-cubic crystal lattice defining a unit cell, and wherein the unit cell of the organometallic-halide ionic solid perovskite semiconductor's cubic crystal lattice is rotated 45-degrees in-plane from the unit cell of the semiconductor substrate's cubic crystal lattice. | A semiconductor device includes a semiconductor substrate and at least one perovskite layer disposed on the substrate. The semiconductor substrate includes a single-crystal semiconductor and the at least one perovskite layer includes a single-crystal organometallic-halide ionic solid perovskite.1. A semiconductor device, comprising:
a substrate comprising a single-crystal semiconductor; and at least one perovskite layer disposed on the substrate, wherein the at least one perovskite layer comprises a single-crystal organometallic-halide ionic solid perovskite disposed on the substrate. 2. The semiconductor device of claim 1 further comprising a first electrical contact and a second electrical contact to be in electrical communication with the substrate, the at least one perovskite layer, or both. 3. The semiconductor device of claim 1, wherein single-crystal organometallic-halide ionic solid perovskite comprises an epitaxially grown single crystal. 4. The semiconductor device of claim 3 further comprising a lattice mismatch of about 5% or less between a crystal structure of the single-crystal semiconductor and a crystal structure of the single-crystal organometallic-halide ionic solid perovskite. 5. The semiconductor device of claim 1, wherein the at least one perovskite layer comprises a thickness of equal to or less than about 10 microns. 6. The semiconductor device of claim 1, wherein the single-crystal organometallic halide ionic solid perovskite is represented by the formula, ABX3, where A comprises methylammonium (MA), formamidine (FA), cesium (Cs), rubidium (Rb), or a combination thereof; B comprises Pb, Sn, or a combination thereof; and X comprises a halide such as Cl, Br, I, or a combinations thereof. 7. The semiconductor device of claim 1, wherein the single-crystal organometallic halide ionic solid perovskite comprises methylammonium lead iodide (CH3NH3PbI3). 8. The semiconductor device of claim 1, wherein the substrate comprises a group III-V semiconductor, a group II-VI semiconductor, a group IV-VI semiconductor, or a group IV semiconductor. 9. The semiconductor device of claim 8, wherein the group III-V semiconductor comprises GaInP, GaAs, InGaAs, InAs, InP, or mixtures thereof. 10. The semiconductor device of claim 9, wherein a top surface of substrate is group-III terminated. 11. The semiconductor device of claim 9, wherein a top surface of the substrate is group-V terminated. 12. The semiconductor device of claim 8, wherein the group II-VI comprises ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, HgSe, HgTe, or mixtures thereof 13. The semiconductor device of claim 12, wherein a top surface of the substrate is group-II terminated. 14. The semiconductor device of claim 12, wherein a top surface of the substrate is group-VI terminated. 15. The semiconductor device of claim 8, wherein the group IV semiconductor comprises C, Si, Ge, Sn, or mixtures thereof. 16. The semiconductor device of claim 1, wherein the substrate comprises a cubic crystal lattice and the single-crystal organometallic-halide ionic solid perovskite comprises a quasi-cubic crystal lattice. 17. The semiconductor device of claim 16, wherein a unit cell of the single-crystal organometallic-halide ionic solid perovskite's quasi-cubic crystal lattice is rotated 45-degrees in plane from a unit cell of the substrate's cubic crystal lattice. 18. The semiconductor device of claim 1, wherein the single-crystal semiconductor comprises a first organometallic-halide ionic solid perovskite, the at least one perovskite layer comprises a second organometallic-halide ionic solid perovskite, and wherein the first organometallic-halide ionic solid perovskite is different than the second organometallic-halide ionic solid perovskite. 19. A method for making a semiconductor device, comprising:
forming at least one perovskite layer on a substrate, wherein the substrate comprises a single-crystal semiconductor and wherein the at least one perovskite layer comprises a single-crystal organometallic-halide ionic solid perovskite; and forming a first electrical contact in electrical communication with the substrate, the at least one perovskite layer or both; and forming a second electrical contact in electrical communication with the substrate, the at least one perovskite layer, or both. 20. The method of claim 19, wherein the forming of the at least one perovskite layer comprises epitaxially growing the at least one perovskite layer. 21. The method of claim 20, wherein the epitaxially growing comprises forming a lattice mismatch of about 5% or less between a crystal structure of the single-crystal semiconductor and a crystal structure of the single-crystal organometallic-halide ionic solid perovskite. 22. The method of claim 19, wherein the substrate comprises a cubic crystal lattice and wherein the organometallic-halide ionic solid perovskite semiconductor comprises a quasi-cubic crystal lattice. 23. The method of claim 19, wherein the substrate comprises a cubic crystal lattice defining a unit cell, wherein the at least one perovskite layer comprises a quasi-cubic crystal lattice defining a unit cell, and wherein the unit cell of the organometallic-halide ionic solid perovskite semiconductor's cubic crystal lattice is rotated 45-degrees in-plane from the unit cell of the semiconductor substrate's cubic crystal lattice. | 2,800 |
11,881 | 11,881 | 15,397,409 | 2,842 | A control circuit includes an oscillator responsive to a control voltage to generate a clock signal having an associated frequency. A counter is responsive to the clock signal to generate a count signal and a comparator is responsive to the count signal and to a threshold signal to generate a comparison signal. The control circuit farther includes a delay line comprising a plurality of series coupled delay elements, each responsive to the comparison signal and to the control voltage to generate a phase shifted signal at a respective delay line output. A latch is responsive to a selected phase shifted signal to generate a control signal having edges occurring in response to edges of a signal used to set the latch and in response to the selected phase shifted signal to reset the latch. A method for generating a control signal in a control circuit is also provided. | 1. A control circuit, comprising:
an oscillator responsive to a control voltage to generate a clock signal having an associated frequency, wherein the frequency is related to a voltage level of the control voltage, wherein the oscillator comprises a first plurality of series coupled delay elements including a first delay element and a last delay element each coupled to receive the control voltage, wherein an output of the last delay element is directly coupled to an input of die first delay element at which the clock signal is provided; a counter responsive to the clock signal to generate a count signal; a comparator responsive to the count signal and to a threshold signal to generate a comparison signal; a delay line comprising a second plurality of series coupled delay elements and a corresponding plurality of delay line outputs, wherein each of the delay elements of the second plurality of series coupled delay elements is responsive to the comparison signal and to the control voltage to generate a phase shifted signal at a respective delay line output of the plurality of delay line outputs; a multiplexer responsive to a select signal received at a select signal input of the multiplexer and to the delay line outputs to provide a selected phase shifted signal at an output of the multiplexer; and a latch responsive to the selected phase shifted signal to generate a control signal having edges occurring in response to edges of a signal used to set the latch and in response to the selected phase shifted signal to reset the latch, wherein the signal used to set the latch is associated with the count signal. 2. The circuit of claim 1, wherein the oscillator is provided in a phase locked loop and the voltage level of the control voltage is controlled by a charge pump. 3. The circuit of claim 2, wherein the clock signal generated by the oscillator is substantially locked to a reference clock signal received at an input of the phase locked loop. 4. The circuit of claim 2, wherein the voltage level of the control voltage is adjusted such that the frequency of the clock signal is substantially equal to one system clock period for a system in which the control circuit is provided. 5. The circuit of claim 4, wherein the clock signal is a system clock signal for the system. 6. The circuit of claim 2, wherein the voltage level of the control voltage controls a delay across the delay line. 7. The circuit of claim 6, wherein the voltage level of the control voltage is adjusted to achieve a predetermined system clock period. 8. The circuit of claim 1, wherein the oscillator is a ring oscillator. 9. The circuit of claim 8, wherein the delay elements in both the ring oscillator and the delay line comprise inverters. 10. The circuit of claim 9, wherein each of the delay elements comprises two inverters. 11. The circuit of claim 8, wherein the ring oscillator and the delay line each consists of a respective number of elements, wherein a number of the elements in the delay line is a multiple of a number of the delay elements in the ring oscillator. 12. The circuit of claim 11, wherein the multiple is two. 13. The circuit of claim 1, wherein a total delay across the delay line is indirectly locked to a predetermined system clock period of the clock signal generated by the oscillator. 14. The circuit of claim 1, wherein the threshold signal is associated with most significant bits of a duty cycle signal received at an input of the control circuit. 15. The circuit of claim 1, wherein the counter counts up to most significant bits of a duty cycle signal received at an input of the control circuit to generate the count signal. 16. The circuit of claim 1, wherein the selected phase shifted signal is associated with remaining least significant bits of a duty cycle signal received at an input of the control circuit. 17. The control circuit of claim 1, wherein the control circuit is a circuit for generating a pulse width modulated (PWM) signal for a DC-DC converter. 18. The control circuit of claim 17, wherein the control circuit and the DC-DC converter are both provided in a buck regulator. 19. A control circuit, comprising:
means for generating a clock signal having an associated frequency, wherein the frequency is related to a voltage level of a control voltage; means for generating a count signal in response to the clock signal; means for comparing the count signal to a threshold signal to generate a comparison signal; means for generating a plurality of phase shifted signals in response to the comparison signal, the phase shifted signals each having an associated phase shift related to the voltage level of the control voltage, wherein the means for generating the plurality of phase shifted signals comprises a delay line including at least a first delay element and a last delay element, wherein the phase shift between each set of two consecutive phase shifted signals or the plurality of phase shifted signals is substantially the same, and wherein a total delay across the delay line between an input of the first delay element and an output of the last delay element is selected to match a clock period of the clock signal: means for selecting a phase shifted signal of the plurality of phase shifted signals in response to a select signal; and means for generating a control signal in response to the selected phase shifted signal and to a signal associated with the count signal, the control signal having edges occurring in response to edges of the signal associated with the count signal and in response to the selected phase shifted signal. 20. The circuit of claim 19, wherein the means for generating the clock signal is provided in a phase locked loop and the voltage level of the control voltage is controlled by a charge pump. 21. (canceled) 22. The circuit of claim 19, wherein the means for generating the clock signal and the means for generating the plurality of phase shifted signals each comprise a respective number of elements, wherein a number of the elements in the means for generating the plurality of phase shifted signals is a multiple of a number of the elements in the means for generating the clock signal. 23. The circuit of claim 22, wherein the multiple is two. 24. (canceled) 25. A method for generating a control signal in a control circuit, comprising:
receiving a control voltage from a voltage source; generating a clock signal having an associated frequency, wherein the frequency is related to a voltage level of the control voltage, the clock signal having a clock signal period; generating a count signal in response to the clock signal; comparing the count signal to a threshold signal to generate a comparison signal; generating a plurality of phase shifted signals, by a delay line in response to the comparison signal, the phase shifted signals each having an associated phase shift related to the voltage level of the control voltage, wherein the phase shift between each set of two consecutive phase shifted signals of the plurality of phase shifted signals is substantially the same, and wherein a total delay between an input of a first delay element of the delay line and an output of a last delay element of the delay line is selected to match the clock signal period: selecting a phase shifted signal of the plurality of phase shifted signals in response to a select signal; and generating the control signal in response to the selected phase shifted signal and to a signal associated with the count signal, the control signal having edges occurring in response to edges of the signal associated with the count signal and in response to the selected phase shifted signal. 26. (canceled) 27. The method of claim 25, further comprising adjusting the voltage level of the control voltage to control the phase shift of the phase shifted signals. 28. The control circuit of claim 1, wherein each of the first plurality of delay elements in the oscillator comprises a same type of delay element. | A control circuit includes an oscillator responsive to a control voltage to generate a clock signal having an associated frequency. A counter is responsive to the clock signal to generate a count signal and a comparator is responsive to the count signal and to a threshold signal to generate a comparison signal. The control circuit farther includes a delay line comprising a plurality of series coupled delay elements, each responsive to the comparison signal and to the control voltage to generate a phase shifted signal at a respective delay line output. A latch is responsive to a selected phase shifted signal to generate a control signal having edges occurring in response to edges of a signal used to set the latch and in response to the selected phase shifted signal to reset the latch. A method for generating a control signal in a control circuit is also provided.1. A control circuit, comprising:
an oscillator responsive to a control voltage to generate a clock signal having an associated frequency, wherein the frequency is related to a voltage level of the control voltage, wherein the oscillator comprises a first plurality of series coupled delay elements including a first delay element and a last delay element each coupled to receive the control voltage, wherein an output of the last delay element is directly coupled to an input of die first delay element at which the clock signal is provided; a counter responsive to the clock signal to generate a count signal; a comparator responsive to the count signal and to a threshold signal to generate a comparison signal; a delay line comprising a second plurality of series coupled delay elements and a corresponding plurality of delay line outputs, wherein each of the delay elements of the second plurality of series coupled delay elements is responsive to the comparison signal and to the control voltage to generate a phase shifted signal at a respective delay line output of the plurality of delay line outputs; a multiplexer responsive to a select signal received at a select signal input of the multiplexer and to the delay line outputs to provide a selected phase shifted signal at an output of the multiplexer; and a latch responsive to the selected phase shifted signal to generate a control signal having edges occurring in response to edges of a signal used to set the latch and in response to the selected phase shifted signal to reset the latch, wherein the signal used to set the latch is associated with the count signal. 2. The circuit of claim 1, wherein the oscillator is provided in a phase locked loop and the voltage level of the control voltage is controlled by a charge pump. 3. The circuit of claim 2, wherein the clock signal generated by the oscillator is substantially locked to a reference clock signal received at an input of the phase locked loop. 4. The circuit of claim 2, wherein the voltage level of the control voltage is adjusted such that the frequency of the clock signal is substantially equal to one system clock period for a system in which the control circuit is provided. 5. The circuit of claim 4, wherein the clock signal is a system clock signal for the system. 6. The circuit of claim 2, wherein the voltage level of the control voltage controls a delay across the delay line. 7. The circuit of claim 6, wherein the voltage level of the control voltage is adjusted to achieve a predetermined system clock period. 8. The circuit of claim 1, wherein the oscillator is a ring oscillator. 9. The circuit of claim 8, wherein the delay elements in both the ring oscillator and the delay line comprise inverters. 10. The circuit of claim 9, wherein each of the delay elements comprises two inverters. 11. The circuit of claim 8, wherein the ring oscillator and the delay line each consists of a respective number of elements, wherein a number of the elements in the delay line is a multiple of a number of the delay elements in the ring oscillator. 12. The circuit of claim 11, wherein the multiple is two. 13. The circuit of claim 1, wherein a total delay across the delay line is indirectly locked to a predetermined system clock period of the clock signal generated by the oscillator. 14. The circuit of claim 1, wherein the threshold signal is associated with most significant bits of a duty cycle signal received at an input of the control circuit. 15. The circuit of claim 1, wherein the counter counts up to most significant bits of a duty cycle signal received at an input of the control circuit to generate the count signal. 16. The circuit of claim 1, wherein the selected phase shifted signal is associated with remaining least significant bits of a duty cycle signal received at an input of the control circuit. 17. The control circuit of claim 1, wherein the control circuit is a circuit for generating a pulse width modulated (PWM) signal for a DC-DC converter. 18. The control circuit of claim 17, wherein the control circuit and the DC-DC converter are both provided in a buck regulator. 19. A control circuit, comprising:
means for generating a clock signal having an associated frequency, wherein the frequency is related to a voltage level of a control voltage; means for generating a count signal in response to the clock signal; means for comparing the count signal to a threshold signal to generate a comparison signal; means for generating a plurality of phase shifted signals in response to the comparison signal, the phase shifted signals each having an associated phase shift related to the voltage level of the control voltage, wherein the means for generating the plurality of phase shifted signals comprises a delay line including at least a first delay element and a last delay element, wherein the phase shift between each set of two consecutive phase shifted signals or the plurality of phase shifted signals is substantially the same, and wherein a total delay across the delay line between an input of the first delay element and an output of the last delay element is selected to match a clock period of the clock signal: means for selecting a phase shifted signal of the plurality of phase shifted signals in response to a select signal; and means for generating a control signal in response to the selected phase shifted signal and to a signal associated with the count signal, the control signal having edges occurring in response to edges of the signal associated with the count signal and in response to the selected phase shifted signal. 20. The circuit of claim 19, wherein the means for generating the clock signal is provided in a phase locked loop and the voltage level of the control voltage is controlled by a charge pump. 21. (canceled) 22. The circuit of claim 19, wherein the means for generating the clock signal and the means for generating the plurality of phase shifted signals each comprise a respective number of elements, wherein a number of the elements in the means for generating the plurality of phase shifted signals is a multiple of a number of the elements in the means for generating the clock signal. 23. The circuit of claim 22, wherein the multiple is two. 24. (canceled) 25. A method for generating a control signal in a control circuit, comprising:
receiving a control voltage from a voltage source; generating a clock signal having an associated frequency, wherein the frequency is related to a voltage level of the control voltage, the clock signal having a clock signal period; generating a count signal in response to the clock signal; comparing the count signal to a threshold signal to generate a comparison signal; generating a plurality of phase shifted signals, by a delay line in response to the comparison signal, the phase shifted signals each having an associated phase shift related to the voltage level of the control voltage, wherein the phase shift between each set of two consecutive phase shifted signals of the plurality of phase shifted signals is substantially the same, and wherein a total delay between an input of a first delay element of the delay line and an output of a last delay element of the delay line is selected to match the clock signal period: selecting a phase shifted signal of the plurality of phase shifted signals in response to a select signal; and generating the control signal in response to the selected phase shifted signal and to a signal associated with the count signal, the control signal having edges occurring in response to edges of the signal associated with the count signal and in response to the selected phase shifted signal. 26. (canceled) 27. The method of claim 25, further comprising adjusting the voltage level of the control voltage to control the phase shift of the phase shifted signals. 28. The control circuit of claim 1, wherein each of the first plurality of delay elements in the oscillator comprises a same type of delay element. | 2,800 |
11,882 | 11,882 | 15,550,164 | 2,896 | A method and system of distributed Compressed Air Energy Storage with thermal energy interchange network of cooling and heating circuits and dynamically scheduled power production, energy storage and power generation from storage, of integrated individual power resources to enhance system thermal efficiency and capacity factor. | 1. A method and system of compressed air energy storage to improve the capacity factor of distributed intermittent power sources such as wind turbines on a wind farm, comprising of:
distributing the air storage, compression and expansion to a multiplicity of storage tanks and compressor-expander trains at each wind turbine or intermittent power source, providing a thermal energy interchange network linking all the power source or turbine stations with insulated and controlled cooling and heating circuits, and includes supervisory farm level controls and distributed turbine level controls which dynamically schedule individual turbine power production and or compressed air energy storage or compressed air power production in concert with the energy farm operational objectives and optimization of thermal efficiency and capacity factor for the farm. 2. The method and system of claim 1, wherein the turbine power sources, the distributed air storage, compression and expansion systems, the thermal energy interchange network and the control systems are integrated and function as a system for demand power production at optimal thermal efficiency, with:
generated power from turbines utilized for farm power including demand power satisfaction, air compression, and driving the cooling and heating circuits, generated power from compressed air is also utilized for farm power, heat produced during air compression is captured in the heat interchange network, and heat demand during air expansion is met by the heat interchange network. 3. The method and system of claim 1, wherein a hierarchical control system includes in the farm level controls regulation of fluid flow and energy interchange in the heat network and optimization of thermal efficiency in the farm; and the operational regimes implemented by the turbine station level controls are elaborated to encompass combinations of (1) turbine operation (not run, run during wind speeds above cut-in speed and below allowable wind speed for high rotor speed, run during wind speeds above allowable wind speed for high rotor speed but below furling wind speed, and turbine shut down for safety considerations), (2) compressed air energy storage, and (3) compressed air power production. 4. The method and system of claim 1, wherein the distributed air storage, compression and expansion systems may also incorporate proven and available components and capacity improvement options of conventional compressed air energy storage and power production systems. 5. The system of claim 2, wherein the air storage, compression and expansion, comprising of the air storage tank, compressor train and expander/generator train, with their accessories, including after coolers, intercoolers, preheaters, and reheaters, flow devices, power electronics and control systems, may be incorporated within the turbine tower and support structures such as the platform, the transition piece and foundation piece. 6. The system of claim 2, wherein the heat interchange network is comprised of a network of uninsulated and insulated pipes on the sea bed or covered or buried in the sea floor, and linking the compressed air compressor intercoolers and after coolers and the compressed air expander preheaters and reheaters to constitute heating and cooling circuits, with the necessary complement headers, pumping stations, flow and pressure control devices. 7. The system of claim 2, wherein the turbine stations are linked by a network of inner-array electric power cables on the sea bed or covered or buried in the sea floor, and linking each wind turbine through its power control unit; a set of outer-array cables; a wind farm substation or switch yard; and controls and accessories to gather and transmit externally power generated by the farm. 8. The system of claim 4, wherein the reduced size air storage tanks may operate at higher pressures than feasible for large consolidated or underground formation compressed air storage. | A method and system of distributed Compressed Air Energy Storage with thermal energy interchange network of cooling and heating circuits and dynamically scheduled power production, energy storage and power generation from storage, of integrated individual power resources to enhance system thermal efficiency and capacity factor.1. A method and system of compressed air energy storage to improve the capacity factor of distributed intermittent power sources such as wind turbines on a wind farm, comprising of:
distributing the air storage, compression and expansion to a multiplicity of storage tanks and compressor-expander trains at each wind turbine or intermittent power source, providing a thermal energy interchange network linking all the power source or turbine stations with insulated and controlled cooling and heating circuits, and includes supervisory farm level controls and distributed turbine level controls which dynamically schedule individual turbine power production and or compressed air energy storage or compressed air power production in concert with the energy farm operational objectives and optimization of thermal efficiency and capacity factor for the farm. 2. The method and system of claim 1, wherein the turbine power sources, the distributed air storage, compression and expansion systems, the thermal energy interchange network and the control systems are integrated and function as a system for demand power production at optimal thermal efficiency, with:
generated power from turbines utilized for farm power including demand power satisfaction, air compression, and driving the cooling and heating circuits, generated power from compressed air is also utilized for farm power, heat produced during air compression is captured in the heat interchange network, and heat demand during air expansion is met by the heat interchange network. 3. The method and system of claim 1, wherein a hierarchical control system includes in the farm level controls regulation of fluid flow and energy interchange in the heat network and optimization of thermal efficiency in the farm; and the operational regimes implemented by the turbine station level controls are elaborated to encompass combinations of (1) turbine operation (not run, run during wind speeds above cut-in speed and below allowable wind speed for high rotor speed, run during wind speeds above allowable wind speed for high rotor speed but below furling wind speed, and turbine shut down for safety considerations), (2) compressed air energy storage, and (3) compressed air power production. 4. The method and system of claim 1, wherein the distributed air storage, compression and expansion systems may also incorporate proven and available components and capacity improvement options of conventional compressed air energy storage and power production systems. 5. The system of claim 2, wherein the air storage, compression and expansion, comprising of the air storage tank, compressor train and expander/generator train, with their accessories, including after coolers, intercoolers, preheaters, and reheaters, flow devices, power electronics and control systems, may be incorporated within the turbine tower and support structures such as the platform, the transition piece and foundation piece. 6. The system of claim 2, wherein the heat interchange network is comprised of a network of uninsulated and insulated pipes on the sea bed or covered or buried in the sea floor, and linking the compressed air compressor intercoolers and after coolers and the compressed air expander preheaters and reheaters to constitute heating and cooling circuits, with the necessary complement headers, pumping stations, flow and pressure control devices. 7. The system of claim 2, wherein the turbine stations are linked by a network of inner-array electric power cables on the sea bed or covered or buried in the sea floor, and linking each wind turbine through its power control unit; a set of outer-array cables; a wind farm substation or switch yard; and controls and accessories to gather and transmit externally power generated by the farm. 8. The system of claim 4, wherein the reduced size air storage tanks may operate at higher pressures than feasible for large consolidated or underground formation compressed air storage. | 2,800 |
11,883 | 11,883 | 15,686,990 | 2,875 | A portable light includes an elongate body, a plurality of extension poles slidably received in the body and movable out of the body between an extended position and a retracted position, a light head pivotably coupled to one of the extension poles, and a head assembly housing fixed to the body and having an opening to receive the light head when the extension poles are in the retracted position. The portable light also includes a collar positioned around a portion of the body and movable between a first position and a second position, a handle coupled to the collar for movement with the collar, and a plurality of legs pivotably coupled to the collar. The legs are collapsed against the body when the handle and the collar are in the first position and are expanded apart from the body when the handle and the collar are in the second position. | 1. A portable light comprising:
an elongate body having a first end, a second end opposite the first end, and a longitudinal axis extending through the first and second ends; a plurality of extension poles slidably received in the elongate body and being coaxial with the elongate body, the plurality of extension poles being movable out of the first end of the elongate body between an extended position and a retracted position; a light head pivotably coupled to an end of one of the plurality of extension poles; a head assembly housing fixed to the first end of the elongate body, the head assembly housing including an opening to receive the light head when the plurality of extension poles is in the retracted position, the head assembly housing also includes a stationary handle to facilitate carrying the portable light, the stationary handle defining a grip axis that is perpendicular to and offset from the longitudinal axis of the elongate body; a collar positioned around a portion of the elongate body, the collar being movable along the elongate body in a direction parallel to the longitudinal axis between a first position and a second position; a movable handle coupled to the collar for movement with the collar between the first position and the second position, the movable handle defining a grip axis that is parallel to and offset from the longitudinal axis of the elongate body; and a plurality of legs pivotably coupled to the collar, the plurality of legs being collapsed against the elongate body when the movable handle and the collar are in the first position and being expanded apart from the elongate body when the movable handle and the collar are in the second position. 2. The portable light of claim 1, wherein when in the first position the movable handle is adjacent the first end of the elongate body, and wherein when in the second position the movable handle is adjacent the second end of the elongate body. 3. The portable light of claim 1, further comprising a locking assembly including an actuator supported on the movable handle, wherein the actuator is actuatable to allow movement of the collar and the movable handle from the first position to the second position. 4. The portable light of claim 3, wherein the elongate body defines a locking recess, wherein the locking assembly further includes a locking pin coupled to the actuator and received in the locking recess, and wherein the actuator is actuatable to move the locking pin out of the locking recess. 5. The portable light of claim 3, wherein the actuator is movable along the movable handle in a direction parallel to the grip axis of the movable handle. 6. The portable light of claim 1, wherein the head assembly housing includes a user interface supported by the head assembly housing adjacent the stationary handle, and wherein the user interface is operable to control operation of the light head. 7. The portable light of claim 1, wherein the plurality of extension poles includes a first extension pole and a second extension pole, and wherein the second extension pole includes a rib that is slidably received in a groove of the first extension pole to inhibit the first and second extension poles from rotating relative to each other. 8. The portable light of claim 7, wherein the first extension pole is received in the second extension pole when in the retracted position, and wherein the light head is pivotably coupled to an end of the first extension pole. 9. The portable light of claim 8, further comprising a clamping assembly coupled to an upper end of the second extension pole, wherein the clamping assembly is movable between a clamped position to hold the first extension pole in either the extended position or the retracted position, and an unclamped position to allow relative axial movement between the first and second extension poles. 10. The portable light of claim 9, further comprising a wiper positioned between the first extension pole and the second extension pole, wherein when in the clamped position the clamping assembly radially compresses the wiper against the first extension pole. 11. The portable light of claim 1, wherein the head assembly housing defines cutaways in sidewalls of the head assembly housing to facilitate cooling the light head when the light head is received in the opening. 12. The portable light of claim 1, wherein the light head includes a plurality of light emitting diodes. 13. The portable light of claim 1, wherein the light head includes a hinge coupled to the end of one of the plurality of extension poles, and wherein the hinge allows the light head to pivot more than 180 degrees relative to the plurality of extension poles. 14. The portable light of claim 13, wherein the hinge includes two arms arranged in a U-shape, and wherein the arms are pivotably connected to the end of the one of the plurality of extension poles. 15. The portable light of claim 1, wherein each leg includes a first end hingedly coupled to the collar and a second end opposite the first end, and wherein the second end is pivoted away from the elongate body when the collar and the movable handle are moved to the second position. 16. The portable light of claim 15, wherein each leg includes an anchor hole at the second end of the leg, and wherein the anchor hole is configured to receive a fastener to secure the leg to a surface. 17. The portable light of claim 15, wherein each leg is pivotally coupled to the second end of the elongate body by a leg link. 18. The portable light of claim 17, wherein each leg link includes a pair of parallel members connected together by an offset portion, wherein the pair of parallel members define a longitudinal axis of the leg link, and wherein the offset portion extends perpendicularly from the longitudinal axis of the leg link. 19. The portable light of claim 18, wherein the elongate body defines a pair of grooves corresponding to each leg link, and wherein each pair of grooves receives the offset portion of one of the leg links. 20. The portable light of claim 1, further comprising:
a base housing positioned at the second end of the elongate body, the base housing including a battery pack interface that defines a recess; and a battery pack received in the recess. 21. A portable light comprising:
an elongate body having a first end, a second end opposite the first end, and a longitudinal axis extending through the first and second ends; a plurality of extension poles slidably received in the elongate body and being coaxial with the elongate body, the plurality of extension poles being movable out of the first end of the elongate body between an extended position and a retracted position; a light head pivotably coupled to an end of one of the plurality of extension poles; a head assembly housing fixed to the first end of the elongate body, the head assembly housing including an opening to receive the light head when the plurality of extension poles is in the retracted position; a collar positioned around a portion of the elongate body, the collar being movable along the elongate body in a direction parallel to the longitudinal axis between a first position and a second position; a handle coupled to the collar for movement with the collar between the first position and the second position; and a plurality of legs, each leg including a first end hingedly coupled to the collar and a second end opposite the first end, the second end of each leg being collapsed against the elongate body when the handle and the collar are in the first position and being expanded apart from the elongate body when the handle and the collar are in the second position, wherein each leg is pivotally coupled to the second end of the elongate body by a leg link including a pair of parallel members, wherein the elongate body defines a pair of grooves corresponding to each leg link, and wherein each pair of grooves receives a portion of one of the leg links. 22. The portable light of claim 21, wherein the pair of parallel members defines a longitudinal axis of each leg link, wherein each leg link further includes an offset portion that extends perpendicularly from the longitudinal axis and connects the pair of parallel members, and wherein the offset portion of each leg link is received in a corresponding one of the pair of grooves. 23. The portable light of claim 21, wherein each leg includes an anchor hole at the second end of the leg, and wherein the anchor hole is configured to receive a fastener to secure the leg to a surface. 24. A portable light comprising:
an elongate body having a first end, a second end opposite the first end, and a longitudinal axis extending through the first and second ends; a first extension pole and a second extension pole slidably received in the elongate body, the first extension pole and the second extension pole being movable out of the first end of the elongate body between an extended position and a retracted position, the second extension pole including a rib that is slidably received in a groove of the first extension pole to inhibit the first and second extension poles from rotating relative to each other; a clamping assembly coupled to an upper end of the second extension pole, the clamping assembly being movable between a clamped position to hold the first extension pole in either the extended position or the retracted position, and an unclamped position to allow relative axial movement between the first and second extension poles; a light head pivotably coupled to an end of the first extension pole; a head assembly housing fixed to the first end of the elongate body, the head assembly housing including an opening to receive the light head when the first and second extension poles are in the retracted position; a collar positioned around a portion of the elongate body, the collar being movable along the elongate body in a direction parallel to the longitudinal axis between a first position and a second position; a handle coupled to the collar for movement with the collar between the first position and the second position; and a plurality of legs pivotably coupled to the collar, the plurality of legs being collapsed against the elongate body when the handle and the collar are in the first position and being expanded apart from the elongate body when the handle and the collar are in the second position. 25. The portable light of claim 24, wherein the rib extends radially inward from the second extension pole. 26. The portable light of claim 24, wherein the rib extends along a length of the second extension pole, and wherein the groove extends along a length of the first extension pole. 27. A method of operating a portable light, the portable light including an elongate body, a plurality of extension poles slidably received in the elongate body and being movable between an extended position and a retracted position, a light head coupled to an end of one of the plurality of extension poles, a stationary handle fixed to the elongate body, a collar movable along the elongate body, a movable handle coupled to the collar for movement with the collar, and a plurality of legs pivotably coupled to the collar, the method comprising:
grasping the stationary handle with a first hand of a user; grasping the movable handle with a second hand of the user; depressing an actuator on the movable handle with a thumb of the second hand to unlock the collar from the elongate body; and sliding the movable handle and the collar along the elongate body away from the stationary handle to move the plurality of legs from a first position, in which the plurality of legs is collapsed against the elongate body, to a second position, in which the plurality of legs is expanded apart from the elongate body. 28. The method of claim 27, further comprising sliding the movable handle and the collar along the elongate body toward the stationary handle to move the plurality of legs from the second position to the first position. 29. The method of claim 27, further comprising extending the light head away from the elongate body by axially sliding the plurality of extension poles out of the elongate body from a retracted position to an extended position. 30. The method of claim 27, wherein the stand light includes a user interface supported adjacent the stationary handle, and further comprising actuating the user interface to control power to the light head. | A portable light includes an elongate body, a plurality of extension poles slidably received in the body and movable out of the body between an extended position and a retracted position, a light head pivotably coupled to one of the extension poles, and a head assembly housing fixed to the body and having an opening to receive the light head when the extension poles are in the retracted position. The portable light also includes a collar positioned around a portion of the body and movable between a first position and a second position, a handle coupled to the collar for movement with the collar, and a plurality of legs pivotably coupled to the collar. The legs are collapsed against the body when the handle and the collar are in the first position and are expanded apart from the body when the handle and the collar are in the second position.1. A portable light comprising:
an elongate body having a first end, a second end opposite the first end, and a longitudinal axis extending through the first and second ends; a plurality of extension poles slidably received in the elongate body and being coaxial with the elongate body, the plurality of extension poles being movable out of the first end of the elongate body between an extended position and a retracted position; a light head pivotably coupled to an end of one of the plurality of extension poles; a head assembly housing fixed to the first end of the elongate body, the head assembly housing including an opening to receive the light head when the plurality of extension poles is in the retracted position, the head assembly housing also includes a stationary handle to facilitate carrying the portable light, the stationary handle defining a grip axis that is perpendicular to and offset from the longitudinal axis of the elongate body; a collar positioned around a portion of the elongate body, the collar being movable along the elongate body in a direction parallel to the longitudinal axis between a first position and a second position; a movable handle coupled to the collar for movement with the collar between the first position and the second position, the movable handle defining a grip axis that is parallel to and offset from the longitudinal axis of the elongate body; and a plurality of legs pivotably coupled to the collar, the plurality of legs being collapsed against the elongate body when the movable handle and the collar are in the first position and being expanded apart from the elongate body when the movable handle and the collar are in the second position. 2. The portable light of claim 1, wherein when in the first position the movable handle is adjacent the first end of the elongate body, and wherein when in the second position the movable handle is adjacent the second end of the elongate body. 3. The portable light of claim 1, further comprising a locking assembly including an actuator supported on the movable handle, wherein the actuator is actuatable to allow movement of the collar and the movable handle from the first position to the second position. 4. The portable light of claim 3, wherein the elongate body defines a locking recess, wherein the locking assembly further includes a locking pin coupled to the actuator and received in the locking recess, and wherein the actuator is actuatable to move the locking pin out of the locking recess. 5. The portable light of claim 3, wherein the actuator is movable along the movable handle in a direction parallel to the grip axis of the movable handle. 6. The portable light of claim 1, wherein the head assembly housing includes a user interface supported by the head assembly housing adjacent the stationary handle, and wherein the user interface is operable to control operation of the light head. 7. The portable light of claim 1, wherein the plurality of extension poles includes a first extension pole and a second extension pole, and wherein the second extension pole includes a rib that is slidably received in a groove of the first extension pole to inhibit the first and second extension poles from rotating relative to each other. 8. The portable light of claim 7, wherein the first extension pole is received in the second extension pole when in the retracted position, and wherein the light head is pivotably coupled to an end of the first extension pole. 9. The portable light of claim 8, further comprising a clamping assembly coupled to an upper end of the second extension pole, wherein the clamping assembly is movable between a clamped position to hold the first extension pole in either the extended position or the retracted position, and an unclamped position to allow relative axial movement between the first and second extension poles. 10. The portable light of claim 9, further comprising a wiper positioned between the first extension pole and the second extension pole, wherein when in the clamped position the clamping assembly radially compresses the wiper against the first extension pole. 11. The portable light of claim 1, wherein the head assembly housing defines cutaways in sidewalls of the head assembly housing to facilitate cooling the light head when the light head is received in the opening. 12. The portable light of claim 1, wherein the light head includes a plurality of light emitting diodes. 13. The portable light of claim 1, wherein the light head includes a hinge coupled to the end of one of the plurality of extension poles, and wherein the hinge allows the light head to pivot more than 180 degrees relative to the plurality of extension poles. 14. The portable light of claim 13, wherein the hinge includes two arms arranged in a U-shape, and wherein the arms are pivotably connected to the end of the one of the plurality of extension poles. 15. The portable light of claim 1, wherein each leg includes a first end hingedly coupled to the collar and a second end opposite the first end, and wherein the second end is pivoted away from the elongate body when the collar and the movable handle are moved to the second position. 16. The portable light of claim 15, wherein each leg includes an anchor hole at the second end of the leg, and wherein the anchor hole is configured to receive a fastener to secure the leg to a surface. 17. The portable light of claim 15, wherein each leg is pivotally coupled to the second end of the elongate body by a leg link. 18. The portable light of claim 17, wherein each leg link includes a pair of parallel members connected together by an offset portion, wherein the pair of parallel members define a longitudinal axis of the leg link, and wherein the offset portion extends perpendicularly from the longitudinal axis of the leg link. 19. The portable light of claim 18, wherein the elongate body defines a pair of grooves corresponding to each leg link, and wherein each pair of grooves receives the offset portion of one of the leg links. 20. The portable light of claim 1, further comprising:
a base housing positioned at the second end of the elongate body, the base housing including a battery pack interface that defines a recess; and a battery pack received in the recess. 21. A portable light comprising:
an elongate body having a first end, a second end opposite the first end, and a longitudinal axis extending through the first and second ends; a plurality of extension poles slidably received in the elongate body and being coaxial with the elongate body, the plurality of extension poles being movable out of the first end of the elongate body between an extended position and a retracted position; a light head pivotably coupled to an end of one of the plurality of extension poles; a head assembly housing fixed to the first end of the elongate body, the head assembly housing including an opening to receive the light head when the plurality of extension poles is in the retracted position; a collar positioned around a portion of the elongate body, the collar being movable along the elongate body in a direction parallel to the longitudinal axis between a first position and a second position; a handle coupled to the collar for movement with the collar between the first position and the second position; and a plurality of legs, each leg including a first end hingedly coupled to the collar and a second end opposite the first end, the second end of each leg being collapsed against the elongate body when the handle and the collar are in the first position and being expanded apart from the elongate body when the handle and the collar are in the second position, wherein each leg is pivotally coupled to the second end of the elongate body by a leg link including a pair of parallel members, wherein the elongate body defines a pair of grooves corresponding to each leg link, and wherein each pair of grooves receives a portion of one of the leg links. 22. The portable light of claim 21, wherein the pair of parallel members defines a longitudinal axis of each leg link, wherein each leg link further includes an offset portion that extends perpendicularly from the longitudinal axis and connects the pair of parallel members, and wherein the offset portion of each leg link is received in a corresponding one of the pair of grooves. 23. The portable light of claim 21, wherein each leg includes an anchor hole at the second end of the leg, and wherein the anchor hole is configured to receive a fastener to secure the leg to a surface. 24. A portable light comprising:
an elongate body having a first end, a second end opposite the first end, and a longitudinal axis extending through the first and second ends; a first extension pole and a second extension pole slidably received in the elongate body, the first extension pole and the second extension pole being movable out of the first end of the elongate body between an extended position and a retracted position, the second extension pole including a rib that is slidably received in a groove of the first extension pole to inhibit the first and second extension poles from rotating relative to each other; a clamping assembly coupled to an upper end of the second extension pole, the clamping assembly being movable between a clamped position to hold the first extension pole in either the extended position or the retracted position, and an unclamped position to allow relative axial movement between the first and second extension poles; a light head pivotably coupled to an end of the first extension pole; a head assembly housing fixed to the first end of the elongate body, the head assembly housing including an opening to receive the light head when the first and second extension poles are in the retracted position; a collar positioned around a portion of the elongate body, the collar being movable along the elongate body in a direction parallel to the longitudinal axis between a first position and a second position; a handle coupled to the collar for movement with the collar between the first position and the second position; and a plurality of legs pivotably coupled to the collar, the plurality of legs being collapsed against the elongate body when the handle and the collar are in the first position and being expanded apart from the elongate body when the handle and the collar are in the second position. 25. The portable light of claim 24, wherein the rib extends radially inward from the second extension pole. 26. The portable light of claim 24, wherein the rib extends along a length of the second extension pole, and wherein the groove extends along a length of the first extension pole. 27. A method of operating a portable light, the portable light including an elongate body, a plurality of extension poles slidably received in the elongate body and being movable between an extended position and a retracted position, a light head coupled to an end of one of the plurality of extension poles, a stationary handle fixed to the elongate body, a collar movable along the elongate body, a movable handle coupled to the collar for movement with the collar, and a plurality of legs pivotably coupled to the collar, the method comprising:
grasping the stationary handle with a first hand of a user; grasping the movable handle with a second hand of the user; depressing an actuator on the movable handle with a thumb of the second hand to unlock the collar from the elongate body; and sliding the movable handle and the collar along the elongate body away from the stationary handle to move the plurality of legs from a first position, in which the plurality of legs is collapsed against the elongate body, to a second position, in which the plurality of legs is expanded apart from the elongate body. 28. The method of claim 27, further comprising sliding the movable handle and the collar along the elongate body toward the stationary handle to move the plurality of legs from the second position to the first position. 29. The method of claim 27, further comprising extending the light head away from the elongate body by axially sliding the plurality of extension poles out of the elongate body from a retracted position to an extended position. 30. The method of claim 27, wherein the stand light includes a user interface supported adjacent the stationary handle, and further comprising actuating the user interface to control power to the light head. | 2,800 |
11,884 | 11,884 | 14,087,416 | 2,893 | An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing. | 1. A semiconductor device comprising:
a drift layer having a first surface with an active region and a plurality of junction barrier element recesses, wherein the drift layer is doped with a doping material of a first conductivity type; a Schottky layer over the active region of the first surface to form a Schottky junction; and a plurality of first doped regions that extend into the drift layer about corresponding ones of the plurality of junction barrier element recesses wherein the plurality of first doped regions are doped with a doping material of a second conductivity type, which is opposite the first conductivity type, and form an array of junction barrier elements in the drift layer below the Schottky junction. 2. The semiconductor device of claim 1 wherein each of the plurality of junction barrier element recesses has at least one side and a bottom and each of the plurality of first doped regions extends into the drift layer about the at least one side and the bottom of a corresponding one of the plurality of junction barrier element recesses. 3. The semiconductor device of claim 1 wherein junction barrier elements in the array of junction barrier elements are separated from one another within the drift layer. 4. The semiconductor device of claim 1 wherein a depth of at least one of the plurality of junction barrier element recesses is at least 0.1 microns. 5. The semiconductor device of claim 4 wherein a width of at least one of the plurality of junction barrier element recesses is at least 0.5 microns. 6. The semiconductor device of claim 1 wherein a width of at least one of the plurality of junction barrier element recesses is at least 0.5 microns. 7. The semiconductor device of claim 1 wherein the drift layer is further associated with an edge termination region that is substantially laterally adjacent the active region and comprises an edge termination structure. 8. The semiconductor device of claim 7 wherein the edge termination structure comprises a plurality of guard rings and the first surface of the drift layer comprises a plurality of guard ring recesses such that at least some of the plurality of guard rings are second doped regions that extend into the drift layer about corresponding ones of the plurality of guard ring recesses, and the second doped regions are doped with the doping material of the second conductivity type. 9. The semiconductor device of claim 8 wherein guard rings in the plurality of guard rings are separated from each other within the drift layer. 10. The semiconductor device of claim 1 wherein the Schottky layer is formed from a low barrier height capable metal. 11. The semiconductor device of claim 10 wherein the low barrier height capable metal of the Schottky layer comprises at least one of a group consisting of titanium, chromium, and aluminum. 12. The semiconductor device of claim 1 wherein the drift layer comprises silicon carbide. 13. The semiconductor device of claim 1 wherein the drift layer and the Schottky layer are part of a Schottky diode. 14. The semiconductor device of claim 1 wherein the drift layer and the Schottky layer are part of a silicon carbide Schottky diode. | An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing.1. A semiconductor device comprising:
a drift layer having a first surface with an active region and a plurality of junction barrier element recesses, wherein the drift layer is doped with a doping material of a first conductivity type; a Schottky layer over the active region of the first surface to form a Schottky junction; and a plurality of first doped regions that extend into the drift layer about corresponding ones of the plurality of junction barrier element recesses wherein the plurality of first doped regions are doped with a doping material of a second conductivity type, which is opposite the first conductivity type, and form an array of junction barrier elements in the drift layer below the Schottky junction. 2. The semiconductor device of claim 1 wherein each of the plurality of junction barrier element recesses has at least one side and a bottom and each of the plurality of first doped regions extends into the drift layer about the at least one side and the bottom of a corresponding one of the plurality of junction barrier element recesses. 3. The semiconductor device of claim 1 wherein junction barrier elements in the array of junction barrier elements are separated from one another within the drift layer. 4. The semiconductor device of claim 1 wherein a depth of at least one of the plurality of junction barrier element recesses is at least 0.1 microns. 5. The semiconductor device of claim 4 wherein a width of at least one of the plurality of junction barrier element recesses is at least 0.5 microns. 6. The semiconductor device of claim 1 wherein a width of at least one of the plurality of junction barrier element recesses is at least 0.5 microns. 7. The semiconductor device of claim 1 wherein the drift layer is further associated with an edge termination region that is substantially laterally adjacent the active region and comprises an edge termination structure. 8. The semiconductor device of claim 7 wherein the edge termination structure comprises a plurality of guard rings and the first surface of the drift layer comprises a plurality of guard ring recesses such that at least some of the plurality of guard rings are second doped regions that extend into the drift layer about corresponding ones of the plurality of guard ring recesses, and the second doped regions are doped with the doping material of the second conductivity type. 9. The semiconductor device of claim 8 wherein guard rings in the plurality of guard rings are separated from each other within the drift layer. 10. The semiconductor device of claim 1 wherein the Schottky layer is formed from a low barrier height capable metal. 11. The semiconductor device of claim 10 wherein the low barrier height capable metal of the Schottky layer comprises at least one of a group consisting of titanium, chromium, and aluminum. 12. The semiconductor device of claim 1 wherein the drift layer comprises silicon carbide. 13. The semiconductor device of claim 1 wherein the drift layer and the Schottky layer are part of a Schottky diode. 14. The semiconductor device of claim 1 wherein the drift layer and the Schottky layer are part of a silicon carbide Schottky diode. | 2,800 |
11,885 | 11,885 | 15,329,401 | 2,853 | A method of preparing a printer cartridge for transport may comprise applying a volume of immiscible fluid to a nozzle bore of a printhead. A printer cartridge may comprise a volume of immiscible fluid deposited into a nozzle bore of a nozzle of the printhead and a layer of immiscible fluid applied over the nozzle bore opening. A printhead die may comprise a volume of immiscible fluid deposited into a nozzle bore of the die and a layer of immiscible fluid applied over the nozzle bore opening. | 1. A method of preparing a printer cartridge for transport, comprising:
applying a volume of immiscible fluid to a nozzle bore of a printhead. 2. The method of claim 1, comprising applying a volume of immiscible fluid into a nozzle bore of a printhead and applying a layer of immiscible fluid over the nozzle bore opening. 3. The method of claim 1, in which the immiscible fluid is an isoparaffin. 3. The method of claim 1, in which the in which the immiscible fluid has a density of 0.6 to 1.2 g/cm3. 4. The method of claim 1, in which the immiscible fluid has a molecular weight of 130 to 300 g/mol. 5. The method of claim 1, in which the immiscible fluid has a viscosity of 0.8 to 5 centipoise. 6. The method of claim 1, in which the immiscible fluid is water soluble to 200 ppm at a water temperature of 20° C. 7. The method of claim 1, in which the immiscible fluid has a surface tension of 18 to 35 mN/m. 8. A printhead comprising:
a volume of immiscible fluid deposited into a nozzle bore of a nozzle of the printhead; and a layer of immiscible fluid applied over the nozzle bore opening. 9. The printhead of claim 8, in which the immiscible fluid has a viscosity of 0.8 to 5 centipoise. 10. The printhead of claim 8, in which the in which the immiscible fluid has a density of 0.6 to 1.2 g/cm3. 11. The printhead of claim 8, in which the miscible fluid has a surface tension of 18 to 35 mN/m. 12. The printhead of claim 8, in which the immiscible fluid has a molecular weight of 130 to 300 g/mol. 13. The printhead of claim 8, in which the immiscible fluid has a surface tension of 18 to 35 mN/m. 14. A printhead die comprising:
a volume of immiscible fluid deposited into a nozzle bore of the die; and a layer of immiscible fluid applied over the nozzle bore opening. 15. The printhead die of claim 14, in which the immiscible fluid is an isoparaffin. | A method of preparing a printer cartridge for transport may comprise applying a volume of immiscible fluid to a nozzle bore of a printhead. A printer cartridge may comprise a volume of immiscible fluid deposited into a nozzle bore of a nozzle of the printhead and a layer of immiscible fluid applied over the nozzle bore opening. A printhead die may comprise a volume of immiscible fluid deposited into a nozzle bore of the die and a layer of immiscible fluid applied over the nozzle bore opening.1. A method of preparing a printer cartridge for transport, comprising:
applying a volume of immiscible fluid to a nozzle bore of a printhead. 2. The method of claim 1, comprising applying a volume of immiscible fluid into a nozzle bore of a printhead and applying a layer of immiscible fluid over the nozzle bore opening. 3. The method of claim 1, in which the immiscible fluid is an isoparaffin. 3. The method of claim 1, in which the in which the immiscible fluid has a density of 0.6 to 1.2 g/cm3. 4. The method of claim 1, in which the immiscible fluid has a molecular weight of 130 to 300 g/mol. 5. The method of claim 1, in which the immiscible fluid has a viscosity of 0.8 to 5 centipoise. 6. The method of claim 1, in which the immiscible fluid is water soluble to 200 ppm at a water temperature of 20° C. 7. The method of claim 1, in which the immiscible fluid has a surface tension of 18 to 35 mN/m. 8. A printhead comprising:
a volume of immiscible fluid deposited into a nozzle bore of a nozzle of the printhead; and a layer of immiscible fluid applied over the nozzle bore opening. 9. The printhead of claim 8, in which the immiscible fluid has a viscosity of 0.8 to 5 centipoise. 10. The printhead of claim 8, in which the in which the immiscible fluid has a density of 0.6 to 1.2 g/cm3. 11. The printhead of claim 8, in which the miscible fluid has a surface tension of 18 to 35 mN/m. 12. The printhead of claim 8, in which the immiscible fluid has a molecular weight of 130 to 300 g/mol. 13. The printhead of claim 8, in which the immiscible fluid has a surface tension of 18 to 35 mN/m. 14. A printhead die comprising:
a volume of immiscible fluid deposited into a nozzle bore of the die; and a layer of immiscible fluid applied over the nozzle bore opening. 15. The printhead die of claim 14, in which the immiscible fluid is an isoparaffin. | 2,800 |
11,886 | 11,886 | 15,914,905 | 2,841 | Secure IoT devices and methods of use are disclosed herein. An example Internet-of-Things (IoT) device includes an interface for transmitting and receiving data on a network; and a chip comprising a reconfigurable hardware core configured to transmit the data using the interface. The reconfigurable hardware core is not vulnerable to malicious attacks can be used to replace a central processing unit (CPU) which is vulnerable to malicious attacks. | 1. An Internet-of-Things (IoT) device, comprising:
an interface for transmitting and receiving data on a network; and a chip comprising a reconfigurable hardware core configured to transmit the data using the interface, the reconfigurable hardware core being reconfigurable by:
physically removing the chip from the IoT device;
upon removal of the chip, coupling the chip to an off-chip memory module;
receiving, by the reconfigurable hardware core, from the off-chip memory module, instructions to be stored on the reconfigurable hardware core to reconfigure the reconfigurable hardware core;
decoupling the chip with the reconfigured hardware core from the off-chip memory module; and
physically inserting the chip with the reconfigured hardware core into the IoT device. 2. The IoT device according to claim 1, further comprising a chip receiver that receives the chip, wherein at least a portion of the circuitry of the chip is releasably removable from the chip receiver. 3. The IoT device according to claim 2, further comprising a housing, wherein the housing comprises a slot that aligns with the chip receiver, the chip being inserted through the slot into the chip receiver. 4. The IoT device according to claim 1, wherein the reconfigurable hardware core is a field programmable gate array (FGPA). 5. The IoT device according to claim 1, wherein the reconfigurable hardware core is not a central processing unit or other von Neumann architecture device. 6. An integrated circuit, comprising:
a reconfigurable hardware core; an input/output interface; a power management interface; and a configuration memory module. 7. The integrated circuit according to claim 6, further comprising an off-chip memory module coupled to the input/output interface that provide instructions that cause the reconfigurable hardware core to perform one or more functionalities. 8. The integrated circuit according to claim 7, further comprising one or more sub-devices that couple to the input/output interface, wherein the integrated circuit controls the one or more sub-devices. 9. The integrated circuit according to claim 7, further comprising pins that couple the chip with a chip receiver of an Internet-of-Things (IoT) device. 10. A method, comprising:
removing a central processing unit and memory from an Internet-of-Things (IoT) device, the central processing unit and memory providing one or more functionalities; and replacing the central processing unit and memory with an integrated circuit comprising a reconfigurable hardware core configured to provide the one or more functionalities. 11. The method according to claim 10, further comprising controlling one or more sub-devices that are coupled to an input/output interface of the integrated circuit. 12. The method according to claim 11, further comprising receiving instructions from an off-chip memory module coupled to the input/output interface of the integrated circuit, the off-chip memory module causing the reconfigurable hardware core to perform one or more functionalities. | Secure IoT devices and methods of use are disclosed herein. An example Internet-of-Things (IoT) device includes an interface for transmitting and receiving data on a network; and a chip comprising a reconfigurable hardware core configured to transmit the data using the interface. The reconfigurable hardware core is not vulnerable to malicious attacks can be used to replace a central processing unit (CPU) which is vulnerable to malicious attacks.1. An Internet-of-Things (IoT) device, comprising:
an interface for transmitting and receiving data on a network; and a chip comprising a reconfigurable hardware core configured to transmit the data using the interface, the reconfigurable hardware core being reconfigurable by:
physically removing the chip from the IoT device;
upon removal of the chip, coupling the chip to an off-chip memory module;
receiving, by the reconfigurable hardware core, from the off-chip memory module, instructions to be stored on the reconfigurable hardware core to reconfigure the reconfigurable hardware core;
decoupling the chip with the reconfigured hardware core from the off-chip memory module; and
physically inserting the chip with the reconfigured hardware core into the IoT device. 2. The IoT device according to claim 1, further comprising a chip receiver that receives the chip, wherein at least a portion of the circuitry of the chip is releasably removable from the chip receiver. 3. The IoT device according to claim 2, further comprising a housing, wherein the housing comprises a slot that aligns with the chip receiver, the chip being inserted through the slot into the chip receiver. 4. The IoT device according to claim 1, wherein the reconfigurable hardware core is a field programmable gate array (FGPA). 5. The IoT device according to claim 1, wherein the reconfigurable hardware core is not a central processing unit or other von Neumann architecture device. 6. An integrated circuit, comprising:
a reconfigurable hardware core; an input/output interface; a power management interface; and a configuration memory module. 7. The integrated circuit according to claim 6, further comprising an off-chip memory module coupled to the input/output interface that provide instructions that cause the reconfigurable hardware core to perform one or more functionalities. 8. The integrated circuit according to claim 7, further comprising one or more sub-devices that couple to the input/output interface, wherein the integrated circuit controls the one or more sub-devices. 9. The integrated circuit according to claim 7, further comprising pins that couple the chip with a chip receiver of an Internet-of-Things (IoT) device. 10. A method, comprising:
removing a central processing unit and memory from an Internet-of-Things (IoT) device, the central processing unit and memory providing one or more functionalities; and replacing the central processing unit and memory with an integrated circuit comprising a reconfigurable hardware core configured to provide the one or more functionalities. 11. The method according to claim 10, further comprising controlling one or more sub-devices that are coupled to an input/output interface of the integrated circuit. 12. The method according to claim 11, further comprising receiving instructions from an off-chip memory module coupled to the input/output interface of the integrated circuit, the off-chip memory module causing the reconfigurable hardware core to perform one or more functionalities. | 2,800 |
11,887 | 11,887 | 15,354,137 | 2,822 | The surface of a substrate of a first material is modified by depositing a layer of a solvent paste comprising nanoparticles of a second material that have a size that provides a melting point at a lower temperature than the melting point temperature of the bulk second material, and nanoparticles of a third material that have a size at least as large as the nanoparticle size of the second material and a melting point at a temperature higher than the melting point temperature of the second material. Nanoparticles of the second material have a higher weight percentage than nanoparticles of the third material. The nanoparticles of the second material are sintered together at the melting point temperature of the second material. Voids are created in the layer of second material by removing the nanoparticles of the third material The voids have random distribution and random three-dimensional configurations. | 1. A device comprising:
a substrate of a first material; a diffusion region at a surface of the substrate, the diffusion region including an admixture of a second material in the first material; a sintered structure adjoining the surface of the substrate, the sintered structure including; sintered nanoparticles of the second material; and a polymeric compound filling voids having random distribution and random three-dimensional configurations within the sintered structure; the nanoparticles of the second material having a first size, a first weight percentage and a first melting point temperature lower than a melting point temperature of the sintered structure; and the voids resulting from a removal of nanoparticles of a third material from within the sintered structure; the nanoparticles of the third material having a second size at least as large as the first size, a second weight percentage smaller than the first weight percentage, and a second melting point temperature higher than the first melting point temperature. 2. The device of claim 1, wherein some of the voids have a substantially spherical shape and entrances. 3. The device of claim 1, wherein the substrate is a metallic leadframe. 4. The device of claim 3, wherein the metallic leadframe includes a base metal and metal layers plated on the base metal. 5. The device of claim 3, wherein a semiconductor chip is mounted on the metallic leadframe and covered by the polymeric compound. 6. The device of claim 1, wherein the second material is selected from a group including metals, metal oxides, oxides, and ceramics. 7. A method for substrate modification, the method comprising:
providing a substrate of a first material; additively depositing a layer of a solvent paste on a surface of the substrate, the solvent paste comprising:
nanoparticles of a second material with a first weight percentage, the nanoparticles of the second material having a size that creates a melting point at a lower temperature than a melting point temperature of a bulk second material; and
nanoparticles of a third material with a second weight percentage smaller than the first weight percentage, the nanoparticles of the third material having a size at least as large as the nanoparticle size of the second material and a melting point at a temperature higher than the melting point temperature of the nanoparticles of the second material;
sintering together the nanoparticles of the second material at the melting point temperature of the second material, wherein a sintered structure surrounds the nanoparticles of the third material; and creating voids in the sintered structure by removing the nanoparticles of the third material; wherein the voids have random distribution and random three-dimensional configurations. 8. The method of claim 7, wherein the substrate is selected from a group including metallic substrates, metallic leadframes, and laminated substrates including metallic layers alternating with insulating layers. 9. The method of claim 8, wherein the first material is selected from a group including copper, copper alloys, aluminum, aluminum alloys, iron-nickel alloys, and Kovar™. 10. The method of claim 9, wherein the first material includes a plated layer of a metal selected from a group including tin, silver, nickel, palladium, and gold. 11. The method of claim 7, wherein a method of additively depositing is selected from a group including screen printing, flexographic printing, gravure printing, dip coating, spray coating, and inkjet printing comprising piezoelectric, thermal, acoustic, and electrostatic inkjet printing. 12. The method of claim 7, wherein the second material is selected from a group including metals, metal oxides, oxides, and ceramics. 13. The method of claim 12, wherein a size of the nanoparticles of the second material is in the range from about 10 nm to 20 nm. 14. The method of claim 7, wherein the third material is selected from a group including polymers, oxides, ceramics, metals, and metal oxides. 15. The method of claim 7, wherein an energy for sintering the second nanoparticles is selected from a group including thermal energy, photonic energy, electromagnetic energy, and chemical energy. 16. The method of claim 7, wherein a method of removing the third nanoparticles is selected from a group including heating, vapor etching, and liquid phase etching. 17. The method of claim 7, wherein some of the voids have a substantially spherical shape and narrow entrances. 18. A method for enhancing adhesion of packaged semiconductor device % the method comprising:
providing a substrate of a first material; providing a solvent paste including nanoparticles of a second material with a first weight percentage, and nanoparticles of a third material with a second weight percentage smaller than the first weight percentage; wherein the nanoparticles of the second material have a size that provides a melting point at a lower temperature than a melting point temperature of a bulk second material, and the nanoparticles of the third material have a size at least as large as the nanoparticle size of the second material and a melting point at a temperature higher than the melting point temperature of the nanoparticles of the second material; additively depositing a layer of the paste on a surface of the substrate; providing energy to increase temperature of the second material to a temperature above the melting point of the second material; sintering together the nanoparticles of the second material into a liquid surrounding the nanoparticles of the third material, and concurrently diffusing second material into the first material of the surface of the substrate; solidifying the liquid of the second material to create a solid layer of second material surrounding the nanoparticles of the third material; creating voids in the solid layer of second material by removing the nanoparticles of the third material wherein the voids have random distribution and random three-dimensional configurations; encapsulating the solid layer of second material and the surface of the substrate in a polymeric compound, wherein the polymeric compound fills the voids in the solid layer of second material. 19. The method of claim 18, wherein the substrate is a metallic leadframe. 20. The method of claim 18, wherein the second material is selected from a group including metals, metal oxides, oxides, and ceramics. 21. The method of claim 20, wherein a size of the nanoparticles of the second material is in the range from about 10 nm to 20 nm. 22. The method of claim 18, wherein the third material is selected from a group including polymers, oxides, ceramics, metals, and metal oxides. 23. The method of claim 18, wherein a method of additively depositing is selected from a group including screen printing, flexographic printing, gravure printing, dip coating, spray coating, and inkjet printing comprising piezoelectric, thermal, acoustic, and electrostatic inkjet printing. 24. The method of claim 18, wherein a method of removing the third nanoparticles is selected from a group including heating, vapor etching, and liquid phase etching. 25. The method of claim 18, further including: before encapsulating, assembling a semiconductor circuit chip on the substrate so that the chip will be positioned inside the polymeric compound after encapsulating. 26. The device of claim 1, wherein the sintered structure consists essentially of: the sintered nanoparticles of the second material; and the polymeric compound filling the voids. | The surface of a substrate of a first material is modified by depositing a layer of a solvent paste comprising nanoparticles of a second material that have a size that provides a melting point at a lower temperature than the melting point temperature of the bulk second material, and nanoparticles of a third material that have a size at least as large as the nanoparticle size of the second material and a melting point at a temperature higher than the melting point temperature of the second material. Nanoparticles of the second material have a higher weight percentage than nanoparticles of the third material. The nanoparticles of the second material are sintered together at the melting point temperature of the second material. Voids are created in the layer of second material by removing the nanoparticles of the third material The voids have random distribution and random three-dimensional configurations.1. A device comprising:
a substrate of a first material; a diffusion region at a surface of the substrate, the diffusion region including an admixture of a second material in the first material; a sintered structure adjoining the surface of the substrate, the sintered structure including; sintered nanoparticles of the second material; and a polymeric compound filling voids having random distribution and random three-dimensional configurations within the sintered structure; the nanoparticles of the second material having a first size, a first weight percentage and a first melting point temperature lower than a melting point temperature of the sintered structure; and the voids resulting from a removal of nanoparticles of a third material from within the sintered structure; the nanoparticles of the third material having a second size at least as large as the first size, a second weight percentage smaller than the first weight percentage, and a second melting point temperature higher than the first melting point temperature. 2. The device of claim 1, wherein some of the voids have a substantially spherical shape and entrances. 3. The device of claim 1, wherein the substrate is a metallic leadframe. 4. The device of claim 3, wherein the metallic leadframe includes a base metal and metal layers plated on the base metal. 5. The device of claim 3, wherein a semiconductor chip is mounted on the metallic leadframe and covered by the polymeric compound. 6. The device of claim 1, wherein the second material is selected from a group including metals, metal oxides, oxides, and ceramics. 7. A method for substrate modification, the method comprising:
providing a substrate of a first material; additively depositing a layer of a solvent paste on a surface of the substrate, the solvent paste comprising:
nanoparticles of a second material with a first weight percentage, the nanoparticles of the second material having a size that creates a melting point at a lower temperature than a melting point temperature of a bulk second material; and
nanoparticles of a third material with a second weight percentage smaller than the first weight percentage, the nanoparticles of the third material having a size at least as large as the nanoparticle size of the second material and a melting point at a temperature higher than the melting point temperature of the nanoparticles of the second material;
sintering together the nanoparticles of the second material at the melting point temperature of the second material, wherein a sintered structure surrounds the nanoparticles of the third material; and creating voids in the sintered structure by removing the nanoparticles of the third material; wherein the voids have random distribution and random three-dimensional configurations. 8. The method of claim 7, wherein the substrate is selected from a group including metallic substrates, metallic leadframes, and laminated substrates including metallic layers alternating with insulating layers. 9. The method of claim 8, wherein the first material is selected from a group including copper, copper alloys, aluminum, aluminum alloys, iron-nickel alloys, and Kovar™. 10. The method of claim 9, wherein the first material includes a plated layer of a metal selected from a group including tin, silver, nickel, palladium, and gold. 11. The method of claim 7, wherein a method of additively depositing is selected from a group including screen printing, flexographic printing, gravure printing, dip coating, spray coating, and inkjet printing comprising piezoelectric, thermal, acoustic, and electrostatic inkjet printing. 12. The method of claim 7, wherein the second material is selected from a group including metals, metal oxides, oxides, and ceramics. 13. The method of claim 12, wherein a size of the nanoparticles of the second material is in the range from about 10 nm to 20 nm. 14. The method of claim 7, wherein the third material is selected from a group including polymers, oxides, ceramics, metals, and metal oxides. 15. The method of claim 7, wherein an energy for sintering the second nanoparticles is selected from a group including thermal energy, photonic energy, electromagnetic energy, and chemical energy. 16. The method of claim 7, wherein a method of removing the third nanoparticles is selected from a group including heating, vapor etching, and liquid phase etching. 17. The method of claim 7, wherein some of the voids have a substantially spherical shape and narrow entrances. 18. A method for enhancing adhesion of packaged semiconductor device % the method comprising:
providing a substrate of a first material; providing a solvent paste including nanoparticles of a second material with a first weight percentage, and nanoparticles of a third material with a second weight percentage smaller than the first weight percentage; wherein the nanoparticles of the second material have a size that provides a melting point at a lower temperature than a melting point temperature of a bulk second material, and the nanoparticles of the third material have a size at least as large as the nanoparticle size of the second material and a melting point at a temperature higher than the melting point temperature of the nanoparticles of the second material; additively depositing a layer of the paste on a surface of the substrate; providing energy to increase temperature of the second material to a temperature above the melting point of the second material; sintering together the nanoparticles of the second material into a liquid surrounding the nanoparticles of the third material, and concurrently diffusing second material into the first material of the surface of the substrate; solidifying the liquid of the second material to create a solid layer of second material surrounding the nanoparticles of the third material; creating voids in the solid layer of second material by removing the nanoparticles of the third material wherein the voids have random distribution and random three-dimensional configurations; encapsulating the solid layer of second material and the surface of the substrate in a polymeric compound, wherein the polymeric compound fills the voids in the solid layer of second material. 19. The method of claim 18, wherein the substrate is a metallic leadframe. 20. The method of claim 18, wherein the second material is selected from a group including metals, metal oxides, oxides, and ceramics. 21. The method of claim 20, wherein a size of the nanoparticles of the second material is in the range from about 10 nm to 20 nm. 22. The method of claim 18, wherein the third material is selected from a group including polymers, oxides, ceramics, metals, and metal oxides. 23. The method of claim 18, wherein a method of additively depositing is selected from a group including screen printing, flexographic printing, gravure printing, dip coating, spray coating, and inkjet printing comprising piezoelectric, thermal, acoustic, and electrostatic inkjet printing. 24. The method of claim 18, wherein a method of removing the third nanoparticles is selected from a group including heating, vapor etching, and liquid phase etching. 25. The method of claim 18, further including: before encapsulating, assembling a semiconductor circuit chip on the substrate so that the chip will be positioned inside the polymeric compound after encapsulating. 26. The device of claim 1, wherein the sintered structure consists essentially of: the sintered nanoparticles of the second material; and the polymeric compound filling the voids. | 2,800 |
11,888 | 11,888 | 15,048,009 | 2,827 | Automation equipment ( 21 ) including at least one automation device ( 9 ) and an operator system ( 22 ) for the visualization and operation of at least one sequencer (SFC) of a sequential control. Objects ( 24 ) created from the sequencer ( 16 ) are processed during a RUN operation of the automation device ( 9 ). The objects ( 24 ) parameterize and activate CFC functions ( 15 ) loaded into the automation device ( 9 ) and defined by a Continuous Function Chart editor. The interaction and link between the objects ( 24 ) and the CFC functions ( 15 ) are effected via process values ( 18 ) and control signals ( 19 ). Modification of the sequential control is enabled during the RUN operation of the automation device ( 9 ). | 1. In automation equipment that includes at least one automation device (9) and an operator system (22) for visualization and operation of a sequencer (SFC) of a sequential control, wherein objects (24) created from the sequencer (16) are processed during a RUN operation of the automation device, wherein the objects (24) parameterize and activate CFC functions (15) loaded into the automation device (9) and defined by a Continuous Function Chart editor, and wherein an interaction and link between the objects (24) and the CFC functions (15) are effected via process values (18) and control signals (19), the operator system (22) comprising:
an interpreter for interpreting and processing of the sequential control and for activating the CFC functions (15) in the automation device (9); an engineering interface for modifying the sequencer (16) of the sequential control; and an interface for the visualization and operation of the sequencer (16) of the sequential control. 2. An operator system (22) for automation equipment and operable for visualization and operation of a sequencer (SFC) of a sequential control, wherein objects (24) created from the sequencer (16) are processed during a RUN operation of an automation device of the automation equipment, wherein the objects (24) parameterize and activate CFC functions (15) loaded into the automation device (9) and defined by a Continuous Function Chart editor, and wherein an interaction and link between the objects (24) and the CFC functions (15) are effected via process values (18) and control signals (19), the operator system (22) comprising:
an interpreter for interpreting and processing of the sequential control and for activating the CFC functions (15) in the automation device (9); an engineering interface for modifying the sequencer (16) of the sequential control; and an interface for the visualization and operation of the sequencer (16) of the sequential control. | Automation equipment ( 21 ) including at least one automation device ( 9 ) and an operator system ( 22 ) for the visualization and operation of at least one sequencer (SFC) of a sequential control. Objects ( 24 ) created from the sequencer ( 16 ) are processed during a RUN operation of the automation device ( 9 ). The objects ( 24 ) parameterize and activate CFC functions ( 15 ) loaded into the automation device ( 9 ) and defined by a Continuous Function Chart editor. The interaction and link between the objects ( 24 ) and the CFC functions ( 15 ) are effected via process values ( 18 ) and control signals ( 19 ). Modification of the sequential control is enabled during the RUN operation of the automation device ( 9 ).1. In automation equipment that includes at least one automation device (9) and an operator system (22) for visualization and operation of a sequencer (SFC) of a sequential control, wherein objects (24) created from the sequencer (16) are processed during a RUN operation of the automation device, wherein the objects (24) parameterize and activate CFC functions (15) loaded into the automation device (9) and defined by a Continuous Function Chart editor, and wherein an interaction and link between the objects (24) and the CFC functions (15) are effected via process values (18) and control signals (19), the operator system (22) comprising:
an interpreter for interpreting and processing of the sequential control and for activating the CFC functions (15) in the automation device (9); an engineering interface for modifying the sequencer (16) of the sequential control; and an interface for the visualization and operation of the sequencer (16) of the sequential control. 2. An operator system (22) for automation equipment and operable for visualization and operation of a sequencer (SFC) of a sequential control, wherein objects (24) created from the sequencer (16) are processed during a RUN operation of an automation device of the automation equipment, wherein the objects (24) parameterize and activate CFC functions (15) loaded into the automation device (9) and defined by a Continuous Function Chart editor, and wherein an interaction and link between the objects (24) and the CFC functions (15) are effected via process values (18) and control signals (19), the operator system (22) comprising:
an interpreter for interpreting and processing of the sequential control and for activating the CFC functions (15) in the automation device (9); an engineering interface for modifying the sequencer (16) of the sequential control; and an interface for the visualization and operation of the sequencer (16) of the sequential control. | 2,800 |
11,889 | 11,889 | 14,843,964 | 2,814 | A voltage regulator having a coil inductor is integrated or embedded in a system-on-chip (SOC) device. The coil inductor is fabricated on an inductor wafer with through vias, and the inductor wafer is joined with an SOC wafer for integration with the SOC device. | 1. A device, comprising:
a system-on-chip (SOC) wafer; an inductor wafer having first and second surfaces and a plurality of vias therethrough, the vias forming a plurality of sidewalls in the inductor wafer, the first surface of the inductor wafer disposed adjacent to the SOC wafer; a magnetic layer on at least a portion of the first surface of the inductor wafer; and a conductive layer disposed on the magnetic layer, on at least a portion of the second surface of the inductor wafer, and on at least some of the sidewalls formed by the vias in the inductor wafer. 2. The device of claim 1, wherein the magnetic layer comprises a thin-film magnetic layer. 3. The device of claim 1, wherein the conductive layer comprises a copper plating. 4. The device of claim 3, wherein the copper plating comprises a copper semi-additive plating. 5. The device of claim 1, further comprising a conductor disposed between the SOC wafer and the inductor wafer. 6. The device of claim 5, wherein the conductor comprises a solder. 7. The device of claim 6, wherein the solder is positioned directly over at least one of the vias. 8. The device of claim 6, wherein the solder is in direct contact with at least a portion of the conductive layer. 9. The device of claim 1, wherein the inductor wafer comprises a glass wafer. 10. The device of claim 1, wherein the inductor wafer comprises a quartz wafer. 11. A device, comprising:
a voltage regulator, comprising:
a die;
an inductor wafer having first and second surfaces and a plurality of vias therethrough, the vias forming a plurality of sidewalls in the inductor wafer, the first surface of the inductor wafer disposed adjacent to the die;
a magnetic layer on at least a portion of the first surface of the inductor wafer; and
a plurality of conductors disposed within at least some of the vias in the inductor wafer, the conductors having respective first ends adjacent to the first surface of the inductor wafer and second ends adjacent to the second surface of the inductor wafer; and
a system-on-chip (SOC) package configured to receive a power supply voltage from the voltage regulator, the SOC package having at least one conductor connected to at least one of the first and second ends of the conductors. 12. The device of claim 11, further comprising a printed circuit board (PCB) coupled to the SOC package. 13. The device of claim 11, wherein the magnetic layer comprises a thin-film magnetic layer. 14. The device of claim 11, wherein the voltage regulator further comprises a plurality of additional conductors disposed on the first and second surfaces of the inductor wafer, the additional conductors on the first and second surfaces of the inductor wafer and the conductors within at least some of the vias in the inductor wafer forming a coil of an inductor. 15. The device of claim 14, wherein the coil at least partially surrounds the magnetic layer. 16. The device of claim 1, wherein the inductor wafer comprises a glass wafer. 17. The device of claim 1, wherein the inductor wafer comprises a quartz wafer. 18. A method of making a device, comprising:
providing a first wafer having a first surface and a second surface; forming a plurality of vias through the first and second surfaces of the first wafer, the vias defined by a plurality of sidewalls within the first wafer; forming a patterned magnetic layer on at least a portion of the first surface of the first wafer; forming a conductive layer on the patterned magnetic layer over the patterned magnetic layer, at least a portion of the second surface of the first wafer, and at least some of the sidewalls of the vias; and joining a second wafer to the first wafer. 19. The method of claim 18, wherein the first wafer comprises an inductor wafer. 20. The method of claim 19, wherein the inductor wafer comprises a glass wafer. 21. The method of claim 19, wherein the inductor wafer comprises a quartz wafer. 22. The method of claim 18, further comprising forming a plurality of solders on the second wafer. 23. The method of claim 18, wherein forming the conductive layer comprises forming a semi-additive plating of copper. 24. The method of claim 18, wherein forming the patterned magnetic layer comprises sputtering a magnetic material on at least a portion of the first surface of the first wafer. 25. The method of claim 24, wherein the magnetic material comprises cobalt-tantalum-zirconium (CoTaZr). 26. A method of making a device, comprising:
providing a system-on-chip (SOC) package; and forming a voltage regulator on the SOC package, comprising:
providing an SOC die;
providing an inductor wafer having first and second surfaces, the first surface of the inductor wafer disposed adjacent to the SOC die;
forming a plurality of vias through the first and second surfaces of the inductor wafer, the vias defined by a plurality of sidewalls in the inductor wafer; and
forming a plurality of conductors disposed within at least some of the vias in the inductor wafer, the conductors having respective first ends adjacent to the first surface of the inductor wafer and second ends adjacent to the second surface of the inductor wafer,
wherein the SOC package is configured to receive a power supply voltage from the voltage regulator, the SOC package having at least one conductor connected to at least one of the first and second ends of the conductors. 27. The method of claim 26, further comprising providing a printed circuit board (PCB) coupled to the SOC package. 28. The method of claim 26, further comprising forming patterned conductive layers on the first and second surfaces of the inductor wafer, the patterned conductive layers on the first and second surfaces of the inductor wafer and the conductors within at least some of the vias in the inductor wafer forming a coil of an inductor. 29. The method of claim 26, further comprising forming a patterned magnetic layer on the inductor wafer. 30. The method of claim 29, wherein the patterned magnetic layer comprises cobalt-tantalum-zirconium (CoTaZr). | A voltage regulator having a coil inductor is integrated or embedded in a system-on-chip (SOC) device. The coil inductor is fabricated on an inductor wafer with through vias, and the inductor wafer is joined with an SOC wafer for integration with the SOC device.1. A device, comprising:
a system-on-chip (SOC) wafer; an inductor wafer having first and second surfaces and a plurality of vias therethrough, the vias forming a plurality of sidewalls in the inductor wafer, the first surface of the inductor wafer disposed adjacent to the SOC wafer; a magnetic layer on at least a portion of the first surface of the inductor wafer; and a conductive layer disposed on the magnetic layer, on at least a portion of the second surface of the inductor wafer, and on at least some of the sidewalls formed by the vias in the inductor wafer. 2. The device of claim 1, wherein the magnetic layer comprises a thin-film magnetic layer. 3. The device of claim 1, wherein the conductive layer comprises a copper plating. 4. The device of claim 3, wherein the copper plating comprises a copper semi-additive plating. 5. The device of claim 1, further comprising a conductor disposed between the SOC wafer and the inductor wafer. 6. The device of claim 5, wherein the conductor comprises a solder. 7. The device of claim 6, wherein the solder is positioned directly over at least one of the vias. 8. The device of claim 6, wherein the solder is in direct contact with at least a portion of the conductive layer. 9. The device of claim 1, wherein the inductor wafer comprises a glass wafer. 10. The device of claim 1, wherein the inductor wafer comprises a quartz wafer. 11. A device, comprising:
a voltage regulator, comprising:
a die;
an inductor wafer having first and second surfaces and a plurality of vias therethrough, the vias forming a plurality of sidewalls in the inductor wafer, the first surface of the inductor wafer disposed adjacent to the die;
a magnetic layer on at least a portion of the first surface of the inductor wafer; and
a plurality of conductors disposed within at least some of the vias in the inductor wafer, the conductors having respective first ends adjacent to the first surface of the inductor wafer and second ends adjacent to the second surface of the inductor wafer; and
a system-on-chip (SOC) package configured to receive a power supply voltage from the voltage regulator, the SOC package having at least one conductor connected to at least one of the first and second ends of the conductors. 12. The device of claim 11, further comprising a printed circuit board (PCB) coupled to the SOC package. 13. The device of claim 11, wherein the magnetic layer comprises a thin-film magnetic layer. 14. The device of claim 11, wherein the voltage regulator further comprises a plurality of additional conductors disposed on the first and second surfaces of the inductor wafer, the additional conductors on the first and second surfaces of the inductor wafer and the conductors within at least some of the vias in the inductor wafer forming a coil of an inductor. 15. The device of claim 14, wherein the coil at least partially surrounds the magnetic layer. 16. The device of claim 1, wherein the inductor wafer comprises a glass wafer. 17. The device of claim 1, wherein the inductor wafer comprises a quartz wafer. 18. A method of making a device, comprising:
providing a first wafer having a first surface and a second surface; forming a plurality of vias through the first and second surfaces of the first wafer, the vias defined by a plurality of sidewalls within the first wafer; forming a patterned magnetic layer on at least a portion of the first surface of the first wafer; forming a conductive layer on the patterned magnetic layer over the patterned magnetic layer, at least a portion of the second surface of the first wafer, and at least some of the sidewalls of the vias; and joining a second wafer to the first wafer. 19. The method of claim 18, wherein the first wafer comprises an inductor wafer. 20. The method of claim 19, wherein the inductor wafer comprises a glass wafer. 21. The method of claim 19, wherein the inductor wafer comprises a quartz wafer. 22. The method of claim 18, further comprising forming a plurality of solders on the second wafer. 23. The method of claim 18, wherein forming the conductive layer comprises forming a semi-additive plating of copper. 24. The method of claim 18, wherein forming the patterned magnetic layer comprises sputtering a magnetic material on at least a portion of the first surface of the first wafer. 25. The method of claim 24, wherein the magnetic material comprises cobalt-tantalum-zirconium (CoTaZr). 26. A method of making a device, comprising:
providing a system-on-chip (SOC) package; and forming a voltage regulator on the SOC package, comprising:
providing an SOC die;
providing an inductor wafer having first and second surfaces, the first surface of the inductor wafer disposed adjacent to the SOC die;
forming a plurality of vias through the first and second surfaces of the inductor wafer, the vias defined by a plurality of sidewalls in the inductor wafer; and
forming a plurality of conductors disposed within at least some of the vias in the inductor wafer, the conductors having respective first ends adjacent to the first surface of the inductor wafer and second ends adjacent to the second surface of the inductor wafer,
wherein the SOC package is configured to receive a power supply voltage from the voltage regulator, the SOC package having at least one conductor connected to at least one of the first and second ends of the conductors. 27. The method of claim 26, further comprising providing a printed circuit board (PCB) coupled to the SOC package. 28. The method of claim 26, further comprising forming patterned conductive layers on the first and second surfaces of the inductor wafer, the patterned conductive layers on the first and second surfaces of the inductor wafer and the conductors within at least some of the vias in the inductor wafer forming a coil of an inductor. 29. The method of claim 26, further comprising forming a patterned magnetic layer on the inductor wafer. 30. The method of claim 29, wherein the patterned magnetic layer comprises cobalt-tantalum-zirconium (CoTaZr). | 2,800 |
11,890 | 11,890 | 14,469,875 | 2,857 | An automated global weather notification system is provided. The automated global weather notification system is capable of obtaining observational weather data, including data form of forecast grids, and applying business rules and conditional variables to that data. Based on the business rules and conditional variables, notifications are generated. Relevant users are identified in particular geographic areas and notifications are delivered to those users via, for example, SMS, MMS, email, or other methods of electronic information delivery. | 1. A method of producing informational weather notifications based on a weather forecast, the method comprising:
obtaining aggregated forecast data corresponding to a geographic location, wherein the aggregated forecast data comprises data for a plurality of notification categories; comparing the weather data to a first threshold condition for the at least one notification category, the first threshold condition taking into account aggregated forecast data relating to the at least one notification category over a predetermined period of time; and if the first threshold condition is met for the at least one notification category, automatically producing an informational weather notification. 2. The method of claim 1, wherein the first threshold condition comprises a plurality of business rules. 3. The method of claim 1, further comprising delivering the automated informational weather notification to a user device. 4. The method of claim 3, wherein delivering the informational weather notification comprises incorporating the informational weather notification into a website or smart-phone application. 5. The method of claim 3, wherein delivering the informational weather notification comprises pushing the informational weather notification, via a telecommunication network, to subscribed users in proximity to the geographic location. 6. The method of claim 1, wherein the aggregated forecast data comprises global forecast grids, and wherein the geographic location relates to at least one box of the global forecast grids. 7. The method of claim 6, wherein the global forecast grids have a first resolution and a second resolution, the first resolution being finer than the second resolution. 8. The method of claim 1, wherein the first threshold condition is based on a period of time less than 48 hours in the future. 9. The method of claim 1, wherein the first threshold condition is based on a period of time of at least 3 hours. 10. The method of claim 1, further comprising comparing the weather data to a second threshold condition for a second notification category, and if the second threshold condition is met, producing an automated informational weather notification for the second threshold condition. 11. The method of claim 10, wherein the comparisons of the first and second threshold conditions, respectively, are done independently of one another. 12. The method of claim 1, wherein the plurality of notification categories comprise rainfall, snowfall, ice, extreme heat, extreme cold, high wind, thunderstorm, and/or fog. 13. The method of claim 1, wherein the informational weather notification automatically expires after a predetermined period of time. 14. A system for producing informational weather notifications, comprising:
a database comprising aggregated global forecast data; a plurality of business rules to be applied to at least a subset of the aggregated global forecast data; a plurality of conditional variables to be applied to the subset of aggregated global forecast data; a processor for automatically interpreting results of the business rules and conditional variables applied to the subset of aggregated global forecast data, and based on the results, automatically generating an informational weather notification. 15. The system of claim 14, further comprising a network for automatically distributing the informational weather notification to users located in a relevant geographic location. 16. The system of claim 14, wherein the aggregated global forecast data comprises global forecast grids. 17. The system of claim 14, wherein at least one of the plurality of business rules is applied to forecast data over a predetermined period of time. 18. The system of claim 14, wherein the informational weather notification automatically expires after a predetermined period of time. 19. The system of claim 14, wherein the business rules consider data relating to at least one of rain, snow, ice, extreme heat, extreme cold, wind, thunderstorms, and fog. 20. A non-transitory, computer-readable medium comprising instructions for causing a computer to execute the steps of:
obtaining aggregated forecast data corresponding to a geographic location, wherein the aggregated forecast data comprises data for a plurality of notification categories; comparing the weather data to a first threshold condition for the at least one notification category, the first threshold condition taking into account aggregated forecast data relating to the at least one notification category over a predetermined period of time; and if the first threshold condition is met for the at least one notification category, automatically producing an informational weather notification. | An automated global weather notification system is provided. The automated global weather notification system is capable of obtaining observational weather data, including data form of forecast grids, and applying business rules and conditional variables to that data. Based on the business rules and conditional variables, notifications are generated. Relevant users are identified in particular geographic areas and notifications are delivered to those users via, for example, SMS, MMS, email, or other methods of electronic information delivery.1. A method of producing informational weather notifications based on a weather forecast, the method comprising:
obtaining aggregated forecast data corresponding to a geographic location, wherein the aggregated forecast data comprises data for a plurality of notification categories; comparing the weather data to a first threshold condition for the at least one notification category, the first threshold condition taking into account aggregated forecast data relating to the at least one notification category over a predetermined period of time; and if the first threshold condition is met for the at least one notification category, automatically producing an informational weather notification. 2. The method of claim 1, wherein the first threshold condition comprises a plurality of business rules. 3. The method of claim 1, further comprising delivering the automated informational weather notification to a user device. 4. The method of claim 3, wherein delivering the informational weather notification comprises incorporating the informational weather notification into a website or smart-phone application. 5. The method of claim 3, wherein delivering the informational weather notification comprises pushing the informational weather notification, via a telecommunication network, to subscribed users in proximity to the geographic location. 6. The method of claim 1, wherein the aggregated forecast data comprises global forecast grids, and wherein the geographic location relates to at least one box of the global forecast grids. 7. The method of claim 6, wherein the global forecast grids have a first resolution and a second resolution, the first resolution being finer than the second resolution. 8. The method of claim 1, wherein the first threshold condition is based on a period of time less than 48 hours in the future. 9. The method of claim 1, wherein the first threshold condition is based on a period of time of at least 3 hours. 10. The method of claim 1, further comprising comparing the weather data to a second threshold condition for a second notification category, and if the second threshold condition is met, producing an automated informational weather notification for the second threshold condition. 11. The method of claim 10, wherein the comparisons of the first and second threshold conditions, respectively, are done independently of one another. 12. The method of claim 1, wherein the plurality of notification categories comprise rainfall, snowfall, ice, extreme heat, extreme cold, high wind, thunderstorm, and/or fog. 13. The method of claim 1, wherein the informational weather notification automatically expires after a predetermined period of time. 14. A system for producing informational weather notifications, comprising:
a database comprising aggregated global forecast data; a plurality of business rules to be applied to at least a subset of the aggregated global forecast data; a plurality of conditional variables to be applied to the subset of aggregated global forecast data; a processor for automatically interpreting results of the business rules and conditional variables applied to the subset of aggregated global forecast data, and based on the results, automatically generating an informational weather notification. 15. The system of claim 14, further comprising a network for automatically distributing the informational weather notification to users located in a relevant geographic location. 16. The system of claim 14, wherein the aggregated global forecast data comprises global forecast grids. 17. The system of claim 14, wherein at least one of the plurality of business rules is applied to forecast data over a predetermined period of time. 18. The system of claim 14, wherein the informational weather notification automatically expires after a predetermined period of time. 19. The system of claim 14, wherein the business rules consider data relating to at least one of rain, snow, ice, extreme heat, extreme cold, wind, thunderstorms, and fog. 20. A non-transitory, computer-readable medium comprising instructions for causing a computer to execute the steps of:
obtaining aggregated forecast data corresponding to a geographic location, wherein the aggregated forecast data comprises data for a plurality of notification categories; comparing the weather data to a first threshold condition for the at least one notification category, the first threshold condition taking into account aggregated forecast data relating to the at least one notification category over a predetermined period of time; and if the first threshold condition is met for the at least one notification category, automatically producing an informational weather notification. | 2,800 |
11,891 | 11,891 | 15,809,708 | 2,884 | A PET detector and method thereof are provided. The PET detector may include: a crystal array including a plurality of crystal elements arranged in an array and light-splitting structures set on surfaces of the plurality of crystal elements, the light-splitting structures jointly define a light output surface of the crystal array; a semiconductor sensor array, which is set in opposite to the light output surface of the crystal array and is suitable to receive photons from the light output surface, the semiconductor sensor array comprises a plurality of semiconductor sensors arranged in an array. | 1. A positron emission tomography (PET) detector, the PET detector comprising:
a crystal array, the crystal array comprising a plurality of crystal elements arranged in a single layer; and a semiconductor sensor array comprising a plurality of semiconductor sensors for receiving photons from the plurality of crystal elements the plurality of semiconductor sensors being configured to be coupled with the plurality of crystal elements of the crystal array, wherein the number of the plurality of crystal elements of the crystal array is more than or equal to the number of the plurality of semiconductor sensors of the semiconductor sensor array. 2. The PET detector according to claim 1, wherein more than one of the plurality of crystal elements in the crystal array are coupled with one semiconductor sensor of the semiconductor sensor array. 3. The PET detector according to claim 1, wherein at least one semiconductor sensor of the semiconductor sensor array are coupled with one of the plurality of crystal elements in the crystal array. 4. The PET detector according to claim 1, wherein the coupling of the plurality of semiconductor sensors with the plurality of crystal elements of the crystal array comprises a contact between the semiconductor sensors and the crystal elements directly or through an adhesive material. 5. The PET detector according to claim 1, wherein a center-of-gravity of the semiconductor sensor array coincides with a center-of-gravity of the crystal array. 6. The PET detector according to claim 21, wherein the number of light-reflective films define a light output surface facing to the semiconductor sensor array, and the semiconductor sensor array completely or partially covers the light output surface. 7. (canceled) 8. The PET detector according to claim 1 further comprising a first amplifier, wherein an input terminal of the first amplifier is connected with an output terminal of a semiconductor sensor in a predetermined row of the semiconductor sensor array. 9. The PET detector according to claim 1 further comprising a second amplifier, wherein an input terminal of the second amplifier is connected with an output terminal of a semiconductor sensor in a predetermined column of the semiconductor sensor array. 10. The PET detector according to claim 21, wherein the light-reflective films are set based on light-receiving areas of the semiconductor sensors, a relative location between the semiconductor sensors, and relative positioning between the semiconductor sensors and the crystal array. 11. The PET detector according to claim 1, wherein the number or positioning of the semiconductor sensors relates to a spatial resolution of the crystal elements in an image. 12-17. (canceled) 18. The PET detector according to claim 1, wherein the crystal elements have a same length along a top-to-bottom direction. 19-20. (canceled) 21. The PET detector according to claim 1, wherein the crystal array further includes a number of light-reflective films, and the light-reflective films are mounted on a surface of at least one of the plurality of crystal elements. 22. The PET detector according to claim 21, wherein the light-reflective films mounted on the surfaces of two of the plurality of crystal elements have different lengths along a top-to-bottom direction. 23. The PET detector according to claim 21, wherein the light-reflective films mounted on the surfaces of two of the plurality of crystal elements have a same length along a top-to-bottom direction. 24. The PET detector according to claim 21, wherein the light-reflective films mounted on the surfaces of two of the plurality of crystal elements have different areas. 25. The PET detector according to claim 1, wherein the PET detector further comprises a driver board connected to the semiconductor sensor array and configured to drive the semiconductor sensor array. 26. The PET detector according to claim 1, wherein the plurality of semiconductor sensors completely cover surfaces of the plurality of crystal elements, and the plurality of semiconductor sensors receive the photons from the surfaces of the plurality of crystal elements. 27. The PET detector according to claim 1, wherein the plurality of semiconductor sensors partially cover surfaces of the plurality of crystal elements, and the plurality of semiconductor sensors receives the photons from the surfaces of the plurality of crystal elements. 28. The PET detector according to claim 1, wherein the coupling of the plurality of semiconductor sensors with the plurality of crystal elements of the crystal array comprises a contact between the semiconductor sensors and the crystal elements through a light guide. 29. The PET detector according to claim 1, wherein the plurality of semiconductor sensors are arranged in a one-to-one correspondence with the plurality of crystal elements. | A PET detector and method thereof are provided. The PET detector may include: a crystal array including a plurality of crystal elements arranged in an array and light-splitting structures set on surfaces of the plurality of crystal elements, the light-splitting structures jointly define a light output surface of the crystal array; a semiconductor sensor array, which is set in opposite to the light output surface of the crystal array and is suitable to receive photons from the light output surface, the semiconductor sensor array comprises a plurality of semiconductor sensors arranged in an array.1. A positron emission tomography (PET) detector, the PET detector comprising:
a crystal array, the crystal array comprising a plurality of crystal elements arranged in a single layer; and a semiconductor sensor array comprising a plurality of semiconductor sensors for receiving photons from the plurality of crystal elements the plurality of semiconductor sensors being configured to be coupled with the plurality of crystal elements of the crystal array, wherein the number of the plurality of crystal elements of the crystal array is more than or equal to the number of the plurality of semiconductor sensors of the semiconductor sensor array. 2. The PET detector according to claim 1, wherein more than one of the plurality of crystal elements in the crystal array are coupled with one semiconductor sensor of the semiconductor sensor array. 3. The PET detector according to claim 1, wherein at least one semiconductor sensor of the semiconductor sensor array are coupled with one of the plurality of crystal elements in the crystal array. 4. The PET detector according to claim 1, wherein the coupling of the plurality of semiconductor sensors with the plurality of crystal elements of the crystal array comprises a contact between the semiconductor sensors and the crystal elements directly or through an adhesive material. 5. The PET detector according to claim 1, wherein a center-of-gravity of the semiconductor sensor array coincides with a center-of-gravity of the crystal array. 6. The PET detector according to claim 21, wherein the number of light-reflective films define a light output surface facing to the semiconductor sensor array, and the semiconductor sensor array completely or partially covers the light output surface. 7. (canceled) 8. The PET detector according to claim 1 further comprising a first amplifier, wherein an input terminal of the first amplifier is connected with an output terminal of a semiconductor sensor in a predetermined row of the semiconductor sensor array. 9. The PET detector according to claim 1 further comprising a second amplifier, wherein an input terminal of the second amplifier is connected with an output terminal of a semiconductor sensor in a predetermined column of the semiconductor sensor array. 10. The PET detector according to claim 21, wherein the light-reflective films are set based on light-receiving areas of the semiconductor sensors, a relative location between the semiconductor sensors, and relative positioning between the semiconductor sensors and the crystal array. 11. The PET detector according to claim 1, wherein the number or positioning of the semiconductor sensors relates to a spatial resolution of the crystal elements in an image. 12-17. (canceled) 18. The PET detector according to claim 1, wherein the crystal elements have a same length along a top-to-bottom direction. 19-20. (canceled) 21. The PET detector according to claim 1, wherein the crystal array further includes a number of light-reflective films, and the light-reflective films are mounted on a surface of at least one of the plurality of crystal elements. 22. The PET detector according to claim 21, wherein the light-reflective films mounted on the surfaces of two of the plurality of crystal elements have different lengths along a top-to-bottom direction. 23. The PET detector according to claim 21, wherein the light-reflective films mounted on the surfaces of two of the plurality of crystal elements have a same length along a top-to-bottom direction. 24. The PET detector according to claim 21, wherein the light-reflective films mounted on the surfaces of two of the plurality of crystal elements have different areas. 25. The PET detector according to claim 1, wherein the PET detector further comprises a driver board connected to the semiconductor sensor array and configured to drive the semiconductor sensor array. 26. The PET detector according to claim 1, wherein the plurality of semiconductor sensors completely cover surfaces of the plurality of crystal elements, and the plurality of semiconductor sensors receive the photons from the surfaces of the plurality of crystal elements. 27. The PET detector according to claim 1, wherein the plurality of semiconductor sensors partially cover surfaces of the plurality of crystal elements, and the plurality of semiconductor sensors receives the photons from the surfaces of the plurality of crystal elements. 28. The PET detector according to claim 1, wherein the coupling of the plurality of semiconductor sensors with the plurality of crystal elements of the crystal array comprises a contact between the semiconductor sensors and the crystal elements through a light guide. 29. The PET detector according to claim 1, wherein the plurality of semiconductor sensors are arranged in a one-to-one correspondence with the plurality of crystal elements. | 2,800 |
11,892 | 11,892 | 15,131,660 | 2,827 | The invention relates to an automation system and a method for operating automation equipment that includes an operator system for displaying a technical process to be controlled and at least one automation device that is configured to process, for process control, CFC functions of a control program which are loaded onto the at least one automation device and are created by means of a Continuous Function Chart editor. The load on an automation device in such a system is operatively reduced in accord with the monitored load on the device, without the need to upgrade or change the hardware of the automation device, by loading corresponding CFC functions onto the operator system and switching between corresponding CFC functions on the automation device and the operator system. | 1. A method for operating automation equipment that includes an operator system for displaying a technical process to be controlled and at least one automation device which is configured to process, for process control, CFC functions of a control program that are loaded onto the at least one automation device and are created by means of a Continuous Function Chart editor, the method comprising:
capturing a processing load of the at least one automation device; loading onto the operator system CFC functions that correspond to the CFC functions of the control program that are loaded onto the at least one automation device; and activating and processing, by means of at least one selector of the at least one automation device as a function of the processing load, one of (i) at least one of the CFC functions in the at least one automation device and (ii) a CFC function in the operator system corresponding to the at least one CFC function. 2. The method of claim 1, further comprising transmitting to a process image of the operator system, by means of the selector, a process value to activate the CFC function in the operator system. 3. In an automation system that includes an operator system for displaying a technical process to be controlled, and at least one automation device that is configured to process, for process control, CFC functions of a control program that are loaded onto the at least one automation device and are created by means of a Continuous Function Chart editor,
the at least one automation device being configured to capture its processing load, the operator system being configured to process CFC functions that are loaded onto the operator system and which correspond to the CFC functions of the control program that are loaded onto the at least one automation device, and further comprising an execution selector of the at least one automation device for at least one of the CFC functions in the at least one automation device, the execution selector being configured to, as a function of the captured processing load, one of (i) activate one of the CFC functions in the at least one automation device and (ii) activate one of the CFC functions in the operator system corresponding to the one CFC function in the at least one automation device. 4. The automation device of claim 3, wherein the execution selector is configured to transmit a process value to a process image of the operator system to activate the one CFC function in the operator system. | The invention relates to an automation system and a method for operating automation equipment that includes an operator system for displaying a technical process to be controlled and at least one automation device that is configured to process, for process control, CFC functions of a control program which are loaded onto the at least one automation device and are created by means of a Continuous Function Chart editor. The load on an automation device in such a system is operatively reduced in accord with the monitored load on the device, without the need to upgrade or change the hardware of the automation device, by loading corresponding CFC functions onto the operator system and switching between corresponding CFC functions on the automation device and the operator system.1. A method for operating automation equipment that includes an operator system for displaying a technical process to be controlled and at least one automation device which is configured to process, for process control, CFC functions of a control program that are loaded onto the at least one automation device and are created by means of a Continuous Function Chart editor, the method comprising:
capturing a processing load of the at least one automation device; loading onto the operator system CFC functions that correspond to the CFC functions of the control program that are loaded onto the at least one automation device; and activating and processing, by means of at least one selector of the at least one automation device as a function of the processing load, one of (i) at least one of the CFC functions in the at least one automation device and (ii) a CFC function in the operator system corresponding to the at least one CFC function. 2. The method of claim 1, further comprising transmitting to a process image of the operator system, by means of the selector, a process value to activate the CFC function in the operator system. 3. In an automation system that includes an operator system for displaying a technical process to be controlled, and at least one automation device that is configured to process, for process control, CFC functions of a control program that are loaded onto the at least one automation device and are created by means of a Continuous Function Chart editor,
the at least one automation device being configured to capture its processing load, the operator system being configured to process CFC functions that are loaded onto the operator system and which correspond to the CFC functions of the control program that are loaded onto the at least one automation device, and further comprising an execution selector of the at least one automation device for at least one of the CFC functions in the at least one automation device, the execution selector being configured to, as a function of the captured processing load, one of (i) activate one of the CFC functions in the at least one automation device and (ii) activate one of the CFC functions in the operator system corresponding to the one CFC function in the at least one automation device. 4. The automation device of claim 3, wherein the execution selector is configured to transmit a process value to a process image of the operator system to activate the one CFC function in the operator system. | 2,800 |
11,893 | 11,893 | 15,909,258 | 2,853 | The present disclosure relates to methodologies, systems and devices for controlling pressure of a mobile phase in a CO2-based chromatography system. A pump is used to pump a mobile phase containing CO2 and is located upstream of a chromatography column. A primary pressure control element is located downstream of the chromatography column and controls the pressure of the mobile phase within the column. A secondary pressure control element is located downstream of the primary pressure control element and maintains the pressure of the mobile phase above a threshold value between an outlet of the primary pressure control element and the point of detection within a detector. The detector is located downstream of both the primary pressure control element and the secondary pressure control element. | 1. A system of controlling pressure of a mobile phase, the system comprising:
a pump for pumping a mobile phase including CO2, the pump located upstream of a chromatography column; a primary pressure control element located downstream of the column and disposed to control pressure of the mobile phase within the column; a detector located downstream of the primary pressure control element; and a secondary pressure control element located downstream of the primary pressure control element and disposed to maintain a pressure of the mobile phase above a threshold value between an outlet of the primary pressure control element and the point of detection within the detector. 2. The system of claim 1, wherein the primary pressure control element is an active back pressure regulator. 3. The system of claim 1, wherein the secondary pressure control element maintains the pressure of the analyte between about 6.55 to 10.3 MPa (950 to 1500 psi). 4. The system of claim 1, wherein an outlet of the secondary pressure control element is located within 5.0 cm from the point of detection. 5. The system of claim 1, wherein the detector is a flame ionization detector, a mass spectrometer, or an aerosol-based detector. 6. The system of claim 1, wherein the secondary pressure control element prevents phase separation between CO2 and a liquid co-solvent while transporting the analyte from the primary pressure control element to the detector. 7. The system of claim 1, wherein the secondary pressure control element is incorporated into a section of tubing disposed between the outlet of the primary pressure control element and the point of detection within the detector. 8. The system of claim 7, wherein the secondary pressure control element has a diameter between 0.1 microns and 100 microns, and a length between 0.1 microns and 100 centimeters. 9. The system of claim 1, wherein the secondary pressure control element is a restrictor, a back pressure regulator, or a variable restrictor. 10. A method of controlling pressure of a mobile phase in a CO2-based chromatography system, the method comprising:
controlling pressure of the mobile phase within a column of a CO2-based chromatography system using a primary pressure control element located downstream of the column; and maintaining a pressure of the mobile phase above a threshold value between an outlet of the primary pressure control element and the point of detection within a detector using a secondary pressure control element located downstream of the primary pressure control element. 11. The method of claim 10, wherein the primary pressure control element is a back pressure regulator. 12. The method of claim 10, wherein the secondary pressure control element maintains the pressure of the analyte between about 6.55 to 10.3 MPa (950 to 1500 psi). 13. The method of claim 10, wherein an outlet of the secondary pressure control element is located within 5.0 cm from the point of detection. 14. The method of claim 10, wherein the secondary pressure control element prevents phase separation between CO2 and a liquid co-solvent while transporting the analyte from the primary pressure control element to the detector. 15. The method of claim 10, wherein the secondary pressure control element is incorporated into a section of tubing disposed between the outlet of the primary pressure control element and the point of detection within the detector. 16. The method of claim 15, wherein the secondary pressure control element has a diameter between 0.1 microns to 100 microns, and a length between 0.1 microns and 100 centimeters. 17. The method of claim 10, wherein the secondary pressure control element is a BPR, restrictor, or variable restrictor. 18. A device for managing pressure within a CO2-based chromatography system, the device comprising:
a pressure control element having a diameter between 0.1 microns and 100 microns, and a length between 0.1 microns and 100 centimeters; a first end of the pressure control element disposed to receive a fluid from a back pressure regulator; and a second end of the pressure control element disposed to transmit the fluid to a detector; wherein the pressure control element is disposed to maintain a pressure of the fluid above a threshold value. 19. The device of claim 18, wherein the diameter of the pressure control element is greater at the first end than at the second end. 20. The device of claim 18, wherein the pressure control element prevents phase separation between CO2 and a liquid co-solvent while transporting the fluid from the back pressure regulator to the detector. | The present disclosure relates to methodologies, systems and devices for controlling pressure of a mobile phase in a CO2-based chromatography system. A pump is used to pump a mobile phase containing CO2 and is located upstream of a chromatography column. A primary pressure control element is located downstream of the chromatography column and controls the pressure of the mobile phase within the column. A secondary pressure control element is located downstream of the primary pressure control element and maintains the pressure of the mobile phase above a threshold value between an outlet of the primary pressure control element and the point of detection within a detector. The detector is located downstream of both the primary pressure control element and the secondary pressure control element.1. A system of controlling pressure of a mobile phase, the system comprising:
a pump for pumping a mobile phase including CO2, the pump located upstream of a chromatography column; a primary pressure control element located downstream of the column and disposed to control pressure of the mobile phase within the column; a detector located downstream of the primary pressure control element; and a secondary pressure control element located downstream of the primary pressure control element and disposed to maintain a pressure of the mobile phase above a threshold value between an outlet of the primary pressure control element and the point of detection within the detector. 2. The system of claim 1, wherein the primary pressure control element is an active back pressure regulator. 3. The system of claim 1, wherein the secondary pressure control element maintains the pressure of the analyte between about 6.55 to 10.3 MPa (950 to 1500 psi). 4. The system of claim 1, wherein an outlet of the secondary pressure control element is located within 5.0 cm from the point of detection. 5. The system of claim 1, wherein the detector is a flame ionization detector, a mass spectrometer, or an aerosol-based detector. 6. The system of claim 1, wherein the secondary pressure control element prevents phase separation between CO2 and a liquid co-solvent while transporting the analyte from the primary pressure control element to the detector. 7. The system of claim 1, wherein the secondary pressure control element is incorporated into a section of tubing disposed between the outlet of the primary pressure control element and the point of detection within the detector. 8. The system of claim 7, wherein the secondary pressure control element has a diameter between 0.1 microns and 100 microns, and a length between 0.1 microns and 100 centimeters. 9. The system of claim 1, wherein the secondary pressure control element is a restrictor, a back pressure regulator, or a variable restrictor. 10. A method of controlling pressure of a mobile phase in a CO2-based chromatography system, the method comprising:
controlling pressure of the mobile phase within a column of a CO2-based chromatography system using a primary pressure control element located downstream of the column; and maintaining a pressure of the mobile phase above a threshold value between an outlet of the primary pressure control element and the point of detection within a detector using a secondary pressure control element located downstream of the primary pressure control element. 11. The method of claim 10, wherein the primary pressure control element is a back pressure regulator. 12. The method of claim 10, wherein the secondary pressure control element maintains the pressure of the analyte between about 6.55 to 10.3 MPa (950 to 1500 psi). 13. The method of claim 10, wherein an outlet of the secondary pressure control element is located within 5.0 cm from the point of detection. 14. The method of claim 10, wherein the secondary pressure control element prevents phase separation between CO2 and a liquid co-solvent while transporting the analyte from the primary pressure control element to the detector. 15. The method of claim 10, wherein the secondary pressure control element is incorporated into a section of tubing disposed between the outlet of the primary pressure control element and the point of detection within the detector. 16. The method of claim 15, wherein the secondary pressure control element has a diameter between 0.1 microns to 100 microns, and a length between 0.1 microns and 100 centimeters. 17. The method of claim 10, wherein the secondary pressure control element is a BPR, restrictor, or variable restrictor. 18. A device for managing pressure within a CO2-based chromatography system, the device comprising:
a pressure control element having a diameter between 0.1 microns and 100 microns, and a length between 0.1 microns and 100 centimeters; a first end of the pressure control element disposed to receive a fluid from a back pressure regulator; and a second end of the pressure control element disposed to transmit the fluid to a detector; wherein the pressure control element is disposed to maintain a pressure of the fluid above a threshold value. 19. The device of claim 18, wherein the diameter of the pressure control element is greater at the first end than at the second end. 20. The device of claim 18, wherein the pressure control element prevents phase separation between CO2 and a liquid co-solvent while transporting the fluid from the back pressure regulator to the detector. | 2,800 |
11,894 | 11,894 | 15,095,562 | 2,861 | The invention relates to a system and method for measuring the flow stream height and velocity and other properties of water, drilling mud, or other liquid flowing through a pipe. The system comprises at least one and preferably a plurality of capacitive pads, connected to a data acquisition system capable of measuring the capacitance of each pad. These capacitive pads may be arranged radially around the inner diameter of a pipe or on a vertical probe inserted into the pipe. The pads that are submerged below the liquid level within the pipe will have a larger capacitance due to their proximity with a high dielectric fluid such as water or drilling mud. Conversely, the pads above the flow stream will have a lower capacitance due to their proximity to air. The fluid level can be inferred by determining the number of pads submerged in the fluid and by analysis of the capacitive values of pads nearest the fluid-air interface. | 1. A system for measuring the flow stream height of a liquid flowing through a pipe comprising:
a plurality of capacitive pads, said capacitive pads arranged within a pipe; a data acquisition system connected to said pads wherein said data acquisition system is capable of measuring the capacitance of each pad; and a processor capable of calculating the flow stream height based on the capacitance of each pad. 2. The system of claim 1, wherein the capacitive pad geometry is optimized to maximize the signal to noise ratio. 3. The system of claim 1 wherein multiple capacitive pads are axially displaced along the pipe. 4. The system of claim 1 wherein multiple capacitive pads are arranged in at least one array. 5. The system of claim 4 wherein a plurality of arrays are angularly offset from each other. 6. The system of claim 1 wherein the capacitive pads are interdigital finger pads. 7. The system of claim 1 wherein time division multiplexing is used to measure the capacitance of the capacitive pads. 8. The system of claim 1 wherein a dynamic sampling method is used to measure the capacitance of the capacitive pads. 9. The system of claim 8 wherein the capacitance of multiple capacitive pads is measured simultaneously. 10. The system of claim 8 wherein the capacitance of the capacitive pads proximate to a liquid gas interface is measured more frequently than the capacitance of the capacitive pads further from said interface. 11. The system of claim 1 wherein the capacitive pads are arranged on a vertical probe. 12. A method for measuring the flow stream height of a liquid within a pipe comprising:
measuring the capacitance of a plurality of capacitive pads, calculating the height of a flow stream based on the measured capacitance of the capacitive pads. 13. The method of claim 12 further comprising measuring the capacitance of a plurality of capacitive pads axially displaced from one another. 14. The method of claim 12 further comprising using a previously calculated flow stream height to optimize subsequent measuring of the capacitance from a plurality of capacitive pads. 15. The method of claim 12 wherein the capacitance of multiple capacitive pads is measured simultaneously. 16. The method of claim 12 further comprising calculating the presence of a gas entrained in a liquid stream based on the measured capacitance. 17. A method for measuring the velocity of a liquid flow stream comprising:
using a Doppler radar system to illuminate the surface of a liquid flow stream, receiving a Doppler radar signal, and calculating the velocity of the flow stream based on the received Doppler radar signal. 18. The method of claim 17 wherein multiple axially offset sensors are used to measure the velocity of the liquid flow stream. 19. The method of claim 17 further comprising using an ultrasonic flow stream height measurement to calculate the height or velocity of the flow stream 20. A method for calculating the flow stream velocity of a liquid within a pipe comprising:
measuring the capacitance waveforms of a first set of capacitive pads, measuring the capacitance waveforms of a second set of capacitive pads,
said second set of capacitive pads being axially displaced a known distance from the first set,
comparing the capacitance waveforms of the first set of capacitive pads with the capacitance waveforms of the second set of capacitive pads, calculating the velocity of the flow stream based on the relationship of the capacitance waveforms of the first set and second set of capacitive pads. | The invention relates to a system and method for measuring the flow stream height and velocity and other properties of water, drilling mud, or other liquid flowing through a pipe. The system comprises at least one and preferably a plurality of capacitive pads, connected to a data acquisition system capable of measuring the capacitance of each pad. These capacitive pads may be arranged radially around the inner diameter of a pipe or on a vertical probe inserted into the pipe. The pads that are submerged below the liquid level within the pipe will have a larger capacitance due to their proximity with a high dielectric fluid such as water or drilling mud. Conversely, the pads above the flow stream will have a lower capacitance due to their proximity to air. The fluid level can be inferred by determining the number of pads submerged in the fluid and by analysis of the capacitive values of pads nearest the fluid-air interface.1. A system for measuring the flow stream height of a liquid flowing through a pipe comprising:
a plurality of capacitive pads, said capacitive pads arranged within a pipe; a data acquisition system connected to said pads wherein said data acquisition system is capable of measuring the capacitance of each pad; and a processor capable of calculating the flow stream height based on the capacitance of each pad. 2. The system of claim 1, wherein the capacitive pad geometry is optimized to maximize the signal to noise ratio. 3. The system of claim 1 wherein multiple capacitive pads are axially displaced along the pipe. 4. The system of claim 1 wherein multiple capacitive pads are arranged in at least one array. 5. The system of claim 4 wherein a plurality of arrays are angularly offset from each other. 6. The system of claim 1 wherein the capacitive pads are interdigital finger pads. 7. The system of claim 1 wherein time division multiplexing is used to measure the capacitance of the capacitive pads. 8. The system of claim 1 wherein a dynamic sampling method is used to measure the capacitance of the capacitive pads. 9. The system of claim 8 wherein the capacitance of multiple capacitive pads is measured simultaneously. 10. The system of claim 8 wherein the capacitance of the capacitive pads proximate to a liquid gas interface is measured more frequently than the capacitance of the capacitive pads further from said interface. 11. The system of claim 1 wherein the capacitive pads are arranged on a vertical probe. 12. A method for measuring the flow stream height of a liquid within a pipe comprising:
measuring the capacitance of a plurality of capacitive pads, calculating the height of a flow stream based on the measured capacitance of the capacitive pads. 13. The method of claim 12 further comprising measuring the capacitance of a plurality of capacitive pads axially displaced from one another. 14. The method of claim 12 further comprising using a previously calculated flow stream height to optimize subsequent measuring of the capacitance from a plurality of capacitive pads. 15. The method of claim 12 wherein the capacitance of multiple capacitive pads is measured simultaneously. 16. The method of claim 12 further comprising calculating the presence of a gas entrained in a liquid stream based on the measured capacitance. 17. A method for measuring the velocity of a liquid flow stream comprising:
using a Doppler radar system to illuminate the surface of a liquid flow stream, receiving a Doppler radar signal, and calculating the velocity of the flow stream based on the received Doppler radar signal. 18. The method of claim 17 wherein multiple axially offset sensors are used to measure the velocity of the liquid flow stream. 19. The method of claim 17 further comprising using an ultrasonic flow stream height measurement to calculate the height or velocity of the flow stream 20. A method for calculating the flow stream velocity of a liquid within a pipe comprising:
measuring the capacitance waveforms of a first set of capacitive pads, measuring the capacitance waveforms of a second set of capacitive pads,
said second set of capacitive pads being axially displaced a known distance from the first set,
comparing the capacitance waveforms of the first set of capacitive pads with the capacitance waveforms of the second set of capacitive pads, calculating the velocity of the flow stream based on the relationship of the capacitance waveforms of the first set and second set of capacitive pads. | 2,800 |
11,895 | 11,895 | 16,292,994 | 2,875 | The LED luminaire is constructed with an LED/driver printed circuit board mounted directly on a floor of the heat sink assembly. By mounting the LED/driver printed circuit board directly in and on the heat sink assembly, the heat imposed on the LED/driver printed circuit board during use in a canopy hood over a cooking surface is transferred directly to the heat sink assembly for dissipation. | 1. A LED luminaire for a canopy hood comprising
a heat sink assembly having a circular mounting flange and an internal cavity with a floor that extends across said cavity; an LED/driver printed circuit board removably mounted on said floor for emitting light therefrom; and a lens cover assembly removably mounted on said flange of said heat sink assembly for passage of light emitted from said printed circuit board. 2. An LED luminaire as set forth in claim 1 wherein said heat sink assembly has a chamber to receive wiring for delivering electricity to said LED/driver printed circuit board and a pair of diametrically disposed ports extending into communication with said chamber for receiving conductors from a mains power supply. 3. An LED luminaire as set forth in claim 2 wherein said heat sink assembly further includes an array of fins extending radially outwardly of said chamber to aid in the dissipation of heat to the surrounding environment. 4. An LED luminaire as set forth in claim 2 further comprising a junction box cover assembly mounted coaxially on said heat sink assembly for sealing said chamber. 5. An LED luminaire as set forth in claim 1 wherein said lens cover assembly includes a circular collar removably secured to said flange and a lens secured in said collar. 6. An LED luminaire as set forth in claim 5 wherein said collar has a radially inwardly directed lip and said lens cover assembly includes a circular insert secured concentrically within said collar and having an upstanding flange fitting inside said flange and a gasket seated in sealing relation in said insert and receiving said lens. 7. An LED luminaire as set forth in claim 5 wherein said collar is made of stainless steel and said heat sink assembly is made of die cast aluminum 8. (canceled) 9. An LED luminaire as set forth in claim 1 further comprising a gasket on said flange of said heat sink assembly for sealing against a canopy hood surface. 10. An LED luminaire as set forth in claim 5 wherein said collar has an outer rim fitting circumferentially about said flange of said heat sink assembly and said lens cover assembly has a circular insert secured concentrically within said collar with an upstanding flange fitting inside said mounting flange to fully contain said mounting flange of said heat sink assembly. 11. An LED luminaire as set forth in claim 6 wherein said gasket has a plurality of sealing ribs on a circumferential periphery thereof sized to fit within and against said flange of said insert in seal tight relation and a plurality of sealing ribs on an upper surface thereof seated against said mounting flange of said heat sink assembly. | The LED luminaire is constructed with an LED/driver printed circuit board mounted directly on a floor of the heat sink assembly. By mounting the LED/driver printed circuit board directly in and on the heat sink assembly, the heat imposed on the LED/driver printed circuit board during use in a canopy hood over a cooking surface is transferred directly to the heat sink assembly for dissipation.1. A LED luminaire for a canopy hood comprising
a heat sink assembly having a circular mounting flange and an internal cavity with a floor that extends across said cavity; an LED/driver printed circuit board removably mounted on said floor for emitting light therefrom; and a lens cover assembly removably mounted on said flange of said heat sink assembly for passage of light emitted from said printed circuit board. 2. An LED luminaire as set forth in claim 1 wherein said heat sink assembly has a chamber to receive wiring for delivering electricity to said LED/driver printed circuit board and a pair of diametrically disposed ports extending into communication with said chamber for receiving conductors from a mains power supply. 3. An LED luminaire as set forth in claim 2 wherein said heat sink assembly further includes an array of fins extending radially outwardly of said chamber to aid in the dissipation of heat to the surrounding environment. 4. An LED luminaire as set forth in claim 2 further comprising a junction box cover assembly mounted coaxially on said heat sink assembly for sealing said chamber. 5. An LED luminaire as set forth in claim 1 wherein said lens cover assembly includes a circular collar removably secured to said flange and a lens secured in said collar. 6. An LED luminaire as set forth in claim 5 wherein said collar has a radially inwardly directed lip and said lens cover assembly includes a circular insert secured concentrically within said collar and having an upstanding flange fitting inside said flange and a gasket seated in sealing relation in said insert and receiving said lens. 7. An LED luminaire as set forth in claim 5 wherein said collar is made of stainless steel and said heat sink assembly is made of die cast aluminum 8. (canceled) 9. An LED luminaire as set forth in claim 1 further comprising a gasket on said flange of said heat sink assembly for sealing against a canopy hood surface. 10. An LED luminaire as set forth in claim 5 wherein said collar has an outer rim fitting circumferentially about said flange of said heat sink assembly and said lens cover assembly has a circular insert secured concentrically within said collar with an upstanding flange fitting inside said mounting flange to fully contain said mounting flange of said heat sink assembly. 11. An LED luminaire as set forth in claim 6 wherein said gasket has a plurality of sealing ribs on a circumferential periphery thereof sized to fit within and against said flange of said insert in seal tight relation and a plurality of sealing ribs on an upper surface thereof seated against said mounting flange of said heat sink assembly. | 2,800 |
11,896 | 11,896 | 15,603,885 | 2,846 | An embodiment of a control system includes a current command module configured to receive a torque command and output a current command for controlling a direct current (DC) motor, and a supply current limiting module configured to receive a supply current limit as an input and actively compute a motor current limit based on the supply current limit, the supply current limiting module configured to limit the current command based on the motor current limit. | 1. A control system, comprising:
a current command module configured to receive a torque command and output a current command for controlling a direct current (DC) motor; and a supply current limiting module configured to receive a supply current limit as an input and actively compute a motor current limit based on the supply current limit, the supply current limiting module configured to limit the current command based on the motor current limit. 2. The system of claim 1, further comprising a current regulator configured to apply a voltage to the DC motor based on the limited current command. 3. The system of claim 1, wherein the supply current limiting module is configured to compute the motor current command based on a voltage loop defined by a motor control system and the DC motor. 4. The system of claim 1, wherein the supply current limiting module is configured to compute the motor current command using a power equation that is based on operating conditions of the DC motor. 5. The system of claim 4, wherein the power equation is represented by:
V ECU I s −R c I s 2 =P e,
wherein VECU is a voltage input to a motor control system, Is is a supply current to the DC motor, Rc is an input resistance of the motor control system, and Pe is an electrical power input to a motor control system. 6. The system of claim 5, wherein the electrical power input Pe is represented by:
P
e
=
v
m
i
m
=
R
m
i
m
2
+
K
e
ω
m
i
m
+
v
B
i
m
,
wherein vm is a motor voltage, im is a motor current, Rm is an electrical resistance of the DC motor, ωm is a rotational speed of the DC motor, vB is a brush drop voltage, and Ke is a constant. 7. The system of claim 1, wherein the motor current limit includes a maximum motor capability curve and a minimum motor capability curve. 8. The system of claim 1, further comprising a current limiting module configured to receive an external current limit, and limit the current command based on the external current limit. 9. The system of claim 1, wherein the DC motor is a brushed DC motor. 10. The system of claim 1, wherein the supply current limiting module is part of an electrical power steering system of a vehicle. 11. A method of controlling a direct current (DC) motor, comprising:
receiving a torque command and outputting a current command for controlling a direct current (DC) motor; receiving a supply current limit as an input; actively computing, by a supply current limiting module, a motor current limit based on the supply current limit; and limiting the current command based on the motor current limit. 12. The method of claim 11, further comprising applying, by a current regulator, a voltage to the DC motor based on the limited current command. 13. The method of claim 1, wherein the motor current command is computed based on a voltage loop defined by a motor control system and the DC motor. 14. The method of claim 1, wherein the motor current command is computed using a power equation that is based on operating conditions of the DC motor. 15. The method of claim 14, wherein the power equation is represented by:
V ECU I s −R c I s 2 =P e,
wherein VECU is a voltage input to a motor control system, Is is a supply current to the DC motor, Rc is an input resistance of the motor control system, and Pe is an electrical power input to a motor control system. 16. The method of claim 15, wherein the electrical power input Pe is represented by:
P
e
=
v
m
i
m
=
R
m
i
m
2
+
K
e
ω
m
i
m
+
v
B
i
m
,
wherein vm is a motor voltage, im is a motor current, Rm is an electrical resistance of the DC motor, ωm is a rotational speed of the DC motor, vB is a brush drop voltage, and Ke is a constant. 17. The method of claim 11, wherein the motor current limit includes a maximum motor capability curve and a minimum motor capability curve. 18. The method of claim 11, wherein the DC motor is a brushed DC motor. 19. The method of claim 11, wherein the supply current limiting module is part of an electrical power steering system of a vehicle. | An embodiment of a control system includes a current command module configured to receive a torque command and output a current command for controlling a direct current (DC) motor, and a supply current limiting module configured to receive a supply current limit as an input and actively compute a motor current limit based on the supply current limit, the supply current limiting module configured to limit the current command based on the motor current limit.1. A control system, comprising:
a current command module configured to receive a torque command and output a current command for controlling a direct current (DC) motor; and a supply current limiting module configured to receive a supply current limit as an input and actively compute a motor current limit based on the supply current limit, the supply current limiting module configured to limit the current command based on the motor current limit. 2. The system of claim 1, further comprising a current regulator configured to apply a voltage to the DC motor based on the limited current command. 3. The system of claim 1, wherein the supply current limiting module is configured to compute the motor current command based on a voltage loop defined by a motor control system and the DC motor. 4. The system of claim 1, wherein the supply current limiting module is configured to compute the motor current command using a power equation that is based on operating conditions of the DC motor. 5. The system of claim 4, wherein the power equation is represented by:
V ECU I s −R c I s 2 =P e,
wherein VECU is a voltage input to a motor control system, Is is a supply current to the DC motor, Rc is an input resistance of the motor control system, and Pe is an electrical power input to a motor control system. 6. The system of claim 5, wherein the electrical power input Pe is represented by:
P
e
=
v
m
i
m
=
R
m
i
m
2
+
K
e
ω
m
i
m
+
v
B
i
m
,
wherein vm is a motor voltage, im is a motor current, Rm is an electrical resistance of the DC motor, ωm is a rotational speed of the DC motor, vB is a brush drop voltage, and Ke is a constant. 7. The system of claim 1, wherein the motor current limit includes a maximum motor capability curve and a minimum motor capability curve. 8. The system of claim 1, further comprising a current limiting module configured to receive an external current limit, and limit the current command based on the external current limit. 9. The system of claim 1, wherein the DC motor is a brushed DC motor. 10. The system of claim 1, wherein the supply current limiting module is part of an electrical power steering system of a vehicle. 11. A method of controlling a direct current (DC) motor, comprising:
receiving a torque command and outputting a current command for controlling a direct current (DC) motor; receiving a supply current limit as an input; actively computing, by a supply current limiting module, a motor current limit based on the supply current limit; and limiting the current command based on the motor current limit. 12. The method of claim 11, further comprising applying, by a current regulator, a voltage to the DC motor based on the limited current command. 13. The method of claim 1, wherein the motor current command is computed based on a voltage loop defined by a motor control system and the DC motor. 14. The method of claim 1, wherein the motor current command is computed using a power equation that is based on operating conditions of the DC motor. 15. The method of claim 14, wherein the power equation is represented by:
V ECU I s −R c I s 2 =P e,
wherein VECU is a voltage input to a motor control system, Is is a supply current to the DC motor, Rc is an input resistance of the motor control system, and Pe is an electrical power input to a motor control system. 16. The method of claim 15, wherein the electrical power input Pe is represented by:
P
e
=
v
m
i
m
=
R
m
i
m
2
+
K
e
ω
m
i
m
+
v
B
i
m
,
wherein vm is a motor voltage, im is a motor current, Rm is an electrical resistance of the DC motor, ωm is a rotational speed of the DC motor, vB is a brush drop voltage, and Ke is a constant. 17. The method of claim 11, wherein the motor current limit includes a maximum motor capability curve and a minimum motor capability curve. 18. The method of claim 11, wherein the DC motor is a brushed DC motor. 19. The method of claim 11, wherein the supply current limiting module is part of an electrical power steering system of a vehicle. | 2,800 |
11,897 | 11,897 | 15,110,325 | 2,865 | A system and method are disclosed for predicting, and optionally removing surface multiples from acquired seismic data that lacks surface consistency, such as seismic data acquired using an Ocean Bottom Cable (OBC) or Ocean Bottom Node (OBN) system where the sources are located at or near the water's surface and the receivers are located at or near the ocean's floor. By processing the acquired seismic data using seismic interferometry, source side and/or receiver side operators can be generated which satisfy the surface consistency requirement of techniques such as Surface Related Multiple Elimination (SRME) so that SRME or the like can be used to predict the surface multiples. | 1. A method for processing seismic data comprising:
receiving seismic data which was generated using sources and receivers; performing seismic interferometry on the received seismic data to generate additional seismic data; and using the received seismic data and the additional seismic data to predict multiples in the received seismic data. 2. The method of claim 1, wherein said sources and receivers are spaced apart depthwise by at least a predetermined distance. 3. The method of claim 1, wherein the received seismic data was generated using an Ocean Bottom Cable (OBC) system. 4. The method of claim 3, wherein the additional seismic data is one of: data that would have been recorded by the receivers, which are located on the ocean floor, if the receivers were instead located at the ocean surface or data that would have been recorded by the receivers on the ocean floor if the sources were also located on the ocean floor. 5. The method of claim 1, wherein the step of performing seismic interferometry further comprises:
cross-correlating recordings of wave fields at two receiver positions to generate a Green's function that would have been be observed at one of the two receiver positions if there had been an impulsive source at the other one of the two receiver positions. 6. The method of claim 5, wherein the step of cross-correlating further comprises calculating:
R
{
G
(
X
A
,
X
B
,
ω
)
}
=
∫
∂
D
-
1
j
ω
ρ
(
X
)
(
G
*
(
X
A
,
X
,
ω
)
∂
i
G
(
X
B
,
X
,
ω
)
-
∂
i
G
*
(
X
A
,
X
,
ω
)
G
(
X
B
,
X
,
ω
)
)
n
i
2
x
where R denotes the real part, G refers to Green's function, ρ refers to density, n refers to a normal direction of a boundary, j refers to √{square root over (−1)}, ω refers to frequency; super script * refers to the complex conjugate; X refers to locations and D refers to an enclosed boundary. 7. The method of claim 1, further comprising the step of:
removing the predicted multiples from the seismic data. 8. A system for processing seismic data comprising:
a processor configured to receive seismic data which was generated using sources and receivers, and to perform seismic interferometry on the received seismic data to generate additional seismic data; wherein the processor uses the received seismic data and the additional seismic data to predict multiples in the received seismic data. 9. The system of claim 8, wherein said sources and receivers are spaced apart depthwise by at least a predetermined distance. 10. The system of claim 8, wherein the received seismic data was generated using an Ocean Bottom Cable (OBC) system. 11. The system of claim 10, wherein the additional seismic data is one of: data that would have been recorded by the receivers, which are located on the ocean floor, if the receivers were instead located at the ocean surface or data that would have been recorded by the receivers on the ocean floor if the sources were also located on the ocean floor. 12. The system of claim 8, wherein the processor performs seismic interferometry further by cross-correlating recordings of wave fields at two receiver positions to generate a Green's function that would have been be observed at one of the two receiver positions if there had been an impulsive source at the other one of the two receiver positions. 13. The system of claim 12, wherein the processor performs the cross-correlating by calculating:
R
{
G
(
X
A
,
X
B
,
ω
)
}
=
∫
∂
D
-
1
j
ω
ρ
(
X
)
(
G
*
(
X
A
,
X
,
ω
)
∂
i
G
(
X
B
,
X
,
ω
)
-
∂
i
G
*
(
X
A
,
X
,
ω
)
G
(
X
B
,
X
,
ω
)
)
n
i
2
x
where R denotes the real part, G refers to Green's function, ρ refers to density, n refers to a normal direction of a boundary, j refers to √{square root over (−1)}, ω refers to frequency; super script * refers to the complex conjugate; X refers to locations and D refers to an enclosed boundary. 14. The system of claim 8, wherein the processor is further configured to remove the predicted multiples from the seismic data. 15. A computer-readable medium containing program instructions which, when executed on a suitably programmed computer processing device, perform the steps of:
receiving seismic data which was generated using sources and receivers; performing seismic interferometry on the received seismic data to generate additional seismic data; and using the received seismic data and the additional seismic data to predict multiples in the received seismic data. 16. The computer-readable medium of claim 15, wherein said sources and receivers are spaced apart depthwise by at least a predetermined distance. 17. The computer-readable medium of claim 15, wherein the received seismic data was generated using an Ocean Bottom Cable (OBC) system. 18. The computer-readable medium of claim 17, wherein the additional seismic data is one of: data that would have been recorded by the receivers, which are located on the ocean floor, if the receivers were instead located at the ocean surface or data that would have been recorded by the receivers on the ocean floor if the sources were also located on the ocean floor. 19. The computer-readable medium of claim 15, wherein the step of performing seismic interferometry further comprises:
cross-correlating recordings of wave fields at two receiver positions to generate a Green's function that would have been be observed at one of the two receiver positions if there had been an impulsive source at the other one of the two receiver positions. 20. The computer-readable medium of claim 19, wherein the step of cross-correlating further comprises calculating:
{
G
(
X
A
,
X
B
,
ω
)
}
=
∫
∂
D
-
1
j
ω
ρ
(
X
)
(
G
*
(
X
A
,
X
,
ω
)
∂
i
G
(
X
B
,
X
,
ω
)
-
∂
i
G
*
(
X
A
,
X
,
ω
)
G
(
X
B
,
X
,
ω
)
)
n
i
2
x
where R denotes the real part, G refers to Green's function, ρ refers to density, n refers to a normal direction of a boundary, j refers to √{square root over (−1)}, ω refers to frequency; super script * refers to the complex conjugate; X refers to locations and D refers to an enclosed boundary. | A system and method are disclosed for predicting, and optionally removing surface multiples from acquired seismic data that lacks surface consistency, such as seismic data acquired using an Ocean Bottom Cable (OBC) or Ocean Bottom Node (OBN) system where the sources are located at or near the water's surface and the receivers are located at or near the ocean's floor. By processing the acquired seismic data using seismic interferometry, source side and/or receiver side operators can be generated which satisfy the surface consistency requirement of techniques such as Surface Related Multiple Elimination (SRME) so that SRME or the like can be used to predict the surface multiples.1. A method for processing seismic data comprising:
receiving seismic data which was generated using sources and receivers; performing seismic interferometry on the received seismic data to generate additional seismic data; and using the received seismic data and the additional seismic data to predict multiples in the received seismic data. 2. The method of claim 1, wherein said sources and receivers are spaced apart depthwise by at least a predetermined distance. 3. The method of claim 1, wherein the received seismic data was generated using an Ocean Bottom Cable (OBC) system. 4. The method of claim 3, wherein the additional seismic data is one of: data that would have been recorded by the receivers, which are located on the ocean floor, if the receivers were instead located at the ocean surface or data that would have been recorded by the receivers on the ocean floor if the sources were also located on the ocean floor. 5. The method of claim 1, wherein the step of performing seismic interferometry further comprises:
cross-correlating recordings of wave fields at two receiver positions to generate a Green's function that would have been be observed at one of the two receiver positions if there had been an impulsive source at the other one of the two receiver positions. 6. The method of claim 5, wherein the step of cross-correlating further comprises calculating:
R
{
G
(
X
A
,
X
B
,
ω
)
}
=
∫
∂
D
-
1
j
ω
ρ
(
X
)
(
G
*
(
X
A
,
X
,
ω
)
∂
i
G
(
X
B
,
X
,
ω
)
-
∂
i
G
*
(
X
A
,
X
,
ω
)
G
(
X
B
,
X
,
ω
)
)
n
i
2
x
where R denotes the real part, G refers to Green's function, ρ refers to density, n refers to a normal direction of a boundary, j refers to √{square root over (−1)}, ω refers to frequency; super script * refers to the complex conjugate; X refers to locations and D refers to an enclosed boundary. 7. The method of claim 1, further comprising the step of:
removing the predicted multiples from the seismic data. 8. A system for processing seismic data comprising:
a processor configured to receive seismic data which was generated using sources and receivers, and to perform seismic interferometry on the received seismic data to generate additional seismic data; wherein the processor uses the received seismic data and the additional seismic data to predict multiples in the received seismic data. 9. The system of claim 8, wherein said sources and receivers are spaced apart depthwise by at least a predetermined distance. 10. The system of claim 8, wherein the received seismic data was generated using an Ocean Bottom Cable (OBC) system. 11. The system of claim 10, wherein the additional seismic data is one of: data that would have been recorded by the receivers, which are located on the ocean floor, if the receivers were instead located at the ocean surface or data that would have been recorded by the receivers on the ocean floor if the sources were also located on the ocean floor. 12. The system of claim 8, wherein the processor performs seismic interferometry further by cross-correlating recordings of wave fields at two receiver positions to generate a Green's function that would have been be observed at one of the two receiver positions if there had been an impulsive source at the other one of the two receiver positions. 13. The system of claim 12, wherein the processor performs the cross-correlating by calculating:
R
{
G
(
X
A
,
X
B
,
ω
)
}
=
∫
∂
D
-
1
j
ω
ρ
(
X
)
(
G
*
(
X
A
,
X
,
ω
)
∂
i
G
(
X
B
,
X
,
ω
)
-
∂
i
G
*
(
X
A
,
X
,
ω
)
G
(
X
B
,
X
,
ω
)
)
n
i
2
x
where R denotes the real part, G refers to Green's function, ρ refers to density, n refers to a normal direction of a boundary, j refers to √{square root over (−1)}, ω refers to frequency; super script * refers to the complex conjugate; X refers to locations and D refers to an enclosed boundary. 14. The system of claim 8, wherein the processor is further configured to remove the predicted multiples from the seismic data. 15. A computer-readable medium containing program instructions which, when executed on a suitably programmed computer processing device, perform the steps of:
receiving seismic data which was generated using sources and receivers; performing seismic interferometry on the received seismic data to generate additional seismic data; and using the received seismic data and the additional seismic data to predict multiples in the received seismic data. 16. The computer-readable medium of claim 15, wherein said sources and receivers are spaced apart depthwise by at least a predetermined distance. 17. The computer-readable medium of claim 15, wherein the received seismic data was generated using an Ocean Bottom Cable (OBC) system. 18. The computer-readable medium of claim 17, wherein the additional seismic data is one of: data that would have been recorded by the receivers, which are located on the ocean floor, if the receivers were instead located at the ocean surface or data that would have been recorded by the receivers on the ocean floor if the sources were also located on the ocean floor. 19. The computer-readable medium of claim 15, wherein the step of performing seismic interferometry further comprises:
cross-correlating recordings of wave fields at two receiver positions to generate a Green's function that would have been be observed at one of the two receiver positions if there had been an impulsive source at the other one of the two receiver positions. 20. The computer-readable medium of claim 19, wherein the step of cross-correlating further comprises calculating:
{
G
(
X
A
,
X
B
,
ω
)
}
=
∫
∂
D
-
1
j
ω
ρ
(
X
)
(
G
*
(
X
A
,
X
,
ω
)
∂
i
G
(
X
B
,
X
,
ω
)
-
∂
i
G
*
(
X
A
,
X
,
ω
)
G
(
X
B
,
X
,
ω
)
)
n
i
2
x
where R denotes the real part, G refers to Green's function, ρ refers to density, n refers to a normal direction of a boundary, j refers to √{square root over (−1)}, ω refers to frequency; super script * refers to the complex conjugate; X refers to locations and D refers to an enclosed boundary. | 2,800 |
11,898 | 11,898 | 15,472,576 | 2,837 | A piezoelectric vibrator is a piezoelectric vibrator including a vibration portion. The vibration portion has an n-type Si layer which is a degenerated semiconductor and which has a resistivity of not less than 0.5 mΩcm and not greater than 1.2 mΩcm and preferably not greater than 0.9 mΩcm. | 1. A piezoelectric vibrator comprising a vibration portion having an n-type Si layer which is a degenerated semiconductor and which has a resistivity of not less than 0.5 mΩcm and not greater than 0.9 mΩcm. 2. The piezoelectric vibrator according to claim 1, wherein the vibration portion has a piezoelectric thin film formed on the Si layer. 3. The piezoelectric vibrator according to claim 2, wherein the vibration portion further has a silicon oxide layer formed on at least one of an upper surface of the Si layer, a lower surface of the Si layer, and an upper surface of the piezoelectric thin film. 4. The piezoelectric vibrator according to claim 1, wherein the vibrator is planar and operates in an in plane vibration mode. 5. The piezoelectric vibrator according to claim 1, wherein the vibrator is planar and operates in an out of plane vibration mode. 6. A piezoelectric vibration device comprising:
a lower substrate; an upper substrate cooperating with the lower substrate to form a vibration space between the lower substrate and the upper substrate; and a piezoelectric vibrator disposed within the vibration space, the piezoelectric vibrator including a vibration portion having an n-type Si layer which is a degenerated semiconductor and which has a resistivity of not less than 0.5 mΩcm and not greater than 0.9 mΩcm. 7. The piezoelectric vibration device according to claim 6, wherein the vibration portion has a piezoelectric thin film formed on the Si layer. 8. The piezoelectric vibration device according to claim 7, wherein the vibration portion further has a silicon oxide layer formed on at least one of an upper surface of the Si layer, a lower surface of the Si layer, and an upper surface of the piezoelectric thin film. 9. The piezoelectric vibration device according to claim 6, wherein the vibrator is planar and operates in an in plane vibration mode. 10. The piezoelectric vibration device according to claim 6, wherein the vibrator is planar and operates in an out of plane vibration mode. | A piezoelectric vibrator is a piezoelectric vibrator including a vibration portion. The vibration portion has an n-type Si layer which is a degenerated semiconductor and which has a resistivity of not less than 0.5 mΩcm and not greater than 1.2 mΩcm and preferably not greater than 0.9 mΩcm.1. A piezoelectric vibrator comprising a vibration portion having an n-type Si layer which is a degenerated semiconductor and which has a resistivity of not less than 0.5 mΩcm and not greater than 0.9 mΩcm. 2. The piezoelectric vibrator according to claim 1, wherein the vibration portion has a piezoelectric thin film formed on the Si layer. 3. The piezoelectric vibrator according to claim 2, wherein the vibration portion further has a silicon oxide layer formed on at least one of an upper surface of the Si layer, a lower surface of the Si layer, and an upper surface of the piezoelectric thin film. 4. The piezoelectric vibrator according to claim 1, wherein the vibrator is planar and operates in an in plane vibration mode. 5. The piezoelectric vibrator according to claim 1, wherein the vibrator is planar and operates in an out of plane vibration mode. 6. A piezoelectric vibration device comprising:
a lower substrate; an upper substrate cooperating with the lower substrate to form a vibration space between the lower substrate and the upper substrate; and a piezoelectric vibrator disposed within the vibration space, the piezoelectric vibrator including a vibration portion having an n-type Si layer which is a degenerated semiconductor and which has a resistivity of not less than 0.5 mΩcm and not greater than 0.9 mΩcm. 7. The piezoelectric vibration device according to claim 6, wherein the vibration portion has a piezoelectric thin film formed on the Si layer. 8. The piezoelectric vibration device according to claim 7, wherein the vibration portion further has a silicon oxide layer formed on at least one of an upper surface of the Si layer, a lower surface of the Si layer, and an upper surface of the piezoelectric thin film. 9. The piezoelectric vibration device according to claim 6, wherein the vibrator is planar and operates in an in plane vibration mode. 10. The piezoelectric vibration device according to claim 6, wherein the vibrator is planar and operates in an out of plane vibration mode. | 2,800 |
11,899 | 11,899 | 15,531,305 | 2,835 | Electronic device including a housing enclosing an electronic board and a heatsink having a first face applied against the electronic board and, opposite, a second face making contact with the housing, an antenna being electrically connected to the electronic board and extending flatly between the heatsink and the housing while making contact with the heatsink and the housing. | 1. An electronic device comprising a box containing an electronic card and a heatsink having a first face applied against the electronic card, and an opposite, second face having a portion in contact with the box, an antenna being electrically connected to the electronic card and extending flat at least in part between the heatsink and the box around the portion of the second face that is in contact with the box. 2. The electronic device according to claim 1, wherein the antenna is in contact with the heatsink and with the box. 3. The device according to claim 1, wherein the heatsink is electrically connected to the electrical ground of the electronic card. 4. The device according to claim 1, wherein the antenna extends in a groove made along an outline of the second face of the heatsink. 5. The device according to claim 4, wherein the antenna comprises a ring having an outer edge from which at least one radiating portion extends along a flank of the heatsink. 6. The device according to claim 5, wherein the heatsink has two flanks forming an angle between them and the antenna has at least two radiating portions, each extending along a respective one of the flanks of the heatsink. 7. The device according to claim 1, wherein the antenna is fastened to the box. 8. The device according to claim 7, wherein the fastening is achieved by heading. 9. The device according to claim 1, wherein the antenna is fastened to the heatsink. | Electronic device including a housing enclosing an electronic board and a heatsink having a first face applied against the electronic board and, opposite, a second face making contact with the housing, an antenna being electrically connected to the electronic board and extending flatly between the heatsink and the housing while making contact with the heatsink and the housing.1. An electronic device comprising a box containing an electronic card and a heatsink having a first face applied against the electronic card, and an opposite, second face having a portion in contact with the box, an antenna being electrically connected to the electronic card and extending flat at least in part between the heatsink and the box around the portion of the second face that is in contact with the box. 2. The electronic device according to claim 1, wherein the antenna is in contact with the heatsink and with the box. 3. The device according to claim 1, wherein the heatsink is electrically connected to the electrical ground of the electronic card. 4. The device according to claim 1, wherein the antenna extends in a groove made along an outline of the second face of the heatsink. 5. The device according to claim 4, wherein the antenna comprises a ring having an outer edge from which at least one radiating portion extends along a flank of the heatsink. 6. The device according to claim 5, wherein the heatsink has two flanks forming an angle between them and the antenna has at least two radiating portions, each extending along a respective one of the flanks of the heatsink. 7. The device according to claim 1, wherein the antenna is fastened to the box. 8. The device according to claim 7, wherein the fastening is achieved by heading. 9. The device according to claim 1, wherein the antenna is fastened to the heatsink. | 2,800 |
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