Unnamed: 0 int64 0 350k | level_0 int64 0 351k | ApplicationNumber int64 9.75M 96.1M | ArtUnit int64 1.6k 3.99k | Abstract stringlengths 1 8.37k | Claims stringlengths 3 292k | abstract-claims stringlengths 68 293k | TechCenter int64 1.6k 3.9k |
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11,900 | 11,900 | 15,457,416 | 2,861 | In an embodiment, an ice-prevention dam for a pitot tube includes a body and a head. The body includes a notch having a substantially planar back, and the head extends from the body and has a substantially planar side that is substantially parallel to the back of the notch. Such a dam can prevent ice accumulation in a pitot tube, and can facilitate proper positioning of the dam. For example, during manufacture of a pitot tube, an assembler inserts the dam into a hole in a side of a pitot-tube body having a front opening such that the head of the dam is located outside of the pitot-tube body and a body of the dam is located inside of the pitot-tube body. Next, the assembler positions the dam by causing the substantially planar side of the dam head to be substantially parallel with the front opening of the pitot-tube body. | 1. A dam for a pitot tube, the dam comprising:
a body including a notch having a substantially planar back; and a head extending from the body and having a substantially planar side that is substantially parallel to the back of the notch. 2. The dam of claim 1 wherein the body has a substantially cylindrical shape. 3. The dam of claim 1 wherein:
the body has a longitudinal axis; and
the back of the notch is substantially parallel to the longitudinal axis. 4. The dam of claim 1 wherein:
the body has a longitudinal axis and a diameter in a dimension that is normal to the longitudinal axis; and
the notch has a width that is less than the diameter. 5. The dam of claim 1 wherein:
the body has a longitudinal axis and a radius in a dimension that is normal to the longitudinal axis; and
the notch has a width that is greater than the radius. 6. A pitot tube, comprising:
a tube body defining an inlet; at least one hole formed in the tube body; and at least one dam respectively disposed within the at least one hole, each dam having a respective dam body that includes a notch having a substantially planar back that faces, and that is substantially parallel to, the inlet, at least a portion of the notch disposed inside of the tube body. 7. The pitot tube of claim 6 wherein the tube body is substantially cylindrical. 8. The pitot tube of claim 6, further comprising:
wherein the tube body includes an outer surface; and a groove formed in the outer surface of the tube body and intersecting at least one of the at least one dam. 9. The pitot tube of claim 6, further comprising:
wherein the tube body includes an outer surface; a groove formed in the outer surface of the tube body; and a heating coil disposed in the groove. 10. The pitot tube of claim 6, further comprising:
wherein the tube body includes an outer surface; a groove formed in the outer surface of the tube body and intersecting at least one of the at least one dam; and a heating coil disposed in the groove and contacting the at least one of the at least one dam. 11. The pitot tube of claim 6 wherein the notch of at least one of the at least one dam is entirely disposed inside of the tube body. 12. A pitot-tube assembly, comprising:
a flange configured for coupling to an aircraft and having an aircraft-facing side and an opposite side; a pitot-tube connector extending from the aircraft-facing side of the flange and configured for coupling to a speed determiner of an object; a strut extending from the opposite side of the flange; and a pitot tube, including
a tube body extending from the strut and having a front edge that defines an inlet, having an outlet in fluid communication with the pitot-tube connector, and having an outer surface,
at least one hole formed in the tube body,
at least one dam respectively disposed within the at least one hole, each dam having a respective dam body that includes a notch at least partially disposed within the tube body and having a substantially planar back that faces, and that is substantially parallel to, the front edge,
a groove formed in the outer surface of the tube body, and
a heating coil disposed in the groove. 13. The pitot-tube assembly of claim 12, further comprising a cover disposed over the outer surface of the tube body and over the heating coil. 14. The pitot-tube assembly of claim 12 wherein the pitot-tube connector includes a fluid connecter. 15. The pitot-tube assembly of claim 12 wherein the object includes an aircraft. 16. An aircraft, comprising:
a speed determiner having a first pitot-tube connector; a fuselage having an opening; and a pitot-tube assembly, comprising
a flange coupled to the fuselage over the opening,
a second pitot-tube connector extending from the flange and toward the opening, and coupled to the first pitot-tube connector,
a strut extending from the flange and away from the fuselage, and
a pitot tube, including
a tube body extending from the strut and having a front edge that defines an inlet, having an outlet in fluid communication with the speed determiner via the first and second pitot-tube connectors, and having an outer surface,
at least one hole formed in the tube body,
at least one dam respectively disposed within the at least one hole, each dam having a respective dam body that includes a notch at least partially disposed within the tube body and having a substantially planar back that faces, and that is substantially parallel to, the front edge, and
a groove formed in the outer surface of the tube body, and
a heating coil disposed in the groove. 17. A method, comprising:
inserting a dam into a hole in a side of a pitot-tube body having a front opening such that a head of the dam is located outside of the pitot-tube body and a body of the dam is located inside of the pitot-tube body; and positioning the dam by causing a substantially flat portion of the head of the dam to be substantially parallel with the front opening of the pitot-tube body. 18. The method of claim 17 wherein the head cannot be inserted into the hole. 19. The method of claim 17 wherein inserting the dam includes press fitting the dam into the hole. 20. The method of claim 17 wherein positioning the dam includes causing a substantially planar back of a notch formed in the body of the dam to be substantially parallel with the front opening of the pitot-tube body by causing the substantially flat portion of the head of the dam to be substantially parallel with the front opening of the pitot-tube body. 21. The method of claim 17, further comprising removing the head of the dam after causing the substantially flat portion of the head to be substantially parallel with the front opening of the pitot-tube body. 22. The method of claim 21, further comprising, after removing the head of the dam, forming, in an outside surface of the pitot-tube body, a heating-coil groove that intersects the dam. 23. The method of claim 17, further comprising brazing the dam to the pitot-tube body after positioning the dam. | In an embodiment, an ice-prevention dam for a pitot tube includes a body and a head. The body includes a notch having a substantially planar back, and the head extends from the body and has a substantially planar side that is substantially parallel to the back of the notch. Such a dam can prevent ice accumulation in a pitot tube, and can facilitate proper positioning of the dam. For example, during manufacture of a pitot tube, an assembler inserts the dam into a hole in a side of a pitot-tube body having a front opening such that the head of the dam is located outside of the pitot-tube body and a body of the dam is located inside of the pitot-tube body. Next, the assembler positions the dam by causing the substantially planar side of the dam head to be substantially parallel with the front opening of the pitot-tube body.1. A dam for a pitot tube, the dam comprising:
a body including a notch having a substantially planar back; and a head extending from the body and having a substantially planar side that is substantially parallel to the back of the notch. 2. The dam of claim 1 wherein the body has a substantially cylindrical shape. 3. The dam of claim 1 wherein:
the body has a longitudinal axis; and
the back of the notch is substantially parallel to the longitudinal axis. 4. The dam of claim 1 wherein:
the body has a longitudinal axis and a diameter in a dimension that is normal to the longitudinal axis; and
the notch has a width that is less than the diameter. 5. The dam of claim 1 wherein:
the body has a longitudinal axis and a radius in a dimension that is normal to the longitudinal axis; and
the notch has a width that is greater than the radius. 6. A pitot tube, comprising:
a tube body defining an inlet; at least one hole formed in the tube body; and at least one dam respectively disposed within the at least one hole, each dam having a respective dam body that includes a notch having a substantially planar back that faces, and that is substantially parallel to, the inlet, at least a portion of the notch disposed inside of the tube body. 7. The pitot tube of claim 6 wherein the tube body is substantially cylindrical. 8. The pitot tube of claim 6, further comprising:
wherein the tube body includes an outer surface; and a groove formed in the outer surface of the tube body and intersecting at least one of the at least one dam. 9. The pitot tube of claim 6, further comprising:
wherein the tube body includes an outer surface; a groove formed in the outer surface of the tube body; and a heating coil disposed in the groove. 10. The pitot tube of claim 6, further comprising:
wherein the tube body includes an outer surface; a groove formed in the outer surface of the tube body and intersecting at least one of the at least one dam; and a heating coil disposed in the groove and contacting the at least one of the at least one dam. 11. The pitot tube of claim 6 wherein the notch of at least one of the at least one dam is entirely disposed inside of the tube body. 12. A pitot-tube assembly, comprising:
a flange configured for coupling to an aircraft and having an aircraft-facing side and an opposite side; a pitot-tube connector extending from the aircraft-facing side of the flange and configured for coupling to a speed determiner of an object; a strut extending from the opposite side of the flange; and a pitot tube, including
a tube body extending from the strut and having a front edge that defines an inlet, having an outlet in fluid communication with the pitot-tube connector, and having an outer surface,
at least one hole formed in the tube body,
at least one dam respectively disposed within the at least one hole, each dam having a respective dam body that includes a notch at least partially disposed within the tube body and having a substantially planar back that faces, and that is substantially parallel to, the front edge,
a groove formed in the outer surface of the tube body, and
a heating coil disposed in the groove. 13. The pitot-tube assembly of claim 12, further comprising a cover disposed over the outer surface of the tube body and over the heating coil. 14. The pitot-tube assembly of claim 12 wherein the pitot-tube connector includes a fluid connecter. 15. The pitot-tube assembly of claim 12 wherein the object includes an aircraft. 16. An aircraft, comprising:
a speed determiner having a first pitot-tube connector; a fuselage having an opening; and a pitot-tube assembly, comprising
a flange coupled to the fuselage over the opening,
a second pitot-tube connector extending from the flange and toward the opening, and coupled to the first pitot-tube connector,
a strut extending from the flange and away from the fuselage, and
a pitot tube, including
a tube body extending from the strut and having a front edge that defines an inlet, having an outlet in fluid communication with the speed determiner via the first and second pitot-tube connectors, and having an outer surface,
at least one hole formed in the tube body,
at least one dam respectively disposed within the at least one hole, each dam having a respective dam body that includes a notch at least partially disposed within the tube body and having a substantially planar back that faces, and that is substantially parallel to, the front edge, and
a groove formed in the outer surface of the tube body, and
a heating coil disposed in the groove. 17. A method, comprising:
inserting a dam into a hole in a side of a pitot-tube body having a front opening such that a head of the dam is located outside of the pitot-tube body and a body of the dam is located inside of the pitot-tube body; and positioning the dam by causing a substantially flat portion of the head of the dam to be substantially parallel with the front opening of the pitot-tube body. 18. The method of claim 17 wherein the head cannot be inserted into the hole. 19. The method of claim 17 wherein inserting the dam includes press fitting the dam into the hole. 20. The method of claim 17 wherein positioning the dam includes causing a substantially planar back of a notch formed in the body of the dam to be substantially parallel with the front opening of the pitot-tube body by causing the substantially flat portion of the head of the dam to be substantially parallel with the front opening of the pitot-tube body. 21. The method of claim 17, further comprising removing the head of the dam after causing the substantially flat portion of the head to be substantially parallel with the front opening of the pitot-tube body. 22. The method of claim 21, further comprising, after removing the head of the dam, forming, in an outside surface of the pitot-tube body, a heating-coil groove that intersects the dam. 23. The method of claim 17, further comprising brazing the dam to the pitot-tube body after positioning the dam. | 2,800 |
11,901 | 11,901 | 13,852,825 | 2,883 | A fiber optic cable includes a tube, a stack of fiber optic ribbons twisting along a lengthwise axis through the tube, a support, and water-blocking tape positioned at least partially around the stack, between the stack and the tube. The support and water-blocking tape provide an elevated portion of the water-blocking tape that is raised. As the stack twists along the lengthwise axis of the tube, corners of the stack interface with the elevated portion to provide intermittent frictional coupling between the stack and the tube. | 1. A fiber optic cable, comprising:
a tube having an interior; a stack of fiber optic ribbons extending through the interior of the tube, wherein the stack twists along a lengthwise axis of the tube; a water-blocking tape positioned at least partially around the stack between the stack and the tube, in the interior of the tube; a support positioned between the water-blocking tape and the tube, in the interior of the tube, wherein the water-blocking tape at least partially overlays the support such that an elevated portion of the water-blocking tape is raised toward a lengthwise center of the interior of the tube, wherein, as the stack twists along the lengthwise axis of the tube at a position along the length of the cable in which a first cross-sectional dimension of the stack is aligned with the elevated portion, the stack interfaces with the elevated portion to provide frictional coupling between the stack and the tube, and wherein, at another position along the length of the cable in which a second cross-sectional dimension of the stack is aligned with the elevated portion, the stack has less frictional coupling with the tube. 2. The cable of claim 1, wherein the first cross-sectional dimension includes a corner of the stack, which, when aligned with the elevated portion, compresses the water-blocking tape and support against the interior of the tube. 3. The cable of claim 2, wherein the second cross-sectional dimension includes a side of the stack between corners, which, when aligned with the elevated portion, does not pin the water-blocking tape or support to the interior of the tube. 4. The cable of claim 3, wherein frictional coupling of the first cross-sectional dimension to the interior of the tube by way of the elevated portion of water-blocking tape is at least twice that of the second cross-sectional dimension. 5. The cable of claim 4, wherein frictional coupling of the first cross-sectional dimension to the interior of the tube by way of the elevated portion of water-blocking tape is at least ten times that of the second cross-sectional dimension. 6. The cable of claim 3, wherein, for a 30 meter length, the net force to pull the stack from the tube is at least 0.05 N per optical fiber in the stack facilitated by the frictional coupling provided by the water-blocking tape. 7. The cable of claim 6, wherein, for a 30 meter length, the net force to pull the stack from the tube is at least 0.1 N per optical fiber in the stack. 8. The cable of claim 7, wherein, for a 30 meter length, the net force to pull the stack from the tube is less than 1.0 N per optical fiber in the stack. 9. The cable of claim 1, wherein the support is at least one water-blocking yarn. 10. The cable of claim 1, wherein the support is a tape that is more rigid than the water-blocking tape. 11. The cable of claim 1, wherein the support is closer to the stack than the water-blocking tape is to the stack. 12. The cable of claim 1, wherein the water-blocking tape is a first water-blocking tape, and wherein the support is a second water-blocking tape. 13. The cable of claim 12, wherein the second water-blocking tape has less surface area than the first water-blocking tape. 14. The cable of claim 13, wherein the first water-blocking tape extends fully around the stack and the second water-blocking tape extend less than halfway around the stack. 15. The cable of claim 12, wherein the interior of the tube is round the elevated portion covers an arc of at least 15-degrees of the interior. 16. The cable of claim 15, wherein the elevated portion covers an arc of less than 90-degrees of the interior. 17. The cable of claim 1, wherein the support is such that the elevated portion extends at least 350 micrometers from the interior of the tube toward the center of the tube when uncompressed by the ribbon stack. 18. The cable of claim 17, wherein interaction with the first cross-sectional dimension of the stack compresses the elevated portion to less than 200 micrometers from the interior of the tube toward the center of tube. 19. A fiber optic cable, comprising:
a tube having an interior; an optical element comprising optical fibers extending through the interior of the tube, wherein the optical element twists along a lengthwise axis of the tube; a tape positioned at least partially around the optical element between the optical element and the tube, in the interior of the tube; a support positioned between the optical element and the tube, in the interior of the tube, wherein the tape at least partially overlays the support such that an elevated portion of either the support or the tape is raised toward a lengthwise center of the interior of the tube, wherein, as the optical element twists along the lengthwise axis of the tube at a position along the length of the cable in which a first cross-sectional dimension of the optical element is aligned with the elevated portion, the optical element interfaces with the elevated portion to provide frictional coupling between the optical element and the tube, and wherein, at another position along the length of the cable in which a second cross-sectional dimension of the optical element is aligned with the elevated portion, the optical element has less frictional coupling with the tube. 20. A method of manufacturing a cable, comprising steps of:
positioning a water-blocking tape around a stack of fiber optic ribbons; positioning a support adjacent to the water-blocking tape such that the tape overlays the support to form an elevated portion of either the support or the water-blocking tape; twisting the stack; extruding a tube around the stack, the support, and the water-blocking tape, wherein the water-blocking tape is positioned at least partially around the stack in the interior of the tube, between the stack and the tube, wherein the elevated portion is raised toward a lengthwise center of the interior of the tube,
wherein, as the stack twists along the lengthwise axis of the tube, at a position along the length of the cable in which a first cross-sectional dimension of the stack is aligned with the elevated portion, the stack interfaces with the elevated portion to provide frictional coupling between the stack and the tube, and
wherein, at another position along the length of the cable in which a second cross-sectional dimension of the stack is aligned with the elevated portion, the stack has less frictional coupling with the tube. | A fiber optic cable includes a tube, a stack of fiber optic ribbons twisting along a lengthwise axis through the tube, a support, and water-blocking tape positioned at least partially around the stack, between the stack and the tube. The support and water-blocking tape provide an elevated portion of the water-blocking tape that is raised. As the stack twists along the lengthwise axis of the tube, corners of the stack interface with the elevated portion to provide intermittent frictional coupling between the stack and the tube.1. A fiber optic cable, comprising:
a tube having an interior; a stack of fiber optic ribbons extending through the interior of the tube, wherein the stack twists along a lengthwise axis of the tube; a water-blocking tape positioned at least partially around the stack between the stack and the tube, in the interior of the tube; a support positioned between the water-blocking tape and the tube, in the interior of the tube, wherein the water-blocking tape at least partially overlays the support such that an elevated portion of the water-blocking tape is raised toward a lengthwise center of the interior of the tube, wherein, as the stack twists along the lengthwise axis of the tube at a position along the length of the cable in which a first cross-sectional dimension of the stack is aligned with the elevated portion, the stack interfaces with the elevated portion to provide frictional coupling between the stack and the tube, and wherein, at another position along the length of the cable in which a second cross-sectional dimension of the stack is aligned with the elevated portion, the stack has less frictional coupling with the tube. 2. The cable of claim 1, wherein the first cross-sectional dimension includes a corner of the stack, which, when aligned with the elevated portion, compresses the water-blocking tape and support against the interior of the tube. 3. The cable of claim 2, wherein the second cross-sectional dimension includes a side of the stack between corners, which, when aligned with the elevated portion, does not pin the water-blocking tape or support to the interior of the tube. 4. The cable of claim 3, wherein frictional coupling of the first cross-sectional dimension to the interior of the tube by way of the elevated portion of water-blocking tape is at least twice that of the second cross-sectional dimension. 5. The cable of claim 4, wherein frictional coupling of the first cross-sectional dimension to the interior of the tube by way of the elevated portion of water-blocking tape is at least ten times that of the second cross-sectional dimension. 6. The cable of claim 3, wherein, for a 30 meter length, the net force to pull the stack from the tube is at least 0.05 N per optical fiber in the stack facilitated by the frictional coupling provided by the water-blocking tape. 7. The cable of claim 6, wherein, for a 30 meter length, the net force to pull the stack from the tube is at least 0.1 N per optical fiber in the stack. 8. The cable of claim 7, wherein, for a 30 meter length, the net force to pull the stack from the tube is less than 1.0 N per optical fiber in the stack. 9. The cable of claim 1, wherein the support is at least one water-blocking yarn. 10. The cable of claim 1, wherein the support is a tape that is more rigid than the water-blocking tape. 11. The cable of claim 1, wherein the support is closer to the stack than the water-blocking tape is to the stack. 12. The cable of claim 1, wherein the water-blocking tape is a first water-blocking tape, and wherein the support is a second water-blocking tape. 13. The cable of claim 12, wherein the second water-blocking tape has less surface area than the first water-blocking tape. 14. The cable of claim 13, wherein the first water-blocking tape extends fully around the stack and the second water-blocking tape extend less than halfway around the stack. 15. The cable of claim 12, wherein the interior of the tube is round the elevated portion covers an arc of at least 15-degrees of the interior. 16. The cable of claim 15, wherein the elevated portion covers an arc of less than 90-degrees of the interior. 17. The cable of claim 1, wherein the support is such that the elevated portion extends at least 350 micrometers from the interior of the tube toward the center of the tube when uncompressed by the ribbon stack. 18. The cable of claim 17, wherein interaction with the first cross-sectional dimension of the stack compresses the elevated portion to less than 200 micrometers from the interior of the tube toward the center of tube. 19. A fiber optic cable, comprising:
a tube having an interior; an optical element comprising optical fibers extending through the interior of the tube, wherein the optical element twists along a lengthwise axis of the tube; a tape positioned at least partially around the optical element between the optical element and the tube, in the interior of the tube; a support positioned between the optical element and the tube, in the interior of the tube, wherein the tape at least partially overlays the support such that an elevated portion of either the support or the tape is raised toward a lengthwise center of the interior of the tube, wherein, as the optical element twists along the lengthwise axis of the tube at a position along the length of the cable in which a first cross-sectional dimension of the optical element is aligned with the elevated portion, the optical element interfaces with the elevated portion to provide frictional coupling between the optical element and the tube, and wherein, at another position along the length of the cable in which a second cross-sectional dimension of the optical element is aligned with the elevated portion, the optical element has less frictional coupling with the tube. 20. A method of manufacturing a cable, comprising steps of:
positioning a water-blocking tape around a stack of fiber optic ribbons; positioning a support adjacent to the water-blocking tape such that the tape overlays the support to form an elevated portion of either the support or the water-blocking tape; twisting the stack; extruding a tube around the stack, the support, and the water-blocking tape, wherein the water-blocking tape is positioned at least partially around the stack in the interior of the tube, between the stack and the tube, wherein the elevated portion is raised toward a lengthwise center of the interior of the tube,
wherein, as the stack twists along the lengthwise axis of the tube, at a position along the length of the cable in which a first cross-sectional dimension of the stack is aligned with the elevated portion, the stack interfaces with the elevated portion to provide frictional coupling between the stack and the tube, and
wherein, at another position along the length of the cable in which a second cross-sectional dimension of the stack is aligned with the elevated portion, the stack has less frictional coupling with the tube. | 2,800 |
11,902 | 11,902 | 14,802,066 | 2,855 | An apparatus for detecting a physical variable has a first sensor unit and a second sensor unit. The first sensor unit detects a physical variable on the basis of a first detection principle. Furthermore, the second sensor unit detects the physical variable on the basis of a second detection principle. In this case, the first detection principle differs from the second detection principle. The first sensor unit the second sensor unit are accommodated in a common housing. | 1. An apparatus for detecting a physical variable, having the following features:
a first sensor unit which is designed to detect a physical variable on the basis of a first detection principle; and a second sensor unit which is designed to detect the physical variable on the basis of a second detection principle, the first detection principle differing from the second detection principle, and the first sensor unit and the second sensor unit being accommodated in a common housing. 2. The apparatus as claimed in claim 1, the first sensor unit being a first semiconductor-based sensor unit and the second sensor unit being a second semiconductor-based sensor unit. 3. The apparatus as claimed in claim 1, the physical variable being a magnetic field. 4. The apparatus as claimed in claim 1, the first sensor unit having a Hall element which is designed to detect a magnetic field on the basis of the Hall effect. 5. The apparatus as claimed in claim 1, the second sensor unit having a magnetoresistive element which is designed to detect a magnetic field on the basis of the giant magnetoresistance effect, the magnetic tunnel resistance effect or the anisotropic magnetoresistive effect. 6. The apparatus as claimed in claim 1, the physical variable being a pressure. 7. The apparatus as claimed in claim 1, the first sensor unit having a piezoelectric pressure element which is designed to detect a pressure on the basis of the piezoelectric effect. 8. The apparatus as claimed in claim 1, the second sensor unit having a capacitive pressure element which is designed to detect a pressure on the basis of a capacitance which can be changed by pressure. 9. The apparatus as claimed in claim 1, the first sensor unit and the second sensor unit being implemented on different semiconductor chips. 10. The apparatus as claimed in claim 9, the semiconductor chip of the first sensor unit and the semiconductor chip of the second sensor unit being arranged beside one another on the same side of a common leadframe or being arranged opposite one another on different sides of a common leadframe. 11. The apparatus as claimed in claim 1, the first sensor unit and the second sensor unit being implemented on the same semiconductor chip. 12. The apparatus as claimed in claim 1, the common housing having molding compound which at least partially surrounds one or more semiconductor chips of the first sensor unit and of the second sensor unit. 13. The apparatus as claimed in claim 1, the common housing being a surface-mounted device gullwing, a surface-mounted device flat lead, a leadless QFN, a leadless TSLP or a P-SSO. 14. The apparatus as claimed in claim 1, the first sensor unit being designed to output a first sensor signal having information relating to the physical variable detected on the basis of the first detection principle, and the second sensor unit being designed to output a second sensor signal having information relating to the physical variable detected on the basis of the second detection principle. 15. A system for detecting a physical variable, having the following features:
an apparatus as claimed in claim 1; and an error recognition unit which is designed to recognize an error in the first sensor unit and/or in the second sensor unit on the basis of at least one first sensor signal provided by the first sensor unit and/or at least one second sensor signal provided by the second sensor unit. 16. The system as claimed in claim 15, the error recognition unit being designed to recognize an error on the basis of a comparison of the first sensor signal with the second sensor signal. 17. The system as claimed in claim 15, the error recognition unit being designed to recognize a change in an air gap between the common housing and a magnetic element on the basis of at least one first sensor signal provided by the first sensor unit and/or at least one second sensor signal provided by the second sensor unit. | An apparatus for detecting a physical variable has a first sensor unit and a second sensor unit. The first sensor unit detects a physical variable on the basis of a first detection principle. Furthermore, the second sensor unit detects the physical variable on the basis of a second detection principle. In this case, the first detection principle differs from the second detection principle. The first sensor unit the second sensor unit are accommodated in a common housing.1. An apparatus for detecting a physical variable, having the following features:
a first sensor unit which is designed to detect a physical variable on the basis of a first detection principle; and a second sensor unit which is designed to detect the physical variable on the basis of a second detection principle, the first detection principle differing from the second detection principle, and the first sensor unit and the second sensor unit being accommodated in a common housing. 2. The apparatus as claimed in claim 1, the first sensor unit being a first semiconductor-based sensor unit and the second sensor unit being a second semiconductor-based sensor unit. 3. The apparatus as claimed in claim 1, the physical variable being a magnetic field. 4. The apparatus as claimed in claim 1, the first sensor unit having a Hall element which is designed to detect a magnetic field on the basis of the Hall effect. 5. The apparatus as claimed in claim 1, the second sensor unit having a magnetoresistive element which is designed to detect a magnetic field on the basis of the giant magnetoresistance effect, the magnetic tunnel resistance effect or the anisotropic magnetoresistive effect. 6. The apparatus as claimed in claim 1, the physical variable being a pressure. 7. The apparatus as claimed in claim 1, the first sensor unit having a piezoelectric pressure element which is designed to detect a pressure on the basis of the piezoelectric effect. 8. The apparatus as claimed in claim 1, the second sensor unit having a capacitive pressure element which is designed to detect a pressure on the basis of a capacitance which can be changed by pressure. 9. The apparatus as claimed in claim 1, the first sensor unit and the second sensor unit being implemented on different semiconductor chips. 10. The apparatus as claimed in claim 9, the semiconductor chip of the first sensor unit and the semiconductor chip of the second sensor unit being arranged beside one another on the same side of a common leadframe or being arranged opposite one another on different sides of a common leadframe. 11. The apparatus as claimed in claim 1, the first sensor unit and the second sensor unit being implemented on the same semiconductor chip. 12. The apparatus as claimed in claim 1, the common housing having molding compound which at least partially surrounds one or more semiconductor chips of the first sensor unit and of the second sensor unit. 13. The apparatus as claimed in claim 1, the common housing being a surface-mounted device gullwing, a surface-mounted device flat lead, a leadless QFN, a leadless TSLP or a P-SSO. 14. The apparatus as claimed in claim 1, the first sensor unit being designed to output a first sensor signal having information relating to the physical variable detected on the basis of the first detection principle, and the second sensor unit being designed to output a second sensor signal having information relating to the physical variable detected on the basis of the second detection principle. 15. A system for detecting a physical variable, having the following features:
an apparatus as claimed in claim 1; and an error recognition unit which is designed to recognize an error in the first sensor unit and/or in the second sensor unit on the basis of at least one first sensor signal provided by the first sensor unit and/or at least one second sensor signal provided by the second sensor unit. 16. The system as claimed in claim 15, the error recognition unit being designed to recognize an error on the basis of a comparison of the first sensor signal with the second sensor signal. 17. The system as claimed in claim 15, the error recognition unit being designed to recognize a change in an air gap between the common housing and a magnetic element on the basis of at least one first sensor signal provided by the first sensor unit and/or at least one second sensor signal provided by the second sensor unit. | 2,800 |
11,903 | 11,903 | 14,757,918 | 2,859 | A method of wirelessly charging batteries of devices includes detecting at least two devices being simultaneously present on a charging mat. It is determined, for each of the at least two devices, whether the device is compatible with a wireless charging standard. It is determined, for each of the two devices, whether the device is enabled for a near field communication. Charging of the devices is prevented if at least one of the devices is enabled for a near field communication but not compatible with the wireless charging standard. | 1. A method of wirelessly charging batteries of devices, comprising:
detecting at least two devices being simultaneously present on a charging mat; determining, for each of the at least two devices, whether the device is compatible with a wireless charging standard; determining, for each of the at least two devices, whether the device is enabled for a near field communication; and preventing a charging of the devices if at least one of the devices is enabled for a near field communication but not compatible with the wireless charging standard. 2. The method of claim 1, wherein the detecting two devices comprises using a capacitive sensor. 3. The method of claim 1, wherein the detecting two devices comprises using a capacitive sensor to sense a change in capacitance associated with a grounded body placing one of the two devices onto the charging mat. 4. The method of claim 1, wherein the detecting two devices comprises measuring a change in charging impedance due to one of the at least two devices being introduced onto the charging mat. 5. The method of claim 1, wherein determining, for each of the at least two devices, whether the device is enabled for near field communication comprises using an near field communication (NFC) reader to determine whether a NFC standard compliant device is placed on the charging mat. 6. The method of claim 1, wherein the determining, for each of the at least two devices, whether the device is compatible with a wireless charging standard comprises receiving an A4WP standard compliant response from an A4WP compliant receiver. 7. The method of claim 6, wherein the determining, for each of the at least two devices, whether the device is enabled for near field communication comprises reading a bit in the A4WP standard compliant response that indicates existence of NFC in the device. 8. The method of claim 6, wherein the A4WP standard compliant response is a Bluetooth low energy response. 9. The method of claim 1, wherein each of the devices is a telephone, an near field communication tag, a tablet computer, a wearable device, and/or a laptop computer. 10. A system for wirelessly charging batteries of devices, comprising:
a transmission coil wirelessly transmitting electrical current to a first device present on a charging mat; a capacitive sensor detecting a second device being moved toward the charging mat while the first device is on the charging mat; a wireless communication device receiving signals from each of the first device and the second device, the signals indicating whether the device is compatible with a wireless charging standard; a Near Field Communication (NFC) reader determining, for each of the first device and the second device, whether the device is enabled for a near field communication; and an electronic processor communicatively coupled to each of the transmission coil, the capacitive sensor, the wireless communication device, and the NFC reader, the electronic processor to prevent the transmission coil from charging the devices if at least one of the first device and the second device is enabled for the near field communication but not compatible with the wireless charging standard. 11. The system of claim 10, wherein the capacitive sensor detects a change in capacitance associated with a grounded body placing the second device onto the charging mat. 12. The system of claim 11, wherein a sensing range of the capacitive sensor is greater than a reading range of a near field communication tag, and the reading range of a near field communication tag is greater than a distance from the charging mat at which a near field communication tag is damaged during charging. 13. The system of claim 10, further comprising a current sensor detecting a change in charging impedance due to the second device being introduced onto the charging mat. 14. The system of claim 10, wherein the NFC reader ascertains that a NFC standard compliant device has been placed on the charging mat. 15. The system of claim 10, wherein the wireless communication device receives an A4WP standard compliant response from an A4WP compliant receiver. 16. The system of claim 15, wherein the NFC reader reads a bit in the A4WP standard compliant response that indicates existence of a near field communication component in the device. 17. The system of claim 15, wherein the A4WP standard compliant response is a Bluetooth low energy response. 18. The system of claim 10, wherein each of the first device and the second device is a telephone, a near field communication tag, a tablet computer, and/or a laptop computer. 19. A non-transitory computer-readable medium comprising instructions that, when executed by a processor, control the processor to:
detect a first device being present on a charging mat; detect a second device being moved toward the charging mat while the first device is on the charging mat; determine, for each of the two devices, whether the device is compatible with a wireless charging standard; determine, for each of the two devices, whether the device is enabled for near field communication; and prevent charging the devices if at least one of the first device and the second device is enabled for the near field communication but not compatible with the wireless charging standard. 20. The non-transitory computer-readable medium of claim 19, wherein to detect a second device comprises to use a capacitive sensor to sense a change in capacitance associated with a grounded body placing the second device onto the charging mat. 21. The non-transitory computer-readable medium of claim 20, wherein a sensing range of the capacitive sensor is greater than a reading range of a near field communication tag, and the reading range of the near field communication tag is greater than a distance from the charging mat at which the near field communication tag is damaged during charging. 22. The non-transitory computer-readable medium of claim 19, wherein to detect a second device being moved toward the charging mat comprises to measure a change in charging impedance due to the second device being introduced onto the charging mat. 23. The non-transitory computer-readable medium of claim 19, wherein to determine, for each of the two devices, whether the device is enabled for near field communication comprises to use a Near Field Communication (NFC) reader to ascertain that a NFC standard compliant device has been placed on the charging mat. 24. The non-transitory computer-readable medium of claim 19, wherein to determine, for each of the first device and the second device, whether the device is compatible with the wireless charging standard comprises to receive an A4WP standard compliant response from an A4WP compliant receiver. 25. The non-transitory computer-readable medium of claim 24, wherein to determine, for each of the first device and the second device, whether the device is enabled for near field communication comprises to read a bit in the A4WP standard compliant response that indicates existence of a near field communication component in the device. | A method of wirelessly charging batteries of devices includes detecting at least two devices being simultaneously present on a charging mat. It is determined, for each of the at least two devices, whether the device is compatible with a wireless charging standard. It is determined, for each of the two devices, whether the device is enabled for a near field communication. Charging of the devices is prevented if at least one of the devices is enabled for a near field communication but not compatible with the wireless charging standard.1. A method of wirelessly charging batteries of devices, comprising:
detecting at least two devices being simultaneously present on a charging mat; determining, for each of the at least two devices, whether the device is compatible with a wireless charging standard; determining, for each of the at least two devices, whether the device is enabled for a near field communication; and preventing a charging of the devices if at least one of the devices is enabled for a near field communication but not compatible with the wireless charging standard. 2. The method of claim 1, wherein the detecting two devices comprises using a capacitive sensor. 3. The method of claim 1, wherein the detecting two devices comprises using a capacitive sensor to sense a change in capacitance associated with a grounded body placing one of the two devices onto the charging mat. 4. The method of claim 1, wherein the detecting two devices comprises measuring a change in charging impedance due to one of the at least two devices being introduced onto the charging mat. 5. The method of claim 1, wherein determining, for each of the at least two devices, whether the device is enabled for near field communication comprises using an near field communication (NFC) reader to determine whether a NFC standard compliant device is placed on the charging mat. 6. The method of claim 1, wherein the determining, for each of the at least two devices, whether the device is compatible with a wireless charging standard comprises receiving an A4WP standard compliant response from an A4WP compliant receiver. 7. The method of claim 6, wherein the determining, for each of the at least two devices, whether the device is enabled for near field communication comprises reading a bit in the A4WP standard compliant response that indicates existence of NFC in the device. 8. The method of claim 6, wherein the A4WP standard compliant response is a Bluetooth low energy response. 9. The method of claim 1, wherein each of the devices is a telephone, an near field communication tag, a tablet computer, a wearable device, and/or a laptop computer. 10. A system for wirelessly charging batteries of devices, comprising:
a transmission coil wirelessly transmitting electrical current to a first device present on a charging mat; a capacitive sensor detecting a second device being moved toward the charging mat while the first device is on the charging mat; a wireless communication device receiving signals from each of the first device and the second device, the signals indicating whether the device is compatible with a wireless charging standard; a Near Field Communication (NFC) reader determining, for each of the first device and the second device, whether the device is enabled for a near field communication; and an electronic processor communicatively coupled to each of the transmission coil, the capacitive sensor, the wireless communication device, and the NFC reader, the electronic processor to prevent the transmission coil from charging the devices if at least one of the first device and the second device is enabled for the near field communication but not compatible with the wireless charging standard. 11. The system of claim 10, wherein the capacitive sensor detects a change in capacitance associated with a grounded body placing the second device onto the charging mat. 12. The system of claim 11, wherein a sensing range of the capacitive sensor is greater than a reading range of a near field communication tag, and the reading range of a near field communication tag is greater than a distance from the charging mat at which a near field communication tag is damaged during charging. 13. The system of claim 10, further comprising a current sensor detecting a change in charging impedance due to the second device being introduced onto the charging mat. 14. The system of claim 10, wherein the NFC reader ascertains that a NFC standard compliant device has been placed on the charging mat. 15. The system of claim 10, wherein the wireless communication device receives an A4WP standard compliant response from an A4WP compliant receiver. 16. The system of claim 15, wherein the NFC reader reads a bit in the A4WP standard compliant response that indicates existence of a near field communication component in the device. 17. The system of claim 15, wherein the A4WP standard compliant response is a Bluetooth low energy response. 18. The system of claim 10, wherein each of the first device and the second device is a telephone, a near field communication tag, a tablet computer, and/or a laptop computer. 19. A non-transitory computer-readable medium comprising instructions that, when executed by a processor, control the processor to:
detect a first device being present on a charging mat; detect a second device being moved toward the charging mat while the first device is on the charging mat; determine, for each of the two devices, whether the device is compatible with a wireless charging standard; determine, for each of the two devices, whether the device is enabled for near field communication; and prevent charging the devices if at least one of the first device and the second device is enabled for the near field communication but not compatible with the wireless charging standard. 20. The non-transitory computer-readable medium of claim 19, wherein to detect a second device comprises to use a capacitive sensor to sense a change in capacitance associated with a grounded body placing the second device onto the charging mat. 21. The non-transitory computer-readable medium of claim 20, wherein a sensing range of the capacitive sensor is greater than a reading range of a near field communication tag, and the reading range of the near field communication tag is greater than a distance from the charging mat at which the near field communication tag is damaged during charging. 22. The non-transitory computer-readable medium of claim 19, wherein to detect a second device being moved toward the charging mat comprises to measure a change in charging impedance due to the second device being introduced onto the charging mat. 23. The non-transitory computer-readable medium of claim 19, wherein to determine, for each of the two devices, whether the device is enabled for near field communication comprises to use a Near Field Communication (NFC) reader to ascertain that a NFC standard compliant device has been placed on the charging mat. 24. The non-transitory computer-readable medium of claim 19, wherein to determine, for each of the first device and the second device, whether the device is compatible with the wireless charging standard comprises to receive an A4WP standard compliant response from an A4WP compliant receiver. 25. The non-transitory computer-readable medium of claim 24, wherein to determine, for each of the first device and the second device, whether the device is enabled for near field communication comprises to read a bit in the A4WP standard compliant response that indicates existence of a near field communication component in the device. | 2,800 |
11,904 | 11,904 | 15,435,777 | 2,834 | An electric machine includes a stator carrying two sets of multiphase windings. The sets are electrically isolated from each other and have an angular space displacement of A° electric corresponding to a torque ripple of harmonic order N. Responsive to current flow through the sets with a phase shift of A° electric, N±1 harmonic orders of resulting stator magnetic fields cancel to preclude formation of the torque ripple of harmonic order N. | 1. An electric machine comprising:
a stator carrying two sets of multiphase windings electrically isolated from each other and having an angular space displacement of A° electric corresponding to a torque ripple of harmonic order N such that, responsive to current flowing through the sets with a phase shift of A° electric, N±1 harmonic orders of resulting stator magnetic fields cancel to preclude formation of the torque ripple of harmonic order N. 2. The electric machine of claim 1, wherein fundamental orders of the stator magnetic fields are in phase. 3. The electric machine of claim 1, wherein a value of A° electric is equal to a quotient of 180° and N. 4. The electric machine of claim 1, wherein the sets are arranged in a single layer configuration. 5. The electric machine of claim 1, wherein the sets are arranged in a double layer configuration. 6. The electric machine of claim 1, wherein a value of N is a multiple of 6. 7. An automotive powertrain comprising:
an electric machine configured to provide propulsive force to wheels, and including a stator carrying two sets of multiphase windings electrically isolated from each other and having an angular space displacement of A° electric such that, responsive to current flowing through the sets with a phase shift of A° electric, fundamental orders of resulting stator magnetic fields are in phase and N±1 harmonic orders of the resulting stator magnetic fields cancel to preclude formation of a torque ripple of harmonic order N. 8. The automotive powertrain of claim 7, wherein a value of A° electric is equal to a quotient of 180° and N. 9. The automotive powertrain of claim 7, wherein the sets are arranged in a single layer configuration. 10. The automotive powertrain of claim 7, wherein the sets are arranged in a double layer configuration. 11. The automotive powertrain of claim 7, wherein a value of N is a multiple of 6. 12. The automotive powertrain of claim 7, wherein the electric machine is a 48-slot, 4-pole electric machine. 13. The automotive powertrain of claim 7, wherein each of the multiphase windings is a 3-phase winding. 14. An electric machine comprising:
a stator; and a plurality of sets of multiphase windings wound on the stator so as to be electrically isolated from each other and have an angular space displacement of A° electric, and configured to generate stator magnetic fields with N±1 harmonic orders that cancel to preclude formation of torque ripple of harmonic order N responsive to current flowing through the sets with a phase shift of A° electric. 15. The electric machine of claim 14, wherein fundamental orders of the stator magnetic fields are in phase. 16. The electric machine of claim 14, wherein a value of A° electric is equal to a quotient of 180° and N. 17. The electric machine of claim 14, wherein the sets are arranged in a single layer configuration. 18. The electric machine of claim 14, wherein the sets are arranged in a double layer configuration. 19. The electric machine of claim 14, wherein a value of N is a multiple of 6. | An electric machine includes a stator carrying two sets of multiphase windings. The sets are electrically isolated from each other and have an angular space displacement of A° electric corresponding to a torque ripple of harmonic order N. Responsive to current flow through the sets with a phase shift of A° electric, N±1 harmonic orders of resulting stator magnetic fields cancel to preclude formation of the torque ripple of harmonic order N.1. An electric machine comprising:
a stator carrying two sets of multiphase windings electrically isolated from each other and having an angular space displacement of A° electric corresponding to a torque ripple of harmonic order N such that, responsive to current flowing through the sets with a phase shift of A° electric, N±1 harmonic orders of resulting stator magnetic fields cancel to preclude formation of the torque ripple of harmonic order N. 2. The electric machine of claim 1, wherein fundamental orders of the stator magnetic fields are in phase. 3. The electric machine of claim 1, wherein a value of A° electric is equal to a quotient of 180° and N. 4. The electric machine of claim 1, wherein the sets are arranged in a single layer configuration. 5. The electric machine of claim 1, wherein the sets are arranged in a double layer configuration. 6. The electric machine of claim 1, wherein a value of N is a multiple of 6. 7. An automotive powertrain comprising:
an electric machine configured to provide propulsive force to wheels, and including a stator carrying two sets of multiphase windings electrically isolated from each other and having an angular space displacement of A° electric such that, responsive to current flowing through the sets with a phase shift of A° electric, fundamental orders of resulting stator magnetic fields are in phase and N±1 harmonic orders of the resulting stator magnetic fields cancel to preclude formation of a torque ripple of harmonic order N. 8. The automotive powertrain of claim 7, wherein a value of A° electric is equal to a quotient of 180° and N. 9. The automotive powertrain of claim 7, wherein the sets are arranged in a single layer configuration. 10. The automotive powertrain of claim 7, wherein the sets are arranged in a double layer configuration. 11. The automotive powertrain of claim 7, wherein a value of N is a multiple of 6. 12. The automotive powertrain of claim 7, wherein the electric machine is a 48-slot, 4-pole electric machine. 13. The automotive powertrain of claim 7, wherein each of the multiphase windings is a 3-phase winding. 14. An electric machine comprising:
a stator; and a plurality of sets of multiphase windings wound on the stator so as to be electrically isolated from each other and have an angular space displacement of A° electric, and configured to generate stator magnetic fields with N±1 harmonic orders that cancel to preclude formation of torque ripple of harmonic order N responsive to current flowing through the sets with a phase shift of A° electric. 15. The electric machine of claim 14, wherein fundamental orders of the stator magnetic fields are in phase. 16. The electric machine of claim 14, wherein a value of A° electric is equal to a quotient of 180° and N. 17. The electric machine of claim 14, wherein the sets are arranged in a single layer configuration. 18. The electric machine of claim 14, wherein the sets are arranged in a double layer configuration. 19. The electric machine of claim 14, wherein a value of N is a multiple of 6. | 2,800 |
11,905 | 11,905 | 15,397,485 | 2,836 | The systems and methods described herein relate to an adapter driver board for parallel operation of power modules. The systems and methods receive an electrical signal at an input interface of a high voltage adapter board. The systems and methods further deliver the electrical signals to first and second switches along corresponding first and second conductive traces. The first conductive trace extends along the high voltage adapter board and is conductively coupled to the input interface and the first switch. The second conductive trace extending along the high voltage adapter board and is conductively coupled to the input interface and the second switch. The first and second conductive traces are each configured to have an inductance substantially the same. The systems and methods synchronously activate the first and second switches based on the electrical signal. | 1. A system comprising:
a high voltage adapter board coupled to a first module and a second module, wherein the first module is conductively coupled to a first terminal of the high voltage adapter board, a first conductive trace extending along the high voltage adapter board and is conductively coupled to the first terminal, the second module conductively coupled to a second terminal of the high voltage adapter board and a second conductive trace extending along the high voltage adapter board and is conductively coupled to the second terminal, wherein the first conductive trace and the second conductive trace are each conductively coupled to an input interface; and a first switch of the first module and a second switch of the second module, wherein the first switch is conductively coupled to the first terminal and the second switch is conductively coupled to the second terminal, wherein the first and second conductive traces are configured to have an inductance substantially the same such that the first and second conductive traces are configured to synchronously activate the first and second switches. 2. The module system of claim 1, further comprising a driver circuit conductively coupled to the input interface, the driver circuit being configured to communicate an electrical signal to the high voltage adapter board. 3. The module system of claim 2, wherein the driver circuit is positioned remotely with respect to the high voltage adapter board. 4. The module system of claim 2, wherein the driver circuit is mounted to the high voltage adapter board. 5. The module system of claim 1, wherein the high voltage adapter board includes a driver circuit, wherein the driver circuit is configured to communicate an electrical signal to the input interface. 6. The module system of claim 1, wherein a geometric shape of at least one of the first conductive trace or the second conductive trace are configured such that the respective inductances of the first conductive trace and the second conductive trace are substantially the same. 7. The module system of claim 6, wherein the geometric shape corresponds to a cross-sectional area or a length. 8. The module system of claim 1, wherein the first and second switches are wide-bandgap semiconductors, the first and second switches include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, cadmium telluride, aluminum gallium nitride, or gallium nitride. 9. The module system of claim 1, wherein, a clamping circuit is conductively coupled to each of the terminal pairs of the high voltage board. 10. The module system of claim 1, further comprising a fourth and fifth conductive traces, wherein the first and fourth conductive traces represent a first pair of conductive traces extending along first adjacent layers of the high voltage adapter board, and the second and fifth conductive traces correspond to a second pair of conductive traces extending along second adjacent layers. 11. The module system of claim 10, wherein a spatial relationship between the first and fourth conductive traces are configured such that the inductances of the first pair of conductive traces and the second conductive traces are substantially the same. 12. The module system of claim 11, wherein the spatial relationship corresponds to at least one of a distance between the first and fourth of conductive traces with respect to each other, or a lateral offset between the first and fourth conductive traces with respect to each other. 13. The module system of claim 1, wherein the input interface includes at least one of a connector, a cable, or a flexible circuit board. 14. The module system of claim 1, wherein the first and second modules each include an upper switch and a lower switch such that the first switch and second switch correspond to one of the upper switch or the lower switch. 15. A method comprising:
receiving an electrical signal at an input interface of a high voltage adapter board; delivering the electrical signals to first and second switches along corresponding first and second conductive traces, wherein the first conductive trace extends along the high voltage adapter board and is conductively coupled to the input interface and the first switch, the second conductive trace extending along the high voltage adapter board and is conductively coupled to the input interface and the second switch, wherein the first and second conductive traces are each configured to have an inductance substantially the same; and synchronously activating the first and second switches based on the electrical signal. 16. The method of claim 15, further comprising delivering the electrical signal to the input interface from a driver circuit conductively coupled to the input interface, wherein the driver circuit board is positioned remotely with respect to the high voltage adapter board or is mounted to the high voltage adapter board. 17. The method of claim 15, further comprising adjusting a geometric shape of at least one of the first conductive trace or the second conductive trace to configure the respective inductances of the first and second conductive traces to be substantially the same, wherein the adjusting of the geometric shape includes at least one of adjusting a cross-sectional area or a length. 18. The method of claim 15, wherein the first conductive trace corresponds to a first pair of conductive traces extending along first adjacent layers of the high voltage adapter board, and the second conductive trace corresponds to a second pair of conductive traces extending along second adjacent layers; and
further comprising adjusting a spatial relationship between at least one of the first pair of conductive traces or the second pair of conductive traces to adjust the inductance to be substantially the same. 19. The method of claim 15, wherein the first and second switches are fitted with wide-bandgap semiconductors, wherein the first and second switches include silicon carbide or gallium nitride. 20. A system comprising:
a high voltage adapter board connected to a plurality of modules, wherein each module includes a first switch conductively coupled to an input interface through conductive traces along the high voltage board, each of the conductive traces are configured to have an inductance substantially the same such that the conductive traces are configured to synchronously activate the corresponding first switches based on an electrical signal; and a driver circuit positioned remotely with respect to the high voltage adapter board, wherein the driver circuit is conductively coupled to the input interface and communicate the electrical signal to the high voltage adapter board. | The systems and methods described herein relate to an adapter driver board for parallel operation of power modules. The systems and methods receive an electrical signal at an input interface of a high voltage adapter board. The systems and methods further deliver the electrical signals to first and second switches along corresponding first and second conductive traces. The first conductive trace extends along the high voltage adapter board and is conductively coupled to the input interface and the first switch. The second conductive trace extending along the high voltage adapter board and is conductively coupled to the input interface and the second switch. The first and second conductive traces are each configured to have an inductance substantially the same. The systems and methods synchronously activate the first and second switches based on the electrical signal.1. A system comprising:
a high voltage adapter board coupled to a first module and a second module, wherein the first module is conductively coupled to a first terminal of the high voltage adapter board, a first conductive trace extending along the high voltage adapter board and is conductively coupled to the first terminal, the second module conductively coupled to a second terminal of the high voltage adapter board and a second conductive trace extending along the high voltage adapter board and is conductively coupled to the second terminal, wherein the first conductive trace and the second conductive trace are each conductively coupled to an input interface; and a first switch of the first module and a second switch of the second module, wherein the first switch is conductively coupled to the first terminal and the second switch is conductively coupled to the second terminal, wherein the first and second conductive traces are configured to have an inductance substantially the same such that the first and second conductive traces are configured to synchronously activate the first and second switches. 2. The module system of claim 1, further comprising a driver circuit conductively coupled to the input interface, the driver circuit being configured to communicate an electrical signal to the high voltage adapter board. 3. The module system of claim 2, wherein the driver circuit is positioned remotely with respect to the high voltage adapter board. 4. The module system of claim 2, wherein the driver circuit is mounted to the high voltage adapter board. 5. The module system of claim 1, wherein the high voltage adapter board includes a driver circuit, wherein the driver circuit is configured to communicate an electrical signal to the input interface. 6. The module system of claim 1, wherein a geometric shape of at least one of the first conductive trace or the second conductive trace are configured such that the respective inductances of the first conductive trace and the second conductive trace are substantially the same. 7. The module system of claim 6, wherein the geometric shape corresponds to a cross-sectional area or a length. 8. The module system of claim 1, wherein the first and second switches are wide-bandgap semiconductors, the first and second switches include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, cadmium telluride, aluminum gallium nitride, or gallium nitride. 9. The module system of claim 1, wherein, a clamping circuit is conductively coupled to each of the terminal pairs of the high voltage board. 10. The module system of claim 1, further comprising a fourth and fifth conductive traces, wherein the first and fourth conductive traces represent a first pair of conductive traces extending along first adjacent layers of the high voltage adapter board, and the second and fifth conductive traces correspond to a second pair of conductive traces extending along second adjacent layers. 11. The module system of claim 10, wherein a spatial relationship between the first and fourth conductive traces are configured such that the inductances of the first pair of conductive traces and the second conductive traces are substantially the same. 12. The module system of claim 11, wherein the spatial relationship corresponds to at least one of a distance between the first and fourth of conductive traces with respect to each other, or a lateral offset between the first and fourth conductive traces with respect to each other. 13. The module system of claim 1, wherein the input interface includes at least one of a connector, a cable, or a flexible circuit board. 14. The module system of claim 1, wherein the first and second modules each include an upper switch and a lower switch such that the first switch and second switch correspond to one of the upper switch or the lower switch. 15. A method comprising:
receiving an electrical signal at an input interface of a high voltage adapter board; delivering the electrical signals to first and second switches along corresponding first and second conductive traces, wherein the first conductive trace extends along the high voltage adapter board and is conductively coupled to the input interface and the first switch, the second conductive trace extending along the high voltage adapter board and is conductively coupled to the input interface and the second switch, wherein the first and second conductive traces are each configured to have an inductance substantially the same; and synchronously activating the first and second switches based on the electrical signal. 16. The method of claim 15, further comprising delivering the electrical signal to the input interface from a driver circuit conductively coupled to the input interface, wherein the driver circuit board is positioned remotely with respect to the high voltage adapter board or is mounted to the high voltage adapter board. 17. The method of claim 15, further comprising adjusting a geometric shape of at least one of the first conductive trace or the second conductive trace to configure the respective inductances of the first and second conductive traces to be substantially the same, wherein the adjusting of the geometric shape includes at least one of adjusting a cross-sectional area or a length. 18. The method of claim 15, wherein the first conductive trace corresponds to a first pair of conductive traces extending along first adjacent layers of the high voltage adapter board, and the second conductive trace corresponds to a second pair of conductive traces extending along second adjacent layers; and
further comprising adjusting a spatial relationship between at least one of the first pair of conductive traces or the second pair of conductive traces to adjust the inductance to be substantially the same. 19. The method of claim 15, wherein the first and second switches are fitted with wide-bandgap semiconductors, wherein the first and second switches include silicon carbide or gallium nitride. 20. A system comprising:
a high voltage adapter board connected to a plurality of modules, wherein each module includes a first switch conductively coupled to an input interface through conductive traces along the high voltage board, each of the conductive traces are configured to have an inductance substantially the same such that the conductive traces are configured to synchronously activate the corresponding first switches based on an electrical signal; and a driver circuit positioned remotely with respect to the high voltage adapter board, wherein the driver circuit is conductively coupled to the input interface and communicate the electrical signal to the high voltage adapter board. | 2,800 |
11,906 | 11,906 | 15,216,398 | 2,886 | Apparatus and associated methods relate to sampling a large volume of a cloud atmosphere so as to obtain a large signal response from even a sparse distribution of water droplets in the cloud atmosphere. Such a volume can be probed by projecting an uncollimated optical beam into the cloud atmosphere and sampling the signal backscattered from the water droplets located within the probed volume. The uncollimated optical beam can be generated by projecting a diverging pulse of light energy from a polished end of a first optical fiber. A second optical fiber can be used to receive the optical signal backscattered from the cloud atmosphere. The second optical fiber can also have substantially the same field of view as the first optical fiber, so as to receive signals from a volume of the cloud atmosphere that is substantially commensurate with the probed volume. | 1. A system for measuring cloud conditions comprising:
a laser diode configured to generate a pulse of light energy; a transmitter fiber configured to receive the generated pulse of light energy and to project the received pulse of light energy into a cloud atmosphere, the projected pulse of light energy projected over a field of view determined by a numerical aperture of a transmission end of the transmitter fiber; a receiver fiber having a reception end aligned proximate and substantially parallel to the transmission end of the transmitter fiber, the receiver fiber configured to receive a portion of the transmitted pulse of light energy backscattered by the cloud atmosphere; and a detector configured to detect the portion of the transmitted pulse of light energy received by the receiver fiber, wherein a numerical aperture of the reception end of the receiver fiber is substantially equal to the numerical aperture of the transmission end of the transmitter fiber. 2. The system of claim 1, wherein the numerical apertures of the transmission end of the transmitter fiber and the reception end of the receiving fiber are greater than a predetermined threshold. 3. The system of claim 2, wherein the predetermined threshold is 0.25. 4. The system of claim 2, wherein the predetermined threshold is 0.3. 5. The system of claim 2, wherein the predetermined threshold is 0.35. 6. The system of claim 1, further comprising:
a processor configured to calculate a super-cooled large droplet size based on the detected portion of the transmitted light energy received by the receiver fiber. 7. The system of claim 1, wherein the laser diode is a first laser diode, the pulse of light energy is a first pulse of light energy of a first wavelength, the transmitter fiber is a first transmitter fiber, the receiver fiber is a first receiver fiber, and the detector is a first detector, the cloud conditions measurement system further comprising:
a second laser diode configured to generate a second pulse of light energy of a second wavelength different from the first wavelength; and a second detector configured to detect the portion of the second pulse of light energy backscattered by the cloud atmosphere. 8. The system of claim 7, further comprising:
a second transmitter fiber configured to receive the generated second pulse of light energy and to project the received second pulse of light energy into a cloud atmosphere, the projected second pulse of light energy projected over a field of view determined by a numerical aperture of a second transmission end of the second transmitter fiber; and a second receiver fiber having a reception end aligned proximate and substantially parallel to the transmission end of the second transmitter fiber, the second receiver fiber configured to receive a portion of the transmitted second pulse of light energy backscattered by the cloud atmosphere; wherein a numerical aperture of the reception end of the second receiver fiber is substantially equal to the numerical aperture of the transmission end of the second transmitter fiber. 9. The system of claim 8, further comprising:
a third receiver fiber having a reception end aligned proximate and substantially parallel to the transmission end of the second transmitter fiber, the third receiver fiber configured to receive a portion of the transmitted second pulse of light energy backscattered by the cloud atmosphere; and a third detector configured to detect the portion of the transmitted second pulse of light energy received by the receiver fiber, wherein a numerical aperture of the reception end of the third receiver fiber is substantially equal to the numerical aperture of the transmission end of the second transmitter fiber. 10. The system of claim 9, further comprising:
a circular polarizing element configured to circularly polarize the second pulse of light energy, wherein the second and third detectors are configured to detect circularly polarized light energy of opposite polarization directions. 11. The system of claim 7, wherein the second pulse of light energy is a collimated beam. 12. A method for measuring cloud parameters, the method comprising:
generating a pulse of light energy; diverging the generated pulse of light energy over a first solid angle greater than a predetermined threshold; projecting the diverged pulse of light energy into a cloud atmosphere, wherein the projected pulse is projected in a projection direction aligned with a directional axis; receiving a portion of the projected pulse of light energy backscattered by the cloud atmosphere, wherein the received portion is received over a second solid angle substantially equal to the first solid angle of the diverged pulse, and wherein the received portion is received from a reception direction substantially parallel to the directional axis; and detecting the received portion of the projected pulse of light energy. 13. The method of claim 12, wherein the predetermined threshold is 0.3 steradians. 14. The method of claim 12, wherein the predetermined threshold is 0.4 steradians. 15. The method of claim 12, wherein the predetermined threshold is 0.5 steradians. 16. The method of claim 12, further comprising:
calculating a super-cooled large droplet size based on the detected received portion of the projected pulse of light energy. 17. The method of claim 12, wherein the pulse of light energy is a first pulse of light energy of a first wavelength, the projection direction is a first projection direction, and the reception direction is a first reception direction, the method further comprising:
generating a second pulse of light energy; and projecting the generated second pulse of light energy into the cloud atmosphere, wherein the projected second pulse of light energy is projected in a second projection direction; receiving a portion of the projected second pulse of light energy backscattered by the cloud atmosphere, wherein the received portion is received from a second reception direction substantially parallel to the second projection direction; and detecting the received portion of the second pulse of light energy. 18. The method of claim 17, further comprising:
diverging the generated second pulse of light energy over a third solid angle, wherein the third solid angle is substantially equal to the first solid angle. 19. The method of claim 17, wherein the second pulse of light energy is a collimated beam. 20. The method of claim 17, wherein detecting the received portion of the second pulse of light energy comprises detecting a left-hand circularly polarized portion of the second pulse of light energy, the method further comprising:
circularly polarizing the second pulse of light energy; and detecting a right-hand circularly polarized portion of the second pulse of light energy. | Apparatus and associated methods relate to sampling a large volume of a cloud atmosphere so as to obtain a large signal response from even a sparse distribution of water droplets in the cloud atmosphere. Such a volume can be probed by projecting an uncollimated optical beam into the cloud atmosphere and sampling the signal backscattered from the water droplets located within the probed volume. The uncollimated optical beam can be generated by projecting a diverging pulse of light energy from a polished end of a first optical fiber. A second optical fiber can be used to receive the optical signal backscattered from the cloud atmosphere. The second optical fiber can also have substantially the same field of view as the first optical fiber, so as to receive signals from a volume of the cloud atmosphere that is substantially commensurate with the probed volume.1. A system for measuring cloud conditions comprising:
a laser diode configured to generate a pulse of light energy; a transmitter fiber configured to receive the generated pulse of light energy and to project the received pulse of light energy into a cloud atmosphere, the projected pulse of light energy projected over a field of view determined by a numerical aperture of a transmission end of the transmitter fiber; a receiver fiber having a reception end aligned proximate and substantially parallel to the transmission end of the transmitter fiber, the receiver fiber configured to receive a portion of the transmitted pulse of light energy backscattered by the cloud atmosphere; and a detector configured to detect the portion of the transmitted pulse of light energy received by the receiver fiber, wherein a numerical aperture of the reception end of the receiver fiber is substantially equal to the numerical aperture of the transmission end of the transmitter fiber. 2. The system of claim 1, wherein the numerical apertures of the transmission end of the transmitter fiber and the reception end of the receiving fiber are greater than a predetermined threshold. 3. The system of claim 2, wherein the predetermined threshold is 0.25. 4. The system of claim 2, wherein the predetermined threshold is 0.3. 5. The system of claim 2, wherein the predetermined threshold is 0.35. 6. The system of claim 1, further comprising:
a processor configured to calculate a super-cooled large droplet size based on the detected portion of the transmitted light energy received by the receiver fiber. 7. The system of claim 1, wherein the laser diode is a first laser diode, the pulse of light energy is a first pulse of light energy of a first wavelength, the transmitter fiber is a first transmitter fiber, the receiver fiber is a first receiver fiber, and the detector is a first detector, the cloud conditions measurement system further comprising:
a second laser diode configured to generate a second pulse of light energy of a second wavelength different from the first wavelength; and a second detector configured to detect the portion of the second pulse of light energy backscattered by the cloud atmosphere. 8. The system of claim 7, further comprising:
a second transmitter fiber configured to receive the generated second pulse of light energy and to project the received second pulse of light energy into a cloud atmosphere, the projected second pulse of light energy projected over a field of view determined by a numerical aperture of a second transmission end of the second transmitter fiber; and a second receiver fiber having a reception end aligned proximate and substantially parallel to the transmission end of the second transmitter fiber, the second receiver fiber configured to receive a portion of the transmitted second pulse of light energy backscattered by the cloud atmosphere; wherein a numerical aperture of the reception end of the second receiver fiber is substantially equal to the numerical aperture of the transmission end of the second transmitter fiber. 9. The system of claim 8, further comprising:
a third receiver fiber having a reception end aligned proximate and substantially parallel to the transmission end of the second transmitter fiber, the third receiver fiber configured to receive a portion of the transmitted second pulse of light energy backscattered by the cloud atmosphere; and a third detector configured to detect the portion of the transmitted second pulse of light energy received by the receiver fiber, wherein a numerical aperture of the reception end of the third receiver fiber is substantially equal to the numerical aperture of the transmission end of the second transmitter fiber. 10. The system of claim 9, further comprising:
a circular polarizing element configured to circularly polarize the second pulse of light energy, wherein the second and third detectors are configured to detect circularly polarized light energy of opposite polarization directions. 11. The system of claim 7, wherein the second pulse of light energy is a collimated beam. 12. A method for measuring cloud parameters, the method comprising:
generating a pulse of light energy; diverging the generated pulse of light energy over a first solid angle greater than a predetermined threshold; projecting the diverged pulse of light energy into a cloud atmosphere, wherein the projected pulse is projected in a projection direction aligned with a directional axis; receiving a portion of the projected pulse of light energy backscattered by the cloud atmosphere, wherein the received portion is received over a second solid angle substantially equal to the first solid angle of the diverged pulse, and wherein the received portion is received from a reception direction substantially parallel to the directional axis; and detecting the received portion of the projected pulse of light energy. 13. The method of claim 12, wherein the predetermined threshold is 0.3 steradians. 14. The method of claim 12, wherein the predetermined threshold is 0.4 steradians. 15. The method of claim 12, wherein the predetermined threshold is 0.5 steradians. 16. The method of claim 12, further comprising:
calculating a super-cooled large droplet size based on the detected received portion of the projected pulse of light energy. 17. The method of claim 12, wherein the pulse of light energy is a first pulse of light energy of a first wavelength, the projection direction is a first projection direction, and the reception direction is a first reception direction, the method further comprising:
generating a second pulse of light energy; and projecting the generated second pulse of light energy into the cloud atmosphere, wherein the projected second pulse of light energy is projected in a second projection direction; receiving a portion of the projected second pulse of light energy backscattered by the cloud atmosphere, wherein the received portion is received from a second reception direction substantially parallel to the second projection direction; and detecting the received portion of the second pulse of light energy. 18. The method of claim 17, further comprising:
diverging the generated second pulse of light energy over a third solid angle, wherein the third solid angle is substantially equal to the first solid angle. 19. The method of claim 17, wherein the second pulse of light energy is a collimated beam. 20. The method of claim 17, wherein detecting the received portion of the second pulse of light energy comprises detecting a left-hand circularly polarized portion of the second pulse of light energy, the method further comprising:
circularly polarizing the second pulse of light energy; and detecting a right-hand circularly polarized portion of the second pulse of light energy. | 2,800 |
11,907 | 11,907 | 16,174,361 | 2,839 | Systems and methods for balancing phase currents of the phases of a multiphase converter include alternately connecting the phases during respective intervals to an input current and sampling, at a node of the multiphase converter that is common to the phases, the input current provided to the phases to obtain respective input current samples for the phases. While the input current samples are unequal, the intervals are adjusted to minimize inequality of the input current samples and thereby balance the phase currents. | 1. A method for balancing phase currents of a plurality of phases of a multiphase converter, the method comprising:
alternately connecting the phases during respective intervals to an input current; generating trigger signals at successive time instants respectively for the phases, wherein the trigger signals are synchronous in that the trigger signals are generated at a same time following the connection of the phases to the input current; sampling, at the time instants in response to the trigger signals, at a node of the multiphase converter that is common to the phases, the input current provided to the phases to obtain respective input current samples for the phases; and while the input current samples are unequal, adjusting the intervals based only on differences between the input current samples to minimize inequality of the input current samples. 2-3. (canceled) 4. The method of claim 1 wherein:
the node of the multiphase converter that is common to the phases is connected to a DC-link capacitor of the multiphase converter. 5. The method of claim 1 wherein:
adjusting the intervals includes increasing the interval for a phase having an input current sample lower than an average of the input current samples to increase the input current provided to the phase; and
adjusting the intervals includes decreasing the interval for a phase having an input current sample greater than the average of the input current samples to decrease the input current provided to the phase. 6. The method of claim 1 wherein:
each phase includes an inductor, the inductors of the phases have a same inductor value and tolerance. 7. The method of claim 1 wherein:
the intervals initially are the same. 8. A system for balancing phase currents of a plurality of phases of a multiphase converter, the system comprising:
a controller configured to alternately connect the phases during respective intervals to an input current from a power source and to generate trigger signals at successive time instants respectively for the phases, wherein the trigger signals are synchronous in that the trigger signals are generated at a same time following the connection of the phases to the input current; a current sensor configured to sample, at the time instants in response to the trigger signals, at a node of the multiphase converter that is common to the phases, the input current provided to the phases to obtain respective input current samples for the phases, wherein the current sensor includes a current shunt connected in series between the power source and the node; and wherein the controller is further configured to adjust the intervals based only on differences between the input current samples to minimize inequality of the input current samples. 9-10. (canceled) 11. The system of claim 8 wherein:
the node of the multiphase converter that is common to the phases is connected to a DC-link capacitor of the multiphase converter. 12. The system of claim 8 wherein:
the controller is further configured to adjust the intervals includes increasing the interval for a phase having an input current sample lower than an average of the input current samples to increase the input current provided to the phase; and
the controller is further configured to adjust the intervals includes decreasing the interval for a phase having an input current sample greater than the average of the input current samples to decrease the input current provided to the phase. 13. The system of claim 8 wherein:
each phase includes an inductor, the inductors of the phases have a same inductor value and tolerance. 14. The system of claim 8 wherein:
the intervals initially are the same. 15. A converter for converting DC voltage levels, comprising:
a plurality of phases connected in parallel to a common node; a power source configured to provide an input current to the common node; a controller configured to alternately connect the phases during respective intervals to the input current at the common node and to generate trigger signals at successive time instants respectively for the phases, wherein the trigger signals are synchronous in that the trigger signals are generated at a same time following the connection of the phases to the input current; a current sensor having a current shunt connected in series between the power source and the common node, the current sensor configured to sample, at the time instants in response to the trigger signals, the input current provided to the phases to obtain respective input current samples for the phases; and the controller is further configured to adjust the intervals based only on differences between the input current samples to minimize inequality of the input current samples. 16-17. (canceled) 18. The converter of claim 15 further comprising:
a DC-link capacitor connected to the common node. 19. The converter of claim 15 wherein:
the controller is further configured to adjust the intervals includes increasing the interval for a phase having an input current sample lower than an average of the input current samples to increase the input current provided to the phase; and
the controller is further configured to adjust the intervals includes decreasing the interval for a phase having an input current sample greater than the average of the input current samples to decrease the input current provided to the phase. 20. The converter of claim 15 wherein:
each phase includes an inductor, the inductors of the phases have a same inductor value and tolerance. 21. The method of claim 1 wherein:
each time instant at which a corresponding trigger signal is generated occurs after M cycles of the phases have been alternately connected to the input current, wherein M is an integer greater than one. 22. The system of claim 8 wherein:
each time instant at which a corresponding trigger signal is generated occurs after M cycles of the phases have been alternately connected to the input current, wherein M is an integer greater than one. 23. The converter of claim 15 wherein:
each time instant at which a corresponding trigger signal is generated occurs after M cycles of the phases have been alternately connected to the input current, wherein M is an integer greater than one. | Systems and methods for balancing phase currents of the phases of a multiphase converter include alternately connecting the phases during respective intervals to an input current and sampling, at a node of the multiphase converter that is common to the phases, the input current provided to the phases to obtain respective input current samples for the phases. While the input current samples are unequal, the intervals are adjusted to minimize inequality of the input current samples and thereby balance the phase currents.1. A method for balancing phase currents of a plurality of phases of a multiphase converter, the method comprising:
alternately connecting the phases during respective intervals to an input current; generating trigger signals at successive time instants respectively for the phases, wherein the trigger signals are synchronous in that the trigger signals are generated at a same time following the connection of the phases to the input current; sampling, at the time instants in response to the trigger signals, at a node of the multiphase converter that is common to the phases, the input current provided to the phases to obtain respective input current samples for the phases; and while the input current samples are unequal, adjusting the intervals based only on differences between the input current samples to minimize inequality of the input current samples. 2-3. (canceled) 4. The method of claim 1 wherein:
the node of the multiphase converter that is common to the phases is connected to a DC-link capacitor of the multiphase converter. 5. The method of claim 1 wherein:
adjusting the intervals includes increasing the interval for a phase having an input current sample lower than an average of the input current samples to increase the input current provided to the phase; and
adjusting the intervals includes decreasing the interval for a phase having an input current sample greater than the average of the input current samples to decrease the input current provided to the phase. 6. The method of claim 1 wherein:
each phase includes an inductor, the inductors of the phases have a same inductor value and tolerance. 7. The method of claim 1 wherein:
the intervals initially are the same. 8. A system for balancing phase currents of a plurality of phases of a multiphase converter, the system comprising:
a controller configured to alternately connect the phases during respective intervals to an input current from a power source and to generate trigger signals at successive time instants respectively for the phases, wherein the trigger signals are synchronous in that the trigger signals are generated at a same time following the connection of the phases to the input current; a current sensor configured to sample, at the time instants in response to the trigger signals, at a node of the multiphase converter that is common to the phases, the input current provided to the phases to obtain respective input current samples for the phases, wherein the current sensor includes a current shunt connected in series between the power source and the node; and wherein the controller is further configured to adjust the intervals based only on differences between the input current samples to minimize inequality of the input current samples. 9-10. (canceled) 11. The system of claim 8 wherein:
the node of the multiphase converter that is common to the phases is connected to a DC-link capacitor of the multiphase converter. 12. The system of claim 8 wherein:
the controller is further configured to adjust the intervals includes increasing the interval for a phase having an input current sample lower than an average of the input current samples to increase the input current provided to the phase; and
the controller is further configured to adjust the intervals includes decreasing the interval for a phase having an input current sample greater than the average of the input current samples to decrease the input current provided to the phase. 13. The system of claim 8 wherein:
each phase includes an inductor, the inductors of the phases have a same inductor value and tolerance. 14. The system of claim 8 wherein:
the intervals initially are the same. 15. A converter for converting DC voltage levels, comprising:
a plurality of phases connected in parallel to a common node; a power source configured to provide an input current to the common node; a controller configured to alternately connect the phases during respective intervals to the input current at the common node and to generate trigger signals at successive time instants respectively for the phases, wherein the trigger signals are synchronous in that the trigger signals are generated at a same time following the connection of the phases to the input current; a current sensor having a current shunt connected in series between the power source and the common node, the current sensor configured to sample, at the time instants in response to the trigger signals, the input current provided to the phases to obtain respective input current samples for the phases; and the controller is further configured to adjust the intervals based only on differences between the input current samples to minimize inequality of the input current samples. 16-17. (canceled) 18. The converter of claim 15 further comprising:
a DC-link capacitor connected to the common node. 19. The converter of claim 15 wherein:
the controller is further configured to adjust the intervals includes increasing the interval for a phase having an input current sample lower than an average of the input current samples to increase the input current provided to the phase; and
the controller is further configured to adjust the intervals includes decreasing the interval for a phase having an input current sample greater than the average of the input current samples to decrease the input current provided to the phase. 20. The converter of claim 15 wherein:
each phase includes an inductor, the inductors of the phases have a same inductor value and tolerance. 21. The method of claim 1 wherein:
each time instant at which a corresponding trigger signal is generated occurs after M cycles of the phases have been alternately connected to the input current, wherein M is an integer greater than one. 22. The system of claim 8 wherein:
each time instant at which a corresponding trigger signal is generated occurs after M cycles of the phases have been alternately connected to the input current, wherein M is an integer greater than one. 23. The converter of claim 15 wherein:
each time instant at which a corresponding trigger signal is generated occurs after M cycles of the phases have been alternately connected to the input current, wherein M is an integer greater than one. | 2,800 |
11,908 | 11,908 | 15,229,616 | 2,839 | A method may include monitoring an input power supply, monitoring an inductance of an inductor of a boost converter, monitoring one or more other characteristics of the boost converter, and calculating a target peak inductor current based on the input power supply voltage, the inductance, the one or more other characteristics of the boost converter, and a target average current of the inductor during a switching cycle of the boost converter. A method may include monitoring an input power supply voltage, monitoring an inductance of an inductor of a boost converter, monitoring one or more other characteristics of the boost converter, and calculating an average current of the inductor during a switching cycle of the boost converter based on the input power supply voltage, the inductance, the one or more other characteristics of the boost converter, and a peak inductor current of the inductor. | 1. A method comprising:
monitoring an input power supply voltage of a power supply; monitoring an inductance of an inductor of a boost converter comprising the inductor; monitoring one or more other characteristics of the boost converter; and calculating a target peak inductor current based on the input power supply voltage, the inductance, the one or more other characteristics of the boost converter, and a target average current of the inductor during a switching cycle of the boost converter. 2. The method of claim 1, further comprising controlling an average current of the inductor by regulating a peak inductor current of the inductor in accordance with a maximum average inductor current during a switching cycle. 3. The method of claim 1, wherein the one or more characteristics comprise a duty cycle for switching of a switch of the boost converter. 4. The method of claim 1, wherein the one or more characteristics comprise an output voltage of the boost converter. 5. The method of claim 1, wherein the one or more characteristics comprise an output current of the boost converter. 6. The method of claim 1, wherein the one or more characteristics comprise an efficiency of the boost converter. 7. The method of claim 1, further comprising deactivating a switch of the boost converter in response to an instantaneous inductor current of the inductor exceeding the target peak inductor current. 8. The method of claim 1, further comprising controlling an instantaneous inductor current and the target peak inductor current based on a user configuration. 9. The method of claim 8, wherein the user configuration comprises at least one of a voltage response threshold, a slope response of a voltage response threshold, state machine response timings, changes of supply current with respect to input power supply voltage, a desired limit of the target peak inductor current, and recovery options in response to recovery of the power supply. 10. The method of claim 1, further comprising reducing the target peak inductor current in a controllable manner responsive to the input power supply voltage falling below a threshold voltage. 11. An apparatus comprising:
a boost converter having a power supply input for receiving an input power supply voltage of a power supply, an inductor, and an output for generating an output voltage greater than the input power supply voltage; and a controller configured to:
monitor the input power supply voltage;
monitor the inductance of the inductor;
monitor one or more other characteristics of the boost converter; and
calculate a target peak inductor current based on the input power supply voltage, the inductance, the one or more other characteristics of the boost converter, and a target average current of the inductor during a switching cycle of the boost converter. 12. The apparatus of claim 11, wherein the controller is further configured to control an average current of the inductor by regulating a peak inductor current of the inductor in accordance with a maximum average inductor current during a switching cycle. 13. The apparatus of claim 11, wherein the one or more characteristics comprise a duty cycle for switching of a switch of the boost converter. 14. The apparatus of claim 11, wherein the one or more characteristics comprise the output voltage. 15. The apparatus of claim 11, wherein the one or more characteristics comprise an output current of the boost converter. 16. The apparatus of claim 11, wherein the one or more characteristics comprise an efficiency of the boost converter. 17. The apparatus of claim 11, wherein the controller is further configured to deactivate a switch of the boost converter in response to an instantaneous inductor current of the inductor exceeding the target peak inductor current. 18. The apparatus of claim 11, wherein the controller is further configured to control an instantaneous inductor current and the target peak inductor current based on a user configuration. 19. The apparatus of claim 18, wherein the user configuration comprises at least one of a voltage response threshold, a slope response of a voltage response threshold, state machine response timings, changes of supply current with respect to input power supply voltage, a desired limit of the target peak inductor current, and recovery options in response to recovery of the power supply. 20. The apparatus of claim 11, wherein the controller is further configured to reduce the target peak inductor current in a controllable manner responsive to the input power supply voltage falling below a threshold voltage. 21. A method comprising:
monitoring an input power supply voltage of a power supply; monitoring an inductance of an inductor of a boost converter comprising the inductor; monitoring one or more other characteristics of the boost converter; and calculating an average current of the inductor during a switching cycle of the boost converter based on the input power supply voltage, the inductance, the one or more other characteristics of the boost converter, and a peak inductor current of the inductor. 22. The method of claim 21, further comprising controlling the peak inductor current of the inductor by regulating an average current of the inductor in accordance with a maximum peak inductor current during a switching cycle. 23. The method of claim 21, wherein the one or more characteristics comprise a duty cycle for switching of a switch of the boost converter. 24. The method of claim 21, wherein the one or more characteristics comprise an output voltage of the boost converter. 25. The method of claim 21, wherein the one or more characteristics comprise an output current of the boost converter. 26. The method of claim 21, wherein the one or more characteristics comprise an efficiency of the boost converter. 27. An apparatus comprising:
a boost converter having a power supply input for receiving an input power supply voltage of a power supply, an inductor, and an output for generating an output voltage greater than the input power supply voltage; and a controller configured to:
monitor the input power supply voltage;
monitor the inductance of the inductor;
monitor one or more other characteristics of the boost converter; and
calculate an average current of the inductor during a switching cycle of the boost converter based on the input power supply voltage, the inductance, the one or more other characteristics of the boost converter, and a peak inductor current of the inductor. 28. The apparatus of claim 27, wherein the controller is further configured to control the peak inductor current of the inductor by regulating an average current of the inductor in accordance with a maximum peak inductor current during a switching cycle. 29. The apparatus of claim 27, wherein the one or more characteristics comprise a duty cycle for switching of a switch of the boost converter. 30. The apparatus of claim 27, wherein the one or more characteristics comprise an output voltage of the boost converter. 31. The apparatus of claim 27, wherein the one or more characteristics comprise an output current of the boost converter. 32. The apparatus of claim 27, wherein the one or more characteristics comprise an efficiency of the boost converter. | A method may include monitoring an input power supply, monitoring an inductance of an inductor of a boost converter, monitoring one or more other characteristics of the boost converter, and calculating a target peak inductor current based on the input power supply voltage, the inductance, the one or more other characteristics of the boost converter, and a target average current of the inductor during a switching cycle of the boost converter. A method may include monitoring an input power supply voltage, monitoring an inductance of an inductor of a boost converter, monitoring one or more other characteristics of the boost converter, and calculating an average current of the inductor during a switching cycle of the boost converter based on the input power supply voltage, the inductance, the one or more other characteristics of the boost converter, and a peak inductor current of the inductor.1. A method comprising:
monitoring an input power supply voltage of a power supply; monitoring an inductance of an inductor of a boost converter comprising the inductor; monitoring one or more other characteristics of the boost converter; and calculating a target peak inductor current based on the input power supply voltage, the inductance, the one or more other characteristics of the boost converter, and a target average current of the inductor during a switching cycle of the boost converter. 2. The method of claim 1, further comprising controlling an average current of the inductor by regulating a peak inductor current of the inductor in accordance with a maximum average inductor current during a switching cycle. 3. The method of claim 1, wherein the one or more characteristics comprise a duty cycle for switching of a switch of the boost converter. 4. The method of claim 1, wherein the one or more characteristics comprise an output voltage of the boost converter. 5. The method of claim 1, wherein the one or more characteristics comprise an output current of the boost converter. 6. The method of claim 1, wherein the one or more characteristics comprise an efficiency of the boost converter. 7. The method of claim 1, further comprising deactivating a switch of the boost converter in response to an instantaneous inductor current of the inductor exceeding the target peak inductor current. 8. The method of claim 1, further comprising controlling an instantaneous inductor current and the target peak inductor current based on a user configuration. 9. The method of claim 8, wherein the user configuration comprises at least one of a voltage response threshold, a slope response of a voltage response threshold, state machine response timings, changes of supply current with respect to input power supply voltage, a desired limit of the target peak inductor current, and recovery options in response to recovery of the power supply. 10. The method of claim 1, further comprising reducing the target peak inductor current in a controllable manner responsive to the input power supply voltage falling below a threshold voltage. 11. An apparatus comprising:
a boost converter having a power supply input for receiving an input power supply voltage of a power supply, an inductor, and an output for generating an output voltage greater than the input power supply voltage; and a controller configured to:
monitor the input power supply voltage;
monitor the inductance of the inductor;
monitor one or more other characteristics of the boost converter; and
calculate a target peak inductor current based on the input power supply voltage, the inductance, the one or more other characteristics of the boost converter, and a target average current of the inductor during a switching cycle of the boost converter. 12. The apparatus of claim 11, wherein the controller is further configured to control an average current of the inductor by regulating a peak inductor current of the inductor in accordance with a maximum average inductor current during a switching cycle. 13. The apparatus of claim 11, wherein the one or more characteristics comprise a duty cycle for switching of a switch of the boost converter. 14. The apparatus of claim 11, wherein the one or more characteristics comprise the output voltage. 15. The apparatus of claim 11, wherein the one or more characteristics comprise an output current of the boost converter. 16. The apparatus of claim 11, wherein the one or more characteristics comprise an efficiency of the boost converter. 17. The apparatus of claim 11, wherein the controller is further configured to deactivate a switch of the boost converter in response to an instantaneous inductor current of the inductor exceeding the target peak inductor current. 18. The apparatus of claim 11, wherein the controller is further configured to control an instantaneous inductor current and the target peak inductor current based on a user configuration. 19. The apparatus of claim 18, wherein the user configuration comprises at least one of a voltage response threshold, a slope response of a voltage response threshold, state machine response timings, changes of supply current with respect to input power supply voltage, a desired limit of the target peak inductor current, and recovery options in response to recovery of the power supply. 20. The apparatus of claim 11, wherein the controller is further configured to reduce the target peak inductor current in a controllable manner responsive to the input power supply voltage falling below a threshold voltage. 21. A method comprising:
monitoring an input power supply voltage of a power supply; monitoring an inductance of an inductor of a boost converter comprising the inductor; monitoring one or more other characteristics of the boost converter; and calculating an average current of the inductor during a switching cycle of the boost converter based on the input power supply voltage, the inductance, the one or more other characteristics of the boost converter, and a peak inductor current of the inductor. 22. The method of claim 21, further comprising controlling the peak inductor current of the inductor by regulating an average current of the inductor in accordance with a maximum peak inductor current during a switching cycle. 23. The method of claim 21, wherein the one or more characteristics comprise a duty cycle for switching of a switch of the boost converter. 24. The method of claim 21, wherein the one or more characteristics comprise an output voltage of the boost converter. 25. The method of claim 21, wherein the one or more characteristics comprise an output current of the boost converter. 26. The method of claim 21, wherein the one or more characteristics comprise an efficiency of the boost converter. 27. An apparatus comprising:
a boost converter having a power supply input for receiving an input power supply voltage of a power supply, an inductor, and an output for generating an output voltage greater than the input power supply voltage; and a controller configured to:
monitor the input power supply voltage;
monitor the inductance of the inductor;
monitor one or more other characteristics of the boost converter; and
calculate an average current of the inductor during a switching cycle of the boost converter based on the input power supply voltage, the inductance, the one or more other characteristics of the boost converter, and a peak inductor current of the inductor. 28. The apparatus of claim 27, wherein the controller is further configured to control the peak inductor current of the inductor by regulating an average current of the inductor in accordance with a maximum peak inductor current during a switching cycle. 29. The apparatus of claim 27, wherein the one or more characteristics comprise a duty cycle for switching of a switch of the boost converter. 30. The apparatus of claim 27, wherein the one or more characteristics comprise an output voltage of the boost converter. 31. The apparatus of claim 27, wherein the one or more characteristics comprise an output current of the boost converter. 32. The apparatus of claim 27, wherein the one or more characteristics comprise an efficiency of the boost converter. | 2,800 |
11,909 | 11,909 | 15,289,943 | 2,883 | A fiber optic cable includes a cable core of core elements and a protective sheath surrounding the core elements, an armor surrounding the cable core, the armor comprising a single overlap portion when the fiber optic cable is viewed in cross-section, and a jacket surrounding the armor, the jacket having at least two longitudinal discontinuities extruded therein. A method of accessing the cable core without the use of ripcords includes removing a portion of the armor in an access section by pulling the minor away from the cable core so that an overlap portion separates around the cable core as it is being pulled past the cable core. A protective sheath protects the core elements as the armor is being pulled around the cable core. | 1. A fiber optic cable, comprising:
a cable core of core elements and a protective sheath surrounding the core elements, wherein the protective sheath is continuous peripherally around the core elements, forming a continuous closed loop when viewed in cross-section, and continuous lengthwise along a length of the cable, and wherein the cable core is devoid of any ripcords; an armor surrounding the cable core, the armor comprising a single overlap portion when the fiber optic cable is viewed in cross-section; and a jacket surrounding the armor, the jacket having at least two longitudinal discontinuities extruded therein. 2. The fiber optic cable of claim 1, further comprising an access section, the access section defined by a jacket portion removed via separation of the jacket along the discontinuities and an armor portion removed via separation of the overlap portion around the cable core. 3. The fiber optic cable of claim 3, wherein the core elements comprise:
a tube surrounding one or more optical fibers; at least one of a filler rod and an additional tube; and a central strength member, wherein the core elements are stranded around the central strength member in a pattern of stranding including reversals in lay direction of the core elements. 4. The fiber optic cable of claim 1, wherein the protective sheath is in radial tension around the core elements such that the protective sheath opposes outwardly transverse deflection of the core elements, and wherein the protective sheath loads the core elements normally to the central strength member such that contact between the core elements and central strength member provides coupling therebetween, limiting axial migration of the core elements relative to the central strength member. 5. The fiber optic cable of claim 1, wherein the radial tension of the protective sheath has a distributed loading of at least 5 newtons per meter length of the cable. 6. The fiber optic cable of claim 1, wherein the protective sheath is 0.2 millimeters or less in thickness. 7. The fiber optic cable of claim 1, wherein the armor is comprised of steel, aluminum, or copper. 8. The fiber optic cable of claim 1, wherein, around the cross-sectional periphery of the protective sheath, the protective sheath takes the shape of adjoining core elements and extends in generally concave arcs over interstices between the core elements. 9. The fiber optic cable of claim 1, wherein the jacket is at least five times thicker than the protective sheath. 10. The fiber optic cable of claim 1, wherein the jacket is opaque and the protective sheath is translucent so that the core elements are at least partially visible through the protective sheath. 11. A method of accessing core elements of a fiber optic cable without the use of ripcords, the fiber optic cable comprising a cable core of the core elements and a protective sheath surrounding the core elements, an armor surrounding the cable core, the armor comprising a single overlap portion when the fiber optic cable is viewed in cross-section, and a jacket surrounding the armor, the jacket having at least two longitudinal discontinuities extruded therein, the method comprising:
making a ring cut of the jacket at a mid-span location; making a longitudinal cut in the jacket where at least one of the two longitudinal discontinuities are located, the longitudinal cut orthogonally intersecting the ring cut; grasping the jacket at the intersection of the longitudinal cut and the ring cut and peeling back the jacket so that the jacket separates along the discontinuities a predetermined length; removing the predetermined length of jacket peeled back from the core to expose the armor and define an access section; scoring the armor near an end of the access section to remove a small section of the armor and expose the cable core; and removing a remaining portion of the armor in the access section by pulling the armor away from the cable core so that the overlap portion separates around the cable core as it is being pulled past the cable core. 12. The method of claim 11, further comprising:
making a lengthwise incision in the protective sheath to provide an opening through which the core elements may be accessed. 13. The method of claim 12, wherein the core elements include a plurality of buffer tubes, at least one of the buffer tubes surrounding optical fibers. 14. The method of claim 13, wherein the core elements further include a central strength element, the buffer tubes being stranded around the central strength element in an s-z stranding configuration. 15. The method of claim 14, wherein the lengthwise incision is made at a reversal of the s-z stranding configuration. | A fiber optic cable includes a cable core of core elements and a protective sheath surrounding the core elements, an armor surrounding the cable core, the armor comprising a single overlap portion when the fiber optic cable is viewed in cross-section, and a jacket surrounding the armor, the jacket having at least two longitudinal discontinuities extruded therein. A method of accessing the cable core without the use of ripcords includes removing a portion of the armor in an access section by pulling the minor away from the cable core so that an overlap portion separates around the cable core as it is being pulled past the cable core. A protective sheath protects the core elements as the armor is being pulled around the cable core.1. A fiber optic cable, comprising:
a cable core of core elements and a protective sheath surrounding the core elements, wherein the protective sheath is continuous peripherally around the core elements, forming a continuous closed loop when viewed in cross-section, and continuous lengthwise along a length of the cable, and wherein the cable core is devoid of any ripcords; an armor surrounding the cable core, the armor comprising a single overlap portion when the fiber optic cable is viewed in cross-section; and a jacket surrounding the armor, the jacket having at least two longitudinal discontinuities extruded therein. 2. The fiber optic cable of claim 1, further comprising an access section, the access section defined by a jacket portion removed via separation of the jacket along the discontinuities and an armor portion removed via separation of the overlap portion around the cable core. 3. The fiber optic cable of claim 3, wherein the core elements comprise:
a tube surrounding one or more optical fibers; at least one of a filler rod and an additional tube; and a central strength member, wherein the core elements are stranded around the central strength member in a pattern of stranding including reversals in lay direction of the core elements. 4. The fiber optic cable of claim 1, wherein the protective sheath is in radial tension around the core elements such that the protective sheath opposes outwardly transverse deflection of the core elements, and wherein the protective sheath loads the core elements normally to the central strength member such that contact between the core elements and central strength member provides coupling therebetween, limiting axial migration of the core elements relative to the central strength member. 5. The fiber optic cable of claim 1, wherein the radial tension of the protective sheath has a distributed loading of at least 5 newtons per meter length of the cable. 6. The fiber optic cable of claim 1, wherein the protective sheath is 0.2 millimeters or less in thickness. 7. The fiber optic cable of claim 1, wherein the armor is comprised of steel, aluminum, or copper. 8. The fiber optic cable of claim 1, wherein, around the cross-sectional periphery of the protective sheath, the protective sheath takes the shape of adjoining core elements and extends in generally concave arcs over interstices between the core elements. 9. The fiber optic cable of claim 1, wherein the jacket is at least five times thicker than the protective sheath. 10. The fiber optic cable of claim 1, wherein the jacket is opaque and the protective sheath is translucent so that the core elements are at least partially visible through the protective sheath. 11. A method of accessing core elements of a fiber optic cable without the use of ripcords, the fiber optic cable comprising a cable core of the core elements and a protective sheath surrounding the core elements, an armor surrounding the cable core, the armor comprising a single overlap portion when the fiber optic cable is viewed in cross-section, and a jacket surrounding the armor, the jacket having at least two longitudinal discontinuities extruded therein, the method comprising:
making a ring cut of the jacket at a mid-span location; making a longitudinal cut in the jacket where at least one of the two longitudinal discontinuities are located, the longitudinal cut orthogonally intersecting the ring cut; grasping the jacket at the intersection of the longitudinal cut and the ring cut and peeling back the jacket so that the jacket separates along the discontinuities a predetermined length; removing the predetermined length of jacket peeled back from the core to expose the armor and define an access section; scoring the armor near an end of the access section to remove a small section of the armor and expose the cable core; and removing a remaining portion of the armor in the access section by pulling the armor away from the cable core so that the overlap portion separates around the cable core as it is being pulled past the cable core. 12. The method of claim 11, further comprising:
making a lengthwise incision in the protective sheath to provide an opening through which the core elements may be accessed. 13. The method of claim 12, wherein the core elements include a plurality of buffer tubes, at least one of the buffer tubes surrounding optical fibers. 14. The method of claim 13, wherein the core elements further include a central strength element, the buffer tubes being stranded around the central strength element in an s-z stranding configuration. 15. The method of claim 14, wherein the lengthwise incision is made at a reversal of the s-z stranding configuration. | 2,800 |
11,910 | 11,910 | 15,622,241 | 2,864 | The orientation of the symmetry axis of an underground formation including an HTI layer is determined by comparing azimuthal Fourier coefficient of inversion results in distinct source-receiver azimuth ranges with values expected from the HTI assumption. A branch-stacking technique or prior knowledge may be used to select one of the anisotropy axis orientation values. | 1. A method for determining orientation of stress or cracks in an underground formation including a horizontally transverse isotropic, HTI, layer, the method comprising:
performing isotropic elastic inversions on portions of seismic data acquired during a seismic survey of the underground formation to obtain values of one or more effective elastic parameters or combinations thereof, the portions of the seismic data corresponding to distinct source-receiver azimuth ranges; calculating azimuthal Fourier coefficients, AFCs, for each of the one or more effective elastic parameters or combinations based on the values; estimating an anisotropy axis orientation by solving equations that correspond a minimization of distance between the calculated AFCs and expected AFCs corresponding to an HTI assumption; and using the estimated anisotropy axis orientation to design a hydrocarbon production plan. 2. The method of claim 1, wherein the estimating of the anisotropy axis orientation includes applying branch-stacking to average AFCs within a 3D window yielding a seismic attribute that indicate a most likely value of the anisotropy axis orientation. 3. The method of claim 2, wherein the seismic attribute is maximum for the most likely value of the anisotropy axis orientation. 4. The method of claim 2, wherein the seismic attribute changes sign for the most likely value of the anisotropy axis orientation. 5. The method of claim 1, further comprising:
inferring anisotropy parameters using the anisotropy axis orientation, wherein the inferred anisotropy parameters are also used for designing the hydrocarbon production plan. 6. The method of claim 5, wherein the estimating of the anisotropy axis orientation and the inferring of the anisotropy parameters are iterated until a criterion related to a residual distance is met. 7. The method of claim 5, wherein the estimated anisotropy axis orientation and the inferred anisotropy parameters are used as initial values to repeat performing the isotropic elastic inversions on the portions of the seismic data, calculating the AFCs, estimating the anisotropy axis orientation, and inferring the anisotropy parameters until a criterion related to a residual distance is met. 8. The method of claim 1, wherein a Thomsen-type HTI assumption is employed to calculate the expected AFCs and the minimization refers to
S=Σ n,i |B n i(ϕ)−H n i(ϕn i)|2
subject to bn i=Dna iTa+δn0 ln Pi, where bn i are generic HTI coefficients, Pi are elastic parameters, δnm is Kronecker delta and Dna i are matrices that depend on K=(V s/V p)2, averages of secondary and primary wave propagation velocities. 9. The method of claim 1, wherein the distinct source-receiver azimuth ranges are substantially equal, and divide a range of 0 to π in at least six sectors. 10. The method of claim 1, wherein the distinct source-receiver azimuth ranges divide a range of 0 to π in sectors of uneven size for which the data is resampled or re-binned in the azimuthal dimension to become six or more regular sectors. 11. The method of claim 1, wherein the calculating of the AFCs includes a moving window average. 12. The method of claim 1, wherein the estimating of the anisotropy axis orientation includes selecting a solution value based on additional information. 13. A data processing apparatus for determining orientation of stress or cracks in an underground formation including a horizontally transverse isotropic, HTI, layer, comprising:
a memory storing program instructions; and a processor connected to the memory and configured to execute the program instructions that cause:
performing isotropic elastic inversions on portions of seismic data acquired during a seismic survey of the underground formation to obtain values of one or more effective elastic parameters or combinations thereof, the portions of the seismic data corresponding to distinct source-receiver azimuth ranges;
calculating azimuthal Fourier coefficients, AFCs, for each of the effective elastic parameters or combinations based on the values;
estimating an anisotropy axis orientation by solving equations that correspond a minimization of distance between the calculated AFCs and expected AFCs corresponding to an HTI assumption;
and
using the estimated anisotropy axis orientation to design a hydrocarbon production plan. 14. The apparatus of claim 13, wherein the estimating of the anisotropy axis orientation includes applying branch-stacking to average AFCs within a 3D window yielding a seismic attribute that indicate a most likely value of the anisotropy axis orientation. 15. The apparatus of claim 14, wherein the seismic attribute is maximum for the most likely value of the anisotropy axis orientation. 16. The apparatus of claim 14, wherein the seismic attribute changes sign for the most likely value of the anisotropy axis orientation. 17. The apparatus of claim 13, wherein the processor executing the program instructions further performs:
inferring anisotropy parameters using the anisotropy axis orientation, wherein the inferred anisotropy parameters are also used for designing the hydrocarbon production plan. 18. The apparatus of claim 17, wherein the processor executing the program instructions iterates estimating the anisotropy axis orientation and inferring the anisotropy parameters until a criterion related to residual distance is met. 19. The apparatus of claim 17, wherein the processor executing the program instructions uses the estimated anisotropy axis orientation and the inferred the anisotropy parameters as initial values to repeat performing the isotropic elastic inversions on the portions of the seismic data, calculating the AFCs, estimating the anisotropy axis orientation, and inferring the anisotropy parameters until a criterion related to residual distance is met. 20. The apparatus of claim 13, wherein a Thomsen-type HTI assumption is employed to calculate the estimates of the AFCs and the minimization refers to
S=Σ n,i |B n i(ϕ)−H n i(ϕn i)|2
subject to bn i=Dna iTa+δn0 ln Pi, where bn i are generic HTI coefficients, Pi are elastic parameters, δnm is Kronecker delta and Dna i are matrices that depend on K=(V s/V p)2, averages of secondary and primary wave propagation velocities. | The orientation of the symmetry axis of an underground formation including an HTI layer is determined by comparing azimuthal Fourier coefficient of inversion results in distinct source-receiver azimuth ranges with values expected from the HTI assumption. A branch-stacking technique or prior knowledge may be used to select one of the anisotropy axis orientation values.1. A method for determining orientation of stress or cracks in an underground formation including a horizontally transverse isotropic, HTI, layer, the method comprising:
performing isotropic elastic inversions on portions of seismic data acquired during a seismic survey of the underground formation to obtain values of one or more effective elastic parameters or combinations thereof, the portions of the seismic data corresponding to distinct source-receiver azimuth ranges; calculating azimuthal Fourier coefficients, AFCs, for each of the one or more effective elastic parameters or combinations based on the values; estimating an anisotropy axis orientation by solving equations that correspond a minimization of distance between the calculated AFCs and expected AFCs corresponding to an HTI assumption; and using the estimated anisotropy axis orientation to design a hydrocarbon production plan. 2. The method of claim 1, wherein the estimating of the anisotropy axis orientation includes applying branch-stacking to average AFCs within a 3D window yielding a seismic attribute that indicate a most likely value of the anisotropy axis orientation. 3. The method of claim 2, wherein the seismic attribute is maximum for the most likely value of the anisotropy axis orientation. 4. The method of claim 2, wherein the seismic attribute changes sign for the most likely value of the anisotropy axis orientation. 5. The method of claim 1, further comprising:
inferring anisotropy parameters using the anisotropy axis orientation, wherein the inferred anisotropy parameters are also used for designing the hydrocarbon production plan. 6. The method of claim 5, wherein the estimating of the anisotropy axis orientation and the inferring of the anisotropy parameters are iterated until a criterion related to a residual distance is met. 7. The method of claim 5, wherein the estimated anisotropy axis orientation and the inferred anisotropy parameters are used as initial values to repeat performing the isotropic elastic inversions on the portions of the seismic data, calculating the AFCs, estimating the anisotropy axis orientation, and inferring the anisotropy parameters until a criterion related to a residual distance is met. 8. The method of claim 1, wherein a Thomsen-type HTI assumption is employed to calculate the expected AFCs and the minimization refers to
S=Σ n,i |B n i(ϕ)−H n i(ϕn i)|2
subject to bn i=Dna iTa+δn0 ln Pi, where bn i are generic HTI coefficients, Pi are elastic parameters, δnm is Kronecker delta and Dna i are matrices that depend on K=(V s/V p)2, averages of secondary and primary wave propagation velocities. 9. The method of claim 1, wherein the distinct source-receiver azimuth ranges are substantially equal, and divide a range of 0 to π in at least six sectors. 10. The method of claim 1, wherein the distinct source-receiver azimuth ranges divide a range of 0 to π in sectors of uneven size for which the data is resampled or re-binned in the azimuthal dimension to become six or more regular sectors. 11. The method of claim 1, wherein the calculating of the AFCs includes a moving window average. 12. The method of claim 1, wherein the estimating of the anisotropy axis orientation includes selecting a solution value based on additional information. 13. A data processing apparatus for determining orientation of stress or cracks in an underground formation including a horizontally transverse isotropic, HTI, layer, comprising:
a memory storing program instructions; and a processor connected to the memory and configured to execute the program instructions that cause:
performing isotropic elastic inversions on portions of seismic data acquired during a seismic survey of the underground formation to obtain values of one or more effective elastic parameters or combinations thereof, the portions of the seismic data corresponding to distinct source-receiver azimuth ranges;
calculating azimuthal Fourier coefficients, AFCs, for each of the effective elastic parameters or combinations based on the values;
estimating an anisotropy axis orientation by solving equations that correspond a minimization of distance between the calculated AFCs and expected AFCs corresponding to an HTI assumption;
and
using the estimated anisotropy axis orientation to design a hydrocarbon production plan. 14. The apparatus of claim 13, wherein the estimating of the anisotropy axis orientation includes applying branch-stacking to average AFCs within a 3D window yielding a seismic attribute that indicate a most likely value of the anisotropy axis orientation. 15. The apparatus of claim 14, wherein the seismic attribute is maximum for the most likely value of the anisotropy axis orientation. 16. The apparatus of claim 14, wherein the seismic attribute changes sign for the most likely value of the anisotropy axis orientation. 17. The apparatus of claim 13, wherein the processor executing the program instructions further performs:
inferring anisotropy parameters using the anisotropy axis orientation, wherein the inferred anisotropy parameters are also used for designing the hydrocarbon production plan. 18. The apparatus of claim 17, wherein the processor executing the program instructions iterates estimating the anisotropy axis orientation and inferring the anisotropy parameters until a criterion related to residual distance is met. 19. The apparatus of claim 17, wherein the processor executing the program instructions uses the estimated anisotropy axis orientation and the inferred the anisotropy parameters as initial values to repeat performing the isotropic elastic inversions on the portions of the seismic data, calculating the AFCs, estimating the anisotropy axis orientation, and inferring the anisotropy parameters until a criterion related to residual distance is met. 20. The apparatus of claim 13, wherein a Thomsen-type HTI assumption is employed to calculate the estimates of the AFCs and the minimization refers to
S=Σ n,i |B n i(ϕ)−H n i(ϕn i)|2
subject to bn i=Dna iTa+δn0 ln Pi, where bn i are generic HTI coefficients, Pi are elastic parameters, δnm is Kronecker delta and Dna i are matrices that depend on K=(V s/V p)2, averages of secondary and primary wave propagation velocities. | 2,800 |
11,911 | 11,911 | 14,574,743 | 2,859 | A charging device for charging a charge storage device includes a coupling device for coupling a connector for charging the charge storage device, an optical waveguide for illuminating the coupling device and/or for indicating a state of charge of the charge storage device, and a light source for coupling light into the optical waveguide. Search lighting and an indication of the state of charge of the charge storage device can be realized by way of the optical waveguide. | 1. A charging device for charging a charge storage device, comprising:
a coupling device for coupling a connector for charging the charge storage device; an optical waveguide configured to illuminate the coupling device and/or to indicate a state of charge of the charge storage device; and a light source configured to couple light into the optical waveguide. 2. The charging device according to claim 1, wherein:
the optical waveguide has an in-coupling point at least at one end for coupling light into the optical waveguide, and the light source is arranged at the at least one in-coupling point of the optical waveguide. 3. The charging device according to claim 2, wherein:
the optical waveguide has an out-coupling structure for out-coupling the light from the optical waveguide, the out-coupled light being dependent on a shape of the out-coupling structure, and the out-coupling structure is shaped differently at different positions of the optical waveguide. 4. The charging device according to claim 3, further comprising:
a faceplate in which the coupling device is arranged, the optical waveguide extending along an edge of the faceplate; and a facing element configured to cover the optical waveguide, the facing element being transparent at a lateral edge and being opaque at an upper side. 5. The charging device according to claim 4, wherein the optical waveguide extends in a C-shaped or ring-shaped manner along the edge of the faceplate. 6. The charging device according to claim 4, further comprising:
a cover element configured to cover the coupling device, wherein in an open state of the cover element, the coupling device is not covered by the cover element, and in a closed state of the cover element, the coupling device is covered by the cover element; a Hall sensor detector configured to detect the open state and the closed state of the cover element; and wherein the light source is designed to change light coupled into the optical waveguide depending on the open or closed state of the cover element detected by the Hall sensor detector. 7. The charging device according to claim 6, further comprising:
a brightness sensor configured to detect a brightness of an environment of the coupling device; and wherein the light source is designed to change light coupled into the optical waveguide depending on the brightness detected by the brightness sensor. 8. The charging device according to claim 7, wherein the light source is designed to generate light having different colors, different brightnesses, and/or different sequences of light pulses, said light being coupled into the optical waveguide. 9. A control device for controlling illumination of a charging device for charging a charge storage device, the charging device comprising a coupling device for coupling a connector used in charging the charge storage device, an optical waveguide for illuminating the coupling device and/or indicating a charge state of the charge storage device, and a light source for coupling light into the optical waveguide, the control device comprising:
a controller programmed to:
detect whether the charging device is operating in a first state in which a cover element that covers the coupling device is open and the connector is not connected to the coupling device, or is operated in a second state in which the cover element is open and the connector is connected to the coupling device; and
actuate the light source such that light to be coupled into the optical waveguide of the charging device changes depending on whether the charging device is operated in the first state or the second state. 10. The control device according to claim 9, wherein the controller is further programmed to:
actuate the light source in the first state of the charging device such that the light source illuminates the coupling device of the charging device in the first state with homogeneous light; detect, in the second state of the charging device, if the charging device is ready for charging the charge storage device or if an error status exists; and actuate the light source such that the light to be coupled into the optical waveguide changes depending on whether the charging device is ready for charging or whether the error status exists. 11. The control device according to claim 10, wherein the controller is further programmed to:
detect at what point-in-time the charge storage device is to be charged; and actuate the light source such that the light to be coupled into the optical waveguide changes depending on the point-in-time at which charging of the charge storage device takes place. 12. The control device according to claim 11, wherein the controller is further programmed to:
detect a state of charge of the charge storage device; and actuate the light source such that the light to be coupled into the optical waveguide changes depending on the detected state of charge of the charge storage device. 13. A system for charging a charge storage device comprising:
a charging device for charging the charge storage device, the charging device comprising:
a coupling device for coupling a connector for charging the charge storage device;
an optical waveguide configured to illuminate the coupling device and/or to indicate a state of charge of the charge storage device; and
a light source configured to couple light into the optical waveguide,
a control device for controlling the illumination of the charging device for charging the charge storage device, the control device comprising a controller programmed to:
detect whether the charging device is operating in a first state in which a cover element that covers the coupling device is open and the connector is not connected to the coupling device, or is operated in a second state in which the cover element is open and the connector is connected to the coupling device; and
actuate the light source such that light to be coupled into the optical waveguide of the charging device changes depending on whether the charging device is operated in the first state or the second state. 14. The system according to claim 13, wherein the controller is further programmed to:
actuate the light source in the first state of the charging device such that the light source illuminates the coupling device of the charging device in the first state with homogeneous light; detect, in the second state of the charging device, if the charging device is ready for charging the charge storage device or if an error status exists; and actuate the light source such that the light to be coupled into the optical waveguide changes depending on whether the charging device is ready for charging or whether the error status exists. 15. The system according to claim 13, wherein the controller is further programmed to:
detect at what point-in-time the charge storage device is to be charged; and actuate the light source such that the light to be coupled into the optical waveguide changes depending on the point-in-time at which charging of the charge storage device takes place. 16. The system according to claim 13, wherein the controller is further programmed to:
detect a state of charge of the charge storage device; and actuate the light source such that the light to be coupled into the optical waveguide changes depending on the detected state of charge of the charge storage device. 17. A vehicle, comprising:
a charge storage device; a charging device for charging the charge storage device, the charging device comprising:
a coupling device for coupling a connector for charging the charge storage device;
an optical waveguide configured to illumination the coupling device and/or to indicate a state of charge of the charge storage device; and
a light source configured to couple light into the optical waveguide,
a control device for controlling the illumination of the charging device for charging the charge storage device, the control device comprising a controller programmed to:
detect whether the charging device is operating in a first state in which a cover element that covers the coupling device is open and the connector is not connected to the coupling device, or is operated in a second state in which the cover element is open and the connector is connected to the coupling device; and
actuate the light source such that light to be coupled into the optical waveguide of the charging device changes depending on whether the charging device is operated in the first state or the second state. 18. The vehicle according to claim 17, wherein the controller of the control device is further programmed to:
deactivate the light source of the charging device after a defined time period after plugging the connector into the coupling device of the charging device; and activate the light source for coupling light into the optical waveguide when the vehicle is unlocked. 19. The vehicle according to claim 18, wherein the controller is further programmed to:
detect if the vehicle is in a ready-to-start state; and deactivate the light source of the charging device if the light source has been activated and the vehicle is in the ready-to-start state, or maintain the light source in a deactivated state if the light source is already in the deactivated state and the vehicle is in the ready-to-start state. | A charging device for charging a charge storage device includes a coupling device for coupling a connector for charging the charge storage device, an optical waveguide for illuminating the coupling device and/or for indicating a state of charge of the charge storage device, and a light source for coupling light into the optical waveguide. Search lighting and an indication of the state of charge of the charge storage device can be realized by way of the optical waveguide.1. A charging device for charging a charge storage device, comprising:
a coupling device for coupling a connector for charging the charge storage device; an optical waveguide configured to illuminate the coupling device and/or to indicate a state of charge of the charge storage device; and a light source configured to couple light into the optical waveguide. 2. The charging device according to claim 1, wherein:
the optical waveguide has an in-coupling point at least at one end for coupling light into the optical waveguide, and the light source is arranged at the at least one in-coupling point of the optical waveguide. 3. The charging device according to claim 2, wherein:
the optical waveguide has an out-coupling structure for out-coupling the light from the optical waveguide, the out-coupled light being dependent on a shape of the out-coupling structure, and the out-coupling structure is shaped differently at different positions of the optical waveguide. 4. The charging device according to claim 3, further comprising:
a faceplate in which the coupling device is arranged, the optical waveguide extending along an edge of the faceplate; and a facing element configured to cover the optical waveguide, the facing element being transparent at a lateral edge and being opaque at an upper side. 5. The charging device according to claim 4, wherein the optical waveguide extends in a C-shaped or ring-shaped manner along the edge of the faceplate. 6. The charging device according to claim 4, further comprising:
a cover element configured to cover the coupling device, wherein in an open state of the cover element, the coupling device is not covered by the cover element, and in a closed state of the cover element, the coupling device is covered by the cover element; a Hall sensor detector configured to detect the open state and the closed state of the cover element; and wherein the light source is designed to change light coupled into the optical waveguide depending on the open or closed state of the cover element detected by the Hall sensor detector. 7. The charging device according to claim 6, further comprising:
a brightness sensor configured to detect a brightness of an environment of the coupling device; and wherein the light source is designed to change light coupled into the optical waveguide depending on the brightness detected by the brightness sensor. 8. The charging device according to claim 7, wherein the light source is designed to generate light having different colors, different brightnesses, and/or different sequences of light pulses, said light being coupled into the optical waveguide. 9. A control device for controlling illumination of a charging device for charging a charge storage device, the charging device comprising a coupling device for coupling a connector used in charging the charge storage device, an optical waveguide for illuminating the coupling device and/or indicating a charge state of the charge storage device, and a light source for coupling light into the optical waveguide, the control device comprising:
a controller programmed to:
detect whether the charging device is operating in a first state in which a cover element that covers the coupling device is open and the connector is not connected to the coupling device, or is operated in a second state in which the cover element is open and the connector is connected to the coupling device; and
actuate the light source such that light to be coupled into the optical waveguide of the charging device changes depending on whether the charging device is operated in the first state or the second state. 10. The control device according to claim 9, wherein the controller is further programmed to:
actuate the light source in the first state of the charging device such that the light source illuminates the coupling device of the charging device in the first state with homogeneous light; detect, in the second state of the charging device, if the charging device is ready for charging the charge storage device or if an error status exists; and actuate the light source such that the light to be coupled into the optical waveguide changes depending on whether the charging device is ready for charging or whether the error status exists. 11. The control device according to claim 10, wherein the controller is further programmed to:
detect at what point-in-time the charge storage device is to be charged; and actuate the light source such that the light to be coupled into the optical waveguide changes depending on the point-in-time at which charging of the charge storage device takes place. 12. The control device according to claim 11, wherein the controller is further programmed to:
detect a state of charge of the charge storage device; and actuate the light source such that the light to be coupled into the optical waveguide changes depending on the detected state of charge of the charge storage device. 13. A system for charging a charge storage device comprising:
a charging device for charging the charge storage device, the charging device comprising:
a coupling device for coupling a connector for charging the charge storage device;
an optical waveguide configured to illuminate the coupling device and/or to indicate a state of charge of the charge storage device; and
a light source configured to couple light into the optical waveguide,
a control device for controlling the illumination of the charging device for charging the charge storage device, the control device comprising a controller programmed to:
detect whether the charging device is operating in a first state in which a cover element that covers the coupling device is open and the connector is not connected to the coupling device, or is operated in a second state in which the cover element is open and the connector is connected to the coupling device; and
actuate the light source such that light to be coupled into the optical waveguide of the charging device changes depending on whether the charging device is operated in the first state or the second state. 14. The system according to claim 13, wherein the controller is further programmed to:
actuate the light source in the first state of the charging device such that the light source illuminates the coupling device of the charging device in the first state with homogeneous light; detect, in the second state of the charging device, if the charging device is ready for charging the charge storage device or if an error status exists; and actuate the light source such that the light to be coupled into the optical waveguide changes depending on whether the charging device is ready for charging or whether the error status exists. 15. The system according to claim 13, wherein the controller is further programmed to:
detect at what point-in-time the charge storage device is to be charged; and actuate the light source such that the light to be coupled into the optical waveguide changes depending on the point-in-time at which charging of the charge storage device takes place. 16. The system according to claim 13, wherein the controller is further programmed to:
detect a state of charge of the charge storage device; and actuate the light source such that the light to be coupled into the optical waveguide changes depending on the detected state of charge of the charge storage device. 17. A vehicle, comprising:
a charge storage device; a charging device for charging the charge storage device, the charging device comprising:
a coupling device for coupling a connector for charging the charge storage device;
an optical waveguide configured to illumination the coupling device and/or to indicate a state of charge of the charge storage device; and
a light source configured to couple light into the optical waveguide,
a control device for controlling the illumination of the charging device for charging the charge storage device, the control device comprising a controller programmed to:
detect whether the charging device is operating in a first state in which a cover element that covers the coupling device is open and the connector is not connected to the coupling device, or is operated in a second state in which the cover element is open and the connector is connected to the coupling device; and
actuate the light source such that light to be coupled into the optical waveguide of the charging device changes depending on whether the charging device is operated in the first state or the second state. 18. The vehicle according to claim 17, wherein the controller of the control device is further programmed to:
deactivate the light source of the charging device after a defined time period after plugging the connector into the coupling device of the charging device; and activate the light source for coupling light into the optical waveguide when the vehicle is unlocked. 19. The vehicle according to claim 18, wherein the controller is further programmed to:
detect if the vehicle is in a ready-to-start state; and deactivate the light source of the charging device if the light source has been activated and the vehicle is in the ready-to-start state, or maintain the light source in a deactivated state if the light source is already in the deactivated state and the vehicle is in the ready-to-start state. | 2,800 |
11,912 | 11,912 | 15,927,442 | 2,842 | An integrated circuit having at least one electrically-controlled control loop that includes one or more loop error amplifiers also includes an analog-to-digital converter having both an input that operably couples to two inputs of each loop error amplifier and an output that couples to an off-chip hardware component comprising a control circuit. This control circuit reads digital versions that correspond to the loop error amplifier inputs. When a particular first input is greater than a second input, the control circuit sources a calibration signal to modify and offset for the loop error amplifier in a first direction. When the first input is less than the second input, the control circuit sources a calibration signal to modify the offset for the loop error amplifier in a second direction that is different from the aforementioned first direction. By one approach the control circuit also controls a sampling rate of the analog-to-digital converter. | 1. An integrated circuit comprising:
an electrically-controlled control loop that includes a loop error amplifier; an analog-to-digital converter having an input that selectively operably couples to two inputs of the loop error amplifier and an output; and a contact pad that is operably coupled to the output of the analog-to-digital converter such that the analog-to-digital converter is operably accessible to an off-chip hardware component. 2. The integrated circuit of claim 1 wherein the electrically-controlled control loop comprises a part of a voltage regulator. 3. The integrated circuit of claim 2 wherein the voltage regulator comprises a part of a switched-mode power supply. 4. The integrated circuit of claim 1 wherein the electrically-controlled control loop further comprises a second loop error amplifier, and where the analog-to-digital converter input further selectively operably couples to two inputs of the second loop error amplifier. 5. The integrated circuit of claim 4 wherein the loop error amplifier comprises a voltage loop error amplifier and the second loop error amplifier comprises a current loop error amplifier. 6. A control loop automatic zeroing apparatus comprising:
an integrated circuit having an electrically-controlled control loop and an analog-to-digital converter having an input that selectively operably couples to two inputs of a loop error amplifier that comprises a part of the electrically-controlled control loop; a control circuit that is off-chip with respect to the integrated circuit and that operably couples to the analog-to-digital converter, wherein the control circuit is configured to: read digital versions corresponding to the two inputs of the loop error amplifier; when a first input to the loop error amplifier is greater than a second input to the loop error amplifier, sourcing a calibration signal to modify an offset for the loop error amplifier in a first direction; when the first input to the loop error amplifier is less than the second input to the loop error amplifier, sourcing a calibration signal to modify an offset for the loop error amplifier in a second direction that is different from the first direction. 7. The control loop automatic zeroing apparatus of claim 6 wherein the first input comprises a positive input and the second input comprises a negative input and wherein the first direction is a negative direction and the second direction is a positive direction. 8. The control loop automatic zeroing apparatus of claim 6 wherein the loop error amplifier comprises one of a voltage loop error amplifier and a current loop error amplifier. 9. The control loop automatic zeroing apparatus of claim 6 wherein the control circuit is further configured to control a sampling rate of the analog-to-digital converter. 10. The control loop automatic zeroing apparatus of claim 9 wherein the electrically-controlled control loop further comprises a second loop error amplifier and the input of the analog-to-digital converter further selectively operably couples to two inputs of the second loop error amplifier, and wherein the control circuit is configured to read digital versions corresponding to the inputs of both of the loop error amplifiers and to use a first sampling rate for the analog-to-digital converter when sampling the loop error amplifier and a second sampling rate that is different than the first sampling rate for the analog-to-digital converter when sampling the second loop error amplifier. 11. The control loop automatic zeroing apparatus of claim 10 wherein the loop error amplifier comprises a current loop error amplifier and the second loop error amplifier comprises a voltage loop error amplifier. 12. The control loop automatic zeroing apparatus of claim 11 wherein the first sampling rate is faster than the second sampling rate. 13. A method to facilitate calibrating an electrically-controlled control loop in an integrated circuit having the electrically-controlled control loop and an analog-to-digital converter having an input that selectively operably couples to two inputs of a loop error amplifier that comprises a part of the electrically-controlled control loop, the method comprising:
by a control circuit that is off-chip with respect to the integrated circuit and that operably couples to the analog-to-digital converter:
reading digital versions corresponding to the inputs to the loop error amplifier;
when a first input to the loop error amplifier is greater than a second input to the loop error amplifier, sourcing a calibration signal to modify an offset for the loop error amplifier in a first direction;
when the first input to the loop error amplifier is less than the second input to the loop error amplifier, sourcing a calibration signal to modify an offset for the loop error amplifier in a second direction that is different from the first direction;
such that the electronically-controlled control loop is auto-zeroed in a continuous manner and without breaking the control loop. 14. The method of claim 13 further comprising:
controlling a sampling rate of the analog-to-digital converter. 15. The method of claim 14 wherein controlling the sampling rate of the analog-to-digital converter comprises using a first sampling rate for the analog-to-digital converter when sampling a first loop error amplifier and a second sampling rate that is different than the first sampling rate for the analog-to-digital converter when sampling a second loop error amplifier. | An integrated circuit having at least one electrically-controlled control loop that includes one or more loop error amplifiers also includes an analog-to-digital converter having both an input that operably couples to two inputs of each loop error amplifier and an output that couples to an off-chip hardware component comprising a control circuit. This control circuit reads digital versions that correspond to the loop error amplifier inputs. When a particular first input is greater than a second input, the control circuit sources a calibration signal to modify and offset for the loop error amplifier in a first direction. When the first input is less than the second input, the control circuit sources a calibration signal to modify the offset for the loop error amplifier in a second direction that is different from the aforementioned first direction. By one approach the control circuit also controls a sampling rate of the analog-to-digital converter.1. An integrated circuit comprising:
an electrically-controlled control loop that includes a loop error amplifier; an analog-to-digital converter having an input that selectively operably couples to two inputs of the loop error amplifier and an output; and a contact pad that is operably coupled to the output of the analog-to-digital converter such that the analog-to-digital converter is operably accessible to an off-chip hardware component. 2. The integrated circuit of claim 1 wherein the electrically-controlled control loop comprises a part of a voltage regulator. 3. The integrated circuit of claim 2 wherein the voltage regulator comprises a part of a switched-mode power supply. 4. The integrated circuit of claim 1 wherein the electrically-controlled control loop further comprises a second loop error amplifier, and where the analog-to-digital converter input further selectively operably couples to two inputs of the second loop error amplifier. 5. The integrated circuit of claim 4 wherein the loop error amplifier comprises a voltage loop error amplifier and the second loop error amplifier comprises a current loop error amplifier. 6. A control loop automatic zeroing apparatus comprising:
an integrated circuit having an electrically-controlled control loop and an analog-to-digital converter having an input that selectively operably couples to two inputs of a loop error amplifier that comprises a part of the electrically-controlled control loop; a control circuit that is off-chip with respect to the integrated circuit and that operably couples to the analog-to-digital converter, wherein the control circuit is configured to: read digital versions corresponding to the two inputs of the loop error amplifier; when a first input to the loop error amplifier is greater than a second input to the loop error amplifier, sourcing a calibration signal to modify an offset for the loop error amplifier in a first direction; when the first input to the loop error amplifier is less than the second input to the loop error amplifier, sourcing a calibration signal to modify an offset for the loop error amplifier in a second direction that is different from the first direction. 7. The control loop automatic zeroing apparatus of claim 6 wherein the first input comprises a positive input and the second input comprises a negative input and wherein the first direction is a negative direction and the second direction is a positive direction. 8. The control loop automatic zeroing apparatus of claim 6 wherein the loop error amplifier comprises one of a voltage loop error amplifier and a current loop error amplifier. 9. The control loop automatic zeroing apparatus of claim 6 wherein the control circuit is further configured to control a sampling rate of the analog-to-digital converter. 10. The control loop automatic zeroing apparatus of claim 9 wherein the electrically-controlled control loop further comprises a second loop error amplifier and the input of the analog-to-digital converter further selectively operably couples to two inputs of the second loop error amplifier, and wherein the control circuit is configured to read digital versions corresponding to the inputs of both of the loop error amplifiers and to use a first sampling rate for the analog-to-digital converter when sampling the loop error amplifier and a second sampling rate that is different than the first sampling rate for the analog-to-digital converter when sampling the second loop error amplifier. 11. The control loop automatic zeroing apparatus of claim 10 wherein the loop error amplifier comprises a current loop error amplifier and the second loop error amplifier comprises a voltage loop error amplifier. 12. The control loop automatic zeroing apparatus of claim 11 wherein the first sampling rate is faster than the second sampling rate. 13. A method to facilitate calibrating an electrically-controlled control loop in an integrated circuit having the electrically-controlled control loop and an analog-to-digital converter having an input that selectively operably couples to two inputs of a loop error amplifier that comprises a part of the electrically-controlled control loop, the method comprising:
by a control circuit that is off-chip with respect to the integrated circuit and that operably couples to the analog-to-digital converter:
reading digital versions corresponding to the inputs to the loop error amplifier;
when a first input to the loop error amplifier is greater than a second input to the loop error amplifier, sourcing a calibration signal to modify an offset for the loop error amplifier in a first direction;
when the first input to the loop error amplifier is less than the second input to the loop error amplifier, sourcing a calibration signal to modify an offset for the loop error amplifier in a second direction that is different from the first direction;
such that the electronically-controlled control loop is auto-zeroed in a continuous manner and without breaking the control loop. 14. The method of claim 13 further comprising:
controlling a sampling rate of the analog-to-digital converter. 15. The method of claim 14 wherein controlling the sampling rate of the analog-to-digital converter comprises using a first sampling rate for the analog-to-digital converter when sampling a first loop error amplifier and a second sampling rate that is different than the first sampling rate for the analog-to-digital converter when sampling a second loop error amplifier. | 2,800 |
11,913 | 11,913 | 14,497,920 | 2,815 | A layer of P-metal material having a work function of about 4.3 or 4.4 eV or less is formed over a high-k dielectric layer. Portions of the N-metal layer are converted to P-metal materials by introducing additives such as O, C, N, Si or others to produce a P-metal material having an increased work function of about 4.7 or 4.8 eV or greater. A TaC film may be converted to a material of TaCO, TaCN, or TaCON using this technique. The layer of material including original N-metal portions and converted P-metal portions is then patterned using a single patterning operation to simultaneously form semiconductor devices from both the unconverted N-metal sections and converted P-metal sections. | 1. A method for forming a semiconductor device comprising:
forming an N-metal layer suitable for use as a gate electrode for N-metal semiconductor devices, over a surface of a substrate; converting portions of said N-metal layer to P-metal portions suitable for use as gate electrodes in P-metal semiconductor devices; and forming N-metal semiconductor devices using unconverted sections of said N-metal layer and P-metal semiconductor devices using sections of said P-metal portions, wherein said N-metal layer comprises TaN and said P-metal portions comprise TaSiN and said converting includes forming a patterned removable layer over said N-metal layer, said patterned removable layer formed of polysilicon. 2. The method as in claim 1, further comprising forming a high-k gate dielectric material over said surface, and wherein said forming an N-metal layer comprises forming said N-metal layer over said high-k gate dielectric material. 3. The method as in claim 2, wherein said high-k gate dielectric material comprises one of lanthanum oxide, La2O3, aluminum oxide, Al2O3 and hafnium oxide. 4. The method as in claim 2, wherein said converting comprises adding Si to said N-metal layer and said high-k gate dielectric material comprises one of hafnium oxynitride, HfON and zirconium oxide. 5. The method as in claim 1, wherein said N-metal layer includes a work function of about 4.4 eV or less and said converting comprises said P-metal sections having a work function of about 4.8 eV or higher. 6. The method as in claim 1, wherein said converting comprises adding Si to said N-metal layer using one of ion implantation, diffusion and GCIB (gas cluster ion beam) implantation. 7. The method as in claim 6, wherein said forming N-metal semiconductor devices and P-metal semiconductor devices comprises simultaneously etching said unconverted portions of said N-metal layer and said P-metal portions,
said forming N-metal semiconductor devices comprises forming at least an N-type metal gate MOSFET, and said forming P-metal semiconductor devices comprises forming at least one P-type metal gate MOSFET. 8. The method as in claim 1, wherein said portions comprise portions of said N-metal layer that are not covered by said patterned removable layer, and further comprising removing said patterned removable layer after said converting. 9. The method as in claim 1, wherein said forming an N-metal layer comprises forming said N-metal layer over a high-k dielectric formed over said surface, said forming N-metal semiconductor devices and said forming P-metal semiconductor devices includes using said high-k dielectric as a gate dielectric and said N-metal semiconductor devices and said P-metal semiconductor devices each comprise metal gate transistors. 10. The method as in claim 1, wherein said converting comprises adding Si to said N-metal layer. 11. A method for forming a semiconductor device comprising:
forming an N-metal layer suitable for use as a gate electrode for N-metal semiconductor devices, over a surface of a substrate; converting portions of said N-metal layer to P-metal portions suitable for use as gate electrodes in P-metal semiconductor devices; and forming N-metal semiconductor devices using unconverted sections of said N-metal layer and P-metal semiconductor devices using sections of said P-metal portions, wherein said converting comprises adding Si to said N-metal layer to convert said portions of said N-metal layer to said P-metal portions and said converting includes forming a patterned removable layer over said N-metal layer, said patterned removable layer formed of polysilicon. 12. The method as in claim 11, wherein said N-metal layer comprises TaN and said P-Metal portions comprise TaSiN. 13. The method as in claim 11, further comprising forming a high-k gate dielectric material over said surface, and wherein said forming an N-metal layer comprises forming said N-metal layer over said high-k gate dielectric material. 14. The method as in claim 13, wherein said high-k gate dielectric material comprises one of lanthanum oxide, La2O3, aluminum oxide, Al2O3, hafnium oxide, hafnium oxynitride, HfON and zirconium oxide. 15. A method for forming a semiconductor device comprising:
forming an N-metal layer suitable for use as a gate electrode for N-metal semiconductor devices, over a surface of a substrate; converting portions of said N-metal layer to P-metal portions suitable for use as gate electrodes in P-metal semiconductor devices; and forming N-metal semiconductor devices using unconverted sections of said N-metal layer and P-metal semiconductor devices using sections of said P-metal portions, wherein said converting comprises adding Si to said N-metal layer to convert said portions of said N-metal layer to said P-metal portions, and wherein said N-metal layer comprises TaN and said P-metal portions comprise TaSiN and said converting further comprises forming a patterned removable layer over said N-metal layer, said patterned removable layer formed of polysilicon. 16. The method as in claim 15, further comprising forming a high-k gate dielectric material over said surface of said substrate and wherein said forming an N-metal layer comprises forming said N-metal layer over said high-k gate dielectric material. 17. The method as in claim 16, wherein said high-k gate dielectric material comprises one of lanthanum oxide, La2O3, aluminum oxide, Al2O3 and hafnium oxide 18. The method as in claim 15, wherein said adding Si comprises GCIB (gas cluster ion beam) implantation and wherein said high-k gate dielectric material comprises hafnium oxynitride, HfON. 18. The method as in claim 15, wherein said portions comprise portions of said N-metal layer that are not covered by said patterned removable layer, and further comprising removing said patterned removable layer after said converting. 20. The method as in claim 15, wherein said adding Si includes using one of ion implantation, diffusion and GCIB (gas cluster ion beam) implantation and said forming N-metal semiconductor devices and P-metal semiconductor devices comprises simultaneously etching said unconverted portions of said N-metal layer and said P-metal portions. | A layer of P-metal material having a work function of about 4.3 or 4.4 eV or less is formed over a high-k dielectric layer. Portions of the N-metal layer are converted to P-metal materials by introducing additives such as O, C, N, Si or others to produce a P-metal material having an increased work function of about 4.7 or 4.8 eV or greater. A TaC film may be converted to a material of TaCO, TaCN, or TaCON using this technique. The layer of material including original N-metal portions and converted P-metal portions is then patterned using a single patterning operation to simultaneously form semiconductor devices from both the unconverted N-metal sections and converted P-metal sections.1. A method for forming a semiconductor device comprising:
forming an N-metal layer suitable for use as a gate electrode for N-metal semiconductor devices, over a surface of a substrate; converting portions of said N-metal layer to P-metal portions suitable for use as gate electrodes in P-metal semiconductor devices; and forming N-metal semiconductor devices using unconverted sections of said N-metal layer and P-metal semiconductor devices using sections of said P-metal portions, wherein said N-metal layer comprises TaN and said P-metal portions comprise TaSiN and said converting includes forming a patterned removable layer over said N-metal layer, said patterned removable layer formed of polysilicon. 2. The method as in claim 1, further comprising forming a high-k gate dielectric material over said surface, and wherein said forming an N-metal layer comprises forming said N-metal layer over said high-k gate dielectric material. 3. The method as in claim 2, wherein said high-k gate dielectric material comprises one of lanthanum oxide, La2O3, aluminum oxide, Al2O3 and hafnium oxide. 4. The method as in claim 2, wherein said converting comprises adding Si to said N-metal layer and said high-k gate dielectric material comprises one of hafnium oxynitride, HfON and zirconium oxide. 5. The method as in claim 1, wherein said N-metal layer includes a work function of about 4.4 eV or less and said converting comprises said P-metal sections having a work function of about 4.8 eV or higher. 6. The method as in claim 1, wherein said converting comprises adding Si to said N-metal layer using one of ion implantation, diffusion and GCIB (gas cluster ion beam) implantation. 7. The method as in claim 6, wherein said forming N-metal semiconductor devices and P-metal semiconductor devices comprises simultaneously etching said unconverted portions of said N-metal layer and said P-metal portions,
said forming N-metal semiconductor devices comprises forming at least an N-type metal gate MOSFET, and said forming P-metal semiconductor devices comprises forming at least one P-type metal gate MOSFET. 8. The method as in claim 1, wherein said portions comprise portions of said N-metal layer that are not covered by said patterned removable layer, and further comprising removing said patterned removable layer after said converting. 9. The method as in claim 1, wherein said forming an N-metal layer comprises forming said N-metal layer over a high-k dielectric formed over said surface, said forming N-metal semiconductor devices and said forming P-metal semiconductor devices includes using said high-k dielectric as a gate dielectric and said N-metal semiconductor devices and said P-metal semiconductor devices each comprise metal gate transistors. 10. The method as in claim 1, wherein said converting comprises adding Si to said N-metal layer. 11. A method for forming a semiconductor device comprising:
forming an N-metal layer suitable for use as a gate electrode for N-metal semiconductor devices, over a surface of a substrate; converting portions of said N-metal layer to P-metal portions suitable for use as gate electrodes in P-metal semiconductor devices; and forming N-metal semiconductor devices using unconverted sections of said N-metal layer and P-metal semiconductor devices using sections of said P-metal portions, wherein said converting comprises adding Si to said N-metal layer to convert said portions of said N-metal layer to said P-metal portions and said converting includes forming a patterned removable layer over said N-metal layer, said patterned removable layer formed of polysilicon. 12. The method as in claim 11, wherein said N-metal layer comprises TaN and said P-Metal portions comprise TaSiN. 13. The method as in claim 11, further comprising forming a high-k gate dielectric material over said surface, and wherein said forming an N-metal layer comprises forming said N-metal layer over said high-k gate dielectric material. 14. The method as in claim 13, wherein said high-k gate dielectric material comprises one of lanthanum oxide, La2O3, aluminum oxide, Al2O3, hafnium oxide, hafnium oxynitride, HfON and zirconium oxide. 15. A method for forming a semiconductor device comprising:
forming an N-metal layer suitable for use as a gate electrode for N-metal semiconductor devices, over a surface of a substrate; converting portions of said N-metal layer to P-metal portions suitable for use as gate electrodes in P-metal semiconductor devices; and forming N-metal semiconductor devices using unconverted sections of said N-metal layer and P-metal semiconductor devices using sections of said P-metal portions, wherein said converting comprises adding Si to said N-metal layer to convert said portions of said N-metal layer to said P-metal portions, and wherein said N-metal layer comprises TaN and said P-metal portions comprise TaSiN and said converting further comprises forming a patterned removable layer over said N-metal layer, said patterned removable layer formed of polysilicon. 16. The method as in claim 15, further comprising forming a high-k gate dielectric material over said surface of said substrate and wherein said forming an N-metal layer comprises forming said N-metal layer over said high-k gate dielectric material. 17. The method as in claim 16, wherein said high-k gate dielectric material comprises one of lanthanum oxide, La2O3, aluminum oxide, Al2O3 and hafnium oxide 18. The method as in claim 15, wherein said adding Si comprises GCIB (gas cluster ion beam) implantation and wherein said high-k gate dielectric material comprises hafnium oxynitride, HfON. 18. The method as in claim 15, wherein said portions comprise portions of said N-metal layer that are not covered by said patterned removable layer, and further comprising removing said patterned removable layer after said converting. 20. The method as in claim 15, wherein said adding Si includes using one of ion implantation, diffusion and GCIB (gas cluster ion beam) implantation and said forming N-metal semiconductor devices and P-metal semiconductor devices comprises simultaneously etching said unconverted portions of said N-metal layer and said P-metal portions. | 2,800 |
11,914 | 11,914 | 15,308,489 | 2,837 | This ferroelectric thin film comprises lead zirconate titanate niobate. In said ferroelectric thin film, the ratio (a) of number of moles of lead to the total number of moles of zirconium, titanium, and niobium is greater than or equal to 100%; the ratio (b) of the number of moles of niobium to the total number of moles of zirconium, titanium, and niobium is between 10% and 20%, inclusive; and the ratio (c) of the number of moles of zirconium to the total number of moles of zirconium and titanium is between 52% and 59%, inclusive. The film stress exhibited by the ferroelectric thin film is between 100 and 250 MPa, inclusive. | 1. A ferroelectric thin film comprising lead niobate titanate zirconate, wherein
a ratio “a” of lead to a sum of zirconium, titanium, and niobium is 100% or more by mol ratio, a ratio “b” of niobium to the sum of zirconium, titanium, and niobium is 10% or more but 20% or less by mol ratio, a ratio “c” of zirconium to a sum of zirconium and titanium is 52% or more but 59% or less by mol ratio, and a film stress is 100 MPa or more but 250 MPa or less. 2. The ferroelectric thin film of claim 1, wherein the ratio “a” is 105% or less by mol ratio. 3. A ferroelectric thin film comprising lead niobate titanate zirconate, wherein
a ratio “a” of lead to a sum of zirconium, titanium, and niobium is 100% or more but 105% or less by mol ratio, a ratio “b” of niobium to the sum of zirconium, titanium, and niobium is 10% or more but 20% or less by mol ratio, and a ratio “c” of zirconium to a sum of zirconium and titanium is 54% or more but 59% or less by mol ratio. 4. The ferroelectric thin film of claim 1, wherein
the ratio “b” is 15% or more but 19% or less by mol ratio, and the ratio “c” is 55% or more but 59% or less by mol ratio. 5. The ferroelectric thin film of claim 1, wherein
a crystal orientation of the film is a (100) orientation of a pseudo-cubic crystal. 6. The ferroelectric thin film of claim 1, wherein
a crystal structure of the film is a columnar crystal. 7. The ferroelectric thin film of claim 1, wherein
a film thickness is 1 μm or more but 10 μm or less. 8. A piezoelectric thin film-coated substrate having a piezoelectric thin film formed as an upper layer relative to a substrate, wherein
the piezoelectric thin film comprises the ferroelectric thin film according to claim 1. 9. The piezoelectric thin film-coated substrate of claim 8, wherein
the substrate comprises a silicon substrate or an SOI substrate. 10. The piezoelectric thin film-coated substrate of claim 8, wherein
a seed layer for controlling crystal orientation of the piezoelectric thin film is disposed between the substrate and the piezoelectric thin film. 11. The piezoelectric thin film-coated substrate of claim 10, wherein
the seed layer comprises lead lanthanum. 12. The piezoelectric thin film-coated substrate of claim 8, wherein
an electrode is formed between the substrate and the piezoelectric thin film. 13. A piezoelectric actuator comprising:
the piezoelectric thin film-coated substrate of claim 12; and another electrode formed on a side opposite from the electrode with respect to the piezoelectric thin film of the piezoelectric thin film-coated substrate. 14. An inkjet head comprising:
the piezoelectric actuator of claim 13; and a nozzle substrate having a nozzle orifice through which ink stored in a cavity formed in the substrate of the piezoelectric actuator is ejected to outside. 15. An inkjet printer comprising the inkjet head of claim 14, wherein
the ink is ejected from the inkjet head onto a recording medium. 16. The ferroelectric thin film of claim 3, wherein a film stress is 100 MPa or more but 250 MPa or less. 17. The ferroelectric thin film of claim 3, wherein
the ratio “b” is 15% or more but 19% or less by mol ratio, and the ratio “c” is 55% or more but 59% or less by mol ratio. 18. The ferroelectric thin film of claim 3, wherein
a crystal orientation of the film is a (100) orientation of a pseudo-cubic crystal. 19. The ferroelectric thin film of claim 3, wherein
a crystal structure of the film is a columnar crystal. 20. The ferroelectric thin film of claim 3, wherein
a film thickness is 1 μm or more but 10 μm or less. | This ferroelectric thin film comprises lead zirconate titanate niobate. In said ferroelectric thin film, the ratio (a) of number of moles of lead to the total number of moles of zirconium, titanium, and niobium is greater than or equal to 100%; the ratio (b) of the number of moles of niobium to the total number of moles of zirconium, titanium, and niobium is between 10% and 20%, inclusive; and the ratio (c) of the number of moles of zirconium to the total number of moles of zirconium and titanium is between 52% and 59%, inclusive. The film stress exhibited by the ferroelectric thin film is between 100 and 250 MPa, inclusive.1. A ferroelectric thin film comprising lead niobate titanate zirconate, wherein
a ratio “a” of lead to a sum of zirconium, titanium, and niobium is 100% or more by mol ratio, a ratio “b” of niobium to the sum of zirconium, titanium, and niobium is 10% or more but 20% or less by mol ratio, a ratio “c” of zirconium to a sum of zirconium and titanium is 52% or more but 59% or less by mol ratio, and a film stress is 100 MPa or more but 250 MPa or less. 2. The ferroelectric thin film of claim 1, wherein the ratio “a” is 105% or less by mol ratio. 3. A ferroelectric thin film comprising lead niobate titanate zirconate, wherein
a ratio “a” of lead to a sum of zirconium, titanium, and niobium is 100% or more but 105% or less by mol ratio, a ratio “b” of niobium to the sum of zirconium, titanium, and niobium is 10% or more but 20% or less by mol ratio, and a ratio “c” of zirconium to a sum of zirconium and titanium is 54% or more but 59% or less by mol ratio. 4. The ferroelectric thin film of claim 1, wherein
the ratio “b” is 15% or more but 19% or less by mol ratio, and the ratio “c” is 55% or more but 59% or less by mol ratio. 5. The ferroelectric thin film of claim 1, wherein
a crystal orientation of the film is a (100) orientation of a pseudo-cubic crystal. 6. The ferroelectric thin film of claim 1, wherein
a crystal structure of the film is a columnar crystal. 7. The ferroelectric thin film of claim 1, wherein
a film thickness is 1 μm or more but 10 μm or less. 8. A piezoelectric thin film-coated substrate having a piezoelectric thin film formed as an upper layer relative to a substrate, wherein
the piezoelectric thin film comprises the ferroelectric thin film according to claim 1. 9. The piezoelectric thin film-coated substrate of claim 8, wherein
the substrate comprises a silicon substrate or an SOI substrate. 10. The piezoelectric thin film-coated substrate of claim 8, wherein
a seed layer for controlling crystal orientation of the piezoelectric thin film is disposed between the substrate and the piezoelectric thin film. 11. The piezoelectric thin film-coated substrate of claim 10, wherein
the seed layer comprises lead lanthanum. 12. The piezoelectric thin film-coated substrate of claim 8, wherein
an electrode is formed between the substrate and the piezoelectric thin film. 13. A piezoelectric actuator comprising:
the piezoelectric thin film-coated substrate of claim 12; and another electrode formed on a side opposite from the electrode with respect to the piezoelectric thin film of the piezoelectric thin film-coated substrate. 14. An inkjet head comprising:
the piezoelectric actuator of claim 13; and a nozzle substrate having a nozzle orifice through which ink stored in a cavity formed in the substrate of the piezoelectric actuator is ejected to outside. 15. An inkjet printer comprising the inkjet head of claim 14, wherein
the ink is ejected from the inkjet head onto a recording medium. 16. The ferroelectric thin film of claim 3, wherein a film stress is 100 MPa or more but 250 MPa or less. 17. The ferroelectric thin film of claim 3, wherein
the ratio “b” is 15% or more but 19% or less by mol ratio, and the ratio “c” is 55% or more but 59% or less by mol ratio. 18. The ferroelectric thin film of claim 3, wherein
a crystal orientation of the film is a (100) orientation of a pseudo-cubic crystal. 19. The ferroelectric thin film of claim 3, wherein
a crystal structure of the film is a columnar crystal. 20. The ferroelectric thin film of claim 3, wherein
a film thickness is 1 μm or more but 10 μm or less. | 2,800 |
11,915 | 11,915 | 14,964,248 | 2,894 | A flip-chip on leadframe package includes a leadframe having a plurality of leads with each lead including an inner leadfinger portion, wherein at least a landing region of all of the inner leadfinger portions are in a single common level (or plane) and include etched areas providing bump pads having concave landing sites (landing sites). A semiconductor die (die) having an active top side surface with functional circuitry including bond pads has bumps or pillars thereon. An area of the landing sites is greater than an area of the bumps or pillars. A distal end of the bumps or pillars is within and electrically coupling to the landing sites. A mold material encapsulates the die and at least a portion of the inner leadfinger portions. The package can be a leaded package or a leadless package. | 1. An integrated circuit (IC) package, comprising:
a leadframe comprising a plurality of leads with each said lead including an inner leadfinger portion, wherein at least a landing region of all of said inner leadfinger portions include partially-etched areas providing bump pads having concave landing sites (landing sites); a semiconductor die (die) having an active top side surface with functional circuitry including bond pads with bumps or pillars thereon; wherein an area of said landing sites is greater than an area of said bumps or pillars; wherein a distal end of said bumps or pillars is within and electrically coupled to said landing sites, and a mold material encapsulating said die and at least a portion of said inner leadfinger portions. 2. The IC package of claim 1, wherein said leads each include an external lead portion connected to said inner leadfinger portion extending out from said mold material. 3. The IC package of claim 1, wherein said leads consist of said inner leadfinger portions, and a periphery of said inner leadfinger portions on a bottom of said IC package are exposed from said mold material. 4. The IC package of claim 1, wherein said landing sites include an electroplated layer comprising a metal alloy. 5. The IC package of claim 1, wherein said landing sites have one of a semi-circular, rectangular and trapezoidal cross sectional shape. 6. The IC package of claim 1, wherein said leadframe comprises one of a copper and a copper alloy. 7. The IC package of claim 1, wherein said bumps consist of solder bumps. 8. The IC package of claim 1, wherein said leadframe excludes a die pad. 9. The IC package of claim 1, wherein said area of said landing sites is greater than said area of said bumps or pillars by a factor of 1.1 to 1.5. 10. A method of assembling a flip-chip on leadframe package, comprising:
providing a leadframe comprising a plurality of leads with each said lead including an inner leadfinger portion, wherein at least a landing region of all of said inner leadfinger portions are in a single common level and include partially-etched areas providing bump pads having concave landing sites (landing sites); positioning a semiconductor die (die) having an active top side surface with functional circuitry including bond pads with bumps or pillars thereon so that a distal end of said bumps or pillars are within and physically contacting said landing sites, and a heating process for reflowing so that at least said distal end of said bumps or pillars become electrically coupled to said landing sites. 11. The method of claim 10, further comprising forming a mold material providing encapsulation for said die and said inner leadfinger portions. 12. The method of claim 10, further comprising electroplating a plating layer comprising a metal alloy compatible with a material of said distal end of said bump or said pillar in said landing sites before said positioning. 13. The method of claim 10, further comprising applying solder paste or flux to said landing sites before said positioning. 14. The method of claim 11, wherein said leads each include an external lead portion connected to said inner leadfinger portion extending out from said mold material to provide a leaded package. 15. The method of claim 11, wherein said leads consist of said inner leadfinger portions, and a periphery of said inner leadfinger portions on a bottom of said packaged are exposed from said mold material. 16. The method of claim 10, wherein said bumps or pillars consist of solder bumps. 17. The method of claim 10, wherein said area of said landing sites is greater than said area of said bumps or pillars by a factor of 1.1 to 1.5. | A flip-chip on leadframe package includes a leadframe having a plurality of leads with each lead including an inner leadfinger portion, wherein at least a landing region of all of the inner leadfinger portions are in a single common level (or plane) and include etched areas providing bump pads having concave landing sites (landing sites). A semiconductor die (die) having an active top side surface with functional circuitry including bond pads has bumps or pillars thereon. An area of the landing sites is greater than an area of the bumps or pillars. A distal end of the bumps or pillars is within and electrically coupling to the landing sites. A mold material encapsulates the die and at least a portion of the inner leadfinger portions. The package can be a leaded package or a leadless package.1. An integrated circuit (IC) package, comprising:
a leadframe comprising a plurality of leads with each said lead including an inner leadfinger portion, wherein at least a landing region of all of said inner leadfinger portions include partially-etched areas providing bump pads having concave landing sites (landing sites); a semiconductor die (die) having an active top side surface with functional circuitry including bond pads with bumps or pillars thereon; wherein an area of said landing sites is greater than an area of said bumps or pillars; wherein a distal end of said bumps or pillars is within and electrically coupled to said landing sites, and a mold material encapsulating said die and at least a portion of said inner leadfinger portions. 2. The IC package of claim 1, wherein said leads each include an external lead portion connected to said inner leadfinger portion extending out from said mold material. 3. The IC package of claim 1, wherein said leads consist of said inner leadfinger portions, and a periphery of said inner leadfinger portions on a bottom of said IC package are exposed from said mold material. 4. The IC package of claim 1, wherein said landing sites include an electroplated layer comprising a metal alloy. 5. The IC package of claim 1, wherein said landing sites have one of a semi-circular, rectangular and trapezoidal cross sectional shape. 6. The IC package of claim 1, wherein said leadframe comprises one of a copper and a copper alloy. 7. The IC package of claim 1, wherein said bumps consist of solder bumps. 8. The IC package of claim 1, wherein said leadframe excludes a die pad. 9. The IC package of claim 1, wherein said area of said landing sites is greater than said area of said bumps or pillars by a factor of 1.1 to 1.5. 10. A method of assembling a flip-chip on leadframe package, comprising:
providing a leadframe comprising a plurality of leads with each said lead including an inner leadfinger portion, wherein at least a landing region of all of said inner leadfinger portions are in a single common level and include partially-etched areas providing bump pads having concave landing sites (landing sites); positioning a semiconductor die (die) having an active top side surface with functional circuitry including bond pads with bumps or pillars thereon so that a distal end of said bumps or pillars are within and physically contacting said landing sites, and a heating process for reflowing so that at least said distal end of said bumps or pillars become electrically coupled to said landing sites. 11. The method of claim 10, further comprising forming a mold material providing encapsulation for said die and said inner leadfinger portions. 12. The method of claim 10, further comprising electroplating a plating layer comprising a metal alloy compatible with a material of said distal end of said bump or said pillar in said landing sites before said positioning. 13. The method of claim 10, further comprising applying solder paste or flux to said landing sites before said positioning. 14. The method of claim 11, wherein said leads each include an external lead portion connected to said inner leadfinger portion extending out from said mold material to provide a leaded package. 15. The method of claim 11, wherein said leads consist of said inner leadfinger portions, and a periphery of said inner leadfinger portions on a bottom of said packaged are exposed from said mold material. 16. The method of claim 10, wherein said bumps or pillars consist of solder bumps. 17. The method of claim 10, wherein said area of said landing sites is greater than said area of said bumps or pillars by a factor of 1.1 to 1.5. | 2,800 |
11,916 | 11,916 | 15,611,218 | 2,852 | A method of operating a particulate matter sensor includes accumulating particulate matter on the sensor, thereby changing resistance between electrodes of the sensor. The sensor provides a signal that varies based upon an amount of the particulate matter on the sensor and includes a measurement cycle that includes a deadband zone in which the resistance is greater than a first predetermined value, followed by an active zone in which the resistance is less than or equal to the first predetermined value, followed by a regeneration zone. A first bias voltage is applied across the electrodes during the deadband zone and a second bias voltage which is less than the first bias voltage is applied across the electrodes during the active zone. An output that is representative of the amount of the particulate matter is calculated after an end of the deadband zone is reached and prior to an end of the measurement cycle. | 1. A method of operating a particulate matter sensor having a pair of spaced apart electrodes, said method comprising the steps of:
accumulating particulate matter on said particulate matter sensor, thereby changing resistance between said pair of spaced apart electrodes, wherein said particulate matter sensor provides a signal that varies based upon an amount of the particulate matter on said particulate matter sensor, wherein said particulate matter sensor includes a measurement cycle that includes a deadband zone in which said resistance is greater than a first predetermined value, followed by an active zone in which said resistance is less than or equal to said first predetermined value, which is followed by a regeneration zone; applying a first bias voltage across said pair of spaced apart electrodes during said deadband zone; applying a second bias voltage across said pair of spaced apart electrodes during said active zone such that said first bias voltage is greater than said second bias voltage; and calculating an output that is representative of the amount of the particulate matter after an end of the deadband zone is reached and prior to an end of the measurement cycle. 2. A method in accordance with claim 1, wherein said resistance during said active zone is greater than a second predetermined value. 3. A method in accordance with claim 1, wherein said first bias voltage is in a range of 24V to 48V. 4. A method in accordance with claim 3, wherein said second bias voltage is in a range of 3V to 6V. 5. A method in accordance with claim 1, wherein said first bias voltage accumulates the particulate matter on said particulate matter sensor at a first rate and said second bias voltage accumulates particulate matter on said particulate matter sensor at a second rate which is less than said first rate. 6. A method in accordance with claim 1, wherein a change from said first bias voltage to said second bias voltage is triggered based on said resistance being said first predetermined value. 7. A method in accordance with claim 1, wherein said first bias voltage is in a range of 20% to 50% of a dielectric breakdown voltage of said particulate matter sensor. 8. A method in accordance with claim 7, wherein said second bias voltage is in a range of 1% to 20% of said dielectric breakdown voltage of said particulate matter sensor. 9. A method in accordance with claim 8, wherein the difference between said first bias voltage and said second bias voltage, as a percentage of said dielectric breakdown voltage of said particulate matter sensor, is at least 10%. | A method of operating a particulate matter sensor includes accumulating particulate matter on the sensor, thereby changing resistance between electrodes of the sensor. The sensor provides a signal that varies based upon an amount of the particulate matter on the sensor and includes a measurement cycle that includes a deadband zone in which the resistance is greater than a first predetermined value, followed by an active zone in which the resistance is less than or equal to the first predetermined value, followed by a regeneration zone. A first bias voltage is applied across the electrodes during the deadband zone and a second bias voltage which is less than the first bias voltage is applied across the electrodes during the active zone. An output that is representative of the amount of the particulate matter is calculated after an end of the deadband zone is reached and prior to an end of the measurement cycle.1. A method of operating a particulate matter sensor having a pair of spaced apart electrodes, said method comprising the steps of:
accumulating particulate matter on said particulate matter sensor, thereby changing resistance between said pair of spaced apart electrodes, wherein said particulate matter sensor provides a signal that varies based upon an amount of the particulate matter on said particulate matter sensor, wherein said particulate matter sensor includes a measurement cycle that includes a deadband zone in which said resistance is greater than a first predetermined value, followed by an active zone in which said resistance is less than or equal to said first predetermined value, which is followed by a regeneration zone; applying a first bias voltage across said pair of spaced apart electrodes during said deadband zone; applying a second bias voltage across said pair of spaced apart electrodes during said active zone such that said first bias voltage is greater than said second bias voltage; and calculating an output that is representative of the amount of the particulate matter after an end of the deadband zone is reached and prior to an end of the measurement cycle. 2. A method in accordance with claim 1, wherein said resistance during said active zone is greater than a second predetermined value. 3. A method in accordance with claim 1, wherein said first bias voltage is in a range of 24V to 48V. 4. A method in accordance with claim 3, wherein said second bias voltage is in a range of 3V to 6V. 5. A method in accordance with claim 1, wherein said first bias voltage accumulates the particulate matter on said particulate matter sensor at a first rate and said second bias voltage accumulates particulate matter on said particulate matter sensor at a second rate which is less than said first rate. 6. A method in accordance with claim 1, wherein a change from said first bias voltage to said second bias voltage is triggered based on said resistance being said first predetermined value. 7. A method in accordance with claim 1, wherein said first bias voltage is in a range of 20% to 50% of a dielectric breakdown voltage of said particulate matter sensor. 8. A method in accordance with claim 7, wherein said second bias voltage is in a range of 1% to 20% of said dielectric breakdown voltage of said particulate matter sensor. 9. A method in accordance with claim 8, wherein the difference between said first bias voltage and said second bias voltage, as a percentage of said dielectric breakdown voltage of said particulate matter sensor, is at least 10%. | 2,800 |
11,917 | 11,917 | 15,424,958 | 2,853 | A printing apparatus, such as a large-scale ink jet printer, includes two removable, interchangeable dryer modules, which may be operated separately or in series. Each dryer module permits a sheet or web to pass therethrough in a process direction. Each dryer module includes a lamp mount, suitable for holding one or more heating or curing lamps, the lamp mount being slidably disposed within the module for easy access to the lamps. Each dryer module defines a top portion suitable for maintaining an airflow above the lamp mount, and a bottom portion suitable for maintaining an airflow below the lamp mount. A plate having a pattern of openings therein enables an airflow through the lamps. | 1. A dryer module for use in printing, comprising:
a cabinet forming a chamber with a top portion and a bottom portion; the cabinet defining a plurality of sheet slots, for passage of a sheet through the chamber in a process direction; a lamp mount, suitable for holding one or more lamps, slidably disposed relative to the cabinet, whereby the lamp mount may be at least partially removed from the chamber for access to at least one lamp; the cabinet defining a first air opening and a second air opening, suitable for permitting a first airflow through the top portion of the chamber, the first airflow passing over the lamp mount, transverse to the process direction; and the cabinet defining a third air opening and a fourth air opening, the third air opening permitting air to enter the bottom portion of the chamber, permitting a second airflow through the bottom portion of the chamber, the second airflow passing under the lamp mount. 2. The module of claim 1, further comprising a plate disposed between the bottom of the chamber and the lamp mount, the plate defining a plurality of small openings. 3. The module of claim 2, the plurality of small openings defining a total area in the plate comparable to the area of the third air opening. 4. The module of claim 1, further comprising a cover plate forming a portion of the cabinet, the cover plate being openable for accessing the lamp mount. 5. The module of claim 4, the cover plate defining the first air opening. 6. The module of claim 4, the cover plate being configured so that the lamp mount may be accessed while the module is disposed within a printing apparatus. 7. The module of claim 1, wherein the lamp mount retains the lamps so that the lamps extend perpendicular to the process direction. 8. A printing apparatus comprising a first dryer module and a second dryer module, each dryer module including,
a cabinet forming a chamber with a top portion and a bottom portion; the cabinet defining a plurality of sheet slots, for passage of a substrate through the chamber in a process direction; a lamp mount, suitable for holding one or more lamps, slidably disposed relative to the cabinet, whereby the lamp mount may be at least partially removed from the chamber for access to at least one lamp; the cabinet defining a first air opening and a second air opening, suitable for permitting a first airflow through the top portion of the chamber, the first airflow passing over the lamp mount, transverse to the process direction; and the cabinet defining a third air opening and a fourth air opening, suitable for permitting a second airflow through the bottom portion of the chamber, the first airflow passing under the lamp mount. 9. The printing apparatus of claim 8, wherein the first dryer module and the second dryer module are interchangeable in position within the printing apparatus. 10. The printing apparatus of claim 8, wherein the first dryer module and the second dryer module are disposed in series within the printing apparatus, so that a sheet may pass through the first dryer module and then immediately through the second dryer module. 11. The printing apparatus of claim 10, operable whereby the first dryer module is energized to perform drying and the second dryer module is turned off. 12. The printing apparatus of claim 8, further comprising at least one blower, the blower drawing the first airflow from the top portion of the chamber of at least one dryer module and directing the airflow into the bottom portion of the chamber of the at least one dryer module. 13. A printing apparatus comprising a first dryer module and a second dryer module, each dryer module including
(a) a cabinet defining a plurality of sheet slots, for passage of a substrate through the chamber in a process direction, and (b) a lamp mount, suitable for holding one or more lamps; and wherein the first dryer module and the second dryer module are interchangeable in position within the printing apparatus. 14. The printing apparatus of claim 13, wherein the first dryer module and the second dryer module are disposed in series within the printing apparatus, so that a sheet may pass through the first dryer module and then immediately through the second dryer module. 15. The printing apparatus of claim 14, operable whereby the first dryer module is energized to perform drying and the second dryer module is turned off. 16. The printing apparatus of claim 13, further comprising at least one blower, the blower drawing airflow through at least one dryer module. | A printing apparatus, such as a large-scale ink jet printer, includes two removable, interchangeable dryer modules, which may be operated separately or in series. Each dryer module permits a sheet or web to pass therethrough in a process direction. Each dryer module includes a lamp mount, suitable for holding one or more heating or curing lamps, the lamp mount being slidably disposed within the module for easy access to the lamps. Each dryer module defines a top portion suitable for maintaining an airflow above the lamp mount, and a bottom portion suitable for maintaining an airflow below the lamp mount. A plate having a pattern of openings therein enables an airflow through the lamps.1. A dryer module for use in printing, comprising:
a cabinet forming a chamber with a top portion and a bottom portion; the cabinet defining a plurality of sheet slots, for passage of a sheet through the chamber in a process direction; a lamp mount, suitable for holding one or more lamps, slidably disposed relative to the cabinet, whereby the lamp mount may be at least partially removed from the chamber for access to at least one lamp; the cabinet defining a first air opening and a second air opening, suitable for permitting a first airflow through the top portion of the chamber, the first airflow passing over the lamp mount, transverse to the process direction; and the cabinet defining a third air opening and a fourth air opening, the third air opening permitting air to enter the bottom portion of the chamber, permitting a second airflow through the bottom portion of the chamber, the second airflow passing under the lamp mount. 2. The module of claim 1, further comprising a plate disposed between the bottom of the chamber and the lamp mount, the plate defining a plurality of small openings. 3. The module of claim 2, the plurality of small openings defining a total area in the plate comparable to the area of the third air opening. 4. The module of claim 1, further comprising a cover plate forming a portion of the cabinet, the cover plate being openable for accessing the lamp mount. 5. The module of claim 4, the cover plate defining the first air opening. 6. The module of claim 4, the cover plate being configured so that the lamp mount may be accessed while the module is disposed within a printing apparatus. 7. The module of claim 1, wherein the lamp mount retains the lamps so that the lamps extend perpendicular to the process direction. 8. A printing apparatus comprising a first dryer module and a second dryer module, each dryer module including,
a cabinet forming a chamber with a top portion and a bottom portion; the cabinet defining a plurality of sheet slots, for passage of a substrate through the chamber in a process direction; a lamp mount, suitable for holding one or more lamps, slidably disposed relative to the cabinet, whereby the lamp mount may be at least partially removed from the chamber for access to at least one lamp; the cabinet defining a first air opening and a second air opening, suitable for permitting a first airflow through the top portion of the chamber, the first airflow passing over the lamp mount, transverse to the process direction; and the cabinet defining a third air opening and a fourth air opening, suitable for permitting a second airflow through the bottom portion of the chamber, the first airflow passing under the lamp mount. 9. The printing apparatus of claim 8, wherein the first dryer module and the second dryer module are interchangeable in position within the printing apparatus. 10. The printing apparatus of claim 8, wherein the first dryer module and the second dryer module are disposed in series within the printing apparatus, so that a sheet may pass through the first dryer module and then immediately through the second dryer module. 11. The printing apparatus of claim 10, operable whereby the first dryer module is energized to perform drying and the second dryer module is turned off. 12. The printing apparatus of claim 8, further comprising at least one blower, the blower drawing the first airflow from the top portion of the chamber of at least one dryer module and directing the airflow into the bottom portion of the chamber of the at least one dryer module. 13. A printing apparatus comprising a first dryer module and a second dryer module, each dryer module including
(a) a cabinet defining a plurality of sheet slots, for passage of a substrate through the chamber in a process direction, and (b) a lamp mount, suitable for holding one or more lamps; and wherein the first dryer module and the second dryer module are interchangeable in position within the printing apparatus. 14. The printing apparatus of claim 13, wherein the first dryer module and the second dryer module are disposed in series within the printing apparatus, so that a sheet may pass through the first dryer module and then immediately through the second dryer module. 15. The printing apparatus of claim 14, operable whereby the first dryer module is energized to perform drying and the second dryer module is turned off. 16. The printing apparatus of claim 13, further comprising at least one blower, the blower drawing airflow through at least one dryer module. | 2,800 |
11,918 | 11,918 | 15,629,610 | 2,872 | A process for creating wiring on a curved surface, such as the surface of a contact lens, includes the following. Creating a groove or trench in the curved surface. Forming a seed layer on the surface and on the groove. Removing the seed layer from the surface while leaving some or all of it in the groove. Depositing conductive material in the groove. Preferably, the deposited conductive material is thicker than the seed layer. | 1. A method for creating conductive traces on a curved surface of a contact lens, the method comprising:
creating a groove in a curved surface of a contact lens material; forming a seed layer on the curved surface and on the groove; removing the seed layer from the curved surface, and leaving some seed layer within the groove; and depositing a conductive material onto the seed layer in the groove. 2. The method of claim 1 where the deposited conductive material has a thickness that is greater than a thickness of the seed layer. 3. The method of claim 1 where the seed layer comprises two or more different materials. 4. The method of claim 1 where the seed layer and the deposited conductive material are made from a same material. 5. The method of claim 1 further comprising: after depositing the conductive material onto the seed layer, finishing the contact lens material into a contact lens. 6. The method of claim 1 where the conductive material is deposited by plating a conductive material onto the seed layer in the groove. 7. The method of claim 6 where the seed layer comprises at least one of chrome and copper, and the conductive material comprises at least one of copper, nickel and gold. 8. The method of claim 1 where the groove is created by one of milling and lathing. 9. The method of claim 1 where the groove is created by laser machining. 10. The method of claim 1 where the seed layer is formed by one of vacuum evaporation and vacuum sputtering. 11. The method of claim 1 where the seed layer is removed by one of diamond turning or polishing. 12. The method of claim 1 where removing the seed layer from the curved surface leaves the curved surface optically smooth. 13. A device comprising:
a contact lens having a curved surface, with a groove created in the curved surface; a seed layer formed on a bottom of the groove and a conductive material deposited onto the seed layer in the groove, the deposited conductive material having a thickness that is greater than a thickness of the seed layer. 14. The device of claim 13 further comprising electronics mounted on or in the contact lens, where the deposited conductive material connects to the electronics. 15. The device of claim 14 where the deposited conductive material forms a coil that wirelessly receives power for the electronics. 16. The device of claim 15 where the coil contains between 1 and 30 turns. 17. The device of claim 14 where the deposited conductive material forms an antenna for wireless communication with electronics. 18. The device of claim 14 where the deposited conductive material forms electrical interconnects for the electronics. 19. The device of claim 14 where the electronics include display electronics for projecting images onto a user's retina. 20. The device of claim 13 where the deposited conductive material extends beyond the curved surface of the contact lens. 21. The device of claim 13 where the contact lens is a scleral contact lens. | A process for creating wiring on a curved surface, such as the surface of a contact lens, includes the following. Creating a groove or trench in the curved surface. Forming a seed layer on the surface and on the groove. Removing the seed layer from the surface while leaving some or all of it in the groove. Depositing conductive material in the groove. Preferably, the deposited conductive material is thicker than the seed layer.1. A method for creating conductive traces on a curved surface of a contact lens, the method comprising:
creating a groove in a curved surface of a contact lens material; forming a seed layer on the curved surface and on the groove; removing the seed layer from the curved surface, and leaving some seed layer within the groove; and depositing a conductive material onto the seed layer in the groove. 2. The method of claim 1 where the deposited conductive material has a thickness that is greater than a thickness of the seed layer. 3. The method of claim 1 where the seed layer comprises two or more different materials. 4. The method of claim 1 where the seed layer and the deposited conductive material are made from a same material. 5. The method of claim 1 further comprising: after depositing the conductive material onto the seed layer, finishing the contact lens material into a contact lens. 6. The method of claim 1 where the conductive material is deposited by plating a conductive material onto the seed layer in the groove. 7. The method of claim 6 where the seed layer comprises at least one of chrome and copper, and the conductive material comprises at least one of copper, nickel and gold. 8. The method of claim 1 where the groove is created by one of milling and lathing. 9. The method of claim 1 where the groove is created by laser machining. 10. The method of claim 1 where the seed layer is formed by one of vacuum evaporation and vacuum sputtering. 11. The method of claim 1 where the seed layer is removed by one of diamond turning or polishing. 12. The method of claim 1 where removing the seed layer from the curved surface leaves the curved surface optically smooth. 13. A device comprising:
a contact lens having a curved surface, with a groove created in the curved surface; a seed layer formed on a bottom of the groove and a conductive material deposited onto the seed layer in the groove, the deposited conductive material having a thickness that is greater than a thickness of the seed layer. 14. The device of claim 13 further comprising electronics mounted on or in the contact lens, where the deposited conductive material connects to the electronics. 15. The device of claim 14 where the deposited conductive material forms a coil that wirelessly receives power for the electronics. 16. The device of claim 15 where the coil contains between 1 and 30 turns. 17. The device of claim 14 where the deposited conductive material forms an antenna for wireless communication with electronics. 18. The device of claim 14 where the deposited conductive material forms electrical interconnects for the electronics. 19. The device of claim 14 where the electronics include display electronics for projecting images onto a user's retina. 20. The device of claim 13 where the deposited conductive material extends beyond the curved surface of the contact lens. 21. The device of claim 13 where the contact lens is a scleral contact lens. | 2,800 |
11,919 | 11,919 | 15,945,489 | 2,848 | A method and device are provided. The device includes a system component that has a circuit board that includes a cable connection portion. The cable connection portion is disposed on and extends along a mounting surface, and includes board pads disposed on the mounting surface within the cable connection portion. The board pads define corresponding board contact surfaces for electrical coupling with connector pads, and include a board adhesive material disposed on the corresponding board contact surfaces. | 1. A system for surface mounting cable connections comprising:
one or more cables having a planar connector end, the planar connector end having a connector surface, the connector surface having connector pads disposed thereon, the connector pads in electrical communication with cable traces, the connector pads including a connector adhesive material disposed thereon, the connector pads arranged in an array of connector pads; and one or more system components operatively coupled via the one or more cables, the one or more system components each having a circuit board comprising:
a cable connection portion disposed on and extending along a mounting surface for coupling with the planar connector end of the cable, the cable connection portion including board pads disposed on the mounting surface within the cable connection portion, the board pads defining corresponding board contact surfaces for electrical coupling with the connector pads of the planar connector end of one of the one or more cables, the board pads arranged in an array of board pads that matches the array of connector pads for individual coupling of each connector pad with a corresponding board pad, the board pads including a board adhesive material disposed on the corresponding board contact surfaces, wherein the planar connector end of the one of the one or more cables and the cable connection portion of the circuit board define a connection plane when the connector pads are coupled to the board pads, wherein an open gap is defined between adjacent connector pads when the connector pads are coupled to the board pads. 2. The system of claim 1, wherein the board adhesive material comprises a first portion of an epoxy and the connector adhesive material comprises a second portion of the epoxy, the first portion of the epoxy cooperating with the second portion of the epoxy when the board pads and connector pads are brought into contact with each other. 3. The system of claim 1, wherein the cable connection portion of the circuit board comprises a non-conductive board adhesive portion and the planar connector end comprises a non-conductive cable adhesive portion disposed on the connector surface, the non-conductive board adhesive portion and the non-conductive cable adhesive portion cooperating with each other to secure the planar connector end to the cable connection portion of the circuit board. 4. The system of claim 1, wherein the circuit board comprises a board adhesive covering sheet removable from the cable connection portion before electrical coupling with the one or more cables, and wherein the one or more cables comprises a cable adhesive covering sheet removable from the planar connector end before electrical coupling with the circuit board. 5. The system of claim 1, wherein the circuit board comprises a board guide feature disposed within the cable connection portion, and wherein the one or more cables comprises a cable guide feature disposed on the planar connector end, the board guide feature and cable guide feature cooperating to align the board pads with the connector pads. 6. The system of claim 5, wherein the board guide feature comprises a post extending from the mounting surface of the circuit board, and the cable guide feature comprises an opening that accepts the post. 7. The system of claim 6, wherein the one or more cables comprises a flat cable portion extending from the planar connector end. 8. The system of claim 7, wherein the planar connector end has an end width and the flat cable portion has a cable width, wherein the end width is greater than the cable width. 9. A system component having a circuit board comprising:
a cable connection portion disposed on and extending along a mounting surface, the cable connection portion including board pads disposed on the mounting surface within the cable connection portion, the board pads defining corresponding board contact surfaces for electrical coupling with connector pads, the board pads including a board adhesive material disposed on the corresponding board contact surfaces. 10. The circuit board of claim 9, wherein the board adhesive material comprises a first portion of an epoxy, the first portion of the epoxy cooperating with a second portion of the epoxy disposed on the connector pads when the connector pads and board pads are coupled. 11. The circuit board of claim 9, wherein the cable connection portion comprises a non-conductive board adhesive portion, the non-conductive board adhesive portion having a non-conductive adhesive material disposed thereon. 12. The circuit board of claim 9, further comprising a board adhesive covering sheet, the board adhesive covering sheet removable from the cable connection portion before electrical coupling with the at least one connector. 13. The circuit board of claim 9, further comprising a board guide feature disposed within the cable connection portion, the board guide feature for aligning the board pads with the connector pads. 14. The circuit board of claim 13, wherein the board guide feature comprises a post extending from the mounting surface of the circuit board. 15. A method comprising:
providing one or more cables having a planar connector end, the planar connector end having a connector surface, the connector surface having connector pads disposed thereon, the connector pads in electrical communication with cable traces, the connector pads including a connector adhesive material disposed thereon; and providing one or more system components, each of the one or more system components having a circuit board that comprises:
a cable connection portion disposed on and extending along a mounting surface for coupling with the planar connector end of the cable, the cable connection portion including board pads disposed on the mounting surface within the cable connection portion, the board pads defining corresponding board contact surfaces for electrical coupling with the connector pads of the planar connector end of one of the one or more cables, the board pads including a board adhesive material disposed on the corresponding board contact surfaces,
positioning the planar connector end with the connector surface oriented toward the mounting side of the circuit board; aligning the connector pads of the planar connector end with the board pads of the circuit board; adhering the connector pads of the planar connector end with the board pads of the circuit board, wherein the planar connector end of the one of the one or more cables and the cable connection portion of the circuit board define a connection plane when the connector pads are coupled to the board pads. 16. The method of claim 15, wherein the board adhesive material comprises a first portion of an epoxy and the connector adhesive material comprises a second portion of the epoxy, the first portion of the epoxy cooperating with the second portion of the epoxy, the method further comprising contacting the connector pads with the board pads to activate the epoxy. 17. The method of claim 15, wherein the cable connection portion of the circuit board comprises a non-conductive board adhesive portion and the planar connector end comprises a non-conductive cable adhesive portion disposed on the connector surface, the method further comprising adhering the non-conductive board adhesive portion and the non-conductive cable adhesive portion together. 18. The method of claim 15, further comprising removing a board adhesive covering sheet from the cable connection portion before electrical coupling with one of the one or more cables, and removing a cable adhesive covering sheet from the planar connector end before electrical coupling with the circuit board. 19. The method of claim 15, further comprising using a board guide feature disposed within the cable connection portion, and a cable guide feature disposed on the planar connector end, to align the board pads with the connector pads. 20. The method of claim 19, wherein the board guide feature comprises a post extending from the mounting surface of the circuit board, and the cable guide feature comprises an opening that accepts the post. | A method and device are provided. The device includes a system component that has a circuit board that includes a cable connection portion. The cable connection portion is disposed on and extends along a mounting surface, and includes board pads disposed on the mounting surface within the cable connection portion. The board pads define corresponding board contact surfaces for electrical coupling with connector pads, and include a board adhesive material disposed on the corresponding board contact surfaces.1. A system for surface mounting cable connections comprising:
one or more cables having a planar connector end, the planar connector end having a connector surface, the connector surface having connector pads disposed thereon, the connector pads in electrical communication with cable traces, the connector pads including a connector adhesive material disposed thereon, the connector pads arranged in an array of connector pads; and one or more system components operatively coupled via the one or more cables, the one or more system components each having a circuit board comprising:
a cable connection portion disposed on and extending along a mounting surface for coupling with the planar connector end of the cable, the cable connection portion including board pads disposed on the mounting surface within the cable connection portion, the board pads defining corresponding board contact surfaces for electrical coupling with the connector pads of the planar connector end of one of the one or more cables, the board pads arranged in an array of board pads that matches the array of connector pads for individual coupling of each connector pad with a corresponding board pad, the board pads including a board adhesive material disposed on the corresponding board contact surfaces, wherein the planar connector end of the one of the one or more cables and the cable connection portion of the circuit board define a connection plane when the connector pads are coupled to the board pads, wherein an open gap is defined between adjacent connector pads when the connector pads are coupled to the board pads. 2. The system of claim 1, wherein the board adhesive material comprises a first portion of an epoxy and the connector adhesive material comprises a second portion of the epoxy, the first portion of the epoxy cooperating with the second portion of the epoxy when the board pads and connector pads are brought into contact with each other. 3. The system of claim 1, wherein the cable connection portion of the circuit board comprises a non-conductive board adhesive portion and the planar connector end comprises a non-conductive cable adhesive portion disposed on the connector surface, the non-conductive board adhesive portion and the non-conductive cable adhesive portion cooperating with each other to secure the planar connector end to the cable connection portion of the circuit board. 4. The system of claim 1, wherein the circuit board comprises a board adhesive covering sheet removable from the cable connection portion before electrical coupling with the one or more cables, and wherein the one or more cables comprises a cable adhesive covering sheet removable from the planar connector end before electrical coupling with the circuit board. 5. The system of claim 1, wherein the circuit board comprises a board guide feature disposed within the cable connection portion, and wherein the one or more cables comprises a cable guide feature disposed on the planar connector end, the board guide feature and cable guide feature cooperating to align the board pads with the connector pads. 6. The system of claim 5, wherein the board guide feature comprises a post extending from the mounting surface of the circuit board, and the cable guide feature comprises an opening that accepts the post. 7. The system of claim 6, wherein the one or more cables comprises a flat cable portion extending from the planar connector end. 8. The system of claim 7, wherein the planar connector end has an end width and the flat cable portion has a cable width, wherein the end width is greater than the cable width. 9. A system component having a circuit board comprising:
a cable connection portion disposed on and extending along a mounting surface, the cable connection portion including board pads disposed on the mounting surface within the cable connection portion, the board pads defining corresponding board contact surfaces for electrical coupling with connector pads, the board pads including a board adhesive material disposed on the corresponding board contact surfaces. 10. The circuit board of claim 9, wherein the board adhesive material comprises a first portion of an epoxy, the first portion of the epoxy cooperating with a second portion of the epoxy disposed on the connector pads when the connector pads and board pads are coupled. 11. The circuit board of claim 9, wherein the cable connection portion comprises a non-conductive board adhesive portion, the non-conductive board adhesive portion having a non-conductive adhesive material disposed thereon. 12. The circuit board of claim 9, further comprising a board adhesive covering sheet, the board adhesive covering sheet removable from the cable connection portion before electrical coupling with the at least one connector. 13. The circuit board of claim 9, further comprising a board guide feature disposed within the cable connection portion, the board guide feature for aligning the board pads with the connector pads. 14. The circuit board of claim 13, wherein the board guide feature comprises a post extending from the mounting surface of the circuit board. 15. A method comprising:
providing one or more cables having a planar connector end, the planar connector end having a connector surface, the connector surface having connector pads disposed thereon, the connector pads in electrical communication with cable traces, the connector pads including a connector adhesive material disposed thereon; and providing one or more system components, each of the one or more system components having a circuit board that comprises:
a cable connection portion disposed on and extending along a mounting surface for coupling with the planar connector end of the cable, the cable connection portion including board pads disposed on the mounting surface within the cable connection portion, the board pads defining corresponding board contact surfaces for electrical coupling with the connector pads of the planar connector end of one of the one or more cables, the board pads including a board adhesive material disposed on the corresponding board contact surfaces,
positioning the planar connector end with the connector surface oriented toward the mounting side of the circuit board; aligning the connector pads of the planar connector end with the board pads of the circuit board; adhering the connector pads of the planar connector end with the board pads of the circuit board, wherein the planar connector end of the one of the one or more cables and the cable connection portion of the circuit board define a connection plane when the connector pads are coupled to the board pads. 16. The method of claim 15, wherein the board adhesive material comprises a first portion of an epoxy and the connector adhesive material comprises a second portion of the epoxy, the first portion of the epoxy cooperating with the second portion of the epoxy, the method further comprising contacting the connector pads with the board pads to activate the epoxy. 17. The method of claim 15, wherein the cable connection portion of the circuit board comprises a non-conductive board adhesive portion and the planar connector end comprises a non-conductive cable adhesive portion disposed on the connector surface, the method further comprising adhering the non-conductive board adhesive portion and the non-conductive cable adhesive portion together. 18. The method of claim 15, further comprising removing a board adhesive covering sheet from the cable connection portion before electrical coupling with one of the one or more cables, and removing a cable adhesive covering sheet from the planar connector end before electrical coupling with the circuit board. 19. The method of claim 15, further comprising using a board guide feature disposed within the cable connection portion, and a cable guide feature disposed on the planar connector end, to align the board pads with the connector pads. 20. The method of claim 19, wherein the board guide feature comprises a post extending from the mounting surface of the circuit board, and the cable guide feature comprises an opening that accepts the post. | 2,800 |
11,920 | 11,920 | 15,634,952 | 2,841 | An apparatus can include a processor; memory accessible by the processor; a first housing that includes a first display operatively coupled to the processor; a second display operatively coupled to the processor and operatively coupled to a mechanism that rotates the second display with respect to the first display; a second housing that includes a keyboard; and a hinge assembly that operatively couples the first housing to the second housing. | 1. An apparatus comprising:
a processor; memory accessible by the processor; a first housing that comprises a first display operatively coupled to the processor; a second display operatively coupled to the processor and operatively coupled to a mechanism that rotates the second display with respect to the first display; a second housing that comprises a keyboard; and a hinge assembly that operatively couples the first housing to the second housing. 2. The apparatus of claim 1 wherein a display area of the first display is greater than a display area of the second display. 3. The apparatus of claim 1 wherein the mechanism rotates the second display about an axis. 4. The apparatus of claim 3 wherein the mechanism rotates the second display about the axis to a maximum angle with respect to the first display that is greater than approximately 90 degrees with respect to the second housing. 5. The apparatus of claim 3 wherein the mechanism comprises axles that define the axis. 6. The apparatus of claim 1 wherein the mechanism comprises a biasing element that applies a biasing force to the second display that rotates the second display. 7. The apparatus of claim 6 wherein the biasing element comprises a torsion spring. 8. The apparatus of claim 1 wherein the second display comprises a co-planar orientation with respect to the first display and a plurality of non-co-planar, rotated orientations with respect to the first display. 9. The apparatus of claim 1 wherein the second display comprises a co-planar orientation with respect to the first display wherein a display surface of the first display and a display surface of the second display face opposite directions. 10. The apparatus of claim 1 comprising a closed orientation wherein the first display faces the keyboard and wherein the second display faces away from the keyboard. 11. The apparatus of claim 1 comprising an open orientation wherein the first display forms a first angle with respect to the keyboard and wherein the second display forms a second, different angle with respect to the keyboard. 12. The apparatus of claim 11 wherein the second, different angle is greater than the first angle. 13. The apparatus of claim 1 wherein the second display comprises an edge that forms a contact with the second housing. 14. The apparatus of claim 13 wherein the contact determines an angle of the second display with respect to the second housing. 15. The apparatus of claim 1 wherein the mechanism comprises a biasing element that applies force to the second display and wherein the second display applies at least a portion of the force to the second housing. 16. The apparatus of claim 1 wherein the first housing comprises an opening and wherein, in a closed orientation of the first housing and the second housing, the second display is disposed in the opening. 17. A method comprising:
for an apparatus that comprises a first housing that comprises a first display, a second display operatively coupled to a mechanism that rotates the second display with respect to the first display, a second housing that comprises a keyboard, and a hinge assembly that operatively couples the first housing to the second housing, in a rotated, non-co-planar orientation of the first display and the second display, applying force to the second housing via the second display. 18. The method of claim 17 comprising, in a co-planar orientation of the first display and the second display, applying force to the second housing via the second display. 19. The method of claim 17 wherein the mechanism comprises a biasing element that biases the second display against the second housing. 20. A method comprising:
for an apparatus that comprises a first housing that comprises a first display, a second display operatively coupled to a mechanism that rotates the second display with respect to the first display, a second housing that comprises a keyboard, and a hinge assembly that operatively couples the first housing to the second housing, transitioning the first housing and the second housing from a closed orientation wherein the first display faces the keyboard to an open orientation that forms an angle between the first housing and the second housing and, responsive to the transitioning, rotating the second display from a first viewable orientation associated with the closed orientation of the first housing and the second housing to a second viewable orientation associated with the open orientation that form the angle between the first housing and the second housing. | An apparatus can include a processor; memory accessible by the processor; a first housing that includes a first display operatively coupled to the processor; a second display operatively coupled to the processor and operatively coupled to a mechanism that rotates the second display with respect to the first display; a second housing that includes a keyboard; and a hinge assembly that operatively couples the first housing to the second housing.1. An apparatus comprising:
a processor; memory accessible by the processor; a first housing that comprises a first display operatively coupled to the processor; a second display operatively coupled to the processor and operatively coupled to a mechanism that rotates the second display with respect to the first display; a second housing that comprises a keyboard; and a hinge assembly that operatively couples the first housing to the second housing. 2. The apparatus of claim 1 wherein a display area of the first display is greater than a display area of the second display. 3. The apparatus of claim 1 wherein the mechanism rotates the second display about an axis. 4. The apparatus of claim 3 wherein the mechanism rotates the second display about the axis to a maximum angle with respect to the first display that is greater than approximately 90 degrees with respect to the second housing. 5. The apparatus of claim 3 wherein the mechanism comprises axles that define the axis. 6. The apparatus of claim 1 wherein the mechanism comprises a biasing element that applies a biasing force to the second display that rotates the second display. 7. The apparatus of claim 6 wherein the biasing element comprises a torsion spring. 8. The apparatus of claim 1 wherein the second display comprises a co-planar orientation with respect to the first display and a plurality of non-co-planar, rotated orientations with respect to the first display. 9. The apparatus of claim 1 wherein the second display comprises a co-planar orientation with respect to the first display wherein a display surface of the first display and a display surface of the second display face opposite directions. 10. The apparatus of claim 1 comprising a closed orientation wherein the first display faces the keyboard and wherein the second display faces away from the keyboard. 11. The apparatus of claim 1 comprising an open orientation wherein the first display forms a first angle with respect to the keyboard and wherein the second display forms a second, different angle with respect to the keyboard. 12. The apparatus of claim 11 wherein the second, different angle is greater than the first angle. 13. The apparatus of claim 1 wherein the second display comprises an edge that forms a contact with the second housing. 14. The apparatus of claim 13 wherein the contact determines an angle of the second display with respect to the second housing. 15. The apparatus of claim 1 wherein the mechanism comprises a biasing element that applies force to the second display and wherein the second display applies at least a portion of the force to the second housing. 16. The apparatus of claim 1 wherein the first housing comprises an opening and wherein, in a closed orientation of the first housing and the second housing, the second display is disposed in the opening. 17. A method comprising:
for an apparatus that comprises a first housing that comprises a first display, a second display operatively coupled to a mechanism that rotates the second display with respect to the first display, a second housing that comprises a keyboard, and a hinge assembly that operatively couples the first housing to the second housing, in a rotated, non-co-planar orientation of the first display and the second display, applying force to the second housing via the second display. 18. The method of claim 17 comprising, in a co-planar orientation of the first display and the second display, applying force to the second housing via the second display. 19. The method of claim 17 wherein the mechanism comprises a biasing element that biases the second display against the second housing. 20. A method comprising:
for an apparatus that comprises a first housing that comprises a first display, a second display operatively coupled to a mechanism that rotates the second display with respect to the first display, a second housing that comprises a keyboard, and a hinge assembly that operatively couples the first housing to the second housing, transitioning the first housing and the second housing from a closed orientation wherein the first display faces the keyboard to an open orientation that forms an angle between the first housing and the second housing and, responsive to the transitioning, rotating the second display from a first viewable orientation associated with the closed orientation of the first housing and the second housing to a second viewable orientation associated with the open orientation that form the angle between the first housing and the second housing. | 2,800 |
11,921 | 11,921 | 15,593,486 | 2,881 | Compositions, methods, and apparatus are described for carrying out nitrogen ion implantation, which avoid the incidence of severe glitching when the nitrogen ion implantation is followed by another ion implantation operation susceptible to glitching, e.g., implantation of arsenic and/or phosphorus ionic species. The nitrogen ion implantation operation is advantageously conducted with a nitrogen ion implantation composition introduced to or formed in the ion source chamber of the ion implantation system, wherein the nitrogen ion implantation composition includes nitrogen (N 2 ) dopant gas and a glitching-suppressing gas including one or more selected from the group consisting of NF 3 , N 2 F 4 , F 2 , SiF4, WF 6 , PF 3 , PF 5 , AsF 3 , AsF 5 , CF 4 and other fluorinated hydrocarbons of C x F y (x≧1, y≧1) general formula, SF 6 , HF, COF 2 , OF 2 , BF 3 , B 2 F 4 , GeF 4 , XeF 2 , O 2 , N 2 O, NO, NO 2 , N 2 O 4 , and O 3 , and optionally hydrogen-containing gas, e.g., hydrogen-containing gas including one or more selected from the group consisting of H 2 , NH 3 , N 2 H 4 , B 2 H 6 , AsH 3 , PH 3 , SiH 4 , Si 2 H 6 , H 2 S, H 2 Se, CH 4 and other hydrocarbons of C x H y (x≧1, y≧1) general formula and GeH 4 . | 1. A nitrogen ion implantation composition for combating glitching in an ion implantation system when nitrogen ion implantation is followed by another ion implantation operation susceptible to glitching when following the nitrogen ion implantation, the nitrogen ion implantation composition comprising nitrogen (N2) dopant gas and a glitching-suppressing gas comprising one or more selected from the group consisting of NF3, N2F4, F2, SiF4, WF6, PF3, PF5, AsF3, AsF5, CF4 and other fluorinated hydrocarbons of CxFy (x≧1, y≧1) general formula, SF6, HF, COF2, OF2, BF3, B2F4, GeF4, XeF2, O2, N2O, NO, NO2, N2O4, and O3, and optionally hydrogen-containing gas. 2. The nitrogen ion implantation composition according to claim 1, wherein the optional hydrogen-containing gas comprises one or more selected from the group consisting of H2, NH3, N2H4, B2H6, AsH3, PH3, SiH4, Si2H6, H2S, H2Se, CH4 and other hydrocarbons of CxHy (x≧1, y≧1) general formula and GeH4. 3. The nitrogen ion implantation composition according to claim 1, wherein the nitrogen (N2) dopant gas constitutes greater than 50 volume percent (vol. %) of the nitrogen ion implantation composition. 4. The nitrogen ion implantation composition according claim 1, wherein the glitching-suppressing gas is present in an amount of from 1 vol. % to 49 vol. % of the nitrogen ion implantation composition. 5. The nitrogen ion implantation composition according to claim 1, wherein the glitching-suppressing gas is present in an amount of from 5 vol. % to 45 vol. % of the nitrogen ion implantation composition. 6. The nitrogen ion implantation composition according to claim 1, wherein the glitching-suppressing gas is present in an amount in a range whose lower endpoint vol. % value is any of 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 18, 20, 22, 25, 28, 30, 32, 34, 35, 37, 38, 40, and whose upper endpoint vol. % value is greater than the lower endpoint value and is any of 4, 5, 6, 8, 10, 12, 15, 18, 20, 22, 25, 28, 30, 32, 34, 35, 37, 38, 40, 42, 44, 45, 47, 48, and 49. 7. The nitrogen ion implantation composition according to claim 1, wherein the glitching-suppressing gas comprises one or more selected from the group consisting of NF3, N2F4, F2, SiF4, WF6, PF3, PF5, AsF3, AsF5, CF4 and other fluorinated hydrocarbons of CxFy (x≧1, y≧1) general formula, SF6, HF, COF2, OF2, BF3, B2F4, GeF4, and XeF2. 8. The nitrogen ion implantation composition according to claim 1, wherein the glitching-suppressing gas comprises NF3. 9. The nitrogen ion implantation composition according to claim 1, wherein the glitching-suppressing gas comprises oxic gas. 10. The nitrogen ion implantation composition according to claim 9, wherein the oxic gas comprises at least one selected from the group consisting of COF2, OF2, O2, N2O, NO, NO2, N2O4, and O3. 11. The nitrogen ion implantation composition according to claim 9, wherein the oxic gas comprises O2. 12. A gas supply package for supplying a nitrogen ion implantation composition to an ion implantation system, in which the gas supply package comprises a gas storage and dispensing vessel containing the nitrogen ion implantation composition according to claim 1. 13. A method of supplying gas for nitrogen ion implantation, comprising delivering such gas to an ion implantation system in a packaged form comprising at least one of:
(i) a gas supply package comprising a gas storage and dispensing vessel containing a nitrogen ion implantation composition comprising nitrogen (N2) dopant gas and a glitching-suppressing gas comprising one or more selected from the group consisting of NF3, N2F4, F2, SiF4, WF6, PF3, PF5, AsF3, AsF5, CF4 and other fluorinated hydrocarbons of CxFy (x≧1, y≧1) general formula, SF6, HF, COF2, OF2, BF3, B2F4, GeF4, XeF2, O2, N2O, NO, NO2, N2O4, and O3, and optionally hydrogen-containing gas, as a packaged gas mixture; and (ii) a gas supply kit for supplying a nitrogen ion implantation composition to an ion implantation system, in which the gas supply kit comprises a first gas storage and dispensing vessel containing nitrogen (N2) dopant gas, and a second gas storage and dispensing vessel containing a glitching-suppressing gas comprising one or more selected from the group consisting of NF3, N2F4, F2, SiF4, WF6, PF3, PF5, AsF3, AsF5, CF4 and other fluorinated hydrocarbons of CxFy (x≧1, y≧1) general formula, SF6, HF, COF2, OF2, BF3, B2F4, GeF4, XeF2, O2, N2O, NO, NO2, N2O4, and O3, optionally wherein the gas supply kit further comprises hydrogen-containing gas in a third gas storage and dispensing vessel, or in one or more of the first and second gas storage and dispensing vessels. 14. The method of claim 13, wherein the hydrogen-containing gas in the gas supply package (i) comprises one or more selected from the group consisting of H2, NH3, N2H4, B2H6, AsH3, PH3, SiH4, Si2H6, H2S, H2Se, CH4 and other hydrocarbons of CxHy (x≧1, y≧1) general formula and GeH4. 15. The method of claim 13, wherein the hydrogen-containing gas in the gas supply kit (ii) comprises one or more selected from the group consisting of H2, NH3, N2H4, B2H6, AsH3, PH3, SiH4, Si2H6, H2S, H2Se, CH4 and other hydrocarbons of CxHy (x≧1, y≧1) general formula and GeH4. 16. A packaged gas mixture comprises a gas storage and dispensing vessel containing the nitrogen gas mixture comprising nitrogen (N2) dopant gas and a glitching-suppressing gas comprising one or more selected from the group consisting of NF3, N2F4, F2, SiF4, WF6, PF3, PF5, AsF3, AsF5, CF4 and other fluorinated hydrocarbons of CxFy (x≧1, y≧1) general formula, SF6, HF, COF2, OF2, BF3, B2F4, GeF4, XeF2, O2, N2O, NO, NO2, N2O4, and O3, and optionally hydrogen-containing gas. 17. The packaged gas mixture according to claim 16, wherein the optional hydrogen-containing gas comprises one or more selected from the group consisting of H2, NH3, N2H4, B2H6, AsH3, PH3, SiH4, Si2H6, H2S, H2Se, CH4 and other hydrocarbons of CxHy (x≧1, y≧1) general formula and GeH4. 18. The packaged gas mixture according to claim 16, wherein the nitrogen (N2) dopant gas constitutes greater than 50 volume percent (vol. %) of the nitrogen ion implantation composition. 19. The packaged gas mixture according to claim 16, wherein the glitching-suppressing gas is present in an amount of from 1 vol. % to 49 vol. % of the nitrogen ion implantation composition. 20. The packaged gas mixture according to claim 16, wherein the glitching-suppressing gas is present in an amount of from 5 vol. % to 45 vol. % of the nitrogen ion implantation composition | Compositions, methods, and apparatus are described for carrying out nitrogen ion implantation, which avoid the incidence of severe glitching when the nitrogen ion implantation is followed by another ion implantation operation susceptible to glitching, e.g., implantation of arsenic and/or phosphorus ionic species. The nitrogen ion implantation operation is advantageously conducted with a nitrogen ion implantation composition introduced to or formed in the ion source chamber of the ion implantation system, wherein the nitrogen ion implantation composition includes nitrogen (N 2 ) dopant gas and a glitching-suppressing gas including one or more selected from the group consisting of NF 3 , N 2 F 4 , F 2 , SiF4, WF 6 , PF 3 , PF 5 , AsF 3 , AsF 5 , CF 4 and other fluorinated hydrocarbons of C x F y (x≧1, y≧1) general formula, SF 6 , HF, COF 2 , OF 2 , BF 3 , B 2 F 4 , GeF 4 , XeF 2 , O 2 , N 2 O, NO, NO 2 , N 2 O 4 , and O 3 , and optionally hydrogen-containing gas, e.g., hydrogen-containing gas including one or more selected from the group consisting of H 2 , NH 3 , N 2 H 4 , B 2 H 6 , AsH 3 , PH 3 , SiH 4 , Si 2 H 6 , H 2 S, H 2 Se, CH 4 and other hydrocarbons of C x H y (x≧1, y≧1) general formula and GeH 4 .1. A nitrogen ion implantation composition for combating glitching in an ion implantation system when nitrogen ion implantation is followed by another ion implantation operation susceptible to glitching when following the nitrogen ion implantation, the nitrogen ion implantation composition comprising nitrogen (N2) dopant gas and a glitching-suppressing gas comprising one or more selected from the group consisting of NF3, N2F4, F2, SiF4, WF6, PF3, PF5, AsF3, AsF5, CF4 and other fluorinated hydrocarbons of CxFy (x≧1, y≧1) general formula, SF6, HF, COF2, OF2, BF3, B2F4, GeF4, XeF2, O2, N2O, NO, NO2, N2O4, and O3, and optionally hydrogen-containing gas. 2. The nitrogen ion implantation composition according to claim 1, wherein the optional hydrogen-containing gas comprises one or more selected from the group consisting of H2, NH3, N2H4, B2H6, AsH3, PH3, SiH4, Si2H6, H2S, H2Se, CH4 and other hydrocarbons of CxHy (x≧1, y≧1) general formula and GeH4. 3. The nitrogen ion implantation composition according to claim 1, wherein the nitrogen (N2) dopant gas constitutes greater than 50 volume percent (vol. %) of the nitrogen ion implantation composition. 4. The nitrogen ion implantation composition according claim 1, wherein the glitching-suppressing gas is present in an amount of from 1 vol. % to 49 vol. % of the nitrogen ion implantation composition. 5. The nitrogen ion implantation composition according to claim 1, wherein the glitching-suppressing gas is present in an amount of from 5 vol. % to 45 vol. % of the nitrogen ion implantation composition. 6. The nitrogen ion implantation composition according to claim 1, wherein the glitching-suppressing gas is present in an amount in a range whose lower endpoint vol. % value is any of 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 18, 20, 22, 25, 28, 30, 32, 34, 35, 37, 38, 40, and whose upper endpoint vol. % value is greater than the lower endpoint value and is any of 4, 5, 6, 8, 10, 12, 15, 18, 20, 22, 25, 28, 30, 32, 34, 35, 37, 38, 40, 42, 44, 45, 47, 48, and 49. 7. The nitrogen ion implantation composition according to claim 1, wherein the glitching-suppressing gas comprises one or more selected from the group consisting of NF3, N2F4, F2, SiF4, WF6, PF3, PF5, AsF3, AsF5, CF4 and other fluorinated hydrocarbons of CxFy (x≧1, y≧1) general formula, SF6, HF, COF2, OF2, BF3, B2F4, GeF4, and XeF2. 8. The nitrogen ion implantation composition according to claim 1, wherein the glitching-suppressing gas comprises NF3. 9. The nitrogen ion implantation composition according to claim 1, wherein the glitching-suppressing gas comprises oxic gas. 10. The nitrogen ion implantation composition according to claim 9, wherein the oxic gas comprises at least one selected from the group consisting of COF2, OF2, O2, N2O, NO, NO2, N2O4, and O3. 11. The nitrogen ion implantation composition according to claim 9, wherein the oxic gas comprises O2. 12. A gas supply package for supplying a nitrogen ion implantation composition to an ion implantation system, in which the gas supply package comprises a gas storage and dispensing vessel containing the nitrogen ion implantation composition according to claim 1. 13. A method of supplying gas for nitrogen ion implantation, comprising delivering such gas to an ion implantation system in a packaged form comprising at least one of:
(i) a gas supply package comprising a gas storage and dispensing vessel containing a nitrogen ion implantation composition comprising nitrogen (N2) dopant gas and a glitching-suppressing gas comprising one or more selected from the group consisting of NF3, N2F4, F2, SiF4, WF6, PF3, PF5, AsF3, AsF5, CF4 and other fluorinated hydrocarbons of CxFy (x≧1, y≧1) general formula, SF6, HF, COF2, OF2, BF3, B2F4, GeF4, XeF2, O2, N2O, NO, NO2, N2O4, and O3, and optionally hydrogen-containing gas, as a packaged gas mixture; and (ii) a gas supply kit for supplying a nitrogen ion implantation composition to an ion implantation system, in which the gas supply kit comprises a first gas storage and dispensing vessel containing nitrogen (N2) dopant gas, and a second gas storage and dispensing vessel containing a glitching-suppressing gas comprising one or more selected from the group consisting of NF3, N2F4, F2, SiF4, WF6, PF3, PF5, AsF3, AsF5, CF4 and other fluorinated hydrocarbons of CxFy (x≧1, y≧1) general formula, SF6, HF, COF2, OF2, BF3, B2F4, GeF4, XeF2, O2, N2O, NO, NO2, N2O4, and O3, optionally wherein the gas supply kit further comprises hydrogen-containing gas in a third gas storage and dispensing vessel, or in one or more of the first and second gas storage and dispensing vessels. 14. The method of claim 13, wherein the hydrogen-containing gas in the gas supply package (i) comprises one or more selected from the group consisting of H2, NH3, N2H4, B2H6, AsH3, PH3, SiH4, Si2H6, H2S, H2Se, CH4 and other hydrocarbons of CxHy (x≧1, y≧1) general formula and GeH4. 15. The method of claim 13, wherein the hydrogen-containing gas in the gas supply kit (ii) comprises one or more selected from the group consisting of H2, NH3, N2H4, B2H6, AsH3, PH3, SiH4, Si2H6, H2S, H2Se, CH4 and other hydrocarbons of CxHy (x≧1, y≧1) general formula and GeH4. 16. A packaged gas mixture comprises a gas storage and dispensing vessel containing the nitrogen gas mixture comprising nitrogen (N2) dopant gas and a glitching-suppressing gas comprising one or more selected from the group consisting of NF3, N2F4, F2, SiF4, WF6, PF3, PF5, AsF3, AsF5, CF4 and other fluorinated hydrocarbons of CxFy (x≧1, y≧1) general formula, SF6, HF, COF2, OF2, BF3, B2F4, GeF4, XeF2, O2, N2O, NO, NO2, N2O4, and O3, and optionally hydrogen-containing gas. 17. The packaged gas mixture according to claim 16, wherein the optional hydrogen-containing gas comprises one or more selected from the group consisting of H2, NH3, N2H4, B2H6, AsH3, PH3, SiH4, Si2H6, H2S, H2Se, CH4 and other hydrocarbons of CxHy (x≧1, y≧1) general formula and GeH4. 18. The packaged gas mixture according to claim 16, wherein the nitrogen (N2) dopant gas constitutes greater than 50 volume percent (vol. %) of the nitrogen ion implantation composition. 19. The packaged gas mixture according to claim 16, wherein the glitching-suppressing gas is present in an amount of from 1 vol. % to 49 vol. % of the nitrogen ion implantation composition. 20. The packaged gas mixture according to claim 16, wherein the glitching-suppressing gas is present in an amount of from 5 vol. % to 45 vol. % of the nitrogen ion implantation composition | 2,800 |
11,922 | 11,922 | 14,653,990 | 2,859 | A hand-held power tool rechargeable battery is provided which includes at least one first rechargeable battery cell and at least one inductive charging unit which includes at least one inductive charging coil for charging the at least one first rechargeable battery cell. It is provided that the at least one first rechargeable battery cell has a main direction of extension which is oriented at least essentially perpendicularly with respect to a coil plane of the inductive charging unit. | 1.-17. (canceled) 18. A hand-held power tool rechargeable battery, comprising:
at least one first rechargeable battery cell; and at least one inductive charging unit that includes at least one inductive charging coil for charging the at least one first rechargeable battery cell, wherein the at least one first rechargeable battery cell has a main direction of extension that is oriented at least essentially perpendicularly with respect to a coil plane of the inductive charging unit. 19. The hand-held power tool rechargeable battery as recited in claim 18, further comprising:
at least one additional rechargeable battery cell having a main direction of extension that is oriented at least essentially in parallel to the coil plane of the inductive charging unit. 20. The hand-held power tool rechargeable battery as recited in claim 19, wherein the at least one additional rechargeable battery cell is situated between the at least one first rechargeable battery cell and the inductive charging coil. 21. The hand-held power tool rechargeable battery as recited in claim 19, wherein a diameter of the inductive charging coil is greater than a main length of extension of the at least one additional rechargeable battery cell. 22. The hand-held power tool rechargeable battery as recited in claim 18, further comprising:
a rechargeable battery housing having a coil receiving area for accommodating the inductive charging coil, the inductive charging coil at least partially forming a form-fit element. 23. The hand-held power tool rechargeable battery as recited in claim 18, wherein the inductive charging unit includes a coil core unit having a plate area that at least partially shields the at least one first rechargeable battery cell from the inductive charging coil. 24. The hand-held power tool rechargeable battery as recited in claim 23, wherein the plate area is at least essentially rectangular. 25. The hand-held power tool rechargeable battery as recited in claim 18, further comprising at least one heat distribution element for distributing waste heat. 26. The hand-held power tool rechargeable battery as recited in claim 18, wherein the inductive charging unit is a preassembled module. 27. A system, comprising:
a hand-held power tool; and a hand-held power tool rechargeable battery that includes:
at least one first rechargeable battery cell, and
at least one inductive charging unit that includes at least one inductive charging coil for charging the at least one first rechargeable battery cell, wherein the at least one first rechargeable battery cell has a main direction of extension that is oriented at least essentially perpendicularly with respect to a coil plane of the inductive charging unit. 28. The system as recited in claim 27, wherein the hand-held power tool and the hand-held power tool rechargeable battery are separable from one another without a tool. 29. The system as recited in claim 28, wherein the at least one first rechargeable battery cell is at least essentially enclosed by a handle housing in an installed state of the hand-held power tool and of the hand-held power tool rechargeable battery. 30. The system as recited in claim 27, further comprising an installation direction for installing the hand-held power tool rechargeable battery on the hand-held power tool, and which extends at least essentially perpendicularly with respect to the coil plane of the inductive charging unit. 31. A system, comprising:
an inductive charging device; and a hand-held power tool rechargeable battery that includes:
at least one first rechargeable battery cell, and
at least one inductive charging unit that includes at least one inductive charging coil for charging the at least one first rechargeable battery cell, wherein the at least one first rechargeable battery cell has a main direction of extension that is oriented at least essentially perpendicularly with respect to a coil plane of the inductive charging unit. 32. The system as recited in claim 31, wherein the inductive charging device includes form-fit elements for fastening the hand-held power tool rechargeable battery during a charging phase. 33. The system as recited in claim 31, wherein the inductive charging device and the hand-held power tool rechargeable battery include a positioning projection and a positioning recess having basic shapes which are different from one another. 34. An inductive charging unit of a hand-held power tool rechargeable battery that includes:
at least one first rechargeable battery cell, and at least one inductive charging unit that includes at least one inductive charging coil for charging the at least one first rechargeable battery cell, wherein the at least one first rechargeable battery cell has a main direction of extension that is oriented at least essentially perpendicularly with respect to a coil plane of the inductive charging unit. | A hand-held power tool rechargeable battery is provided which includes at least one first rechargeable battery cell and at least one inductive charging unit which includes at least one inductive charging coil for charging the at least one first rechargeable battery cell. It is provided that the at least one first rechargeable battery cell has a main direction of extension which is oriented at least essentially perpendicularly with respect to a coil plane of the inductive charging unit.1.-17. (canceled) 18. A hand-held power tool rechargeable battery, comprising:
at least one first rechargeable battery cell; and at least one inductive charging unit that includes at least one inductive charging coil for charging the at least one first rechargeable battery cell, wherein the at least one first rechargeable battery cell has a main direction of extension that is oriented at least essentially perpendicularly with respect to a coil plane of the inductive charging unit. 19. The hand-held power tool rechargeable battery as recited in claim 18, further comprising:
at least one additional rechargeable battery cell having a main direction of extension that is oriented at least essentially in parallel to the coil plane of the inductive charging unit. 20. The hand-held power tool rechargeable battery as recited in claim 19, wherein the at least one additional rechargeable battery cell is situated between the at least one first rechargeable battery cell and the inductive charging coil. 21. The hand-held power tool rechargeable battery as recited in claim 19, wherein a diameter of the inductive charging coil is greater than a main length of extension of the at least one additional rechargeable battery cell. 22. The hand-held power tool rechargeable battery as recited in claim 18, further comprising:
a rechargeable battery housing having a coil receiving area for accommodating the inductive charging coil, the inductive charging coil at least partially forming a form-fit element. 23. The hand-held power tool rechargeable battery as recited in claim 18, wherein the inductive charging unit includes a coil core unit having a plate area that at least partially shields the at least one first rechargeable battery cell from the inductive charging coil. 24. The hand-held power tool rechargeable battery as recited in claim 23, wherein the plate area is at least essentially rectangular. 25. The hand-held power tool rechargeable battery as recited in claim 18, further comprising at least one heat distribution element for distributing waste heat. 26. The hand-held power tool rechargeable battery as recited in claim 18, wherein the inductive charging unit is a preassembled module. 27. A system, comprising:
a hand-held power tool; and a hand-held power tool rechargeable battery that includes:
at least one first rechargeable battery cell, and
at least one inductive charging unit that includes at least one inductive charging coil for charging the at least one first rechargeable battery cell, wherein the at least one first rechargeable battery cell has a main direction of extension that is oriented at least essentially perpendicularly with respect to a coil plane of the inductive charging unit. 28. The system as recited in claim 27, wherein the hand-held power tool and the hand-held power tool rechargeable battery are separable from one another without a tool. 29. The system as recited in claim 28, wherein the at least one first rechargeable battery cell is at least essentially enclosed by a handle housing in an installed state of the hand-held power tool and of the hand-held power tool rechargeable battery. 30. The system as recited in claim 27, further comprising an installation direction for installing the hand-held power tool rechargeable battery on the hand-held power tool, and which extends at least essentially perpendicularly with respect to the coil plane of the inductive charging unit. 31. A system, comprising:
an inductive charging device; and a hand-held power tool rechargeable battery that includes:
at least one first rechargeable battery cell, and
at least one inductive charging unit that includes at least one inductive charging coil for charging the at least one first rechargeable battery cell, wherein the at least one first rechargeable battery cell has a main direction of extension that is oriented at least essentially perpendicularly with respect to a coil plane of the inductive charging unit. 32. The system as recited in claim 31, wherein the inductive charging device includes form-fit elements for fastening the hand-held power tool rechargeable battery during a charging phase. 33. The system as recited in claim 31, wherein the inductive charging device and the hand-held power tool rechargeable battery include a positioning projection and a positioning recess having basic shapes which are different from one another. 34. An inductive charging unit of a hand-held power tool rechargeable battery that includes:
at least one first rechargeable battery cell, and at least one inductive charging unit that includes at least one inductive charging coil for charging the at least one first rechargeable battery cell, wherein the at least one first rechargeable battery cell has a main direction of extension that is oriented at least essentially perpendicularly with respect to a coil plane of the inductive charging unit. | 2,800 |
11,923 | 11,923 | 15,487,226 | 2,846 | A drive circuit is provided and includes a rectification circuit, a buck converter, a first inverter, and a second inverter. The rectification circuit is configured to rectify a first AC voltage signal to generate a rectified voltage signal. The buck converter is configured to downconvert the rectified voltage signal to a DC voltage signal, wherein the DC voltage signal is supplied to a DC bus. The first inverter is configured to convert the DC voltage signal to a second AC voltage signal and supply the second AC voltage signal to a compressor motor. The second inverter is configured to convert the DC voltage signal to a third AC voltage signal and supply the third AC voltage signal to a condenser fan motor. Peak voltages of the second AC voltage signal and the third AC voltage signal are less than peak voltages of the first AC voltage signal. | 1. A drive circuit comprising:
a rectification circuit configured to rectify a first alternating current (AC) voltage signal to generate a rectified voltage signal; a buck converter configured to downconvert the rectified voltage signal to a direct current (DC) voltage signal, wherein the DC voltage signal is supplied to a DC bus; a first inverter configured to convert the DC voltage signal to a second AC voltage signal and supply the second AC voltage signal to a compressor motor; and a second inverter configured to convert the DC voltage signal to a third AC voltage signal and supply the third AC voltage signal to a condenser fan motor, wherein peak voltages of the second AC voltage signal and the third AC voltage signal are less than peak voltages of the first AC voltage signal. 2. The drive circuit of claim 1, wherein:
the buck converter comprises
a switch, and
a driver configured to transition the switch between an open state and a closed state;
a peak voltage of the DC voltage signal is based on an average voltage at an output of the switch; and the driver is configured to reduce a DC voltage of the DC voltage signal by adjusting a duty cycle of the switch. 3. The drive circuit of claim 1, further comprising an inductor connected in series between an output of the second inverter and an input of the condenser fan motor. 4. The drive circuit of claim 1, wherein a speed of the condenser fan motor is independent of a speed of the compressor motor. 5. The drive circuit of claim 1, further comprising a control module, wherein:
the buck converter comprises a switch and a driver; the driver is configured to receive a first control signal from the control module and control a state of the switch based on the first control signal; the first inverter and the second inverter are configured to receive a plurality of control signals from the driver or the control module; and the control module is separate from the driver. 6. The drive circuit of claim 5, wherein the driver is configured to receive a second control signal from the control module and provide the plurality of control signals to the first inverter and the second inverter based on the second control signal. 7. The drive circuit of claim 5, wherein the control module is configured to provide the plurality of control signals to the first inverter and the second inverter. 8. A drive circuit comprising:
a rectification circuit configured to rectify a first alternating current (AC) voltage signal to generate a rectified voltage signal; a buck converter configured to downconvert the rectified voltage signal to a first direct current (DC) voltage signal, wherein the first DC voltage signal is supplied to a DC bus; a first inverter configured to convert the first DC voltage signal to a second AC voltage signal and supply the second AC voltage signal to a compressor motor; and a condenser fan motor assembly configured to receive the first DC voltage signal and one of
convert the first DC voltage signal to a third AC voltage signal and supply the third AC voltage signal to a condenser fan motor,
pulse the first DC voltage signal and supply the pulsed first DC voltage signal to the condenser fan motor, and
convert the first DC voltage signal to a second DC voltage signal and supply a pulsed version of the second DC voltage signal to the condenser fan motor. 9. The drive circuit of claim 8, wherein:
the condenser fan motor assembly comprises a control circuit; and the control circuit is configured to convert the first DC voltage signal to the third AC voltage signal and supply the third AC voltage signal to the condenser fan motor of the condenser fan motor assembly. 10. The drive circuit of claim 8, further comprising a control module, wherein:
the buck converter comprises a switch and a driver; the driver is configured to receive a first control signal from the control module and control a state of the switch based on the first control signal; the condenser fan motor assembly comprises a controller; the controller is configured to receive a second control signal from the control module and adjust the third AC voltage signal based on the second control signal to adjust a speed of the condenser fan motor; and the control module is separate from the driver and the condenser fan motor assembly. 11. The drive circuit of claim 8, wherein:
the buck converter comprises
a switch, and
a driver configured to transition the switch between an open state and a closed state; and
a peak voltage of the DC voltage signal is based on an average voltage at an output of the switch. 12. The drive circuit of claim 8, wherein:
the buck converter comprises a switch and a driver; and the driver is configured to reduce a DC voltage of the first DC voltage signal by adjusting a duty cycle of the switch. 13. A drive circuit comprising:
a rectification circuit configured to rectify a first alternating current (AC) voltage signal to generate a rectified voltage signal; a buck converter configured to downconvert the rectified voltage signal to a direct current (DC) voltage signal, wherein the DC voltage signal is supplied to a DC bus; and a first inverter configured to convert the DC voltage signal to a second AC voltage signal and supply the second AC voltage signal to a compressor motor and to a condenser fan motor, wherein peak voltages of the second AC voltage signal are less than peak voltages of the first AC voltage signal. 14. The drive circuit of claim 13, wherein a number of poles of the condenser fan motor is greater than a number of poles of a motor of the compressor motor. 15. The drive circuit of claim 14, wherein
the condenser fan motor is an induction motor; and the motor of the compressor motor is an induction motor or a permanent magnet motor. 16. The drive circuit of claim 13, wherein a number of poles of the condenser fan motor is twice or three times the number of poles of the compressor motor. 17. The drive circuit of claim 13, wherein a speed of the condenser fan motor is based on the second AC voltage signal, such that a speed of the condenser fan motor is adjusted when a speed of the compressor motor is adjusted. 18. The drive circuit of claim 13, wherein the condenser fan motor is operated at a same stator frequency as a motor of the compressor motor. 19. The drive circuit of claim 13, wherein:
the buck converter comprises
a switch, and
a driver configured to transition the switch between an open state and a closed state;
a peak voltage of the DC voltage signal is based on an average voltage at an output of the switch; and the driver is configured to reduce a DC voltage of the DC voltage signal by adjusting a duty cycle of the switch. 20. The drive circuit of claim 13, further comprising a control module, wherein:
the buck converter comprises a switch and a driver; the driver is configured to receive a first control signal from the control module and control a state of the switch based on the first control signal; the inverter is configured to receive a plurality of control signals from the driver or the control module; and the control module is separate from the driver. | A drive circuit is provided and includes a rectification circuit, a buck converter, a first inverter, and a second inverter. The rectification circuit is configured to rectify a first AC voltage signal to generate a rectified voltage signal. The buck converter is configured to downconvert the rectified voltage signal to a DC voltage signal, wherein the DC voltage signal is supplied to a DC bus. The first inverter is configured to convert the DC voltage signal to a second AC voltage signal and supply the second AC voltage signal to a compressor motor. The second inverter is configured to convert the DC voltage signal to a third AC voltage signal and supply the third AC voltage signal to a condenser fan motor. Peak voltages of the second AC voltage signal and the third AC voltage signal are less than peak voltages of the first AC voltage signal.1. A drive circuit comprising:
a rectification circuit configured to rectify a first alternating current (AC) voltage signal to generate a rectified voltage signal; a buck converter configured to downconvert the rectified voltage signal to a direct current (DC) voltage signal, wherein the DC voltage signal is supplied to a DC bus; a first inverter configured to convert the DC voltage signal to a second AC voltage signal and supply the second AC voltage signal to a compressor motor; and a second inverter configured to convert the DC voltage signal to a third AC voltage signal and supply the third AC voltage signal to a condenser fan motor, wherein peak voltages of the second AC voltage signal and the third AC voltage signal are less than peak voltages of the first AC voltage signal. 2. The drive circuit of claim 1, wherein:
the buck converter comprises
a switch, and
a driver configured to transition the switch between an open state and a closed state;
a peak voltage of the DC voltage signal is based on an average voltage at an output of the switch; and the driver is configured to reduce a DC voltage of the DC voltage signal by adjusting a duty cycle of the switch. 3. The drive circuit of claim 1, further comprising an inductor connected in series between an output of the second inverter and an input of the condenser fan motor. 4. The drive circuit of claim 1, wherein a speed of the condenser fan motor is independent of a speed of the compressor motor. 5. The drive circuit of claim 1, further comprising a control module, wherein:
the buck converter comprises a switch and a driver; the driver is configured to receive a first control signal from the control module and control a state of the switch based on the first control signal; the first inverter and the second inverter are configured to receive a plurality of control signals from the driver or the control module; and the control module is separate from the driver. 6. The drive circuit of claim 5, wherein the driver is configured to receive a second control signal from the control module and provide the plurality of control signals to the first inverter and the second inverter based on the second control signal. 7. The drive circuit of claim 5, wherein the control module is configured to provide the plurality of control signals to the first inverter and the second inverter. 8. A drive circuit comprising:
a rectification circuit configured to rectify a first alternating current (AC) voltage signal to generate a rectified voltage signal; a buck converter configured to downconvert the rectified voltage signal to a first direct current (DC) voltage signal, wherein the first DC voltage signal is supplied to a DC bus; a first inverter configured to convert the first DC voltage signal to a second AC voltage signal and supply the second AC voltage signal to a compressor motor; and a condenser fan motor assembly configured to receive the first DC voltage signal and one of
convert the first DC voltage signal to a third AC voltage signal and supply the third AC voltage signal to a condenser fan motor,
pulse the first DC voltage signal and supply the pulsed first DC voltage signal to the condenser fan motor, and
convert the first DC voltage signal to a second DC voltage signal and supply a pulsed version of the second DC voltage signal to the condenser fan motor. 9. The drive circuit of claim 8, wherein:
the condenser fan motor assembly comprises a control circuit; and the control circuit is configured to convert the first DC voltage signal to the third AC voltage signal and supply the third AC voltage signal to the condenser fan motor of the condenser fan motor assembly. 10. The drive circuit of claim 8, further comprising a control module, wherein:
the buck converter comprises a switch and a driver; the driver is configured to receive a first control signal from the control module and control a state of the switch based on the first control signal; the condenser fan motor assembly comprises a controller; the controller is configured to receive a second control signal from the control module and adjust the third AC voltage signal based on the second control signal to adjust a speed of the condenser fan motor; and the control module is separate from the driver and the condenser fan motor assembly. 11. The drive circuit of claim 8, wherein:
the buck converter comprises
a switch, and
a driver configured to transition the switch between an open state and a closed state; and
a peak voltage of the DC voltage signal is based on an average voltage at an output of the switch. 12. The drive circuit of claim 8, wherein:
the buck converter comprises a switch and a driver; and the driver is configured to reduce a DC voltage of the first DC voltage signal by adjusting a duty cycle of the switch. 13. A drive circuit comprising:
a rectification circuit configured to rectify a first alternating current (AC) voltage signal to generate a rectified voltage signal; a buck converter configured to downconvert the rectified voltage signal to a direct current (DC) voltage signal, wherein the DC voltage signal is supplied to a DC bus; and a first inverter configured to convert the DC voltage signal to a second AC voltage signal and supply the second AC voltage signal to a compressor motor and to a condenser fan motor, wherein peak voltages of the second AC voltage signal are less than peak voltages of the first AC voltage signal. 14. The drive circuit of claim 13, wherein a number of poles of the condenser fan motor is greater than a number of poles of a motor of the compressor motor. 15. The drive circuit of claim 14, wherein
the condenser fan motor is an induction motor; and the motor of the compressor motor is an induction motor or a permanent magnet motor. 16. The drive circuit of claim 13, wherein a number of poles of the condenser fan motor is twice or three times the number of poles of the compressor motor. 17. The drive circuit of claim 13, wherein a speed of the condenser fan motor is based on the second AC voltage signal, such that a speed of the condenser fan motor is adjusted when a speed of the compressor motor is adjusted. 18. The drive circuit of claim 13, wherein the condenser fan motor is operated at a same stator frequency as a motor of the compressor motor. 19. The drive circuit of claim 13, wherein:
the buck converter comprises
a switch, and
a driver configured to transition the switch between an open state and a closed state;
a peak voltage of the DC voltage signal is based on an average voltage at an output of the switch; and the driver is configured to reduce a DC voltage of the DC voltage signal by adjusting a duty cycle of the switch. 20. The drive circuit of claim 13, further comprising a control module, wherein:
the buck converter comprises a switch and a driver; the driver is configured to receive a first control signal from the control module and control a state of the switch based on the first control signal; the inverter is configured to receive a plurality of control signals from the driver or the control module; and the control module is separate from the driver. | 2,800 |
11,924 | 11,924 | 15,825,486 | 2,897 | A semiconductor device forming a bidirectional switch includes a carrier, first and second semiconductor elements arranged on the carrier, a first row of terminals arranged along a first side face of the carrier, a second row of terminals arranged along a second side face of the carrier opposite the first side face, and an encapsulation body encapsulating the first and second semiconductor elements. Each row of terminals includes a gate terminal, a sensing terminal and at least one power terminal of the bidirectional switch. | 1. A semiconductor device forming a bidirectional switch, the semiconductor device comprising:
a carrier; a first semiconductor chip and a second semiconductor chip arranged on the carrier; a first row of terminals arranged along a first side face of the carrier; a second row of terminals arranged along a second side face of the carrier opposite the first side face; and an encapsulation body encapsulating the first and the second semiconductor chips, wherein the first semiconductor chip comprises a first transistor structure comprising first source, drain and gate electrodes, wherein the second semiconductor chip comprises a second transistor structure comprising second source, drain and gate electrodes, wherein the first and the second transistor structures are coupled with each other by the respective first and second drain electrodes via the carrier, wherein the first row of terminals comprises a first gate terminal coupled with the first gate electrode, a first sensing terminal coupled with the first source electrode, and a first power terminal of the bidirectional switch coupled with the first source electrode, wherein the second row of terminals comprises a second gate terminal coupled with the second gate electrode, a second sensing terminal coupled with the second source electrode, and a second power terminal of the bidirectional switch coupled with the second source electrode, wherein the carrier and the first and the second rows of terminals are parts of a leadframe. 2. The semiconductor device of claim 1, wherein the first and the second semiconductor chips are implemented monolithically. 3. The semiconductor device of claim 1, wherein the first and the second semiconductor chips are identical semiconductor chips. 4. The semiconductor device of claim 1, wherein the first and the second semiconductor chips are arranged on a first main face of the carrier, and wherein a second main face of the carrier opposite the first main face is exposed from the encapsulation body. 5. The semiconductor device of claim 1, wherein the first and the second rows of terminals are physically separated from the carrier. 6. A semiconductor device forming a bidirectional switch, the semiconductor device comprising:
a first carrier; a second carrier; a first semiconductor chip arranged on the first carrier; a second semiconductor chip arranged on the second carrier; an encapsulation body encapsulating the first and the second semiconductor chips; a first row of terminals arranged along a first side face of the encapsulation body; and a second row of terminals arranged along a second side face of the encapsulation body opposite the first side face, wherein the first semiconductor chip comprises a first transistor structure comprising first source, drain and gate electrodes, wherein the second semiconductor chip comprises a second transistor structure comprising second source, drain and gate electrodes, wherein the first and the second transistor structures are coupled with each other by the respective first and second source electrodes, wherein the first row of terminals comprises a first gate terminal coupled with the first gate electrode, a first sensing terminal coupled with the first source electrode, and a first power terminal coupled with the first drain electrode, wherein the second row of terminals comprises a second gate terminal coupled with the second gate electrode, a second sensing terminal coupled with the second source electrode, and a second power terminal of the bidirectional switch coupled with the second drain electrode. 7. The semiconductor device of claim 6, wherein the first sensing terminal of the first row of terminals, the source electrode of the first semiconductor chip, the source electrode of the second semiconductor chip, and the second sensing terminal of the second row of terminals are electrically coupled by a contiguous bonding wire. 8. The semiconductor device of claim 6, wherein the first power terminal of the first row of terminals is an integral part of the first carrier, and wherein the second power terminal of the second row of terminals is an integral part of the second carrier. 9. The semiconductor device of claim 6, wherein at each semiconductor chip a drain electrode is arranged on a lower main face facing the first and the second carrier and each being electrically coupled to the first and the second carrier. 10. The semiconductor device of claim 6, wherein the first and the second carriers are separated from one another. 11. A semiconductor device forming a bidirectional switch, the semiconductor device comprising:
a carrier; a semiconductor element arranged on the carrier; a first row of terminals arranged along a first side face of the carrier; a second row of terminals arranged along a second side face of the carrier opposite the first side face; and an encapsulation body encapsulating the semiconductor element, wherein the semiconductor element comprises a first transistor structure comprising first source and gate electrodes and a second transistor structure comprising second source and gate electrodes, the first and the second transistor structures comprising a common drain electrode, wherein the first row of terminals comprises a first gate terminal coupled with the first gate electrode, a first sensing terminal coupled with the first source electrode, and a first power terminal of the bidirectional switch coupled with the first source electrode, wherein the second row of terminals comprises a second gate terminal coupled with the second gate electrode, a second sensing terminal coupled with the second source electrode, and a second power terminal of the bidirectional switch coupled with the second source electrode. 12. The semiconductor device of claim 11, wherein the semiconductor element comprises a III-V semiconductor. 13. The semiconductor device of claim 12, wherein the III-V semiconductor is GaN. 14. The semiconductor device of claim 11, wherein the first and the second rows of terminals are physically separated from the carrier. | A semiconductor device forming a bidirectional switch includes a carrier, first and second semiconductor elements arranged on the carrier, a first row of terminals arranged along a first side face of the carrier, a second row of terminals arranged along a second side face of the carrier opposite the first side face, and an encapsulation body encapsulating the first and second semiconductor elements. Each row of terminals includes a gate terminal, a sensing terminal and at least one power terminal of the bidirectional switch.1. A semiconductor device forming a bidirectional switch, the semiconductor device comprising:
a carrier; a first semiconductor chip and a second semiconductor chip arranged on the carrier; a first row of terminals arranged along a first side face of the carrier; a second row of terminals arranged along a second side face of the carrier opposite the first side face; and an encapsulation body encapsulating the first and the second semiconductor chips, wherein the first semiconductor chip comprises a first transistor structure comprising first source, drain and gate electrodes, wherein the second semiconductor chip comprises a second transistor structure comprising second source, drain and gate electrodes, wherein the first and the second transistor structures are coupled with each other by the respective first and second drain electrodes via the carrier, wherein the first row of terminals comprises a first gate terminal coupled with the first gate electrode, a first sensing terminal coupled with the first source electrode, and a first power terminal of the bidirectional switch coupled with the first source electrode, wherein the second row of terminals comprises a second gate terminal coupled with the second gate electrode, a second sensing terminal coupled with the second source electrode, and a second power terminal of the bidirectional switch coupled with the second source electrode, wherein the carrier and the first and the second rows of terminals are parts of a leadframe. 2. The semiconductor device of claim 1, wherein the first and the second semiconductor chips are implemented monolithically. 3. The semiconductor device of claim 1, wherein the first and the second semiconductor chips are identical semiconductor chips. 4. The semiconductor device of claim 1, wherein the first and the second semiconductor chips are arranged on a first main face of the carrier, and wherein a second main face of the carrier opposite the first main face is exposed from the encapsulation body. 5. The semiconductor device of claim 1, wherein the first and the second rows of terminals are physically separated from the carrier. 6. A semiconductor device forming a bidirectional switch, the semiconductor device comprising:
a first carrier; a second carrier; a first semiconductor chip arranged on the first carrier; a second semiconductor chip arranged on the second carrier; an encapsulation body encapsulating the first and the second semiconductor chips; a first row of terminals arranged along a first side face of the encapsulation body; and a second row of terminals arranged along a second side face of the encapsulation body opposite the first side face, wherein the first semiconductor chip comprises a first transistor structure comprising first source, drain and gate electrodes, wherein the second semiconductor chip comprises a second transistor structure comprising second source, drain and gate electrodes, wherein the first and the second transistor structures are coupled with each other by the respective first and second source electrodes, wherein the first row of terminals comprises a first gate terminal coupled with the first gate electrode, a first sensing terminal coupled with the first source electrode, and a first power terminal coupled with the first drain electrode, wherein the second row of terminals comprises a second gate terminal coupled with the second gate electrode, a second sensing terminal coupled with the second source electrode, and a second power terminal of the bidirectional switch coupled with the second drain electrode. 7. The semiconductor device of claim 6, wherein the first sensing terminal of the first row of terminals, the source electrode of the first semiconductor chip, the source electrode of the second semiconductor chip, and the second sensing terminal of the second row of terminals are electrically coupled by a contiguous bonding wire. 8. The semiconductor device of claim 6, wherein the first power terminal of the first row of terminals is an integral part of the first carrier, and wherein the second power terminal of the second row of terminals is an integral part of the second carrier. 9. The semiconductor device of claim 6, wherein at each semiconductor chip a drain electrode is arranged on a lower main face facing the first and the second carrier and each being electrically coupled to the first and the second carrier. 10. The semiconductor device of claim 6, wherein the first and the second carriers are separated from one another. 11. A semiconductor device forming a bidirectional switch, the semiconductor device comprising:
a carrier; a semiconductor element arranged on the carrier; a first row of terminals arranged along a first side face of the carrier; a second row of terminals arranged along a second side face of the carrier opposite the first side face; and an encapsulation body encapsulating the semiconductor element, wherein the semiconductor element comprises a first transistor structure comprising first source and gate electrodes and a second transistor structure comprising second source and gate electrodes, the first and the second transistor structures comprising a common drain electrode, wherein the first row of terminals comprises a first gate terminal coupled with the first gate electrode, a first sensing terminal coupled with the first source electrode, and a first power terminal of the bidirectional switch coupled with the first source electrode, wherein the second row of terminals comprises a second gate terminal coupled with the second gate electrode, a second sensing terminal coupled with the second source electrode, and a second power terminal of the bidirectional switch coupled with the second source electrode. 12. The semiconductor device of claim 11, wherein the semiconductor element comprises a III-V semiconductor. 13. The semiconductor device of claim 12, wherein the III-V semiconductor is GaN. 14. The semiconductor device of claim 11, wherein the first and the second rows of terminals are physically separated from the carrier. | 2,800 |
11,925 | 11,925 | 14,318,658 | 2,865 | A method for determining power output levels of a plurality of nodes in an electric power system includes receiving, at a first node of the plurality of nodes, voltage information and multipliers of all neighboring nodes of the first node within the electric power system, determining, by the first node, a local power generation and a local voltage using the voltage information and the multipliers of the neighboring nodes and distributing the local power generation and the local voltage to the neighboring nodes, determining, by the first node, an estimated voltage of each of the neighboring nodes and distributing the estimated voltage to each of the neighboring nodes, and updating, by the first node, a local multiplier using the voltage information received from the neighboring nodes and the estimated voltage of each of the neighboring nodes determined by the node. | 1. A method for determining power output levels of a plurality of nodes in an electric power system comprising:
receiving, at a first node of the plurality of nodes, voltage information and multipliers of all neighboring nodes of the first node within the electric power system; determining, by the first node, a local power generation and a local voltage using the voltage information and the multipliers of the neighboring nodes and distributing the local power generation and the local voltage to the neighboring nodes; determining, by the first node, an estimated voltage of each of the neighboring nodes and distributing the estimated voltage to each of the neighboring nodes; and updating, by the first node, a local multiplier using the voltage information received from the neighboring nodes and the estimated voltage of each of the neighboring nodes determined by the node. 2. The method of claim 1, performed by each node of the plurality of nodes. 3. The method of claim 1, iteratively performed by the first node, the method further comprising evaluating a stopping criteria after updating the local multiplier. 4. The method of claim 1, wherein the first node is a power generator in the electric power system. 5. The method of claim 1, wherein each of the plurality of nodes are power generators in the electric power system. 6. The method of claim 1, implemented as a fully distributed system wherein each of the plurality of nodes communicates directly with all of its neighboring nodes. 7. A computer program product for determining a power output level of a node in an electric power system, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:
receiving, at a first node of the plurality of nodes, voltage information and multipliers of all neighboring nodes of the first node within the electric power system; determining, by the first node, a local power generation and a local voltage using the voltage information and the multipliers of the neighboring nodes and distributing the local power generation and the local voltage to the neighboring nodes; determining, by the first node, an estimated voltage of each of the neighboring nodes and distributing the estimated voltage to each of the neighboring nodes; and updating, by the first node, a local multiplier using the voltage information received from the neighboring nodes and the estimated voltage of each of the neighboring nodes determined by the node. 8. The computer program product of claim 7, performed by each node of the plurality of nodes. 9. The computer program product of claim 7, iteratively performed by the first node, the method further comprising evaluating a stopping criteria after updating the local multiplier. 10. The computer program product of claim 7, wherein the first node is a power generator in the electric power system. 11. The computer program product of claim 7, wherein each of the plurality of nodes are power generators in the electric power system. 12. The computer program product of claim 7, implemented as a fully distributed system wherein each of the plurality of nodes communicates directly with all of its neighboring nodes. 13. A generator in an electric power system configured to determine a power output level comprising:
a computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the generator to: receive, from at least one neighboring generator within the electric power system, voltage information and multipliers; determine a local power generation and a local voltage using the voltage information and the multipliers of the at least one neighboring node and distributing the local power generation and the local voltage to the at least one neighboring node; determine an estimated voltage of the at least one neighboring node and distributing the estimated voltage to the at least one neighboring node; and update a local multiplier using the voltage information received from the at least one neighboring node and the estimated voltage of the at least one neighboring node determined by the generator. 14. The generator of claim 13, iteratively executing the program of instructions and further comprising evaluating a stopping criteria after updating the local multiplier. 15. The generator of claim 14, further comprising a communication module configured for two-way communication with the at least one neighboring node. | A method for determining power output levels of a plurality of nodes in an electric power system includes receiving, at a first node of the plurality of nodes, voltage information and multipliers of all neighboring nodes of the first node within the electric power system, determining, by the first node, a local power generation and a local voltage using the voltage information and the multipliers of the neighboring nodes and distributing the local power generation and the local voltage to the neighboring nodes, determining, by the first node, an estimated voltage of each of the neighboring nodes and distributing the estimated voltage to each of the neighboring nodes, and updating, by the first node, a local multiplier using the voltage information received from the neighboring nodes and the estimated voltage of each of the neighboring nodes determined by the node.1. A method for determining power output levels of a plurality of nodes in an electric power system comprising:
receiving, at a first node of the plurality of nodes, voltage information and multipliers of all neighboring nodes of the first node within the electric power system; determining, by the first node, a local power generation and a local voltage using the voltage information and the multipliers of the neighboring nodes and distributing the local power generation and the local voltage to the neighboring nodes; determining, by the first node, an estimated voltage of each of the neighboring nodes and distributing the estimated voltage to each of the neighboring nodes; and updating, by the first node, a local multiplier using the voltage information received from the neighboring nodes and the estimated voltage of each of the neighboring nodes determined by the node. 2. The method of claim 1, performed by each node of the plurality of nodes. 3. The method of claim 1, iteratively performed by the first node, the method further comprising evaluating a stopping criteria after updating the local multiplier. 4. The method of claim 1, wherein the first node is a power generator in the electric power system. 5. The method of claim 1, wherein each of the plurality of nodes are power generators in the electric power system. 6. The method of claim 1, implemented as a fully distributed system wherein each of the plurality of nodes communicates directly with all of its neighboring nodes. 7. A computer program product for determining a power output level of a node in an electric power system, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:
receiving, at a first node of the plurality of nodes, voltage information and multipliers of all neighboring nodes of the first node within the electric power system; determining, by the first node, a local power generation and a local voltage using the voltage information and the multipliers of the neighboring nodes and distributing the local power generation and the local voltage to the neighboring nodes; determining, by the first node, an estimated voltage of each of the neighboring nodes and distributing the estimated voltage to each of the neighboring nodes; and updating, by the first node, a local multiplier using the voltage information received from the neighboring nodes and the estimated voltage of each of the neighboring nodes determined by the node. 8. The computer program product of claim 7, performed by each node of the plurality of nodes. 9. The computer program product of claim 7, iteratively performed by the first node, the method further comprising evaluating a stopping criteria after updating the local multiplier. 10. The computer program product of claim 7, wherein the first node is a power generator in the electric power system. 11. The computer program product of claim 7, wherein each of the plurality of nodes are power generators in the electric power system. 12. The computer program product of claim 7, implemented as a fully distributed system wherein each of the plurality of nodes communicates directly with all of its neighboring nodes. 13. A generator in an electric power system configured to determine a power output level comprising:
a computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the generator to: receive, from at least one neighboring generator within the electric power system, voltage information and multipliers; determine a local power generation and a local voltage using the voltage information and the multipliers of the at least one neighboring node and distributing the local power generation and the local voltage to the at least one neighboring node; determine an estimated voltage of the at least one neighboring node and distributing the estimated voltage to the at least one neighboring node; and update a local multiplier using the voltage information received from the at least one neighboring node and the estimated voltage of the at least one neighboring node determined by the generator. 14. The generator of claim 13, iteratively executing the program of instructions and further comprising evaluating a stopping criteria after updating the local multiplier. 15. The generator of claim 14, further comprising a communication module configured for two-way communication with the at least one neighboring node. | 2,800 |
11,926 | 11,926 | 15,182,309 | 2,875 | Electronic devices may include displays. A display may include backlight components that provide backlight illumination for the display. Backlight components may include a light guide plate that distributes light from a light source across the display. Display chassis structures may be used to support display layers and backlight components. A metal chassis may include a portion that partially surrounds the light source. Openings or perforations in the metal chassis may allow the portion that surrounds the light source to flex about a flex axis. A portion of a display layer may be mounted to a plastic chassis. The plastic chassis may be insert molded over a light source, may form part of a package for a light source, may be adhered to a light source, or may wrap around the light source. An encapsulant may be formed over the light source to protect the light source from vibrations and contaminants. | 1. An electronic device, comprising:
a display having a display layer; a light source configured to provide light; a light guide plate configured to receive the light and to provide the light to the display as backlight illumination; and a plastic display chassis on which a portion of the display layer is mounted, wherein the plastic display chassis partially surrounds the light source. 2. The electronic device defined in claim 1 wherein the light source comprises a light-emitting diode and wherein the light-emitting diode comprises a semiconductor device mounted on a lead frame structure. 3. The electronic device defined in claim 2 further comprising a wire bond that electrically couples the semiconductor device to the lead frame structure. 4. The electronic device defined in claim 2 wherein the plastic display chassis is molded over at least some of the lead frame structure to form a package for the light source. 5. The electronic device defined in claim 2 further comprising a printed circuit substrate, wherein the light-emitting diode is attached to the printed circuit substrate using solder. 6. The electronic device defined in claim 5 further comprising a metal display chassis, wherein the printed circuit substrate is attached to the metal display chassis using adhesive. 7. The electronic device defined in claim 2, wherein the semiconductor device and the lead frame structure are mounted in a package for the light-emitting diode. 8. The electronic device defined in claim 7, wherein the plastic display chassis is molded over the semiconductor device and the lead frame structure to form the package for the light-emitting diode. 9. The electronic device defined in claim 7, wherein the plastic chassis comprises a bent portion that wraps around the package for the light-emitting diode. 10. An electronic device, comprising:
a liquid crystal display having opposing upper and lower polarizers, a color filter layer and a thin-film transistor layer interposed between the upper and lower polarizers, and a layer of liquid crystal between the color filter layer and the thin film transistor layer; a light guide plate that provides backlight to the liquid crystal display; light-emitting diodes that emit light into the light guide plate; and a metal chassis beneath the light guide plate and the light-emitting diodes that does not wrap around the light-emitting diodes. 11. The electronic device defined in claim 10 further comprising:
a plastic chassis having a bent portion that wraps around the light emitting diodes, wherein the plastic chassis comprises a first portion that is attached to the metal chassis with a first adhesive layer and a second portion that is attached to the lower polarizer with a second adhesive layer. 12. The electronic device defined in claim 10 further comprising:
a plastic chassis that is attached to and at least partially surrounds the light-emitting diodes. 13. An electronic device, comprising:
a display having a display layer; a light source configured to provide light; a light guide plate configured to receive the light and to provide the light to the display as backlight illumination; and an insert molded plastic display chassis on which a portion of the display layer is mounted, wherein the insert molded plastic display chassis is insert molded over the light source. 14. The electronic device defined in claim 13 wherein the light source includes a diode die mounted within a molded package and wherein the insert molded plastic display chassis is insert molded over the molded package. 15. The electronic device defined in claim 13 further comprising an encapsulant formed over the light source, wherein the insert molded plastic display chassis is insert molded over the encapsulant. 16. The electronic device defined in claim 15 wherein the encapsulant comprises potting material. 17. The electronic device defined in claim 13, further comprising a sheet of metal, wherein the light source is interposed between the insert molded plastic display chassis and the sheet of metal. 18. The electronic device defined in claim 17, further comprising a flexible substrate on which the light source is mounted. 19. The electronic device defined in claim 18 wherein the flexible substrate is attached to the sheet of metal with adhesive. 20. The electronic device defined in claim 19 wherein the insert molded plastic display chassis comprises polycarbonate. | Electronic devices may include displays. A display may include backlight components that provide backlight illumination for the display. Backlight components may include a light guide plate that distributes light from a light source across the display. Display chassis structures may be used to support display layers and backlight components. A metal chassis may include a portion that partially surrounds the light source. Openings or perforations in the metal chassis may allow the portion that surrounds the light source to flex about a flex axis. A portion of a display layer may be mounted to a plastic chassis. The plastic chassis may be insert molded over a light source, may form part of a package for a light source, may be adhered to a light source, or may wrap around the light source. An encapsulant may be formed over the light source to protect the light source from vibrations and contaminants.1. An electronic device, comprising:
a display having a display layer; a light source configured to provide light; a light guide plate configured to receive the light and to provide the light to the display as backlight illumination; and a plastic display chassis on which a portion of the display layer is mounted, wherein the plastic display chassis partially surrounds the light source. 2. The electronic device defined in claim 1 wherein the light source comprises a light-emitting diode and wherein the light-emitting diode comprises a semiconductor device mounted on a lead frame structure. 3. The electronic device defined in claim 2 further comprising a wire bond that electrically couples the semiconductor device to the lead frame structure. 4. The electronic device defined in claim 2 wherein the plastic display chassis is molded over at least some of the lead frame structure to form a package for the light source. 5. The electronic device defined in claim 2 further comprising a printed circuit substrate, wherein the light-emitting diode is attached to the printed circuit substrate using solder. 6. The electronic device defined in claim 5 further comprising a metal display chassis, wherein the printed circuit substrate is attached to the metal display chassis using adhesive. 7. The electronic device defined in claim 2, wherein the semiconductor device and the lead frame structure are mounted in a package for the light-emitting diode. 8. The electronic device defined in claim 7, wherein the plastic display chassis is molded over the semiconductor device and the lead frame structure to form the package for the light-emitting diode. 9. The electronic device defined in claim 7, wherein the plastic chassis comprises a bent portion that wraps around the package for the light-emitting diode. 10. An electronic device, comprising:
a liquid crystal display having opposing upper and lower polarizers, a color filter layer and a thin-film transistor layer interposed between the upper and lower polarizers, and a layer of liquid crystal between the color filter layer and the thin film transistor layer; a light guide plate that provides backlight to the liquid crystal display; light-emitting diodes that emit light into the light guide plate; and a metal chassis beneath the light guide plate and the light-emitting diodes that does not wrap around the light-emitting diodes. 11. The electronic device defined in claim 10 further comprising:
a plastic chassis having a bent portion that wraps around the light emitting diodes, wherein the plastic chassis comprises a first portion that is attached to the metal chassis with a first adhesive layer and a second portion that is attached to the lower polarizer with a second adhesive layer. 12. The electronic device defined in claim 10 further comprising:
a plastic chassis that is attached to and at least partially surrounds the light-emitting diodes. 13. An electronic device, comprising:
a display having a display layer; a light source configured to provide light; a light guide plate configured to receive the light and to provide the light to the display as backlight illumination; and an insert molded plastic display chassis on which a portion of the display layer is mounted, wherein the insert molded plastic display chassis is insert molded over the light source. 14. The electronic device defined in claim 13 wherein the light source includes a diode die mounted within a molded package and wherein the insert molded plastic display chassis is insert molded over the molded package. 15. The electronic device defined in claim 13 further comprising an encapsulant formed over the light source, wherein the insert molded plastic display chassis is insert molded over the encapsulant. 16. The electronic device defined in claim 15 wherein the encapsulant comprises potting material. 17. The electronic device defined in claim 13, further comprising a sheet of metal, wherein the light source is interposed between the insert molded plastic display chassis and the sheet of metal. 18. The electronic device defined in claim 17, further comprising a flexible substrate on which the light source is mounted. 19. The electronic device defined in claim 18 wherein the flexible substrate is attached to the sheet of metal with adhesive. 20. The electronic device defined in claim 19 wherein the insert molded plastic display chassis comprises polycarbonate. | 2,800 |
11,927 | 11,927 | 14,376,707 | 2,836 | An energy production system with energy store and method for operating an energy production system, solar cells, particularly a module including solar cells, being connected to an inverter, especially at its DC-side terminal, the inverter being connected at its terminal on the alternating-voltage side to a power consumer and/or an AC system, a DC/DC converter being connected, especially with its first DC-side terminal, in parallel to the solar cells, particularly to the module including solar cells, the DC/DC converter being connected to an energy store, particularly which is connected to the second DC-side terminal of the DC/DC converter. | 1-15. (canceled) 16. An energy production system, comprising:
an energy store; an inverter; a solar generator connected to the inverter, wherein a terminal on an alternating-voltage side of the inverter is connected to at least one of a power consumer and an AC system; and a power converter connected, in parallel to the solar generator, to the energy store. 17. The energy production system as recited in claim 16, wherein the solar generator includes modules including one or more solar cells. 18. The energy production system as recited in claim 16, wherein the solar generator is connected to a DC-side terminal of the inverter. 19. The energy production system as recited in claim 16, wherein a first DC-side terminal of the power converter is connected to the energy store. 20. The energy production system as recited in claim 19, wherein the energy store is connected to a second DC-side terminal of the power converter. 21. The energy production system as recited in claim 16, wherein at least one of:
the power converter is a DC/DC converter for the energy store, and the power converter is a DC/AC converter for a rotary storage device. 22. The energy production system as recited in claim 21, wherein the rotary storage device includes an electromechanical energy converter. 23. The energy production system as recited in claim 22, wherein the electromechanical energy converter includes an electric machine operable in one of a motor mode and a generator mode. 24. The energy production system as recited in claim 16, further comprising:
a film capacitor connected in parallel to the solar generator. 25. The energy production system as recited in claim 16, wherein at least one of:
the energy store at least one of includes a double-layer capacitor and is made up of a plurality of double-layer capacitors interconnected to each other, and the energy store includes at least one of an accumulator and a battery. 26. The energy production system as recited in claim 16, wherein the inverter includes an MPP tracker. 27. A method for operating an energy production system that includes an energy store, an inverter, a solar generator connected to the inverter, wherein a terminal on an alternating-voltage side of the inverter is connected to at least one of a power consumer and an AC system, and a power converter connected, in parallel to the solar generator, to the energy store, the method comprising:
supplying electrical energy from the energy store via the power converter to the inverter; detecting a voltage present at the inverter on a DC side; and determining, according to a characteristic curve, a setpoint power to be delivered by the power converter to a DC-side terminal of the inverter. 28. The method as recited in claim 27, wherein the inverter includes an MPP tracker. 29. The method as recited in claim 27, wherein the setpoint power delivered by the power converter to the DC-side terminal of the inverter is determined by multiplying a voltage present on the DC side with a current delivered by the power converter to the inverter, wherein the current to be delivered by the power converter to the inverter is determined based on a difference between the setpoint power and an actual power, in doing which, further influence variables such as operating mode, a behavior of an MPP tracker of the inverter are taken into account. 30. The method as recited in claim 27, wherein the characteristic curve represents a correlation of such a kind between power and DC-side voltage, that after addition of a corresponding power-voltage characteristic curve of the solar generator, a value of the voltage at which a maximum of power is present remains essentially unchanged. 31. The method as recited in claim 27, wherein the characteristic curve is changeable so little that after addition of a corresponding power-voltage characteristic curve of the solar generator, a value of a voltage at which a maximum of power exists remains essentially unchanged, so that an MPP tracker regulates to the same power maximum of the solar generator as if no energy store with power converter were present. 32. The method as recited in claim 27, wherein the characteristic curve has a maximum in a voltage range that is formed of those voltage values that in each case belong to an operating point having maximum power of the solar generator as a function of a voltage, all operating conditions, including temperature and light intensity, being taken into account in this connection. 33. A method for operating an energy production system, comprising:
operating an inverter having an MPP tracker to ascertain a DC-side input current; regulating a voltage at a DC-side terminal of the inverter to a maximum of power; connecting an energy-generation arrangement to the DC-side terminal; connecting a device to the DC-side terminal, which from the voltage detected on the DC side and taking a characteristic curve into account, determines a setpoint power; ascertaining an actual current delivered by the device to the DC-side terminal of the inverter as well as the voltage present at the inverter on the DC side; and from the actual current and the voltage present at the inverter on the DC-side, determining an actual power that the device regulates to the setpoint power by determining a corresponding setpoint current and regulating thereto. 34. The method as recited in claim 33, wherein the energy-generation arrangement includes at least one solar cell. 35. The method as recited in claim 33, wherein the characteristic curve represents a dependence of the setpoint power on the voltage present at the inverter on the DC side. 36. The method as recited in claim 33, wherein the characteristic curve is alterable with the aid of a primary control action. 37. The method as recited in claim 33, wherein the characteristic curve is altered by influence variables accordingly. 38. The method as recited in claim 37, wherein the characteristic curve is altered by being one of expanded and compressed in an ordinate direction. 39. The method as recited in claim 33, wherein a preceding sign of the characteristic curve is a function of an operating mode. 40. The method as recited in claim 39, wherein the operating mode involves one of a withdrawal of energy from and a feeding of energy into the energy store. 41. The method as recited in claim 33, wherein the characteristic curve has a constant setpoint-power value in a voltage range which includes a specific voltage value that is assigned to a power maximum of the solar generator. 42. The method as recited in claim 41, wherein the specific voltage value is assigned to the power maximum of the solar generator in the case of all operating conditions of the solar generator. 43. The method as recited in claim 42, wherein the operating conditions includes at least one of permissible temperatures and light intensities. 44. The method as recited in claim 41, wherein the characteristic curve has a locally minimal progression of setpoint-power values as a function of the voltage in a voltage range which includes the specific voltage value that is assigned to the power maximum of the solar generator. 45. The method as recited in claim 44, wherein the specific voltage is assigned to the power maximum of the solar generator in the case of all light intensities of the solar generator. | An energy production system with energy store and method for operating an energy production system, solar cells, particularly a module including solar cells, being connected to an inverter, especially at its DC-side terminal, the inverter being connected at its terminal on the alternating-voltage side to a power consumer and/or an AC system, a DC/DC converter being connected, especially with its first DC-side terminal, in parallel to the solar cells, particularly to the module including solar cells, the DC/DC converter being connected to an energy store, particularly which is connected to the second DC-side terminal of the DC/DC converter.1-15. (canceled) 16. An energy production system, comprising:
an energy store; an inverter; a solar generator connected to the inverter, wherein a terminal on an alternating-voltage side of the inverter is connected to at least one of a power consumer and an AC system; and a power converter connected, in parallel to the solar generator, to the energy store. 17. The energy production system as recited in claim 16, wherein the solar generator includes modules including one or more solar cells. 18. The energy production system as recited in claim 16, wherein the solar generator is connected to a DC-side terminal of the inverter. 19. The energy production system as recited in claim 16, wherein a first DC-side terminal of the power converter is connected to the energy store. 20. The energy production system as recited in claim 19, wherein the energy store is connected to a second DC-side terminal of the power converter. 21. The energy production system as recited in claim 16, wherein at least one of:
the power converter is a DC/DC converter for the energy store, and the power converter is a DC/AC converter for a rotary storage device. 22. The energy production system as recited in claim 21, wherein the rotary storage device includes an electromechanical energy converter. 23. The energy production system as recited in claim 22, wherein the electromechanical energy converter includes an electric machine operable in one of a motor mode and a generator mode. 24. The energy production system as recited in claim 16, further comprising:
a film capacitor connected in parallel to the solar generator. 25. The energy production system as recited in claim 16, wherein at least one of:
the energy store at least one of includes a double-layer capacitor and is made up of a plurality of double-layer capacitors interconnected to each other, and the energy store includes at least one of an accumulator and a battery. 26. The energy production system as recited in claim 16, wherein the inverter includes an MPP tracker. 27. A method for operating an energy production system that includes an energy store, an inverter, a solar generator connected to the inverter, wherein a terminal on an alternating-voltage side of the inverter is connected to at least one of a power consumer and an AC system, and a power converter connected, in parallel to the solar generator, to the energy store, the method comprising:
supplying electrical energy from the energy store via the power converter to the inverter; detecting a voltage present at the inverter on a DC side; and determining, according to a characteristic curve, a setpoint power to be delivered by the power converter to a DC-side terminal of the inverter. 28. The method as recited in claim 27, wherein the inverter includes an MPP tracker. 29. The method as recited in claim 27, wherein the setpoint power delivered by the power converter to the DC-side terminal of the inverter is determined by multiplying a voltage present on the DC side with a current delivered by the power converter to the inverter, wherein the current to be delivered by the power converter to the inverter is determined based on a difference between the setpoint power and an actual power, in doing which, further influence variables such as operating mode, a behavior of an MPP tracker of the inverter are taken into account. 30. The method as recited in claim 27, wherein the characteristic curve represents a correlation of such a kind between power and DC-side voltage, that after addition of a corresponding power-voltage characteristic curve of the solar generator, a value of the voltage at which a maximum of power is present remains essentially unchanged. 31. The method as recited in claim 27, wherein the characteristic curve is changeable so little that after addition of a corresponding power-voltage characteristic curve of the solar generator, a value of a voltage at which a maximum of power exists remains essentially unchanged, so that an MPP tracker regulates to the same power maximum of the solar generator as if no energy store with power converter were present. 32. The method as recited in claim 27, wherein the characteristic curve has a maximum in a voltage range that is formed of those voltage values that in each case belong to an operating point having maximum power of the solar generator as a function of a voltage, all operating conditions, including temperature and light intensity, being taken into account in this connection. 33. A method for operating an energy production system, comprising:
operating an inverter having an MPP tracker to ascertain a DC-side input current; regulating a voltage at a DC-side terminal of the inverter to a maximum of power; connecting an energy-generation arrangement to the DC-side terminal; connecting a device to the DC-side terminal, which from the voltage detected on the DC side and taking a characteristic curve into account, determines a setpoint power; ascertaining an actual current delivered by the device to the DC-side terminal of the inverter as well as the voltage present at the inverter on the DC side; and from the actual current and the voltage present at the inverter on the DC-side, determining an actual power that the device regulates to the setpoint power by determining a corresponding setpoint current and regulating thereto. 34. The method as recited in claim 33, wherein the energy-generation arrangement includes at least one solar cell. 35. The method as recited in claim 33, wherein the characteristic curve represents a dependence of the setpoint power on the voltage present at the inverter on the DC side. 36. The method as recited in claim 33, wherein the characteristic curve is alterable with the aid of a primary control action. 37. The method as recited in claim 33, wherein the characteristic curve is altered by influence variables accordingly. 38. The method as recited in claim 37, wherein the characteristic curve is altered by being one of expanded and compressed in an ordinate direction. 39. The method as recited in claim 33, wherein a preceding sign of the characteristic curve is a function of an operating mode. 40. The method as recited in claim 39, wherein the operating mode involves one of a withdrawal of energy from and a feeding of energy into the energy store. 41. The method as recited in claim 33, wherein the characteristic curve has a constant setpoint-power value in a voltage range which includes a specific voltage value that is assigned to a power maximum of the solar generator. 42. The method as recited in claim 41, wherein the specific voltage value is assigned to the power maximum of the solar generator in the case of all operating conditions of the solar generator. 43. The method as recited in claim 42, wherein the operating conditions includes at least one of permissible temperatures and light intensities. 44. The method as recited in claim 41, wherein the characteristic curve has a locally minimal progression of setpoint-power values as a function of the voltage in a voltage range which includes the specific voltage value that is assigned to the power maximum of the solar generator. 45. The method as recited in claim 44, wherein the specific voltage is assigned to the power maximum of the solar generator in the case of all light intensities of the solar generator. | 2,800 |
11,928 | 11,928 | 15,347,392 | 2,834 | A permanent magnet embedded rotating electrical machine such that permanent magnets of a multiple of poles are embedded in an interior of a rotor of which one pole is configured by two permanent magnets has a rotor such that an outer periphery of the rotor and a magnet embedding hole housing the permanent magnet communicate. Magnet embedding holes are arrayed so as to form an inverted V-shape. An auxiliary process, which is a V-shape process, a boss process, a pinhole process, or a bolt hole process, is performed in a region between an inscribed circle of the magnet embedding hole and the outer periphery of the rotor in each rotor steel plate configuring the rotor. | 1. A permanent magnet embedded rotating electrical machine comprising:
a rotor comprised of a plurality of stacked rotor steel plates, the rotor having
a plurality of poles, each of the poles configured by two permanent magnets embedded in an interior of the rotor, and
in each of the plurality of poles, two magnet embedding holes and a center bridge between the two magnet embedding holes, each of the two magnet embedding holes housing one of the two permanent magnets configuring the respective pole and being in communication with an outer periphery of the rotor,
each of the plurality of stacked rotor steel plates having, in a region thereof between an inscribed circle of the magnet embedding hole and an outer periphery of the rotor, a structure, formed by an auxiliary process, to fix positions of neighboring plates of the plurality of stacked rotor steel plates. 2. The permanent magnet embedded rotating electrical machine according to claim 1, wherein in each of the plurality of poles,
each of the two magnet embedding holes has an inner peripheral wall on a side thereof that is proximate to a central axis of rotation of the rotor, and the inner peripheral wall has a region that projects in a direction away from a center of rotation of the rotor as the region moves away from a center of neighboring poles and approaches a region between the two magnet embedding holes. 3. The permanent magnet embedded rotating electrical machine according to claim 1, wherein the structure formed by the auxiliary process is in one place within a region of the plurality of poles in the rotor steel plate. 4. The permanent magnet embedded rotating electrical machine according to claim 1, wherein the rotor has a q-axis projection protruding in a direction away from a central axis of rotation of the rotor between neighboring poles. 5. The permanent magnet embedded rotating electrical machine according to claim 1, having a positioning projection that regulates movement of the permanent magnet in a region of an inner wall of the magnet embedding hole on an outer side in a rotor radial direction as seen from the permanent magnet. 6. The permanent magnet embedded rotating electrical machine according to claim 5, wherein the positioning projection is provided on a side communicating with the outer periphery of the rotor. 7. The permanent magnet embedded rotating electrical machine according to claim 1, wherein one portion or a whole of an outer peripheral surface of at least one of the rotor steel plates on an outer side of the permanent magnet as seen from a rotor center of rotation has a radius of curvature smaller than a distance from a central axis of rotation of the rotor to an outermost peripheral portion of the rotor. 8. The permanent magnet embedded rotating electrical machine according to claim 1, wherein in each of the plurality of poles, the permanent magnets are fixed to the magnet embedding holes by an adhesive. 9. The permanent magnet embedded rotating electrical machine according to claim 1, wherein for each of the rotor steel plates, the structure formed by the auxiliary process is any one or more of:
a V-shaped projection portion, aligned with a V-shaped projection portion of a neighboring rotor steel plate and formed by a V-shape process included in the auxiliary process, a boss projection portion, aligned with a boss projection of a neighboring rotor steel plate and formed by a boss process included in the auxiliary process, a pinhole, aligned with a pinhole of a neighboring rotor steel plate and formed by a pinhole process included in the auxiliary process, and a bolt hole, aligned with a bolt hole of a neighboring rotor steel plate and formed by a bolt hole process included in the auxiliary process. 10. The permanent magnet embedded rotating electrical machine according to claim 2, wherein for each of the rotor steel plates, the structure formed by the auxiliary process is any one or more of:
a V-shaped projection portion, aligned with a V-shaped projection portion of a neighboring rotor steel plate and formed by a V-shape process included in the auxiliary process, a boss projection portion, aligned with a boss projection of a neighboring rotor steel plate and formed by a boss process included in the auxiliary process, a pinhole, aligned with a pinhole of a neighboring rotor steel plate and formed by a pinhole process included in the auxiliary process, and a bolt hole, aligned with a bolt hole of a neighboring rotor steel plate and formed by a bolt hole process included in the auxiliary process. 11. The permanent magnet embedded rotating electrical machine according to claim 3, wherein for each of the rotor steel plates, the structure formed by the auxiliary process is any one or more of:
a V-shaped projection portion, aligned with a V-shaped projection portion of a neighboring rotor steel plate and formed by a V-shape process included in the auxiliary process, a boss projection portion, aligned with a boss projection of a neighboring rotor steel plate and formed by a boss process included in the auxiliary process, a pinhole, aligned with a pinhole of a neighboring rotor steel plate and formed by a pinhole process included in the auxiliary process, and a bolt hole, aligned with a bolt hole of a neighboring rotor steel plate and formed by a bolt hole process included in the auxiliary process. 12. The permanent magnet embedded rotating electrical machine according to claim 4, wherein for each of the rotor steel plates, the structure formed by the auxiliary process is any one or more of:
a V-shaped projection portion, aligned with a V-shaped projection portion of a neighboring rotor steel plate and formed by a V-shape process included in the auxiliary process, a boss projection portion, aligned with a boss projection of a neighboring rotor steel plate and formed by a boss process included in the auxiliary process, a pinhole, aligned with a pinhole of a neighboring rotor steel plate and formed by a pinhole process included in the auxiliary process, and a bolt hole, aligned with a bolt hole of a neighboring rotor steel plate and formed by a bolt hole process included in the auxiliary process. 13. The permanent magnet embedded rotating electrical machine according to claim 5, wherein for each of the rotor steel plates, the structure formed by the auxiliary process is any one or more of:
a V-shaped projection portion, aligned with a V-shaped projection portion of a neighboring rotor steel plate and formed by a V-shape process included in the auxiliary process, a boss projection portion, aligned with a boss projection of a neighboring rotor steel plate and formed by a boss process included in the auxiliary process, a pinhole, aligned with a pinhole of a neighboring rotor steel plate and formed by a pinhole process included in the auxiliary process, and a bolt hole, aligned with a bolt hole of a neighboring rotor steel plate and formed by a bolt hole process included in the auxiliary process. 14. The permanent magnet embedded rotating electrical machine according to claim 6, wherein for each of the rotor steel plates, the structure formed by the auxiliary process is any one or more of:
a V-shaped projection portion, aligned with a V-shaped projection portion of a neighboring rotor steel plate and formed by a V-shape process included in the auxiliary process, a boss projection portion, aligned with a boss projection of a neighboring rotor steel plate and formed by a boss process included in the auxiliary process, a pinhole, aligned with a pinhole of a neighboring rotor steel plate and formed by a pinhole process included in the auxiliary process, and a bolt hole, aligned with a bolt hole of a neighboring rotor steel plate and formed by a bolt hole process included in the auxiliary process. 15. The permanent magnet embedded rotating electrical machine according to claim 7, wherein for each of the rotor steel plates, the structure formed by the auxiliary process is any one or more of:
a V-shaped projection portion, aligned with a V-shaped projection portion of a neighboring rotor steel plate and formed by a V-shape process included in the auxiliary process, a boss projection portion, aligned with a boss projection of a neighboring rotor steel plate and formed by a boss process included in the auxiliary process, a pinhole, aligned with a pinhole of a neighboring rotor steel plate and formed by a pinhole process included in the auxiliary process, and a bolt hole, aligned with a bolt hole of a neighboring rotor steel plate and formed by a bolt hole process included in the auxiliary process. 16. The permanent magnet embedded rotating electrical machine according to claim 8, wherein for each of the rotor steel plates, the structure formed by the auxiliary process is any one or more of:
a V-shaped projection portion, aligned with a V-shaped projection portion of a neighboring rotor steel plate and formed by a V-shape process included in the auxiliary process, a boss projection portion, aligned with a boss projection of a neighboring rotor steel plate and formed by a boss process included in the auxiliary process, a pinhole, aligned with a pinhole of a neighboring rotor steel plate and formed by a pinhole process included in the auxiliary process, and a bolt hole, aligned with a bolt hole of a neighboring rotor steel plate and formed by a bolt hole process included in the auxiliary process. | A permanent magnet embedded rotating electrical machine such that permanent magnets of a multiple of poles are embedded in an interior of a rotor of which one pole is configured by two permanent magnets has a rotor such that an outer periphery of the rotor and a magnet embedding hole housing the permanent magnet communicate. Magnet embedding holes are arrayed so as to form an inverted V-shape. An auxiliary process, which is a V-shape process, a boss process, a pinhole process, or a bolt hole process, is performed in a region between an inscribed circle of the magnet embedding hole and the outer periphery of the rotor in each rotor steel plate configuring the rotor.1. A permanent magnet embedded rotating electrical machine comprising:
a rotor comprised of a plurality of stacked rotor steel plates, the rotor having
a plurality of poles, each of the poles configured by two permanent magnets embedded in an interior of the rotor, and
in each of the plurality of poles, two magnet embedding holes and a center bridge between the two magnet embedding holes, each of the two magnet embedding holes housing one of the two permanent magnets configuring the respective pole and being in communication with an outer periphery of the rotor,
each of the plurality of stacked rotor steel plates having, in a region thereof between an inscribed circle of the magnet embedding hole and an outer periphery of the rotor, a structure, formed by an auxiliary process, to fix positions of neighboring plates of the plurality of stacked rotor steel plates. 2. The permanent magnet embedded rotating electrical machine according to claim 1, wherein in each of the plurality of poles,
each of the two magnet embedding holes has an inner peripheral wall on a side thereof that is proximate to a central axis of rotation of the rotor, and the inner peripheral wall has a region that projects in a direction away from a center of rotation of the rotor as the region moves away from a center of neighboring poles and approaches a region between the two magnet embedding holes. 3. The permanent magnet embedded rotating electrical machine according to claim 1, wherein the structure formed by the auxiliary process is in one place within a region of the plurality of poles in the rotor steel plate. 4. The permanent magnet embedded rotating electrical machine according to claim 1, wherein the rotor has a q-axis projection protruding in a direction away from a central axis of rotation of the rotor between neighboring poles. 5. The permanent magnet embedded rotating electrical machine according to claim 1, having a positioning projection that regulates movement of the permanent magnet in a region of an inner wall of the magnet embedding hole on an outer side in a rotor radial direction as seen from the permanent magnet. 6. The permanent magnet embedded rotating electrical machine according to claim 5, wherein the positioning projection is provided on a side communicating with the outer periphery of the rotor. 7. The permanent magnet embedded rotating electrical machine according to claim 1, wherein one portion or a whole of an outer peripheral surface of at least one of the rotor steel plates on an outer side of the permanent magnet as seen from a rotor center of rotation has a radius of curvature smaller than a distance from a central axis of rotation of the rotor to an outermost peripheral portion of the rotor. 8. The permanent magnet embedded rotating electrical machine according to claim 1, wherein in each of the plurality of poles, the permanent magnets are fixed to the magnet embedding holes by an adhesive. 9. The permanent magnet embedded rotating electrical machine according to claim 1, wherein for each of the rotor steel plates, the structure formed by the auxiliary process is any one or more of:
a V-shaped projection portion, aligned with a V-shaped projection portion of a neighboring rotor steel plate and formed by a V-shape process included in the auxiliary process, a boss projection portion, aligned with a boss projection of a neighboring rotor steel plate and formed by a boss process included in the auxiliary process, a pinhole, aligned with a pinhole of a neighboring rotor steel plate and formed by a pinhole process included in the auxiliary process, and a bolt hole, aligned with a bolt hole of a neighboring rotor steel plate and formed by a bolt hole process included in the auxiliary process. 10. The permanent magnet embedded rotating electrical machine according to claim 2, wherein for each of the rotor steel plates, the structure formed by the auxiliary process is any one or more of:
a V-shaped projection portion, aligned with a V-shaped projection portion of a neighboring rotor steel plate and formed by a V-shape process included in the auxiliary process, a boss projection portion, aligned with a boss projection of a neighboring rotor steel plate and formed by a boss process included in the auxiliary process, a pinhole, aligned with a pinhole of a neighboring rotor steel plate and formed by a pinhole process included in the auxiliary process, and a bolt hole, aligned with a bolt hole of a neighboring rotor steel plate and formed by a bolt hole process included in the auxiliary process. 11. The permanent magnet embedded rotating electrical machine according to claim 3, wherein for each of the rotor steel plates, the structure formed by the auxiliary process is any one or more of:
a V-shaped projection portion, aligned with a V-shaped projection portion of a neighboring rotor steel plate and formed by a V-shape process included in the auxiliary process, a boss projection portion, aligned with a boss projection of a neighboring rotor steel plate and formed by a boss process included in the auxiliary process, a pinhole, aligned with a pinhole of a neighboring rotor steel plate and formed by a pinhole process included in the auxiliary process, and a bolt hole, aligned with a bolt hole of a neighboring rotor steel plate and formed by a bolt hole process included in the auxiliary process. 12. The permanent magnet embedded rotating electrical machine according to claim 4, wherein for each of the rotor steel plates, the structure formed by the auxiliary process is any one or more of:
a V-shaped projection portion, aligned with a V-shaped projection portion of a neighboring rotor steel plate and formed by a V-shape process included in the auxiliary process, a boss projection portion, aligned with a boss projection of a neighboring rotor steel plate and formed by a boss process included in the auxiliary process, a pinhole, aligned with a pinhole of a neighboring rotor steel plate and formed by a pinhole process included in the auxiliary process, and a bolt hole, aligned with a bolt hole of a neighboring rotor steel plate and formed by a bolt hole process included in the auxiliary process. 13. The permanent magnet embedded rotating electrical machine according to claim 5, wherein for each of the rotor steel plates, the structure formed by the auxiliary process is any one or more of:
a V-shaped projection portion, aligned with a V-shaped projection portion of a neighboring rotor steel plate and formed by a V-shape process included in the auxiliary process, a boss projection portion, aligned with a boss projection of a neighboring rotor steel plate and formed by a boss process included in the auxiliary process, a pinhole, aligned with a pinhole of a neighboring rotor steel plate and formed by a pinhole process included in the auxiliary process, and a bolt hole, aligned with a bolt hole of a neighboring rotor steel plate and formed by a bolt hole process included in the auxiliary process. 14. The permanent magnet embedded rotating electrical machine according to claim 6, wherein for each of the rotor steel plates, the structure formed by the auxiliary process is any one or more of:
a V-shaped projection portion, aligned with a V-shaped projection portion of a neighboring rotor steel plate and formed by a V-shape process included in the auxiliary process, a boss projection portion, aligned with a boss projection of a neighboring rotor steel plate and formed by a boss process included in the auxiliary process, a pinhole, aligned with a pinhole of a neighboring rotor steel plate and formed by a pinhole process included in the auxiliary process, and a bolt hole, aligned with a bolt hole of a neighboring rotor steel plate and formed by a bolt hole process included in the auxiliary process. 15. The permanent magnet embedded rotating electrical machine according to claim 7, wherein for each of the rotor steel plates, the structure formed by the auxiliary process is any one or more of:
a V-shaped projection portion, aligned with a V-shaped projection portion of a neighboring rotor steel plate and formed by a V-shape process included in the auxiliary process, a boss projection portion, aligned with a boss projection of a neighboring rotor steel plate and formed by a boss process included in the auxiliary process, a pinhole, aligned with a pinhole of a neighboring rotor steel plate and formed by a pinhole process included in the auxiliary process, and a bolt hole, aligned with a bolt hole of a neighboring rotor steel plate and formed by a bolt hole process included in the auxiliary process. 16. The permanent magnet embedded rotating electrical machine according to claim 8, wherein for each of the rotor steel plates, the structure formed by the auxiliary process is any one or more of:
a V-shaped projection portion, aligned with a V-shaped projection portion of a neighboring rotor steel plate and formed by a V-shape process included in the auxiliary process, a boss projection portion, aligned with a boss projection of a neighboring rotor steel plate and formed by a boss process included in the auxiliary process, a pinhole, aligned with a pinhole of a neighboring rotor steel plate and formed by a pinhole process included in the auxiliary process, and a bolt hole, aligned with a bolt hole of a neighboring rotor steel plate and formed by a bolt hole process included in the auxiliary process. | 2,800 |
11,929 | 11,929 | 15,824,816 | 2,835 | Carriers may be adapted, or configured, to allow devices received thereby to move towards and away from an interface end region. When devices are positioned proximate the interface end region of the carriers, interfaces of the devices may be presented by the carriers for operable coupling to an enclosure. When devices are positioned away from the interface end region of the carriers, interface adapters may be coupled to the interfaces of the devices, which may present a different interface for operable coupling to an enclosure. | 1. A carrier comprising:
a first side rail and a second side rail spaced apart from the first side rail to receive a device therebetween, the first and second side rails extending from a forward end region to an interface end region; and a first movable portion movably coupled to the first side rail and a second movable portion movably coupled to the second side rail, the first and second movable portions couplable to the device to allow the device to move towards or away from the interface end region. 2. The carrier of claim 1, wherein the first and second movable portions are toollessly couplable to the device. 3. The carrier of claim 2, wherein each of the first and second movable portions comprise a device connection post to be inserted into a corresponding opening in the device to facilitate the toolless coupling of the first and second movable portions to the device. 4. The carrier of claim 1, wherein the first and second movable portions are movably coupled to the first and second side rails to allow the device to move between at least a device interface position and an adapter interface position, wherein, when in the device interface position, a device interface of the device is positioned proximate the interface region to allow operable coupling of the device interface to a corresponding interface of an enclosure that receives the carrier, wherein, when in the adapter interface position, the device interface is positioned apart from the interface region to allow an interface adapter be positioned between the device and the interface region. 5. The carrier of claim 4, wherein the first side rail comprises a restriction tab to restrict the movement of first movable portion between the device interface position and the adapter interface position. 6. The carrier of claim 5, wherein the first movable portion comprises a deflectable tab to abut the restriction tab to restrict the movement of first movable portion between the device interface position and the adapter interface position, wherein the deflectable tab is deflectable to release the first movable portion from being restricted by the restriction tab of the first side rail. 7. The carrier of claim 1, wherein the first and second side rails extend parallel to a carrier axis, wherein the first and second movable portions move in directions toward and away from the interface end region that are parallel to the carrier axis. 8. The carrier of claim 1, wherein the first side rail defines a slot to receive a portion of the first movable portion, wherein the first movable portion slides along the slot when allowing the device to move towards or away from the interface end region. 9. The carrier of claim 1 further comprises:
a forward portion coupled to the forward end regions of the first and second side rails; and
an interface portion coupled to the interface end regions of the first and second side rails, wherein the interface portion defines an interface opening for one of a device interface of the device coupled to the first and second movable portions and an adapter interface of an interface adapter positioned between the device coupled to the first and second movable portions and the interface end region. 10. A system comprising:
a carrier to receive a device and extending from a forward end region to an interface region, the interface region comprising one or more interface adapter supports to receive an interface adapter; and a plurality of different interface adapters to adapt a device interface of the device to an adapter interface different than the device interface, each of the interface adapters positionable between the device and the interface region to allow operable coupling of the adapter interface to a corresponding interface of an enclosure that receives the carrier. 11. The system of claim 10, wherein the interface adapter to is toollessly couplable to the carrier using the one or more interface adapter supports. 12. The system of claim 10, wherein at least one of the plurality of different interface adapters adapts a single-ported SATA drive interface to a dual-ported SAS interface. 13. The system of claim 10, wherein the carrier comprises one or more movable portions couplable to the device to allow the device to move between at least a device interface position and an adapter interface position, wherein, when in the device interface position, the device interface is positioned proximate the interface region to allow operable coupling of the device interface to a corresponding interface of an enclosure that receives the carrier, wherein, when in the adapter interface position, the device interface is positioned apart from the interface region to allow an interface adapter to be positioned between the device and the interface region. 14. The system of claim 13, wherein the carrier further comprises a first side rail and a second side rail spaced apart from the first side rail to receive the device therebetween, wherein the first and second side rails extend from the forward end region to the interface end region, wherein each of the one or more movable portions are movably coupled to one of the first and second side rails to allow the device to move towards or away from the interface end region. 15. Apparatus comprising:
a first side rail and a second side rail spaced apart from the first side rail to toollessly receive a device therebetween, the first and second side rails extending from a forward end region to an interface end region, the first and second side rails allowing the device to move between at least a device interface position and an adapter interface position, when in the device interface position, the device interface is positioned proximate the interface region to allow operable coupling of the device interface to a corresponding interface of an enclosure that receives the carrier, when in the adapter interface position, the device interface is positioned apart from the interface region to allow an interface adapter to be positioned between the device and the interface region. 16. The apparatus of claim 15 further comprising an interface portion coupled to the interface end regions of the first and second side rails, wherein the interface portion defines an interface opening for one of a device interface of the device received by the first and second side rails and an adapter interface of an interface adapter positioned between the device received by the first and second side rails and the interface end region. 17. The apparatus of claim 15 further comprising at least one movable portion movably coupled to one of the first and second side rails and toollessly coupled to the device to allow the device to move towards or away from the interface end region. 18. The apparatus of claim 17, wherein the at least one movable portion comprises a device connection post to be inserted into a corresponding opening in the device to facilitate the toolless coupling of the at least one movable portion to the device. 19. The apparatus of claim 17, wherein the at least one movable portion comprises a deflectable tab to abut a portion of the first or second side rail to restrict the movement of the at least one movable portion between the device interface position and the adapter interface position, wherein the deflectable tab is deflectable to release the at least one movable portion from being restricted by the first or second side rail. 20. The apparatus of claim 15, wherein the first and second side rails extend parallel to a carrier axis, wherein the device is movable in directions toward and away from the interface end region that are parallel to the carrier axis. | Carriers may be adapted, or configured, to allow devices received thereby to move towards and away from an interface end region. When devices are positioned proximate the interface end region of the carriers, interfaces of the devices may be presented by the carriers for operable coupling to an enclosure. When devices are positioned away from the interface end region of the carriers, interface adapters may be coupled to the interfaces of the devices, which may present a different interface for operable coupling to an enclosure.1. A carrier comprising:
a first side rail and a second side rail spaced apart from the first side rail to receive a device therebetween, the first and second side rails extending from a forward end region to an interface end region; and a first movable portion movably coupled to the first side rail and a second movable portion movably coupled to the second side rail, the first and second movable portions couplable to the device to allow the device to move towards or away from the interface end region. 2. The carrier of claim 1, wherein the first and second movable portions are toollessly couplable to the device. 3. The carrier of claim 2, wherein each of the first and second movable portions comprise a device connection post to be inserted into a corresponding opening in the device to facilitate the toolless coupling of the first and second movable portions to the device. 4. The carrier of claim 1, wherein the first and second movable portions are movably coupled to the first and second side rails to allow the device to move between at least a device interface position and an adapter interface position, wherein, when in the device interface position, a device interface of the device is positioned proximate the interface region to allow operable coupling of the device interface to a corresponding interface of an enclosure that receives the carrier, wherein, when in the adapter interface position, the device interface is positioned apart from the interface region to allow an interface adapter be positioned between the device and the interface region. 5. The carrier of claim 4, wherein the first side rail comprises a restriction tab to restrict the movement of first movable portion between the device interface position and the adapter interface position. 6. The carrier of claim 5, wherein the first movable portion comprises a deflectable tab to abut the restriction tab to restrict the movement of first movable portion between the device interface position and the adapter interface position, wherein the deflectable tab is deflectable to release the first movable portion from being restricted by the restriction tab of the first side rail. 7. The carrier of claim 1, wherein the first and second side rails extend parallel to a carrier axis, wherein the first and second movable portions move in directions toward and away from the interface end region that are parallel to the carrier axis. 8. The carrier of claim 1, wherein the first side rail defines a slot to receive a portion of the first movable portion, wherein the first movable portion slides along the slot when allowing the device to move towards or away from the interface end region. 9. The carrier of claim 1 further comprises:
a forward portion coupled to the forward end regions of the first and second side rails; and
an interface portion coupled to the interface end regions of the first and second side rails, wherein the interface portion defines an interface opening for one of a device interface of the device coupled to the first and second movable portions and an adapter interface of an interface adapter positioned between the device coupled to the first and second movable portions and the interface end region. 10. A system comprising:
a carrier to receive a device and extending from a forward end region to an interface region, the interface region comprising one or more interface adapter supports to receive an interface adapter; and a plurality of different interface adapters to adapt a device interface of the device to an adapter interface different than the device interface, each of the interface adapters positionable between the device and the interface region to allow operable coupling of the adapter interface to a corresponding interface of an enclosure that receives the carrier. 11. The system of claim 10, wherein the interface adapter to is toollessly couplable to the carrier using the one or more interface adapter supports. 12. The system of claim 10, wherein at least one of the plurality of different interface adapters adapts a single-ported SATA drive interface to a dual-ported SAS interface. 13. The system of claim 10, wherein the carrier comprises one or more movable portions couplable to the device to allow the device to move between at least a device interface position and an adapter interface position, wherein, when in the device interface position, the device interface is positioned proximate the interface region to allow operable coupling of the device interface to a corresponding interface of an enclosure that receives the carrier, wherein, when in the adapter interface position, the device interface is positioned apart from the interface region to allow an interface adapter to be positioned between the device and the interface region. 14. The system of claim 13, wherein the carrier further comprises a first side rail and a second side rail spaced apart from the first side rail to receive the device therebetween, wherein the first and second side rails extend from the forward end region to the interface end region, wherein each of the one or more movable portions are movably coupled to one of the first and second side rails to allow the device to move towards or away from the interface end region. 15. Apparatus comprising:
a first side rail and a second side rail spaced apart from the first side rail to toollessly receive a device therebetween, the first and second side rails extending from a forward end region to an interface end region, the first and second side rails allowing the device to move between at least a device interface position and an adapter interface position, when in the device interface position, the device interface is positioned proximate the interface region to allow operable coupling of the device interface to a corresponding interface of an enclosure that receives the carrier, when in the adapter interface position, the device interface is positioned apart from the interface region to allow an interface adapter to be positioned between the device and the interface region. 16. The apparatus of claim 15 further comprising an interface portion coupled to the interface end regions of the first and second side rails, wherein the interface portion defines an interface opening for one of a device interface of the device received by the first and second side rails and an adapter interface of an interface adapter positioned between the device received by the first and second side rails and the interface end region. 17. The apparatus of claim 15 further comprising at least one movable portion movably coupled to one of the first and second side rails and toollessly coupled to the device to allow the device to move towards or away from the interface end region. 18. The apparatus of claim 17, wherein the at least one movable portion comprises a device connection post to be inserted into a corresponding opening in the device to facilitate the toolless coupling of the at least one movable portion to the device. 19. The apparatus of claim 17, wherein the at least one movable portion comprises a deflectable tab to abut a portion of the first or second side rail to restrict the movement of the at least one movable portion between the device interface position and the adapter interface position, wherein the deflectable tab is deflectable to release the at least one movable portion from being restricted by the first or second side rail. 20. The apparatus of claim 15, wherein the first and second side rails extend parallel to a carrier axis, wherein the device is movable in directions toward and away from the interface end region that are parallel to the carrier axis. | 2,800 |
11,930 | 11,930 | 15,674,266 | 2,894 | A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls, The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer. | 1. An integrated circuit comprising:
a silicon oxide liner film in contact with annealed source/drain regions and a gate electrode of a transistor; and a cap layer comprising silicon and nitrogen in contact with said silicon oxide liner film; wherein said cap layer contains an electrically neutral species. 2. integrated circuit of claim 1 wherein said electrically neutral species comprises Ar. 3. The integrated circuit of claim 1 wherein said electrically neutral species comprises Sb. 4. The integrated circuit of claim 1 wherein said cap layer also contains another electrically neutral species. 5. An integrated circuit comprising:
a silicon oxide liner film in contact with annealed source/drain regions and a gate electrode of a transistor; and a cap layer comprising silicon and carbon in contact with said silicon oxide liner film; wherein said cap layer contains an electrically neutral species. 6. The integrated circuit of claim 5 wherein said electrically neutral species comprises Ar. 7. The integrated circuit of claim 5 wherein said electrically neutral species comprises Sb. 6. The integrated circuit of claim 5 wherein said cap layer also contains another electrically neutral species. 9. An integrated circuit comprising:
a cap layer comprising silicon and nitrogen in contact with unannealed source/drain regions and a gate electrode of a transistor; wherein said cap layer contains an electrically neutral species. 9. An integrated circuit of claim 9 wherein said electrically neutral species comprises Ar. 11. An integrated circuit comprising:
a cap layer comprising silicon and carbon in contact with unannealed source/drain regions and a gate electrode of a transistor; wherein said cap layer contains an electrically neutral species. 12. The integrated circuit of claim 11 wherein said electrically neutral species comprises Ar. | A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls, The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.1. An integrated circuit comprising:
a silicon oxide liner film in contact with annealed source/drain regions and a gate electrode of a transistor; and a cap layer comprising silicon and nitrogen in contact with said silicon oxide liner film; wherein said cap layer contains an electrically neutral species. 2. integrated circuit of claim 1 wherein said electrically neutral species comprises Ar. 3. The integrated circuit of claim 1 wherein said electrically neutral species comprises Sb. 4. The integrated circuit of claim 1 wherein said cap layer also contains another electrically neutral species. 5. An integrated circuit comprising:
a silicon oxide liner film in contact with annealed source/drain regions and a gate electrode of a transistor; and a cap layer comprising silicon and carbon in contact with said silicon oxide liner film; wherein said cap layer contains an electrically neutral species. 6. The integrated circuit of claim 5 wherein said electrically neutral species comprises Ar. 7. The integrated circuit of claim 5 wherein said electrically neutral species comprises Sb. 6. The integrated circuit of claim 5 wherein said cap layer also contains another electrically neutral species. 9. An integrated circuit comprising:
a cap layer comprising silicon and nitrogen in contact with unannealed source/drain regions and a gate electrode of a transistor; wherein said cap layer contains an electrically neutral species. 9. An integrated circuit of claim 9 wherein said electrically neutral species comprises Ar. 11. An integrated circuit comprising:
a cap layer comprising silicon and carbon in contact with unannealed source/drain regions and a gate electrode of a transistor; wherein said cap layer contains an electrically neutral species. 12. The integrated circuit of claim 11 wherein said electrically neutral species comprises Ar. | 2,800 |
11,931 | 11,931 | 14,516,802 | 2,834 | A stator for a rotating electric machine includes an annular stator core, a stator coil and a resin adhesive. The stator coil is formed of a plurality of electric wires that are mounted on the stator core so as to be received in slots of the stator core. The resin adhesive is filled in the slots of the stator core to fix the electric wires in the slots. Each of the electric wires forming the stator coil includes an electric conductor and an insulating coat that covers an outer surface of the electric conductor. The insulating coat is two-layer structured to include an inner coat and an outer coat that is formed outside the inner coat. The coefficient of linear expansion of the outer coat is higher than the coefficient of linear expansion of the inner coat and lower than the coefficient of linear expansion of the resin adhesive. | 1. A stator for a rotating electric machine, the stator comprising:
an annular stator core having a plurality of slots formed therein, the slots being spaced from one another in a circumferential direction of the stator core; a stator coil formed of a plurality of electric wires that are mounted on the stator core so as to be received in the slots of the stator core; and a resin adhesive that is filled in the slots of the stator core to fix the electric wires in the slots, wherein each of the electric wires forming the stator coil includes an electric conductor and an insulating coat that covers an outer surface of the electric conductor, the insulating coat is two-layer structured to include an inner coat and an outer coat that is formed outside the inner coat, and a coefficient of linear expansion of the outer coat is higher than a coefficient of linear expansion of the inner coat and lower than a coefficient of linear expansion of the resin adhesive. 2. The stator as set forth in claim 1, wherein the electric wires forming the stator coil are partially received in the slots of the stator core so that the stator coil has a pair of coil end parts protruding outside the slots respectively from opposite axial end faces of the stator core, and
the resin adhesive is also applied to the coil end parts of the stator end. 3. The stator as set forth in claim 1, wherein each of the electric wires forming the stator coil is comprised of a predetermined number of electric wire segments,
each of the electric wire segments is substantially U-shaped to have a pair of straight portions extending parallel to each other and a turn portion connecting ends of the straight portions on the same side. the straight portions are respectively inserted in a corresponding pair of the slots of the stator core, with the turn portion located outside the corresponding slots on a first axial side of the stator core and free end parts of the straight portions respectively protruding outside the corresponding slots on a second axial side of the stator core, the free end parts of the straight portions are bent to form a pair of oblique portions of the electric wire segment, the oblique portions extending toward opposite circumferential sides and obliquely at a predetermined angle with respect to an axial end face of the stator core, and corresponding ends of the oblique portions of the electric wire segments are joined and thus electrically connected to one another. 4. The stator as set forth in claim 1, wherein each of the turn portions of the electric wire segments is stair-shaped to include a plurality of step portions that extend parallel to the axial end face of the stator core and are spaced from one another in an axial direction of the stator core. 5. The stator as set forth in claim 1, wherein each of the electric wires forming the stator coil is a continuous electric wire which includes a plurality of in-slot portions and a plurality of turn portions, the in-slot portions extending parallel to each other and being respectively received in corresponding ones of the slots of the stator core, the turn portions connecting adjacent in-slot portions alternately on opposite axial sides of the stator core. 6. The stator as set forth in claim 5, wherein each of the turn portions of the electric wires is stair-shaped to include a plurality of step portions that extend parallel to an axial end face of the stator core and are spaced from one another in an axial direction of the stator core. 7. A rotating electric machine comprising:
the stator as set forth in claim 1; a rotor that is rotatably disposed in radial opposition to the stator; and a coolant supplier configured to supply liquid coolant to the stator. 8. The rotating electric machine as set forth in claim 7, wherein the electric wires forming the stator coil are partially received in the slots of the stator core so that the stator coil has a pair of coil end parts protruding outside the slots respectively from opposite axial end faces of the stator core, and
the coolant supplier is configured to supply the liquid coolant to the coil end parts of the stator coil. 9. The rotating electric machine as set forth in claim 7, further comprising a housing which receives the stator therein so that the stator core is in intact with the housing, wherein the coolant supplier is configured to supply cooling water, which is the liquid coolant, to a coolant passage formed in the housing, thereby cooling the stator core. | A stator for a rotating electric machine includes an annular stator core, a stator coil and a resin adhesive. The stator coil is formed of a plurality of electric wires that are mounted on the stator core so as to be received in slots of the stator core. The resin adhesive is filled in the slots of the stator core to fix the electric wires in the slots. Each of the electric wires forming the stator coil includes an electric conductor and an insulating coat that covers an outer surface of the electric conductor. The insulating coat is two-layer structured to include an inner coat and an outer coat that is formed outside the inner coat. The coefficient of linear expansion of the outer coat is higher than the coefficient of linear expansion of the inner coat and lower than the coefficient of linear expansion of the resin adhesive.1. A stator for a rotating electric machine, the stator comprising:
an annular stator core having a plurality of slots formed therein, the slots being spaced from one another in a circumferential direction of the stator core; a stator coil formed of a plurality of electric wires that are mounted on the stator core so as to be received in the slots of the stator core; and a resin adhesive that is filled in the slots of the stator core to fix the electric wires in the slots, wherein each of the electric wires forming the stator coil includes an electric conductor and an insulating coat that covers an outer surface of the electric conductor, the insulating coat is two-layer structured to include an inner coat and an outer coat that is formed outside the inner coat, and a coefficient of linear expansion of the outer coat is higher than a coefficient of linear expansion of the inner coat and lower than a coefficient of linear expansion of the resin adhesive. 2. The stator as set forth in claim 1, wherein the electric wires forming the stator coil are partially received in the slots of the stator core so that the stator coil has a pair of coil end parts protruding outside the slots respectively from opposite axial end faces of the stator core, and
the resin adhesive is also applied to the coil end parts of the stator end. 3. The stator as set forth in claim 1, wherein each of the electric wires forming the stator coil is comprised of a predetermined number of electric wire segments,
each of the electric wire segments is substantially U-shaped to have a pair of straight portions extending parallel to each other and a turn portion connecting ends of the straight portions on the same side. the straight portions are respectively inserted in a corresponding pair of the slots of the stator core, with the turn portion located outside the corresponding slots on a first axial side of the stator core and free end parts of the straight portions respectively protruding outside the corresponding slots on a second axial side of the stator core, the free end parts of the straight portions are bent to form a pair of oblique portions of the electric wire segment, the oblique portions extending toward opposite circumferential sides and obliquely at a predetermined angle with respect to an axial end face of the stator core, and corresponding ends of the oblique portions of the electric wire segments are joined and thus electrically connected to one another. 4. The stator as set forth in claim 1, wherein each of the turn portions of the electric wire segments is stair-shaped to include a plurality of step portions that extend parallel to the axial end face of the stator core and are spaced from one another in an axial direction of the stator core. 5. The stator as set forth in claim 1, wherein each of the electric wires forming the stator coil is a continuous electric wire which includes a plurality of in-slot portions and a plurality of turn portions, the in-slot portions extending parallel to each other and being respectively received in corresponding ones of the slots of the stator core, the turn portions connecting adjacent in-slot portions alternately on opposite axial sides of the stator core. 6. The stator as set forth in claim 5, wherein each of the turn portions of the electric wires is stair-shaped to include a plurality of step portions that extend parallel to an axial end face of the stator core and are spaced from one another in an axial direction of the stator core. 7. A rotating electric machine comprising:
the stator as set forth in claim 1; a rotor that is rotatably disposed in radial opposition to the stator; and a coolant supplier configured to supply liquid coolant to the stator. 8. The rotating electric machine as set forth in claim 7, wherein the electric wires forming the stator coil are partially received in the slots of the stator core so that the stator coil has a pair of coil end parts protruding outside the slots respectively from opposite axial end faces of the stator core, and
the coolant supplier is configured to supply the liquid coolant to the coil end parts of the stator coil. 9. The rotating electric machine as set forth in claim 7, further comprising a housing which receives the stator therein so that the stator core is in intact with the housing, wherein the coolant supplier is configured to supply cooling water, which is the liquid coolant, to a coolant passage formed in the housing, thereby cooling the stator core. | 2,800 |
11,932 | 11,932 | 15,532,253 | 2,844 | Systems, and methods are described herein for identifying and/or controlling influence and/or potential influence of one or more signals on one or more properties of light emitted by one or more lighting units ( 100 ). In various embodiments, one or more signals may be identified that influence, or potentially influence, a manner in which a lighting unit controller ( 110 ) controls one or more properties of light to be emitted by a lighting unit ( 100 ). In some embodiments, a user instruction may be received to alter the manner in which the one or more signals influence how the lighting unit controller ( 110 ) controls the one or more properties of light emitted by the lighting unit ( 100 ) may be received. The lighting unit controller ( 110 ) may control a manner in which light output of the lighting unit ( 100 ) is influenced by the one or more signals in accordance with the user instruction. | 1. A computing device comprising:
one or more processors; a wireless communication interface operably coupled with the one or more processors; and memory operably coupled with the one or more processors, the memory storing instructions that, in response to execution of the instructions by the one or more processors, cause the one or more processors to: receive, from a lighting unit controller over the wireless communication interface, data indicative of one or more signals obtainable by the lighting unit controller that influence, or potentially influence, a manner in which the lighting unit controller controls one or more properties of light to be emitted by a lighting unit; and display a visual representation of the one or more signals and a manner in which the one or more signals influence, or potentially influence, the manner in which the lighting unit controller controls one or more properties of light emitted by the lighting unit; and
obtain, from the lighting unit, an identifier associated with the lighting unit controller; and establish communication with the lighting unit controller via the wireless communication interface based on the identifier. 2. The computing device of claim 1, further comprising a user input, wherein the memory further stores instructions that, in response to execution of the instructions by the one or more processors, cause the one or more processors to:
receive, at the user input, a user instruction to alter the manner in which the one or more signals influence how the lighting unit controller controls the one or more properties of light emitted by the lighting unit; and transmit, via the wireless communication interface to the lighting unit controller, an indication of the user instruction. 3. The computing device of claim 2, wherein the user input comprises a touch screen, and the memory further stores instructions that, in response to execution of the instructions by the one or more processors, cause the one or more processors to render, on the touch screen, a user interface operable to alter the manner in which the one or more signals influence the one or more properties of light emitted by the lighting unit. 4. The computing device of claim 3, wherein the memory further stores instructions that, in response to execution of the instructions by the one or more processors, cause the one or more processors to render an indication of relative priorities of influence by the one or more signals. 5. The computing device of claim 4, wherein the memory further stores instructions that, in response to execution of the instructions by the one or more processors, cause the one or more processors to render one or more graphical elements that are operable by a user to alter the relative priorities of influence by the one or more signals. 6. (canceled) 7. (canceled) 8. The computing device of claim 1, wherein the memory further stores instructions that, in response to execution of the instructions by the one or more processors, cause the one or more processors to extract the identifier associated with the lighting unit controller from coded light emitted by the lighting unit. 9. (canceled) 10. The computing device of claim 1, wherein the memory further stores instructions that, in response to execution of the instructions by the one or more processors, cause the one or more processors to extract the identifier associated with the lighting unit controller from a radio signal emitted by the lighting unit. 11. The computing device of claim 1, wherein the one or more signals include a service or application operating on one or more remote computing devices. 12. (canceled) 13. (canceled) 14. The computing device of claim 1, wherein the one or more signals include one or more rules associated with a lighting system of which the lighting unit is a member. 15. (canceled) 16. (canceled) 17. The computing device of claim 1, wherein the memory further stores instructions that, in response to execution of the instructions by the one or more processors, cause the one or more processors to ascertain one or more signals that have previously influenced how the lighting unit controller controlled, or will influence in the future how the lighting unit controller controls, one or more properties of light emitted by the lighting unit. 18. A lighting unit controller that controls one or more lighting units the lighting unit controller comprising:
a processor configured to: establish a communication with a mobile computing device according to claim 1; determine, one or more signals, external to the lighting unit controller and one or more lighting units controlled by the lighting unit controller, that influence, or potentially influence, how the lighting unit controller controls one or more properties of light to be emitted by the one or more lighting units; and make available data indicative of the one or more signals. 19. The lighting unit controller of claim 18, wherein the processor further configured to alter a manner in which the one or more signals influence how the lighting unit controller controls the one or more properties of light emitted by the lighting unit in accordance with a user instruction. 20. The lighting unit controller of claim 19, wherein the altering comprises:
generating one or more lighting control commands based at least in part on the user instruction; and transmitting the one or more lighting control commands to the lighting unit. 21. The lighting unit controller of claim 20, wherein the generating comprises:
no longer taking into account at least one signal that previously influenced the manner in which the one or more signals influence how the lighting unit controller controls the one or more properties of light emitted by the lighting unit; or taking into account at least one new signal that did not previously influence the manner in which the one or more signals influence how the lighting unit controller controls the one or more properties of light emitted by the lighting unit. 22. The lighting unit controller of claim 19, wherein the altering comprises altering the manner in which a first signal influences a manner in which the lighting unit controller controls a particular property of light emitted by the lighting unit relative to a second signal. | Systems, and methods are described herein for identifying and/or controlling influence and/or potential influence of one or more signals on one or more properties of light emitted by one or more lighting units ( 100 ). In various embodiments, one or more signals may be identified that influence, or potentially influence, a manner in which a lighting unit controller ( 110 ) controls one or more properties of light to be emitted by a lighting unit ( 100 ). In some embodiments, a user instruction may be received to alter the manner in which the one or more signals influence how the lighting unit controller ( 110 ) controls the one or more properties of light emitted by the lighting unit ( 100 ) may be received. The lighting unit controller ( 110 ) may control a manner in which light output of the lighting unit ( 100 ) is influenced by the one or more signals in accordance with the user instruction.1. A computing device comprising:
one or more processors; a wireless communication interface operably coupled with the one or more processors; and memory operably coupled with the one or more processors, the memory storing instructions that, in response to execution of the instructions by the one or more processors, cause the one or more processors to: receive, from a lighting unit controller over the wireless communication interface, data indicative of one or more signals obtainable by the lighting unit controller that influence, or potentially influence, a manner in which the lighting unit controller controls one or more properties of light to be emitted by a lighting unit; and display a visual representation of the one or more signals and a manner in which the one or more signals influence, or potentially influence, the manner in which the lighting unit controller controls one or more properties of light emitted by the lighting unit; and
obtain, from the lighting unit, an identifier associated with the lighting unit controller; and establish communication with the lighting unit controller via the wireless communication interface based on the identifier. 2. The computing device of claim 1, further comprising a user input, wherein the memory further stores instructions that, in response to execution of the instructions by the one or more processors, cause the one or more processors to:
receive, at the user input, a user instruction to alter the manner in which the one or more signals influence how the lighting unit controller controls the one or more properties of light emitted by the lighting unit; and transmit, via the wireless communication interface to the lighting unit controller, an indication of the user instruction. 3. The computing device of claim 2, wherein the user input comprises a touch screen, and the memory further stores instructions that, in response to execution of the instructions by the one or more processors, cause the one or more processors to render, on the touch screen, a user interface operable to alter the manner in which the one or more signals influence the one or more properties of light emitted by the lighting unit. 4. The computing device of claim 3, wherein the memory further stores instructions that, in response to execution of the instructions by the one or more processors, cause the one or more processors to render an indication of relative priorities of influence by the one or more signals. 5. The computing device of claim 4, wherein the memory further stores instructions that, in response to execution of the instructions by the one or more processors, cause the one or more processors to render one or more graphical elements that are operable by a user to alter the relative priorities of influence by the one or more signals. 6. (canceled) 7. (canceled) 8. The computing device of claim 1, wherein the memory further stores instructions that, in response to execution of the instructions by the one or more processors, cause the one or more processors to extract the identifier associated with the lighting unit controller from coded light emitted by the lighting unit. 9. (canceled) 10. The computing device of claim 1, wherein the memory further stores instructions that, in response to execution of the instructions by the one or more processors, cause the one or more processors to extract the identifier associated with the lighting unit controller from a radio signal emitted by the lighting unit. 11. The computing device of claim 1, wherein the one or more signals include a service or application operating on one or more remote computing devices. 12. (canceled) 13. (canceled) 14. The computing device of claim 1, wherein the one or more signals include one or more rules associated with a lighting system of which the lighting unit is a member. 15. (canceled) 16. (canceled) 17. The computing device of claim 1, wherein the memory further stores instructions that, in response to execution of the instructions by the one or more processors, cause the one or more processors to ascertain one or more signals that have previously influenced how the lighting unit controller controlled, or will influence in the future how the lighting unit controller controls, one or more properties of light emitted by the lighting unit. 18. A lighting unit controller that controls one or more lighting units the lighting unit controller comprising:
a processor configured to: establish a communication with a mobile computing device according to claim 1; determine, one or more signals, external to the lighting unit controller and one or more lighting units controlled by the lighting unit controller, that influence, or potentially influence, how the lighting unit controller controls one or more properties of light to be emitted by the one or more lighting units; and make available data indicative of the one or more signals. 19. The lighting unit controller of claim 18, wherein the processor further configured to alter a manner in which the one or more signals influence how the lighting unit controller controls the one or more properties of light emitted by the lighting unit in accordance with a user instruction. 20. The lighting unit controller of claim 19, wherein the altering comprises:
generating one or more lighting control commands based at least in part on the user instruction; and transmitting the one or more lighting control commands to the lighting unit. 21. The lighting unit controller of claim 20, wherein the generating comprises:
no longer taking into account at least one signal that previously influenced the manner in which the one or more signals influence how the lighting unit controller controls the one or more properties of light emitted by the lighting unit; or taking into account at least one new signal that did not previously influence the manner in which the one or more signals influence how the lighting unit controller controls the one or more properties of light emitted by the lighting unit. 22. The lighting unit controller of claim 19, wherein the altering comprises altering the manner in which a first signal influences a manner in which the lighting unit controller controls a particular property of light emitted by the lighting unit relative to a second signal. | 2,800 |
11,933 | 11,933 | 15,911,350 | 2,827 | An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed. | 1. An electronic processing system, comprising:
a processor; multi-level memory communicatively coupled to the processor; an analog-to-digital converter communicatively coupled to the multi-level memory to convert an analog voltage level of a memory cell of the multi-level memory to a corresponding multi-bit digital value; and logic communicatively coupled to the multi-level memory and the analog-to-digital converter to determine a single-bit value of the memory cell based on the multi-bit digital value. 2. The system of claim 1, wherein the logic is further to:
apply error correction to determine the value of the memory cell based on the multi-bit digital value. 3. The system of claim 1, wherein the logic is further to:
track a history of accesses to the memory cell. 4. The system of claim 3, wherein the logic is further to:
track a temporal history of accesses to the memory cell for a duration in excess of ten seconds. 5. The system of claim 4, wherein the logic is further to:
determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history of accesses to the memory cell. 6. The system of claim 1, wherein the multi-level memory comprises a phase change memory. 7. The system of claim 6, wherein the phase change memory comprises a three dimensional crosspoint memory. 8. A semiconductor apparatus, comprising:
one or more substrates; and logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and
determine a single-bit value of the memory cell based on the multi-bit digital value. 9. The apparatus of claim 8, wherein the logic is further to:
apply error correction to determine the value of the memory cell based on the multi-bit digital value. 10. The apparatus of claim 8, wherein the logic is further to:
track a history of accesses to the memory cell. 11. The apparatus of claim 10, wherein the logic is further to:
track a temporal history of accesses to the memory cell for a duration in excess of ten seconds. 12. The apparatus of claim 11, wherein the logic is further to:
determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history of accesses to the memory cell. 13. The apparatus of claim 8, wherein the multi-level memory comprises a phase change memory. 14. The apparatus of claim 13, wherein the phase change memory comprises a three dimensional crosspoint memory. 15. The apparatus of claim 8, wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates. 16. A method of determining a memory value, comprising:
converting an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value; and determining a single-bit value of the memory cell based on the multi-bit digital value. 17. The method of claim 16, further comprising:
applying error correction to determine the value of the memory cell based on the multi-bit digital value. 18. The method of claim 16, further comprising:
tracking a history of accesses to the memory cell. 19. The method of claim 18, further comprising:
tracking a temporal history of accesses to the memory cell for a duration in excess of ten seconds. 20. The method of claim 19, further comprising:
determining the single-bit value of the memory cell based on the multi-bit digital value and the temporal history of accesses to the memory cell. 21. The method of claim 16, wherein the multi-level memory comprises a phase change memory. 22. The method of claim 21, wherein the phase change memory comprises a three dimensional crosspoint memory. | An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.1. An electronic processing system, comprising:
a processor; multi-level memory communicatively coupled to the processor; an analog-to-digital converter communicatively coupled to the multi-level memory to convert an analog voltage level of a memory cell of the multi-level memory to a corresponding multi-bit digital value; and logic communicatively coupled to the multi-level memory and the analog-to-digital converter to determine a single-bit value of the memory cell based on the multi-bit digital value. 2. The system of claim 1, wherein the logic is further to:
apply error correction to determine the value of the memory cell based on the multi-bit digital value. 3. The system of claim 1, wherein the logic is further to:
track a history of accesses to the memory cell. 4. The system of claim 3, wherein the logic is further to:
track a temporal history of accesses to the memory cell for a duration in excess of ten seconds. 5. The system of claim 4, wherein the logic is further to:
determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history of accesses to the memory cell. 6. The system of claim 1, wherein the multi-level memory comprises a phase change memory. 7. The system of claim 6, wherein the phase change memory comprises a three dimensional crosspoint memory. 8. A semiconductor apparatus, comprising:
one or more substrates; and logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and
determine a single-bit value of the memory cell based on the multi-bit digital value. 9. The apparatus of claim 8, wherein the logic is further to:
apply error correction to determine the value of the memory cell based on the multi-bit digital value. 10. The apparatus of claim 8, wherein the logic is further to:
track a history of accesses to the memory cell. 11. The apparatus of claim 10, wherein the logic is further to:
track a temporal history of accesses to the memory cell for a duration in excess of ten seconds. 12. The apparatus of claim 11, wherein the logic is further to:
determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history of accesses to the memory cell. 13. The apparatus of claim 8, wherein the multi-level memory comprises a phase change memory. 14. The apparatus of claim 13, wherein the phase change memory comprises a three dimensional crosspoint memory. 15. The apparatus of claim 8, wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates. 16. A method of determining a memory value, comprising:
converting an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value; and determining a single-bit value of the memory cell based on the multi-bit digital value. 17. The method of claim 16, further comprising:
applying error correction to determine the value of the memory cell based on the multi-bit digital value. 18. The method of claim 16, further comprising:
tracking a history of accesses to the memory cell. 19. The method of claim 18, further comprising:
tracking a temporal history of accesses to the memory cell for a duration in excess of ten seconds. 20. The method of claim 19, further comprising:
determining the single-bit value of the memory cell based on the multi-bit digital value and the temporal history of accesses to the memory cell. 21. The method of claim 16, wherein the multi-level memory comprises a phase change memory. 22. The method of claim 21, wherein the phase change memory comprises a three dimensional crosspoint memory. | 2,800 |
11,934 | 11,934 | 14,653,227 | 2,862 | A method for determining a mass of fuel injected into an internal combustion engine cylinder provided with a pressure sensor, includes: determining the temperature prevailing in the cylinder and amount heat released from the measured pressure; integrating amounts of heat released over a predetermined time interval to determine a cumulative amount of heat; estimating the heat losses by taking into account heat losses due to radiation and which are dependent on the measured temperature to the fourth power, and heat losses due to conduction and/or convection and dependent on both the measured temperature and corresponding engine speed, according to the formula: QP=α HR CUM , where QP is the amount of heat corresponding to the heat losses, HR CUM is the cumulative amount of heat, a is a corrective factor; and determining the amount of fuel injected, which is proportional to the cumulative amount of heat added to the heat losses. | 1. A method for determining a mass of fuel injected into a cylinder of an internal combustion engine, said cylinder being equipped with a sensor able to detect the pressure predominating in the interior thereof, the method comprising the following steps:
determining, from the pressure measured, firstly the corresponding temperature prevailing in the cylinder and secondly the quantity of heat released, integrating the quantities of heat released over a predefined time interval in order to determine a cumulative quantity of heat, estimating heat losses by taking into account firstly the heat losses by radiation which are dependent on the measured temperature to the power of four, and secondly the heat losses by conduction and/or convection which are dependent both on the measured temperature and on the corresponding engine speed, according to the formula:
QP=α HRCUM
where:
QP is the quantity of heat corresponding to the heat losses,
HRCUM is said cumulative heat quantity,
α is a corrective factor for the cumulative heat quantity,
determining the amount of fuel injected which is proportional to the cumulative quantity of heat plus the heat losses. 2. The determination method as claimed in claim 1, wherein the temperature is calculated from the pressure by assuming that the ratio of the product of pressure and volume firstly and temperature secondly is constant. 3. The determination method as claimed in claim 1, wherein the quantities of heat released are integrated over a complete combustion cycle, i.e. over an interval of 720° for a four-stroke engine. 4. The determination method as claimed in claim 1, wherein the estimation of heat losses also takes into account the increase in the density of the gaseous flow before it enters the cylinder. 5. The determination method as claimed in claim 1, wherein the heat losses by radiation are estimated using the formula:
QR=B HRCUM (Tmax 4−TCO 4)/TCO 4
where:
QR is the quantity of heat dissipated by radiation,
B is a constant,
HRCUM is the cumulative heat quantity,
Tmax is the maximum temperature determined over the predefined time interval taken into account for determining the cumulative heat quantity,
TCO is the engine temperature. 6. The determination method as claimed in claim 1, wherein the heat losses by conduction and/or convection are estimated using the formula:
QC=f(N) HRCUM (Tmax−TCO)/TCO
where:
QC is the quantity of heat dissipated by conduction and/or convection,
f(N) is a function with variable N corresponding to the engine speed,
Tmax is the maximum temperature determined over the predefined time interval taken into account for determining the cumulative heat quantity,
TCO is the engine temperature. 7. The determination method as claimed in claim 4, wherein the heat losses are estimated using the formula:
QP=A HRCUM+QR+QC+C HRCUM Pin/Pamb
where:
QP is the quantity of heat corresponding to the heat losses,
A and C are constants,
Pin is the pressure of a gaseous flow immediately before it enters the cylinder,
Pamb is the ambient pressure,
in which formula, said corrective factor a for the cumulative heat quantity is entered as follows:
α=A+B (Tmax 4−TCO 4)/TCO 4+f(N) (Tmax−TCO)TCO+C Pin/Pamb. 8. A method for correcting the flow of fuel injected into an internal combustion engine, which comprises the following steps:
determination of the amount of fuel injected during a combustion cycle as claimed in claim 1, comparison of the amount of fuel determined in the previous step with a reference value corresponding to the amount of fuel to be injected during the same combustion cycle, and repetition of the previous steps of determination and comparison, use of the results of comparisons between the amounts of fuel determined by the method and reference amounts, in order to define a correction value to apply to a reference value corresponding to an amount of fuel to be injected. 9. A device for determining an amount of fuel injected into a cylinder of an internal combustion engine, said cylinder being equipped with a sensor giving knowledge of the pressure prevailing therein, the device comprising a computer containing means for implementing each of the steps of a method as claimed in claim 1. 10. The determination method as claimed in claim 2, wherein the quantities of heat released are integrated over a complete combustion cycle, i.e. over an interval of 720° for a four-stroke engine. 11. The determination method as claimed in claim 2, wherein the estimation of heat losses also takes into account the increase in the density of the gaseous flow before it enters the cylinder. 12. The determination method as claimed in claim 3, wherein the estimation of heat losses also takes into account the increase in the density of the gaseous flow before it enters the cylinder. 13. The determination method as claimed in claim 5, wherein the heat losses are estimated using the formula:
QP=A HRCUM+QR+QC+C HRCUM Pin/Pamb
where:
QP is the quantity of heat corresponding to the heat losses,
A and C are constants,
Pin is the pressure of a gaseous flow immediately before it enters the cylinder,
Pamb is the ambient pressure,
in which formula, said corrective factor a for the cumulative heat quantity is entered as follows:
α=A+B (Tmax 4−TCO 4)/TCO 4+f(N) (Tmax−TCO)/TCO+C Pin/Pamb. 14. The determination method as claimed in claim 6, wherein the heat losses are estimated using the formula:
QP=A HRCUM+QRQC+C HRCUM Pin/Pamb
where:
QP is the quantity of heat corresponding to the heat losses,
A and C are constants,
Pin is the pressure of a gaseous flow immediately before it enters the cylinder,
Pamb is the ambient pressure,
in which formula, said corrective factor a for the cumulative heat quantity is entered as follows:
α=A+B (Tmax 4−TCO 4)/TCO 4+f(N) (Tmax−TCO)/TCO+C Pin/Pamb. | A method for determining a mass of fuel injected into an internal combustion engine cylinder provided with a pressure sensor, includes: determining the temperature prevailing in the cylinder and amount heat released from the measured pressure; integrating amounts of heat released over a predetermined time interval to determine a cumulative amount of heat; estimating the heat losses by taking into account heat losses due to radiation and which are dependent on the measured temperature to the fourth power, and heat losses due to conduction and/or convection and dependent on both the measured temperature and corresponding engine speed, according to the formula: QP=α HR CUM , where QP is the amount of heat corresponding to the heat losses, HR CUM is the cumulative amount of heat, a is a corrective factor; and determining the amount of fuel injected, which is proportional to the cumulative amount of heat added to the heat losses.1. A method for determining a mass of fuel injected into a cylinder of an internal combustion engine, said cylinder being equipped with a sensor able to detect the pressure predominating in the interior thereof, the method comprising the following steps:
determining, from the pressure measured, firstly the corresponding temperature prevailing in the cylinder and secondly the quantity of heat released, integrating the quantities of heat released over a predefined time interval in order to determine a cumulative quantity of heat, estimating heat losses by taking into account firstly the heat losses by radiation which are dependent on the measured temperature to the power of four, and secondly the heat losses by conduction and/or convection which are dependent both on the measured temperature and on the corresponding engine speed, according to the formula:
QP=α HRCUM
where:
QP is the quantity of heat corresponding to the heat losses,
HRCUM is said cumulative heat quantity,
α is a corrective factor for the cumulative heat quantity,
determining the amount of fuel injected which is proportional to the cumulative quantity of heat plus the heat losses. 2. The determination method as claimed in claim 1, wherein the temperature is calculated from the pressure by assuming that the ratio of the product of pressure and volume firstly and temperature secondly is constant. 3. The determination method as claimed in claim 1, wherein the quantities of heat released are integrated over a complete combustion cycle, i.e. over an interval of 720° for a four-stroke engine. 4. The determination method as claimed in claim 1, wherein the estimation of heat losses also takes into account the increase in the density of the gaseous flow before it enters the cylinder. 5. The determination method as claimed in claim 1, wherein the heat losses by radiation are estimated using the formula:
QR=B HRCUM (Tmax 4−TCO 4)/TCO 4
where:
QR is the quantity of heat dissipated by radiation,
B is a constant,
HRCUM is the cumulative heat quantity,
Tmax is the maximum temperature determined over the predefined time interval taken into account for determining the cumulative heat quantity,
TCO is the engine temperature. 6. The determination method as claimed in claim 1, wherein the heat losses by conduction and/or convection are estimated using the formula:
QC=f(N) HRCUM (Tmax−TCO)/TCO
where:
QC is the quantity of heat dissipated by conduction and/or convection,
f(N) is a function with variable N corresponding to the engine speed,
Tmax is the maximum temperature determined over the predefined time interval taken into account for determining the cumulative heat quantity,
TCO is the engine temperature. 7. The determination method as claimed in claim 4, wherein the heat losses are estimated using the formula:
QP=A HRCUM+QR+QC+C HRCUM Pin/Pamb
where:
QP is the quantity of heat corresponding to the heat losses,
A and C are constants,
Pin is the pressure of a gaseous flow immediately before it enters the cylinder,
Pamb is the ambient pressure,
in which formula, said corrective factor a for the cumulative heat quantity is entered as follows:
α=A+B (Tmax 4−TCO 4)/TCO 4+f(N) (Tmax−TCO)TCO+C Pin/Pamb. 8. A method for correcting the flow of fuel injected into an internal combustion engine, which comprises the following steps:
determination of the amount of fuel injected during a combustion cycle as claimed in claim 1, comparison of the amount of fuel determined in the previous step with a reference value corresponding to the amount of fuel to be injected during the same combustion cycle, and repetition of the previous steps of determination and comparison, use of the results of comparisons between the amounts of fuel determined by the method and reference amounts, in order to define a correction value to apply to a reference value corresponding to an amount of fuel to be injected. 9. A device for determining an amount of fuel injected into a cylinder of an internal combustion engine, said cylinder being equipped with a sensor giving knowledge of the pressure prevailing therein, the device comprising a computer containing means for implementing each of the steps of a method as claimed in claim 1. 10. The determination method as claimed in claim 2, wherein the quantities of heat released are integrated over a complete combustion cycle, i.e. over an interval of 720° for a four-stroke engine. 11. The determination method as claimed in claim 2, wherein the estimation of heat losses also takes into account the increase in the density of the gaseous flow before it enters the cylinder. 12. The determination method as claimed in claim 3, wherein the estimation of heat losses also takes into account the increase in the density of the gaseous flow before it enters the cylinder. 13. The determination method as claimed in claim 5, wherein the heat losses are estimated using the formula:
QP=A HRCUM+QR+QC+C HRCUM Pin/Pamb
where:
QP is the quantity of heat corresponding to the heat losses,
A and C are constants,
Pin is the pressure of a gaseous flow immediately before it enters the cylinder,
Pamb is the ambient pressure,
in which formula, said corrective factor a for the cumulative heat quantity is entered as follows:
α=A+B (Tmax 4−TCO 4)/TCO 4+f(N) (Tmax−TCO)/TCO+C Pin/Pamb. 14. The determination method as claimed in claim 6, wherein the heat losses are estimated using the formula:
QP=A HRCUM+QRQC+C HRCUM Pin/Pamb
where:
QP is the quantity of heat corresponding to the heat losses,
A and C are constants,
Pin is the pressure of a gaseous flow immediately before it enters the cylinder,
Pamb is the ambient pressure,
in which formula, said corrective factor a for the cumulative heat quantity is entered as follows:
α=A+B (Tmax 4−TCO 4)/TCO 4+f(N) (Tmax−TCO)/TCO+C Pin/Pamb. | 2,800 |
11,935 | 11,935 | 15,956,231 | 2,814 | An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween. | 1. A stackable electronic package comprising:
a bottom surface and a top surface, wherein the following elements are positioned between the bottom surface and the top surface:
an electronic component having a surface that forms a first portion of the bottom surface, the electronic component comprising first and second electrical nodes that are positioned between the bottom surface and the top surface;
a first electrically conductive material having a surface that forms a second portion of the bottom surface;
a first metallization that electrically connects the first electrically conductive material to the first node, the first metallization extending down through vias in a dielectric layer positioned on a surface of the electronic component that includes the first and second electrical nodes; and
a feed-thru pad having a surface that forms a first portion of the top surface, wherein the feed-thru pad is electrically coupled to the first metallization. 2. The stackable electronic package of claim 1 wherein the first metallization is in direct contact with the first node and with the first electrically conductive material. 3. The stackable electronic package of claim 1 wherein the first metallization does not form a portion of either the bottom surface or the top surface of the stackable electronic package. 4. The stackable electronic package of claim 1 wherein a thickness of the electronic component is between 10 and 20 microns. 5. The stackable electronic package of claim 1 wherein a thickness of the stackable electronic package between the bottom surface and the top surface is less than 100 microns. 6. The stackable electronic package of claim 1 comprising a second electrically conductive material, the second electrically conductive material having a surface that forms a third portion of the bottom surface. 7. The stackable electronic package of claim 1 wherein the feed-thru pad comprises a layer of nickel and a layer of gold. 8. The stackable electronic package of claim 1 wherein an edge surface is formed between the bottom surface and the top surface, and wherein a center of the surface of the feed-thru pad is approximately the same distance from the edge surface as a center of the second portion of the bottom surface. 9. The stackable electronic package of claim 1 comprising an encapsulant positioned between the electronic component and the first electrically conductive material, wherein a surface of the encapsulant forms a third portion of the bottom surface. 10. The stackable electronic package of claim 9 wherein the encapsulant comprises epoxy. 11. The stackable electronic package of claim 1 further comprising:
one or more additional dielectric layers positioned between the top surface and the dielectric layer; and
one or more additional metallizations extending down through vias in each of the one or more additional dielectric layers. 12. The stackable electronic package of claim 11 wherein a topmost metallization of the one or more additional metallizations is directly coupled to the feed-thru pad. 13. A layer of a multi-layer electronic package, the layer comprising:
a first surface and a second surface, wherein the following elements are positioned between the first surface and the second surface:
an electronic component having a bottom surface that forms a first portion of the first surface and a top surface opposite the bottom surface, the top surface comprising a first contact pad;
a first electrically conductive material having a surface that forms a second portion of the first surface of the layer;
a first electrically insulating layer coupled to the top surface of the electronic component and on another surface of the first electrically conductive material opposite the surface thereof that forms the second portion of the first surface of the layer;
a second electrically insulating layer positioned about the electronic component and about the first electrically conductive material, the second electrically insulating layer having a bottom surface that forms a third portion of the first surface of the layer;
a first metallization extending through the first electrically insulating layer and electrically connecting the first electrically conductive material to the first contact pad; and
a feed-thru pad having a surface that forms a first portion of the second surface of the layer, wherein the feed-thru pad is electrically coupled to the first metallization. 14. The layer of claim 13 wherein the first metallization is in direct contact with the first contact pad and with the first electrically conductive material. 15. The layer of claim 13 wherein the first metallization does not form a portion of either the first surface or the second surface of the layer. 16. The layer of claim 13 further comprising a second electrically conductive material positioned between the first surface and the second surface of the layer, the second electrically conductive material having a surface that forms a third portion of the first surface of the layer. 17. The layer of claim 13 further comprising an encapsulant positioned between the electronic component and the first electrically conductive material, wherein a surface of the encapsulant forms a third portion of the first surface of the layer. 18. The layer of claim 13 further comprising:
one or more additional electrically insulating layers positioned between the second surface of the layer and the first electrically insulating layer; and
one or more additional metallizations extending down through vias in each of the one or more additional electrically insulating layers;
wherein a topmost metallization of the one or more additional metallizations is directly coupled to the feed-thru pad. 19. A layer of a multi-layer electronic package, the layer comprising:
an electronic component comprising an active surface that includes first and second contact pads thereon; a dielectric material having a first surface coupled to the active surface of the electronic component, the dielectric material including a plurality of vias therethrough; an electrically conductive material having a first surface coupled to the first surface of the dielectric material; metallization paths disposed on a second surface of the dielectric material and through the plurality of vias, the metallization paths electrically connecting the electrically conductive material to the first and second contact pads; and feed-thru pads electrically coupled to the metallization paths. 20. The layer of claim 19 wherein a surface of the electronic component opposite the active surface and a surface of the electrically conductive material opposite the second surface thereof form portions of a bottom surface of the layer, and wherein the feed-thru pads form a portion of a top surface of the layer. 21. The layer of claim 19 further comprising an encapsulant positioned about the electronic component and the electrically conductive material. 22. The layer of claim 19 wherein the feed-thru pads comprise multi-layer structures. 23. The layer of claim 19 further comprising a mask layer applied to a second surface of the dielectric material and surrounding side surfaces of the feed-thru pads. 24. An electronic package layer comprising:
a plurality of feed-thru pads having a top surface that defines a topmost surface of the electronic package layer; an electronic component having a bottom surface that defines a first portion of a bottommost surface of the electronic package layer; an electrically conductive material having a bottom surface that defines a second portion of the bottommost surface of the electronic package layer; a first dielectric material having a bottom surface that defines a third portion of the bottommost surface of the electronic package layer; a second dielectric material positioned between a bottom surface of the plurality of feed-thru pads and a top surface of the electrically conductive material; and metallization paths disposed on a top surface of the second dielectric material and extending through the second dielectric material to electrically couple the plurality of feed-through pads and the electrically conductive material to an active surface of the electronic component. 25. The electronic package layer of claim 24 wherein the first dielectric material encapsulates side surfaces of the electrically conductive material and the electronic component. 26. The electronic package layer of claim 24 further comprising a layer of adhesive coupling the second dielectric material to the active surface of the electronic component. 27. The electronic package layer of claim 24 wherein a metallization path of the metallization paths extends through at least two vias in the second dielectric material to electrically couple a feed-through pad of the plurality of feed through pads to the electrically conductive material and a contact pad of the first and second contact pads of the electronic component. | An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.1. A stackable electronic package comprising:
a bottom surface and a top surface, wherein the following elements are positioned between the bottom surface and the top surface:
an electronic component having a surface that forms a first portion of the bottom surface, the electronic component comprising first and second electrical nodes that are positioned between the bottom surface and the top surface;
a first electrically conductive material having a surface that forms a second portion of the bottom surface;
a first metallization that electrically connects the first electrically conductive material to the first node, the first metallization extending down through vias in a dielectric layer positioned on a surface of the electronic component that includes the first and second electrical nodes; and
a feed-thru pad having a surface that forms a first portion of the top surface, wherein the feed-thru pad is electrically coupled to the first metallization. 2. The stackable electronic package of claim 1 wherein the first metallization is in direct contact with the first node and with the first electrically conductive material. 3. The stackable electronic package of claim 1 wherein the first metallization does not form a portion of either the bottom surface or the top surface of the stackable electronic package. 4. The stackable electronic package of claim 1 wherein a thickness of the electronic component is between 10 and 20 microns. 5. The stackable electronic package of claim 1 wherein a thickness of the stackable electronic package between the bottom surface and the top surface is less than 100 microns. 6. The stackable electronic package of claim 1 comprising a second electrically conductive material, the second electrically conductive material having a surface that forms a third portion of the bottom surface. 7. The stackable electronic package of claim 1 wherein the feed-thru pad comprises a layer of nickel and a layer of gold. 8. The stackable electronic package of claim 1 wherein an edge surface is formed between the bottom surface and the top surface, and wherein a center of the surface of the feed-thru pad is approximately the same distance from the edge surface as a center of the second portion of the bottom surface. 9. The stackable electronic package of claim 1 comprising an encapsulant positioned between the electronic component and the first electrically conductive material, wherein a surface of the encapsulant forms a third portion of the bottom surface. 10. The stackable electronic package of claim 9 wherein the encapsulant comprises epoxy. 11. The stackable electronic package of claim 1 further comprising:
one or more additional dielectric layers positioned between the top surface and the dielectric layer; and
one or more additional metallizations extending down through vias in each of the one or more additional dielectric layers. 12. The stackable electronic package of claim 11 wherein a topmost metallization of the one or more additional metallizations is directly coupled to the feed-thru pad. 13. A layer of a multi-layer electronic package, the layer comprising:
a first surface and a second surface, wherein the following elements are positioned between the first surface and the second surface:
an electronic component having a bottom surface that forms a first portion of the first surface and a top surface opposite the bottom surface, the top surface comprising a first contact pad;
a first electrically conductive material having a surface that forms a second portion of the first surface of the layer;
a first electrically insulating layer coupled to the top surface of the electronic component and on another surface of the first electrically conductive material opposite the surface thereof that forms the second portion of the first surface of the layer;
a second electrically insulating layer positioned about the electronic component and about the first electrically conductive material, the second electrically insulating layer having a bottom surface that forms a third portion of the first surface of the layer;
a first metallization extending through the first electrically insulating layer and electrically connecting the first electrically conductive material to the first contact pad; and
a feed-thru pad having a surface that forms a first portion of the second surface of the layer, wherein the feed-thru pad is electrically coupled to the first metallization. 14. The layer of claim 13 wherein the first metallization is in direct contact with the first contact pad and with the first electrically conductive material. 15. The layer of claim 13 wherein the first metallization does not form a portion of either the first surface or the second surface of the layer. 16. The layer of claim 13 further comprising a second electrically conductive material positioned between the first surface and the second surface of the layer, the second electrically conductive material having a surface that forms a third portion of the first surface of the layer. 17. The layer of claim 13 further comprising an encapsulant positioned between the electronic component and the first electrically conductive material, wherein a surface of the encapsulant forms a third portion of the first surface of the layer. 18. The layer of claim 13 further comprising:
one or more additional electrically insulating layers positioned between the second surface of the layer and the first electrically insulating layer; and
one or more additional metallizations extending down through vias in each of the one or more additional electrically insulating layers;
wherein a topmost metallization of the one or more additional metallizations is directly coupled to the feed-thru pad. 19. A layer of a multi-layer electronic package, the layer comprising:
an electronic component comprising an active surface that includes first and second contact pads thereon; a dielectric material having a first surface coupled to the active surface of the electronic component, the dielectric material including a plurality of vias therethrough; an electrically conductive material having a first surface coupled to the first surface of the dielectric material; metallization paths disposed on a second surface of the dielectric material and through the plurality of vias, the metallization paths electrically connecting the electrically conductive material to the first and second contact pads; and feed-thru pads electrically coupled to the metallization paths. 20. The layer of claim 19 wherein a surface of the electronic component opposite the active surface and a surface of the electrically conductive material opposite the second surface thereof form portions of a bottom surface of the layer, and wherein the feed-thru pads form a portion of a top surface of the layer. 21. The layer of claim 19 further comprising an encapsulant positioned about the electronic component and the electrically conductive material. 22. The layer of claim 19 wherein the feed-thru pads comprise multi-layer structures. 23. The layer of claim 19 further comprising a mask layer applied to a second surface of the dielectric material and surrounding side surfaces of the feed-thru pads. 24. An electronic package layer comprising:
a plurality of feed-thru pads having a top surface that defines a topmost surface of the electronic package layer; an electronic component having a bottom surface that defines a first portion of a bottommost surface of the electronic package layer; an electrically conductive material having a bottom surface that defines a second portion of the bottommost surface of the electronic package layer; a first dielectric material having a bottom surface that defines a third portion of the bottommost surface of the electronic package layer; a second dielectric material positioned between a bottom surface of the plurality of feed-thru pads and a top surface of the electrically conductive material; and metallization paths disposed on a top surface of the second dielectric material and extending through the second dielectric material to electrically couple the plurality of feed-through pads and the electrically conductive material to an active surface of the electronic component. 25. The electronic package layer of claim 24 wherein the first dielectric material encapsulates side surfaces of the electrically conductive material and the electronic component. 26. The electronic package layer of claim 24 further comprising a layer of adhesive coupling the second dielectric material to the active surface of the electronic component. 27. The electronic package layer of claim 24 wherein a metallization path of the metallization paths extends through at least two vias in the second dielectric material to electrically couple a feed-through pad of the plurality of feed through pads to the electrically conductive material and a contact pad of the first and second contact pads of the electronic component. | 2,800 |
11,936 | 11,936 | 13,754,025 | 2,872 | Certain example embodiments of this invention relate to sputtered aluminum second surface mirrors with permanent protective coatings optionally provided thereto, and/or methods of making the same. A mirror coating supported by a substrate may include, for example, first and second dielectric layers sandwiching a metallic or substantially metallic layer including aluminum, and an optional layer including Ni and/or Cr in direct contact with the metallic or substantially metallic layer comprising aluminum. A protective film may be disposed directly over and contacting an outermost layer of the mirror coating, with the protective film having a peel strength of 200-500 cN/20 mm wide strip. | 1. A mirror, comprising:
a glass substrate; a multilayer thin film coating supported by the substrate, the multilayer thin film coating comprising, in order moving away from the substrate:
a first dielectric layer,
a metallic or substantially metallic layer comprising aluminum, and
a second dielectric layer; and
a protective film disposed directly over and contacting an outermost layer of the multilayer thin film coating, the protective film having a peel strength of 200-500 cN/20 mm wide strip, wherein the protective film is adapted to survive seven day exposure to an 85 degree C. temperature at 85% relative humidity, as well as seven day exposure to a 49 degree C. temperature at 100% relative humidity. 2. A mirror comprising:
a substrate; a multilayer thin film coating supported by the substrate, the multilayer thin film coating comprising a metallic or substantially metallic layer comprising aluminum sandwiched between inner and outer dielectric layers, the inner dielectric layer being located between at least the substrate and the metallic or substantially metallic layer comprising aluminum; and a protective film disposed directly over and contacting an outermost layer of the multilayer thin film coating. 3. The mirror of claim 2, wherein the protective film has a peel strength of 200-500 cN/20 mm wide strip. 4. The mirror of claim 2, wherein the protective film is capable of surviving seven day exposure to an 85 degree C. temperature at 85% relative humidity, as well as seven day exposure to a 49 degree C. temperature at 100% relative humidity. 5. The mirror of claim 2, wherein a layer comprising Ni and/or Cr is interposed between the metallic or substantially metallic layer comprising aluminum and the outer dielectric layer. 6. The mirror of claim 2, wherein the inner and outer dielectric layers each comprise silicon nitride. 7. The mirror of claim 2, wherein the inner dielectric layer is less than 100 angstroms thick. 8. The mirror of claim 2, wherein a layer comprising NiCr is interposed between the metallic or substantially metallic layer comprising aluminum and the outer dielectric layer, and wherein the layer comprising NiCr is 5-20 angstroms thick. 9. The mirror of claim 2, wherein the coated article has a glass side reflectance of at least 76%. 10. The mirror of claim 2, wherein the metallic or substantially metallic layer comprising aluminum is 250-650 angstroms thick. 11. The mirror of claim 2, wherein the first dielectric layer comprises material selected from one or more of: silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, zirconium oxide, titanium oxide, yittrium oxide, zinc aluminum oxide, and tin oxide. 12. The mirror of claim 2, wherein the second dielectric layer comprises material selected from one or more of: silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, zirconium oxide, titanium oxide, yittrium oxide, zinc aluminum oxide, and tin oxide. 13. The mirror of claim 2, wherein the first and second dielectric layers each comprise material selected from one or more of: silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, zirconium oxide, titanium oxide, yittrium oxide, zinc aluminum oxide, and tin oxide. 14. The mirror of claim 2, wherein the first and/or second dielectric layer(s) comprises silicon oxynitride. 15. The mirror of claim 2, wherein the first and/or second dielectric layer(s) comprises zirconium oxide. 16. The mirror of claim 2, wherein the first and/or second dielectric layer(s) comprises aluminum oxynitride. 17. The mirror of claim 2, wherein the outer dielectric layer is from 10-200 angstroms thick. 18. A method of making a mirror, the method comprising:
sputter-depositing on a glass substrate a coating comprising at least the following layers in the following order:
a first dielectric layer,
a metallic or substantially metallic layer comprising aluminum, and
a second dielectric layer; and
applying a protective film directly over and contacting an outermost layer of the coating, the protective film having a peel strength of 200-500 cN/20 mm wide strip. 19. The method of claim 18, wherein the protective film is adapted to survive seven day exposure to an 85 degree C. temperature at 85% relative humidity, as well as seven day exposure to a 49 degree C. temperature at 100% relative humidity, with no evidence of delamination of the protective film and no evidence of deterioration of the coating. 20. The method of claim 18, further comprising:
receiving, at a fabricator location, a coated article made in accordance with the method of claim 18; and cutting the coated article into pieces of one or more respective desired sizes for making mirrors. | Certain example embodiments of this invention relate to sputtered aluminum second surface mirrors with permanent protective coatings optionally provided thereto, and/or methods of making the same. A mirror coating supported by a substrate may include, for example, first and second dielectric layers sandwiching a metallic or substantially metallic layer including aluminum, and an optional layer including Ni and/or Cr in direct contact with the metallic or substantially metallic layer comprising aluminum. A protective film may be disposed directly over and contacting an outermost layer of the mirror coating, with the protective film having a peel strength of 200-500 cN/20 mm wide strip.1. A mirror, comprising:
a glass substrate; a multilayer thin film coating supported by the substrate, the multilayer thin film coating comprising, in order moving away from the substrate:
a first dielectric layer,
a metallic or substantially metallic layer comprising aluminum, and
a second dielectric layer; and
a protective film disposed directly over and contacting an outermost layer of the multilayer thin film coating, the protective film having a peel strength of 200-500 cN/20 mm wide strip, wherein the protective film is adapted to survive seven day exposure to an 85 degree C. temperature at 85% relative humidity, as well as seven day exposure to a 49 degree C. temperature at 100% relative humidity. 2. A mirror comprising:
a substrate; a multilayer thin film coating supported by the substrate, the multilayer thin film coating comprising a metallic or substantially metallic layer comprising aluminum sandwiched between inner and outer dielectric layers, the inner dielectric layer being located between at least the substrate and the metallic or substantially metallic layer comprising aluminum; and a protective film disposed directly over and contacting an outermost layer of the multilayer thin film coating. 3. The mirror of claim 2, wherein the protective film has a peel strength of 200-500 cN/20 mm wide strip. 4. The mirror of claim 2, wherein the protective film is capable of surviving seven day exposure to an 85 degree C. temperature at 85% relative humidity, as well as seven day exposure to a 49 degree C. temperature at 100% relative humidity. 5. The mirror of claim 2, wherein a layer comprising Ni and/or Cr is interposed between the metallic or substantially metallic layer comprising aluminum and the outer dielectric layer. 6. The mirror of claim 2, wherein the inner and outer dielectric layers each comprise silicon nitride. 7. The mirror of claim 2, wherein the inner dielectric layer is less than 100 angstroms thick. 8. The mirror of claim 2, wherein a layer comprising NiCr is interposed between the metallic or substantially metallic layer comprising aluminum and the outer dielectric layer, and wherein the layer comprising NiCr is 5-20 angstroms thick. 9. The mirror of claim 2, wherein the coated article has a glass side reflectance of at least 76%. 10. The mirror of claim 2, wherein the metallic or substantially metallic layer comprising aluminum is 250-650 angstroms thick. 11. The mirror of claim 2, wherein the first dielectric layer comprises material selected from one or more of: silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, zirconium oxide, titanium oxide, yittrium oxide, zinc aluminum oxide, and tin oxide. 12. The mirror of claim 2, wherein the second dielectric layer comprises material selected from one or more of: silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, zirconium oxide, titanium oxide, yittrium oxide, zinc aluminum oxide, and tin oxide. 13. The mirror of claim 2, wherein the first and second dielectric layers each comprise material selected from one or more of: silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, zirconium oxide, titanium oxide, yittrium oxide, zinc aluminum oxide, and tin oxide. 14. The mirror of claim 2, wherein the first and/or second dielectric layer(s) comprises silicon oxynitride. 15. The mirror of claim 2, wherein the first and/or second dielectric layer(s) comprises zirconium oxide. 16. The mirror of claim 2, wherein the first and/or second dielectric layer(s) comprises aluminum oxynitride. 17. The mirror of claim 2, wherein the outer dielectric layer is from 10-200 angstroms thick. 18. A method of making a mirror, the method comprising:
sputter-depositing on a glass substrate a coating comprising at least the following layers in the following order:
a first dielectric layer,
a metallic or substantially metallic layer comprising aluminum, and
a second dielectric layer; and
applying a protective film directly over and contacting an outermost layer of the coating, the protective film having a peel strength of 200-500 cN/20 mm wide strip. 19. The method of claim 18, wherein the protective film is adapted to survive seven day exposure to an 85 degree C. temperature at 85% relative humidity, as well as seven day exposure to a 49 degree C. temperature at 100% relative humidity, with no evidence of delamination of the protective film and no evidence of deterioration of the coating. 20. The method of claim 18, further comprising:
receiving, at a fabricator location, a coated article made in accordance with the method of claim 18; and cutting the coated article into pieces of one or more respective desired sizes for making mirrors. | 2,800 |
11,937 | 11,937 | 15,597,769 | 2,896 | A semiconductor device with a substrate, a low defect layer formed in a fixed position relative to the substrate, and a barrier layer comprising III-N semiconductor material formed on the low-defect layer and forming an electron gas in the low-defect layer. The device also has a source contact, a drain contact, and a gate contact for receiving a potential, the potential for adjusting a conductive path in the electron gas and between the source contact and the drain contact. Lastly, the device has a one-sided PN junction between the barrier layer and the substrate. | 1. A semiconductor device, comprising:
a substrate of a first conductivity type; a gallium-nitride layer formed over the substrate; a barrier layer comprising III-N semiconductor material formed on the gallium-nitride layer; a doped layer of a second, opposite conductivity type between the gallium-nitride layer and the substrate, wherein the doped layer has a greater doping concentration than the substrate; a source contact; a drain contact; a gate contact between the source contact and the drain contact; a first dielectric filled trench along a first edge of the gallium-nitride layer, a first edge of the barrier layer, and a first edge of the doped layer; and a second dielectric filled trench along a second edge of the gallium-nitride layer, a second edge of the barrier layer, and a second edge of the doped layer. 2. The semiconductor device of claim 1, further comprising a conductive via between the source contact and the doped layer. 3. The semiconductor device of claim 1, further comprising a conductive via between the drain contact and the doped layer. 4. The semiconductor device of claim 1, wherein a single transistor is formed between the first dielectric filled trench and the second dielectric filled trench. 5. The semiconductor device of claim 4, further comprising a second transistor formed adjacent the first transistor, the second transistor isolated from the first transistor by the first dielectric filled trench. 6. The semiconductor device of claim 5, further comprising a third dielectric filled trench, wherein the second transistor is located between the first dielectric filed trench and the third dielectric filled trench and includes a portion of the doped layer extending between the first and third dielectric filled trenches. 7. The semiconductor device of claim 6, wherein the second transistor further comprises:
a second source contact; and a conductive member between the second source contact and the portion of doped layer. 8. The semiconductor device of claim 1, further comprising an aluminum-nitride layer adjacent the doped layer. 9. The semiconductor device of claim 8, further comprising a buffer layer adjacent the aluminum-nitride layer, the buffer layer comprising a first layer adjacent the aluminum-nitride layer and a second layer, away from the aluminum-nitride layer and adjacent the first layer, wherein the first layer and second layer comprise aluminum and gallium and wherein the first layer comprises more aluminum and less gallium than the second layer. 10. The semiconductor device of claim 9, further comprising a gallium-nitride layer adjacent the buffer layer. 11. A method of forming a semiconductor device, comprising:
forming a gallium-nitride layer over a substrate, the substrate having a first conductivity type; forming a barrier layer comprising III-N semiconductor material on the gallium nitride layer; forming a doped layer of a second, opposite conductivity type between the gallium-nitride layer and the substrate, wherein the doped layer has a greater doping concentration than the substrate; forming a source contact; forming a drain contact; forming a gate contact between the source contact and the drain contact; and forming a first dielectric filled trench along a first edge of the gallium-nitride layer, a first edge of the barrier layer, and a first edge of the doped layer; and forming a second dielectric filled trench along a second edge of the gallium-nitride layer, a second edge of the barrier layer, and a second edge of the doped layer. 12. The method of claim 11, further comprising forming a conductive via between the source contact and the doped layer. 13. The method of claim 11, further comprising forming a conductive via between the drain contact and the doped layer. 14. The method of claim 11, wherein a single transistor is formed between the first dielectric filled trench and the second dielectric filled trench. 15. The method of claim 14, further comprising forming a second transistor adjacent the first transistor, the second transistor isolated from the first transistor by the first dielectric filled trench. 16. The method of claim 15, further comprising forming a third dielectric filled trench, wherein the second transistor is located between the first dielectric filed trench and the third dielectric filled trench and includes a portion of the doped layer extending between the first and third dielectric filled trenches. 17. The method of claim 16, wherein forming the second transistor further comprises:
forming a second source contact; and forming a conductive member between the second source contact and the portion of doped layer. 18. The method of claim 11, further comprising forming an aluminum-nitride layer adjacent the doped layer. 19. The method of claim 18, further comprising forming a buffer layer adjacent the aluminum-nitride layer, the buffer layer comprising a first layer adjacent the aluminum-nitride layer and a second layer, away from the aluminum-nitride layer and adjacent the first layer, wherein the first layer and second layer comprise aluminum and gallium and wherein the first layer comprises more aluminum and less gallium than the second layer. 20. The method of claim 19, further comprising forming a gallium-nitride layer adjacent the buffer layer. | A semiconductor device with a substrate, a low defect layer formed in a fixed position relative to the substrate, and a barrier layer comprising III-N semiconductor material formed on the low-defect layer and forming an electron gas in the low-defect layer. The device also has a source contact, a drain contact, and a gate contact for receiving a potential, the potential for adjusting a conductive path in the electron gas and between the source contact and the drain contact. Lastly, the device has a one-sided PN junction between the barrier layer and the substrate.1. A semiconductor device, comprising:
a substrate of a first conductivity type; a gallium-nitride layer formed over the substrate; a barrier layer comprising III-N semiconductor material formed on the gallium-nitride layer; a doped layer of a second, opposite conductivity type between the gallium-nitride layer and the substrate, wherein the doped layer has a greater doping concentration than the substrate; a source contact; a drain contact; a gate contact between the source contact and the drain contact; a first dielectric filled trench along a first edge of the gallium-nitride layer, a first edge of the barrier layer, and a first edge of the doped layer; and a second dielectric filled trench along a second edge of the gallium-nitride layer, a second edge of the barrier layer, and a second edge of the doped layer. 2. The semiconductor device of claim 1, further comprising a conductive via between the source contact and the doped layer. 3. The semiconductor device of claim 1, further comprising a conductive via between the drain contact and the doped layer. 4. The semiconductor device of claim 1, wherein a single transistor is formed between the first dielectric filled trench and the second dielectric filled trench. 5. The semiconductor device of claim 4, further comprising a second transistor formed adjacent the first transistor, the second transistor isolated from the first transistor by the first dielectric filled trench. 6. The semiconductor device of claim 5, further comprising a third dielectric filled trench, wherein the second transistor is located between the first dielectric filed trench and the third dielectric filled trench and includes a portion of the doped layer extending between the first and third dielectric filled trenches. 7. The semiconductor device of claim 6, wherein the second transistor further comprises:
a second source contact; and a conductive member between the second source contact and the portion of doped layer. 8. The semiconductor device of claim 1, further comprising an aluminum-nitride layer adjacent the doped layer. 9. The semiconductor device of claim 8, further comprising a buffer layer adjacent the aluminum-nitride layer, the buffer layer comprising a first layer adjacent the aluminum-nitride layer and a second layer, away from the aluminum-nitride layer and adjacent the first layer, wherein the first layer and second layer comprise aluminum and gallium and wherein the first layer comprises more aluminum and less gallium than the second layer. 10. The semiconductor device of claim 9, further comprising a gallium-nitride layer adjacent the buffer layer. 11. A method of forming a semiconductor device, comprising:
forming a gallium-nitride layer over a substrate, the substrate having a first conductivity type; forming a barrier layer comprising III-N semiconductor material on the gallium nitride layer; forming a doped layer of a second, opposite conductivity type between the gallium-nitride layer and the substrate, wherein the doped layer has a greater doping concentration than the substrate; forming a source contact; forming a drain contact; forming a gate contact between the source contact and the drain contact; and forming a first dielectric filled trench along a first edge of the gallium-nitride layer, a first edge of the barrier layer, and a first edge of the doped layer; and forming a second dielectric filled trench along a second edge of the gallium-nitride layer, a second edge of the barrier layer, and a second edge of the doped layer. 12. The method of claim 11, further comprising forming a conductive via between the source contact and the doped layer. 13. The method of claim 11, further comprising forming a conductive via between the drain contact and the doped layer. 14. The method of claim 11, wherein a single transistor is formed between the first dielectric filled trench and the second dielectric filled trench. 15. The method of claim 14, further comprising forming a second transistor adjacent the first transistor, the second transistor isolated from the first transistor by the first dielectric filled trench. 16. The method of claim 15, further comprising forming a third dielectric filled trench, wherein the second transistor is located between the first dielectric filed trench and the third dielectric filled trench and includes a portion of the doped layer extending between the first and third dielectric filled trenches. 17. The method of claim 16, wherein forming the second transistor further comprises:
forming a second source contact; and forming a conductive member between the second source contact and the portion of doped layer. 18. The method of claim 11, further comprising forming an aluminum-nitride layer adjacent the doped layer. 19. The method of claim 18, further comprising forming a buffer layer adjacent the aluminum-nitride layer, the buffer layer comprising a first layer adjacent the aluminum-nitride layer and a second layer, away from the aluminum-nitride layer and adjacent the first layer, wherein the first layer and second layer comprise aluminum and gallium and wherein the first layer comprises more aluminum and less gallium than the second layer. 20. The method of claim 19, further comprising forming a gallium-nitride layer adjacent the buffer layer. | 2,800 |
11,938 | 11,938 | 12,888,181 | 2,859 | An intelligent battery charge equalization and monitoring system may assist in the management of battery string health by detecting individual batteries within a string that may need servicing. The system may detect a battery within a string that is charged to a higher voltage than other batteries within the string and discharge the overcharged battery until the battery's charge is equalized with the other batteries in the string. The system may use metrics related to how often individual batteries within a string of batteries must be equalized and utilize these metrics to perform maintenance actions. | 1. A method, comprising:
receiving a plurality of voltage characteristics, wherein each voltage characteristic of the plurality of voltage characteristics is associated with a corresponding battery in a charging string of batteries; calculating a target voltage characteristic associated with each battery in the charging string of batteries based on the plurality of voltage characteristics; and sending a discharge instruction to a sensor associated with a battery in the charging string of batteries based on the voltage characteristic associated with the battery and the target voltage characteristic. 2. The method as recited in claim 1, wherein each battery in the charging string of batteries is a lead-acid monobloc. 3. The method as recited in claim 1, wherein each battery in the charging string of batteries is a lead-calcium monobloc. 4. The method as recited in claim 1, wherein the target voltage characteristic is the mean battery voltage associated with the charging string of batteries. 5. The method as recited in claim 1, wherein the discharge instruction is indicative of an optimum discharging current for the battery. 6. The method as recited in claim 1, wherein the discharge instruction is indicative of a maximum discharging time for discharging the battery. 7. The method as recited in claim 1, wherein the discharge instruction causes each battery in the charging string of batteries that is not sent a discharge instruction to receive a greater charge. 8. The method as recited in claim 1, further comprising providing a health indication of the battery based on a frequency of discharge instructions sent to the sensor. 9. The method as recited in claim 8, further comprising transmitting an alarm signal when the frequency of the discharge instructions exceed an alarm threshold. 10. The method as recited in claim 1, wherein the voltage characteristic comprises at least one of voltage, current, temperature, or internal admittance associated with the battery. 11. The method as recited in claim 1, wherein said discharge instruction is determined based on a difference between the voltage characteristic associated with the battery and the target voltage characteristic. 12. A battery sensor device comprising:
a communications interface; a controller in communication with a site control unit via the communications interface, wherein the controller is configured to perform the following steps:
measure a voltage characteristic indicative of a condition associated with a battery;
transmit the voltage characteristic to the site control unit;
receive a discharge instruction associated with the battery from the site control unit, wherein the received discharge instruction is based on the measured voltage characteristic and at least one other voltage characteristic associated with at least one other battery; and
generate a discharge current that discharges the battery in accordance with the discharge instructions. 13. The battery sensor device as recited in claim 12, wherein the battery is a lead-acid monobloc. 14. The battery sensor device as recited in claim 12, wherein the battery is a lead-calcium monobloc. 15. The battery sensor device as recited in claim 12, wherein the discharge current causes the battery to generate a test current on the battery until an excess charge is removed. 16. The battery sensor device as recited in claim 12, wherein the discharge instruction is indicative of a maximum discharging time for discharging the battery. 17. The battery sensor device as recited in claim 16, wherein the controller automatically turns off the discharge current when the target voltage is not reached within the maximum discharging time. 18. The battery sensor device as recited in claim 12, wherein the discharge current discharges the battery until an excess charge is removed from the battery. 19. The battery sensor device as recited in claim 12, wherein the discharge instruction is indicative of a pulse-width modulated discharge pattern. 20. The battery sensor device as recited in claim 12, wherein the controller is further configured to receive a target voltage, and wherein the discharge current discharges the battery until the voltage characteristic of the battery is equal to the target voltage characteristic. 21. The battery sensor device as recited in claim 12, wherein the voltage characteristic is transmitted to the site control unit via a wireless transmission. 22. The battery sensor device as recited in claim 12, wherein the battery sensor device is included in the battery. 23. A computer-readable storage medium having computer-executable instructions stored thereon that, when executed, perform a method comprising:
receiving a plurality of voltage characteristics, wherein each voltage characteristic of the plurality of voltage characteristics is associated with a respective lead-acid monobloc of a plurality of lead-acid monoblocs; calculating a target voltage characteristic based on the plurality of voltage characteristics; and sending a discharge instruction to a sensor associated with a lead-acid monobloc of the plurality of lead acid monoblocs based on the difference between the voltage characteristic associated with the lead-acid monobloc and the target voltage characteristic. | An intelligent battery charge equalization and monitoring system may assist in the management of battery string health by detecting individual batteries within a string that may need servicing. The system may detect a battery within a string that is charged to a higher voltage than other batteries within the string and discharge the overcharged battery until the battery's charge is equalized with the other batteries in the string. The system may use metrics related to how often individual batteries within a string of batteries must be equalized and utilize these metrics to perform maintenance actions.1. A method, comprising:
receiving a plurality of voltage characteristics, wherein each voltage characteristic of the plurality of voltage characteristics is associated with a corresponding battery in a charging string of batteries; calculating a target voltage characteristic associated with each battery in the charging string of batteries based on the plurality of voltage characteristics; and sending a discharge instruction to a sensor associated with a battery in the charging string of batteries based on the voltage characteristic associated with the battery and the target voltage characteristic. 2. The method as recited in claim 1, wherein each battery in the charging string of batteries is a lead-acid monobloc. 3. The method as recited in claim 1, wherein each battery in the charging string of batteries is a lead-calcium monobloc. 4. The method as recited in claim 1, wherein the target voltage characteristic is the mean battery voltage associated with the charging string of batteries. 5. The method as recited in claim 1, wherein the discharge instruction is indicative of an optimum discharging current for the battery. 6. The method as recited in claim 1, wherein the discharge instruction is indicative of a maximum discharging time for discharging the battery. 7. The method as recited in claim 1, wherein the discharge instruction causes each battery in the charging string of batteries that is not sent a discharge instruction to receive a greater charge. 8. The method as recited in claim 1, further comprising providing a health indication of the battery based on a frequency of discharge instructions sent to the sensor. 9. The method as recited in claim 8, further comprising transmitting an alarm signal when the frequency of the discharge instructions exceed an alarm threshold. 10. The method as recited in claim 1, wherein the voltage characteristic comprises at least one of voltage, current, temperature, or internal admittance associated with the battery. 11. The method as recited in claim 1, wherein said discharge instruction is determined based on a difference between the voltage characteristic associated with the battery and the target voltage characteristic. 12. A battery sensor device comprising:
a communications interface; a controller in communication with a site control unit via the communications interface, wherein the controller is configured to perform the following steps:
measure a voltage characteristic indicative of a condition associated with a battery;
transmit the voltage characteristic to the site control unit;
receive a discharge instruction associated with the battery from the site control unit, wherein the received discharge instruction is based on the measured voltage characteristic and at least one other voltage characteristic associated with at least one other battery; and
generate a discharge current that discharges the battery in accordance with the discharge instructions. 13. The battery sensor device as recited in claim 12, wherein the battery is a lead-acid monobloc. 14. The battery sensor device as recited in claim 12, wherein the battery is a lead-calcium monobloc. 15. The battery sensor device as recited in claim 12, wherein the discharge current causes the battery to generate a test current on the battery until an excess charge is removed. 16. The battery sensor device as recited in claim 12, wherein the discharge instruction is indicative of a maximum discharging time for discharging the battery. 17. The battery sensor device as recited in claim 16, wherein the controller automatically turns off the discharge current when the target voltage is not reached within the maximum discharging time. 18. The battery sensor device as recited in claim 12, wherein the discharge current discharges the battery until an excess charge is removed from the battery. 19. The battery sensor device as recited in claim 12, wherein the discharge instruction is indicative of a pulse-width modulated discharge pattern. 20. The battery sensor device as recited in claim 12, wherein the controller is further configured to receive a target voltage, and wherein the discharge current discharges the battery until the voltage characteristic of the battery is equal to the target voltage characteristic. 21. The battery sensor device as recited in claim 12, wherein the voltage characteristic is transmitted to the site control unit via a wireless transmission. 22. The battery sensor device as recited in claim 12, wherein the battery sensor device is included in the battery. 23. A computer-readable storage medium having computer-executable instructions stored thereon that, when executed, perform a method comprising:
receiving a plurality of voltage characteristics, wherein each voltage characteristic of the plurality of voltage characteristics is associated with a respective lead-acid monobloc of a plurality of lead-acid monoblocs; calculating a target voltage characteristic based on the plurality of voltage characteristics; and sending a discharge instruction to a sensor associated with a lead-acid monobloc of the plurality of lead acid monoblocs based on the difference between the voltage characteristic associated with the lead-acid monobloc and the target voltage characteristic. | 2,800 |
11,939 | 11,939 | 15,437,409 | 2,863 | Various embodiments for using three-dimensional representations for defect-related applications are provided. One computer-implemented method for determining one or more inspection parameters for a wafer inspection recipe includes generating a three-dimensional representation of one or more layers of a wafer based on design data. The method also includes determining one or more inspection parameters for a wafer inspection recipe based on the three-dimensional representation. | 1. A computer-implemented method for determining one or more inspection parameters for a wafer inspection recipe, comprising:
generating a three-dimensional representation of one or more layers of a wafer based on design data; and determining one or more inspection parameters for a wafer inspection recipe based on the three-dimensional representation, wherein said generating and said determining are performed by a computer system. 2. A non-transitory computer-readable medium containing program instructions stored therein for causing a computer system to perform a computer-implemented method for determining one or more inspection parameters for a wafer inspection recipe, wherein the computer-implemented method comprises:
generating a three-dimensional representation of one or more layers of a wafer based on design data; and determining one or more inspection parameters for a wafer inspection recipe based on the three-dimensional representation. 3. A system configured to determine one or more inspection parameters for a wafer inspection recipe, comprising:
a simulation engine configured to generate a three-dimensional representation of one or more layers of a wafer based on design data; and a computer system configured to determine one or more inspection parameters for a wafer inspection recipe based on the three-dimensional representation. | Various embodiments for using three-dimensional representations for defect-related applications are provided. One computer-implemented method for determining one or more inspection parameters for a wafer inspection recipe includes generating a three-dimensional representation of one or more layers of a wafer based on design data. The method also includes determining one or more inspection parameters for a wafer inspection recipe based on the three-dimensional representation.1. A computer-implemented method for determining one or more inspection parameters for a wafer inspection recipe, comprising:
generating a three-dimensional representation of one or more layers of a wafer based on design data; and determining one or more inspection parameters for a wafer inspection recipe based on the three-dimensional representation, wherein said generating and said determining are performed by a computer system. 2. A non-transitory computer-readable medium containing program instructions stored therein for causing a computer system to perform a computer-implemented method for determining one or more inspection parameters for a wafer inspection recipe, wherein the computer-implemented method comprises:
generating a three-dimensional representation of one or more layers of a wafer based on design data; and determining one or more inspection parameters for a wafer inspection recipe based on the three-dimensional representation. 3. A system configured to determine one or more inspection parameters for a wafer inspection recipe, comprising:
a simulation engine configured to generate a three-dimensional representation of one or more layers of a wafer based on design data; and a computer system configured to determine one or more inspection parameters for a wafer inspection recipe based on the three-dimensional representation. | 2,800 |
11,940 | 11,940 | 16,013,397 | 2,818 | Implementations of semiconductor packages may include: a heat sink including a plurality of projections extending from a first side of the heat sink and a die having a first side and a second side. The first side of the die may be coupled directly to a second side of the heat sink through a thermally conductive and electrically isolating material. The package may also include one or more interconnects including a solderable metal. The one or more interconnects may be coupled to the second side of the die. The package may also include a molding compound around the die and the one or more interconnects. The molding compound may be directly coupled to the second side of the heat sink. | 1. A semiconductor package comprising:
a heat sink comprising a plurality of projections extending from a first side of the heat sink; a die comprising a first side and a second side, the first side of the die coupled directly to a second side of the heat sink through a thermally conductive and electrically isolating material; one or more interconnects comprising a solderable metal, the one or more interconnects coupled to the second side of the die; and a molding compound coupled around the die and the one or more interconnects; wherein the one or more interconnects extend through a thickness of the mold compound; and wherein the molding compound is directly coupled to the second side of the heat sink. 2. The package of claim 1, wherein the heat sink is derived from a lead frame. 3. The package of claim 1, wherein the heat sink comprises a thickness of between 4 mils to at least 50 mils. 4. The package of claim 1, wherein the thermally conductive and electrically isolating material is one of solder, epoxy, die attach film, and any combination thereof. 5. The package of claim 1, wherein the one or more interconnects comprise copper pillars, solder, and plated pads. 6. The package of claim 1, wherein the plurality of projections comprise one of squares, concentric circles, lines, and waved lines. 7. A semiconductor package comprising:
a heat sink derived from a lead frame, the heat sink comprising a first side and a second side wherein a plurality of projections extend from the first side of the lead frame; a die comprising a first side and a second side, the first side of the die coupled directly to the second side of the heat sink through a thermally conductive and electrically isolating material; one or more interconnects coupled to the second side of the die, the one or more interconnects comprising a solderable metal on a second side of the interconnect opposite the die; and a molding compound coupled around the die and the one of more interconnects; wherein the one or more interconnects extend through a thickness of the mold compound; and wherein the molding compound is directly coupled to the second side of the heat sink. 8. The package of claim 7, wherein the heat sink comprises a thickness of between 4 mils to at least 50 mils. 9. The package of claim 7, wherein the thermally conductive and electrically isolating material is one of solder, epoxy, die attach film, and any combination thereof. 10. The package of claim 7, wherein the one or more interconnects comprise one of copper pillars, solder, and plated pads. 11. The package of claim 7, wherein the plurality of projections comprise one of squares, concentric circles, lines, and waved lines. 12-20. (canceled) 21. A semiconductor package comprising:
a heat sink comprising a plurality of projections extending from a first side of the heat sink; a die comprising a first side and a second side, the first side of the die coupled directly to a second side of the heat sink through a thermally conductive and electrically isolating material, wherein the entire second side of the heat sink is coplanar with the entire first side of the die; one or more interconnects comprising a solderable metal, the one or more interconnects coupled to the second side of the die; and a molding compound coupled around the die and the one or more interconnects, wherein the molding compound is directly coupled to the second side of the heat sink. 22. The package of claim 21, wherein the heat sink is derived from a lead frame. 23. The package of claim 21, wherein the heat sink comprises a thickness of between 4 mils to at least 50 mils. 24. The package of claim 21, wherein the thermally conductive and electrically isolating material is one of solder, epoxy, die attach film, or any combination thereof. 25. The package of claim 21, wherein the one or more interconnects comprise one of copper pillars, solder, or plated pads. 26. The package of claim 21, wherein the plurality of projections comprise one of squares, concentric circles, lines, or waved lines. | Implementations of semiconductor packages may include: a heat sink including a plurality of projections extending from a first side of the heat sink and a die having a first side and a second side. The first side of the die may be coupled directly to a second side of the heat sink through a thermally conductive and electrically isolating material. The package may also include one or more interconnects including a solderable metal. The one or more interconnects may be coupled to the second side of the die. The package may also include a molding compound around the die and the one or more interconnects. The molding compound may be directly coupled to the second side of the heat sink.1. A semiconductor package comprising:
a heat sink comprising a plurality of projections extending from a first side of the heat sink; a die comprising a first side and a second side, the first side of the die coupled directly to a second side of the heat sink through a thermally conductive and electrically isolating material; one or more interconnects comprising a solderable metal, the one or more interconnects coupled to the second side of the die; and a molding compound coupled around the die and the one or more interconnects; wherein the one or more interconnects extend through a thickness of the mold compound; and wherein the molding compound is directly coupled to the second side of the heat sink. 2. The package of claim 1, wherein the heat sink is derived from a lead frame. 3. The package of claim 1, wherein the heat sink comprises a thickness of between 4 mils to at least 50 mils. 4. The package of claim 1, wherein the thermally conductive and electrically isolating material is one of solder, epoxy, die attach film, and any combination thereof. 5. The package of claim 1, wherein the one or more interconnects comprise copper pillars, solder, and plated pads. 6. The package of claim 1, wherein the plurality of projections comprise one of squares, concentric circles, lines, and waved lines. 7. A semiconductor package comprising:
a heat sink derived from a lead frame, the heat sink comprising a first side and a second side wherein a plurality of projections extend from the first side of the lead frame; a die comprising a first side and a second side, the first side of the die coupled directly to the second side of the heat sink through a thermally conductive and electrically isolating material; one or more interconnects coupled to the second side of the die, the one or more interconnects comprising a solderable metal on a second side of the interconnect opposite the die; and a molding compound coupled around the die and the one of more interconnects; wherein the one or more interconnects extend through a thickness of the mold compound; and wherein the molding compound is directly coupled to the second side of the heat sink. 8. The package of claim 7, wherein the heat sink comprises a thickness of between 4 mils to at least 50 mils. 9. The package of claim 7, wherein the thermally conductive and electrically isolating material is one of solder, epoxy, die attach film, and any combination thereof. 10. The package of claim 7, wherein the one or more interconnects comprise one of copper pillars, solder, and plated pads. 11. The package of claim 7, wherein the plurality of projections comprise one of squares, concentric circles, lines, and waved lines. 12-20. (canceled) 21. A semiconductor package comprising:
a heat sink comprising a plurality of projections extending from a first side of the heat sink; a die comprising a first side and a second side, the first side of the die coupled directly to a second side of the heat sink through a thermally conductive and electrically isolating material, wherein the entire second side of the heat sink is coplanar with the entire first side of the die; one or more interconnects comprising a solderable metal, the one or more interconnects coupled to the second side of the die; and a molding compound coupled around the die and the one or more interconnects, wherein the molding compound is directly coupled to the second side of the heat sink. 22. The package of claim 21, wherein the heat sink is derived from a lead frame. 23. The package of claim 21, wherein the heat sink comprises a thickness of between 4 mils to at least 50 mils. 24. The package of claim 21, wherein the thermally conductive and electrically isolating material is one of solder, epoxy, die attach film, or any combination thereof. 25. The package of claim 21, wherein the one or more interconnects comprise one of copper pillars, solder, or plated pads. 26. The package of claim 21, wherein the plurality of projections comprise one of squares, concentric circles, lines, or waved lines. | 2,800 |
11,941 | 11,941 | 15,818,156 | 2,836 | A power adapter and method of use wherein a power adapter provided with a power supply portion and human detection and cooling circuitry may be cooled and/or disabled upon detection of a human proximate the power adapter. In use, a voltage regulator integrated circuit of the power adapter is disabled if an overload temperature is sensed. Alternatively, if a human presence is sensed proximate the power adapter, the voltage regulator integrated circuit is also disabled and a cooling fan is energized. | 1. A power adapter, comprising:
a power supply portion coupled to human detection and cooling circuitry via an enable/disable input of a voltage regulator integrated circuit of the power supply portion; the voltage regulator integrated circuit provided with a temperature sensor; and the human detection and cooling circuitry provided with a sensor; the human detection and cooling circuitry configured to disable the voltage regulator and energize a fan of the human detection and cooling circuitry upon detection of a human presence by the sensor. 2. The power adapter of claim 1, wherein the sensor comprises an infrared light emitting diode and a proximity sensor. 3. The power adapter of claim 2, wherein the proximity sensor is coupled to a microcontroller unit configured to receive an interrupt signal from the proximity sensor when the human presence is sensed. 4. The power adapter of claim 3, wherein the fan is energized by a switch controlled by the microcontroller unit. 5. The power adapter of claim 4, wherein the switch is a semiconductor switch. 6. The power adapter of claim 5, wherein the switch is a metal-oxide semiconductor field-effect transistor. 7. The power adapter of claim 1, wherein the power supply portion has an alternating current input. 8. The power adapter of claim 1, wherein the power supply portion has a direct current input. 9. The power adapter of claim 1, wherein the power supply portion has a voltage bus output configured as a USB interface. 10. A method for operation of a power adapter, comprising:
disabling a voltage regulator integrated circuit of the power adapter if an overload temperature is sensed; and disabling the voltage regulator integrated circuit of the power adapter and energizing a fan if a human presence is sensed by a sensor of the power adapter. 11. The method of claim 10, wherein the overload temperature is sensed by a temperature sensor of the voltage regulator integrated circuit. 12. The method of claim 10, wherein the sensor comprises an infrared light emitting diode and a proximity sensor. 13. The method of claim 12, further including a microcontroller unit;
the disabling of the voltage regulator integrated circuit and the energizing of the fan initiated by the microcontroller unit upon reception of an interrupt signal from the proximity sensor when the human presence is sensed. 14. The method of claim 13, wherein the microcontroller unit enables a switch to energize the fan. 15. The method of claim 14, wherein the switch is a semiconductor switch. 16. The method of claim 10, wherein once the human presence is sensed, the voltage regulator remains disabled and the fan remains energized until the human presence is no longer sensed by the sensor. 17. The method of claim 10, wherein the power adapter receives an alternating current input. 18. The method of claim 10, wherein the power adapter receives a direct current input. 19. The method of claim 10, wherein the power adapter provides a voltage bus output; the voltage bus output configured as a USB interface. | A power adapter and method of use wherein a power adapter provided with a power supply portion and human detection and cooling circuitry may be cooled and/or disabled upon detection of a human proximate the power adapter. In use, a voltage regulator integrated circuit of the power adapter is disabled if an overload temperature is sensed. Alternatively, if a human presence is sensed proximate the power adapter, the voltage regulator integrated circuit is also disabled and a cooling fan is energized.1. A power adapter, comprising:
a power supply portion coupled to human detection and cooling circuitry via an enable/disable input of a voltage regulator integrated circuit of the power supply portion; the voltage regulator integrated circuit provided with a temperature sensor; and the human detection and cooling circuitry provided with a sensor; the human detection and cooling circuitry configured to disable the voltage regulator and energize a fan of the human detection and cooling circuitry upon detection of a human presence by the sensor. 2. The power adapter of claim 1, wherein the sensor comprises an infrared light emitting diode and a proximity sensor. 3. The power adapter of claim 2, wherein the proximity sensor is coupled to a microcontroller unit configured to receive an interrupt signal from the proximity sensor when the human presence is sensed. 4. The power adapter of claim 3, wherein the fan is energized by a switch controlled by the microcontroller unit. 5. The power adapter of claim 4, wherein the switch is a semiconductor switch. 6. The power adapter of claim 5, wherein the switch is a metal-oxide semiconductor field-effect transistor. 7. The power adapter of claim 1, wherein the power supply portion has an alternating current input. 8. The power adapter of claim 1, wherein the power supply portion has a direct current input. 9. The power adapter of claim 1, wherein the power supply portion has a voltage bus output configured as a USB interface. 10. A method for operation of a power adapter, comprising:
disabling a voltage regulator integrated circuit of the power adapter if an overload temperature is sensed; and disabling the voltage regulator integrated circuit of the power adapter and energizing a fan if a human presence is sensed by a sensor of the power adapter. 11. The method of claim 10, wherein the overload temperature is sensed by a temperature sensor of the voltage regulator integrated circuit. 12. The method of claim 10, wherein the sensor comprises an infrared light emitting diode and a proximity sensor. 13. The method of claim 12, further including a microcontroller unit;
the disabling of the voltage regulator integrated circuit and the energizing of the fan initiated by the microcontroller unit upon reception of an interrupt signal from the proximity sensor when the human presence is sensed. 14. The method of claim 13, wherein the microcontroller unit enables a switch to energize the fan. 15. The method of claim 14, wherein the switch is a semiconductor switch. 16. The method of claim 10, wherein once the human presence is sensed, the voltage regulator remains disabled and the fan remains energized until the human presence is no longer sensed by the sensor. 17. The method of claim 10, wherein the power adapter receives an alternating current input. 18. The method of claim 10, wherein the power adapter receives a direct current input. 19. The method of claim 10, wherein the power adapter provides a voltage bus output; the voltage bus output configured as a USB interface. | 2,800 |
11,942 | 11,942 | 13,780,773 | 2,832 | A dual magnetic phase stator lamination for use in stator permanent magnet electric machines is disclosed. The permanent magnet electrical machine includes a rotor mounted for rotation about a central axis and a stator positioned about the rotor and comprising a plurality of stator laminations, wherein each of the stator laminations is composed of a dual magnetic phase material and includes a first stator lamination portion comprising a magnetic material and a second stator lamination portion comprising a non-magnetic material, the second stator lamination portion comprising an area positioned adjacent to each of a plurality of permanent magnets embedded in the stator lamination. The second stator lamination portion comprises a heat treated portion of the stator lamination, with the heat treating of the second stator lamination portion rendering the dual magnetic phase material of the stator lamination non-magnetic at the locations of the second stator lamination portion. | 1. A permanent magnet electrical machine comprising:
a rotor mounted for rotation about a central axis; and a stator positioned about the rotor and comprising a plurality of stator laminations, wherein each of the stator laminations is composed of a dual magnetic phase material and includes:
a first stator lamination portion comprising a magnetic material; and
a second stator lamination portion comprising a non-magnetic material, the second stator lamination portion comprising an area positioned adjacent to each of a plurality of permanent magnets embedded in the stator lamination;
wherein the second stator lamination portion comprises a heat treated portion of the stator lamination, with the heat treating of the second stator lamination portion rendering the dual magnetic phase material of the stator lamination non-magnetic at the locations of the second stator lamination portion. 2. The permanent magnet electrical machine of claim 1 further comprising a bridge positioned adjacent each of the plurality of permanent magnets, such that each bridge is formed on one or both sides of a respective permanent magnet. 3. The permanent magnet electrical machine of claim 2 wherein the second lamination portion comprises the bridges positioned adjacent the plurality of permanent magnets, with each bridge being non-magnetic on one or both sides of its respective permanent magnet. 4. The permanent magnet electrical machine of claim 3 wherein the plurality of permanent magnets are embedded in openings formed in teeth of the stator lamination and oriented generally parallel to a direction of the tooth, with each bridge being non-magnetic on both sides of a respective permanent magnet, on an outer edge of a respective permanent magnet, or on an inner edge of a respective permanent magnet. 5. The permanent magnet electrical machine of claim 3 wherein the plurality of permanent magnets are embedded in openings formed in teeth of the stator lamination so as to be oriented generally perpendicular to a direction of the teeth and along a face of the teeth, with each bridge being non-magnetic on both sides of a respective permanent magnet. 6. The permanent magnet electrical machine of claim 3 wherein the plurality of permanent magnets are embedded in openings formed in an outer casing of the stator lamination, with each bridge being non-magnetic on both sides of a respective permanent magnet, on an outer edge of a respective permanent magnet, or on an inner edge of a respective permanent magnet. 7. The permanent magnet electrical machine of claim 1 wherein the non-magnetic second stator lamination portion blocks a leakage path of permanent magnet flux. 8. The permanent magnet electrical machine of claim 1 wherein each of the plurality of stator laminations comprises an integral, non-segmented stator lamination formed as a single piece from the dual magnetic phase material. 9. The permanent magnet electrical machine of claim 8 wherein the integral, non-segmented stator lamination has a uniform coefficient of thermal expansion. 10. The permanent magnet electrical machine of claim 1 wherein the machine comprises one of a permanent magnet flux switching machine, a permanent magnet flux reversal machine, and a doubly salient permanent magnet machine. 11. A method for manufacturing a permanent magnet electrical machine, the method comprising:
providing a rotor mounted for rotation about a central axis; forming each of a plurality of stator laminations for use in forming a stator, wherein forming each of the plurality of stator laminations comprises:
providing a non-segmented stator lamination formed of a dual magnetic phase material, the dual magnetic phase material being magnetic in a first state and non-magnetic in a second state, with the non-segmented stator lamination being provided in the magnetic first state;
embedding a plurality of permanent magnets in the stator lamination; and
heat treating the stator lamination at a plurality of pre-determined locations adjacent to the plurality of permanent magnets so as to cause the pre-determined locations of the stator lamination to transition to the non-magnetic second state; and
joining the stator laminations to form a stator, with the stator being positioned about the rotor so as to enable rotation of the rotor within the stator. 12. The method of claim 11 wherein each of the plurality of stator laminations comprises a plurality of bridges positioned adjacent the plurality of permanent magnets, such that a bridge is formed on one or both sides of each respective permanent magnet. 13. The method of claim 11 wherein heat treating the stator lamination at the plurality of pre-determined locations comprises heat treating the plurality of bridges. 14. The method of claim 11 wherein embedding the plurality of permanent magnets comprises embedding the plurality of permanent magnets in teeth of the stator lamination so as to be oriented generally parallel to a direction of the teeth; and
wherein heat treating the plurality of bridges comprises heat treating each bridge on both sides of a respective permanent magnet, heat treating each bridge on an outer edge of a respective permanent magnet, or heat treating each bridge on an inner edge of a respective permanent magnet. 15. The method of claim 11 wherein embedding the plurality of permanent magnets comprises embedding the plurality of permanent magnets in teeth of the stator lamination so as to be oriented generally perpendicular to a direction of the teeth and along a face of the teeth; and
wherein heat treating the plurality of bridges comprises heat treating each bridge on both sides of a respective permanent magnet. 16. The method of claim 11 wherein embedding the plurality of permanent magnets comprises embedding the plurality of permanent magnets in an outer casing of the stator lamination; and
wherein heat treating the plurality of bridges comprises heat treating each bridge on both sides of a respective permanent magnet, on an outer edge of a respective permanent magnet, or on an inner edge of a respective permanent magnet. 17. The method of claim 11 wherein heat treating the stator lamination at the plurality of pre-determined locations adjacent to the plurality of permanent magnets blocks a leakage path of permanent magnet flux. 18. A stator lamination for a permanent magnet electrical machine, the stator lamination comprising:
an outer casing; a plurality of teeth extending radially inward from the outer casing; a plurality of openings formed in one of the outer casing and the plurality of teeth, wherein a bridge structure is formed adjacent each opening to provide mechanical stability to the stator lamination; and a plurality of permanent magnets embedded in the stator lamination within the plurality of openings, such that the plurality of permanent magnets in one of the outer casing or the plurality of teeth; wherein the stator lamination is formed of a dual magnetic phase material, with the bridge structures being heat treated so as to be in a non-magnetic state and a remainder of the stator lamination being in a magnetic state, such that the bridge structures block a leakage path of permanent magnet flux. 19. The stator lamination of claim 18 wherein the plurality of permanent magnets are embedded in openings formed in the plurality of teeth, with each of the bridge structures being non-magnetic on both sides of a respective permanent magnet, on an outer edge of a respective permanent magnet, or on an inner edge of a respective permanent magnet. 20. The stator lamination of claim 18 wherein the plurality of permanent magnets are embedded in openings formed in the outer casing, with each of the bridge structures being non-magnetic on both sides of a respective permanent magnet, on an outer edge of a respective permanent magnet, or on an inner edge of a respective permanent magnet. 21. The stator lamination of claim 18 the stator lamination is formed as an integral, non-segmented stator lamination formed as a single piece from the dual magnetic phase material. | A dual magnetic phase stator lamination for use in stator permanent magnet electric machines is disclosed. The permanent magnet electrical machine includes a rotor mounted for rotation about a central axis and a stator positioned about the rotor and comprising a plurality of stator laminations, wherein each of the stator laminations is composed of a dual magnetic phase material and includes a first stator lamination portion comprising a magnetic material and a second stator lamination portion comprising a non-magnetic material, the second stator lamination portion comprising an area positioned adjacent to each of a plurality of permanent magnets embedded in the stator lamination. The second stator lamination portion comprises a heat treated portion of the stator lamination, with the heat treating of the second stator lamination portion rendering the dual magnetic phase material of the stator lamination non-magnetic at the locations of the second stator lamination portion.1. A permanent magnet electrical machine comprising:
a rotor mounted for rotation about a central axis; and a stator positioned about the rotor and comprising a plurality of stator laminations, wherein each of the stator laminations is composed of a dual magnetic phase material and includes:
a first stator lamination portion comprising a magnetic material; and
a second stator lamination portion comprising a non-magnetic material, the second stator lamination portion comprising an area positioned adjacent to each of a plurality of permanent magnets embedded in the stator lamination;
wherein the second stator lamination portion comprises a heat treated portion of the stator lamination, with the heat treating of the second stator lamination portion rendering the dual magnetic phase material of the stator lamination non-magnetic at the locations of the second stator lamination portion. 2. The permanent magnet electrical machine of claim 1 further comprising a bridge positioned adjacent each of the plurality of permanent magnets, such that each bridge is formed on one or both sides of a respective permanent magnet. 3. The permanent magnet electrical machine of claim 2 wherein the second lamination portion comprises the bridges positioned adjacent the plurality of permanent magnets, with each bridge being non-magnetic on one or both sides of its respective permanent magnet. 4. The permanent magnet electrical machine of claim 3 wherein the plurality of permanent magnets are embedded in openings formed in teeth of the stator lamination and oriented generally parallel to a direction of the tooth, with each bridge being non-magnetic on both sides of a respective permanent magnet, on an outer edge of a respective permanent magnet, or on an inner edge of a respective permanent magnet. 5. The permanent magnet electrical machine of claim 3 wherein the plurality of permanent magnets are embedded in openings formed in teeth of the stator lamination so as to be oriented generally perpendicular to a direction of the teeth and along a face of the teeth, with each bridge being non-magnetic on both sides of a respective permanent magnet. 6. The permanent magnet electrical machine of claim 3 wherein the plurality of permanent magnets are embedded in openings formed in an outer casing of the stator lamination, with each bridge being non-magnetic on both sides of a respective permanent magnet, on an outer edge of a respective permanent magnet, or on an inner edge of a respective permanent magnet. 7. The permanent magnet electrical machine of claim 1 wherein the non-magnetic second stator lamination portion blocks a leakage path of permanent magnet flux. 8. The permanent magnet electrical machine of claim 1 wherein each of the plurality of stator laminations comprises an integral, non-segmented stator lamination formed as a single piece from the dual magnetic phase material. 9. The permanent magnet electrical machine of claim 8 wherein the integral, non-segmented stator lamination has a uniform coefficient of thermal expansion. 10. The permanent magnet electrical machine of claim 1 wherein the machine comprises one of a permanent magnet flux switching machine, a permanent magnet flux reversal machine, and a doubly salient permanent magnet machine. 11. A method for manufacturing a permanent magnet electrical machine, the method comprising:
providing a rotor mounted for rotation about a central axis; forming each of a plurality of stator laminations for use in forming a stator, wherein forming each of the plurality of stator laminations comprises:
providing a non-segmented stator lamination formed of a dual magnetic phase material, the dual magnetic phase material being magnetic in a first state and non-magnetic in a second state, with the non-segmented stator lamination being provided in the magnetic first state;
embedding a plurality of permanent magnets in the stator lamination; and
heat treating the stator lamination at a plurality of pre-determined locations adjacent to the plurality of permanent magnets so as to cause the pre-determined locations of the stator lamination to transition to the non-magnetic second state; and
joining the stator laminations to form a stator, with the stator being positioned about the rotor so as to enable rotation of the rotor within the stator. 12. The method of claim 11 wherein each of the plurality of stator laminations comprises a plurality of bridges positioned adjacent the plurality of permanent magnets, such that a bridge is formed on one or both sides of each respective permanent magnet. 13. The method of claim 11 wherein heat treating the stator lamination at the plurality of pre-determined locations comprises heat treating the plurality of bridges. 14. The method of claim 11 wherein embedding the plurality of permanent magnets comprises embedding the plurality of permanent magnets in teeth of the stator lamination so as to be oriented generally parallel to a direction of the teeth; and
wherein heat treating the plurality of bridges comprises heat treating each bridge on both sides of a respective permanent magnet, heat treating each bridge on an outer edge of a respective permanent magnet, or heat treating each bridge on an inner edge of a respective permanent magnet. 15. The method of claim 11 wherein embedding the plurality of permanent magnets comprises embedding the plurality of permanent magnets in teeth of the stator lamination so as to be oriented generally perpendicular to a direction of the teeth and along a face of the teeth; and
wherein heat treating the plurality of bridges comprises heat treating each bridge on both sides of a respective permanent magnet. 16. The method of claim 11 wherein embedding the plurality of permanent magnets comprises embedding the plurality of permanent magnets in an outer casing of the stator lamination; and
wherein heat treating the plurality of bridges comprises heat treating each bridge on both sides of a respective permanent magnet, on an outer edge of a respective permanent magnet, or on an inner edge of a respective permanent magnet. 17. The method of claim 11 wherein heat treating the stator lamination at the plurality of pre-determined locations adjacent to the plurality of permanent magnets blocks a leakage path of permanent magnet flux. 18. A stator lamination for a permanent magnet electrical machine, the stator lamination comprising:
an outer casing; a plurality of teeth extending radially inward from the outer casing; a plurality of openings formed in one of the outer casing and the plurality of teeth, wherein a bridge structure is formed adjacent each opening to provide mechanical stability to the stator lamination; and a plurality of permanent magnets embedded in the stator lamination within the plurality of openings, such that the plurality of permanent magnets in one of the outer casing or the plurality of teeth; wherein the stator lamination is formed of a dual magnetic phase material, with the bridge structures being heat treated so as to be in a non-magnetic state and a remainder of the stator lamination being in a magnetic state, such that the bridge structures block a leakage path of permanent magnet flux. 19. The stator lamination of claim 18 wherein the plurality of permanent magnets are embedded in openings formed in the plurality of teeth, with each of the bridge structures being non-magnetic on both sides of a respective permanent magnet, on an outer edge of a respective permanent magnet, or on an inner edge of a respective permanent magnet. 20. The stator lamination of claim 18 wherein the plurality of permanent magnets are embedded in openings formed in the outer casing, with each of the bridge structures being non-magnetic on both sides of a respective permanent magnet, on an outer edge of a respective permanent magnet, or on an inner edge of a respective permanent magnet. 21. The stator lamination of claim 18 the stator lamination is formed as an integral, non-segmented stator lamination formed as a single piece from the dual magnetic phase material. | 2,800 |
11,943 | 11,943 | 15,380,724 | 2,863 | A system and method for detecting a phase-to-ground fault in an AC electrical machine operates to receive measurements of three-phase voltages and currents provided to the AC electrical machine, compute at least one of a zero sequence component and a negative sequence component of voltage and current from the three-phase voltages and currents, and calculate a fault severity index (F SI) based on the zero or negative sequence component of voltage and current, so as to identify a phase-to-ground fault in the AC electrical machine. Calculating the FSI further includes determining a total value of the zero or negative sequence current, determining a noise-contributed value of the zero or negative sequence current included in the total value, determining a compensated value of the zero or negative sequence current based on the total value and the noise-contributed value, and calculating the FSI based on the compensated value. | 1. A controller configured to detect a phase-to-ground fault in an AC electrical machine, the controller comprising a processor programmed to:
receive measurements of three-phase voltages and currents provided to the AC electrical machine, the measurements being received from voltage and current sensors associated with the electrical distribution circuit; compute at least one of a zero sequence component and a negative sequence component of voltage and current from the three-phase voltages and currents; and calculate a fault severity index (F SI) based on the at least one of the zero sequence component and the negative sequence component of voltage and current, so as to identify a phase-to-ground fault in the AC electrical machine, wherein calculating the FSI comprises:
determining a total value of at least one of a zero sequence current and a negative sequence current;
determining a noise-contributed value of the at least one of the zero sequence current and the negative sequence current included in the total value;
determining a compensated value of the at least one of the zero sequence current and the negative sequence current based on the total value and the noise-contributed value; and
calculating the FSI based on the compensated value. 2. The controller of claim 1 wherein, in computing the at least one of the zero sequence component and the negative sequence component of voltage and current, the processor is programmed to compute the zero sequence component of voltage and current, with a total value, noise-contributed value, and compensated value of the zero sequence current being determined. 3. The controller of claim 2 wherein, when the AC electrical machine is a star-connected electrical machine, the processor is programmed to calculate the FSI according to:
I 0PG=3*(I s0 −I l0)=I fa +I fb +I fc,
where Ifa, Ifb, Ifc are phase-to-ground fault currents, Is0 is the zero sequence current, and Il0 is a noise-contributed zero sequence leakage current. 4. The controller of claim 3 wherein the processor is programmed to calculate the noise-contributed zero sequence leakage current according to:
I l0 =Y 0 *V g0 +k*I 1,
where Vg0 is a zero sequence component of phase-to-ground or phase-to-neutral voltage, I1 is a positive sequence current, and Y0 and k are constants calibrated to the AC electrical machine upon initialization of a phase-to-ground fault detection algorithm. 5. The controller of claim 2 wherein, when the AC electrical machine is a delta-connected electrical machine, the processor is programmed to calculate the FSI according to:
I 0PG=3*(I s0−Ilo)=Ifca +I fab +I fbc
where Ifca, Ifab, Ifbc are phase-to-ground fault currents, Is0 is the zero sequence current, and Il0 is a zero sequence leakage current. 6. The controller of claim 1 wherein, in computing the at least one of the zero sequence component and the negative sequence component of voltage and current, the processor is programmed to compute the negative sequence component of voltage and current, with a total value, noise-contributed value, and compensated value of the negative sequence current being determined. 7. The controller of claim 6 wherein, when the AC electrical machine is a star-connected electrical machine, the processor is programmed to calculate the FSI according to:
I 2PG=3*(I s2 −I m2)=Ifa +a 2 I fb +I fc
where Ifa, Ifb, Ifc are phase-to-ground fault currents, Is2 is the negative sequence current, Im2 is a noise-contributed negative sequence current, and a is an angle notation. 8. The controller of claim 7 wherein the processor is programmed to calculate the noise-contributed negative sequence current according to:
I m2 =k 1 *V 1 +k 2 *I 1 +k 3 *V 2
where V1 is a positive sequence voltage, I1 is a positive sequence current, V2 is a negative sequence voltage, and k1, k2, k3 are constants that relate V1, I1 and V2, respectively, to Im2, and that are calibrated to the AC electrical machine upon initialization of a phase-to-ground fault detection algorithm. 9. The controller of claim 6 wherein, when the AC electrical machine is a delta-connected electrical machine, the processor is programmed to calculate the FSI according to:
I 2PG=3*(I s2 −I m2)=I fca +a 2Ifab +aI fbc
where Ifca, Ifab, Ifbc are phase-to-ground fault currents, Is2 is the negative sequence current, Im2 is a noise-contributed zero sequence current, and a is an angle notation. 10. The controller of claim 1 wherein the processor is further programmed to identify a phase-to-ground fault in the AC electrical machine without input from a current transformer or other sensing device that measures current flowing to ground. 11. The controller of claim 1 wherein the processor is further programmed to:
compare the calculated FSI to a FSI threshold value; and
if the calculated FSI is greater than the FSI threshold value, then indicate that a phase-to-ground fault is present in the AC electrical machine. 12. A method for identifying a phase-to-ground fault in an AC electrical machine, the method comprising:
measuring three-phase voltages and currents provided to the AC electrical machine by way of voltage and current sensors, the AC electrical machine comprising a plurality of stator windings; and causing a fault detector to identify a phase-to-ground fault in the AC electrical machine, wherein causing the fault detector to identify the phase-to-ground fault comprises:
receiving the measured three-phase voltages and currents provided to the AC electrical machine;
determining one or more of a zero sequence current and a negative sequence current from the three-phase currents;
performing a noise-based compensation of the one or more of the zero sequence current and the negative sequence current to produce one or more of a residual zero sequence current and residual negative sequence current representative of a phase-to-ground current; and
identifying a phase-to-ground fault in the AC electrical machine based on the one or more of the residual zero sequence current and the residual negative sequence current. 13. The method of claim 12 wherein the one or more of the residual zero sequence current and the residual negative sequence current comprises a fault severity index (FSI). 14. The method of claim 13 further comprising:
comparing the FSI to a FSI threshold value; and
identifying a phase-to-ground fault in the AC electrical machine when the FSI is greater than the FSI threshold value. 15. The method of claim 12 wherein performing the noise-based compensation of the one or more of the zero sequence current and the negative sequence current comprises:
determining a total value of the one or more of the zero sequence current and the negative sequence current;
determining a noise-contributed value of the one or more of the zero sequence current and the negative sequence current included in the total value; and
determining the one or more of the residual zero sequence current and the residual negative sequence current based on the total value and the noise-contributed value. 16. The method of claim 15 wherein, when determining the one or more of the zero sequence current and the negative sequence current comprises determining the zero sequence current, the noise-contributed value of the zero sequence current is determined according to:
I l0 =Y 0 *V g0 +k*I 1
where Vg0 is a zero sequence component of phase-to-ground or phase-to-neutral voltage, I1 is a positive sequence current, and Y0 and k are constants calibrated to the AC electrical machine upon initialization of a phase-to-ground fault detection algorithm. 17. The method of claim 15 wherein, when determining the one or more of the zero sequence current and the negative sequence current comprises determining the negative sequence current, the noise-contributed value of the negative sequence current is determined according to:
Im2 =k 1 *V 1 +k 2 *I 1 +k 3 *V 2
where V1 is a positive sequence voltage, I1 is a positive sequence current, V2 is a negative sequence voltage, and k1, k2, k3 are constants that relate V1, I1 and V2, respectively, to Im2, and that are calibrated to the AC electrical machine upon initialization of a phase-to-ground fault detection algorithm. 18. A fault detector for detecting a phase-to-ground fault in an AC electrical machine, the fault detector comprising a processor programmed to:
receive an input comprising three-phase voltages and currents provided to the AC electrical machine; determine one or more of a zero sequence current and a negative sequence current from the three-phase currents; perform a noise-based compensation of the one or more of the zero sequence current and the negative sequence current to produce one or more of a residual zero sequence current and residual negative sequence current representative of a phase-to-ground current; and identify a phase-to-ground fault in the AC electrical machine based on the one or more of the residual zero sequence current and the residual negative sequence current. 19. The fault detector of claim 18 wherein the processor is programmed to:
determine a total value of the one or more of the zero sequence current and the negative sequence current;
determine a noise-contributed value of the one or more of the zero sequence current and the negative sequence current included in the total value; and
determine the one or more of the residual zero sequence current and the residual negative sequence current based on the total value and the noise-contributed value. 20. The fault detector of claim 18 wherein the noise-contributed value of the one or more of the zero sequence current and the negative sequence current is specific to the AC electrical machine and is derived from a plurality of motor constants determined at a start-up of the AC electrical machine and from one of a phase-to-ground voltage, phase-to-neutral voltage, or line-to-line voltage. | A system and method for detecting a phase-to-ground fault in an AC electrical machine operates to receive measurements of three-phase voltages and currents provided to the AC electrical machine, compute at least one of a zero sequence component and a negative sequence component of voltage and current from the three-phase voltages and currents, and calculate a fault severity index (F SI) based on the zero or negative sequence component of voltage and current, so as to identify a phase-to-ground fault in the AC electrical machine. Calculating the FSI further includes determining a total value of the zero or negative sequence current, determining a noise-contributed value of the zero or negative sequence current included in the total value, determining a compensated value of the zero or negative sequence current based on the total value and the noise-contributed value, and calculating the FSI based on the compensated value.1. A controller configured to detect a phase-to-ground fault in an AC electrical machine, the controller comprising a processor programmed to:
receive measurements of three-phase voltages and currents provided to the AC electrical machine, the measurements being received from voltage and current sensors associated with the electrical distribution circuit; compute at least one of a zero sequence component and a negative sequence component of voltage and current from the three-phase voltages and currents; and calculate a fault severity index (F SI) based on the at least one of the zero sequence component and the negative sequence component of voltage and current, so as to identify a phase-to-ground fault in the AC electrical machine, wherein calculating the FSI comprises:
determining a total value of at least one of a zero sequence current and a negative sequence current;
determining a noise-contributed value of the at least one of the zero sequence current and the negative sequence current included in the total value;
determining a compensated value of the at least one of the zero sequence current and the negative sequence current based on the total value and the noise-contributed value; and
calculating the FSI based on the compensated value. 2. The controller of claim 1 wherein, in computing the at least one of the zero sequence component and the negative sequence component of voltage and current, the processor is programmed to compute the zero sequence component of voltage and current, with a total value, noise-contributed value, and compensated value of the zero sequence current being determined. 3. The controller of claim 2 wherein, when the AC electrical machine is a star-connected electrical machine, the processor is programmed to calculate the FSI according to:
I 0PG=3*(I s0 −I l0)=I fa +I fb +I fc,
where Ifa, Ifb, Ifc are phase-to-ground fault currents, Is0 is the zero sequence current, and Il0 is a noise-contributed zero sequence leakage current. 4. The controller of claim 3 wherein the processor is programmed to calculate the noise-contributed zero sequence leakage current according to:
I l0 =Y 0 *V g0 +k*I 1,
where Vg0 is a zero sequence component of phase-to-ground or phase-to-neutral voltage, I1 is a positive sequence current, and Y0 and k are constants calibrated to the AC electrical machine upon initialization of a phase-to-ground fault detection algorithm. 5. The controller of claim 2 wherein, when the AC electrical machine is a delta-connected electrical machine, the processor is programmed to calculate the FSI according to:
I 0PG=3*(I s0−Ilo)=Ifca +I fab +I fbc
where Ifca, Ifab, Ifbc are phase-to-ground fault currents, Is0 is the zero sequence current, and Il0 is a zero sequence leakage current. 6. The controller of claim 1 wherein, in computing the at least one of the zero sequence component and the negative sequence component of voltage and current, the processor is programmed to compute the negative sequence component of voltage and current, with a total value, noise-contributed value, and compensated value of the negative sequence current being determined. 7. The controller of claim 6 wherein, when the AC electrical machine is a star-connected electrical machine, the processor is programmed to calculate the FSI according to:
I 2PG=3*(I s2 −I m2)=Ifa +a 2 I fb +I fc
where Ifa, Ifb, Ifc are phase-to-ground fault currents, Is2 is the negative sequence current, Im2 is a noise-contributed negative sequence current, and a is an angle notation. 8. The controller of claim 7 wherein the processor is programmed to calculate the noise-contributed negative sequence current according to:
I m2 =k 1 *V 1 +k 2 *I 1 +k 3 *V 2
where V1 is a positive sequence voltage, I1 is a positive sequence current, V2 is a negative sequence voltage, and k1, k2, k3 are constants that relate V1, I1 and V2, respectively, to Im2, and that are calibrated to the AC electrical machine upon initialization of a phase-to-ground fault detection algorithm. 9. The controller of claim 6 wherein, when the AC electrical machine is a delta-connected electrical machine, the processor is programmed to calculate the FSI according to:
I 2PG=3*(I s2 −I m2)=I fca +a 2Ifab +aI fbc
where Ifca, Ifab, Ifbc are phase-to-ground fault currents, Is2 is the negative sequence current, Im2 is a noise-contributed zero sequence current, and a is an angle notation. 10. The controller of claim 1 wherein the processor is further programmed to identify a phase-to-ground fault in the AC electrical machine without input from a current transformer or other sensing device that measures current flowing to ground. 11. The controller of claim 1 wherein the processor is further programmed to:
compare the calculated FSI to a FSI threshold value; and
if the calculated FSI is greater than the FSI threshold value, then indicate that a phase-to-ground fault is present in the AC electrical machine. 12. A method for identifying a phase-to-ground fault in an AC electrical machine, the method comprising:
measuring three-phase voltages and currents provided to the AC electrical machine by way of voltage and current sensors, the AC electrical machine comprising a plurality of stator windings; and causing a fault detector to identify a phase-to-ground fault in the AC electrical machine, wherein causing the fault detector to identify the phase-to-ground fault comprises:
receiving the measured three-phase voltages and currents provided to the AC electrical machine;
determining one or more of a zero sequence current and a negative sequence current from the three-phase currents;
performing a noise-based compensation of the one or more of the zero sequence current and the negative sequence current to produce one or more of a residual zero sequence current and residual negative sequence current representative of a phase-to-ground current; and
identifying a phase-to-ground fault in the AC electrical machine based on the one or more of the residual zero sequence current and the residual negative sequence current. 13. The method of claim 12 wherein the one or more of the residual zero sequence current and the residual negative sequence current comprises a fault severity index (FSI). 14. The method of claim 13 further comprising:
comparing the FSI to a FSI threshold value; and
identifying a phase-to-ground fault in the AC electrical machine when the FSI is greater than the FSI threshold value. 15. The method of claim 12 wherein performing the noise-based compensation of the one or more of the zero sequence current and the negative sequence current comprises:
determining a total value of the one or more of the zero sequence current and the negative sequence current;
determining a noise-contributed value of the one or more of the zero sequence current and the negative sequence current included in the total value; and
determining the one or more of the residual zero sequence current and the residual negative sequence current based on the total value and the noise-contributed value. 16. The method of claim 15 wherein, when determining the one or more of the zero sequence current and the negative sequence current comprises determining the zero sequence current, the noise-contributed value of the zero sequence current is determined according to:
I l0 =Y 0 *V g0 +k*I 1
where Vg0 is a zero sequence component of phase-to-ground or phase-to-neutral voltage, I1 is a positive sequence current, and Y0 and k are constants calibrated to the AC electrical machine upon initialization of a phase-to-ground fault detection algorithm. 17. The method of claim 15 wherein, when determining the one or more of the zero sequence current and the negative sequence current comprises determining the negative sequence current, the noise-contributed value of the negative sequence current is determined according to:
Im2 =k 1 *V 1 +k 2 *I 1 +k 3 *V 2
where V1 is a positive sequence voltage, I1 is a positive sequence current, V2 is a negative sequence voltage, and k1, k2, k3 are constants that relate V1, I1 and V2, respectively, to Im2, and that are calibrated to the AC electrical machine upon initialization of a phase-to-ground fault detection algorithm. 18. A fault detector for detecting a phase-to-ground fault in an AC electrical machine, the fault detector comprising a processor programmed to:
receive an input comprising three-phase voltages and currents provided to the AC electrical machine; determine one or more of a zero sequence current and a negative sequence current from the three-phase currents; perform a noise-based compensation of the one or more of the zero sequence current and the negative sequence current to produce one or more of a residual zero sequence current and residual negative sequence current representative of a phase-to-ground current; and identify a phase-to-ground fault in the AC electrical machine based on the one or more of the residual zero sequence current and the residual negative sequence current. 19. The fault detector of claim 18 wherein the processor is programmed to:
determine a total value of the one or more of the zero sequence current and the negative sequence current;
determine a noise-contributed value of the one or more of the zero sequence current and the negative sequence current included in the total value; and
determine the one or more of the residual zero sequence current and the residual negative sequence current based on the total value and the noise-contributed value. 20. The fault detector of claim 18 wherein the noise-contributed value of the one or more of the zero sequence current and the negative sequence current is specific to the AC electrical machine and is derived from a plurality of motor constants determined at a start-up of the AC electrical machine and from one of a phase-to-ground voltage, phase-to-neutral voltage, or line-to-line voltage. | 2,800 |
11,944 | 11,944 | 15,468,992 | 2,865 | Machine health can be monitored using multiple sensors. For example, a computing device can determine a target sensor to monitor from among multiple sensors associated with the machine. The computing device can determine magnitude values for a particular component of a time series associated with the target sensor. The computing device can generate a dataset including the magnitude values for the particular component of the time series and the sensor measurements from the multiple sensors. The computing device can generate a model using the dataset. The computing device can then receive additional sensor-measurements from the multiple sensors and use the model to determine a predicted magnitude-value for the particular component of the time series based on the additional sensor-measurements. The computing device can use the predicted magnitude-value to identify an anomaly with the machine. | 1. A system comprising:
a machine; a plurality of sensors coupled to the machine for detecting characteristics of the machine; a processing device communicatively coupled to the plurality of sensors; and a memory device on which instructions executable by the processing device are stored for causing the processing device to:
receive sensor measurements from the plurality of sensors, the sensor measurements being usable as data points to form respective time series associated with respective sensors of the plurality of sensors;
determine a target sensor to monitor from among the plurality of sensors for detecting an anomaly with the machine;
determine magnitude values for a particular component of a time series associated with the target sensor by decomposing the time series into a plurality of components;
generate a dataset comprising the magnitude values for the particular component of the time series and the sensor measurements from the plurality of sensors;
generate a model using the dataset by assigning respective weights to each respective sensor of the plurality of sensors indicating how the sensor measurements from the respective sensor contribute to the magnitude values for the particular component of the time series associated with the target sensor, the model being representative of a relationship between (i) the sensor measurements from the plurality of sensors, and (ii) the magnitude values for the particular component of the time series associated with the target sensor;
receive additional sensor measurements from a subset of the plurality of sensors that excludes the target sensor;
use the model to determine a predicted magnitude value for the particular component of the time series associated with the target sensor based on the additional sensor measurements;
identify the anomaly with the machine by determining that (i) the predicted magnitude value of the particular component meets or exceeds a predetermined threshold; or (ii) multiple predicted magnitude values for the particular component comprise a predetermined pattern that is indicative of the anomaly; and
based on identifying the anomaly, output a notification indicative of the anomaly. 2. The system of claim 1, wherein the particular component of the time series is at least one of a cycle component, a seasonal component, a trend component, or a noise component. 3. The system of claim 2, wherein the memory device further includes instructions that are executable by the processing device for causing the processing device to perform an operation configured to reduce a likelihood of the anomaly occurring. 4. The system of claim 1, wherein the memory device further includes instructions that are executable by the processing device for causing the processing device to generate the dataset by creating a table having a plurality of entries, each entry of the plurality of entries comprising (i) a respective time; (ii) a respective magnitude value for the particular component of the time series at the respective time; and (iii) respective sensor measurements taken at the respective time by each of the respective sensors of the plurality of sensors. 5. The system of claim 1, wherein the memory device further includes instructions that are executable by the processing device for causing the processing device to generate the model using Chi-square correlation to determine the respective weights for each respective sensor of the plurality of sensors. 6. The system of claim 1, wherein the memory device further includes instructions that are executable by the processing device for causing the processing device to generate the model by performing a regression analysis using the dataset. 7. The system of claim 1, wherein the memory device further includes instructions that are executable by the processing device for causing the processing device to generate the model by:
dividing the dataset into a training dataset and a validation dataset; training a classifier using the training dataset; and determining an accuracy of the classifier using the validation dataset. 8. The system of claim 1, wherein the memory device further includes instructions that are executable by the processing device for causing the processing device to generate the dataset by normalizing the time series formed from the sensor measurements to use a common time interval by:
determining which respective time series has data recorded at a smallest time interval; determining that the smallest time interval is to be the common time interval; and adjusting a remainder of the time series to use the common time interval. 9. The system of claim 1, wherein the memory device further includes instructions that are executable by the processing device for causing the processing device to decompose the time series into the plurality of components by decomposing the time series using at least one of additive decomposition, multiplicative decomposition, an exponential-smoothing model, an autoregressive integrated moving-average model, an unobserved-components model, a singular spectrum analysis model, or an intermittent-demand model. 10. The system of claim 1, wherein the time series associated with the target sensor is (i) an intermittent time-series in which a majority of the magnitude values of the data points are zero, or (ii) a count series in which all of the magnitude values of the data points are non-negative integers. 11. A non-transitory computer readable medium comprising program code that is executable by a processing device for causing the processing device to:
receive sensor measurements from a plurality of sensors that detect characteristics of the machine, the sensor measurements being usable as data points to form respective time series associated with respective sensors of the plurality of sensors; determine a target sensor to monitor from among the plurality of sensors for detecting an anomaly with the machine; determine magnitude values for a particular component of a time series associated with the target sensor by decomposing the time series into a plurality of components; generate a dataset comprising the magnitude values for the particular component of the time series and the sensor measurements from the plurality of sensors; generate a model using the dataset by assigning respective weights to each respective sensor of the plurality of sensors indicating how the sensor measurements from the respective sensor contribute to the magnitude values for the particular component of the time series associated with the target sensor, the model being representative of a relationship between (i) the sensor measurements from the plurality of sensors, and (ii) the magnitude values for the particular component of the time series associated with the target sensor; receive additional sensor measurements from a subset of the plurality of sensors that excludes the target sensor; use the model to determine a predicted magnitude value for the particular component of the time series associated with the target sensor based on the additional sensor measurements; identify the anomaly with the machine by determining that (i) the predicted magnitude value of the particular component meets or exceeds a predetermined threshold; or (ii) multiple predicted magnitude values for the particular component comprise a predetermined pattern that is indicative of the anomaly; and based on identifying the anomaly, output a notification indicative of the anomaly. 12. The non-transitory computer readable medium of claim 11, wherein the particular component of the time series is at least one of a cycle component, a seasonal component, a trend component, or a noise component. 13. The non-transitory computer readable medium of claim 12, further comprising program code that is executable by the processing device for causing the processing device to perform an operation configured to reduce a likelihood of the anomaly occurring. 14. The non-transitory computer readable medium of claim 11, further comprising program code that is executable by the processing device for causing the processing device to generate the dataset by creating a table having a plurality of entries, each entry of the plurality of entries comprising (i) a respective time; (ii) a respective magnitude value for the particular component of the time series at the respective time; and (iii) respective sensor measurements taken at the respective time by each of the respective sensors of the plurality of sensors. 15. The non-transitory computer readable medium of claim 11, further comprising program code that is executable by the processing device for causing the processing device to generate the model using Chi-square correlation to determine the respective weights for each respective sensor of the plurality of sensors. 16. The non-transitory computer readable medium of claim 11, further comprising program code that is executable by the processing device for causing the processing device to generate the model by performing a regression analysis using the dataset. 17. The non-transitory computer readable medium of claim 11, further comprising program code that is executable by the processing device for causing the processing device to generate the model by:
dividing the dataset into a training dataset and a validation dataset; training a classifier using the training dataset; and determining an accuracy of the classifier using the validation dataset. 18. The non-transitory computer readable medium of claim 11, further comprising program code that is executable by the processing device for causing the processing device to generate the dataset by normalizing the time series formed from the sensor measurements to use a common time interval by:
determining which respective time series has data recorded at a smallest time interval; determining that the smallest time interval is to be the common time interval; and adjusting a remainder of the time series to use the common time interval. 19. The non-transitory computer readable medium of claim 11, further comprising program code that is executable by the processing device for causing the processing device to decompose the time series into the plurality of components by decomposing the time series using at least one of additive decomposition, multiplicative decomposition, an exponential-smoothing model, an autoregressive integrated moving-average model, an unobserved-components model, a singular spectrum analysis model, or an intermittent-demand model. 20. The non-transitory computer readable medium of claim 11, wherein the time series associated with the target sensor is (i) an intermittent time-series in which a majority of the magnitude values of the data points are zero, or (ii) a count series in which all of the magnitude values of the data points are non-negative integers. 21. A method for performing real-time monitoring of a machine, the method comprising:
receiving sensor measurements from a plurality of sensors that detect characteristics of the machine, the sensor measurements being usable as data points to form respective time series associated with respective sensors of the plurality of sensors; determining a target sensor to monitor from among the plurality of sensors for detecting an anomaly with the machine; determining, by a processor, magnitude values for a particular component of a time series associated with the target sensor by decomposing the time series into a plurality of components; generating, by the processor, a dataset comprising the magnitude values for the particular component of the time series and the sensor measurements from the plurality of sensors; generating, by the processor, a model using the dataset by assigning respective weights to each respective sensor of the plurality of sensors indicating how the sensor measurements from the respective sensor contribute to the magnitude values for the particular component of the time series associated with the target sensor, the model being representative of a relationship between (i) the sensor measurements from the plurality of sensors, and (ii) the magnitude values for the particular component of the time series associated with the target sensor; receiving, by the processor, additional sensor measurements from a subset of the plurality of sensors that excludes the target sensor; using, by the processor, the model to determine a predicted magnitude value for the particular component of the time series associated with the target sensor based on the additional sensor measurements; identifying, by the processor, the anomaly with the machine by determining that (i) the predicted magnitude value of the particular component meets or exceeds a predetermined threshold; or (ii) multiple predicted magnitude values for the particular component comprise a predetermined pattern that is indicative of the anomaly; and based on identifying the anomaly, outputting, a notification indicative of the anomaly. 22. The method of claim 21, wherein the particular component of the time series is at least one of a cycle component, a seasonal component, a trend component, or a noise component. 23. The method of claim 22, further comprising performing an operation configured to reduce a likelihood of the anomaly occurring. 24. The method of claim 21, wherein generating the dataset comprises creating a table having a plurality of entries, each entry of the plurality of entries comprising (i) a respective time; (ii) a respective magnitude value for the particular component of the time series at the respective time; and (iii) respective sensor measurements taken at the respective time by each of the respective sensors of the plurality of sensors. 25. The method of claim 21, wherein generating the model comprises using Chi-square correlation to determine the respective weights for each respective sensor of the plurality of sensors. 26. The method of claim 21, wherein generating the model comprises performing a regression analysis using the dataset. 27. The method of claim 21, wherein generating the model comprises:
dividing the dataset into a training dataset and a validation dataset; training a classifier using the training dataset; and determining an accuracy of the classifier using the validation dataset. 28. The method of claim 21, wherein generating the dataset comprises normalizing the time series formed from the sensor measurements to use a common time interval by:
determining which respective time series has data recorded at a smallest time interval; determining that the smallest time interval is to be the common time interval; and adjusting a remainder of the time series to use the common time interval. 29. The method of claim 21, wherein decomposing the time series into the plurality of components comprises decomposing the time series using at least one of additive decomposition, multiplicative decomposition, an exponential-smoothing model, an autoregressive integrated moving-average model, an unobserved-components model, a singular spectrum analysis model, or an intermittent-demand model. 30. The method of claim 21, wherein the time series associated with the target sensor is (i) an intermittent time-series in which a majority of the magnitude values of the data points are zero, or (ii) a count series in which all of the magnitude values of the data points are non-negative integers. | Machine health can be monitored using multiple sensors. For example, a computing device can determine a target sensor to monitor from among multiple sensors associated with the machine. The computing device can determine magnitude values for a particular component of a time series associated with the target sensor. The computing device can generate a dataset including the magnitude values for the particular component of the time series and the sensor measurements from the multiple sensors. The computing device can generate a model using the dataset. The computing device can then receive additional sensor-measurements from the multiple sensors and use the model to determine a predicted magnitude-value for the particular component of the time series based on the additional sensor-measurements. The computing device can use the predicted magnitude-value to identify an anomaly with the machine.1. A system comprising:
a machine; a plurality of sensors coupled to the machine for detecting characteristics of the machine; a processing device communicatively coupled to the plurality of sensors; and a memory device on which instructions executable by the processing device are stored for causing the processing device to:
receive sensor measurements from the plurality of sensors, the sensor measurements being usable as data points to form respective time series associated with respective sensors of the plurality of sensors;
determine a target sensor to monitor from among the plurality of sensors for detecting an anomaly with the machine;
determine magnitude values for a particular component of a time series associated with the target sensor by decomposing the time series into a plurality of components;
generate a dataset comprising the magnitude values for the particular component of the time series and the sensor measurements from the plurality of sensors;
generate a model using the dataset by assigning respective weights to each respective sensor of the plurality of sensors indicating how the sensor measurements from the respective sensor contribute to the magnitude values for the particular component of the time series associated with the target sensor, the model being representative of a relationship between (i) the sensor measurements from the plurality of sensors, and (ii) the magnitude values for the particular component of the time series associated with the target sensor;
receive additional sensor measurements from a subset of the plurality of sensors that excludes the target sensor;
use the model to determine a predicted magnitude value for the particular component of the time series associated with the target sensor based on the additional sensor measurements;
identify the anomaly with the machine by determining that (i) the predicted magnitude value of the particular component meets or exceeds a predetermined threshold; or (ii) multiple predicted magnitude values for the particular component comprise a predetermined pattern that is indicative of the anomaly; and
based on identifying the anomaly, output a notification indicative of the anomaly. 2. The system of claim 1, wherein the particular component of the time series is at least one of a cycle component, a seasonal component, a trend component, or a noise component. 3. The system of claim 2, wherein the memory device further includes instructions that are executable by the processing device for causing the processing device to perform an operation configured to reduce a likelihood of the anomaly occurring. 4. The system of claim 1, wherein the memory device further includes instructions that are executable by the processing device for causing the processing device to generate the dataset by creating a table having a plurality of entries, each entry of the plurality of entries comprising (i) a respective time; (ii) a respective magnitude value for the particular component of the time series at the respective time; and (iii) respective sensor measurements taken at the respective time by each of the respective sensors of the plurality of sensors. 5. The system of claim 1, wherein the memory device further includes instructions that are executable by the processing device for causing the processing device to generate the model using Chi-square correlation to determine the respective weights for each respective sensor of the plurality of sensors. 6. The system of claim 1, wherein the memory device further includes instructions that are executable by the processing device for causing the processing device to generate the model by performing a regression analysis using the dataset. 7. The system of claim 1, wherein the memory device further includes instructions that are executable by the processing device for causing the processing device to generate the model by:
dividing the dataset into a training dataset and a validation dataset; training a classifier using the training dataset; and determining an accuracy of the classifier using the validation dataset. 8. The system of claim 1, wherein the memory device further includes instructions that are executable by the processing device for causing the processing device to generate the dataset by normalizing the time series formed from the sensor measurements to use a common time interval by:
determining which respective time series has data recorded at a smallest time interval; determining that the smallest time interval is to be the common time interval; and adjusting a remainder of the time series to use the common time interval. 9. The system of claim 1, wherein the memory device further includes instructions that are executable by the processing device for causing the processing device to decompose the time series into the plurality of components by decomposing the time series using at least one of additive decomposition, multiplicative decomposition, an exponential-smoothing model, an autoregressive integrated moving-average model, an unobserved-components model, a singular spectrum analysis model, or an intermittent-demand model. 10. The system of claim 1, wherein the time series associated with the target sensor is (i) an intermittent time-series in which a majority of the magnitude values of the data points are zero, or (ii) a count series in which all of the magnitude values of the data points are non-negative integers. 11. A non-transitory computer readable medium comprising program code that is executable by a processing device for causing the processing device to:
receive sensor measurements from a plurality of sensors that detect characteristics of the machine, the sensor measurements being usable as data points to form respective time series associated with respective sensors of the plurality of sensors; determine a target sensor to monitor from among the plurality of sensors for detecting an anomaly with the machine; determine magnitude values for a particular component of a time series associated with the target sensor by decomposing the time series into a plurality of components; generate a dataset comprising the magnitude values for the particular component of the time series and the sensor measurements from the plurality of sensors; generate a model using the dataset by assigning respective weights to each respective sensor of the plurality of sensors indicating how the sensor measurements from the respective sensor contribute to the magnitude values for the particular component of the time series associated with the target sensor, the model being representative of a relationship between (i) the sensor measurements from the plurality of sensors, and (ii) the magnitude values for the particular component of the time series associated with the target sensor; receive additional sensor measurements from a subset of the plurality of sensors that excludes the target sensor; use the model to determine a predicted magnitude value for the particular component of the time series associated with the target sensor based on the additional sensor measurements; identify the anomaly with the machine by determining that (i) the predicted magnitude value of the particular component meets or exceeds a predetermined threshold; or (ii) multiple predicted magnitude values for the particular component comprise a predetermined pattern that is indicative of the anomaly; and based on identifying the anomaly, output a notification indicative of the anomaly. 12. The non-transitory computer readable medium of claim 11, wherein the particular component of the time series is at least one of a cycle component, a seasonal component, a trend component, or a noise component. 13. The non-transitory computer readable medium of claim 12, further comprising program code that is executable by the processing device for causing the processing device to perform an operation configured to reduce a likelihood of the anomaly occurring. 14. The non-transitory computer readable medium of claim 11, further comprising program code that is executable by the processing device for causing the processing device to generate the dataset by creating a table having a plurality of entries, each entry of the plurality of entries comprising (i) a respective time; (ii) a respective magnitude value for the particular component of the time series at the respective time; and (iii) respective sensor measurements taken at the respective time by each of the respective sensors of the plurality of sensors. 15. The non-transitory computer readable medium of claim 11, further comprising program code that is executable by the processing device for causing the processing device to generate the model using Chi-square correlation to determine the respective weights for each respective sensor of the plurality of sensors. 16. The non-transitory computer readable medium of claim 11, further comprising program code that is executable by the processing device for causing the processing device to generate the model by performing a regression analysis using the dataset. 17. The non-transitory computer readable medium of claim 11, further comprising program code that is executable by the processing device for causing the processing device to generate the model by:
dividing the dataset into a training dataset and a validation dataset; training a classifier using the training dataset; and determining an accuracy of the classifier using the validation dataset. 18. The non-transitory computer readable medium of claim 11, further comprising program code that is executable by the processing device for causing the processing device to generate the dataset by normalizing the time series formed from the sensor measurements to use a common time interval by:
determining which respective time series has data recorded at a smallest time interval; determining that the smallest time interval is to be the common time interval; and adjusting a remainder of the time series to use the common time interval. 19. The non-transitory computer readable medium of claim 11, further comprising program code that is executable by the processing device for causing the processing device to decompose the time series into the plurality of components by decomposing the time series using at least one of additive decomposition, multiplicative decomposition, an exponential-smoothing model, an autoregressive integrated moving-average model, an unobserved-components model, a singular spectrum analysis model, or an intermittent-demand model. 20. The non-transitory computer readable medium of claim 11, wherein the time series associated with the target sensor is (i) an intermittent time-series in which a majority of the magnitude values of the data points are zero, or (ii) a count series in which all of the magnitude values of the data points are non-negative integers. 21. A method for performing real-time monitoring of a machine, the method comprising:
receiving sensor measurements from a plurality of sensors that detect characteristics of the machine, the sensor measurements being usable as data points to form respective time series associated with respective sensors of the plurality of sensors; determining a target sensor to monitor from among the plurality of sensors for detecting an anomaly with the machine; determining, by a processor, magnitude values for a particular component of a time series associated with the target sensor by decomposing the time series into a plurality of components; generating, by the processor, a dataset comprising the magnitude values for the particular component of the time series and the sensor measurements from the plurality of sensors; generating, by the processor, a model using the dataset by assigning respective weights to each respective sensor of the plurality of sensors indicating how the sensor measurements from the respective sensor contribute to the magnitude values for the particular component of the time series associated with the target sensor, the model being representative of a relationship between (i) the sensor measurements from the plurality of sensors, and (ii) the magnitude values for the particular component of the time series associated with the target sensor; receiving, by the processor, additional sensor measurements from a subset of the plurality of sensors that excludes the target sensor; using, by the processor, the model to determine a predicted magnitude value for the particular component of the time series associated with the target sensor based on the additional sensor measurements; identifying, by the processor, the anomaly with the machine by determining that (i) the predicted magnitude value of the particular component meets or exceeds a predetermined threshold; or (ii) multiple predicted magnitude values for the particular component comprise a predetermined pattern that is indicative of the anomaly; and based on identifying the anomaly, outputting, a notification indicative of the anomaly. 22. The method of claim 21, wherein the particular component of the time series is at least one of a cycle component, a seasonal component, a trend component, or a noise component. 23. The method of claim 22, further comprising performing an operation configured to reduce a likelihood of the anomaly occurring. 24. The method of claim 21, wherein generating the dataset comprises creating a table having a plurality of entries, each entry of the plurality of entries comprising (i) a respective time; (ii) a respective magnitude value for the particular component of the time series at the respective time; and (iii) respective sensor measurements taken at the respective time by each of the respective sensors of the plurality of sensors. 25. The method of claim 21, wherein generating the model comprises using Chi-square correlation to determine the respective weights for each respective sensor of the plurality of sensors. 26. The method of claim 21, wherein generating the model comprises performing a regression analysis using the dataset. 27. The method of claim 21, wherein generating the model comprises:
dividing the dataset into a training dataset and a validation dataset; training a classifier using the training dataset; and determining an accuracy of the classifier using the validation dataset. 28. The method of claim 21, wherein generating the dataset comprises normalizing the time series formed from the sensor measurements to use a common time interval by:
determining which respective time series has data recorded at a smallest time interval; determining that the smallest time interval is to be the common time interval; and adjusting a remainder of the time series to use the common time interval. 29. The method of claim 21, wherein decomposing the time series into the plurality of components comprises decomposing the time series using at least one of additive decomposition, multiplicative decomposition, an exponential-smoothing model, an autoregressive integrated moving-average model, an unobserved-components model, a singular spectrum analysis model, or an intermittent-demand model. 30. The method of claim 21, wherein the time series associated with the target sensor is (i) an intermittent time-series in which a majority of the magnitude values of the data points are zero, or (ii) a count series in which all of the magnitude values of the data points are non-negative integers. | 2,800 |
11,945 | 11,945 | 15,577,738 | 2,834 | A drive device includes an electric motor and a gear unit that is driven by the electric motor. The electric motor has a laminated stator core which includes stator windings and is accommodated in a stator housing. The stator housing has recesses that are axially uninterrupted, i.e. in particular in the direction of the rotor shaft axis, and the stator housing is surrounded, especially radially surrounded, by a housing of the drive device, in particular a tubular housing and/or a cup-shaped housing, and the housing is set apart from the stator housing, in particular such that an especially circulating airflow is able to be provided within the housing, the recesses in particular guiding the airflow through in the axial direction, and the airflow being returned in the opposite direction in the set-apart region between the stator housing part and the housing. | 1-15. (canceled) 16. A drive device, comprising:
a gear unit; and an electric motor adapted to drive the gear unit, the electric motor including a laminated stator core which has stator windings and is accommodated in a stator housing; wherein the stator housing is surrounded by and/or radially surrounded by a housing, a tubular housing, and/or a cup-shaped housing of the drive device, the housing being set apart from the stator housing, the gear unit including a first housing part and a second housing part, the second housing part including a surface having at least one pocket-type depression past which at least a portion of an airflow and/or a circulating airflow is flowable, so that dirt and/or dust from at least a portion of the is able to be deposited in the pocket-type depression of the second housing part; wherein a connection element and/or a screw connects the first housing part to the second housing part, a space region required to operate the connection element using a tool is formed and/or made available by the depression, the tool at least partially engaging in and/or around the connection element and being operable from the direction of the environment, so that the pocket-type depression is open toward an interior region encompassed by the housing. 17. The drive device according to claim 16, wherein the stator housing includes recesses that are axially uninterrupted in a direction of a rotor shaft axis, such that the recesses route the airflow in an axial direction and the airflow is returned in an opposite direction in a set-apart region between the stator housing part and the housing. 18. The drive device according to claim 16, wherein the stator housing includes a continuous casting component, and a drawing direction extends parallel to an axial direction and/or parallel to a direction of a rotor shaft axis. 19. The drive device according to claim 16, wherein the gear unit includes a first housing part and a second housing part, which are connected to each other, the stator housing being screw-connected to the second housing part, and the housing of the drive device being screw-connected to the second housing part. 20. The drive device according to claim 17, wherein the airflow flows from the recesses of the stator housing through individual recesses of the second housing part that are at least partially delimited by fins that project from the second housing part. 21. The drive device according to claim 16, wherein the stator housing is formed of a second material, and the housing is formed of a first material, the first material having a greater thermal conductivity than the second material. 22. The drive device according to claim 16, wherein the stator housing has a coating on a surface and/or an external surface facing the housing, in order to increase an emitted heat output, and/or the housing has a coating on a surface and/or an internal surface facing the stator housing, in order to increase an absorbed heat output. 23. The drive device according to claim 16, wherein the airflow is driven convectively and/or solely convectively. 24. The drive device according to claim 16, wherein at least one fan or two fans adapted to drive the airflow is disposed on a bearing flange of the motor. 25. The drive device according to claim 24, wherein the bearing flange includes a circular base plate section and a separating wall section that is disposed on the base plate section, the separating wall section being adapted to separate the airflow from a space region that surrounds a B-side axial end region of a rotor shaft facing away from the gear unit, or that at least partially surrounds an angle sensor disposed in the end region. 26. The drive device according to claim 24, wherein a bearing of a rotor shaft of the motor is accommodated in the bearing flange. 27. The drive device according to claim 25, wherein the separating wall section has a smaller radial extension in a first peripheral angle direction than in a second peripheral angle direction that differs from the first peripheral angle direction. 28. The drive device according to claim 25, wherein the fan is disposed radially outside the separating wall section, and the fan is set apart from the second peripheral angle direction in the peripheral direction, the peripheral angle section covered by the fan encompassing the first peripheral angle. 29. The drive device according to claim 25, wherein the separating wall section is arranged on an axial side of the base plate section facing away from the gear unit, and/or a projection for axial delimitation of the fan is arranged on the separating wall section. 30. The drive device according to claim 25, wherein the base plate section has at least one and/or two recesses for feedthrough of cables, the stator housing having a coating on a surface facing the housing and/or an external surface, in order to increase emitted heat radiation, and the base plate section includes a central recess adapted to accommodate a stator of an angle sensor. | A drive device includes an electric motor and a gear unit that is driven by the electric motor. The electric motor has a laminated stator core which includes stator windings and is accommodated in a stator housing. The stator housing has recesses that are axially uninterrupted, i.e. in particular in the direction of the rotor shaft axis, and the stator housing is surrounded, especially radially surrounded, by a housing of the drive device, in particular a tubular housing and/or a cup-shaped housing, and the housing is set apart from the stator housing, in particular such that an especially circulating airflow is able to be provided within the housing, the recesses in particular guiding the airflow through in the axial direction, and the airflow being returned in the opposite direction in the set-apart region between the stator housing part and the housing.1-15. (canceled) 16. A drive device, comprising:
a gear unit; and an electric motor adapted to drive the gear unit, the electric motor including a laminated stator core which has stator windings and is accommodated in a stator housing; wherein the stator housing is surrounded by and/or radially surrounded by a housing, a tubular housing, and/or a cup-shaped housing of the drive device, the housing being set apart from the stator housing, the gear unit including a first housing part and a second housing part, the second housing part including a surface having at least one pocket-type depression past which at least a portion of an airflow and/or a circulating airflow is flowable, so that dirt and/or dust from at least a portion of the is able to be deposited in the pocket-type depression of the second housing part; wherein a connection element and/or a screw connects the first housing part to the second housing part, a space region required to operate the connection element using a tool is formed and/or made available by the depression, the tool at least partially engaging in and/or around the connection element and being operable from the direction of the environment, so that the pocket-type depression is open toward an interior region encompassed by the housing. 17. The drive device according to claim 16, wherein the stator housing includes recesses that are axially uninterrupted in a direction of a rotor shaft axis, such that the recesses route the airflow in an axial direction and the airflow is returned in an opposite direction in a set-apart region between the stator housing part and the housing. 18. The drive device according to claim 16, wherein the stator housing includes a continuous casting component, and a drawing direction extends parallel to an axial direction and/or parallel to a direction of a rotor shaft axis. 19. The drive device according to claim 16, wherein the gear unit includes a first housing part and a second housing part, which are connected to each other, the stator housing being screw-connected to the second housing part, and the housing of the drive device being screw-connected to the second housing part. 20. The drive device according to claim 17, wherein the airflow flows from the recesses of the stator housing through individual recesses of the second housing part that are at least partially delimited by fins that project from the second housing part. 21. The drive device according to claim 16, wherein the stator housing is formed of a second material, and the housing is formed of a first material, the first material having a greater thermal conductivity than the second material. 22. The drive device according to claim 16, wherein the stator housing has a coating on a surface and/or an external surface facing the housing, in order to increase an emitted heat output, and/or the housing has a coating on a surface and/or an internal surface facing the stator housing, in order to increase an absorbed heat output. 23. The drive device according to claim 16, wherein the airflow is driven convectively and/or solely convectively. 24. The drive device according to claim 16, wherein at least one fan or two fans adapted to drive the airflow is disposed on a bearing flange of the motor. 25. The drive device according to claim 24, wherein the bearing flange includes a circular base plate section and a separating wall section that is disposed on the base plate section, the separating wall section being adapted to separate the airflow from a space region that surrounds a B-side axial end region of a rotor shaft facing away from the gear unit, or that at least partially surrounds an angle sensor disposed in the end region. 26. The drive device according to claim 24, wherein a bearing of a rotor shaft of the motor is accommodated in the bearing flange. 27. The drive device according to claim 25, wherein the separating wall section has a smaller radial extension in a first peripheral angle direction than in a second peripheral angle direction that differs from the first peripheral angle direction. 28. The drive device according to claim 25, wherein the fan is disposed radially outside the separating wall section, and the fan is set apart from the second peripheral angle direction in the peripheral direction, the peripheral angle section covered by the fan encompassing the first peripheral angle. 29. The drive device according to claim 25, wherein the separating wall section is arranged on an axial side of the base plate section facing away from the gear unit, and/or a projection for axial delimitation of the fan is arranged on the separating wall section. 30. The drive device according to claim 25, wherein the base plate section has at least one and/or two recesses for feedthrough of cables, the stator housing having a coating on a surface facing the housing and/or an external surface, in order to increase emitted heat radiation, and the base plate section includes a central recess adapted to accommodate a stator of an angle sensor. | 2,800 |
11,946 | 11,946 | 13,954,557 | 2,883 | An optical network architecture can include a first pair of tapered mixing rods and a second pair of tapered mixing rods. A first plurality of plastic optical fibers is communicatively coupled from the first pair of tapered mixing rods to a first plurality of line replaceable components, and a second plurality of plastic optical fibers is communicatively coupled from the second pair of tapered mixing rods to a second plurality of line replaceable components. At least one optical fiber communicatively coupled from the first pair of tapered mixing rods to the second pair of tapered mixing rods, the at least one optical transmission line comprising a hard clad silica optical fiber. | 1. An optical network architecture comprising:
a first pair of tapered mixing rods; a second pair of tapered mixing rods; a first plurality of plastic optical fibers communicatively coupled from the first pair of tapered mixing rods to a first plurality of line replaceable units; a second plurality of plastic optical fibers communicatively coupled from the second pair of tapered mixing rods to a second plurality of line replaceable units; and at least one optical fiber communicatively coupled from the first pair of tapered mixing rods to the second pair of tapered mixing rods, the at least one optical fiber comprising a hard clad silica optical fiber. 2. The optical network architecture of claim 1, wherein a first end of the hard clad silica optical fiber is coupled to one of the first pair of mixing rods. 3. The optical network architecture of claim 2, wherein a second end of the hard clad silica optical fiber is coupled to a first end of a plastic optical fiber. 4. The optical network architecture of claim 3, wherein a second end of the plastic optical fiber is coupled to one of the second pair of mixing rods. 5. The optical network architecture of claim 1, wherein a first end of a first plastic optical fiber is coupled to one of the first pair of mixing rods, and wherein a second end of the first plastic optical fiber is coupled to a first end of the hard clad silica optical fiber. 6. The optical network architecture of claim 5, wherein a core diameter of the first plastic optical fiber is larger than a core diameter of the hard clad silica optical fiber. 7. The optical network architecture of claim 6, wherein the second end of the first plastic optical fiber comprises a hemispherical lens configured to direct light from the first plastic optical fiber into the hard clad silica optical fiber. 8. The optical network architecture of claim 5, wherein a first end of a second plastic optical fiber is coupled to a second end of the hard clad silica optical fiber, and wherein a second end of the second plastic optical fiber is coupled to one of the second pair of mixing rods. 9. The optical network architecture of claim 8, wherein a core diameter of the second plastic optical fiber is larger than a core diameter of the hard clad silica optical fiber. 10. A method of transmitting optical signals comprising:
receiving, by a first tapered mixing rod, optical signals from a first plurality of plastic optical fibers communicatively coupled to a first plurality of line replaceable units; directing, by the first tapered mixing rod, the optical signals received from the first plurality of plastic optical fibers along each of a first optical fiber and a second optical fiber; receiving, by a second tapered mixing rod, optical signals from the second optical fiber and a third optical fiber; and directing, by the second tapered mixing rod, the optical signals received from the second optical fiber and the third optical fiber along each of a second plurality of plastic optical fibers communicatively coupled to the first plurality of line replaceable units; wherein each of the first optical fiber and the third optical fiber comprises at least one hard clad silica optical fiber. 11. The method of claim 10, further comprising:
receiving, by a third tapered mixing rod, optical signals from a third plurality of plastic optical fibers communicatively coupled to a second plurality of line replaceable units; directing, by the third tapered mixing rod, the optical signals received from the third plurality of plastic optical fibers along each of the third optical fiber and a fourth optical fiber; receiving, by a fourth tapered mixing rod, optical signals from the first optical fiber and the fourth optical fiber; and directing, by the fourth tapered mixing rod, the optical signals received from the first optical fiber and the fourth optical fiber along each of a fourth plurality of plastic optical fibers communicatively coupled to the second plurality of line replaceable units. 12. The method of claim 11, further comprising:
attenuating optical signals propagating along the fourth optical fiber such that a strength of optical signals received by the fourth tapered mixing rod from the fourth optical fiber and a strength of optical signals received by the fourth tapered mixing rod from the first optical fiber are within a predetermined range of optical signal strengths. 13. The method of claim 12, wherein the attenuating optical signals propagating along the fourth optical fiber is performed by an optical attenuator located on the fourth optical fiber. 14. The method of claim 11, further comprising:
attenuating optical signals propagating along the third optical fiber such that a strength of optical signals received by the second tapered mixing rod from the second optical fiber and a strength of optical signals received by the second tapered mixing rod from the third optical fiber are within a predetermined range of optical signal strengths. 15. The method of claim 14, wherein the third optical fiber further comprises a plastic optical fiber, and wherein the at least one hard clad silica fiber of the third optical fiber and the plastic optical fiber of the third optical fiber are connected in series. 16. The method of claim 15, wherein the attenuating optical signals propagating along the third optical fiber is performed by an optical attenuator, and wherein the optical attenuator is located on one of the plastic optical fiber of the third optical fiber and the at least one hard clad silica fiber of the third optical fiber. 17. An aircraft optical network comprising:
a first pair of tapered mixing rods located at a front end of the aircraft; a second pair of tapered mixing rods located at a back end of the aircraft; a first plurality of plastic optical fibers communicatively coupled from the first pair of tapered mixing rods to a first plurality of line replaceable components, the first plurality of line replaceable components located at the front end of the aircraft; a second plurality of plastic optical fibers communicatively coupled from the second pair of tapered mixing rods to a second plurality of line replaceable components, the second plurality of line replaceable components located at the back end of the aircraft; and at least one optical fiber communicatively coupled from the first pair of tapered mixing rods to the second pair of tapered mixing rods, the at least one optical fiber comprising a hard clad silica optical fiber. 18. The aircraft optical network of claim 17, wherein the first plurality of plastic optical fibers have lengths equal to or less than 20 meters. 19. The aircraft optical network of claim 18, wherein the second plurality of plastic optical fibers have lengths equal to or less than 20 meters. 20. The aircraft optical network of claim 19, wherein the at least one optical fiber has a length in a range from 50 meters to 100 meters. | An optical network architecture can include a first pair of tapered mixing rods and a second pair of tapered mixing rods. A first plurality of plastic optical fibers is communicatively coupled from the first pair of tapered mixing rods to a first plurality of line replaceable components, and a second plurality of plastic optical fibers is communicatively coupled from the second pair of tapered mixing rods to a second plurality of line replaceable components. At least one optical fiber communicatively coupled from the first pair of tapered mixing rods to the second pair of tapered mixing rods, the at least one optical transmission line comprising a hard clad silica optical fiber.1. An optical network architecture comprising:
a first pair of tapered mixing rods; a second pair of tapered mixing rods; a first plurality of plastic optical fibers communicatively coupled from the first pair of tapered mixing rods to a first plurality of line replaceable units; a second plurality of plastic optical fibers communicatively coupled from the second pair of tapered mixing rods to a second plurality of line replaceable units; and at least one optical fiber communicatively coupled from the first pair of tapered mixing rods to the second pair of tapered mixing rods, the at least one optical fiber comprising a hard clad silica optical fiber. 2. The optical network architecture of claim 1, wherein a first end of the hard clad silica optical fiber is coupled to one of the first pair of mixing rods. 3. The optical network architecture of claim 2, wherein a second end of the hard clad silica optical fiber is coupled to a first end of a plastic optical fiber. 4. The optical network architecture of claim 3, wherein a second end of the plastic optical fiber is coupled to one of the second pair of mixing rods. 5. The optical network architecture of claim 1, wherein a first end of a first plastic optical fiber is coupled to one of the first pair of mixing rods, and wherein a second end of the first plastic optical fiber is coupled to a first end of the hard clad silica optical fiber. 6. The optical network architecture of claim 5, wherein a core diameter of the first plastic optical fiber is larger than a core diameter of the hard clad silica optical fiber. 7. The optical network architecture of claim 6, wherein the second end of the first plastic optical fiber comprises a hemispherical lens configured to direct light from the first plastic optical fiber into the hard clad silica optical fiber. 8. The optical network architecture of claim 5, wherein a first end of a second plastic optical fiber is coupled to a second end of the hard clad silica optical fiber, and wherein a second end of the second plastic optical fiber is coupled to one of the second pair of mixing rods. 9. The optical network architecture of claim 8, wherein a core diameter of the second plastic optical fiber is larger than a core diameter of the hard clad silica optical fiber. 10. A method of transmitting optical signals comprising:
receiving, by a first tapered mixing rod, optical signals from a first plurality of plastic optical fibers communicatively coupled to a first plurality of line replaceable units; directing, by the first tapered mixing rod, the optical signals received from the first plurality of plastic optical fibers along each of a first optical fiber and a second optical fiber; receiving, by a second tapered mixing rod, optical signals from the second optical fiber and a third optical fiber; and directing, by the second tapered mixing rod, the optical signals received from the second optical fiber and the third optical fiber along each of a second plurality of plastic optical fibers communicatively coupled to the first plurality of line replaceable units; wherein each of the first optical fiber and the third optical fiber comprises at least one hard clad silica optical fiber. 11. The method of claim 10, further comprising:
receiving, by a third tapered mixing rod, optical signals from a third plurality of plastic optical fibers communicatively coupled to a second plurality of line replaceable units; directing, by the third tapered mixing rod, the optical signals received from the third plurality of plastic optical fibers along each of the third optical fiber and a fourth optical fiber; receiving, by a fourth tapered mixing rod, optical signals from the first optical fiber and the fourth optical fiber; and directing, by the fourth tapered mixing rod, the optical signals received from the first optical fiber and the fourth optical fiber along each of a fourth plurality of plastic optical fibers communicatively coupled to the second plurality of line replaceable units. 12. The method of claim 11, further comprising:
attenuating optical signals propagating along the fourth optical fiber such that a strength of optical signals received by the fourth tapered mixing rod from the fourth optical fiber and a strength of optical signals received by the fourth tapered mixing rod from the first optical fiber are within a predetermined range of optical signal strengths. 13. The method of claim 12, wherein the attenuating optical signals propagating along the fourth optical fiber is performed by an optical attenuator located on the fourth optical fiber. 14. The method of claim 11, further comprising:
attenuating optical signals propagating along the third optical fiber such that a strength of optical signals received by the second tapered mixing rod from the second optical fiber and a strength of optical signals received by the second tapered mixing rod from the third optical fiber are within a predetermined range of optical signal strengths. 15. The method of claim 14, wherein the third optical fiber further comprises a plastic optical fiber, and wherein the at least one hard clad silica fiber of the third optical fiber and the plastic optical fiber of the third optical fiber are connected in series. 16. The method of claim 15, wherein the attenuating optical signals propagating along the third optical fiber is performed by an optical attenuator, and wherein the optical attenuator is located on one of the plastic optical fiber of the third optical fiber and the at least one hard clad silica fiber of the third optical fiber. 17. An aircraft optical network comprising:
a first pair of tapered mixing rods located at a front end of the aircraft; a second pair of tapered mixing rods located at a back end of the aircraft; a first plurality of plastic optical fibers communicatively coupled from the first pair of tapered mixing rods to a first plurality of line replaceable components, the first plurality of line replaceable components located at the front end of the aircraft; a second plurality of plastic optical fibers communicatively coupled from the second pair of tapered mixing rods to a second plurality of line replaceable components, the second plurality of line replaceable components located at the back end of the aircraft; and at least one optical fiber communicatively coupled from the first pair of tapered mixing rods to the second pair of tapered mixing rods, the at least one optical fiber comprising a hard clad silica optical fiber. 18. The aircraft optical network of claim 17, wherein the first plurality of plastic optical fibers have lengths equal to or less than 20 meters. 19. The aircraft optical network of claim 18, wherein the second plurality of plastic optical fibers have lengths equal to or less than 20 meters. 20. The aircraft optical network of claim 19, wherein the at least one optical fiber has a length in a range from 50 meters to 100 meters. | 2,800 |
11,947 | 11,947 | 15,572,308 | 2,845 | A body-wearable antenna system is described that comprises at least two antenna elements ( 2, 4 ) arranged to be mountable in a substantially equi-spaced distributed array around a user's body. Each antenna element is a directional type antenna and the antenna system is configurable such that when worn the antenna elements operate in phase to deliver a combined, higher gain, omnidirectional performance radiating away from the user's body, compared to one or more conventional body-worn omnidirectional antennas. The antenna system can operate in transmit and receive. Each antenna element may be a planar inverted-F antenna (PIFA) housed in a protective radome ( 3, 5 ). Each PIFA may feature at least one slot cut into the radiating top plate or at least one parasitic radiator, or a combination of both, to allow operation within distinct frequency bands and with predetermined impedance bandwidth. | 1. A body-wearable antenna system capable of operating in transmit and receive, comprising at least two antenna elements arranged to be mountable in a substantially equi-spaced distributed array around a user's body, wherein each antenna element is a directional type antenna and wherein the antenna system is configured, in use, such that the antenna elements operate in phase with each other to deliver a combined, higher gain, omnidirectional performance radiating away from the user's body, compared to one or more conventional body-worn omnidirectional antennas. 2. A body-wearable antenna system according to claim 1 wherein each antenna element is a planar type antenna comprising a radiating top plate and a ground plane. 3. A body-wearable antenna system according to claim 2 wherein each antenna element is a planar inverted-F antenna (PIFA). 4. A body-wearable antenna system according to claim 3 wherein the radiating top plate of each PIFA is triangular in shape. 5. A body-wearable antenna system according to claim 3 wherein at least one slot is provided in the radiating top plate of each PIFA. 6. A body-wearable antenna system according to claim 3 wherein at least one parasitic radiator is provided on the ground plane of each PIFA. 7. A body-wearable antenna system according to claim 2 wherein the ground plane of each antenna element is provided with mounting tabs. 8. A body-wearable antenna system according to claim 1 wherein each antenna element is provided with a protective radome. 9. A body-wearable antenna system according to claim 1 wherein each antenna element is flexible. 10. A body-wearable antenna system according to claim 1 wherein each antenna element is provided with an electrical conductor for electrically connecting the antenna element to a power source. 11. A body-wearable antenna system according to claim 1 comprising a power source electrically connected to a power divider, the power divider being electrically connected to the at least two antenna elements. 12. A body-wearable antenna system according to claim 1 further comprising one or more transceivers. 13. A body-wearable antenna system according to claim 1 further comprising a signal processor. 14. A garment incorporating a body-wearable antenna system according to claim 1 wherein the garment comprises at least a first and a second packet substantially equi-spaced around the garment for mounting the antenna elements in a distributed array. 15. (canceled) | A body-wearable antenna system is described that comprises at least two antenna elements ( 2, 4 ) arranged to be mountable in a substantially equi-spaced distributed array around a user's body. Each antenna element is a directional type antenna and the antenna system is configurable such that when worn the antenna elements operate in phase to deliver a combined, higher gain, omnidirectional performance radiating away from the user's body, compared to one or more conventional body-worn omnidirectional antennas. The antenna system can operate in transmit and receive. Each antenna element may be a planar inverted-F antenna (PIFA) housed in a protective radome ( 3, 5 ). Each PIFA may feature at least one slot cut into the radiating top plate or at least one parasitic radiator, or a combination of both, to allow operation within distinct frequency bands and with predetermined impedance bandwidth.1. A body-wearable antenna system capable of operating in transmit and receive, comprising at least two antenna elements arranged to be mountable in a substantially equi-spaced distributed array around a user's body, wherein each antenna element is a directional type antenna and wherein the antenna system is configured, in use, such that the antenna elements operate in phase with each other to deliver a combined, higher gain, omnidirectional performance radiating away from the user's body, compared to one or more conventional body-worn omnidirectional antennas. 2. A body-wearable antenna system according to claim 1 wherein each antenna element is a planar type antenna comprising a radiating top plate and a ground plane. 3. A body-wearable antenna system according to claim 2 wherein each antenna element is a planar inverted-F antenna (PIFA). 4. A body-wearable antenna system according to claim 3 wherein the radiating top plate of each PIFA is triangular in shape. 5. A body-wearable antenna system according to claim 3 wherein at least one slot is provided in the radiating top plate of each PIFA. 6. A body-wearable antenna system according to claim 3 wherein at least one parasitic radiator is provided on the ground plane of each PIFA. 7. A body-wearable antenna system according to claim 2 wherein the ground plane of each antenna element is provided with mounting tabs. 8. A body-wearable antenna system according to claim 1 wherein each antenna element is provided with a protective radome. 9. A body-wearable antenna system according to claim 1 wherein each antenna element is flexible. 10. A body-wearable antenna system according to claim 1 wherein each antenna element is provided with an electrical conductor for electrically connecting the antenna element to a power source. 11. A body-wearable antenna system according to claim 1 comprising a power source electrically connected to a power divider, the power divider being electrically connected to the at least two antenna elements. 12. A body-wearable antenna system according to claim 1 further comprising one or more transceivers. 13. A body-wearable antenna system according to claim 1 further comprising a signal processor. 14. A garment incorporating a body-wearable antenna system according to claim 1 wherein the garment comprises at least a first and a second packet substantially equi-spaced around the garment for mounting the antenna elements in a distributed array. 15. (canceled) | 2,800 |
11,948 | 11,948 | 15,533,514 | 2,864 | In an example, a method of anticipating maintenance in a printing device includes determining an inertial reference signal of a printer carriage and measuring a current inertial signal of the printer carriage. The method includes cross-correlating the inertial reference signal with the current inertial signal and determining from the cross-correlating when the current inertial signal is not within a preset confidence interval of the inertial reference signal. | 1. A method of anticipating maintenance in a printing device, the method comprising:
determining an inertial reference signal of a printer carriage; measuring a current inertial signal of the printer carriage; cross-correlating the inertial reference signal with the current inertial signal; and determining from the cross-correlating when the current inertial signal is not within a preset confidence interval of the inertial reference signal. 2. A method as in claim 1, wherein determining an inertial reference signal comprises accessing the inertial reference signal from a memory of the printing device. 3. A method as in claim 1, wherein determining an inertial reference signal comprises:
measuring an inertial metric value for each of a plurality of scans of the printer carriage; averaging the inertial metric values between the scans of the printer carriage to determine the inertial reference signal; and storing the inertial reference signal in a memory. 4. A method as in claim 3, wherein measuring an inertial metric value comprises measuring a metric selected from the group consisting of acceleration, velocity, and distance. 5. A method as in claim 4, wherein measuring an inertial metric value comprises measuring the inertial metric value of the printer carriage in X, Y, and Z coordinate directions. 6. A method as in claim 1, further comprising:
when the current inertial signal is not within a preset confidence interval of the inertial reference signal, providing a user notification to indicate abnormal movement of the printer carriage. 7. A method as in claim 1, wherein determining from the cross-correlating when the current inertial signal is not within a preset confidence interval of the inertial reference signal comprises determining that the current inertial signal is not within a 95% confidence interval of the inertial reference signal. 8. A method as in claim 1, wherein the inertial reference signal and the current inertial signal comprise acceleration signals of the printer carriage, the method comprising:
measuring the acceleration signals with a device selected from the group consisting of an accelerometer affixed to the printer carriage and a linear encoder associated with a carriage drive motor. 9. A printing device capable of anticipating maintenance, comprising:
an inertial measurement unit (IMU) to measure an inertial component of a carriage as the carriage passes from one edge to another edge of a print media; a sample module to store a carriage pass signal formed from sample values provided by the IMU, the carriage pass signal characterizing movement of the carriage across the print media; and a cross-correlator to cross-correlate the carriage pass signal with a reference signal and determine a malfunction when the carriage pass signal is not within a preset confidence interval of the reference signal. 10. A printing device as in claim 9, further comprising a reporting module to report the malfunction to a user interface. 11. A printing device as in claim 9, further comprising:
a toothed belt to transport the carriage between edges of the print media; and, a carriage motor to drive the toothed belt. 12. A printing device as in claim 11, wherein the IMU comprises a device selected from the group consisting of an accelerometer affixed to the carriage and a linear encoder associated with the carriage motor. 13. A non-transitory processor-readable medium storing code representing instructions that when executed by a processor of a printing device cause the printing device to:
measure an inertial signal of a printer carriage; compare the inertial signal with a reference signal; and anticipate maintenance for the printing device when the inertial signal does not fall within a confidence interval of the reference signal. 14. A non-transitory processor-readable medium as in claim 13, wherein measuring the inertial signal comprises measuring acceleration of the printer carriage as the printer carriage moves across a printable medium. 15. A non-transitory processor-readable medium as in claim 13, wherein comparing the inertial signal with the reference signal comprises comparing the inertial signal with the reference signal by cross-correlating the inertial signal with the reference signal. | In an example, a method of anticipating maintenance in a printing device includes determining an inertial reference signal of a printer carriage and measuring a current inertial signal of the printer carriage. The method includes cross-correlating the inertial reference signal with the current inertial signal and determining from the cross-correlating when the current inertial signal is not within a preset confidence interval of the inertial reference signal.1. A method of anticipating maintenance in a printing device, the method comprising:
determining an inertial reference signal of a printer carriage; measuring a current inertial signal of the printer carriage; cross-correlating the inertial reference signal with the current inertial signal; and determining from the cross-correlating when the current inertial signal is not within a preset confidence interval of the inertial reference signal. 2. A method as in claim 1, wherein determining an inertial reference signal comprises accessing the inertial reference signal from a memory of the printing device. 3. A method as in claim 1, wherein determining an inertial reference signal comprises:
measuring an inertial metric value for each of a plurality of scans of the printer carriage; averaging the inertial metric values between the scans of the printer carriage to determine the inertial reference signal; and storing the inertial reference signal in a memory. 4. A method as in claim 3, wherein measuring an inertial metric value comprises measuring a metric selected from the group consisting of acceleration, velocity, and distance. 5. A method as in claim 4, wherein measuring an inertial metric value comprises measuring the inertial metric value of the printer carriage in X, Y, and Z coordinate directions. 6. A method as in claim 1, further comprising:
when the current inertial signal is not within a preset confidence interval of the inertial reference signal, providing a user notification to indicate abnormal movement of the printer carriage. 7. A method as in claim 1, wherein determining from the cross-correlating when the current inertial signal is not within a preset confidence interval of the inertial reference signal comprises determining that the current inertial signal is not within a 95% confidence interval of the inertial reference signal. 8. A method as in claim 1, wherein the inertial reference signal and the current inertial signal comprise acceleration signals of the printer carriage, the method comprising:
measuring the acceleration signals with a device selected from the group consisting of an accelerometer affixed to the printer carriage and a linear encoder associated with a carriage drive motor. 9. A printing device capable of anticipating maintenance, comprising:
an inertial measurement unit (IMU) to measure an inertial component of a carriage as the carriage passes from one edge to another edge of a print media; a sample module to store a carriage pass signal formed from sample values provided by the IMU, the carriage pass signal characterizing movement of the carriage across the print media; and a cross-correlator to cross-correlate the carriage pass signal with a reference signal and determine a malfunction when the carriage pass signal is not within a preset confidence interval of the reference signal. 10. A printing device as in claim 9, further comprising a reporting module to report the malfunction to a user interface. 11. A printing device as in claim 9, further comprising:
a toothed belt to transport the carriage between edges of the print media; and, a carriage motor to drive the toothed belt. 12. A printing device as in claim 11, wherein the IMU comprises a device selected from the group consisting of an accelerometer affixed to the carriage and a linear encoder associated with the carriage motor. 13. A non-transitory processor-readable medium storing code representing instructions that when executed by a processor of a printing device cause the printing device to:
measure an inertial signal of a printer carriage; compare the inertial signal with a reference signal; and anticipate maintenance for the printing device when the inertial signal does not fall within a confidence interval of the reference signal. 14. A non-transitory processor-readable medium as in claim 13, wherein measuring the inertial signal comprises measuring acceleration of the printer carriage as the printer carriage moves across a printable medium. 15. A non-transitory processor-readable medium as in claim 13, wherein comparing the inertial signal with the reference signal comprises comparing the inertial signal with the reference signal by cross-correlating the inertial signal with the reference signal. | 2,800 |
11,949 | 11,949 | 15,171,404 | 2,855 | An integrated capstan for use in fiber processing and testing apparatus. The integrated capstan features a fiber-engaging material that provides a contact surface for fibers. The hardness of the contact surface is controlled to minimize transfer of stress to the fibers to prevent damage to fiber coatings or fiber splice junctions during conveyance or screen testing of fibers during production. The fiber-engaging material includes a resilient material and an optional capping layer. The resilient material may be a lightly crosslinked polyurethane gel. Capping layers include polymers formed by UV curing of aliphatic urethane diacrylate compounds or moisture curing of diisocyanate compounds. | 1. An integrated capstan comprising:
a capstan; and a fiber-engaging material, said fiber-engaging material formed on the surface of said capstan, said fiber-engaging material having a hardness in the range from 40 Shore 00 to 70 Shore 00. 2. The integrated capstan of claim 1, wherein said capstan includes a channel, said fiber-engaging material occupying said channel. 3. The integrated capstan of claim 1, wherein said fiber-engaging material comprises a polyurethane material. 4. The integrated capstan of claim 3, wherein said polyurethane material comprises the cured product of a formulation that includes an isocyanate component and a hydroxy component. 5. The integrated capstan of claim 4, wherein said isocyanate component includes a di-functional isocyanate compound. 6. The integrated capstan of claim 5, wherein said di-functional isocyanate compound is a polymer containing urethane groups. 7. The integrated capstan of claim 6, wherein said polymer is a polyether. 8. The integrated capstan of claim 5, wherein said isocyanate compound has an isocyanate content in the range from 4 wt % to 12 wt %. 9. The integrated capstan of claim 5, wherein said hydroxy component is a polymer containing hydroxy groups. 10. The integrated capstan of claim 9, wherein said hydroxy groups include terminal and pendant hydroxy groups. 11. The integrated capstan of claim 10, wherein said polymer is polybutadiene. 12. The integrated capstan of claim 3, wherein said polyurethane material has a hardness in the range from 40 Shore 00 to 70 Shore 00. 13. The integrated capstan of claim 3, wherein said fiber-engaging material further comprises a capping layer, said capping layer formed on said polyurethane material. 14. The integrated capstan of claim 13, wherein said capping layer has a hardness within ±10 Shore 00 of the hardness of said polyurethane material. 15. The integrated capstan of claim 14, wherein said capping layer comprises the cured product of a formulation that includes an acrylate compound. 16. The integrated capstan of claim 1, wherein said fiber-engaging material comprises a resilient material and a capping layer formed on said resilient material, said resilient material having a hardness in the range from 40 Shore 00 to 70 Shore 00. 17. The integrated capstan of claim 16, wherein said capping layer has a hardness within ±10 Shore 00 of said hardness of said resilient material. 18. An apparatus for processing an optical fiber comprising;
an integrated capstan, said integrated capstan including a capstan and a fiber-engaging material formed on the surface of said capstan, said fiber-engaging material having a hardness in the range from 40 Shore 00 to 70 Shore 00; and a fiber conveyance pathway, said fiber conveyance pathway positioned adjacent to said integrated capstan such that when said optical fiber is directed along said fiber conveyance pathway, said optical fiber contacts said fiber-engaging material. 19. The apparatus of claim 18, further comprising a pinch belt positioned adjacent to said fiber conveyance pathway, said fiber conveyance pathway extending between at least a portion of said pinch belt and said fiber-engaging material, wherein said pinch belt is engagable with said fiber-engaging material such that when said optical fiber is directed over said fiber conveyance pathway, said optical fiber is impinged between said pinch belt and said fiber-engaging material. 20. A method for screen testing an optical fiber comprising:
drawing an optical fiber along a fiber conveyance pathway; and directing said optical fiber around an integrated capstan, said integrated capstan comprising a capstan and a fiber-engaging material, said fiber-engaging material formed on the surface of said capstan, said fiber-engaging material having a hardness in the range from 40 Shore 00 to 70 Shore 00, said optical fiber contacting said fiber-engaging material. | An integrated capstan for use in fiber processing and testing apparatus. The integrated capstan features a fiber-engaging material that provides a contact surface for fibers. The hardness of the contact surface is controlled to minimize transfer of stress to the fibers to prevent damage to fiber coatings or fiber splice junctions during conveyance or screen testing of fibers during production. The fiber-engaging material includes a resilient material and an optional capping layer. The resilient material may be a lightly crosslinked polyurethane gel. Capping layers include polymers formed by UV curing of aliphatic urethane diacrylate compounds or moisture curing of diisocyanate compounds.1. An integrated capstan comprising:
a capstan; and a fiber-engaging material, said fiber-engaging material formed on the surface of said capstan, said fiber-engaging material having a hardness in the range from 40 Shore 00 to 70 Shore 00. 2. The integrated capstan of claim 1, wherein said capstan includes a channel, said fiber-engaging material occupying said channel. 3. The integrated capstan of claim 1, wherein said fiber-engaging material comprises a polyurethane material. 4. The integrated capstan of claim 3, wherein said polyurethane material comprises the cured product of a formulation that includes an isocyanate component and a hydroxy component. 5. The integrated capstan of claim 4, wherein said isocyanate component includes a di-functional isocyanate compound. 6. The integrated capstan of claim 5, wherein said di-functional isocyanate compound is a polymer containing urethane groups. 7. The integrated capstan of claim 6, wherein said polymer is a polyether. 8. The integrated capstan of claim 5, wherein said isocyanate compound has an isocyanate content in the range from 4 wt % to 12 wt %. 9. The integrated capstan of claim 5, wherein said hydroxy component is a polymer containing hydroxy groups. 10. The integrated capstan of claim 9, wherein said hydroxy groups include terminal and pendant hydroxy groups. 11. The integrated capstan of claim 10, wherein said polymer is polybutadiene. 12. The integrated capstan of claim 3, wherein said polyurethane material has a hardness in the range from 40 Shore 00 to 70 Shore 00. 13. The integrated capstan of claim 3, wherein said fiber-engaging material further comprises a capping layer, said capping layer formed on said polyurethane material. 14. The integrated capstan of claim 13, wherein said capping layer has a hardness within ±10 Shore 00 of the hardness of said polyurethane material. 15. The integrated capstan of claim 14, wherein said capping layer comprises the cured product of a formulation that includes an acrylate compound. 16. The integrated capstan of claim 1, wherein said fiber-engaging material comprises a resilient material and a capping layer formed on said resilient material, said resilient material having a hardness in the range from 40 Shore 00 to 70 Shore 00. 17. The integrated capstan of claim 16, wherein said capping layer has a hardness within ±10 Shore 00 of said hardness of said resilient material. 18. An apparatus for processing an optical fiber comprising;
an integrated capstan, said integrated capstan including a capstan and a fiber-engaging material formed on the surface of said capstan, said fiber-engaging material having a hardness in the range from 40 Shore 00 to 70 Shore 00; and a fiber conveyance pathway, said fiber conveyance pathway positioned adjacent to said integrated capstan such that when said optical fiber is directed along said fiber conveyance pathway, said optical fiber contacts said fiber-engaging material. 19. The apparatus of claim 18, further comprising a pinch belt positioned adjacent to said fiber conveyance pathway, said fiber conveyance pathway extending between at least a portion of said pinch belt and said fiber-engaging material, wherein said pinch belt is engagable with said fiber-engaging material such that when said optical fiber is directed over said fiber conveyance pathway, said optical fiber is impinged between said pinch belt and said fiber-engaging material. 20. A method for screen testing an optical fiber comprising:
drawing an optical fiber along a fiber conveyance pathway; and directing said optical fiber around an integrated capstan, said integrated capstan comprising a capstan and a fiber-engaging material, said fiber-engaging material formed on the surface of said capstan, said fiber-engaging material having a hardness in the range from 40 Shore 00 to 70 Shore 00, said optical fiber contacting said fiber-engaging material. | 2,800 |
11,950 | 11,950 | 15,381,229 | 2,835 | An electronic apparatus includes a display subassembly including display device that visually presents information and a connector, a base subassembly including a housing having a connector recess that receives the connector of the display subassembly, and one or more processors that control presentation of the information on the display subassembly. The connector of the display subassembly is sized to be at least partially received into the connector recess of the base subassembly to connect the display subassembly with the base subassembly while allowing the display subassembly to pivot relative to the base subassembly. | 1. An electronic apparatus comprising:
a display subassembly including display device that visually presents information and a connector; a base subassembly including a housing having a connector recess that receives the connector of the display subassembly; and one or more processors that control presentation of the information on the display subassembly, wherein the connector of the display subassembly is sized to be at least partially received into the connector recess of the base subassembly to connect the display subassembly with the base subassembly while allowing the display subassembly to pivot relative to the base subassembly. 2. The electronic apparatus of claim 1, wherein the connector of the display subassembly and the connector recess of the base subassembly include conductive contacts positioned to engage each other and transfer electric current between the display subassembly and the base subassembly. 3. The electronic apparatus of claim 1, wherein the connector recess of the base subassembly is located at an interface between different exterior sides of the housing of the base subassembly. 4. The electronic apparatus of claim 1, wherein the display subassembly includes a housing extending between opposite first and second edges, and wherein the connector is coupled with the housing of the display subassembly in a location that is closer to the first edge than the second edge. 5. The electronic apparatus of claim 1, wherein the connector and the connector recess include magnets to secure the connector to the connector recess. 6. The electronic apparatus of claim 1, wherein the connector and the connector recess are sized to secure to each other by a friction fit. 7. The electronic apparatus of claim 1, wherein the connector has a cylindrical shape and the connector recess has a complementary shape to receive the cylindrical shape of the connector. 8. The electronic apparatus of claim 1, wherein the connector has a flat shape and the connector recess has a complementary slot shape to receive the flat shape of the connector. 9. The electronic apparatus of claim 1, wherein the connector is shaped to pivot within and relative to the connector recess. 10. An electronic subassembly comprising:
a housing having a connector recess that receives a connector of a display subassembly; and one or more processors that control presentation of information on the display subassembly, wherein the connector recess of the housing is sized to at least partially receive the connector of the display subassembly to connect the display subassembly with the one or more processors while allowing the display subassembly to pivot relative to the housing. 11. The electronic subassembly of claim 10, wherein the connector recess includes a conductive contact positioned to engage a conductive contact of the connector of the display subassembly. 12. The electronic subassembly of claim 10, wherein the connector recess is located at an interface between different exterior sides of the housing. 13. The electronic subassembly of claim 10, wherein the connector recess includes a magnet that secures the connector of the display subassembly to the connector recess. 14. The electronic subassembly of claim 10, wherein the connector recess is sized to be secured with the connector of the display subassembly by a friction fit. 15. The electronic subassembly of claim 10, wherein the connector recess has a cylindrical shape to receive a cylindrical shape of the connector of the display subassembly. 16. The electronic subassembly of claim 10, wherein the connector recess has a slot shape to receive a flat shape of the connector of the display subassembly. 17. The electronic subassembly of claim 10, wherein the connector recess is shaped to receive the connector of the display subassembly and allow the connector to pivot within and relative to the connector recess. 18. An electronic subassembly comprising:
a display device that visually presents information; a housing with one or more processors that control presentation of the information on the display device; and a connector sized to be at least partially received into a connector recess of a base subassembly to connect the housing with the base subassembly while allowing the housing to pivot relative to the base subassembly. 19. The electronic subassembly of claim 18, wherein the connector includes a conductive contact positioned to engage a conductive contact in the connector recess of the base subassembly. 20. The electronic subassembly of claim 18, wherein the housing extends between opposite first and second edges, and wherein the connector is coupled with the housing in a location that is closer to the first edge than the second edge. | An electronic apparatus includes a display subassembly including display device that visually presents information and a connector, a base subassembly including a housing having a connector recess that receives the connector of the display subassembly, and one or more processors that control presentation of the information on the display subassembly. The connector of the display subassembly is sized to be at least partially received into the connector recess of the base subassembly to connect the display subassembly with the base subassembly while allowing the display subassembly to pivot relative to the base subassembly.1. An electronic apparatus comprising:
a display subassembly including display device that visually presents information and a connector; a base subassembly including a housing having a connector recess that receives the connector of the display subassembly; and one or more processors that control presentation of the information on the display subassembly, wherein the connector of the display subassembly is sized to be at least partially received into the connector recess of the base subassembly to connect the display subassembly with the base subassembly while allowing the display subassembly to pivot relative to the base subassembly. 2. The electronic apparatus of claim 1, wherein the connector of the display subassembly and the connector recess of the base subassembly include conductive contacts positioned to engage each other and transfer electric current between the display subassembly and the base subassembly. 3. The electronic apparatus of claim 1, wherein the connector recess of the base subassembly is located at an interface between different exterior sides of the housing of the base subassembly. 4. The electronic apparatus of claim 1, wherein the display subassembly includes a housing extending between opposite first and second edges, and wherein the connector is coupled with the housing of the display subassembly in a location that is closer to the first edge than the second edge. 5. The electronic apparatus of claim 1, wherein the connector and the connector recess include magnets to secure the connector to the connector recess. 6. The electronic apparatus of claim 1, wherein the connector and the connector recess are sized to secure to each other by a friction fit. 7. The electronic apparatus of claim 1, wherein the connector has a cylindrical shape and the connector recess has a complementary shape to receive the cylindrical shape of the connector. 8. The electronic apparatus of claim 1, wherein the connector has a flat shape and the connector recess has a complementary slot shape to receive the flat shape of the connector. 9. The electronic apparatus of claim 1, wherein the connector is shaped to pivot within and relative to the connector recess. 10. An electronic subassembly comprising:
a housing having a connector recess that receives a connector of a display subassembly; and one or more processors that control presentation of information on the display subassembly, wherein the connector recess of the housing is sized to at least partially receive the connector of the display subassembly to connect the display subassembly with the one or more processors while allowing the display subassembly to pivot relative to the housing. 11. The electronic subassembly of claim 10, wherein the connector recess includes a conductive contact positioned to engage a conductive contact of the connector of the display subassembly. 12. The electronic subassembly of claim 10, wherein the connector recess is located at an interface between different exterior sides of the housing. 13. The electronic subassembly of claim 10, wherein the connector recess includes a magnet that secures the connector of the display subassembly to the connector recess. 14. The electronic subassembly of claim 10, wherein the connector recess is sized to be secured with the connector of the display subassembly by a friction fit. 15. The electronic subassembly of claim 10, wherein the connector recess has a cylindrical shape to receive a cylindrical shape of the connector of the display subassembly. 16. The electronic subassembly of claim 10, wherein the connector recess has a slot shape to receive a flat shape of the connector of the display subassembly. 17. The electronic subassembly of claim 10, wherein the connector recess is shaped to receive the connector of the display subassembly and allow the connector to pivot within and relative to the connector recess. 18. An electronic subassembly comprising:
a display device that visually presents information; a housing with one or more processors that control presentation of the information on the display device; and a connector sized to be at least partially received into a connector recess of a base subassembly to connect the housing with the base subassembly while allowing the housing to pivot relative to the base subassembly. 19. The electronic subassembly of claim 18, wherein the connector includes a conductive contact positioned to engage a conductive contact in the connector recess of the base subassembly. 20. The electronic subassembly of claim 18, wherein the housing extends between opposite first and second edges, and wherein the connector is coupled with the housing in a location that is closer to the first edge than the second edge. | 2,800 |
11,951 | 11,951 | 15,049,833 | 2,822 | A system and method is provided for enhancing hydrocarbon production. The method and system involve geochemistry analysis and include multiply substituted isotopologue and position specific isotope geochemistry. The method and system involve using clumped isotope and position-specific isotope signatures to enhance reservoir surveillance operations. | 1. A method for enhancing hydrocarbon production comprising:
providing a field deployable system in fluid communication with a subsurface formation, wherein the field deployable system is configured to determine a geochemical signature of a sample based on clumped isotope and/or position specific isotope geochemistry analysis; obtaining one or more hydrocarbon samples from the subsurface formation at a first time and analyzing each of the hydrocarbon samples with the field deployable system to determine a baseline geochemical signature, wherein the baseline geochemical signature is based on clumped isotope and/or position specific isotope geochemistry analysis; obtaining one or more hydrocarbon sample from the subsurface formation at a second time, wherein the second time is after the first time and analyzing each of the hydrocarbon samples with the field deployable system to determine a monitored geochemical signature, wherein the monitored geochemical signature is based on clumped isotope and/or position specific isotope geochemistry analysis; comparing the monitored geochemical signature with the baseline geochemical signature; and adjusting an exploration, development, or production strategy based on the comparison. 2. The method of claim 1, wherein
analyzing each of the hydrocarbon samples collected at the first time from the subsurface formation for the baseline geochemical signature comprises converting each baseline geochemical signature into a baseline temperature; analyzing each for the hydrocarbon samples collected at the second time from the subsurface formation for the monitored geochemical signature comprises converting the monitored geochemical signatures into a monitored temperature; and comparing the monitored geochemical signature with the baseline geochemical signature comprises comparing the monitored temperature with the baseline temperature. 3. The method of claim 1, comprising identifying a source contribution for the monitored geochemical signature based on the baseline geochemical signature. 4. The method of claim 1, wherein the second time is from 1 hour to 3 hours after the first time. 5. The method of claim 1 wherein the second time is based on a specified event. 6. The method of claim 5, wherein the specified event is the detection of elevated hydrocarbon presence from a monitoring module. 7. The method of claim 6, wherein the monitoring module comprises monitoring for changes in the mixture of hydrocarbon and non-hydrocarbon compounds in the sample. 8. The method of claim 7, wherein the monitoring module comprises monitoring for changes in the relative amounts of methane, ethane, carbon dioxide, and nitrogen in the sample. 9. The method of claim 6, wherein the monitoring module comprises monitoring for stable isotope geochemistry changes in one or more of carbon, hydrogen, nitrogen, and sulfur. 10. The method of claim 6, wherein the monitoring module comprises monitoring using mud gas and or produced gas sampling techniques to provide a quantitative analysis of certain hydrocarbon components. 11. The method of claim 6, wherein the monitoring module comprises monitoring changes in the produced gas. 12. The method of claim 6, wherein the specified event is a change in oil field operations. 13. A system for enhancing hydrocarbon production, comprising:
a field deployable system in fluid communication with a subsurface formation, wherein the field deployable system comprises:
a processor;
an input device in communication with the processor and configured to receive input data associated with a subsurface formation;
memory in communication with the processor, the memory having a set of instructions, wherein the set of instructions, when executed, are configured to:
analyze one or more hydrocarbon samples taken from the subsurface formation at a first time for a baseline geochemical signature, wherein the baseline geochemical signature is based on clumped isotope and/or position specific isotope geochemistry analysis;
analyze one or more hydrocarbon samples taken from the subsurface location at a later time for a monitored geochemical signature, wherein the monitored geochemical signature is based on clumped isotope and/or position specific isotope geochemistry analysis;
compare the monitored geochemical signature with the baseline geochemical signature; and
an output device that outputs the comparison. 14. The system of claim 13, wherein the set of instructions are further configured to:
adjust an exploration, development or production strategies based on the comparison; and display the adjusted an exploration, development or production strategies. 15. The system of claim 13, wherein the set of instructions are further configured to:
convert the baseline geochemical signature into a baseline temperature; and convert the monitored geochemical signature into a monitored temperature; and compare the monitored temperature with the baseline temperature. 16. The system of claim 13, wherein the set of instructions are further configured to:
convert the baseline geochemical signature into a baseline composition; and convert the monitored geochemical signature into a monitored composition; and compare the monitored composition with the baseline composition. 17. The system of claim 13, wherein the set of instructions are further configured to: identify a source contribution for the monitored geochemical signature based on the baseline geochemical signature. 18. The system of claim 13, further comprising a monitoring module in fluid communication with a subsurface formation and the field deployable system; the monitoring module comprising:
a processor; an input device in communication with the processor and configured to receive input data associated with a subsurface formation; memory in communication with the processor, the memory having a set of instructions, wherein the set of instructions, when executed, are configured to: monitor produced fluids from the subsurface formation; and detect a specified event in the produced fluids. 19. The system of claim 18, wherein the set of instructions are further configured to:
detect elevated hydrocarbon presence from produced fluids; and transmit a notification to the field deployable system to analyze sample data obtained from the subsurface location at a later time for a monitored geochemical signature. 20. The system of claim 18, wherein the set of instructions are further configured to: monitor for molecular changes in the produced fluids of one or more of methane, ethane, carbon dioxide, and nitrogen. 21. The system of claim 18, wherein the set of instructions are further configured to: monitor for bulk changes in mixtures of gases in the produced fluids. 22. The system of claim 18, wherein the set of instructions are further configured to: monitor for stable isotope geochemistry changes in the produced fluid in one or more of carbon, hydrogen, nitrogen, and sulfur. | A system and method is provided for enhancing hydrocarbon production. The method and system involve geochemistry analysis and include multiply substituted isotopologue and position specific isotope geochemistry. The method and system involve using clumped isotope and position-specific isotope signatures to enhance reservoir surveillance operations.1. A method for enhancing hydrocarbon production comprising:
providing a field deployable system in fluid communication with a subsurface formation, wherein the field deployable system is configured to determine a geochemical signature of a sample based on clumped isotope and/or position specific isotope geochemistry analysis; obtaining one or more hydrocarbon samples from the subsurface formation at a first time and analyzing each of the hydrocarbon samples with the field deployable system to determine a baseline geochemical signature, wherein the baseline geochemical signature is based on clumped isotope and/or position specific isotope geochemistry analysis; obtaining one or more hydrocarbon sample from the subsurface formation at a second time, wherein the second time is after the first time and analyzing each of the hydrocarbon samples with the field deployable system to determine a monitored geochemical signature, wherein the monitored geochemical signature is based on clumped isotope and/or position specific isotope geochemistry analysis; comparing the monitored geochemical signature with the baseline geochemical signature; and adjusting an exploration, development, or production strategy based on the comparison. 2. The method of claim 1, wherein
analyzing each of the hydrocarbon samples collected at the first time from the subsurface formation for the baseline geochemical signature comprises converting each baseline geochemical signature into a baseline temperature; analyzing each for the hydrocarbon samples collected at the second time from the subsurface formation for the monitored geochemical signature comprises converting the monitored geochemical signatures into a monitored temperature; and comparing the monitored geochemical signature with the baseline geochemical signature comprises comparing the monitored temperature with the baseline temperature. 3. The method of claim 1, comprising identifying a source contribution for the monitored geochemical signature based on the baseline geochemical signature. 4. The method of claim 1, wherein the second time is from 1 hour to 3 hours after the first time. 5. The method of claim 1 wherein the second time is based on a specified event. 6. The method of claim 5, wherein the specified event is the detection of elevated hydrocarbon presence from a monitoring module. 7. The method of claim 6, wherein the monitoring module comprises monitoring for changes in the mixture of hydrocarbon and non-hydrocarbon compounds in the sample. 8. The method of claim 7, wherein the monitoring module comprises monitoring for changes in the relative amounts of methane, ethane, carbon dioxide, and nitrogen in the sample. 9. The method of claim 6, wherein the monitoring module comprises monitoring for stable isotope geochemistry changes in one or more of carbon, hydrogen, nitrogen, and sulfur. 10. The method of claim 6, wherein the monitoring module comprises monitoring using mud gas and or produced gas sampling techniques to provide a quantitative analysis of certain hydrocarbon components. 11. The method of claim 6, wherein the monitoring module comprises monitoring changes in the produced gas. 12. The method of claim 6, wherein the specified event is a change in oil field operations. 13. A system for enhancing hydrocarbon production, comprising:
a field deployable system in fluid communication with a subsurface formation, wherein the field deployable system comprises:
a processor;
an input device in communication with the processor and configured to receive input data associated with a subsurface formation;
memory in communication with the processor, the memory having a set of instructions, wherein the set of instructions, when executed, are configured to:
analyze one or more hydrocarbon samples taken from the subsurface formation at a first time for a baseline geochemical signature, wherein the baseline geochemical signature is based on clumped isotope and/or position specific isotope geochemistry analysis;
analyze one or more hydrocarbon samples taken from the subsurface location at a later time for a monitored geochemical signature, wherein the monitored geochemical signature is based on clumped isotope and/or position specific isotope geochemistry analysis;
compare the monitored geochemical signature with the baseline geochemical signature; and
an output device that outputs the comparison. 14. The system of claim 13, wherein the set of instructions are further configured to:
adjust an exploration, development or production strategies based on the comparison; and display the adjusted an exploration, development or production strategies. 15. The system of claim 13, wherein the set of instructions are further configured to:
convert the baseline geochemical signature into a baseline temperature; and convert the monitored geochemical signature into a monitored temperature; and compare the monitored temperature with the baseline temperature. 16. The system of claim 13, wherein the set of instructions are further configured to:
convert the baseline geochemical signature into a baseline composition; and convert the monitored geochemical signature into a monitored composition; and compare the monitored composition with the baseline composition. 17. The system of claim 13, wherein the set of instructions are further configured to: identify a source contribution for the monitored geochemical signature based on the baseline geochemical signature. 18. The system of claim 13, further comprising a monitoring module in fluid communication with a subsurface formation and the field deployable system; the monitoring module comprising:
a processor; an input device in communication with the processor and configured to receive input data associated with a subsurface formation; memory in communication with the processor, the memory having a set of instructions, wherein the set of instructions, when executed, are configured to: monitor produced fluids from the subsurface formation; and detect a specified event in the produced fluids. 19. The system of claim 18, wherein the set of instructions are further configured to:
detect elevated hydrocarbon presence from produced fluids; and transmit a notification to the field deployable system to analyze sample data obtained from the subsurface location at a later time for a monitored geochemical signature. 20. The system of claim 18, wherein the set of instructions are further configured to: monitor for molecular changes in the produced fluids of one or more of methane, ethane, carbon dioxide, and nitrogen. 21. The system of claim 18, wherein the set of instructions are further configured to: monitor for bulk changes in mixtures of gases in the produced fluids. 22. The system of claim 18, wherein the set of instructions are further configured to: monitor for stable isotope geochemistry changes in the produced fluid in one or more of carbon, hydrogen, nitrogen, and sulfur. | 2,800 |
11,952 | 11,952 | 15,001,187 | 2,837 | Embodiments described herein provide devices, systems, and techniques for generating a magnetic field pattern that includes a plurality of magnetic poles. In specific embodiments, a magnetic device is disclosed which generates a magnetic field pattern including two magnetic poles of the same polarity on both ends, or sides of the magnetic device, and a third magnetic pole of a different polarity from the other two magnetic poles, wherein the third magnetic pole is located inside the magnetic device and between the other two magnetic poles. Moreover, the magnetic device is configured with two openings located at the two transition boundaries/interfaces of the three-pole magnetic field. As such, the two transition boundaries become accessible to objects. In particular, when another magnet is inserted at an interface between two magnetic poles, the magnet will “register” right at the interface and hover over or be suspended at the opening of the magnetic device. | 1. A magnetic device, comprising:
a base that includes an upper surface, a lower surface, and an inner wall and an outer wall that are sandwiched between the upper surface and the lower surface,
wherein the upper surface includes a first opening defined by the upper edge of the inner wall, the lower surface includes a second opening defined by the lower edge of the inner wall; and
wherein the base further includes a set of magnet placement locations between the inner wall and the outer wall, and arranged around the base; and
a set of magnets placed around the inner wall, such that each of the magnets is placed at a magnet placement location among the set of magnet placement locations, wherein each of the magnets is positioned such that an axis of the magnet connecting the north pole and the south pole of the magnet forms an angle with respect to the upper and lower surfaces, wherein the set of magnets generates three primary fields: a first field of a first polarity formed substantially between the upper surface and the lower surface inside the base, a second field of a second polarity formed outward from the first opening of the base and on a first side of the first field, and a third field of the second polarity formed outward from the second opening of the base and on a second side of the first field opposite to the first side. 2. The magnetic device of claim 1, wherein the set of magnet placement locations includes two locations. 3. The magnetic device of claim 1, wherein the set of magnet placement locations includes three or more locations. 4. The magnetic device of claim 1, wherein the set of magnets is a continuous magnetic structure around the inner wall. 5. The magnetic device of claim 1, wherein an upper portion of each of the magnet placement locations is thinner than a lower portion of the magnet placement location. 6. The magnetic device of claim 1, wherein each magnet within the set of magnets includes a surface in the vicinity of the inner wall which has an angular shape. 7. The magnetic device of claim 1, wherein the set of magnet placement locations are substantially flat on the inner wall and configured to accommodate surface mounting magnets. 8. The magnetic device of claim 1, wherein the region of magnetic influence of the second field can be significantly larger than the region of magnetic influence of the third field. 9. The magnetic device of claim 1, the sizes and geometries of the first and second openings are configured to control the region of magnetic influence of each of the second field and the third field. 10. The magnetic device of claim 1,
wherein the north pole of each magnet faces the center of the base whereas the south pole of the magnet faces away from the center of the base; and wherein the first field of the first polarity is magnetic south and wherein the second field and the third field of the second polarity is magnetic north. 11. The magnetic device of claim 1,
wherein the south pole of each magnet faces the center of the base whereas the north pole of the magnet faces away from the center of the base; and wherein the first field of the first polarity is magnetic north and wherein the second field and the third field of the second polarity is magnetic south. 12. The magnetic device of claim 1, wherein the first pole of the magnet facing the center of the base is positioned closer to the upper surface of the base while the second pole of the magnet facing away from the center of the base is positioned closer to the lower surface of the base. 13. The magnetic device of claim 1, wherein the angle formed between the axis of the magnet connecting the north pole and the south pole of the magnet, and the upper and lower surfaces is between 0 and 90 degrees. 14. The magnetic device of claim 1, wherein the inner wall of the base has a parabolic shape or an angled shape. 15. The magnetic device of claim 1, wherein a surface of each magnet has a parabolic shape, an angular shape or a flat shape. 16. The magnetic device of claim 1, wherein the first field of the first polarity is located substantially within the space surrounded by the first opening, the second opening, and the inner wall. 17. The magnetic device of claim 1, wherein a first transition boundary between the first field of the first polarity and the second field of the second polarity is in the vicinity of the first opening of the base, and wherein a second transition boundary between the first field and the third field of the second polarity is in the vicinity of the second opening of the base. 18. The magnetic device of claim 17, wherein each of the first and second transition boundaries is accessible to an object such that when a magnet is inserted at the first or the second transition boundary, the magnet hovers or registers at the transition boundary. 19. The magnetic device of claim 18, wherein the magnetic device is configured such that if a pressure is applied to the hovering magnet and then released, the magnet inclines to return to substantially the same location. 20. The magnetic device of claim 18, wherein the combination of the magnet and the magnetic device is used to create transducers, valves, speakers, microphones, and pumps. 21. The magnetic device of claim 1, each of the magnets is a permanent magnet, an electromagnetic magnet, a superconducting magnet, or a combination of the above. 22. The magnetic device of claim 1, wherein the base further includes a gap formed into the solid ring structure of the base which connects the space in the center of the base and the space outside the base. 23. A device for propelling a magnetic object from a first location to a second location, comprising:
a first magnetic field generator configured to generate a first magnetic field pattern comprising a first magnetic field of a first polarity, and a second magnetic field and a third magnetic field both of a second polarity and located on either side of the first magnetic field; and a second magnetic field generator coupled in series with the first magnetic field generator and configured to generate a second magnetic field pattern which is substantially identical to the first magnetic field pattern, wherein the first and the second magnetic field patterns form a combined linear field pattern having first-second-first-first-second-first polarities, and wherein the combined linear field pattern causes a magnetic object to enter from a first end of the combined linear field pattern, traverse each of the magnetic field in the combined linear field pattern, and exit from a second end of the combined linear field pattern, as a result of the magnetic interaction between the magnetic object and the combined linear field pattern. 24. The device of claim 23, wherein the first polarity is magnetic north and the second polarity is magnetic south. 25. The device of claim 23, wherein the first polarity is magnetic south and the second polarity is magnetic north. 26. The device of claim 23, wherein each of the first and second magnetic field generators comprises:
a base including an upper surface, a lower surface, and an inner wall and an outer wall that are sandwiched between the upper surface and the lower surface, wherein the upper surface includes a first opening defined by the upper edge of the inner wall, the lower surface includes a second opening defined by the lower edge of the inner wall; and a set of magnets placed to cover a portion of the inner wall, wherein each of the magnets is positioned such that an axis of the magnet connecting the north pole and the south pole of the magnet forms an angle with respect to the upper and lower surfaces. 27. The device of claim 26, wherein the set of magnets are placed inside a set of recessed locations within the inner wall of the base. 28. The device of claim 26, wherein the set of magnets are mounted on the surface of the inner wall of the base. 29. The device of claim 26, wherein each of the set of magnets located in or around the inner wall has a trapezoid, circular, square, and/or triangular geometry. 30. The device of claim 26, wherein the set of magnets includes two or more magnets. 31. The device of claim 26, wherein the first magnetic field of a first polarity is formed substantially between the upper surface and the lower surface inside the base, the second magnetic field of the second polarity is formed outward from the first opening of the base, and the third magnetic field of the second polarity is formed outward from the second opening of the base and on the opposite side of the first magnetic field. 32. The device of claim 26, further comprising one or more additional magnetic field generators coupled in series with the first and second magnetic field generators and configured to generate one or more additional magnetic field patterns which are substantially identical to the first and second magnetic field patterns. 33. The device of claim 32, wherein the first, the second, and the one or more additional magnetic field generators form a linear array for propelling the magnetic object in a linear path. 34. The device of claim 32, wherein the first, the second, and the one or more additional magnetic field generators form a circular array for propelling the magnetic object in a circular path. | Embodiments described herein provide devices, systems, and techniques for generating a magnetic field pattern that includes a plurality of magnetic poles. In specific embodiments, a magnetic device is disclosed which generates a magnetic field pattern including two magnetic poles of the same polarity on both ends, or sides of the magnetic device, and a third magnetic pole of a different polarity from the other two magnetic poles, wherein the third magnetic pole is located inside the magnetic device and between the other two magnetic poles. Moreover, the magnetic device is configured with two openings located at the two transition boundaries/interfaces of the three-pole magnetic field. As such, the two transition boundaries become accessible to objects. In particular, when another magnet is inserted at an interface between two magnetic poles, the magnet will “register” right at the interface and hover over or be suspended at the opening of the magnetic device.1. A magnetic device, comprising:
a base that includes an upper surface, a lower surface, and an inner wall and an outer wall that are sandwiched between the upper surface and the lower surface,
wherein the upper surface includes a first opening defined by the upper edge of the inner wall, the lower surface includes a second opening defined by the lower edge of the inner wall; and
wherein the base further includes a set of magnet placement locations between the inner wall and the outer wall, and arranged around the base; and
a set of magnets placed around the inner wall, such that each of the magnets is placed at a magnet placement location among the set of magnet placement locations, wherein each of the magnets is positioned such that an axis of the magnet connecting the north pole and the south pole of the magnet forms an angle with respect to the upper and lower surfaces, wherein the set of magnets generates three primary fields: a first field of a first polarity formed substantially between the upper surface and the lower surface inside the base, a second field of a second polarity formed outward from the first opening of the base and on a first side of the first field, and a third field of the second polarity formed outward from the second opening of the base and on a second side of the first field opposite to the first side. 2. The magnetic device of claim 1, wherein the set of magnet placement locations includes two locations. 3. The magnetic device of claim 1, wherein the set of magnet placement locations includes three or more locations. 4. The magnetic device of claim 1, wherein the set of magnets is a continuous magnetic structure around the inner wall. 5. The magnetic device of claim 1, wherein an upper portion of each of the magnet placement locations is thinner than a lower portion of the magnet placement location. 6. The magnetic device of claim 1, wherein each magnet within the set of magnets includes a surface in the vicinity of the inner wall which has an angular shape. 7. The magnetic device of claim 1, wherein the set of magnet placement locations are substantially flat on the inner wall and configured to accommodate surface mounting magnets. 8. The magnetic device of claim 1, wherein the region of magnetic influence of the second field can be significantly larger than the region of magnetic influence of the third field. 9. The magnetic device of claim 1, the sizes and geometries of the first and second openings are configured to control the region of magnetic influence of each of the second field and the third field. 10. The magnetic device of claim 1,
wherein the north pole of each magnet faces the center of the base whereas the south pole of the magnet faces away from the center of the base; and wherein the first field of the first polarity is magnetic south and wherein the second field and the third field of the second polarity is magnetic north. 11. The magnetic device of claim 1,
wherein the south pole of each magnet faces the center of the base whereas the north pole of the magnet faces away from the center of the base; and wherein the first field of the first polarity is magnetic north and wherein the second field and the third field of the second polarity is magnetic south. 12. The magnetic device of claim 1, wherein the first pole of the magnet facing the center of the base is positioned closer to the upper surface of the base while the second pole of the magnet facing away from the center of the base is positioned closer to the lower surface of the base. 13. The magnetic device of claim 1, wherein the angle formed between the axis of the magnet connecting the north pole and the south pole of the magnet, and the upper and lower surfaces is between 0 and 90 degrees. 14. The magnetic device of claim 1, wherein the inner wall of the base has a parabolic shape or an angled shape. 15. The magnetic device of claim 1, wherein a surface of each magnet has a parabolic shape, an angular shape or a flat shape. 16. The magnetic device of claim 1, wherein the first field of the first polarity is located substantially within the space surrounded by the first opening, the second opening, and the inner wall. 17. The magnetic device of claim 1, wherein a first transition boundary between the first field of the first polarity and the second field of the second polarity is in the vicinity of the first opening of the base, and wherein a second transition boundary between the first field and the third field of the second polarity is in the vicinity of the second opening of the base. 18. The magnetic device of claim 17, wherein each of the first and second transition boundaries is accessible to an object such that when a magnet is inserted at the first or the second transition boundary, the magnet hovers or registers at the transition boundary. 19. The magnetic device of claim 18, wherein the magnetic device is configured such that if a pressure is applied to the hovering magnet and then released, the magnet inclines to return to substantially the same location. 20. The magnetic device of claim 18, wherein the combination of the magnet and the magnetic device is used to create transducers, valves, speakers, microphones, and pumps. 21. The magnetic device of claim 1, each of the magnets is a permanent magnet, an electromagnetic magnet, a superconducting magnet, or a combination of the above. 22. The magnetic device of claim 1, wherein the base further includes a gap formed into the solid ring structure of the base which connects the space in the center of the base and the space outside the base. 23. A device for propelling a magnetic object from a first location to a second location, comprising:
a first magnetic field generator configured to generate a first magnetic field pattern comprising a first magnetic field of a first polarity, and a second magnetic field and a third magnetic field both of a second polarity and located on either side of the first magnetic field; and a second magnetic field generator coupled in series with the first magnetic field generator and configured to generate a second magnetic field pattern which is substantially identical to the first magnetic field pattern, wherein the first and the second magnetic field patterns form a combined linear field pattern having first-second-first-first-second-first polarities, and wherein the combined linear field pattern causes a magnetic object to enter from a first end of the combined linear field pattern, traverse each of the magnetic field in the combined linear field pattern, and exit from a second end of the combined linear field pattern, as a result of the magnetic interaction between the magnetic object and the combined linear field pattern. 24. The device of claim 23, wherein the first polarity is magnetic north and the second polarity is magnetic south. 25. The device of claim 23, wherein the first polarity is magnetic south and the second polarity is magnetic north. 26. The device of claim 23, wherein each of the first and second magnetic field generators comprises:
a base including an upper surface, a lower surface, and an inner wall and an outer wall that are sandwiched between the upper surface and the lower surface, wherein the upper surface includes a first opening defined by the upper edge of the inner wall, the lower surface includes a second opening defined by the lower edge of the inner wall; and a set of magnets placed to cover a portion of the inner wall, wherein each of the magnets is positioned such that an axis of the magnet connecting the north pole and the south pole of the magnet forms an angle with respect to the upper and lower surfaces. 27. The device of claim 26, wherein the set of magnets are placed inside a set of recessed locations within the inner wall of the base. 28. The device of claim 26, wherein the set of magnets are mounted on the surface of the inner wall of the base. 29. The device of claim 26, wherein each of the set of magnets located in or around the inner wall has a trapezoid, circular, square, and/or triangular geometry. 30. The device of claim 26, wherein the set of magnets includes two or more magnets. 31. The device of claim 26, wherein the first magnetic field of a first polarity is formed substantially between the upper surface and the lower surface inside the base, the second magnetic field of the second polarity is formed outward from the first opening of the base, and the third magnetic field of the second polarity is formed outward from the second opening of the base and on the opposite side of the first magnetic field. 32. The device of claim 26, further comprising one or more additional magnetic field generators coupled in series with the first and second magnetic field generators and configured to generate one or more additional magnetic field patterns which are substantially identical to the first and second magnetic field patterns. 33. The device of claim 32, wherein the first, the second, and the one or more additional magnetic field generators form a linear array for propelling the magnetic object in a linear path. 34. The device of claim 32, wherein the first, the second, and the one or more additional magnetic field generators form a circular array for propelling the magnetic object in a circular path. | 2,800 |
11,953 | 11,953 | 15,476,812 | 2,817 | A display may have an array of organic light-emitting diodes that form an active area on a flexible substrate. Metal traces may extend between the active area and an inactive area of the flexible substrate. Display driver circuitry such as a display driver integrated circuit may be coupled to the inactive area. The metal traces may extend across a bend region in the flexible substrate. The flexible substrate may be bent in the bend region. The flexible substrate may be made of a thin flexible material to reduce metal trace bending stress. A coating layer in the bend region may be provided with an enhanced elasticity to allow its thickness to be reduced. The flexible substrate may be bent on itself and secured within an electronic device without using a mandrel. | 1. A display, comprising:
a flexible substrate; an array of pixels that form an active area on the flexible substrate; metal traces that extend from the active area to an inactive area on the flexible substrate across a bend region on the flexible substrate, wherein the flexible substrate is folded over against itself at the bend region so that the active area overlaps the inactive area; a first polymer layer interposed between the active area and the inactive area that is overlapped by the active area, wherein the first polymer layer has a first edge surface; a second polymer layer interposed between the first polymer layer and the active area, wherein the second polymer layer overlaps the first edge surface of the first polymer layer and has a second edge surface that is not aligned with the first edge surface, and wherein a gap separates the first and second edge surfaces from the flexible substrate; and an adhesive layer interposed between the first and second polymer layers. 2. The display defined in claim 1, wherein the adhesive layer is the only layer interposed between the first and second polymer layers. 3. The display defined in claim 2, further comprising:
a first additional adhesive layer interposed between the first polymer layer and the inactive area that is overlapped by the active area; and a second additional adhesive layer interposed between the second polymer layer and the active area. 4. The display defined in claim 3, wherein the first polymer layer has a first thickness, wherein the second polymer layer has a second thickness that is equal to or greater than the first thickness, and wherein the adhesive layer has a third thickness that is less than the first and second thicknesses. 5. The display defined in claim 3, wherein the first polymer layer, the second polymer layer, the adhesive layer, the first additional adhesive layer, and the second additional adhesive layers are the only layers between the active area and the inactive that is overlapped by the active area. 6. The display defined in claim 1, wherein the adhesive layer has a third edge surface that is aligned with the first edge surface of the first polymer layer. 7. A display, comprising:
a flexible substrate having opposing first and second surfaces; an array of pixels that form an active area on the first surface of the flexible substrate, wherein the flexible substrate is folded at a bend region; a first polymer layer interposed between a first portion of the second surface of the flexible substrate and a second portion of the second surface of the flexible substrate, wherein the first polymer layer has a first thickness; a first layer of adhesive that attaches the first polymer layer to the first portion of the second surface; a second polymer layer interposed between the first polymer layer and the second portion of the second surface, wherein the second polymer layer has a second thickness less than or equal to the first thickness; a second layer of adhesive that attaches the second polymer layer to the second portion of the second surface; and a third layer of adhesive interposed between the first and second polymer layers, wherein the third layer of adhesive has a third thickness that is less than the first and second thicknesses, and wherein the third adhesive layer is the only layer between the first and second polymer layers. 8. The display defined in claim 7, wherein the first polymer layer, the first layer of adhesive, the second polymer layer, the second layer of adhesive, and the third layer of adhesive are the only layers between the first portion of the second surface of the flexible substrate and the second portion of the second surface of the flexible substrate. 9. The display defined in claim 7, wherein the first portion of the second surface is interposed between the active area and the second portion of the second surface. 10. The display defined in claim 9, wherein the second polymer layer, the second layer of adhesive, and the third layer of adhesive each have respective aligned edge surfaces. 11. The display defined in claim 10, wherein the first polymer layer and the first layer of adhesive extend beyond and overlap the respective aligned edge surfaces of the second polymer layer, the second layer of adhesive, and the third layer of adhesive. 12. The display defined in claim 11, wherein the first polymer layer and the first layer of adhesive have respective aligned edge surfaces. 13. The display defined in claim 7, further comprising:
a polymer coating on the first surface of the flexible substrate in the bend region. 14. An organic light-emitting diode display, comprising:
thin-film transistor circuitry that forms an array of pixels; a flexible substrate having a first surface on which the thin-film transistor circuitry is formed and having an opposing second surface, wherein the flexible substrate is bent back on itself so that a first portion of the second surface faces a second portion of the second surface; first and second polymer layers interposed between the first portion and the second portion, wherein the first and second polymer layers have first and second respective edge surfaces; and a layer of adhesive interposed between the first and second polymer layers, wherein the layer of adhesive is thinner than the first and second polymer layers and extends beyond the first and second edge surfaces. 15. The organic light-emitting diode display defined in claim 14, wherein the layer of adhesive is the only layer between the first and second polymer layers. 16. The organic light-emitting diode display defined in claim 15, wherein the flexible substrate is bent back on itself in a bend region, and wherein the layer of adhesive contacts the second surface of the flexible substrate in the bend region. 17. The organic light-emitting diode display defined in claim 16, wherein a gap separates the first and second edge surfaces from the second surface of the flexible substrate in the bend region. 18. The organic light-emitting diode display defined in claim 17 further comprising:
a polymer coating on the first surface of the flexible substrate in the bend region. 19. The organic light-emitting diode display defined in claim 14, further comprising:
a first additional adhesive layer interposed between the first polymer layer and the first portion of the second surface of the flexible substrate; and a second additional adhesive layer interposed between the second polymer layer and the second portion of the second surface of the flexible substrate. 20. The organic light-emitting diode display defined in claim 14, wherein the first and second edge surfaces are aligned. | A display may have an array of organic light-emitting diodes that form an active area on a flexible substrate. Metal traces may extend between the active area and an inactive area of the flexible substrate. Display driver circuitry such as a display driver integrated circuit may be coupled to the inactive area. The metal traces may extend across a bend region in the flexible substrate. The flexible substrate may be bent in the bend region. The flexible substrate may be made of a thin flexible material to reduce metal trace bending stress. A coating layer in the bend region may be provided with an enhanced elasticity to allow its thickness to be reduced. The flexible substrate may be bent on itself and secured within an electronic device without using a mandrel.1. A display, comprising:
a flexible substrate; an array of pixels that form an active area on the flexible substrate; metal traces that extend from the active area to an inactive area on the flexible substrate across a bend region on the flexible substrate, wherein the flexible substrate is folded over against itself at the bend region so that the active area overlaps the inactive area; a first polymer layer interposed between the active area and the inactive area that is overlapped by the active area, wherein the first polymer layer has a first edge surface; a second polymer layer interposed between the first polymer layer and the active area, wherein the second polymer layer overlaps the first edge surface of the first polymer layer and has a second edge surface that is not aligned with the first edge surface, and wherein a gap separates the first and second edge surfaces from the flexible substrate; and an adhesive layer interposed between the first and second polymer layers. 2. The display defined in claim 1, wherein the adhesive layer is the only layer interposed between the first and second polymer layers. 3. The display defined in claim 2, further comprising:
a first additional adhesive layer interposed between the first polymer layer and the inactive area that is overlapped by the active area; and a second additional adhesive layer interposed between the second polymer layer and the active area. 4. The display defined in claim 3, wherein the first polymer layer has a first thickness, wherein the second polymer layer has a second thickness that is equal to or greater than the first thickness, and wherein the adhesive layer has a third thickness that is less than the first and second thicknesses. 5. The display defined in claim 3, wherein the first polymer layer, the second polymer layer, the adhesive layer, the first additional adhesive layer, and the second additional adhesive layers are the only layers between the active area and the inactive that is overlapped by the active area. 6. The display defined in claim 1, wherein the adhesive layer has a third edge surface that is aligned with the first edge surface of the first polymer layer. 7. A display, comprising:
a flexible substrate having opposing first and second surfaces; an array of pixels that form an active area on the first surface of the flexible substrate, wherein the flexible substrate is folded at a bend region; a first polymer layer interposed between a first portion of the second surface of the flexible substrate and a second portion of the second surface of the flexible substrate, wherein the first polymer layer has a first thickness; a first layer of adhesive that attaches the first polymer layer to the first portion of the second surface; a second polymer layer interposed between the first polymer layer and the second portion of the second surface, wherein the second polymer layer has a second thickness less than or equal to the first thickness; a second layer of adhesive that attaches the second polymer layer to the second portion of the second surface; and a third layer of adhesive interposed between the first and second polymer layers, wherein the third layer of adhesive has a third thickness that is less than the first and second thicknesses, and wherein the third adhesive layer is the only layer between the first and second polymer layers. 8. The display defined in claim 7, wherein the first polymer layer, the first layer of adhesive, the second polymer layer, the second layer of adhesive, and the third layer of adhesive are the only layers between the first portion of the second surface of the flexible substrate and the second portion of the second surface of the flexible substrate. 9. The display defined in claim 7, wherein the first portion of the second surface is interposed between the active area and the second portion of the second surface. 10. The display defined in claim 9, wherein the second polymer layer, the second layer of adhesive, and the third layer of adhesive each have respective aligned edge surfaces. 11. The display defined in claim 10, wherein the first polymer layer and the first layer of adhesive extend beyond and overlap the respective aligned edge surfaces of the second polymer layer, the second layer of adhesive, and the third layer of adhesive. 12. The display defined in claim 11, wherein the first polymer layer and the first layer of adhesive have respective aligned edge surfaces. 13. The display defined in claim 7, further comprising:
a polymer coating on the first surface of the flexible substrate in the bend region. 14. An organic light-emitting diode display, comprising:
thin-film transistor circuitry that forms an array of pixels; a flexible substrate having a first surface on which the thin-film transistor circuitry is formed and having an opposing second surface, wherein the flexible substrate is bent back on itself so that a first portion of the second surface faces a second portion of the second surface; first and second polymer layers interposed between the first portion and the second portion, wherein the first and second polymer layers have first and second respective edge surfaces; and a layer of adhesive interposed between the first and second polymer layers, wherein the layer of adhesive is thinner than the first and second polymer layers and extends beyond the first and second edge surfaces. 15. The organic light-emitting diode display defined in claim 14, wherein the layer of adhesive is the only layer between the first and second polymer layers. 16. The organic light-emitting diode display defined in claim 15, wherein the flexible substrate is bent back on itself in a bend region, and wherein the layer of adhesive contacts the second surface of the flexible substrate in the bend region. 17. The organic light-emitting diode display defined in claim 16, wherein a gap separates the first and second edge surfaces from the second surface of the flexible substrate in the bend region. 18. The organic light-emitting diode display defined in claim 17 further comprising:
a polymer coating on the first surface of the flexible substrate in the bend region. 19. The organic light-emitting diode display defined in claim 14, further comprising:
a first additional adhesive layer interposed between the first polymer layer and the first portion of the second surface of the flexible substrate; and a second additional adhesive layer interposed between the second polymer layer and the second portion of the second surface of the flexible substrate. 20. The organic light-emitting diode display defined in claim 14, wherein the first and second edge surfaces are aligned. | 2,800 |
11,954 | 11,954 | 16,381,982 | 2,848 | A system to effectuate improved transfer of semiconductor die. A first frame secures a first substrate having the semiconductor die. A second frame secures a second substrate adjacent the first substrate. A needle is disposed adjacent to the first frame. The needle includes: a longitudinal surface extending in a direction toward the second frame, and a base end having a cross-sectional dimension being based, at least in part, on a cross-sectional dimension of the semiconductor die. A needle actuator is operably connected to the needle and is configured to actuate the needle such that, during the transfer operation, when the first substrate is secured in the first frame and the second substrate is secured in the second frame, the needle presses the semiconductor die into contact with the second substrate so as to transfer the semiconductor die onto the second substrate. | 1. A method of effectuating improved transfer of a semiconductor die from a wafer tape, the method comprising:
positioning the wafer tape having the semiconductor die thereon, the semiconductor die being disposed on a first side of the wafer tape; positioning a substrate adjacent to the wafer tape; selecting, based, at least in part, on one or more characteristics of the semiconductor die, a needle to transfer the semiconductor die; selecting, based, at least in part, on the one or more characteristics of the semiconductor die, a gap distance between the substrate and a bottom surface of the semiconductor die, and the bottom surface of the semiconductor die being opposite a top surface of the semiconductor die adhered to the wafer tape; positioning, based, at least in part, on the gap distance, an end of the needle adjacent to a second surface of the wafer tape; and transferring, via actuation of the needle, the semiconductor die onto the substrate. 2. The method of claim 1, wherein the end of the needle includes:
a longitudinal surface extending in a direction toward the wafer tape; a tip; and a tapered portion interposed between the longitudinal surface and the tip, and wherein a height of the tapered portion is based, at least in part, on a height of the semiconductor die. 3. The method of claim 1, wherein selecting the gap distance is further based, at least in part, on an adhesion force between the semiconductor die and the wafer tape. 4. The method of claim 1, wherein transferring the semiconductor die occurs at a predetermined rate of transfer that is based, at least in part, on an amount of adhesion force adhering the semiconductor die to the wafer tape. 5. The method of claim 1, wherein the needle has a resting position and a transfer position,
wherein a cycle of the needle includes starting at the resting position, transitioning to the transfer position, and returning to the resting position, and wherein a stroke rate of the cycle occurs at predetermined amount of time. 6. The method of claim 5, wherein the needle is in the transfer position for about 30 milliseconds. 7. The method of claim 6, wherein in the resting position, a distance between the end of the needle and the second surface of the wafer tape is about 1 mm. 8. The method of claim 1, wherein the one or more characteristics include:
a height of the semiconductor die; a cross-sectional dimension of the semiconductor die; or a type of the semiconductor die. | A system to effectuate improved transfer of semiconductor die. A first frame secures a first substrate having the semiconductor die. A second frame secures a second substrate adjacent the first substrate. A needle is disposed adjacent to the first frame. The needle includes: a longitudinal surface extending in a direction toward the second frame, and a base end having a cross-sectional dimension being based, at least in part, on a cross-sectional dimension of the semiconductor die. A needle actuator is operably connected to the needle and is configured to actuate the needle such that, during the transfer operation, when the first substrate is secured in the first frame and the second substrate is secured in the second frame, the needle presses the semiconductor die into contact with the second substrate so as to transfer the semiconductor die onto the second substrate.1. A method of effectuating improved transfer of a semiconductor die from a wafer tape, the method comprising:
positioning the wafer tape having the semiconductor die thereon, the semiconductor die being disposed on a first side of the wafer tape; positioning a substrate adjacent to the wafer tape; selecting, based, at least in part, on one or more characteristics of the semiconductor die, a needle to transfer the semiconductor die; selecting, based, at least in part, on the one or more characteristics of the semiconductor die, a gap distance between the substrate and a bottom surface of the semiconductor die, and the bottom surface of the semiconductor die being opposite a top surface of the semiconductor die adhered to the wafer tape; positioning, based, at least in part, on the gap distance, an end of the needle adjacent to a second surface of the wafer tape; and transferring, via actuation of the needle, the semiconductor die onto the substrate. 2. The method of claim 1, wherein the end of the needle includes:
a longitudinal surface extending in a direction toward the wafer tape; a tip; and a tapered portion interposed between the longitudinal surface and the tip, and wherein a height of the tapered portion is based, at least in part, on a height of the semiconductor die. 3. The method of claim 1, wherein selecting the gap distance is further based, at least in part, on an adhesion force between the semiconductor die and the wafer tape. 4. The method of claim 1, wherein transferring the semiconductor die occurs at a predetermined rate of transfer that is based, at least in part, on an amount of adhesion force adhering the semiconductor die to the wafer tape. 5. The method of claim 1, wherein the needle has a resting position and a transfer position,
wherein a cycle of the needle includes starting at the resting position, transitioning to the transfer position, and returning to the resting position, and wherein a stroke rate of the cycle occurs at predetermined amount of time. 6. The method of claim 5, wherein the needle is in the transfer position for about 30 milliseconds. 7. The method of claim 6, wherein in the resting position, a distance between the end of the needle and the second surface of the wafer tape is about 1 mm. 8. The method of claim 1, wherein the one or more characteristics include:
a height of the semiconductor die; a cross-sectional dimension of the semiconductor die; or a type of the semiconductor die. | 2,800 |
11,955 | 11,955 | 15,946,697 | 2,814 | A thin-film transistor (TFT) array substrate including: a first conductive layer selected from an active layer, a gate electrode, a source electrode, and a drain electrode of a TFT; a second conductive layer in a layer different from the first conductive layer; and a connection node coupling the first conductive layer to the second conductive layer. Here, the TFT array has a node contact hole formed by: a first contact hole in the first conductive layer; and a second contact hole in the second conductive layer, the second contact hole being integral with the first contact hole and not being separated from the first contact hole by an insulating layer, and at least a portion of the connection node is in the node contact hole. | 1. A thin-film transistor (TFT) array substrate comprising:
a switching TFT comprising a source electrode and a drain electrode; a driving TFT comprising a gate electrode connected to one of the source electrode and the drain electrode of the switching TFT; an initialization power line connected to the other one of the source electrode and the drain electrode of the switching TFT; an integrated contact hole disposed at one of the source electrode and the drain electrode of the switching TFT; and a connection node extending through the integrated contact hole to contact the initialization power line, and extending through the integrated contact hole to contact the one of the source electrode and the drain electrode of the switching TFT, the connection node being in direct contact with the initialization power line over a first substantially flat surface that is substantially parallel to the TFT array substrate, and the connection node being in direct contact with the one of the source electrode and the drain electrode of the switching TFT over a second substantially flat surface that is substantially parallel to the TFT array substrate. 2. The TFT array substrate of claim 1, wherein the initialization power line
and the one of the source electrode and the drain electrode of the switching TFT overlaps at an overlapping region (OL) between the first substantially flat surface and the second substantially flat surface. 3. The TFT array substrate of claim 2, further comprising a gate insulating layer between the initialization power line and the one of the source electrode and the drain electrode of the switching TFT wherein the gate insulating layer and initialization power line overlap at the overlapping region. 4. The TFT array substrate of claim 2, further comprising an interlayer insulating layer between the initialization power line and the one of the source electrode and the drain electrode, and wherein the interlayer insulating layer is not located at the overlapping region. 5. The TFT array substrate of claim 2, wherein the connection node comprises a same material as the one of the source electrode and the drain electrode. 6. The TFT array substrate of claim 2, further comprising a capacitor connected to the switching TFT, and wherein the switching TFT further comprises an active layer, and wherein a first electrode of the capacitor is in the same layer as the active layer. 7. The TFT array substrate of claim 6, wherein the first electrode of the capacitor comprises a same material as the active layer. | A thin-film transistor (TFT) array substrate including: a first conductive layer selected from an active layer, a gate electrode, a source electrode, and a drain electrode of a TFT; a second conductive layer in a layer different from the first conductive layer; and a connection node coupling the first conductive layer to the second conductive layer. Here, the TFT array has a node contact hole formed by: a first contact hole in the first conductive layer; and a second contact hole in the second conductive layer, the second contact hole being integral with the first contact hole and not being separated from the first contact hole by an insulating layer, and at least a portion of the connection node is in the node contact hole.1. A thin-film transistor (TFT) array substrate comprising:
a switching TFT comprising a source electrode and a drain electrode; a driving TFT comprising a gate electrode connected to one of the source electrode and the drain electrode of the switching TFT; an initialization power line connected to the other one of the source electrode and the drain electrode of the switching TFT; an integrated contact hole disposed at one of the source electrode and the drain electrode of the switching TFT; and a connection node extending through the integrated contact hole to contact the initialization power line, and extending through the integrated contact hole to contact the one of the source electrode and the drain electrode of the switching TFT, the connection node being in direct contact with the initialization power line over a first substantially flat surface that is substantially parallel to the TFT array substrate, and the connection node being in direct contact with the one of the source electrode and the drain electrode of the switching TFT over a second substantially flat surface that is substantially parallel to the TFT array substrate. 2. The TFT array substrate of claim 1, wherein the initialization power line
and the one of the source electrode and the drain electrode of the switching TFT overlaps at an overlapping region (OL) between the first substantially flat surface and the second substantially flat surface. 3. The TFT array substrate of claim 2, further comprising a gate insulating layer between the initialization power line and the one of the source electrode and the drain electrode of the switching TFT wherein the gate insulating layer and initialization power line overlap at the overlapping region. 4. The TFT array substrate of claim 2, further comprising an interlayer insulating layer between the initialization power line and the one of the source electrode and the drain electrode, and wherein the interlayer insulating layer is not located at the overlapping region. 5. The TFT array substrate of claim 2, wherein the connection node comprises a same material as the one of the source electrode and the drain electrode. 6. The TFT array substrate of claim 2, further comprising a capacitor connected to the switching TFT, and wherein the switching TFT further comprises an active layer, and wherein a first electrode of the capacitor is in the same layer as the active layer. 7. The TFT array substrate of claim 6, wherein the first electrode of the capacitor comprises a same material as the active layer. | 2,800 |
11,956 | 11,956 | 14,766,414 | 2,894 | A semiconductor device according to the present invention includes a mount substrate, an adhesive applied to the mount substrate, and a device having its lower surface bonded to the mount substrate with the adhesive. The surface roughness of a side surface upper portion of the device is lower than that of a side surface lower portion of the device. | 1. A semiconductor device comprising:
a mount substrate; an adhesive applied to the mount substrate; and a device having its lower surface bonded to the mount substrate with the adhesive, wherein the surface roughness of a side surface upper portion of the device is lower than that of a side surface lower portion of the device. 2. The semiconductor device according to claim 1, wherein a dicing trace with a surface roughness Rz of 1.0 μm or less is formed on a side surface upper portion of the device, and a dicing trace with a surface roughness Rz of 4.0 μm or more is formed on a side surface lower portion of the device. 3. A semiconductor device manufacturing method comprising:
a laser dicing step of separating a wafer into individual devices by forming through holes in the wafer by laser dicing; a removal step of removing, with a blade or by etching, a molten material formed on side surfaces of the device in the laser dicing step; a die bonding step of bonding a mount substrate and a lower surface of the device to each other with an adhesive after the removal step; and an adhesive curing step of curing the adhesive. 4. The semiconductor device manufacturing method according to claim 3, wherein in the removal step, only the molten material formed on the side surface upper portions of the device is removed. 5. A semiconductor device manufacturing method comprising:
a step of forming grooves in a wafer with blade or by etching; a laser dicing step of forming through holes by performing laser dicing on the portions in which the grooves are formed, as seen in plan, with portions of the grooves left, the wafer being separated into individual devices; a die bonding step of bonding a mount substrate and a lower surface of the device to each other with an adhesive; and an adhesive curing step of curing the adhesive. | A semiconductor device according to the present invention includes a mount substrate, an adhesive applied to the mount substrate, and a device having its lower surface bonded to the mount substrate with the adhesive. The surface roughness of a side surface upper portion of the device is lower than that of a side surface lower portion of the device.1. A semiconductor device comprising:
a mount substrate; an adhesive applied to the mount substrate; and a device having its lower surface bonded to the mount substrate with the adhesive, wherein the surface roughness of a side surface upper portion of the device is lower than that of a side surface lower portion of the device. 2. The semiconductor device according to claim 1, wherein a dicing trace with a surface roughness Rz of 1.0 μm or less is formed on a side surface upper portion of the device, and a dicing trace with a surface roughness Rz of 4.0 μm or more is formed on a side surface lower portion of the device. 3. A semiconductor device manufacturing method comprising:
a laser dicing step of separating a wafer into individual devices by forming through holes in the wafer by laser dicing; a removal step of removing, with a blade or by etching, a molten material formed on side surfaces of the device in the laser dicing step; a die bonding step of bonding a mount substrate and a lower surface of the device to each other with an adhesive after the removal step; and an adhesive curing step of curing the adhesive. 4. The semiconductor device manufacturing method according to claim 3, wherein in the removal step, only the molten material formed on the side surface upper portions of the device is removed. 5. A semiconductor device manufacturing method comprising:
a step of forming grooves in a wafer with blade or by etching; a laser dicing step of forming through holes by performing laser dicing on the portions in which the grooves are formed, as seen in plan, with portions of the grooves left, the wafer being separated into individual devices; a die bonding step of bonding a mount substrate and a lower surface of the device to each other with an adhesive; and an adhesive curing step of curing the adhesive. | 2,800 |
11,957 | 11,957 | 15,648,325 | 2,841 | Portable electronic devices are provided. Each device may be formed from two parts. A first part may be provided with components such as a display, a touch screen, a cover glass, and a frame. A second part may be provided with a plastic housing, circuit boards containing electrical components, and a bezel. Engagement members may be connected to the first and second parts. The engagement members may be formed from metal clips with holes and springs with flexible spring prongs that mate with the holes in the clips. The metal clips may be welded to frame struts on the frame and the springs may be welded to the bezel. Hard stop structures may be used to vertically align the first and second parts. A frame in the device may have an integral gasket. | 1. An electronic device having front and rear surfaces, comprising:
a housing having a glass member that forms at least part of the rear surface; a touch-sensitive display having a cover layer that forms at least part of the front surface; and a frame that attaches the display to the housing, wherein the frame includes a plastic portion molded over a metal portion. 2. The electronic device defined in claim 1 wherein the touch-sensitive display comprises a capacitive touch sensor. 3. The electronic device defined in claim 2 wherein the capacitive touch sensor is interposed between the cover layer and the glass member. 4. The electronic device defined in claim 3 wherein the plastic portion of the frame has a shelf that supports the cover layer. 5. The electronic device defined in claim 4 wherein the cover layer comprises glass. 6. The electronic device defined in claim 5 further comprising an elastomeric gasket between the cover layer and the plastic portion of the frame. 7. The electronic device defined in claim 1 further comprising wireless communications circuitry mounted in the housing. 8. The electronic device defined in claim 1 wherein the glass member has a planar portion. 9. The electronic device defined in claim 1 wherein the metal portion forms a metal frame strut having a hole. 10. The electronic device defined in claim 9 further comprising a clip mounted to the frame, wherein the housing comprises a spring that engages with the clip. 11. An electronic device, comprising:
a housing have a glass portion that forms an exterior surface of the electronic device; a display mounted in the housing, wherein the display comprises a capacitive touch sensor; and a frame that supports the display, wherein the frame comprises a plastic member and a metal member. 12. The electronic device defined in claim 11 wherein the display comprises a glass cover layer. 13. The electronic device defined in claim 12 wherein the capacitive touch sensor is interposed between the glass cover layer and the glass portion of the housing. 14. The electronic device defined in claim 13 further comprising a gasket, wherein the plastic member has a protrusion and wherein the gasket is located between the protrusion and the glass cover layer. 15. The electronic device defined in claim 11 wherein the metal member has an opening and wherein the plastic member passes through the opening. 16. An electronic device having first and second opposing outer surfaces, comprising:
a first glass member that forms at least a portion of the first outer surface; a second glass member that forms at least a portion of the second outer surface; a touch-sensitive display located behind the first glass member; a frame that supports the touch-sensitive display; and a metal mid-plate attached to the frame, wherein the metal mid-plate is interposed between the touch-sensitive display and the second glass member. 17. The electronic device defined in claim 16 wherein the frame comprises plastic. 18. The electronic device defined in claim 16 wherein the touch-sensitive display comprises a capacitive touch sensor. 19. The electronic device defined in claim 16 further comprising a clip attached to the frame, wherein the second glass member forms part of a housing assembly, and wherein the housing assembly comprises a spring that engages with the clip. 20. The electronic device defined in claim 16 further comprising a gasket located between the first glass member and the frame. | Portable electronic devices are provided. Each device may be formed from two parts. A first part may be provided with components such as a display, a touch screen, a cover glass, and a frame. A second part may be provided with a plastic housing, circuit boards containing electrical components, and a bezel. Engagement members may be connected to the first and second parts. The engagement members may be formed from metal clips with holes and springs with flexible spring prongs that mate with the holes in the clips. The metal clips may be welded to frame struts on the frame and the springs may be welded to the bezel. Hard stop structures may be used to vertically align the first and second parts. A frame in the device may have an integral gasket.1. An electronic device having front and rear surfaces, comprising:
a housing having a glass member that forms at least part of the rear surface; a touch-sensitive display having a cover layer that forms at least part of the front surface; and a frame that attaches the display to the housing, wherein the frame includes a plastic portion molded over a metal portion. 2. The electronic device defined in claim 1 wherein the touch-sensitive display comprises a capacitive touch sensor. 3. The electronic device defined in claim 2 wherein the capacitive touch sensor is interposed between the cover layer and the glass member. 4. The electronic device defined in claim 3 wherein the plastic portion of the frame has a shelf that supports the cover layer. 5. The electronic device defined in claim 4 wherein the cover layer comprises glass. 6. The electronic device defined in claim 5 further comprising an elastomeric gasket between the cover layer and the plastic portion of the frame. 7. The electronic device defined in claim 1 further comprising wireless communications circuitry mounted in the housing. 8. The electronic device defined in claim 1 wherein the glass member has a planar portion. 9. The electronic device defined in claim 1 wherein the metal portion forms a metal frame strut having a hole. 10. The electronic device defined in claim 9 further comprising a clip mounted to the frame, wherein the housing comprises a spring that engages with the clip. 11. An electronic device, comprising:
a housing have a glass portion that forms an exterior surface of the electronic device; a display mounted in the housing, wherein the display comprises a capacitive touch sensor; and a frame that supports the display, wherein the frame comprises a plastic member and a metal member. 12. The electronic device defined in claim 11 wherein the display comprises a glass cover layer. 13. The electronic device defined in claim 12 wherein the capacitive touch sensor is interposed between the glass cover layer and the glass portion of the housing. 14. The electronic device defined in claim 13 further comprising a gasket, wherein the plastic member has a protrusion and wherein the gasket is located between the protrusion and the glass cover layer. 15. The electronic device defined in claim 11 wherein the metal member has an opening and wherein the plastic member passes through the opening. 16. An electronic device having first and second opposing outer surfaces, comprising:
a first glass member that forms at least a portion of the first outer surface; a second glass member that forms at least a portion of the second outer surface; a touch-sensitive display located behind the first glass member; a frame that supports the touch-sensitive display; and a metal mid-plate attached to the frame, wherein the metal mid-plate is interposed between the touch-sensitive display and the second glass member. 17. The electronic device defined in claim 16 wherein the frame comprises plastic. 18. The electronic device defined in claim 16 wherein the touch-sensitive display comprises a capacitive touch sensor. 19. The electronic device defined in claim 16 further comprising a clip attached to the frame, wherein the second glass member forms part of a housing assembly, and wherein the housing assembly comprises a spring that engages with the clip. 20. The electronic device defined in claim 16 further comprising a gasket located between the first glass member and the frame. | 2,800 |
11,958 | 11,958 | 15,461,286 | 2,841 | A component for an electronic device include a housing and a plastic substrate. The plastic substrate is disposed in, and adjacent to, the housing, A thermoplastic overlayer is insert molded into the housing. The plastic substrate is disposed between the housing and the thermoplastic overlayer after the insert molding. The plastic substrate and the thermoplastic overlayer can share at least one common incision penetrating the thermoplastic overlayer and at least partially penetrating the plastic substrate. | 1. A component for an electronic device, the component comprising:
a housing; a plastic substrate, disposed adjacent to the housing; and a thermoplastic overlayer, insert molded into the housing; wherein the plastic substrate is disposed between the housing and the thermoplastic overlayer; wherein the thermoplastic overlayer envelops surfaces of the plastic substrate other than interface surfaces of the plastic substrate abutting the housing. 2. The component of claim 1, wherein both the plastic substrate and the thermoplastic overlayer share at least one common incision penetrating the thermoplastic overlayer and at least partially penetrating the plastic substrate. 3. The component of claim 1, wherein the thermoplastic overlayer envelops all major and minor faces of the plastic substrate other than a housing interface, which is a surface of the plastic substrate abutting the housing. 4. The component of claim 3, further comprising an adhesive layer disposed between the plastic substrate and the housing. 5. The component of claim 3, the housing defining one or more mechanical features retaining the plastic substrate at a predetermined location within the housing when the thermoplastic overlayer is insert molded into the housing atop the plastic substrate. 6. The component of claim 2, wherein the plastic substrate comprises a thermoplastic overlayer interface and a housing interface, wherein the housing interface defines one or more concave geometric features. 7. The component of claim 6, wherein the incision completely penetrates the plastic substrate only along portions of the one or more concave geometric features. 8. The component of claim 7, the one or more concave geometric features and the incision defining a snap feature. 9. The component of claim 7, wherein the plastic substrate and the thermoplastic overlayer are manufactured from different materials. 10. The component of claim 9, wherein the housing is manufactured from aluminum. 11. The component of claim 2, further comprising electrically conductive material disposed within the plastic substrate. 12. The component of claim 11, wherein the electrically conductive material defines an antenna. 13. The component of claim 12, wherein the thermoplastic overlayer defines one or more apertures exposing portions of the antenna. 14. (canceled) 15. (canceled) 16. (canceled) 17. (canceled) 18. (canceled) 19. (canceled) 20. (canceled) 21. The component of claim 11, wherein the electrically conductive material comprises a resistive material. 22. The component of claim 11, wherein the plastic substrate comprises a first half and a second half which are joined together about the electrically conductive material. 23. The component of claim 11, wherein the electrically conductive material is insert molded into the plastic substrate. 24. The component of claim 13, further comprising another incision removing a portion of both the thermoplastic overlayer and the plastic substrate. 25. The component of claim 24, wherein the another incision defines a snap feature. | A component for an electronic device include a housing and a plastic substrate. The plastic substrate is disposed in, and adjacent to, the housing, A thermoplastic overlayer is insert molded into the housing. The plastic substrate is disposed between the housing and the thermoplastic overlayer after the insert molding. The plastic substrate and the thermoplastic overlayer can share at least one common incision penetrating the thermoplastic overlayer and at least partially penetrating the plastic substrate.1. A component for an electronic device, the component comprising:
a housing; a plastic substrate, disposed adjacent to the housing; and a thermoplastic overlayer, insert molded into the housing; wherein the plastic substrate is disposed between the housing and the thermoplastic overlayer; wherein the thermoplastic overlayer envelops surfaces of the plastic substrate other than interface surfaces of the plastic substrate abutting the housing. 2. The component of claim 1, wherein both the plastic substrate and the thermoplastic overlayer share at least one common incision penetrating the thermoplastic overlayer and at least partially penetrating the plastic substrate. 3. The component of claim 1, wherein the thermoplastic overlayer envelops all major and minor faces of the plastic substrate other than a housing interface, which is a surface of the plastic substrate abutting the housing. 4. The component of claim 3, further comprising an adhesive layer disposed between the plastic substrate and the housing. 5. The component of claim 3, the housing defining one or more mechanical features retaining the plastic substrate at a predetermined location within the housing when the thermoplastic overlayer is insert molded into the housing atop the plastic substrate. 6. The component of claim 2, wherein the plastic substrate comprises a thermoplastic overlayer interface and a housing interface, wherein the housing interface defines one or more concave geometric features. 7. The component of claim 6, wherein the incision completely penetrates the plastic substrate only along portions of the one or more concave geometric features. 8. The component of claim 7, the one or more concave geometric features and the incision defining a snap feature. 9. The component of claim 7, wherein the plastic substrate and the thermoplastic overlayer are manufactured from different materials. 10. The component of claim 9, wherein the housing is manufactured from aluminum. 11. The component of claim 2, further comprising electrically conductive material disposed within the plastic substrate. 12. The component of claim 11, wherein the electrically conductive material defines an antenna. 13. The component of claim 12, wherein the thermoplastic overlayer defines one or more apertures exposing portions of the antenna. 14. (canceled) 15. (canceled) 16. (canceled) 17. (canceled) 18. (canceled) 19. (canceled) 20. (canceled) 21. The component of claim 11, wherein the electrically conductive material comprises a resistive material. 22. The component of claim 11, wherein the plastic substrate comprises a first half and a second half which are joined together about the electrically conductive material. 23. The component of claim 11, wherein the electrically conductive material is insert molded into the plastic substrate. 24. The component of claim 13, further comprising another incision removing a portion of both the thermoplastic overlayer and the plastic substrate. 25. The component of claim 24, wherein the another incision defines a snap feature. | 2,800 |
11,959 | 11,959 | 15,850,999 | 2,899 | Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees. | 1. A method of fabricating a thick oxide feature on a semiconductor wafer, the method comprising:
forming a oxide layer having a thickness of at least six micrometers, the oxide layer having a first etch rate of X with a given etchant; depositing a photoresist layer on the oxide layer, the photoresist layer having a second etch rate of Y with the given etchant, wherein the ratio of X:Y is less than 4:1; and prior to etching the photoresist layer and the oxide layer, patterning the photoresist layer with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees. 2. The method as recited in claim 1 further comprising etching the photoresist layer and the oxide layer using the given etchant to form the thick oxide feature. 3. The method as recited in claim 1 wherein the ratio of X:Y is less than 3:1. 4. The method as recited in claim 3 wherein etching the photoresist layer and the oxide layer comprises performing a timed etch segment followed by a pause in the etching prior to performing a subsequent etch segment. 5. The method as recited in claim 4 further comprising forming an etch stop layer underneath the oxide layer. 6. The method as recited in claim 5 further comprising performing a final etch segment that stops on the etch stop layer. 7. The method as recited in claim 6 wherein the oxide layer comprises a material chosen from the group comprising silicon oxide, aluminum oxide, tantalum oxide and hafnium oxide. 8. A method of fabricating a thick oxide feature on a semiconductor wafer, the method comprising:
forming a oxide layer having a thickness of at least six micrometers; depositing and patterning a photoresist layer on the oxide layer; performing a first timed etch segment of the photoresist layer and the oxide layer, followed by a first pause during which an etching process is halted and byproducts of the etching process are evacuated; and performing a final etch segment of the photoresist layer and the oxide layer that stops on an etch stop layer. 9. The method as recited in claim 8 further comprising, subsequent to performing the first timed etch segment and prior to performing the final etch segment, performing a second timed etch segment of the photoresist layer and the oxide layer, followed by a second pause during which the etching process is halted and the byproducts of the etching process are evacuated. 10. The method as recited in claim 8 wherein the performing the first timed etch segment and the performing the final timed etch segment utilize a plasma etching process. 11. The method as recited in claim 10 wherein the etching tool re-optimizes the plasma etching process after each pause. 12. The method as recited in claim 9 wherein the pauses last between 15 and 60 seconds. 13. The method as recited in claim 8 further comprising, prior to etching the photoresist layer and the oxide layer, patterning the photoresist layer with a grayscale mask, wherein the oxide layer has a first etch rate of X, the photoresist layer has a second etch rate of Y, and the ratio of X:Y is less than 4:1. 14. The method as recited in claim 13 wherein the ratio of X:Y is less than 3:1. 15. The method as recited in claim 12 wherein the etch stop layer comprises silicon oxynitride. 16. The method as recited in claim 12 wherein the oxide layer comprises a material chosen from the group comprising silicon oxide, aluminum oxide, tantalum oxide and hafnium oxide. 17. A method of fabricating a thick silicon oxide feature on a semiconductor wafer, the method comprising:
forming a silicon oxide layer having a thickness of at least six micrometers, the silicon oxide layer having a first etch rate of X with a given etchant; depositing a photoresist layer on the silicon oxide layer, the photoresist layer having a second etch rate of Y with the given etchant, wherein the ratio of X:Y is less than 4:1; prior to etching the photoresist layer and the silicon oxide layer using the etchant, patterning the photoresist layer with a grayscale mask; and etching the photoresist layer and the silicon oxide layer using a plasma etching process to form the thick silicon oxide feature, wherein the etching is performed in a plurality of etch segments that are separated by pauses during which the plasma etching process is halted and the byproducts of the plasma etching process are evacuated. | Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.1. A method of fabricating a thick oxide feature on a semiconductor wafer, the method comprising:
forming a oxide layer having a thickness of at least six micrometers, the oxide layer having a first etch rate of X with a given etchant; depositing a photoresist layer on the oxide layer, the photoresist layer having a second etch rate of Y with the given etchant, wherein the ratio of X:Y is less than 4:1; and prior to etching the photoresist layer and the oxide layer, patterning the photoresist layer with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees. 2. The method as recited in claim 1 further comprising etching the photoresist layer and the oxide layer using the given etchant to form the thick oxide feature. 3. The method as recited in claim 1 wherein the ratio of X:Y is less than 3:1. 4. The method as recited in claim 3 wherein etching the photoresist layer and the oxide layer comprises performing a timed etch segment followed by a pause in the etching prior to performing a subsequent etch segment. 5. The method as recited in claim 4 further comprising forming an etch stop layer underneath the oxide layer. 6. The method as recited in claim 5 further comprising performing a final etch segment that stops on the etch stop layer. 7. The method as recited in claim 6 wherein the oxide layer comprises a material chosen from the group comprising silicon oxide, aluminum oxide, tantalum oxide and hafnium oxide. 8. A method of fabricating a thick oxide feature on a semiconductor wafer, the method comprising:
forming a oxide layer having a thickness of at least six micrometers; depositing and patterning a photoresist layer on the oxide layer; performing a first timed etch segment of the photoresist layer and the oxide layer, followed by a first pause during which an etching process is halted and byproducts of the etching process are evacuated; and performing a final etch segment of the photoresist layer and the oxide layer that stops on an etch stop layer. 9. The method as recited in claim 8 further comprising, subsequent to performing the first timed etch segment and prior to performing the final etch segment, performing a second timed etch segment of the photoresist layer and the oxide layer, followed by a second pause during which the etching process is halted and the byproducts of the etching process are evacuated. 10. The method as recited in claim 8 wherein the performing the first timed etch segment and the performing the final timed etch segment utilize a plasma etching process. 11. The method as recited in claim 10 wherein the etching tool re-optimizes the plasma etching process after each pause. 12. The method as recited in claim 9 wherein the pauses last between 15 and 60 seconds. 13. The method as recited in claim 8 further comprising, prior to etching the photoresist layer and the oxide layer, patterning the photoresist layer with a grayscale mask, wherein the oxide layer has a first etch rate of X, the photoresist layer has a second etch rate of Y, and the ratio of X:Y is less than 4:1. 14. The method as recited in claim 13 wherein the ratio of X:Y is less than 3:1. 15. The method as recited in claim 12 wherein the etch stop layer comprises silicon oxynitride. 16. The method as recited in claim 12 wherein the oxide layer comprises a material chosen from the group comprising silicon oxide, aluminum oxide, tantalum oxide and hafnium oxide. 17. A method of fabricating a thick silicon oxide feature on a semiconductor wafer, the method comprising:
forming a silicon oxide layer having a thickness of at least six micrometers, the silicon oxide layer having a first etch rate of X with a given etchant; depositing a photoresist layer on the silicon oxide layer, the photoresist layer having a second etch rate of Y with the given etchant, wherein the ratio of X:Y is less than 4:1; prior to etching the photoresist layer and the silicon oxide layer using the etchant, patterning the photoresist layer with a grayscale mask; and etching the photoresist layer and the silicon oxide layer using a plasma etching process to form the thick silicon oxide feature, wherein the etching is performed in a plurality of etch segments that are separated by pauses during which the plasma etching process is halted and the byproducts of the plasma etching process are evacuated. | 2,800 |
11,960 | 11,960 | 15,223,136 | 2,822 | The present disclosure includes textured memory cell structures and method of forming the same. In one or more embodiments, a memory cell includes a buffer portion formed on an amorphous portion and an active portion formed on the buffer portion, wherein the active portion is textured with a single out of plane orientation. | 1. A memory element, comprising:
an amorphous portion; a buffer portion formed on the amorphous portion, wherein the buffer portion is a chalcogenide and wherein the buffer portion is textured with a single out of plane orientation; and an active portion formed on the buffer portion, wherein the active portion is textured with a single out of plane orientation. 2. The memory element of claim 1, wherein the buffer portion is a chalcogenide. 3. The memory element of claim 1, wherein the buffer portion is formed of antimony telluride (Sb2Te3). 4. The memory element of claim 1, wherein the active portion is a mono crystal chalcogenide. 5. The memory element of claim 1, wherein the active portion is a crystalline multi-material chalcogenide. 6. The memory element of claim 5, wherein the crystalline multi-material chalcogenide includes a number of portions of germanium telluride (GeTe) alternating between a number of portions of antimony telluride (Sb2Te3). 7. The memory element of claim 6, wherein the memory cell is a phase change random access memory (PCRAM) cell. 8. A memory element cell, comprising:
an amorphous portion; a first chalcogenide portion formed on the amorphous portion, wherein the first chalcogenide portion has a single out of plane orientation; and a second chalcogenide portion formed on the first chalcogenide portion, wherein the first chalcogenide portion and the second chalcogenide portion are formed of different materials and the second chalcogenide portion has a single out of plane orientation. 9. The memory element of claim 8, wherein the first chalcogenide portion has a single crystal out of plane orientation. 10. The memory element of claim 8, wherein the first chalcogenide portion is antimony telluride (Sb2Te3). 11. The memory element of claim 8, wherein the first chalcogenide portion is approximately 1 nanometer (nm) to 5 nm thick. 12. The memory element of claim 8, the second chalcogenide portion is a mono crystal chalcogenide. 13. The memory element of claim 8, wherein the second chalcogenide portion is a crystalline multi-material chalcogenide. 14. The memory element of claim 13, wherein the crystalline multi-material chalcogenide includes a number of portions of germanium telluride (GeTe) alternating between a number of portions of antimony telluride (Sb2Te3). 15. The memory element of claim 8, wherein the single crystal out of plane orientation of the second chalcogenide portion is in the (00.1) direction. 16. A method of forming a memory cells, comprising:
forming a buffer on an amorphous portion; and forming an active portion having a single out of plane orientation on the buffer. 17. The method of claim 16, wherein forming the buffer includes depositing the buffer at approximately 50° C. and annealing the buffer to approximately 240° C. 18. The method of claim 16, wherein forming the active portion includes depositing the active portion at approximately 227° C. 19. The method of claim 16, wherein forming the active portion includes epitaxially growing a first chalcogenide. 20. The method of claim 16, wherein forming the active portion includes epitaxially growing alternating portions of a first chalcogenide and a second chalcogenide. 21. The method of claim 16, including forming the buffer on amorphous carbon. 22. The method of claim 16, including forming the buffer to a thickness of approximately 1 nanometer (nm) to 5 nm. 23. The method of claim 16, including forming the active portion to a thickness of approximately 5 nanometers (nm) to 70 nm. 24. A method of forming a memory cells, comprising:
forming a first chalcogenide portion on an amorphous portion; and forming a second chalcogenide portion formed on the buffer portion, wherein the second chalcogenide portion has a single out of plane orientation. 25. The method of claim 24, wherein forming the first chalcogenide portion includes forming an antimony telluride (Sb2Te3) portion to a thickness of approximately 1 nanometer (nm) to 5 nms. 26. The method of claim 24, wherein forming the second chalcogenide portion includes forming antimony telluride (Sb2Te3) to a thickness of approximately 5 nanometers (nm) to 70 nm. 27. The method of claim 24, wherein forming the second chalcogenide portion includes forming alternating portions of germanium telluride (GeTe) to a thickness of approximately 0.9 nm and antimony telluride (Sb2Te3) to a thickness of approximately 4 nm. 28. The method of claim 24, wherein forming the second chalcogenide portion includes forming a germanium antimony tellurium (GST portion). 29. The method of claim 24, wherein forming the second chalcogenide portion includes forming a chalcogenide superlattice (CSL) portion 30. The method of claim 24, wherein forming the first chalcogenide portion includes depositing the first chalcogenide portion at approximately 50° C. and annealing the first chalcogenide portion to approximately 240° C. 31. The method of claim 30, wherein annealing the first chalcogenide portion includes exposing the first chalcogenide portion to a tellurium flux. | The present disclosure includes textured memory cell structures and method of forming the same. In one or more embodiments, a memory cell includes a buffer portion formed on an amorphous portion and an active portion formed on the buffer portion, wherein the active portion is textured with a single out of plane orientation.1. A memory element, comprising:
an amorphous portion; a buffer portion formed on the amorphous portion, wherein the buffer portion is a chalcogenide and wherein the buffer portion is textured with a single out of plane orientation; and an active portion formed on the buffer portion, wherein the active portion is textured with a single out of plane orientation. 2. The memory element of claim 1, wherein the buffer portion is a chalcogenide. 3. The memory element of claim 1, wherein the buffer portion is formed of antimony telluride (Sb2Te3). 4. The memory element of claim 1, wherein the active portion is a mono crystal chalcogenide. 5. The memory element of claim 1, wherein the active portion is a crystalline multi-material chalcogenide. 6. The memory element of claim 5, wherein the crystalline multi-material chalcogenide includes a number of portions of germanium telluride (GeTe) alternating between a number of portions of antimony telluride (Sb2Te3). 7. The memory element of claim 6, wherein the memory cell is a phase change random access memory (PCRAM) cell. 8. A memory element cell, comprising:
an amorphous portion; a first chalcogenide portion formed on the amorphous portion, wherein the first chalcogenide portion has a single out of plane orientation; and a second chalcogenide portion formed on the first chalcogenide portion, wherein the first chalcogenide portion and the second chalcogenide portion are formed of different materials and the second chalcogenide portion has a single out of plane orientation. 9. The memory element of claim 8, wherein the first chalcogenide portion has a single crystal out of plane orientation. 10. The memory element of claim 8, wherein the first chalcogenide portion is antimony telluride (Sb2Te3). 11. The memory element of claim 8, wherein the first chalcogenide portion is approximately 1 nanometer (nm) to 5 nm thick. 12. The memory element of claim 8, the second chalcogenide portion is a mono crystal chalcogenide. 13. The memory element of claim 8, wherein the second chalcogenide portion is a crystalline multi-material chalcogenide. 14. The memory element of claim 13, wherein the crystalline multi-material chalcogenide includes a number of portions of germanium telluride (GeTe) alternating between a number of portions of antimony telluride (Sb2Te3). 15. The memory element of claim 8, wherein the single crystal out of plane orientation of the second chalcogenide portion is in the (00.1) direction. 16. A method of forming a memory cells, comprising:
forming a buffer on an amorphous portion; and forming an active portion having a single out of plane orientation on the buffer. 17. The method of claim 16, wherein forming the buffer includes depositing the buffer at approximately 50° C. and annealing the buffer to approximately 240° C. 18. The method of claim 16, wherein forming the active portion includes depositing the active portion at approximately 227° C. 19. The method of claim 16, wherein forming the active portion includes epitaxially growing a first chalcogenide. 20. The method of claim 16, wherein forming the active portion includes epitaxially growing alternating portions of a first chalcogenide and a second chalcogenide. 21. The method of claim 16, including forming the buffer on amorphous carbon. 22. The method of claim 16, including forming the buffer to a thickness of approximately 1 nanometer (nm) to 5 nm. 23. The method of claim 16, including forming the active portion to a thickness of approximately 5 nanometers (nm) to 70 nm. 24. A method of forming a memory cells, comprising:
forming a first chalcogenide portion on an amorphous portion; and forming a second chalcogenide portion formed on the buffer portion, wherein the second chalcogenide portion has a single out of plane orientation. 25. The method of claim 24, wherein forming the first chalcogenide portion includes forming an antimony telluride (Sb2Te3) portion to a thickness of approximately 1 nanometer (nm) to 5 nms. 26. The method of claim 24, wherein forming the second chalcogenide portion includes forming antimony telluride (Sb2Te3) to a thickness of approximately 5 nanometers (nm) to 70 nm. 27. The method of claim 24, wherein forming the second chalcogenide portion includes forming alternating portions of germanium telluride (GeTe) to a thickness of approximately 0.9 nm and antimony telluride (Sb2Te3) to a thickness of approximately 4 nm. 28. The method of claim 24, wherein forming the second chalcogenide portion includes forming a germanium antimony tellurium (GST portion). 29. The method of claim 24, wherein forming the second chalcogenide portion includes forming a chalcogenide superlattice (CSL) portion 30. The method of claim 24, wherein forming the first chalcogenide portion includes depositing the first chalcogenide portion at approximately 50° C. and annealing the first chalcogenide portion to approximately 240° C. 31. The method of claim 30, wherein annealing the first chalcogenide portion includes exposing the first chalcogenide portion to a tellurium flux. | 2,800 |
11,961 | 11,961 | 12,757,251 | 2,858 | A method of navigation includes receiving a magnetic field signal from a magnetic field transducer, the magnetic field signal proportional to sensed magnetic fields associated with magnetic field sources, in a processor, processing the magnetic field signal to determine magnetic field axes of rotation corresponding to rotations of the sensed magnetic fields, and using the magnetic field axes of rotation to render a position of the magnetic field transducer. | 1. A method of navigation, comprising:
receiving a magnetic field signal from a magnetic field transducer, the magnetic field signal proportional to sensed magnetic fields associated with a plurality of magnetic field sources; in a processor, processing the magnetic field signal to determine a plurality of magnetic field axes of rotation corresponding to rotations of the sensed magnetic fields; and using the plurality of magnetic field axes of rotation to render a position of the magnetic field transducer. 2. The method of claim 1, wherein said using the plurality of magnetic field axes of rotation to render the position of the magnetic field transducer comprises:
determining a plurality of orientations of the magnetic field axes of rotation relative to a predetermined coordinate system; and using the plurality of orientations of the magnetic field axes of rotation to render the position of the magnetic field transducer. 3. The method of claim 2, wherein the position of the magnetic field transducer is a fixed position. 4. The method of claim 1, wherein said using the plurality of magnetic field axes of rotation to render the position of the magnetic field transducer comprises:
determining a predetermined number of angles between the magnetic field axes of rotation; and rendering the position of the magnetic field transducer using the predetermined number of angles. 5. The method of claim 4, wherein the predetermined number of angles is at least three angles and the rendered position includes at least one of position information or orientation information. 6. The method of claim 4, wherein the predetermined number of angles is six angles and the rendered position includes a three-dimensional position and a three-dimensional orientation. 7. The method of claim 4, wherein the magnetic field transducer is a rotating magnetic field transducer. 8. The method of claim 4, further comprising:
rendering a position of at least one of the magnetic field sources using the predetermined number of angles. 9. The method of claim 1, wherein the position of the magnetic field transducer corresponds to a position of an object of interest coupled to the magnetic field transducer. 10. The method of claim 1, wherein the magnetic field transducer comprises a magnetometer. 11. The method of claim 1, wherein the plurality of magnetic field sources comprises:
a first spinning dipole generated at a first transmitter having a first predetermined position; a second spinning dipole generated at a second transmitter having a second predetermined position; and a third spinning dipole generated at a third transmitter having a third predetermined position,
wherein the first, second, and third predetermined positions form a triangle. 12. The method of claim 11, wherein the triangle is formed about a navigation area of interest including the magnetic field transducer. 13. The method of claim 1, wherein the plurality of magnetic field sources rotate about a plurality of magnetic field source axes of rotation and are positioned to form a navigation area of interest, further comprising:
rotating each magnetic field source axis of rotation about a respective axis perpendicular to a plane formed by the plurality of magnetic field sources to align each magnetic field source axis of rotation with a successive one of the magnetic field sources. 14. The method of claim 13, further comprising:
rotating at least one of the magnetic field source axes of rotation about a respective axis coincident with the plane formed by the plurality of magnetic field sources to avoid a condition in which the magnetic field transducer is coincident with a plane formed by the magnetic field associated with the at least one magnetic field source axis of rotation. 15. A navigation system, comprising:
a processor to receive a magnetic field signal from a magnetic field transducer, the magnetic field signal proportional to sensed magnetic fields associated with a plurality of magnetic field sources; a memory coupled to the processor, the memory including program instructions for providing navigation information by:
processing the magnetic field signal to determine a plurality of magnetic field axes of rotation corresponding to rotations of the sensed magnetic fields; and
using the plurality of magnetic field axes of rotation to render a position of the magnetic field transducer. 16. The system of claim 15, said using the plurality of magnetic field axes of rotation to render a position of the magnetic field transducer comprises:
determining a plurality of orientations of the magnetic field axes of rotation relative to a predetermined coordinate system; and using the plurality of orientations of the magnetic field axes of rotation to render the position of the magnetic field transducer. 17. The system of claim 16, wherein the position of the magnetic field transducer is a fixed position. 18. The system of claim 15, said using the plurality of magnetic field axes of rotation to render a position of the magnetic field transducer comprises:
determining a predetermined number of angles between the magnetic field axes of rotation; and rendering a position of the magnetic field transducer using the predetermined number of angles. 19. The system of claim 18, wherein the predetermined number of angles is at least three angles and the rendered position includes at least one of position information or orientation information. 20. The system of claim 18, wherein the predetermined number of angles is six angles and the rendered position includes a three-dimensional position and a three-dimensional orientation. 21. The system of claim 18, wherein the magnetic field transducer is a rotating magnetic field transducer. 22. The system of claim 18, further comprising:
rendering a position of at least one of the magnetic field sources using the predetermined number of angles. 23. The system of claim 15, wherein the position of the magnetic field transducer corresponds to a position of an object of interest coupled to the magnetic field transducer. 24. The system of claim 15, wherein the magnetic field transducer comprises a magnetometer. 25. The system of claim 15, wherein the plurality of magnetic field sources comprises:
a first spinning dipole generated at a first transmitter having a first predetermined position; a second spinning dipole generated at a second transmitter having a second predetermined position; and a third spinning dipole generated at a third transmitter having a third predetermined position,
wherein the first, second, and third predetermined positions form a triangle. 26. The system of claim 25, wherein the triangle is formed about a navigation area of interest including the magnetic field transducer. 27. The system of claim 15, wherein the plurality of magnetic field sources rotate about a plurality of magnetic field source axes of rotation and are positioned to form a navigation area of interest, further comprising:
rotating each magnetic field source axis of rotation about a respective axis perpendicular to a plane formed by the plurality of magnetic field sources to align each magnetic field source axis of rotation with a successive one of the magnetic field sources. 28. The system of claim 27, further comprising:
rotating at least one magnetic field source axis of rotation about a respective axis coincident with the plane formed by the plurality of magnetic field sources to avoid a condition in which the magnetic field transducer is coincident with a plane formed by the magnetic field associated with the at least one magnetic field source axis of rotation. 29. A computer-readable medium having encoded thereon software for providing navigation information, said software comprising instructions for:
determining a plurality of magnetic field axes of rotation corresponding to rotations of magnetic fields sensed by a magnetic field transducer and associated with a plurality of magnetic field sources; and processing the plurality of magnetic field axes of rotation to render a position of the magnetic field transducer. 30. The computer-readable medium of claim 1, wherein said processing the plurality of magnetic field axes of rotation to render a position of the magnetic field transducer comprises:
determining a plurality of orientations of the magnetic field axes of rotation relative to a predetermined coordinate system; and using the plurality of orientations of the magnetic field axes of rotation to render the position of the magnetic field transducer. 31. The computer-readable medium of claim 29, wherein said processing the plurality of magnetic field axes of rotation to render a position of the magnetic field transducer comprises:
determining a predetermined number of angles between the magnetic field axes of rotation; and rendering the position of the magnetic field transducer using the predetermined number of angles. 32. The computer-readable medium of claim 31, wherein the predetermined number of angles is at least three angles and the rendered position includes at least one of position information or orientation information. 33. The computer-readable medium of claim 31, wherein the predetermined number of angles is six angles and the rendered position includes a three-dimensional position and a three-dimensional orientation. 34. The computer-readable medium of claim 31, wherein the magnetic field transducer is a rotating magnetic field transducer. 35. The computer-readable medium of claim 31, said software further comprising instructions for:
rendering a position of at least one of the magnetic field sources using the predetermined number of angles. 36. The computer-readable medium of claim 29, wherein the position of the magnetic field transducer corresponds to a position of an object of interest coupled to the magnetic field transducer. 37. The computer-readable medium of claim 29, wherein the magnetic field transducer comprises a magnetometer. | A method of navigation includes receiving a magnetic field signal from a magnetic field transducer, the magnetic field signal proportional to sensed magnetic fields associated with magnetic field sources, in a processor, processing the magnetic field signal to determine magnetic field axes of rotation corresponding to rotations of the sensed magnetic fields, and using the magnetic field axes of rotation to render a position of the magnetic field transducer.1. A method of navigation, comprising:
receiving a magnetic field signal from a magnetic field transducer, the magnetic field signal proportional to sensed magnetic fields associated with a plurality of magnetic field sources; in a processor, processing the magnetic field signal to determine a plurality of magnetic field axes of rotation corresponding to rotations of the sensed magnetic fields; and using the plurality of magnetic field axes of rotation to render a position of the magnetic field transducer. 2. The method of claim 1, wherein said using the plurality of magnetic field axes of rotation to render the position of the magnetic field transducer comprises:
determining a plurality of orientations of the magnetic field axes of rotation relative to a predetermined coordinate system; and using the plurality of orientations of the magnetic field axes of rotation to render the position of the magnetic field transducer. 3. The method of claim 2, wherein the position of the magnetic field transducer is a fixed position. 4. The method of claim 1, wherein said using the plurality of magnetic field axes of rotation to render the position of the magnetic field transducer comprises:
determining a predetermined number of angles between the magnetic field axes of rotation; and rendering the position of the magnetic field transducer using the predetermined number of angles. 5. The method of claim 4, wherein the predetermined number of angles is at least three angles and the rendered position includes at least one of position information or orientation information. 6. The method of claim 4, wherein the predetermined number of angles is six angles and the rendered position includes a three-dimensional position and a three-dimensional orientation. 7. The method of claim 4, wherein the magnetic field transducer is a rotating magnetic field transducer. 8. The method of claim 4, further comprising:
rendering a position of at least one of the magnetic field sources using the predetermined number of angles. 9. The method of claim 1, wherein the position of the magnetic field transducer corresponds to a position of an object of interest coupled to the magnetic field transducer. 10. The method of claim 1, wherein the magnetic field transducer comprises a magnetometer. 11. The method of claim 1, wherein the plurality of magnetic field sources comprises:
a first spinning dipole generated at a first transmitter having a first predetermined position; a second spinning dipole generated at a second transmitter having a second predetermined position; and a third spinning dipole generated at a third transmitter having a third predetermined position,
wherein the first, second, and third predetermined positions form a triangle. 12. The method of claim 11, wherein the triangle is formed about a navigation area of interest including the magnetic field transducer. 13. The method of claim 1, wherein the plurality of magnetic field sources rotate about a plurality of magnetic field source axes of rotation and are positioned to form a navigation area of interest, further comprising:
rotating each magnetic field source axis of rotation about a respective axis perpendicular to a plane formed by the plurality of magnetic field sources to align each magnetic field source axis of rotation with a successive one of the magnetic field sources. 14. The method of claim 13, further comprising:
rotating at least one of the magnetic field source axes of rotation about a respective axis coincident with the plane formed by the plurality of magnetic field sources to avoid a condition in which the magnetic field transducer is coincident with a plane formed by the magnetic field associated with the at least one magnetic field source axis of rotation. 15. A navigation system, comprising:
a processor to receive a magnetic field signal from a magnetic field transducer, the magnetic field signal proportional to sensed magnetic fields associated with a plurality of magnetic field sources; a memory coupled to the processor, the memory including program instructions for providing navigation information by:
processing the magnetic field signal to determine a plurality of magnetic field axes of rotation corresponding to rotations of the sensed magnetic fields; and
using the plurality of magnetic field axes of rotation to render a position of the magnetic field transducer. 16. The system of claim 15, said using the plurality of magnetic field axes of rotation to render a position of the magnetic field transducer comprises:
determining a plurality of orientations of the magnetic field axes of rotation relative to a predetermined coordinate system; and using the plurality of orientations of the magnetic field axes of rotation to render the position of the magnetic field transducer. 17. The system of claim 16, wherein the position of the magnetic field transducer is a fixed position. 18. The system of claim 15, said using the plurality of magnetic field axes of rotation to render a position of the magnetic field transducer comprises:
determining a predetermined number of angles between the magnetic field axes of rotation; and rendering a position of the magnetic field transducer using the predetermined number of angles. 19. The system of claim 18, wherein the predetermined number of angles is at least three angles and the rendered position includes at least one of position information or orientation information. 20. The system of claim 18, wherein the predetermined number of angles is six angles and the rendered position includes a three-dimensional position and a three-dimensional orientation. 21. The system of claim 18, wherein the magnetic field transducer is a rotating magnetic field transducer. 22. The system of claim 18, further comprising:
rendering a position of at least one of the magnetic field sources using the predetermined number of angles. 23. The system of claim 15, wherein the position of the magnetic field transducer corresponds to a position of an object of interest coupled to the magnetic field transducer. 24. The system of claim 15, wherein the magnetic field transducer comprises a magnetometer. 25. The system of claim 15, wherein the plurality of magnetic field sources comprises:
a first spinning dipole generated at a first transmitter having a first predetermined position; a second spinning dipole generated at a second transmitter having a second predetermined position; and a third spinning dipole generated at a third transmitter having a third predetermined position,
wherein the first, second, and third predetermined positions form a triangle. 26. The system of claim 25, wherein the triangle is formed about a navigation area of interest including the magnetic field transducer. 27. The system of claim 15, wherein the plurality of magnetic field sources rotate about a plurality of magnetic field source axes of rotation and are positioned to form a navigation area of interest, further comprising:
rotating each magnetic field source axis of rotation about a respective axis perpendicular to a plane formed by the plurality of magnetic field sources to align each magnetic field source axis of rotation with a successive one of the magnetic field sources. 28. The system of claim 27, further comprising:
rotating at least one magnetic field source axis of rotation about a respective axis coincident with the plane formed by the plurality of magnetic field sources to avoid a condition in which the magnetic field transducer is coincident with a plane formed by the magnetic field associated with the at least one magnetic field source axis of rotation. 29. A computer-readable medium having encoded thereon software for providing navigation information, said software comprising instructions for:
determining a plurality of magnetic field axes of rotation corresponding to rotations of magnetic fields sensed by a magnetic field transducer and associated with a plurality of magnetic field sources; and processing the plurality of magnetic field axes of rotation to render a position of the magnetic field transducer. 30. The computer-readable medium of claim 1, wherein said processing the plurality of magnetic field axes of rotation to render a position of the magnetic field transducer comprises:
determining a plurality of orientations of the magnetic field axes of rotation relative to a predetermined coordinate system; and using the plurality of orientations of the magnetic field axes of rotation to render the position of the magnetic field transducer. 31. The computer-readable medium of claim 29, wherein said processing the plurality of magnetic field axes of rotation to render a position of the magnetic field transducer comprises:
determining a predetermined number of angles between the magnetic field axes of rotation; and rendering the position of the magnetic field transducer using the predetermined number of angles. 32. The computer-readable medium of claim 31, wherein the predetermined number of angles is at least three angles and the rendered position includes at least one of position information or orientation information. 33. The computer-readable medium of claim 31, wherein the predetermined number of angles is six angles and the rendered position includes a three-dimensional position and a three-dimensional orientation. 34. The computer-readable medium of claim 31, wherein the magnetic field transducer is a rotating magnetic field transducer. 35. The computer-readable medium of claim 31, said software further comprising instructions for:
rendering a position of at least one of the magnetic field sources using the predetermined number of angles. 36. The computer-readable medium of claim 29, wherein the position of the magnetic field transducer corresponds to a position of an object of interest coupled to the magnetic field transducer. 37. The computer-readable medium of claim 29, wherein the magnetic field transducer comprises a magnetometer. | 2,800 |
11,962 | 11,962 | 15,988,262 | 2,813 | Implementations of a method of singulating a plurality of die from a semiconductor substrate may include: forming a damage layer beneath a surface of a die street where the die street connects a plurality of semiconductor die formed on a semiconductor substrate. The method may include mounting the semiconductor substrate to a support tape, exposing the semiconductor substrate to sonic energy using a sonic energy source, and singulating the plurality of die at the damage layer using the sonic energy. | 1. A method of singulating a plurality of die from a semiconductor substrate, the method comprising:
forming a damage layer beneath a surface of a die street, the die street connecting a plurality of semiconductor die, the plurality of semiconductor die formed on the semiconductor substrate; mounting the semiconductor substrate to a support tape; exposing the semiconductor substrate to sonic energy using a sonic energy source; and singulating the plurality of die at the damage layer using the sonic energy. 2. The method of claim 1, wherein the sonic energy source emits sonic energy between 20 kHz to 3 GHz. 3. The method of claim 1, wherein forming the damage layer further comprises irradiating the die street with a laser beam at a focal point within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street to form the damage layer. 4. The method of claim 1, wherein forming the damage layer further comprises:
irradiating the die street with a laser beam at a focal point at a first depth within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street; and irradiating the die street with a laser beam at a focal point at a second depth within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street. 5. The method of claim 1, wherein the semiconductor substrate is silicon carbide. 6. The method of claim 1, wherein singulating the plurality of die at the damage layer further comprises stretching the support tape while applying the sonic energy. 7. The method of claim 1, wherein singulating the plurality of die at the damage layer further comprises applying one of a continuous and semicontinuous bias force across a surface of the semiconductor substrate while applying the sonic energy. 8. The method of claim 1, wherein singulating the plurality of die at the damage layer further comprises applying a moving localized bias force across a surface of the semiconductor substrate while applying the sonic energy. 9. The method of claim 1, wherein singulating the plurality of die at the damage layer further comprises applying a plurality of point bias forces distributed across a surface of the semiconductor substrate while applying the sonic energy. 10. A method of singulating a plurality of die from a semiconductor substrate, the method comprising:
irradiating the die street with a laser beam at a focal point within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street to form a damage layer beneath a surface of a die street, the die street connecting a plurality of semiconductor die, the plurality of semiconductor die formed on the semiconductor substrate; mounting the semiconductor substrate to a support tape; exposing the semiconductor substrate to sonic energy using a sonic energy source; and singulating the plurality of die at the damage layer using the sonic energy. 11. The method of claim 10, wherein the sonic energy source emits sonic energy between 20 kHz to 3 GHz. 12. The method of claim 10, wherein irradiating the die street with the laser beam further comprises irradiating the die street with the laser beam at the focal point at a first depth within the semiconductor substrate at the one or more spaced apart locations beneath the surface of the die street; and
irradiating the die street with the laser beam at a focal point at a second depth within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street. 13. The method of claim 10, wherein the semiconductor substrate is silicon carbide. 14. The method of claim 10, wherein singulating the plurality of die at the damage layer further comprises stretching the support tape while applying the sonic energy. 15. The method of claim 10, wherein singulating the plurality of die at the damage layer further comprises applying one of a continuous and semicontinuous bias force across a surface of the semiconductor substrate while applying the sonic energy. 16. The method of claim 10, wherein singulating the plurality of die at the damage layer further comprises applying a moving localized bias force across a surface of the semiconductor substrate while applying the sonic energy. 17. The method of claim 10, wherein singulating the plurality of die at the damage layer further comprises applying a plurality of point bias forces distributed across a surface of the semiconductor substrate while applying the sonic energy. 18. A method of singulating a plurality of die from a silicon carbide substrate, the method comprising:
irradiating the die street with a laser beam at a focal point within the silicon carbide substrate at one or more spaced apart locations beneath the surface of the die street to form a damage layer beneath a surface of a die street, the die street connecting a plurality of semiconductor die, the plurality of semiconductor die formed on the silicon carbide semiconductor substrate; mounting the silicon carbide substrate to a support tape; and singulating the plurality of die at the damage layer using sonic energy from a sonic energy source. 19. The method of claim 18, wherein singulating the plurality of die at the damage layer further comprises stretching the support tape while applying the sonic energy. 20. The method of claim 18, wherein singulating the plurality of die at the damage layer further comprises applying one of a continuous and semicontinuous bias force across a surface of the semiconductor substrate while applying the sonic energy. | Implementations of a method of singulating a plurality of die from a semiconductor substrate may include: forming a damage layer beneath a surface of a die street where the die street connects a plurality of semiconductor die formed on a semiconductor substrate. The method may include mounting the semiconductor substrate to a support tape, exposing the semiconductor substrate to sonic energy using a sonic energy source, and singulating the plurality of die at the damage layer using the sonic energy.1. A method of singulating a plurality of die from a semiconductor substrate, the method comprising:
forming a damage layer beneath a surface of a die street, the die street connecting a plurality of semiconductor die, the plurality of semiconductor die formed on the semiconductor substrate; mounting the semiconductor substrate to a support tape; exposing the semiconductor substrate to sonic energy using a sonic energy source; and singulating the plurality of die at the damage layer using the sonic energy. 2. The method of claim 1, wherein the sonic energy source emits sonic energy between 20 kHz to 3 GHz. 3. The method of claim 1, wherein forming the damage layer further comprises irradiating the die street with a laser beam at a focal point within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street to form the damage layer. 4. The method of claim 1, wherein forming the damage layer further comprises:
irradiating the die street with a laser beam at a focal point at a first depth within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street; and irradiating the die street with a laser beam at a focal point at a second depth within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street. 5. The method of claim 1, wherein the semiconductor substrate is silicon carbide. 6. The method of claim 1, wherein singulating the plurality of die at the damage layer further comprises stretching the support tape while applying the sonic energy. 7. The method of claim 1, wherein singulating the plurality of die at the damage layer further comprises applying one of a continuous and semicontinuous bias force across a surface of the semiconductor substrate while applying the sonic energy. 8. The method of claim 1, wherein singulating the plurality of die at the damage layer further comprises applying a moving localized bias force across a surface of the semiconductor substrate while applying the sonic energy. 9. The method of claim 1, wherein singulating the plurality of die at the damage layer further comprises applying a plurality of point bias forces distributed across a surface of the semiconductor substrate while applying the sonic energy. 10. A method of singulating a plurality of die from a semiconductor substrate, the method comprising:
irradiating the die street with a laser beam at a focal point within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street to form a damage layer beneath a surface of a die street, the die street connecting a plurality of semiconductor die, the plurality of semiconductor die formed on the semiconductor substrate; mounting the semiconductor substrate to a support tape; exposing the semiconductor substrate to sonic energy using a sonic energy source; and singulating the plurality of die at the damage layer using the sonic energy. 11. The method of claim 10, wherein the sonic energy source emits sonic energy between 20 kHz to 3 GHz. 12. The method of claim 10, wherein irradiating the die street with the laser beam further comprises irradiating the die street with the laser beam at the focal point at a first depth within the semiconductor substrate at the one or more spaced apart locations beneath the surface of the die street; and
irradiating the die street with the laser beam at a focal point at a second depth within the semiconductor substrate at one or more spaced apart locations beneath the surface of the die street. 13. The method of claim 10, wherein the semiconductor substrate is silicon carbide. 14. The method of claim 10, wherein singulating the plurality of die at the damage layer further comprises stretching the support tape while applying the sonic energy. 15. The method of claim 10, wherein singulating the plurality of die at the damage layer further comprises applying one of a continuous and semicontinuous bias force across a surface of the semiconductor substrate while applying the sonic energy. 16. The method of claim 10, wherein singulating the plurality of die at the damage layer further comprises applying a moving localized bias force across a surface of the semiconductor substrate while applying the sonic energy. 17. The method of claim 10, wherein singulating the plurality of die at the damage layer further comprises applying a plurality of point bias forces distributed across a surface of the semiconductor substrate while applying the sonic energy. 18. A method of singulating a plurality of die from a silicon carbide substrate, the method comprising:
irradiating the die street with a laser beam at a focal point within the silicon carbide substrate at one or more spaced apart locations beneath the surface of the die street to form a damage layer beneath a surface of a die street, the die street connecting a plurality of semiconductor die, the plurality of semiconductor die formed on the silicon carbide semiconductor substrate; mounting the silicon carbide substrate to a support tape; and singulating the plurality of die at the damage layer using sonic energy from a sonic energy source. 19. The method of claim 18, wherein singulating the plurality of die at the damage layer further comprises stretching the support tape while applying the sonic energy. 20. The method of claim 18, wherein singulating the plurality of die at the damage layer further comprises applying one of a continuous and semicontinuous bias force across a surface of the semiconductor substrate while applying the sonic energy. | 2,800 |
11,963 | 11,963 | 13,524,253 | 2,892 | A multi-chip modular wafer level package of a high voltage unit for an implantable cardiac defibrillator includes one or more high voltage (HV) component chips encapsulated with other components thereof in a polymer mold compound of a single reconstituted wafer, wherein all interconnect segments are preferably located on a single side of the wafer. To electrically couple a contact surface of each HV chip, located on a side of the chip opposite the interconnect side of the wafer, the reconstituted wafer may include conductive through polymer vias; alternately, either wire bonds or layers of conductive polymer are formed to couple the aforementioned contact surface to the corresponding interconnect, prior to encapsulation of the HV chips. In some cases one or more of the components encapsulated in the reconstituted wafer of the package are reconstituted chips. | 1. A multi-chip modular wafer level package of a high voltage unit for an implantable cardiac defibrillator, the package comprising:
a high voltage (HV) component chip including a first contact surface located on a first side thereof, and a second contact surface located on a second side thereof, the second side of the HV chip being opposite the first side of the HV chip; a reconstituted wafer formed by a polymer mold compound in which the HV chip is encapsulated together with other chips of the package, such that the first side of each chip is coplanar with a first side of the wafer; and an interconnect segment coupled to the second contact surface of the HV chip and located on the first side of the wafer. 2. The package of claim 1, further comprising a layer of conductive polymer extending from a first end, coupled to the second contact surface of the HV chip, to a second end that forms the interconnect segment. 3. The package of claim 2, further comprising a redistribution layer extending over the first side of the reconstituted wafer, the redistribution layer comprising a plurality of routing traces, a first of the routing traces being coupled to the first contact surface of the HV component chip and a second of the routing traces being coupled to the interconnect segment. 4. The package of claim 1, further comprising a redistribution layer extending over the first side of the reconstituted wafer, the redistribution layer comprising a plurality of routing traces, a first of the routing traces being coupled to the first contact surface of the HV component chip and a second of the routing traces being coupled to the interconnect segment. 5. The package of claim 1, further comprising:
a layer of conductive polymer overlaying and coupled to the second contact of the HV component chip; and a redistribution layer extending over a second side of the reconstituted wafer, the second side of the reconstituted wafer being opposite the first side thereof, the redistribution layer comprising a routing trace coupled to the layer of conductive polymer; and wherein the reconstituted wafer includes a conductive through polymer via (TPV) extending from a first end at the first side of the wafer to a second end at the second side of the wafer, the second end of the TPV being coupled to the conductive trace of the redistribution layer, and the HV interconnect segment comprising the first end of the TPV. 6. The package of claim 5, further comprising another redistribution layer extending over the first side of the reconstituted wafer, the other redistribution layer comprising a plurality of routing traces, a first of the routing traces being coupled to the first contact surface of the HV component chip and a second of the routing traces being coupled to the interconnect segment. 7. The package of claim 1, wherein:
the reconstituted wafer further includes a perimeter edge bounding the first side thereof; and the HV interconnect segment is recessed from the perimeter edge of the wafer. 8. The package of claim 7, wherein the HV interconnect segment comprises a via block. 9. The package of claim 1, wherein the interconnect segment is included in an interconnect element, the interconnect element further including a conductive post extending from the interconnect segment to a second side of the reconstituted wafer, the second side of the reconstituted wafer being opposite the first side thereof. 10. The package of claim 9, further comprising:
a layer of conductive polymer overlaying and coupled to the second contact of the HV component chip; and a redistribution layer extending over a second side of the reconstituted wafer, the second side of the reconstituted wafer being opposite the first side thereof, the redistribution layer comprising a routing trace coupling the layer of conductive polymer to the conductive post of interconnect element. 11. The package of claim 1, wherein:
the HV chip is incorporated in a reconstituted chip, the reconstituted chip further comprising:
a first side corresponding to and coplanar with the first side of the HV chip;
a second side corresponding to the second side of the HV chip;
a conductive through polymer via (TPV) extending from a first end, at the first side of the reconstituted chip, to a second end, at the second side of the reconstituted chip; and
a routing trace extending over the second side of the reconstituted chip and coupling the second contact surface of the HV chip to the second end of the TPV; and
the interconnect segment comprises the first end of the TPV of the reconstituted chip. 12. The package of claim 11, further comprising:
another HV component chip encapsulated in the reconstituted wafer and having a thickness greater than that of the reconstituted chip, the other HV component chip including a first contact surface located on a first side thereof, and a second contact surface located on a second side thereof, the second side of the other HV component chip being opposite the first side of the other HV component chip, the first contact surface of the other HV component chip being coplanar with the first side of the reconstituted wafer, and the second contact surface of the other HV component chip being coplanar with a second side of the reconstituted wafer, the second side of the reconstituted wafer being opposite the first side; and a redistribution layer extending over the second side of the reconstituted wafer, the redistribution layer comprising a routing trace coupled to the second contact surface of the other HV component chip; and wherein the reconstituted wafer includes a conductive through polymer via (TPV) extending alongside the other HV component chip, from a first end at the first side of the wafer to a second end at the second side of the wafer, the first end of the TPV forming an interconnect segment for the other HV component chip, and the second end of the TPV being coupled to the routing trace of the redistribution layer. 13. The package of claim 11, further comprising:
a stacked pair of reconstituted chips encapsulated in the reconstituted wafer, each reconstituted chip of the stacked pair comprising a first side, a first contact surface located on the first side, a second, opposite side, a second contact surface located on the second side, and a routing trace extending over the corresponding second side and being coupled to the corresponding second contact surface; and wherein the first contact surface of a first reconstituted chip of the stacked pair is coplanar with the first side of the reconstituted wafer, and the first contact surface of a second reconstituted chip of the stacked pair is coplanar with the second side of the reconstituted wafer; and the reconstituted wafer includes a conductive through polymer via (TPV) extending alongside the stacked pair, from a first end at the first side of the wafer to a second end at the second side of the wafer, the TPV coupling together the routing traces that extend over the second sides of the stacked pair of reconstituted chips. 14. The package of claim 11, further comprising:
a stacked pair of reconstituted chips encapsulated in the reconstituted wafer, a first reconstituted chip of the stacked pair comprising a first side, a first contact surface located on the first side, a second, opposite side, a second contact surface located on the second side, and a routing trace extending over the second side and being coupled to the corresponding second contact surface, and a second reconstituted chip of the stacked pair comprising a first side, a first contact surface located on the first side of the second reconstituted chip, a second side, a second contact surface located on the second side of the second reconstituted chip, a through polymer via (TPV) extending from a first end, at the first side of the second reconstituted chip, to a second end, at the second side of the second reconstituted chip, and a routing trace extending over the second side of the second reconstituted chip and coupling the second contact surface of the second reconstituted chip to the second end of the TPV of the second reconstituted chip; and a conductive adhesive adhering the second sides of the stacked pair of reconstituted chips together to conductively couple the routing traces thereof; and wherein the first contact surface of the first reconstituted chip of the stacked pair is coplanar with the first side of the reconstituted wafer, and the first contact surface of the second reconstituted chip of the stacked pair is coplanar with the second side of the reconstituted wafer. 15. The package of claim 11, further comprising:
a stacked pair of reconstituted chips encapsulated in the reconstituted wafer, a first reconstituted chip of the stacked pair comprising a first side, a first contact surface located on the first side, a second, opposite side, a second contact surface located on the second side, a through polymer via (TPV) extending from a first end, at the first side, to a second end, at the second side, and a routing trace extending over the second side and coupling the second contact surface to the second end of the TPV, and a second reconstituted chip of the stacked pair comprising a first side, a first contact surface located on the first side of the second reconstituted chip, a second side, a second contact surface located on the second side of the second reconstituted chip, a through polymer via (TPV) extending from a first end, at the first side of the second reconstituted chip, to a second end, at the second side of the second reconstituted chip, and a routing trace extending over the second side of the second reconstituted chip and coupling the second contact surface of the second reconstituted chip to the second end of the TPV of the second reconstituted chip; and a non-conductive adhesive adhering the second sides of the stacked pair of reconstituted chips together; and wherein the first contact surface of the first reconstituted chip of the stacked pair is coplanar with the first side of the reconstituted wafer, and the first contact surface of the second reconstituted chip of the stacked pair is coplanar with the second side of the reconstituted wafer. 16. The package of claim 11, further comprising:
a redistribution layer extending over a second side of the reconstituted wafer, the second side of the wafer being opposite the first side thereof; and a heat sink plate extending within or over the redistribution layer; wherein the second side of the reconstituted chip is recessed from a second side of the reconstituted wafer; and the reconstituted wafer includes an array of heat pipes formed therein and extending from the second side of the reconstituted chip to the heat sink plate. 17. The package of claim 11, further comprising:
a redistribution layer extending over a second side of the reconstituted wafer, the second side of the wafer being opposite the first side thereof; and a heat sink plate extending within or over the redistribution layer; wherein the second side of the reconstituted chip is recessed from a second side of the reconstituted wafer; and the reconstituted chip further comprises an array of columns of stacked gold stud bumps mounted on the second side of reconstituted chip and extending to the heat sink plate. 18. The package of claim 1, further comprising a heat sink plate extending over a second side of the reconstituted wafer, the second side of the reconstituted wafer being opposite the first side thereof; and wherein:
the second side of the HV chip is recessed from the second side of the reconstituted wafer; and the reconstituted wafer includes an array of heat pipes formed therein and extending from the second side of the HV chip to the heat sink plate. 19. The package of claim 1, further comprising a heat sink plate extending over a second side of the reconstituted wafer, the second side of the reconstituted wafer being opposite the first side thereof; and wherein:
the second side of the HV chip is recessed from the second side of the reconstituted wafer; and the HV chip further includes an array of columns of stacked gold stud bumps mounted on the second side of the HV chip and extending to the heat sink plate. 20. A method for forming a wafer level package of a high voltage unit suitable for an implantable cardiac defibrillator, the method comprising:
encapsulating a plurality of individual high voltage (HV) component chips in a polymer mold compound to form a first reconstituted wafer, such that a first side of each HV chip is coplanar with a first side of the first reconstituted wafer, each HV chip including a first contact surface located on the first side thereof, a second contact surface located on a second side thereof, the second side of each HV chip being opposite the first side of each HV chip, forming a redistribution layer over a second side of the wafer, the second side being opposite the first side thereof, and the redistribution layer comprising a plurality of routing traces, each routing trace of the plurality being coupled to the second contact surface of a corresponding HV chip of the plurality of HV component chips; singulating individual reconstituted chips from the first reconstituted wafer, each individual reconstituted chip including one of the plurality of HV chips and the corresponding routing trace; and encapsulating one or more of the individual reconstituted chips, along with other components of the high voltage unit in a polymer mold compound to form a second reconstituted wafer, such that the first contact surface of at least one of the one or more encapsulated reconstituted chips is coplanar with a first side of the second reconstituted wafer. 21. The method of claim 20, wherein each HV chip further includes a conductive crest protruding from the corresponding second contact surface; and further comprising thinning the first reconstituted wafer, before forming the redistribution layer, to expose the conductive crest of each encapsulated HV chip at the second side of the first reconstituted wafer for coupling to the corresponding routing trace. 22. The method of claim 20, further comprising:
thinning the first reconstituted wafer, before forming the redistribution layer, to within approximately 25 micrometers from each second contact surface; and forming a plurality of conductive vias from the second side of the first reconstituted wafer, before forming the redistribution layer, each via of the plurality of vias extending to a corresponding second contact surface for coupling to the corresponding routing trace when the redistribution layer is formed. 23. The method of claim 20, further comprising forming a plurality of conductive through polymer vias prior to singulating individual reconstituted chips, each through polymer via (TPV) extending alongside each encapsulated HV chip and from a first end thereof, that is coplanar with the first contact surface of the corresponding HV chip, to a second end thereof, that is coupled to the routing trace of the corresponding HV chip; and wherein each individual reconstituted chip further includes the TPV coupled to the routing trace thereof. 24. The method of claim 23, wherein the other encapsulated components of the high voltage unit comprise another HV component chip, the other HV component chip being thicker than the one or more reconstituted chips and including a first contact surface located on a first side thereof, and a second contact surface located on a second side thereof, the second side of the other HV component chip being opposite the first side thereof, and the first side of the other HV component chip being coplanar with the first side of the second reconstituted wafer; and further comprising:
thinning the second reconstituted wafer to form a second side thereof adjacent to the second side of the other HV component chip; forming a redistribution layer over the second side of the thinned second reconstituted wafer, the redistribution layer comprising a routing trace coupled to the second contact surface of the other HV component chip; and forming a conductive through polymer via (TPV) in the second reconstituted wafer extending alongside the other HV chip, the TPV in the second reconstituted wafer being coupled to and extending from the routing trace, that is coupled to the second contact surface of the other HV component chip, to the first side of the second reconstituted wafer. 25. The method of claim 23, wherein the one or more individual reconstituted chips includes a first reconstituted chip and a second reconstituted chip; and further comprising bonding a backside of the first reconstituted chip to a backside of the second reconstituted chip, prior to encapsulating, the backside of each of the first and second reconstituted chips being defined by the redistribution layer formed over the second side thereof. 26. The method of claim 25, further comprising forming a through polymer via (TPV) through the second reconstituted wafer to couple together the routing traces of the first and second reconstituted chips. 27. The method of claim 25, wherein the backsides of the first and second reconstituted chips are bonded together with a non-conductive adhesive. 28. The method of claim 23, further comprising bonding, with a conductive adhesive, a backside of one of the one or more individual reconstituted chips to a backside of a second individual reconstituted chip, prior to encapsulating, the backside of the one of the one or more individual reconstituted chips being defined by the redistribution layer formed over the second side thereof, the backside of the second individual reconstituted chip being defined by a redistribution layer that includes a routing trace coupled to a contact surface thereof, and the first contact surface of the second individual reconstituted chip being coplanar with the first side of the second reconstituted wafer. | A multi-chip modular wafer level package of a high voltage unit for an implantable cardiac defibrillator includes one or more high voltage (HV) component chips encapsulated with other components thereof in a polymer mold compound of a single reconstituted wafer, wherein all interconnect segments are preferably located on a single side of the wafer. To electrically couple a contact surface of each HV chip, located on a side of the chip opposite the interconnect side of the wafer, the reconstituted wafer may include conductive through polymer vias; alternately, either wire bonds or layers of conductive polymer are formed to couple the aforementioned contact surface to the corresponding interconnect, prior to encapsulation of the HV chips. In some cases one or more of the components encapsulated in the reconstituted wafer of the package are reconstituted chips.1. A multi-chip modular wafer level package of a high voltage unit for an implantable cardiac defibrillator, the package comprising:
a high voltage (HV) component chip including a first contact surface located on a first side thereof, and a second contact surface located on a second side thereof, the second side of the HV chip being opposite the first side of the HV chip; a reconstituted wafer formed by a polymer mold compound in which the HV chip is encapsulated together with other chips of the package, such that the first side of each chip is coplanar with a first side of the wafer; and an interconnect segment coupled to the second contact surface of the HV chip and located on the first side of the wafer. 2. The package of claim 1, further comprising a layer of conductive polymer extending from a first end, coupled to the second contact surface of the HV chip, to a second end that forms the interconnect segment. 3. The package of claim 2, further comprising a redistribution layer extending over the first side of the reconstituted wafer, the redistribution layer comprising a plurality of routing traces, a first of the routing traces being coupled to the first contact surface of the HV component chip and a second of the routing traces being coupled to the interconnect segment. 4. The package of claim 1, further comprising a redistribution layer extending over the first side of the reconstituted wafer, the redistribution layer comprising a plurality of routing traces, a first of the routing traces being coupled to the first contact surface of the HV component chip and a second of the routing traces being coupled to the interconnect segment. 5. The package of claim 1, further comprising:
a layer of conductive polymer overlaying and coupled to the second contact of the HV component chip; and a redistribution layer extending over a second side of the reconstituted wafer, the second side of the reconstituted wafer being opposite the first side thereof, the redistribution layer comprising a routing trace coupled to the layer of conductive polymer; and wherein the reconstituted wafer includes a conductive through polymer via (TPV) extending from a first end at the first side of the wafer to a second end at the second side of the wafer, the second end of the TPV being coupled to the conductive trace of the redistribution layer, and the HV interconnect segment comprising the first end of the TPV. 6. The package of claim 5, further comprising another redistribution layer extending over the first side of the reconstituted wafer, the other redistribution layer comprising a plurality of routing traces, a first of the routing traces being coupled to the first contact surface of the HV component chip and a second of the routing traces being coupled to the interconnect segment. 7. The package of claim 1, wherein:
the reconstituted wafer further includes a perimeter edge bounding the first side thereof; and the HV interconnect segment is recessed from the perimeter edge of the wafer. 8. The package of claim 7, wherein the HV interconnect segment comprises a via block. 9. The package of claim 1, wherein the interconnect segment is included in an interconnect element, the interconnect element further including a conductive post extending from the interconnect segment to a second side of the reconstituted wafer, the second side of the reconstituted wafer being opposite the first side thereof. 10. The package of claim 9, further comprising:
a layer of conductive polymer overlaying and coupled to the second contact of the HV component chip; and a redistribution layer extending over a second side of the reconstituted wafer, the second side of the reconstituted wafer being opposite the first side thereof, the redistribution layer comprising a routing trace coupling the layer of conductive polymer to the conductive post of interconnect element. 11. The package of claim 1, wherein:
the HV chip is incorporated in a reconstituted chip, the reconstituted chip further comprising:
a first side corresponding to and coplanar with the first side of the HV chip;
a second side corresponding to the second side of the HV chip;
a conductive through polymer via (TPV) extending from a first end, at the first side of the reconstituted chip, to a second end, at the second side of the reconstituted chip; and
a routing trace extending over the second side of the reconstituted chip and coupling the second contact surface of the HV chip to the second end of the TPV; and
the interconnect segment comprises the first end of the TPV of the reconstituted chip. 12. The package of claim 11, further comprising:
another HV component chip encapsulated in the reconstituted wafer and having a thickness greater than that of the reconstituted chip, the other HV component chip including a first contact surface located on a first side thereof, and a second contact surface located on a second side thereof, the second side of the other HV component chip being opposite the first side of the other HV component chip, the first contact surface of the other HV component chip being coplanar with the first side of the reconstituted wafer, and the second contact surface of the other HV component chip being coplanar with a second side of the reconstituted wafer, the second side of the reconstituted wafer being opposite the first side; and a redistribution layer extending over the second side of the reconstituted wafer, the redistribution layer comprising a routing trace coupled to the second contact surface of the other HV component chip; and wherein the reconstituted wafer includes a conductive through polymer via (TPV) extending alongside the other HV component chip, from a first end at the first side of the wafer to a second end at the second side of the wafer, the first end of the TPV forming an interconnect segment for the other HV component chip, and the second end of the TPV being coupled to the routing trace of the redistribution layer. 13. The package of claim 11, further comprising:
a stacked pair of reconstituted chips encapsulated in the reconstituted wafer, each reconstituted chip of the stacked pair comprising a first side, a first contact surface located on the first side, a second, opposite side, a second contact surface located on the second side, and a routing trace extending over the corresponding second side and being coupled to the corresponding second contact surface; and wherein the first contact surface of a first reconstituted chip of the stacked pair is coplanar with the first side of the reconstituted wafer, and the first contact surface of a second reconstituted chip of the stacked pair is coplanar with the second side of the reconstituted wafer; and the reconstituted wafer includes a conductive through polymer via (TPV) extending alongside the stacked pair, from a first end at the first side of the wafer to a second end at the second side of the wafer, the TPV coupling together the routing traces that extend over the second sides of the stacked pair of reconstituted chips. 14. The package of claim 11, further comprising:
a stacked pair of reconstituted chips encapsulated in the reconstituted wafer, a first reconstituted chip of the stacked pair comprising a first side, a first contact surface located on the first side, a second, opposite side, a second contact surface located on the second side, and a routing trace extending over the second side and being coupled to the corresponding second contact surface, and a second reconstituted chip of the stacked pair comprising a first side, a first contact surface located on the first side of the second reconstituted chip, a second side, a second contact surface located on the second side of the second reconstituted chip, a through polymer via (TPV) extending from a first end, at the first side of the second reconstituted chip, to a second end, at the second side of the second reconstituted chip, and a routing trace extending over the second side of the second reconstituted chip and coupling the second contact surface of the second reconstituted chip to the second end of the TPV of the second reconstituted chip; and a conductive adhesive adhering the second sides of the stacked pair of reconstituted chips together to conductively couple the routing traces thereof; and wherein the first contact surface of the first reconstituted chip of the stacked pair is coplanar with the first side of the reconstituted wafer, and the first contact surface of the second reconstituted chip of the stacked pair is coplanar with the second side of the reconstituted wafer. 15. The package of claim 11, further comprising:
a stacked pair of reconstituted chips encapsulated in the reconstituted wafer, a first reconstituted chip of the stacked pair comprising a first side, a first contact surface located on the first side, a second, opposite side, a second contact surface located on the second side, a through polymer via (TPV) extending from a first end, at the first side, to a second end, at the second side, and a routing trace extending over the second side and coupling the second contact surface to the second end of the TPV, and a second reconstituted chip of the stacked pair comprising a first side, a first contact surface located on the first side of the second reconstituted chip, a second side, a second contact surface located on the second side of the second reconstituted chip, a through polymer via (TPV) extending from a first end, at the first side of the second reconstituted chip, to a second end, at the second side of the second reconstituted chip, and a routing trace extending over the second side of the second reconstituted chip and coupling the second contact surface of the second reconstituted chip to the second end of the TPV of the second reconstituted chip; and a non-conductive adhesive adhering the second sides of the stacked pair of reconstituted chips together; and wherein the first contact surface of the first reconstituted chip of the stacked pair is coplanar with the first side of the reconstituted wafer, and the first contact surface of the second reconstituted chip of the stacked pair is coplanar with the second side of the reconstituted wafer. 16. The package of claim 11, further comprising:
a redistribution layer extending over a second side of the reconstituted wafer, the second side of the wafer being opposite the first side thereof; and a heat sink plate extending within or over the redistribution layer; wherein the second side of the reconstituted chip is recessed from a second side of the reconstituted wafer; and the reconstituted wafer includes an array of heat pipes formed therein and extending from the second side of the reconstituted chip to the heat sink plate. 17. The package of claim 11, further comprising:
a redistribution layer extending over a second side of the reconstituted wafer, the second side of the wafer being opposite the first side thereof; and a heat sink plate extending within or over the redistribution layer; wherein the second side of the reconstituted chip is recessed from a second side of the reconstituted wafer; and the reconstituted chip further comprises an array of columns of stacked gold stud bumps mounted on the second side of reconstituted chip and extending to the heat sink plate. 18. The package of claim 1, further comprising a heat sink plate extending over a second side of the reconstituted wafer, the second side of the reconstituted wafer being opposite the first side thereof; and wherein:
the second side of the HV chip is recessed from the second side of the reconstituted wafer; and the reconstituted wafer includes an array of heat pipes formed therein and extending from the second side of the HV chip to the heat sink plate. 19. The package of claim 1, further comprising a heat sink plate extending over a second side of the reconstituted wafer, the second side of the reconstituted wafer being opposite the first side thereof; and wherein:
the second side of the HV chip is recessed from the second side of the reconstituted wafer; and the HV chip further includes an array of columns of stacked gold stud bumps mounted on the second side of the HV chip and extending to the heat sink plate. 20. A method for forming a wafer level package of a high voltage unit suitable for an implantable cardiac defibrillator, the method comprising:
encapsulating a plurality of individual high voltage (HV) component chips in a polymer mold compound to form a first reconstituted wafer, such that a first side of each HV chip is coplanar with a first side of the first reconstituted wafer, each HV chip including a first contact surface located on the first side thereof, a second contact surface located on a second side thereof, the second side of each HV chip being opposite the first side of each HV chip, forming a redistribution layer over a second side of the wafer, the second side being opposite the first side thereof, and the redistribution layer comprising a plurality of routing traces, each routing trace of the plurality being coupled to the second contact surface of a corresponding HV chip of the plurality of HV component chips; singulating individual reconstituted chips from the first reconstituted wafer, each individual reconstituted chip including one of the plurality of HV chips and the corresponding routing trace; and encapsulating one or more of the individual reconstituted chips, along with other components of the high voltage unit in a polymer mold compound to form a second reconstituted wafer, such that the first contact surface of at least one of the one or more encapsulated reconstituted chips is coplanar with a first side of the second reconstituted wafer. 21. The method of claim 20, wherein each HV chip further includes a conductive crest protruding from the corresponding second contact surface; and further comprising thinning the first reconstituted wafer, before forming the redistribution layer, to expose the conductive crest of each encapsulated HV chip at the second side of the first reconstituted wafer for coupling to the corresponding routing trace. 22. The method of claim 20, further comprising:
thinning the first reconstituted wafer, before forming the redistribution layer, to within approximately 25 micrometers from each second contact surface; and forming a plurality of conductive vias from the second side of the first reconstituted wafer, before forming the redistribution layer, each via of the plurality of vias extending to a corresponding second contact surface for coupling to the corresponding routing trace when the redistribution layer is formed. 23. The method of claim 20, further comprising forming a plurality of conductive through polymer vias prior to singulating individual reconstituted chips, each through polymer via (TPV) extending alongside each encapsulated HV chip and from a first end thereof, that is coplanar with the first contact surface of the corresponding HV chip, to a second end thereof, that is coupled to the routing trace of the corresponding HV chip; and wherein each individual reconstituted chip further includes the TPV coupled to the routing trace thereof. 24. The method of claim 23, wherein the other encapsulated components of the high voltage unit comprise another HV component chip, the other HV component chip being thicker than the one or more reconstituted chips and including a first contact surface located on a first side thereof, and a second contact surface located on a second side thereof, the second side of the other HV component chip being opposite the first side thereof, and the first side of the other HV component chip being coplanar with the first side of the second reconstituted wafer; and further comprising:
thinning the second reconstituted wafer to form a second side thereof adjacent to the second side of the other HV component chip; forming a redistribution layer over the second side of the thinned second reconstituted wafer, the redistribution layer comprising a routing trace coupled to the second contact surface of the other HV component chip; and forming a conductive through polymer via (TPV) in the second reconstituted wafer extending alongside the other HV chip, the TPV in the second reconstituted wafer being coupled to and extending from the routing trace, that is coupled to the second contact surface of the other HV component chip, to the first side of the second reconstituted wafer. 25. The method of claim 23, wherein the one or more individual reconstituted chips includes a first reconstituted chip and a second reconstituted chip; and further comprising bonding a backside of the first reconstituted chip to a backside of the second reconstituted chip, prior to encapsulating, the backside of each of the first and second reconstituted chips being defined by the redistribution layer formed over the second side thereof. 26. The method of claim 25, further comprising forming a through polymer via (TPV) through the second reconstituted wafer to couple together the routing traces of the first and second reconstituted chips. 27. The method of claim 25, wherein the backsides of the first and second reconstituted chips are bonded together with a non-conductive adhesive. 28. The method of claim 23, further comprising bonding, with a conductive adhesive, a backside of one of the one or more individual reconstituted chips to a backside of a second individual reconstituted chip, prior to encapsulating, the backside of the one of the one or more individual reconstituted chips being defined by the redistribution layer formed over the second side thereof, the backside of the second individual reconstituted chip being defined by a redistribution layer that includes a routing trace coupled to a contact surface thereof, and the first contact surface of the second individual reconstituted chip being coplanar with the first side of the second reconstituted wafer. | 2,800 |
11,964 | 11,964 | 16,225,003 | 2,842 | A light emitting diode (LED) luminaire device includes an LED housing with one or more LED modules. Each LED module includes one or more LED arrays and a control circuit. The LED luminaire device also includes an antenna that is electrically connected to a contact surface, a plurality of contacts electrically connected to one of either the control circuit or the contact surface, and a plurality of landing pads electrically connected to the other of either the control circuit or the contact surface. One or more of the plurality of contacts and one or more of the plurality of landing pads are positioned to align to each other and provide one or more conductive paths for communication signals between the antenna and the control circuit when the LED housing is proximate to the contact surface. | 1. A light emitting diode (LED) luminaire device, comprising:
an LED housing comprising one or more LED modules, wherein each LED module comprises one or more LED arrays and a control circuit; an antenna that is electrically connected to a contact surface; a plurality of contacts electrically connected to one of either the control circuit or the contact surface; and a plurality of landing pads electrically connected to the other of either the control circuit or the contact surface; wherein one or more of the plurality of contacts and one or more of the plurality of landing pads are positioned to align to each other and provide one or more conductive paths for communication signals between the antenna and the control circuit when the LED housing is proximate to the contact surface. 2. The LED luminaire device of claim 1, wherein:
the LED housing further comprises an interface plate; and the control circuit is connected to the interface plate. 3. The LED luminaire device of claim 1, wherein one or more of the plurality of contacts are included in a contact housing. 4. The LED luminaire device of claim 3, wherein the one or more of the plurality of contacts and the corresponding contact housing are cylindrical in shape. 5. The LED luminaire device of claim 3, wherein the one or more of the plurality of contacts comprise a resilient member configured to push a conductive contact outwards when in a relaxed position and move the conductive contact at least partially inside the contact housing when in a compressed position. 6. The LED luminaire device of claim 5, wherein the resilient member is a spring. 7. The LED luminaire device of claim 5, wherein the resilient member is in a compressed position when the LED housing is proximate to the contact surface. 8. The LED luminaire device of claim 1, wherein:
the antenna and the contact surface are included in a body; and the LED housing is proximate to the contact surface when the LED housing is connected to the body. 9. The LED luminaire device of claim 8, wherein the body further comprises a plurality of fins that form a heat sink. 10. The LED luminaire device of claim 8, wherein the contact surface has a shape that allows for the attachment of the contact surface to the body in only one configuration. 11. The LED luminaire device of claim 1, wherein each of the plurality of landing pads has a surface area that is more than a surface area of corresponding ones of the plurality of contacts that form the one or more conductive paths. 12. A light emitting diode (LED) luminaire device, comprising:
an LED housing comprising:
one or more LED modules,
an interface plate, and
a control circuit connected to the interface plate, wherein the control circuit is electrically connected to each of the LED modules;
an antenna that is electrically connected to a contact surface; a plurality of contacts electrically connected to one of either the control circuit or the contact surface; and a plurality of landing pads electrically connected to the other of either the control circuit or the contact surface; wherein one or more of the plurality of contacts and one or more of the plurality of landing pads are positioned to align to each other and provide one or more conductive paths for communication signals between the antenna and the control circuit when the LED housing is proximate to the contact surface. 13. The LED luminaire device of claim 12, wherein one or more of the plurality of contacts are included in a contact housing. 14. The LED luminaire device of claim 13, wherein the one or more of the plurality of contacts and the corresponding contact housing are cylindrical in shape. 15. The LED luminaire device of claim 13, wherein the one or more of the plurality of contacts comprise a resilient member configured to push a conductive contact outwards when in a relaxed position and move the conductive contact at least partially inside the contact housing when in a compressed position. 16. The LED luminaire device of claim 15, wherein the resilient member is a spring. 17. The LED luminaire device of claim 15, wherein the resilient member is in a compressed position when the LED housing is proximate to the contact surface. 18. The LED luminaire device of claim 12, wherein:
the antenna and the contact surface are included in a body; and the LED housing is proximate to the contact surface when the LED housing is connected to the body. 19. The LED luminaire device of claim 18, wherein the body further comprises a plurality of fins that form a heat sink. 20. The LED luminaire device of claim 18, wherein the contact surface has a shape that allows for the attachment of the contact surface to the body in only one configuration. 21. The LED luminaire device of claim 12, wherein each of the plurality of landing pads has a surface area that is more than a surface area of corresponding ones of the plurality of contacts that form the one or more conductive paths. | A light emitting diode (LED) luminaire device includes an LED housing with one or more LED modules. Each LED module includes one or more LED arrays and a control circuit. The LED luminaire device also includes an antenna that is electrically connected to a contact surface, a plurality of contacts electrically connected to one of either the control circuit or the contact surface, and a plurality of landing pads electrically connected to the other of either the control circuit or the contact surface. One or more of the plurality of contacts and one or more of the plurality of landing pads are positioned to align to each other and provide one or more conductive paths for communication signals between the antenna and the control circuit when the LED housing is proximate to the contact surface.1. A light emitting diode (LED) luminaire device, comprising:
an LED housing comprising one or more LED modules, wherein each LED module comprises one or more LED arrays and a control circuit; an antenna that is electrically connected to a contact surface; a plurality of contacts electrically connected to one of either the control circuit or the contact surface; and a plurality of landing pads electrically connected to the other of either the control circuit or the contact surface; wherein one or more of the plurality of contacts and one or more of the plurality of landing pads are positioned to align to each other and provide one or more conductive paths for communication signals between the antenna and the control circuit when the LED housing is proximate to the contact surface. 2. The LED luminaire device of claim 1, wherein:
the LED housing further comprises an interface plate; and the control circuit is connected to the interface plate. 3. The LED luminaire device of claim 1, wherein one or more of the plurality of contacts are included in a contact housing. 4. The LED luminaire device of claim 3, wherein the one or more of the plurality of contacts and the corresponding contact housing are cylindrical in shape. 5. The LED luminaire device of claim 3, wherein the one or more of the plurality of contacts comprise a resilient member configured to push a conductive contact outwards when in a relaxed position and move the conductive contact at least partially inside the contact housing when in a compressed position. 6. The LED luminaire device of claim 5, wherein the resilient member is a spring. 7. The LED luminaire device of claim 5, wherein the resilient member is in a compressed position when the LED housing is proximate to the contact surface. 8. The LED luminaire device of claim 1, wherein:
the antenna and the contact surface are included in a body; and the LED housing is proximate to the contact surface when the LED housing is connected to the body. 9. The LED luminaire device of claim 8, wherein the body further comprises a plurality of fins that form a heat sink. 10. The LED luminaire device of claim 8, wherein the contact surface has a shape that allows for the attachment of the contact surface to the body in only one configuration. 11. The LED luminaire device of claim 1, wherein each of the plurality of landing pads has a surface area that is more than a surface area of corresponding ones of the plurality of contacts that form the one or more conductive paths. 12. A light emitting diode (LED) luminaire device, comprising:
an LED housing comprising:
one or more LED modules,
an interface plate, and
a control circuit connected to the interface plate, wherein the control circuit is electrically connected to each of the LED modules;
an antenna that is electrically connected to a contact surface; a plurality of contacts electrically connected to one of either the control circuit or the contact surface; and a plurality of landing pads electrically connected to the other of either the control circuit or the contact surface; wherein one or more of the plurality of contacts and one or more of the plurality of landing pads are positioned to align to each other and provide one or more conductive paths for communication signals between the antenna and the control circuit when the LED housing is proximate to the contact surface. 13. The LED luminaire device of claim 12, wherein one or more of the plurality of contacts are included in a contact housing. 14. The LED luminaire device of claim 13, wherein the one or more of the plurality of contacts and the corresponding contact housing are cylindrical in shape. 15. The LED luminaire device of claim 13, wherein the one or more of the plurality of contacts comprise a resilient member configured to push a conductive contact outwards when in a relaxed position and move the conductive contact at least partially inside the contact housing when in a compressed position. 16. The LED luminaire device of claim 15, wherein the resilient member is a spring. 17. The LED luminaire device of claim 15, wherein the resilient member is in a compressed position when the LED housing is proximate to the contact surface. 18. The LED luminaire device of claim 12, wherein:
the antenna and the contact surface are included in a body; and the LED housing is proximate to the contact surface when the LED housing is connected to the body. 19. The LED luminaire device of claim 18, wherein the body further comprises a plurality of fins that form a heat sink. 20. The LED luminaire device of claim 18, wherein the contact surface has a shape that allows for the attachment of the contact surface to the body in only one configuration. 21. The LED luminaire device of claim 12, wherein each of the plurality of landing pads has a surface area that is more than a surface area of corresponding ones of the plurality of contacts that form the one or more conductive paths. | 2,800 |
11,965 | 11,965 | 15,396,530 | 2,813 | Heat dissipation technology in a die stack is disclosed. In one example, an electronic device comprises a pair of electrically coupled dies; and a heat spreader disposed between the pair of dies and electrically isolated from an electrical connection between the pair of dies. | 1. An electronic device, comprising:
a pair of electrically coupled dies; and a heat spreader disposed between the pair of dies and electrically isolated from an electrical connection between the pair of dies. 2. The electronic device of claim 1, wherein at least a portion of the heat spreader is exposed from between the pair of dies to dissipate heat from between the pair of dies. 3. The electronic device of claim 1, wherein the heat spreader extends beyond a perimeter of at least one of the pair of dies. 4. The electronic device of claim 1, wherein the heat spreader extends to at least a perimeter of at least one of the pair of dies. 5. The electronic device of claim 1, wherein the heat spreader is disposed on one of the pair of dies. 6. The electronic device of claim 1, wherein the electrical connection further comprises through silicon vias (TSVs) extending through one of the pair of dies and electrically coupled to the other of the pair of dies. 7. The electronic device of claim 6, wherein the heat spreader is laterally isolated from the TSVs by an electrical insulator. 8. The electronic device of claim 6, wherein the heat spreader circumscribes the TSVs and extends between the TSVs. 9. The electronic device of claim 6, further comprising:
a first metallization disposed on the TSVs and forming extensions of the TSVs electrically coupled to the other of the pair of dies; a second metallization disposed on one of the pair of dies and defining the heat spreader; and an electrical insulator electrically isolating the second metallization from the first metallization. 10. The electronic device of claim 1, further comprising:
an exposed portion of the heat spreader extending beyond at least one of the pair of dies; and a thermal interface material disposed on the exposed portion of the heat spreader. 11. The electronic device of claim 10, further comprising:
a metal cap disposed over the pair of dies; and the thermal interface material extending from the exposed portion of the heat spreader and the metal cap. 12. The electronic device of claim 1, wherein:
the pair of dies comprises a bottom die and a top die disposed over the bottom die; the electrical connection comprises through silicon vias (TSVs) extending through the bottom die and electrically coupled to the top die; at least a perimeter of the bottom die extends laterally beyond a perimeter of the top die defining a step; and the heat spreader extends from between the top and bottom dies and onto the step. 13. An electronic device package, comprising:
a substrate; a bottom die disposed over and electrically coupled to the substrate and having through silicon vias (TSVs) extending through the bottom die; a top die disposed over the bottom die and electrically coupled to the TSVs; and a heat spreader embedded between the top and bottom dies and electrically isolated from the TSVs. 14. The electronic device package of claim 13, wherein at least a portion of the heat spreader is exposed from between the top and bottom dies to dissipate heat from between the top and bottom dies. 15. The electronic device package of claim 13, wherein the heat spreader extends beyond a perimeter of at least one of the top and bottom dies. 16. The electronic device package of claim 13, wherein the heat spreader extends to at least a perimeter of at least one of the top and bottom dies. 17. The electronic device package of claim 13, wherein the heat spreader is disposed on at least one of the top and bottom dies. 18. The electronic device of package claim 13, wherein the heat spreader is laterally isolated from the TSVs by an electrical insulator. 19. The electronic device package of claim 13, wherein the heat spreader circumscribes the TSVs and extends between the TSVs. 20. The electronic device package of claim 13, further comprising:
a first metallization disposed on the TSVs and forming extensions of the TSVs electrically coupled to the top die; a second metallization disposed on the bottom die and defining the heat spreader; and an electrical insulator electrically isolating the second metallization from the first metallization. 21. The electronic device package of claim 13, further comprising:
an exposed portion of the heat spreader extending beyond the top die; and a thermal interface material disposed on the exposed portion of the heat spreader. 22. The electronic device package of claim 21, further comprising:
a metal cap disposed on the substrate and over the top and bottom dies; and the thermal interface material extending from the exposed portion of the heat spreader and the metal cap. 23. The electronic device package of claim 13, wherein:
at least a perimeter of the bottom die extends laterally beyond a perimeter of the top die defining a step; and the heat spreader extends from between the top and bottom dies and onto the step. 24. A method for making an electronic device package, comprising:
providing a substrate; disposing a bottom die over the substrate and electrically coupling the bottom die to the substrate, the bottom die having through silicon vias (TSVs) extending through the bottom die, the bottom die having a heat spreader disposed over the bottom die and electrically isolated from the TSVs; and disposing a top die over the bottom die and electrically coupling the top die to the TSVs. 25. The method of claim 24, further comprising applying a thermal interface material to an exposed portion of the heat spreader. 26. The method of claim 25, further comprising disposing a metal cap on the substrate and covering the top and bottom dies with the thermal interface material extending to the metal cap. 27. The method of claim 24, wherein the heat spreader is laterally isolated from the TSVs by an electrical insulator. 28. The method of claim 24, wherein the heat spreader circumscribes the TSVs and extends between the TSVs. 29. The method of claim 24, further comprising:
a first metallization disposed on the TSVs and forming extensions of the TSVs electrically coupled to the top die; a second metallization disposed on the bottom die and defining the heat spreader; and an electrical insulator electrically isolating the second metallization from the first metallization. | Heat dissipation technology in a die stack is disclosed. In one example, an electronic device comprises a pair of electrically coupled dies; and a heat spreader disposed between the pair of dies and electrically isolated from an electrical connection between the pair of dies.1. An electronic device, comprising:
a pair of electrically coupled dies; and a heat spreader disposed between the pair of dies and electrically isolated from an electrical connection between the pair of dies. 2. The electronic device of claim 1, wherein at least a portion of the heat spreader is exposed from between the pair of dies to dissipate heat from between the pair of dies. 3. The electronic device of claim 1, wherein the heat spreader extends beyond a perimeter of at least one of the pair of dies. 4. The electronic device of claim 1, wherein the heat spreader extends to at least a perimeter of at least one of the pair of dies. 5. The electronic device of claim 1, wherein the heat spreader is disposed on one of the pair of dies. 6. The electronic device of claim 1, wherein the electrical connection further comprises through silicon vias (TSVs) extending through one of the pair of dies and electrically coupled to the other of the pair of dies. 7. The electronic device of claim 6, wherein the heat spreader is laterally isolated from the TSVs by an electrical insulator. 8. The electronic device of claim 6, wherein the heat spreader circumscribes the TSVs and extends between the TSVs. 9. The electronic device of claim 6, further comprising:
a first metallization disposed on the TSVs and forming extensions of the TSVs electrically coupled to the other of the pair of dies; a second metallization disposed on one of the pair of dies and defining the heat spreader; and an electrical insulator electrically isolating the second metallization from the first metallization. 10. The electronic device of claim 1, further comprising:
an exposed portion of the heat spreader extending beyond at least one of the pair of dies; and a thermal interface material disposed on the exposed portion of the heat spreader. 11. The electronic device of claim 10, further comprising:
a metal cap disposed over the pair of dies; and the thermal interface material extending from the exposed portion of the heat spreader and the metal cap. 12. The electronic device of claim 1, wherein:
the pair of dies comprises a bottom die and a top die disposed over the bottom die; the electrical connection comprises through silicon vias (TSVs) extending through the bottom die and electrically coupled to the top die; at least a perimeter of the bottom die extends laterally beyond a perimeter of the top die defining a step; and the heat spreader extends from between the top and bottom dies and onto the step. 13. An electronic device package, comprising:
a substrate; a bottom die disposed over and electrically coupled to the substrate and having through silicon vias (TSVs) extending through the bottom die; a top die disposed over the bottom die and electrically coupled to the TSVs; and a heat spreader embedded between the top and bottom dies and electrically isolated from the TSVs. 14. The electronic device package of claim 13, wherein at least a portion of the heat spreader is exposed from between the top and bottom dies to dissipate heat from between the top and bottom dies. 15. The electronic device package of claim 13, wherein the heat spreader extends beyond a perimeter of at least one of the top and bottom dies. 16. The electronic device package of claim 13, wherein the heat spreader extends to at least a perimeter of at least one of the top and bottom dies. 17. The electronic device package of claim 13, wherein the heat spreader is disposed on at least one of the top and bottom dies. 18. The electronic device of package claim 13, wherein the heat spreader is laterally isolated from the TSVs by an electrical insulator. 19. The electronic device package of claim 13, wherein the heat spreader circumscribes the TSVs and extends between the TSVs. 20. The electronic device package of claim 13, further comprising:
a first metallization disposed on the TSVs and forming extensions of the TSVs electrically coupled to the top die; a second metallization disposed on the bottom die and defining the heat spreader; and an electrical insulator electrically isolating the second metallization from the first metallization. 21. The electronic device package of claim 13, further comprising:
an exposed portion of the heat spreader extending beyond the top die; and a thermal interface material disposed on the exposed portion of the heat spreader. 22. The electronic device package of claim 21, further comprising:
a metal cap disposed on the substrate and over the top and bottom dies; and the thermal interface material extending from the exposed portion of the heat spreader and the metal cap. 23. The electronic device package of claim 13, wherein:
at least a perimeter of the bottom die extends laterally beyond a perimeter of the top die defining a step; and the heat spreader extends from between the top and bottom dies and onto the step. 24. A method for making an electronic device package, comprising:
providing a substrate; disposing a bottom die over the substrate and electrically coupling the bottom die to the substrate, the bottom die having through silicon vias (TSVs) extending through the bottom die, the bottom die having a heat spreader disposed over the bottom die and electrically isolated from the TSVs; and disposing a top die over the bottom die and electrically coupling the top die to the TSVs. 25. The method of claim 24, further comprising applying a thermal interface material to an exposed portion of the heat spreader. 26. The method of claim 25, further comprising disposing a metal cap on the substrate and covering the top and bottom dies with the thermal interface material extending to the metal cap. 27. The method of claim 24, wherein the heat spreader is laterally isolated from the TSVs by an electrical insulator. 28. The method of claim 24, wherein the heat spreader circumscribes the TSVs and extends between the TSVs. 29. The method of claim 24, further comprising:
a first metallization disposed on the TSVs and forming extensions of the TSVs electrically coupled to the top die; a second metallization disposed on the bottom die and defining the heat spreader; and an electrical insulator electrically isolating the second metallization from the first metallization. | 2,800 |
11,966 | 11,966 | 16,245,718 | 2,847 | Coated articles are provided comprising:
(a) a substrate that demonstrates electrical conductivity; and (b) a coating layer applied to at least one surface of the substrate;
wherein the coating layer demonstrates push-through electrical connectivity. The coated articles are particularly suitable for use in circuit assemblies. | 1. A coated article comprising:
(a) a substrate that demonstrates electrical conductivity; and (b) a coating layer applied to at least one surface of the substrate; wherein the coating layer demonstrates push-through electrical connectivity. 2. The coated article of claim 1 wherein the substrate comprises an electrically conductive circuit pattern imprinted in or on the substrate surface. 3. The coated article of claim 2 wherein the substrate is an electronic component of a circuit assembly. 4. The coated article of claim 3 wherein the substrate is a printed circuit board. 5. The coated article of claim 1, wherein the coating layer is deposited from a film-forming composition comprising a polysiloxane and an organometallic compound in a solvent. 6. The coated article of claim 5 wherein the polysiloxane comprises poly(methylphenyl)siloxane and/or polydimethylsiloxane. 7. The coated article of claim 6 wherein the polysiloxane comprises terminal methyl and/or silanol groups. 8. The coated article of claim 5 wherein the organometallic compound has the structure [M(O)x(OH)y(OR)z]n in which M is a transition metal; R is an alkyl group containing from 1 to 30 carbon atoms; x+y+z=V, wherein V is the valence of M; x is at least 1; y is at least 1; z is at least 1; x=V−y−z; y=V−x−z; z=V−x−y; and n is greater than 2. 9. The coated article of claim 8 wherein the metal is selected from at least one of La, Hf, Ta, W, and Nb. 10. The coated article of claim 5 wherein the solvent comprises isooctane. 11. The coated article of claim 1, wherein the coating layer is deposited from a film-forming composition comprising a fluorinated polymer in a fluorinated solvent. 12. The coated article of claim 11, wherein the film-forming composition further comprises a filler. 13. The coated article of claim 11, wherein the film-forming composition further comprises a viscosity modifying component. 14. The coated article of claim 1, wherein the coating layer has a dry film thickness of 100 nm to 100 microns. 15. The coated article of claim 1, wherein the coating layer is deposited from a film-forming composition comprising a hydrocarbon addition polymer in a hydrocarbon solvent. 16. The coated article of claim 15, wherein the film-forming composition further comprises a filler. 17. The coated article of claim 15, wherein the film-forming composition further comprises a viscosity modifying component. 18. The coated article of claim 15, wherein the hydrocarbon solvent comprises methyl cyclohexane, toluene, and/or cyclohexane. 19. The coated article of claim 1, wherein the coating layer is deposited from a film-forming composition comprising at least one terpolymer in a solvent, wherein the terpolymer is prepared from a reaction mixture comprising ethylene, propylene, and a diene. 20. The coated article of claim 19, wherein the diene comprises 5-ethylidenenorbornene (ENB) and/or dicyclopentadiene (DCPD). | Coated articles are provided comprising:
(a) a substrate that demonstrates electrical conductivity; and (b) a coating layer applied to at least one surface of the substrate;
wherein the coating layer demonstrates push-through electrical connectivity. The coated articles are particularly suitable for use in circuit assemblies.1. A coated article comprising:
(a) a substrate that demonstrates electrical conductivity; and (b) a coating layer applied to at least one surface of the substrate; wherein the coating layer demonstrates push-through electrical connectivity. 2. The coated article of claim 1 wherein the substrate comprises an electrically conductive circuit pattern imprinted in or on the substrate surface. 3. The coated article of claim 2 wherein the substrate is an electronic component of a circuit assembly. 4. The coated article of claim 3 wherein the substrate is a printed circuit board. 5. The coated article of claim 1, wherein the coating layer is deposited from a film-forming composition comprising a polysiloxane and an organometallic compound in a solvent. 6. The coated article of claim 5 wherein the polysiloxane comprises poly(methylphenyl)siloxane and/or polydimethylsiloxane. 7. The coated article of claim 6 wherein the polysiloxane comprises terminal methyl and/or silanol groups. 8. The coated article of claim 5 wherein the organometallic compound has the structure [M(O)x(OH)y(OR)z]n in which M is a transition metal; R is an alkyl group containing from 1 to 30 carbon atoms; x+y+z=V, wherein V is the valence of M; x is at least 1; y is at least 1; z is at least 1; x=V−y−z; y=V−x−z; z=V−x−y; and n is greater than 2. 9. The coated article of claim 8 wherein the metal is selected from at least one of La, Hf, Ta, W, and Nb. 10. The coated article of claim 5 wherein the solvent comprises isooctane. 11. The coated article of claim 1, wherein the coating layer is deposited from a film-forming composition comprising a fluorinated polymer in a fluorinated solvent. 12. The coated article of claim 11, wherein the film-forming composition further comprises a filler. 13. The coated article of claim 11, wherein the film-forming composition further comprises a viscosity modifying component. 14. The coated article of claim 1, wherein the coating layer has a dry film thickness of 100 nm to 100 microns. 15. The coated article of claim 1, wherein the coating layer is deposited from a film-forming composition comprising a hydrocarbon addition polymer in a hydrocarbon solvent. 16. The coated article of claim 15, wherein the film-forming composition further comprises a filler. 17. The coated article of claim 15, wherein the film-forming composition further comprises a viscosity modifying component. 18. The coated article of claim 15, wherein the hydrocarbon solvent comprises methyl cyclohexane, toluene, and/or cyclohexane. 19. The coated article of claim 1, wherein the coating layer is deposited from a film-forming composition comprising at least one terpolymer in a solvent, wherein the terpolymer is prepared from a reaction mixture comprising ethylene, propylene, and a diene. 20. The coated article of claim 19, wherein the diene comprises 5-ethylidenenorbornene (ENB) and/or dicyclopentadiene (DCPD). | 2,800 |
11,967 | 11,967 | 14,615,821 | 2,882 | An illumination module configured for mounting at a vehicle includes at least one illumination source and an optic. The optic is a three dimensional single formed optic that is formed such that, when the illumination source is operated and when the illumination module is disposed at a side of a vehicle, the optic provides projection of an icon, a logo and/or indicia at a ground region at or near the side of the vehicle. The optic includes one of (a) a lens optic configured such that light emitted by the illumination source, when activated, passes through the lens optic to provide projection of the icon, the logo and/or indicia, and (b) a reflector optic configured such that light emitted by the illumination source, when activated, reflects off the reflector optic to provide the selected projection of the icon, the logo and/or indicia. | 1. An illumination module for a vehicle, said illumination module configured for mounting at a side of a vehicle, said illumination module comprising:
at least one illumination source and an optic; wherein said optic comprises a three dimensional single formed optic that is formed such that, when said at least one illumination source is operated and when said illumination module is disposed at a side of a vehicle equipped with said illumination module, said optic provides projection of at least one of (i) an icon, (ii) a logo and (iii) indicia at a ground region at or near the side of the equipped vehicle; and wherein said three dimensional single formed optic comprises one of (a) a lens optic configured such that light emitted by said at least one illumination source, when activated, passes through said lens optic to provide projection of the at least one of (i) an icon, (ii) a logo and (iii) indicia at the ground region at or near the side of the equipped vehicle, and (b) a reflector optic configured such that light emitted by said at least one illumination source, when activated, reflects off said reflector optic to provide projection of the at least one of (i) an icon, (ii) a logo and (iii) indicia at the ground region at or near the side of the equipped vehicle. 2. The illumination module of claim 1, wherein said at least one illumination source comprises a light emitting diode. 3. The illumination module of claim 1, wherein said illumination module is substantially water impervious. 4. The illumination module of claim 1, wherein said three dimensional single formed optic comprises a freeform optic, and wherein said freeform optic provides a three dimensional surface of said freeform optic that, when light passes through said freeform optic, said freeform optic projects the at least one of (i) an icon, (ii) a logo and (iii) indicia. 5. The illumination module of claim 4, wherein mathematical equations are processed responsive to selected parameters, and wherein, responsive to the selected parameters, the mathematical equations are solved to establish the light entrance and light exit surfaces of said freeform optic. 6. The illumination module of claim 5, wherein the selected parameters comprise at least one of (i) selected targets, (ii) selected luminance and (iii) selected optic parameters. 7. The illumination module of claim 1, wherein said three dimensional single formed optic comprises a lens optic configured such that light emitted by said at least one illumination source, when activated, passes through said lens optic to provide a ground illumination pattern over an illuminated ground region at or near the side of the equipped vehicle. 8. The illumination module of claim 7, wherein the ground illumination is a particular illumination pattern established by the formed surfaces of said three dimensional single formed optic. 9. The illumination module of claim 1, wherein said three dimensional single formed optic comprises a lens optic configured such that light emitted by said at least one illumination source, when activated, passes through said lens optic to provide projection of the at least one of (i) an icon, (ii) a logo and (iii) indicia at the ground region at or near the side of the equipped vehicle. 10. The illumination module of claim 1, wherein said at least one illumination source comprises at least one light emitting diode and wherein said lens is overmolded over said at least one light emitting diode. 11. A method of making an illumination module for a vehicle, said method comprising:
providing an illumination source; determining a light pattern that is to be emitted by said illumination module when said illumination source is activated and when said illumination module is disposed at a side of a vehicle equipped with said illumination module; determining three dimensional surfaces of an optic so that light passing through or reflecting off said optic corresponds to the determined light pattern; forming said optic with the determined three dimensional surfaces, wherein said optic comprises one of (i) a lens optic configured so that light passing through said lens optic corresponds to the determined light pattern and (ii) a reflector optic configured so that light reflecting off said reflector optic corresponds to the determined light pattern; assembling said illumination module with said optic and said illumination source, such that light emitted by said illumination source, when activated, passes through or reflects off said optic and provides the determined light pattern; and wherein the determined light pattern comprises at least one of (i) an icon, (ii) a logo and (iii) indicia that, when said illumination module is disposed at the side of the equipped vehicle and when said illumination source is activated, is projected onto a ground region at or near the side of the equipped vehicle. 12. The method of claim 11, wherein the determined light pattern comprises a illumination pattern that illuminates an area at or near said illumination module. 13. The method of claim 12, wherein, when said illumination module is mounted at the exterior portion of the equipped vehicle and when said illumination source is activated, said illumination pattern illuminates a ground area at or near the side of the equipped vehicle at which said ground illumination module is disposed. 14. The method of claim 13, wherein determining a light pattern comprises determining a light pattern that provides a higher intensity illumination region at the ground area and lesser intensity illumination regions at the ground area. 15. The method of claim 11, wherein determining three dimensional surfaces of an optic comprises processing mathematical equations to provide three dimensional surfaces that, when light passes through or reflects off the optic, provide the determined light pattern. 16. The method of claim 15, wherein said mathematical equations are processed responsive to selected parameters, and wherein, responsive to the selected parameters, the mathematical equations are solved to establish the three dimensional surfaces of said optic. 17. The method of claim 11, wherein providing an illumination source comprises providing at least one light emitting diode. 18. The method of claim 17, wherein forming said optic comprises forming a lens optic by overmolding said lens optic over said at least one light emitting diode. 19. An illumination module for a vehicle, said illumination module configured for mounting at a side of a vehicle, said illumination module comprising:
at least one illumination source and an optic, wherein said at least one illumination source comprises a light emitting diode, and wherein said illumination module comprises a substantially sealed module such as to be substantially water impervious; wherein said optic comprises a three dimensional single formed optic that is formed such that, when said at least one illumination source is operated and when said illumination module is disposed at a side of a vehicle equipped with said illumination module, said three dimensional single formed optic provides projection of at least one of (i) an icon, (ii) a logo and (iii) indicia at a ground region at or near the side of the equipped vehicle; wherein said three dimensional single formed optic comprises one of (a) a lens optic configured such that light emitted by said at least one illumination source, when activated, passes through said lens optic to provide projection of the at least one of (i) an icon, (ii) a logo and (iii) indicia at the ground region at or near the side of the equipped vehicle, and (b) a reflector optic configured such that light emitted by said at least one illumination source, when activated, reflects off said reflector optic to provide projection of the at least one of (i) an icon, (ii) a logo and (iii) indicia at the ground region at or near the side of the equipped vehicle; and wherein said three dimensional single formed optic comprises a freeform optic, and wherein said freeform optic provides a three dimensional surface of said freeform optic that, when light passes through said freeform optic, said freeform optic projects the at least one of (i) an icon, (ii) a logo and (iii) indicia at the ground region at or near the side of the equipped vehicle. 20. The illumination module of claim 19, wherein said three dimensional single formed optic comprises a lens optic configured such that light emitted by said at least one illumination source, when activated, passes through said lens optic to provide a ground illumination pattern over an illuminated ground region at or near the side of the equipped vehicle, and wherein the ground illumination is a particular illumination pattern established by the formed surfaces of said three dimensional single formed optic, and wherein the particular illumination pattern comprises a higher intensity illumination region at the ground area and a lesser intensity illumination region at the illuminated ground region at or near the side of the equipped vehicle. | An illumination module configured for mounting at a vehicle includes at least one illumination source and an optic. The optic is a three dimensional single formed optic that is formed such that, when the illumination source is operated and when the illumination module is disposed at a side of a vehicle, the optic provides projection of an icon, a logo and/or indicia at a ground region at or near the side of the vehicle. The optic includes one of (a) a lens optic configured such that light emitted by the illumination source, when activated, passes through the lens optic to provide projection of the icon, the logo and/or indicia, and (b) a reflector optic configured such that light emitted by the illumination source, when activated, reflects off the reflector optic to provide the selected projection of the icon, the logo and/or indicia.1. An illumination module for a vehicle, said illumination module configured for mounting at a side of a vehicle, said illumination module comprising:
at least one illumination source and an optic; wherein said optic comprises a three dimensional single formed optic that is formed such that, when said at least one illumination source is operated and when said illumination module is disposed at a side of a vehicle equipped with said illumination module, said optic provides projection of at least one of (i) an icon, (ii) a logo and (iii) indicia at a ground region at or near the side of the equipped vehicle; and wherein said three dimensional single formed optic comprises one of (a) a lens optic configured such that light emitted by said at least one illumination source, when activated, passes through said lens optic to provide projection of the at least one of (i) an icon, (ii) a logo and (iii) indicia at the ground region at or near the side of the equipped vehicle, and (b) a reflector optic configured such that light emitted by said at least one illumination source, when activated, reflects off said reflector optic to provide projection of the at least one of (i) an icon, (ii) a logo and (iii) indicia at the ground region at or near the side of the equipped vehicle. 2. The illumination module of claim 1, wherein said at least one illumination source comprises a light emitting diode. 3. The illumination module of claim 1, wherein said illumination module is substantially water impervious. 4. The illumination module of claim 1, wherein said three dimensional single formed optic comprises a freeform optic, and wherein said freeform optic provides a three dimensional surface of said freeform optic that, when light passes through said freeform optic, said freeform optic projects the at least one of (i) an icon, (ii) a logo and (iii) indicia. 5. The illumination module of claim 4, wherein mathematical equations are processed responsive to selected parameters, and wherein, responsive to the selected parameters, the mathematical equations are solved to establish the light entrance and light exit surfaces of said freeform optic. 6. The illumination module of claim 5, wherein the selected parameters comprise at least one of (i) selected targets, (ii) selected luminance and (iii) selected optic parameters. 7. The illumination module of claim 1, wherein said three dimensional single formed optic comprises a lens optic configured such that light emitted by said at least one illumination source, when activated, passes through said lens optic to provide a ground illumination pattern over an illuminated ground region at or near the side of the equipped vehicle. 8. The illumination module of claim 7, wherein the ground illumination is a particular illumination pattern established by the formed surfaces of said three dimensional single formed optic. 9. The illumination module of claim 1, wherein said three dimensional single formed optic comprises a lens optic configured such that light emitted by said at least one illumination source, when activated, passes through said lens optic to provide projection of the at least one of (i) an icon, (ii) a logo and (iii) indicia at the ground region at or near the side of the equipped vehicle. 10. The illumination module of claim 1, wherein said at least one illumination source comprises at least one light emitting diode and wherein said lens is overmolded over said at least one light emitting diode. 11. A method of making an illumination module for a vehicle, said method comprising:
providing an illumination source; determining a light pattern that is to be emitted by said illumination module when said illumination source is activated and when said illumination module is disposed at a side of a vehicle equipped with said illumination module; determining three dimensional surfaces of an optic so that light passing through or reflecting off said optic corresponds to the determined light pattern; forming said optic with the determined three dimensional surfaces, wherein said optic comprises one of (i) a lens optic configured so that light passing through said lens optic corresponds to the determined light pattern and (ii) a reflector optic configured so that light reflecting off said reflector optic corresponds to the determined light pattern; assembling said illumination module with said optic and said illumination source, such that light emitted by said illumination source, when activated, passes through or reflects off said optic and provides the determined light pattern; and wherein the determined light pattern comprises at least one of (i) an icon, (ii) a logo and (iii) indicia that, when said illumination module is disposed at the side of the equipped vehicle and when said illumination source is activated, is projected onto a ground region at or near the side of the equipped vehicle. 12. The method of claim 11, wherein the determined light pattern comprises a illumination pattern that illuminates an area at or near said illumination module. 13. The method of claim 12, wherein, when said illumination module is mounted at the exterior portion of the equipped vehicle and when said illumination source is activated, said illumination pattern illuminates a ground area at or near the side of the equipped vehicle at which said ground illumination module is disposed. 14. The method of claim 13, wherein determining a light pattern comprises determining a light pattern that provides a higher intensity illumination region at the ground area and lesser intensity illumination regions at the ground area. 15. The method of claim 11, wherein determining three dimensional surfaces of an optic comprises processing mathematical equations to provide three dimensional surfaces that, when light passes through or reflects off the optic, provide the determined light pattern. 16. The method of claim 15, wherein said mathematical equations are processed responsive to selected parameters, and wherein, responsive to the selected parameters, the mathematical equations are solved to establish the three dimensional surfaces of said optic. 17. The method of claim 11, wherein providing an illumination source comprises providing at least one light emitting diode. 18. The method of claim 17, wherein forming said optic comprises forming a lens optic by overmolding said lens optic over said at least one light emitting diode. 19. An illumination module for a vehicle, said illumination module configured for mounting at a side of a vehicle, said illumination module comprising:
at least one illumination source and an optic, wherein said at least one illumination source comprises a light emitting diode, and wherein said illumination module comprises a substantially sealed module such as to be substantially water impervious; wherein said optic comprises a three dimensional single formed optic that is formed such that, when said at least one illumination source is operated and when said illumination module is disposed at a side of a vehicle equipped with said illumination module, said three dimensional single formed optic provides projection of at least one of (i) an icon, (ii) a logo and (iii) indicia at a ground region at or near the side of the equipped vehicle; wherein said three dimensional single formed optic comprises one of (a) a lens optic configured such that light emitted by said at least one illumination source, when activated, passes through said lens optic to provide projection of the at least one of (i) an icon, (ii) a logo and (iii) indicia at the ground region at or near the side of the equipped vehicle, and (b) a reflector optic configured such that light emitted by said at least one illumination source, when activated, reflects off said reflector optic to provide projection of the at least one of (i) an icon, (ii) a logo and (iii) indicia at the ground region at or near the side of the equipped vehicle; and wherein said three dimensional single formed optic comprises a freeform optic, and wherein said freeform optic provides a three dimensional surface of said freeform optic that, when light passes through said freeform optic, said freeform optic projects the at least one of (i) an icon, (ii) a logo and (iii) indicia at the ground region at or near the side of the equipped vehicle. 20. The illumination module of claim 19, wherein said three dimensional single formed optic comprises a lens optic configured such that light emitted by said at least one illumination source, when activated, passes through said lens optic to provide a ground illumination pattern over an illuminated ground region at or near the side of the equipped vehicle, and wherein the ground illumination is a particular illumination pattern established by the formed surfaces of said three dimensional single formed optic, and wherein the particular illumination pattern comprises a higher intensity illumination region at the ground area and a lesser intensity illumination region at the illuminated ground region at or near the side of the equipped vehicle. | 2,800 |
11,968 | 11,968 | 13,812,853 | 2,837 | The present invention relates to an electromechanical transducer comprising a dielectric elastomer with contact by a first electrode and a second electrode, wherein the dielectric elastomer comprises a polyurethane polymer. In this case, the polyurethane polymer comprises at least one polyester and/or polycarbonate unit. The invention also relates to a process for producing such an electromechanical transducer, to the use of the dielectric elastomer used and also to an electrical and/or electronic apparatus comprising an electromechanical transducer according to the invention. | 1. An electromechanical converter, including a dielectric elastomer which is in contact with a first electrode and a second electrode, in which the dielectric elastomer comprises a polyurethane polymer, wherein the polyurethane polymer can be obtained by reacting
A) trifunctional polyisocyanate having a biuret and/or isocyanurate structure with B) a compound having at least two isocyanate-reactive groups, in which the compound having at least two isocyanate-reactive groups B) includes polyester and/or polycarbonate units, and in which the molar ratios of isocyanate groups in A) to isocyanate-reactive groups in B) are from 0.8:1.0 to 1.3:1.0. 2. An electromechanical converter according to claim 1, in which component A) is based on an aliphatic trifunctional polyisocyanate having a biuret and/or isocyanurate structure. 3. An electromechanical converter according to claim 1 in which component A) is based on hexamethylene diisocyanate. 4. An electromechanical converter according to claims 1, wherein component B) is a polyester polyol and/or polycarbonate polyol. 5. An electromechanical converter according to claim 1, in which the proportion of polyester and/or polycarbonate units in the polyurethane polymer is from ≧20 wt. % to ≦90 wt. %. 6. An electromechanical converter according to claim 1, in which the polyurethane polymer has a modulus of elasticity at an extension of from 50% of ≧0.1 MPa to ≦15 MPa. 7. A method for producing an electromechanical converter comprising:
1) preparation of a first electrode and a second electrode; 2) preparation of a dielectric elastomer, in which the dielectric elastomer includes a polyurethane polymer, and the polyurethane polymer may be obtained by reacting
A) trifunctional polyisocyanate having a biuret and/or isocyanurate structure with
B) a compound having at least two isocyanate-reactive groups,
in which the compound having at least two isocyanate-reactive groups B) includes polyester and/or polycarbonate units, and
in which the molar ratios of isocyanate groups in A) to isocyanate-reactive groups in B) are from 0.8:1.0 to 1.3:1.0;
3) disposition of the dielectric elastomer between the first electrode and the second electrode. 8. A method according to claim 7, in which the dielectric elastomer is prepared by applying a reaction mixture that gives the polyurethane polymer to the first and/or second electrode. 9. An actuator, sensor and/or generator comprising a dielectric elastomer in an electromechanical converter, in which the dielectric elastomer includes a polyurethane polymer and the polyurethane polymer may be obtained by reacting
A) trifunctional polyisocyanate having a biuret and/or isocyanurate structure with B) a compound having at least two isocyanate-reactive groups, in which the compound having at least two isocyanate-reactive groups B) includes polyester and/or polycarbonate units, and in which the molar ratios of isocyanate groups in A) to isocyanate-reactive groups in B) are from 0.8:1.0 to 1.3:1.0. 10. An electrical and/or electronic device, including an electromechanical converter according to claim 1. | The present invention relates to an electromechanical transducer comprising a dielectric elastomer with contact by a first electrode and a second electrode, wherein the dielectric elastomer comprises a polyurethane polymer. In this case, the polyurethane polymer comprises at least one polyester and/or polycarbonate unit. The invention also relates to a process for producing such an electromechanical transducer, to the use of the dielectric elastomer used and also to an electrical and/or electronic apparatus comprising an electromechanical transducer according to the invention.1. An electromechanical converter, including a dielectric elastomer which is in contact with a first electrode and a second electrode, in which the dielectric elastomer comprises a polyurethane polymer, wherein the polyurethane polymer can be obtained by reacting
A) trifunctional polyisocyanate having a biuret and/or isocyanurate structure with B) a compound having at least two isocyanate-reactive groups, in which the compound having at least two isocyanate-reactive groups B) includes polyester and/or polycarbonate units, and in which the molar ratios of isocyanate groups in A) to isocyanate-reactive groups in B) are from 0.8:1.0 to 1.3:1.0. 2. An electromechanical converter according to claim 1, in which component A) is based on an aliphatic trifunctional polyisocyanate having a biuret and/or isocyanurate structure. 3. An electromechanical converter according to claim 1 in which component A) is based on hexamethylene diisocyanate. 4. An electromechanical converter according to claims 1, wherein component B) is a polyester polyol and/or polycarbonate polyol. 5. An electromechanical converter according to claim 1, in which the proportion of polyester and/or polycarbonate units in the polyurethane polymer is from ≧20 wt. % to ≦90 wt. %. 6. An electromechanical converter according to claim 1, in which the polyurethane polymer has a modulus of elasticity at an extension of from 50% of ≧0.1 MPa to ≦15 MPa. 7. A method for producing an electromechanical converter comprising:
1) preparation of a first electrode and a second electrode; 2) preparation of a dielectric elastomer, in which the dielectric elastomer includes a polyurethane polymer, and the polyurethane polymer may be obtained by reacting
A) trifunctional polyisocyanate having a biuret and/or isocyanurate structure with
B) a compound having at least two isocyanate-reactive groups,
in which the compound having at least two isocyanate-reactive groups B) includes polyester and/or polycarbonate units, and
in which the molar ratios of isocyanate groups in A) to isocyanate-reactive groups in B) are from 0.8:1.0 to 1.3:1.0;
3) disposition of the dielectric elastomer between the first electrode and the second electrode. 8. A method according to claim 7, in which the dielectric elastomer is prepared by applying a reaction mixture that gives the polyurethane polymer to the first and/or second electrode. 9. An actuator, sensor and/or generator comprising a dielectric elastomer in an electromechanical converter, in which the dielectric elastomer includes a polyurethane polymer and the polyurethane polymer may be obtained by reacting
A) trifunctional polyisocyanate having a biuret and/or isocyanurate structure with B) a compound having at least two isocyanate-reactive groups, in which the compound having at least two isocyanate-reactive groups B) includes polyester and/or polycarbonate units, and in which the molar ratios of isocyanate groups in A) to isocyanate-reactive groups in B) are from 0.8:1.0 to 1.3:1.0. 10. An electrical and/or electronic device, including an electromechanical converter according to claim 1. | 2,800 |
11,969 | 11,969 | 15,652,590 | 2,875 | A lens diffusing light emitted from a light source includes a concave light-incident surface, a light guide portion, and a light-emitting surface. The light-incident surface includes a plane portion opposed to the light source and an optical function portion that is formed on the plane portion and one of scatters and diffuses the light. The light emitted from the light source enters the light-incident surface. The light that has entered the light-incident surface passes through the light guide portion. The light-emitting surface emits the light passed through the light guide portion. | 1. (canceled) 2. A lens configured to diffuse light emitted from a light source, the lens comprising:
a concave light-incident surface including a plane portion opposed to the light source and an optical function portion that is formed on the plane portion and scatters the light, wherein at least a portion of the light emitted from the light source enters the light-incident surface; a light guide portion through which the light that has entered the light-incident surface passes; a light-emitting surface configured to emit the light that passes through the light guide portion, and a bottom surface including a print processing portion, a roughening processing portion, or a reflective film portion, wherein the light source comprises a plurality of light-emitting elements that are arranged in a predetermined direction, the lens is elongated in the predetermined direction, and the print processing portion, the roughening processing portion, or the reflective film portion of the bottom surface contacts a side surface of a substrate of the light source along the predetermined direction, the side surface being parallel to a shortest line between the plane portion and the light source. 3. The lens according to claim 2, wherein the optical function portion is a part that has been subjected to print processing. 4. The lens according to claim 3, wherein the light-emitting surface includes a part opposed to the plane portion that has been subjected to the print processing. 5. The lens according to claim 2, wherein the optical function portion is a part that has been subjected to roughening processing. 6. The lens according to claim 5, wherein the light-emitting surface includes a part opposed to the plane portion that has been subjected to the roughening processing. 7. The lens according to claim 2, wherein the light-emitting surface includes a part opposed to the plane portion that has been subjected to roughening processing. 8. The lens according to claim 2, wherein the light guide portion comprises a diffusing material for diffusing the light. 9. The lens according to claim 2, further comprising a heat flow path that is forming from the light-incident surface to the light-emitting surface and discharges heat radiated from the light source. 10. The lens according to claim 2, wherein the plurality of light-emitting elements emit light by an EL (Electro Luminescence) phenomenon. 11. The lens according to claim 10, wherein the lens has light distribution characteristics that are substantially the same in a direction orthogonal to the predetermined direction within a plane on which the plurality of light-emitting elements are arranged. 12. A light source unit, comprising:
a light source; and a lens configured to diffuse light emitted from the light source, the lens comprising:
a concave light-incident surface including a plane portion opposed to the light source and an optical function portion that is formed on the plane portion and scatters the light, wherein at least a portion of the light emitted from the light source enters the light-incident surface,
a light guide portion through which the light that has entered the light-incident surface passes,
a light-emitting surface configured to emit the light that passes through the light guide portion, and
a bottom surface including a print processing portion, a roughening processing portion, or a reflective film portion, wherein
the light source comprises a plurality of light-emitting elements that are arranged in a predetermined direction, the lens is elongated in the predetermined direction, and the print processing portion, the roughening processing portion, or the reflective film portion of the bottom surface contacts a side surface of a substrate of the light source along the predetermined direction, the side surface being parallel to a shortest line between the plane portion and the light source. 13. The light source unit according to claim 12, further comprising:
an optical member that is mounted on the light source and scatters the light. 14. The light source unit according to claim 13, wherein the light emitting elements emit light by an EL (Electro Luminescence) phenomenon, and wherein the optical member includes a sealing member to seal up the light-emitting elements. 15. The light source unit according to claim 14, wherein the optical member contains a diffusing material. 16. The light source unit according to claim 14,
wherein the plurality of light-emitting elements being arranged on the substrate of the light source, and wherein the sealing member seals each of the plurality of light-emitting elements. 17. A backlight apparatus, comprising:
a light source unit comprising a light source; a lens to diffuse light emitted from the light source, the lens comprising:
a concave light-incident surface including a plane portion opposed to the light source and an optical function portion that is formed on the plane portion and scatters the light, wherein at least a portion of the light emitted from the light source enters the light-incident surface,
a light guide portion through which the light that has entered the light-incident surface passes,
a light-emitting surface configured to emit the light that passes through the light guide portion, and
a bottom surface including a print processing portion, a roughening processing portion, or a reflective film portion; and
a supporting member to support the light source unit, wherein
the light source comprises a plurality of light-emitting elements that are arranged in a predetermined direction, the lens is elongated in the predetermined direction, and the print processing portion, the roughening processing portion, or the reflective film portion of the bottom surface contacts a side surface of a substrate of the light source along the predetermined direction, the side surface being parallel to a shortest line between the plane portion and the light source. 18. A display apparatus, comprising:
a light source unit including a light source; a lens to diffuse light emitted from the light source, the lens comprising:
a concave light-incident surface including a plane portion opposed to the light source and an optical function portion that is formed on the plane portion and scatters the light, wherein at least a portion of the light emitted from the light source enters the light-incident surface,
a light guide portion through which the light that has entered the light-incident surface passes,
a light-emitting surface configured to emit the light that passes through the light guide portion, and
a bottom surface including a print processing portion, a roughening processing portion, or a reflective film portion;
a supporting member to support the light source unit; and a light transmission control panel that includes a plurality of pixels and controls transmission of the light emitted from the lens for each of the plurality of pixels, wherein the light source comprises a plurality of light-emitting elements that are arranged in a predetermined direction, the lens is elongated in the predetermined direction, and the print processing portion, the roughening processing portion, or the reflective film portion of the bottom surface contacts a side surface of a substrate of the light source along the predetermined direction, the side surface being parallel to a shortest line between the plane portion and the light source. 19. The light source unit according to claim 14, wherein the shape of the sealing member is a hemisphere. 20. The light source unit according to claim 14, wherein at least a portion of the light emitted from the light source enters the sealing member, and
wherein the sealing member is configured to scatter the entered portion of the light into the light-incident surface. 21. A display comprising:
a light source; and lenses configured to diffuse light emitted from the light source, each lens comprising:
a concave light-incident surface, wherein at least a portion of the light emitted from the light source enters the light-incident surface;
a light guide portion through which the light that has entered the light-incident surface passes;
a light-emitting surface configured to emit the light that passes through the light guide portion;
a bottom surface; and
a roughening processing portion on the bottom surface, a portion of the concave light light-incident surface or a portion of the light-emitting surface. 22. The display of claim 21, wherein the light source comprises a plurality of light-emitting elements that are arranged in a predetermined direction. 23. The display of claim 22, wherein the bottom surface comprises the roughening processing portion or a reflective film portion and the bottom surface contacts a side surface of a substrate of the light source along the predetermined direction. 24. The display of claim 21, wherein the light source comprises a series of light emitting diode blocks, each light emitting diode block contains and supports a light emitting diode. 25. The display of claim 24, wherein each light emitting diode block comprises a concave portion therein, each concave portion supports one of the light emitting diodes. 26. The display of claim 25, wherein the concave portions are reflectors. 27. The display of claim 26, wherein each concave portion comprises an optical member therein that diffuses light from the light emitting diodes. 28. The display of claim 25, wherein each concave portion comprises an optical member therein that diffuses light from the light emitting diodes. 29. The display of claim 27, wherein the optical members seal the light emitting diodes. 30. The display of claim 28, wherein the optical members seal the light emitting diodes. 31. The display of claim 27, wherein each lens fits over or is supported by one of the light emitting diode blocks. 32. The display of claim 28, wherein each lens fits over or is supported by one of the light emitting diode blocks. 33. The display of claim 22, wherein the concave light-incident surface a plane portion opposed to the light source and an optical function portion that is formed on the plane portion and scatters the light. | A lens diffusing light emitted from a light source includes a concave light-incident surface, a light guide portion, and a light-emitting surface. The light-incident surface includes a plane portion opposed to the light source and an optical function portion that is formed on the plane portion and one of scatters and diffuses the light. The light emitted from the light source enters the light-incident surface. The light that has entered the light-incident surface passes through the light guide portion. The light-emitting surface emits the light passed through the light guide portion.1. (canceled) 2. A lens configured to diffuse light emitted from a light source, the lens comprising:
a concave light-incident surface including a plane portion opposed to the light source and an optical function portion that is formed on the plane portion and scatters the light, wherein at least a portion of the light emitted from the light source enters the light-incident surface; a light guide portion through which the light that has entered the light-incident surface passes; a light-emitting surface configured to emit the light that passes through the light guide portion, and a bottom surface including a print processing portion, a roughening processing portion, or a reflective film portion, wherein the light source comprises a plurality of light-emitting elements that are arranged in a predetermined direction, the lens is elongated in the predetermined direction, and the print processing portion, the roughening processing portion, or the reflective film portion of the bottom surface contacts a side surface of a substrate of the light source along the predetermined direction, the side surface being parallel to a shortest line between the plane portion and the light source. 3. The lens according to claim 2, wherein the optical function portion is a part that has been subjected to print processing. 4. The lens according to claim 3, wherein the light-emitting surface includes a part opposed to the plane portion that has been subjected to the print processing. 5. The lens according to claim 2, wherein the optical function portion is a part that has been subjected to roughening processing. 6. The lens according to claim 5, wherein the light-emitting surface includes a part opposed to the plane portion that has been subjected to the roughening processing. 7. The lens according to claim 2, wherein the light-emitting surface includes a part opposed to the plane portion that has been subjected to roughening processing. 8. The lens according to claim 2, wherein the light guide portion comprises a diffusing material for diffusing the light. 9. The lens according to claim 2, further comprising a heat flow path that is forming from the light-incident surface to the light-emitting surface and discharges heat radiated from the light source. 10. The lens according to claim 2, wherein the plurality of light-emitting elements emit light by an EL (Electro Luminescence) phenomenon. 11. The lens according to claim 10, wherein the lens has light distribution characteristics that are substantially the same in a direction orthogonal to the predetermined direction within a plane on which the plurality of light-emitting elements are arranged. 12. A light source unit, comprising:
a light source; and a lens configured to diffuse light emitted from the light source, the lens comprising:
a concave light-incident surface including a plane portion opposed to the light source and an optical function portion that is formed on the plane portion and scatters the light, wherein at least a portion of the light emitted from the light source enters the light-incident surface,
a light guide portion through which the light that has entered the light-incident surface passes,
a light-emitting surface configured to emit the light that passes through the light guide portion, and
a bottom surface including a print processing portion, a roughening processing portion, or a reflective film portion, wherein
the light source comprises a plurality of light-emitting elements that are arranged in a predetermined direction, the lens is elongated in the predetermined direction, and the print processing portion, the roughening processing portion, or the reflective film portion of the bottom surface contacts a side surface of a substrate of the light source along the predetermined direction, the side surface being parallel to a shortest line between the plane portion and the light source. 13. The light source unit according to claim 12, further comprising:
an optical member that is mounted on the light source and scatters the light. 14. The light source unit according to claim 13, wherein the light emitting elements emit light by an EL (Electro Luminescence) phenomenon, and wherein the optical member includes a sealing member to seal up the light-emitting elements. 15. The light source unit according to claim 14, wherein the optical member contains a diffusing material. 16. The light source unit according to claim 14,
wherein the plurality of light-emitting elements being arranged on the substrate of the light source, and wherein the sealing member seals each of the plurality of light-emitting elements. 17. A backlight apparatus, comprising:
a light source unit comprising a light source; a lens to diffuse light emitted from the light source, the lens comprising:
a concave light-incident surface including a plane portion opposed to the light source and an optical function portion that is formed on the plane portion and scatters the light, wherein at least a portion of the light emitted from the light source enters the light-incident surface,
a light guide portion through which the light that has entered the light-incident surface passes,
a light-emitting surface configured to emit the light that passes through the light guide portion, and
a bottom surface including a print processing portion, a roughening processing portion, or a reflective film portion; and
a supporting member to support the light source unit, wherein
the light source comprises a plurality of light-emitting elements that are arranged in a predetermined direction, the lens is elongated in the predetermined direction, and the print processing portion, the roughening processing portion, or the reflective film portion of the bottom surface contacts a side surface of a substrate of the light source along the predetermined direction, the side surface being parallel to a shortest line between the plane portion and the light source. 18. A display apparatus, comprising:
a light source unit including a light source; a lens to diffuse light emitted from the light source, the lens comprising:
a concave light-incident surface including a plane portion opposed to the light source and an optical function portion that is formed on the plane portion and scatters the light, wherein at least a portion of the light emitted from the light source enters the light-incident surface,
a light guide portion through which the light that has entered the light-incident surface passes,
a light-emitting surface configured to emit the light that passes through the light guide portion, and
a bottom surface including a print processing portion, a roughening processing portion, or a reflective film portion;
a supporting member to support the light source unit; and a light transmission control panel that includes a plurality of pixels and controls transmission of the light emitted from the lens for each of the plurality of pixels, wherein the light source comprises a plurality of light-emitting elements that are arranged in a predetermined direction, the lens is elongated in the predetermined direction, and the print processing portion, the roughening processing portion, or the reflective film portion of the bottom surface contacts a side surface of a substrate of the light source along the predetermined direction, the side surface being parallel to a shortest line between the plane portion and the light source. 19. The light source unit according to claim 14, wherein the shape of the sealing member is a hemisphere. 20. The light source unit according to claim 14, wherein at least a portion of the light emitted from the light source enters the sealing member, and
wherein the sealing member is configured to scatter the entered portion of the light into the light-incident surface. 21. A display comprising:
a light source; and lenses configured to diffuse light emitted from the light source, each lens comprising:
a concave light-incident surface, wherein at least a portion of the light emitted from the light source enters the light-incident surface;
a light guide portion through which the light that has entered the light-incident surface passes;
a light-emitting surface configured to emit the light that passes through the light guide portion;
a bottom surface; and
a roughening processing portion on the bottom surface, a portion of the concave light light-incident surface or a portion of the light-emitting surface. 22. The display of claim 21, wherein the light source comprises a plurality of light-emitting elements that are arranged in a predetermined direction. 23. The display of claim 22, wherein the bottom surface comprises the roughening processing portion or a reflective film portion and the bottom surface contacts a side surface of a substrate of the light source along the predetermined direction. 24. The display of claim 21, wherein the light source comprises a series of light emitting diode blocks, each light emitting diode block contains and supports a light emitting diode. 25. The display of claim 24, wherein each light emitting diode block comprises a concave portion therein, each concave portion supports one of the light emitting diodes. 26. The display of claim 25, wherein the concave portions are reflectors. 27. The display of claim 26, wherein each concave portion comprises an optical member therein that diffuses light from the light emitting diodes. 28. The display of claim 25, wherein each concave portion comprises an optical member therein that diffuses light from the light emitting diodes. 29. The display of claim 27, wherein the optical members seal the light emitting diodes. 30. The display of claim 28, wherein the optical members seal the light emitting diodes. 31. The display of claim 27, wherein each lens fits over or is supported by one of the light emitting diode blocks. 32. The display of claim 28, wherein each lens fits over or is supported by one of the light emitting diode blocks. 33. The display of claim 22, wherein the concave light-incident surface a plane portion opposed to the light source and an optical function portion that is formed on the plane portion and scatters the light. | 2,800 |
11,970 | 11,970 | 15,668,509 | 2,831 | Example retainer apparatus and related methods are disclosed. An example retainer apparatus disclosed herein includes a post having a first end attachable to a wall plate cover opening of an outlet and a second end opposite the first end. The example retainer apparatus also includes a plug retainer to be removably coupled to the post. The plug retainer of the example retainer apparatus is to move relative to the post between the first end of the post and the second end of the post. | 1. A retainer comprising:
a post having a first end to be received by an opening of a wall plate cover of an outlet and a second end opposite the first end; and a plug retainer to be removably coupled to the post, the plug retainer to move relative to the post between the first end of the post and the second end of the post, the plug retainer including a plurality of flexible tabs protruding from a base of the plug retainer in a direction along a longitudinal length of the post, the flexible tabs to slide relative to the post when the plug retainer is moved relative to the post. 2. The retainer of claim 1, wherein the first end of the post includes a fastener. 3. The retainer of claim 2, wherein the fastener protrudes from the second end of the post. 4. The retainer of claim 2, wherein the fastener is a threaded fastener and the opening of the wall plate cover is a threaded opening. 5. The retainer of claim 1, wherein the post includes a plurality of grooves positioned along at least a portion of the post between the second end of the post and an intermediate portion of the post, the intermediate portion being between the first end of the post and the second end of the post. 6. The retainer of claim 1, wherein the plug retainer includes a first arm and a second arm protruding from the base, the first arm and the second arm defining a gap therebetween. 7. The retainer of claim 6, wherein the plurality of flexible tabs and an aperture of the base define a post-receiving opening to receive the post. 8. A retainer comprising:
a post having a first end to couple to an opening of a wall plate cover of an outlet and a second end opposite the first end; and a plug retainer to be removably coupled to the post, the plug retainer to move relative to the post between the first end of the post and the second end of the post, the plug retainer including a first arm and a second arm protruding from a base, the first arm and the second arm defining a gap therebetween, the plug retainer including a grip protruding from at least one of the first arm or the second arm in a direction non-parallel relative to a longitudinal axis of the at least one of the first arm or the second arm, the grip to facilitate removal of the plug retainer from the post. 9. A retainer comprising:
a post having a first end to be received by an opening of a wall plate cover of an outlet and a second end opposite the first end; and a plug retainer to be removably coupled to the post, the plug retainer to move relative to the post between the first end of the post and the second end of the post, the plug retainer including a first arm and a second arm protruding from a base, the first arm and the second arm defining a gap therebetween, the plug retainer including a boss protruding from at least one of the first arm or the second arm in a direction non-parallel relative to a longitudinal axis of the at least one of the first arm or the second arm, the boss to receive a wall plate cover screw. 10. A retainer comprising:
a post having a first portion to couple to an opening of a wall plate cover of an outlet and a second portion defining a retainer-receiving portion; a plug retainer to be removably coupled to the post, the plug retainer to slide in a first direction relative to the retainer-receiving portion of the post to engage a power plug of an electrical device coupled to the outlet, the plug retainer to slide in a second direction opposite the first direction relative to the retainer-receiving portion of the post to at least one of disengage the plug retainer from the power plug or remove the plug retainer from the retainer-receiving portion of the post; and a lock to removably couple the plug retainer to the post, the lock being movable in a direction radially outwardly relative to a longitudinal axis of the post to enable the lock to slide relative to the post in at least one of the first direction or the second direction in response to the plug retainer being moved relative to the post. 11. The retainer of claim 10, wherein the retainer-receiving portion includes a plurality of grooves spaced along a longitudinal length of the post defining the retainer-receiving portion of the post. 12. The retainer of claim 11, wherein the lock is integrally formed with the plug retainer, the lock including flexible tabs that are to engage one of the grooves to maintain a position of the plug retainer relative to the post. 13. A retainer comprising:
a post having a first portion to be received by an opening of a wall plate cover of an outlet and a second portion defining a retainer-receiving portion, the retainer-receiving portion including a plurality of grooves spaced along a longitudinal length of the post defining the retainer-receiving portion of the post; and a plug retainer to be removably coupled to the post, the plug retainer to slide in a first direction relative to the retainer-receiving portion of the post to engage a power plug of an electrical device coupled to the outlet, the plug retainer to slide in a second direction opposite the first direction relative to the retainer-receiving portion of the post to at least one of disengage the plug retainer from the power plug or remove the plug retainer from the retainer-receiving portion of the post, the plug retainer including flexible tabs to engage one of the grooves to maintain a position of the plug retainer relative to the post, and respective ones of the flexible tabs including a protrusion to engage the grooves. 14. A retainer comprising:
a post having a first portion to be received by an opening of a wall plate cover of an outlet and a second portion defining a retainer-receiving portion, the retainer-receiving portion including a plurality of grooves spaced along a longitudinal length of the post defining the retainer-receiving portion of the post; and a plug retainer to be removably coupled to the post, the plug retainer to slide in a first direction relative to the retainer-receiving portion of the post to engage a power plug of an electrical device coupled to the outlet, the plug retainer to slide in a second direction opposite the first direction relative to the retainer-receiving portion of the post to at least one of disengage the plug retainer from the power plug or remove the plug retainer from the retainer-receiving portion of the post, the plug retainer including flexible tabs that are to engage one of the grooves to maintain a position of the plug retainer relative to the post, and the flexible tabs to protrude from a base of the plug retainer, the flexible tabs having longitudinal axes that are canted relative to a longitudinal axis of the post. 15. The retainer of claim 10, wherein the plug retainer includes a first arm and a second arm protruding from a base of the plug retainer, the first arm being spaced from the second arm to define a gap therebetween, at least one of the first arm or the second arm to engage the power plug to retain the power plug coupled to the outlet. 16. A method comprising:
coupling a post of a retainer to an opening of a wall plate cover of an outlet; aligning a post-receiving opening of a plug retainer of the retainer relative to the post after the post is coupled to the outlet; moving the plug retainer in a first direction along the post relative to a longitudinal axis of the post, the plug retainer including a lock to slide relative to the longitudinal axis of the post when the plug retainer moves in the first direction; and positioning the plug retainer adjacent an electrical plug coupled to the outlet to inhibit removal of the plug from the outlet, the positioning of the plug retainer adjacent the electrical plug causing the lock of the plug retainer to engage the post. 17. The method of claim 16, further including removing a plate cover screw from the opening of the wall plate cover prior to attaching the post to the opening of the wall plate cover. 18. The method of claim 16, further including moving the plug retainer in a second direction along the post relative to the longitudinal axis of the post to enable removal of the electric plug from the outlet. 19. The method of claim 18, wherein the moving of the plug retainer in the first direction or the second direction along the post is performed without use of a tool. 20. The method of claim 18, wherein the moving of the plug retainer in the second direction includes disengaging the plug retainer from the post, wherein the disengaging of the plug retainer from the post is caused by a pulling force in the second direction without use of a tool. 21. The retainer of claim 1, wherein the flexible tabs protrude from the base in a direction parallel to the longitudinal length of the post. 22. The retainer of claim 13, wherein the flexible tabs are to slide relative to the post in response to the plug retainer being moved relative to the post. 23. The retainer of claim 14, wherein the flexible tabs are to slide relative to the post when the plug retainer is moved relative to the post. | Example retainer apparatus and related methods are disclosed. An example retainer apparatus disclosed herein includes a post having a first end attachable to a wall plate cover opening of an outlet and a second end opposite the first end. The example retainer apparatus also includes a plug retainer to be removably coupled to the post. The plug retainer of the example retainer apparatus is to move relative to the post between the first end of the post and the second end of the post.1. A retainer comprising:
a post having a first end to be received by an opening of a wall plate cover of an outlet and a second end opposite the first end; and a plug retainer to be removably coupled to the post, the plug retainer to move relative to the post between the first end of the post and the second end of the post, the plug retainer including a plurality of flexible tabs protruding from a base of the plug retainer in a direction along a longitudinal length of the post, the flexible tabs to slide relative to the post when the plug retainer is moved relative to the post. 2. The retainer of claim 1, wherein the first end of the post includes a fastener. 3. The retainer of claim 2, wherein the fastener protrudes from the second end of the post. 4. The retainer of claim 2, wherein the fastener is a threaded fastener and the opening of the wall plate cover is a threaded opening. 5. The retainer of claim 1, wherein the post includes a plurality of grooves positioned along at least a portion of the post between the second end of the post and an intermediate portion of the post, the intermediate portion being between the first end of the post and the second end of the post. 6. The retainer of claim 1, wherein the plug retainer includes a first arm and a second arm protruding from the base, the first arm and the second arm defining a gap therebetween. 7. The retainer of claim 6, wherein the plurality of flexible tabs and an aperture of the base define a post-receiving opening to receive the post. 8. A retainer comprising:
a post having a first end to couple to an opening of a wall plate cover of an outlet and a second end opposite the first end; and a plug retainer to be removably coupled to the post, the plug retainer to move relative to the post between the first end of the post and the second end of the post, the plug retainer including a first arm and a second arm protruding from a base, the first arm and the second arm defining a gap therebetween, the plug retainer including a grip protruding from at least one of the first arm or the second arm in a direction non-parallel relative to a longitudinal axis of the at least one of the first arm or the second arm, the grip to facilitate removal of the plug retainer from the post. 9. A retainer comprising:
a post having a first end to be received by an opening of a wall plate cover of an outlet and a second end opposite the first end; and a plug retainer to be removably coupled to the post, the plug retainer to move relative to the post between the first end of the post and the second end of the post, the plug retainer including a first arm and a second arm protruding from a base, the first arm and the second arm defining a gap therebetween, the plug retainer including a boss protruding from at least one of the first arm or the second arm in a direction non-parallel relative to a longitudinal axis of the at least one of the first arm or the second arm, the boss to receive a wall plate cover screw. 10. A retainer comprising:
a post having a first portion to couple to an opening of a wall plate cover of an outlet and a second portion defining a retainer-receiving portion; a plug retainer to be removably coupled to the post, the plug retainer to slide in a first direction relative to the retainer-receiving portion of the post to engage a power plug of an electrical device coupled to the outlet, the plug retainer to slide in a second direction opposite the first direction relative to the retainer-receiving portion of the post to at least one of disengage the plug retainer from the power plug or remove the plug retainer from the retainer-receiving portion of the post; and a lock to removably couple the plug retainer to the post, the lock being movable in a direction radially outwardly relative to a longitudinal axis of the post to enable the lock to slide relative to the post in at least one of the first direction or the second direction in response to the plug retainer being moved relative to the post. 11. The retainer of claim 10, wherein the retainer-receiving portion includes a plurality of grooves spaced along a longitudinal length of the post defining the retainer-receiving portion of the post. 12. The retainer of claim 11, wherein the lock is integrally formed with the plug retainer, the lock including flexible tabs that are to engage one of the grooves to maintain a position of the plug retainer relative to the post. 13. A retainer comprising:
a post having a first portion to be received by an opening of a wall plate cover of an outlet and a second portion defining a retainer-receiving portion, the retainer-receiving portion including a plurality of grooves spaced along a longitudinal length of the post defining the retainer-receiving portion of the post; and a plug retainer to be removably coupled to the post, the plug retainer to slide in a first direction relative to the retainer-receiving portion of the post to engage a power plug of an electrical device coupled to the outlet, the plug retainer to slide in a second direction opposite the first direction relative to the retainer-receiving portion of the post to at least one of disengage the plug retainer from the power plug or remove the plug retainer from the retainer-receiving portion of the post, the plug retainer including flexible tabs to engage one of the grooves to maintain a position of the plug retainer relative to the post, and respective ones of the flexible tabs including a protrusion to engage the grooves. 14. A retainer comprising:
a post having a first portion to be received by an opening of a wall plate cover of an outlet and a second portion defining a retainer-receiving portion, the retainer-receiving portion including a plurality of grooves spaced along a longitudinal length of the post defining the retainer-receiving portion of the post; and a plug retainer to be removably coupled to the post, the plug retainer to slide in a first direction relative to the retainer-receiving portion of the post to engage a power plug of an electrical device coupled to the outlet, the plug retainer to slide in a second direction opposite the first direction relative to the retainer-receiving portion of the post to at least one of disengage the plug retainer from the power plug or remove the plug retainer from the retainer-receiving portion of the post, the plug retainer including flexible tabs that are to engage one of the grooves to maintain a position of the plug retainer relative to the post, and the flexible tabs to protrude from a base of the plug retainer, the flexible tabs having longitudinal axes that are canted relative to a longitudinal axis of the post. 15. The retainer of claim 10, wherein the plug retainer includes a first arm and a second arm protruding from a base of the plug retainer, the first arm being spaced from the second arm to define a gap therebetween, at least one of the first arm or the second arm to engage the power plug to retain the power plug coupled to the outlet. 16. A method comprising:
coupling a post of a retainer to an opening of a wall plate cover of an outlet; aligning a post-receiving opening of a plug retainer of the retainer relative to the post after the post is coupled to the outlet; moving the plug retainer in a first direction along the post relative to a longitudinal axis of the post, the plug retainer including a lock to slide relative to the longitudinal axis of the post when the plug retainer moves in the first direction; and positioning the plug retainer adjacent an electrical plug coupled to the outlet to inhibit removal of the plug from the outlet, the positioning of the plug retainer adjacent the electrical plug causing the lock of the plug retainer to engage the post. 17. The method of claim 16, further including removing a plate cover screw from the opening of the wall plate cover prior to attaching the post to the opening of the wall plate cover. 18. The method of claim 16, further including moving the plug retainer in a second direction along the post relative to the longitudinal axis of the post to enable removal of the electric plug from the outlet. 19. The method of claim 18, wherein the moving of the plug retainer in the first direction or the second direction along the post is performed without use of a tool. 20. The method of claim 18, wherein the moving of the plug retainer in the second direction includes disengaging the plug retainer from the post, wherein the disengaging of the plug retainer from the post is caused by a pulling force in the second direction without use of a tool. 21. The retainer of claim 1, wherein the flexible tabs protrude from the base in a direction parallel to the longitudinal length of the post. 22. The retainer of claim 13, wherein the flexible tabs are to slide relative to the post in response to the plug retainer being moved relative to the post. 23. The retainer of claim 14, wherein the flexible tabs are to slide relative to the post when the plug retainer is moved relative to the post. | 2,800 |
11,971 | 11,971 | 14,825,917 | 2,875 | An aircraft beacon light unit has an operating light emission distribution. The operating light emission distribution has a first light emission opening angle of at least 150° in a first cross-sectional plane, and a second light emission opening angle of at most 180° in a second cross-sectional plane orthogonal to the first cross-sectional plane. The aircraft beacon light unit is configured in such a way that it is mountable to an aircraft with the first cross-sectional plane being oriented in a vertical direction and the second cross-sectional plane being oriented in a horizontal direction, and the first light emission opening angle extends at least 75° both above and below the second cross-sectional plane. | 1. Aircraft beacon light unit with an operating light emission distribution, wherein the operating light emission distribution has
a first light emission opening angle of at least 150° in a first cross-sectional plane, and a second light emission opening angle of at most 180° in a second cross-sectional plane orthogonal to the first cross-sectional plane, wherein the aircraft beacon light unit is configured in such a way that it is mountable to an aircraft with the first cross-sectional plane being oriented in a vertical direction and the second cross-sectional plane being oriented in a horizontal direction, and wherein the first light emission opening angle extends at least 75° both above and below the second cross-sectional plane. 2. Aircraft beacon light unit according to claim 1, wherein the operating light emission distribution is symmetric with respect to the second cross-sectional plane. 3. Aircraft beacon light unit according to claim 1, wherein the operating light emission distribution in the first cross-sectional plane satisfies a set of minimum requirements of a predefined vertical light emission distribution of an aircraft beacon light unit. 4. Aircraft beacon light unit according to claim 3, wherein the set of minimum requirements is defined by Federal Aviation Regulation §25.1401. 5. Aircraft beacon light unit according to claim 1, wherein the light intensity values of the operating light emission distribution are at least equal to the following values in the first cross-sectional plane:
400 cd for a first angular range of between 0° and ±5° with respect to the second cross-sectional plane, 240 cd for a second angular range of between ±5° and ±10° with respect to the second cross-sectional plane, 80 cd for a third angular range of between ±10° and ±20° with respect to the second cross-sectional plane, 40 cd for a fourth angular range of between ±20° and ±30° with respect to the second cross-sectional plane, and 20 cd for a fifth angular range of between ±30° and ±75° with respect to the second cross-sectional plane. 6. Aircraft beacon light unit according to claim 1, wherein the light intensity values of the operating light emission distribution are effective light intensity values, calculated via the Blondel Ray formula. 7. Aircraft beacon light unit according to claim 1, wherein the first light emission opening angle is at most 180°. 8. Aircraft beacon light unit according to claim 1, wherein the second light emission opening angle is between 60° and 180°, in particular between 90° and 150°. 9. Aircraft beacon light unit according to claim 1, wherein the operating light emission distribution satisfies a set of minimum requirements of a predefined vertical light emission distribution of an aircraft beacon light unit in all cross-sectional planes that are orthogonal to the second cross-sectional plane and that are within the second light emission opening angle. 10. Aircraft beacon light unit according to claim 1, wherein the aircraft beacon light unit is one of:
a combined aircraft beacon light and navigation light unit, a combined aircraft beacon light and anti-collision light unit, and a combined aircraft beacon light, navigation light and anti-collision light unit. 11. Set of aircraft beacon light units, wherein each of the set of aircraft beacon light units is embodied in accordance with claim 1 and wherein the second light emission angles of the set of aircraft beacon light units add up to at least 360°, such that a 360° illumination in the horizontal plane of an aircraft is possible via the set of aircraft beacon light units. 12. Set according to claim 11, wherein the set of aircraft beacon light units comprises:
a right wing tip aircraft beacon light unit and a left wing tip aircraft beacon light unit, with the second light emission angle of each of the right wing tip aircraft beacon light unit and the left wing tip aircraft beacon light unit being between 90° and 140°. 13. Set according to claim 11, wherein the set of aircraft beacon light units comprises one of:
exactly one tail aircraft beacon light unit, with the second light emission angle of the tail aircraft beacon light unit being between 100° and 180°, and exactly two tail aircraft beacon light units, with the second light emission angle of each of the exactly two tail aircraft beacon light units being between 50° and 90°. 14. Aircraft, having at least one aircraft beacon light unit in accordance with claim 1. 15. (canceled) | An aircraft beacon light unit has an operating light emission distribution. The operating light emission distribution has a first light emission opening angle of at least 150° in a first cross-sectional plane, and a second light emission opening angle of at most 180° in a second cross-sectional plane orthogonal to the first cross-sectional plane. The aircraft beacon light unit is configured in such a way that it is mountable to an aircraft with the first cross-sectional plane being oriented in a vertical direction and the second cross-sectional plane being oriented in a horizontal direction, and the first light emission opening angle extends at least 75° both above and below the second cross-sectional plane.1. Aircraft beacon light unit with an operating light emission distribution, wherein the operating light emission distribution has
a first light emission opening angle of at least 150° in a first cross-sectional plane, and a second light emission opening angle of at most 180° in a second cross-sectional plane orthogonal to the first cross-sectional plane, wherein the aircraft beacon light unit is configured in such a way that it is mountable to an aircraft with the first cross-sectional plane being oriented in a vertical direction and the second cross-sectional plane being oriented in a horizontal direction, and wherein the first light emission opening angle extends at least 75° both above and below the second cross-sectional plane. 2. Aircraft beacon light unit according to claim 1, wherein the operating light emission distribution is symmetric with respect to the second cross-sectional plane. 3. Aircraft beacon light unit according to claim 1, wherein the operating light emission distribution in the first cross-sectional plane satisfies a set of minimum requirements of a predefined vertical light emission distribution of an aircraft beacon light unit. 4. Aircraft beacon light unit according to claim 3, wherein the set of minimum requirements is defined by Federal Aviation Regulation §25.1401. 5. Aircraft beacon light unit according to claim 1, wherein the light intensity values of the operating light emission distribution are at least equal to the following values in the first cross-sectional plane:
400 cd for a first angular range of between 0° and ±5° with respect to the second cross-sectional plane, 240 cd for a second angular range of between ±5° and ±10° with respect to the second cross-sectional plane, 80 cd for a third angular range of between ±10° and ±20° with respect to the second cross-sectional plane, 40 cd for a fourth angular range of between ±20° and ±30° with respect to the second cross-sectional plane, and 20 cd for a fifth angular range of between ±30° and ±75° with respect to the second cross-sectional plane. 6. Aircraft beacon light unit according to claim 1, wherein the light intensity values of the operating light emission distribution are effective light intensity values, calculated via the Blondel Ray formula. 7. Aircraft beacon light unit according to claim 1, wherein the first light emission opening angle is at most 180°. 8. Aircraft beacon light unit according to claim 1, wherein the second light emission opening angle is between 60° and 180°, in particular between 90° and 150°. 9. Aircraft beacon light unit according to claim 1, wherein the operating light emission distribution satisfies a set of minimum requirements of a predefined vertical light emission distribution of an aircraft beacon light unit in all cross-sectional planes that are orthogonal to the second cross-sectional plane and that are within the second light emission opening angle. 10. Aircraft beacon light unit according to claim 1, wherein the aircraft beacon light unit is one of:
a combined aircraft beacon light and navigation light unit, a combined aircraft beacon light and anti-collision light unit, and a combined aircraft beacon light, navigation light and anti-collision light unit. 11. Set of aircraft beacon light units, wherein each of the set of aircraft beacon light units is embodied in accordance with claim 1 and wherein the second light emission angles of the set of aircraft beacon light units add up to at least 360°, such that a 360° illumination in the horizontal plane of an aircraft is possible via the set of aircraft beacon light units. 12. Set according to claim 11, wherein the set of aircraft beacon light units comprises:
a right wing tip aircraft beacon light unit and a left wing tip aircraft beacon light unit, with the second light emission angle of each of the right wing tip aircraft beacon light unit and the left wing tip aircraft beacon light unit being between 90° and 140°. 13. Set according to claim 11, wherein the set of aircraft beacon light units comprises one of:
exactly one tail aircraft beacon light unit, with the second light emission angle of the tail aircraft beacon light unit being between 100° and 180°, and exactly two tail aircraft beacon light units, with the second light emission angle of each of the exactly two tail aircraft beacon light units being between 50° and 90°. 14. Aircraft, having at least one aircraft beacon light unit in accordance with claim 1. 15. (canceled) | 2,800 |
11,972 | 11,972 | 15,702,717 | 2,855 | Spatially-distributed resonant MEMS sensors are coordinated to generate frequency-modulated signals indicative of regional contact forces, ambient conditions and/or environmental composition. | 1. A sensing apparatus comprising:
a first surface; a plurality of resonant MEMS devices each disposed in physical contact with a respective region of the first surface and having a mechanical resonance frequency that varies according to deflection of the first surface in the respective region of physical contact; and readout circuitry to obtain, within a first time interval, information indicative of the respective mechanical resonance frequencies of the plurality of resonant MEMS devices sufficient to identify a locus and amplitude of a force applied to the first surface. 2. The sensing apparatus of claim 1 wherein each of the plurality of resonant MEMS devices comprises a resonant MEMS structure and circuitry to (i) apply an actuating signal to the resonant MEMS structure to sustain at least temporary resonant vibration thereof and (ii) circuitry to sense, as the mechanical resonance frequency of the resonant MEMS device, a frequency of the resonant vibration. 3. The sensing apparatus of claim 2 wherein the circuitry to apply the actuating signal to the resonant MEMS structure comprises at least one of (i) circuitry to generate the actuating signal or (ii) circuitry to receive the actuating signal from an external source. 4. The sensing apparatus of claim 1 wherein the first surface comprises a substantially planar surface that encompasses the respective regions of physical contact of at least a portion of the plurality of resonant MEMS devices, the substantially planar surface subject to localized deflection in response to the applied force. 5. The sensing apparatus of claim 1 further comprising circuitry to generate, based on the information indicative of the respective mechanical resonance frequencies, information indicative of the locus and amplitude of the force applied to the first surface. 6. The sensing apparatus of claim 1 wherein the information indicative of the mechanical resonance frequencies comprises a first set of resonance frequency values and wherein the readout circuitry to obtain the first set of resonance frequency values within the first time interval is additionally to obtain, over a sequence of time intervals that follow the first time interval, additional sets of resonance frequency values, the sensing apparatus further comprising circuitry to generate, based on the first set of resonance frequency values and the additional sets of resonance frequency values, information indicative of motion of an object in physical contact with the first surface. 7. The sensing apparatus of claim 6 wherein the circuitry to generate the information indicative of motion of the object in physical contact with the first surface comprises circuitry to generate information indicative of force applied to the first surface by the object as the object moves. 8. The sensing apparatus of claim 1 wherein the readout circuitry to obtain the information indicative of respective mechanical frequencies comprises circuitry to receive, from each of the plurality of resonant MEMS devices, a respective digital value indicative of the mechanical resonance frequency of the resonant MEMS device during the first time interval. 9. The sensing apparatus of claim 8 wherein each of the resonant MEMS devices comprises a resonant MEMS structure and circuitry to (i) enable resonant vibration of the resonant MEMS structure, (ii) generate an oscillating signal in response to the resonant vibration, (iii) detect a frequency of the oscillating signal and (iv) generate, as the respective digital value indicative of the mechanical resonance frequency, a multi-bit digital numeric value according to the frequency of the oscillating signal. 10. The sensing apparatus of claim 1 wherein the readout circuitry to obtain information indicative of the respective mechanical resonance frequencies sufficient to identify the locus of the force applied to the first surface comprises circuitry to obtain information that enables triangulation of a position on the first surface at which the force is applied. 11. A method of operation within a sensing apparatus having a first surface and a plurality of MEMS devices disposed in physical contact with respective regions of the first surface, the method comprising:
enabling a respective resonant member within each of the plurality of MEMS devices to vibrate at a respective resonance frequency that varies according to deflection of the first surface in the respective region of physical contact; and obtaining from the plurality of MEMS devices, within a first time interval, information indicative of the respective mechanical resonance frequencies of the vibrating resonance members thereof sufficient to identify a locus and amplitude of a force applied to the first surface. 12. The method of claim 11 wherein enabling the respective resonant member within each of the plurality of MEMS devices to vibrate at the respective resonance frequency comprises applying an actuating signal to the resonant MEMS structure to sustain at least temporary resonant vibration thereof, and wherein obtaining the information indicative of the respective mechanical resonance frequencies comprises sensing vibrational frequencies of the respective resonant members of the MEMS devices. 13. The method of claim 12 wherein applying the actuating signal to the resonant MEMS structure to sustain at least temporary resonant vibration thereof comprises at least one of (i) generating the actuating signal within the MEMS device containing the resonant MEMS structure or (ii) generating the actuating signal externally to the MEMS device containing the resonant MEMS structure and supplying the actuating signal to the MEMS device. 14. The method of claim 1 wherein the first surface comprises a substantially planar surface that encompasses the respective regions of physical contact of at least a portion of the plurality of resonant MEMS devices and that is subject to localized deflection in response to the applied force, and wherein obtaining information indicative of the respective mechanical resonance frequencies of the vibrating resonance members sufficient to identify the locus and amplitude of the force applied to the first surface comprises generating information indicative of locus and amplitude of a force applied to the substantially planar surface. 15. The method of claim 11 further comprising generating, based on the information indicative of the respective mechanical resonance frequencies, information indicative of the locus and amplitude of the force applied to the first surface. 16. The method claim 11 wherein the information indicative of the mechanical resonance frequencies comprises a first set of resonance frequency values, and wherein the method further comprises:
obtaining, over a sequence of time intervals that follow the first time interval, additional sets of resonance frequency values; and
generating, based on the first set of resonance frequency values and the additional sets of resonance frequency values, information indicative of motion of an object in physical contact with the first surface. 17. The method of claim 16 wherein generating the information indicative of motion of the object in physical contact with the first surface comprises generating information indicative of force applied to the first surface by the object as the object moves. 18. The method of claim 11 wherein obtaining the information indicative of respective mechanical frequencies comprises receiving, from each of the plurality of MEMS devices, a respective digital value indicative of the mechanical resonance frequency of at which the resonant member therein vibrates during the first time interval. 19. The method of claim 18 further comprising generating the respective digital value within each of the MEMS devices, including generating a multi-bit digital numeric value according to the frequency at which the resonant member within the MEMS device vibrates during the first time interval. 20. The method of claim 11 wherein obtaining information indicative of the respective mechanical resonance frequencies sufficient to identify the locus of the force applied to the first surface comprises obtaining information that enables triangulation of a position on the first surface at which the force is applied. 21. A sensing device comprising:
a first surface; a plurality of resonant MEMS devices each disposed in physical contact with a respective region of the first surface and having a mechanical resonance frequency that varies according to deflection of the first surface in the respective region of physical contact; and means for obtaining, within a first time interval, information indicative of the respective mechanical resonance frequencies of the plurality of resonant MEMS devices sufficient to identify a locus and amplitude of a force applied to the first surface. | Spatially-distributed resonant MEMS sensors are coordinated to generate frequency-modulated signals indicative of regional contact forces, ambient conditions and/or environmental composition.1. A sensing apparatus comprising:
a first surface; a plurality of resonant MEMS devices each disposed in physical contact with a respective region of the first surface and having a mechanical resonance frequency that varies according to deflection of the first surface in the respective region of physical contact; and readout circuitry to obtain, within a first time interval, information indicative of the respective mechanical resonance frequencies of the plurality of resonant MEMS devices sufficient to identify a locus and amplitude of a force applied to the first surface. 2. The sensing apparatus of claim 1 wherein each of the plurality of resonant MEMS devices comprises a resonant MEMS structure and circuitry to (i) apply an actuating signal to the resonant MEMS structure to sustain at least temporary resonant vibration thereof and (ii) circuitry to sense, as the mechanical resonance frequency of the resonant MEMS device, a frequency of the resonant vibration. 3. The sensing apparatus of claim 2 wherein the circuitry to apply the actuating signal to the resonant MEMS structure comprises at least one of (i) circuitry to generate the actuating signal or (ii) circuitry to receive the actuating signal from an external source. 4. The sensing apparatus of claim 1 wherein the first surface comprises a substantially planar surface that encompasses the respective regions of physical contact of at least a portion of the plurality of resonant MEMS devices, the substantially planar surface subject to localized deflection in response to the applied force. 5. The sensing apparatus of claim 1 further comprising circuitry to generate, based on the information indicative of the respective mechanical resonance frequencies, information indicative of the locus and amplitude of the force applied to the first surface. 6. The sensing apparatus of claim 1 wherein the information indicative of the mechanical resonance frequencies comprises a first set of resonance frequency values and wherein the readout circuitry to obtain the first set of resonance frequency values within the first time interval is additionally to obtain, over a sequence of time intervals that follow the first time interval, additional sets of resonance frequency values, the sensing apparatus further comprising circuitry to generate, based on the first set of resonance frequency values and the additional sets of resonance frequency values, information indicative of motion of an object in physical contact with the first surface. 7. The sensing apparatus of claim 6 wherein the circuitry to generate the information indicative of motion of the object in physical contact with the first surface comprises circuitry to generate information indicative of force applied to the first surface by the object as the object moves. 8. The sensing apparatus of claim 1 wherein the readout circuitry to obtain the information indicative of respective mechanical frequencies comprises circuitry to receive, from each of the plurality of resonant MEMS devices, a respective digital value indicative of the mechanical resonance frequency of the resonant MEMS device during the first time interval. 9. The sensing apparatus of claim 8 wherein each of the resonant MEMS devices comprises a resonant MEMS structure and circuitry to (i) enable resonant vibration of the resonant MEMS structure, (ii) generate an oscillating signal in response to the resonant vibration, (iii) detect a frequency of the oscillating signal and (iv) generate, as the respective digital value indicative of the mechanical resonance frequency, a multi-bit digital numeric value according to the frequency of the oscillating signal. 10. The sensing apparatus of claim 1 wherein the readout circuitry to obtain information indicative of the respective mechanical resonance frequencies sufficient to identify the locus of the force applied to the first surface comprises circuitry to obtain information that enables triangulation of a position on the first surface at which the force is applied. 11. A method of operation within a sensing apparatus having a first surface and a plurality of MEMS devices disposed in physical contact with respective regions of the first surface, the method comprising:
enabling a respective resonant member within each of the plurality of MEMS devices to vibrate at a respective resonance frequency that varies according to deflection of the first surface in the respective region of physical contact; and obtaining from the plurality of MEMS devices, within a first time interval, information indicative of the respective mechanical resonance frequencies of the vibrating resonance members thereof sufficient to identify a locus and amplitude of a force applied to the first surface. 12. The method of claim 11 wherein enabling the respective resonant member within each of the plurality of MEMS devices to vibrate at the respective resonance frequency comprises applying an actuating signal to the resonant MEMS structure to sustain at least temporary resonant vibration thereof, and wherein obtaining the information indicative of the respective mechanical resonance frequencies comprises sensing vibrational frequencies of the respective resonant members of the MEMS devices. 13. The method of claim 12 wherein applying the actuating signal to the resonant MEMS structure to sustain at least temporary resonant vibration thereof comprises at least one of (i) generating the actuating signal within the MEMS device containing the resonant MEMS structure or (ii) generating the actuating signal externally to the MEMS device containing the resonant MEMS structure and supplying the actuating signal to the MEMS device. 14. The method of claim 1 wherein the first surface comprises a substantially planar surface that encompasses the respective regions of physical contact of at least a portion of the plurality of resonant MEMS devices and that is subject to localized deflection in response to the applied force, and wherein obtaining information indicative of the respective mechanical resonance frequencies of the vibrating resonance members sufficient to identify the locus and amplitude of the force applied to the first surface comprises generating information indicative of locus and amplitude of a force applied to the substantially planar surface. 15. The method of claim 11 further comprising generating, based on the information indicative of the respective mechanical resonance frequencies, information indicative of the locus and amplitude of the force applied to the first surface. 16. The method claim 11 wherein the information indicative of the mechanical resonance frequencies comprises a first set of resonance frequency values, and wherein the method further comprises:
obtaining, over a sequence of time intervals that follow the first time interval, additional sets of resonance frequency values; and
generating, based on the first set of resonance frequency values and the additional sets of resonance frequency values, information indicative of motion of an object in physical contact with the first surface. 17. The method of claim 16 wherein generating the information indicative of motion of the object in physical contact with the first surface comprises generating information indicative of force applied to the first surface by the object as the object moves. 18. The method of claim 11 wherein obtaining the information indicative of respective mechanical frequencies comprises receiving, from each of the plurality of MEMS devices, a respective digital value indicative of the mechanical resonance frequency of at which the resonant member therein vibrates during the first time interval. 19. The method of claim 18 further comprising generating the respective digital value within each of the MEMS devices, including generating a multi-bit digital numeric value according to the frequency at which the resonant member within the MEMS device vibrates during the first time interval. 20. The method of claim 11 wherein obtaining information indicative of the respective mechanical resonance frequencies sufficient to identify the locus of the force applied to the first surface comprises obtaining information that enables triangulation of a position on the first surface at which the force is applied. 21. A sensing device comprising:
a first surface; a plurality of resonant MEMS devices each disposed in physical contact with a respective region of the first surface and having a mechanical resonance frequency that varies according to deflection of the first surface in the respective region of physical contact; and means for obtaining, within a first time interval, information indicative of the respective mechanical resonance frequencies of the plurality of resonant MEMS devices sufficient to identify a locus and amplitude of a force applied to the first surface. | 2,800 |
11,973 | 11,973 | 15,630,185 | 2,896 | A display device component includes an optical waveguide having a surface; a first material formed on a portion of the surface of the optical waveguide; and a second material formed on a portion of the first material. The first material has light scattering properties. | 1. A display device component comprising:
an optical waveguide having a first surface and a second surface; and a first marking material formed, in an image-wise manner, on said first surface of said optical waveguide to create a plurality of image regions having said first marking material, said first marking material having light scattering properties such that light passing through said first marking material is emitted from said first marking material in a direction away from said first surface of said optical waveguide; said plurality of image regions including,
a first subset of said plurality of image regions having a first density of said first marking material, and
a second subset of said plurality of image regions having a second density of said first marking material;
said first density of said first marking material not being equal to said second density of said first marking material to create areas of different brightness on said first surface of said optical waveguide. 2. The display device component as claimed in claim 1, wherein said first marking material is a white marking material. 3. The display device component as claimed in claim 2, wherein said white marking material is ink. 4. The display device component as claimed in claim 2, wherein said white marking material is toner. 5. A display device component comprising:
an optical waveguide having a first surface and a second surface; and a first marking material formed, in an image-wise manner, on said first surface of said optical waveguide to create a plurality of image regions having said first marking material, said first marking material having light scattering particles embedded therein such that light passing through said first marking material is emitted from said first marking material in a direction away from said first surface of said optical waveguide; said plurality of image regions including,
a first subset of said plurality of image regions having a first density of said first marking material, and
a second subset of said plurality of image regions having a second density of said first marking material;
said first density of said first marking material not being equal to said second density of said first marking material to create areas of different brightness. 6. The display device component as claimed in claim 5, wherein said first marking material is a white marking material. 7. The display device component as claimed in claim 6, wherein said white marking material is ink. 8. The display device component as claimed in claim 6, wherein said white marking material is toner. 9. A display device component comprising:
an optical waveguide having a first surface and a second surface; and a first marking material formed, in an image-wise manner, on said first surface of said optical waveguide to create a plurality of image regions having said first marking material, said first marking material having light scattering particles embedded therein such that light passing through said first marking material is emitted from said first marking material in a direction away from said first surface of said optical waveguide, each image region having an amount of said first marking material formed therein; said amount of said first marking material being modulated for each image region to create areas of different brightness. 10. The display device component as claimed in claim 9, wherein said first marking material is a white marking material. 11. The display device component as claimed in claim 10, wherein said white marking material is ink. 12. The display device component as claimed in claim 10, wherein said white marking material is toner. 13. A process for creating and reusing an optical waveguide utilized in an edge lighting illuminated display, comprising:
(a) forming a first marking material marking on a portion of a first surface of an optical waveguide, the first marking material being a UV curable ink and having light scattering properties such that light passing through the first marking material is emitted from the first marking material in a direction away from the first surface of the optical waveguide; and (b) cleaning the first surface of the optical waveguide, with a solvent, to remove the first marking material. 14. The process as claimed in claim 13, wherein the solvent is acetone. 15. The process as claimed in claim 13, further comprising:
(c) mechanically scrubbing the first surface of the optical waveguide to assist in the removal of the first marking material. 16-20. (canceled) 21. A display device component comprising:
an optical waveguide having a first surface and a second surface; a removable transparent layer having a first surface and a second surface, said first surface of said removable transparent layer being adhered to said first surface of said optical waveguide; and a first marking material formed, in an image-wise manner, on said second surface of said removable transparent layer to create a plurality of image regions having said first marking material, said first marking material having light scattering particles embedded therein such that light passing through said first marking material is emitted from said first marking material in a direction away from said first surface of said optical waveguide; said plurality of image regions including,
a first subset of said plurality of image regions having a first density of said first marking material, and
a second subset of said plurality of image regions having a second density of said first marking material;
said first density of said first marking material not being equal to said second density of said first marking material to create areas of different brightness. 22. The display device component as claimed in claim 21, wherein said first marking material is a UV curable marking material. 23. A display device component comprising:
an optical waveguide having a first surface and a second surface; a removable transparent layer having a first surface and a second surface, said first surface of said removable transparent layer being adhered to said first surface of said optical waveguide; and a first marking material formed, in an image-wise manner, on said second surface of said removable transparent layer to create a plurality of image regions having said first marking material, said first marking material having light scattering particles embedded therein such that light passing through said first marking material is emitted from said first marking material in a direction away from said first surface of said optical waveguide, each image region having an amount of said first marking material formed therein; said amount of said first marking material being modulated for each image region to create areas of different brightness. 24. The display device component as claimed in claim 23, wherein said first marking material is a UV curable marking material. | A display device component includes an optical waveguide having a surface; a first material formed on a portion of the surface of the optical waveguide; and a second material formed on a portion of the first material. The first material has light scattering properties.1. A display device component comprising:
an optical waveguide having a first surface and a second surface; and a first marking material formed, in an image-wise manner, on said first surface of said optical waveguide to create a plurality of image regions having said first marking material, said first marking material having light scattering properties such that light passing through said first marking material is emitted from said first marking material in a direction away from said first surface of said optical waveguide; said plurality of image regions including,
a first subset of said plurality of image regions having a first density of said first marking material, and
a second subset of said plurality of image regions having a second density of said first marking material;
said first density of said first marking material not being equal to said second density of said first marking material to create areas of different brightness on said first surface of said optical waveguide. 2. The display device component as claimed in claim 1, wherein said first marking material is a white marking material. 3. The display device component as claimed in claim 2, wherein said white marking material is ink. 4. The display device component as claimed in claim 2, wherein said white marking material is toner. 5. A display device component comprising:
an optical waveguide having a first surface and a second surface; and a first marking material formed, in an image-wise manner, on said first surface of said optical waveguide to create a plurality of image regions having said first marking material, said first marking material having light scattering particles embedded therein such that light passing through said first marking material is emitted from said first marking material in a direction away from said first surface of said optical waveguide; said plurality of image regions including,
a first subset of said plurality of image regions having a first density of said first marking material, and
a second subset of said plurality of image regions having a second density of said first marking material;
said first density of said first marking material not being equal to said second density of said first marking material to create areas of different brightness. 6. The display device component as claimed in claim 5, wherein said first marking material is a white marking material. 7. The display device component as claimed in claim 6, wherein said white marking material is ink. 8. The display device component as claimed in claim 6, wherein said white marking material is toner. 9. A display device component comprising:
an optical waveguide having a first surface and a second surface; and a first marking material formed, in an image-wise manner, on said first surface of said optical waveguide to create a plurality of image regions having said first marking material, said first marking material having light scattering particles embedded therein such that light passing through said first marking material is emitted from said first marking material in a direction away from said first surface of said optical waveguide, each image region having an amount of said first marking material formed therein; said amount of said first marking material being modulated for each image region to create areas of different brightness. 10. The display device component as claimed in claim 9, wherein said first marking material is a white marking material. 11. The display device component as claimed in claim 10, wherein said white marking material is ink. 12. The display device component as claimed in claim 10, wherein said white marking material is toner. 13. A process for creating and reusing an optical waveguide utilized in an edge lighting illuminated display, comprising:
(a) forming a first marking material marking on a portion of a first surface of an optical waveguide, the first marking material being a UV curable ink and having light scattering properties such that light passing through the first marking material is emitted from the first marking material in a direction away from the first surface of the optical waveguide; and (b) cleaning the first surface of the optical waveguide, with a solvent, to remove the first marking material. 14. The process as claimed in claim 13, wherein the solvent is acetone. 15. The process as claimed in claim 13, further comprising:
(c) mechanically scrubbing the first surface of the optical waveguide to assist in the removal of the first marking material. 16-20. (canceled) 21. A display device component comprising:
an optical waveguide having a first surface and a second surface; a removable transparent layer having a first surface and a second surface, said first surface of said removable transparent layer being adhered to said first surface of said optical waveguide; and a first marking material formed, in an image-wise manner, on said second surface of said removable transparent layer to create a plurality of image regions having said first marking material, said first marking material having light scattering particles embedded therein such that light passing through said first marking material is emitted from said first marking material in a direction away from said first surface of said optical waveguide; said plurality of image regions including,
a first subset of said plurality of image regions having a first density of said first marking material, and
a second subset of said plurality of image regions having a second density of said first marking material;
said first density of said first marking material not being equal to said second density of said first marking material to create areas of different brightness. 22. The display device component as claimed in claim 21, wherein said first marking material is a UV curable marking material. 23. A display device component comprising:
an optical waveguide having a first surface and a second surface; a removable transparent layer having a first surface and a second surface, said first surface of said removable transparent layer being adhered to said first surface of said optical waveguide; and a first marking material formed, in an image-wise manner, on said second surface of said removable transparent layer to create a plurality of image regions having said first marking material, said first marking material having light scattering particles embedded therein such that light passing through said first marking material is emitted from said first marking material in a direction away from said first surface of said optical waveguide, each image region having an amount of said first marking material formed therein; said amount of said first marking material being modulated for each image region to create areas of different brightness. 24. The display device component as claimed in claim 23, wherein said first marking material is a UV curable marking material. | 2,800 |
11,974 | 11,974 | 15,665,069 | 2,836 | In a system and method for operating a system, a drive is connectable to a supply-voltage source, especially an AC-voltage source, with the aid of an apparatus, in particular a control unit, via electric lines installed in the system, and information is transmittable between the control unit and the drive, using the lines. | 1-28. (canceled) 29. A system, comprising:
an apparatus, including a control unit, connectable to a multi-phase AC supply-voltage source; and a device connected to the apparatus via a plurality of lines, each line corresponding to a respective phase of the AC supply-voltage source, each line adapted to supply AC voltage from the apparatus to the device to power the device, a single one of the lines adapted to transmit information between the control unit and the device; wherein the device includes a voltage-measurement device adapted to measure voltage on each of the plurality of lines, the device including a curve evaluation device adapted to evaluate the measured voltage associated with the single one of the lines adapted to transmit information between the control unit and the device, the curve evaluation device including an amplifier adapted to amplify the measured voltage associated with the single one of the lines adapted to transmit information between the control unit and the device by a factor to an amplified value to uniquely identify information transmitted between the control unit and the device. 30. The system according to claim 29, wherein the device is arranged as (a) a drive, (b) a counting device, (c) a gas meter, (d) an electricity meter, and/or (e) a household electrical device. 31. The system according to claim 30, wherein the drive includes a measurement device adapted to measure supply voltages assigned to the lines. 32. The system according to claim 30, wherein three lines are provided, the voltage-measurement device adapted to measure voltage between each line and a reference potential. 33. The system according to claim 29, wherein the apparatus includes at least one of (a) a half-wave control and (b) a half-wave control for at least one of three lines. 34. The system according to claim 29, further comprising a difference device adapted to form a difference between two measured voltages. 35. The system according to claim 29, wherein the curve evaluation device is adapted to determine a sign reversal. 36. The system according to claim 29, further comprising a comparator adapted for comparison with threshold values, the information including a result of the comparison. 37. The system according to claim 29, wherein, during a time interval in which information is transmitted, the device is fully powerable by only two of three phases. 38. The system according to claim 29, wherein the apparatus is adapted to shift the single one of the lines adapted to transmit information between the control unit and the device to different states one after another in time to code and transmit the information. 39. The system according to claim 38, wherein a first state is a blocking of negative current components, and a second state is a blocking of positive current components. 40. The system according to claim 39, wherein a third state is completely blocking current, and a fourth state is completely passing the current through. 41. The system according to claim 29, wherein the device includes signal electronics adapted to receive and decode the information. 42. The system according to claim 30, wherein the drive includes an electronic circuit adapted to reverse a sense of rotation of a three-phase supply. 43. The system according to claim 30, wherein the drive has an electronic circuit adapted to influence a rotary motion of a rotor of an electric motor, including (a) a motor switch, (b) a soft start, and/or (c) a converter. 44. The system according to claim 29, wherein during a time interval in which information is transmitted, two of three phases for powering the drive change, and a third phase changes such that the two other phases are always provided to power signal electronics of the drive, and the third phase is provided for transmitting the information. 45. The system according to claim 29, wherein the apparatus includes a series connection of power switches assigned to the single one of the lines adapted to transmit information between the control unit and the device, the power switches adapted to (a) block and/or (b) let through (a) positive and/or (b) negative current. 46. The system according to claim 45, wherein the power switches are drivable by the control unit. 47. The system according to claim 30, wherein the drive includes a rectifier, fed from the lines, having (a) unipolar and/or (b) rectified output voltage having a negative and positive potential. 48. The system according to claim 47, wherein the negative potential is arranged as a reference potential. 49. The system according to claim 29, wherein (a) signal electronics of the drive are provided at a negative potential and/or (b) a voltage between electrical contacts of components of the signal electronics and the negative potential is always lower in terms of absolute value than the voltage to a positive potential. 50. The system according to claim 29, wherein the apparatus includes two power switches connected to the control unit, each power switch connected in parallel to a respective diode that is external to the power switch and connected in series to each other, each diode being positioned on the single one of the lines adapted to transmit information between the control unit and the device;
wherein the two power switches are configured to switch between four different states of supply voltages of the AC supply-voltage source: (i) a first state where current is blocked; (ii) a second state where only a positive current is enabled; (iii) a third state where only a negative current is enabled; and (iv) a fourth state where the current is completely conducted; and wherein the apparatus is adapted to switch the series connection of power switches between the four different states of the supply voltages of the AC supply-voltage source one after another in time to code the information on the single one of the lines adapted to transmit information between the control unit and the device. 51. A method for operating a system including an apparatus, having a control unit, connected to a multi-phase AC supply-voltage source, and a device connected to the apparatus via a plurality of lines, each line corresponding to a respective phase of the AC supply-voltage source, comprising:
supplying AC voltage from the apparatus to the device via the lines to power the device; transmitting information between the control unit and the device by a single one of the lines adapted to transmit information between the control unit and the device; measuring supply voltages of the lines; forming a difference between the measured supply voltage of the single one of the lines adapted to transmit information between the control unit and the device and the measured supply voltage of at least one other line; and performing a curve evaluation to evaluate the measured voltage associated with the single one of the lines adapted to transmit information between the control unit and the device, the curve evaluation including amplifying the measured supply voltage associated with the single one of the lines adapted to transmit information between the control unit and the device by a factor to an amplified value to uniquely identify information transmitted between the control unit and the device. 52. The method according to claim 50, wherein the apparatus includes two power switches connected to the control unit, each power switch connected in parallel to a respective diode that is external to the power switch and connected in series to each other, each diode being positioned on the single one of the lines adapted to transmit information between the control unit and the device, the method further comprising:
switching the two power switches among four different states of supply voltage of the single one of the lines adapted to transmit information between the control unit and the device: (i) a first state where current is blocked; (ii) a second state where only a positive current is enabled; (iii) a third state where only a negative current is enabled; and (iv) a fourth state where the current is completely conducted, one after another in time to code the information on the single one of the lines adapted to transmit information between the control unit and the device. | In a system and method for operating a system, a drive is connectable to a supply-voltage source, especially an AC-voltage source, with the aid of an apparatus, in particular a control unit, via electric lines installed in the system, and information is transmittable between the control unit and the drive, using the lines.1-28. (canceled) 29. A system, comprising:
an apparatus, including a control unit, connectable to a multi-phase AC supply-voltage source; and a device connected to the apparatus via a plurality of lines, each line corresponding to a respective phase of the AC supply-voltage source, each line adapted to supply AC voltage from the apparatus to the device to power the device, a single one of the lines adapted to transmit information between the control unit and the device; wherein the device includes a voltage-measurement device adapted to measure voltage on each of the plurality of lines, the device including a curve evaluation device adapted to evaluate the measured voltage associated with the single one of the lines adapted to transmit information between the control unit and the device, the curve evaluation device including an amplifier adapted to amplify the measured voltage associated with the single one of the lines adapted to transmit information between the control unit and the device by a factor to an amplified value to uniquely identify information transmitted between the control unit and the device. 30. The system according to claim 29, wherein the device is arranged as (a) a drive, (b) a counting device, (c) a gas meter, (d) an electricity meter, and/or (e) a household electrical device. 31. The system according to claim 30, wherein the drive includes a measurement device adapted to measure supply voltages assigned to the lines. 32. The system according to claim 30, wherein three lines are provided, the voltage-measurement device adapted to measure voltage between each line and a reference potential. 33. The system according to claim 29, wherein the apparatus includes at least one of (a) a half-wave control and (b) a half-wave control for at least one of three lines. 34. The system according to claim 29, further comprising a difference device adapted to form a difference between two measured voltages. 35. The system according to claim 29, wherein the curve evaluation device is adapted to determine a sign reversal. 36. The system according to claim 29, further comprising a comparator adapted for comparison with threshold values, the information including a result of the comparison. 37. The system according to claim 29, wherein, during a time interval in which information is transmitted, the device is fully powerable by only two of three phases. 38. The system according to claim 29, wherein the apparatus is adapted to shift the single one of the lines adapted to transmit information between the control unit and the device to different states one after another in time to code and transmit the information. 39. The system according to claim 38, wherein a first state is a blocking of negative current components, and a second state is a blocking of positive current components. 40. The system according to claim 39, wherein a third state is completely blocking current, and a fourth state is completely passing the current through. 41. The system according to claim 29, wherein the device includes signal electronics adapted to receive and decode the information. 42. The system according to claim 30, wherein the drive includes an electronic circuit adapted to reverse a sense of rotation of a three-phase supply. 43. The system according to claim 30, wherein the drive has an electronic circuit adapted to influence a rotary motion of a rotor of an electric motor, including (a) a motor switch, (b) a soft start, and/or (c) a converter. 44. The system according to claim 29, wherein during a time interval in which information is transmitted, two of three phases for powering the drive change, and a third phase changes such that the two other phases are always provided to power signal electronics of the drive, and the third phase is provided for transmitting the information. 45. The system according to claim 29, wherein the apparatus includes a series connection of power switches assigned to the single one of the lines adapted to transmit information between the control unit and the device, the power switches adapted to (a) block and/or (b) let through (a) positive and/or (b) negative current. 46. The system according to claim 45, wherein the power switches are drivable by the control unit. 47. The system according to claim 30, wherein the drive includes a rectifier, fed from the lines, having (a) unipolar and/or (b) rectified output voltage having a negative and positive potential. 48. The system according to claim 47, wherein the negative potential is arranged as a reference potential. 49. The system according to claim 29, wherein (a) signal electronics of the drive are provided at a negative potential and/or (b) a voltage between electrical contacts of components of the signal electronics and the negative potential is always lower in terms of absolute value than the voltage to a positive potential. 50. The system according to claim 29, wherein the apparatus includes two power switches connected to the control unit, each power switch connected in parallel to a respective diode that is external to the power switch and connected in series to each other, each diode being positioned on the single one of the lines adapted to transmit information between the control unit and the device;
wherein the two power switches are configured to switch between four different states of supply voltages of the AC supply-voltage source: (i) a first state where current is blocked; (ii) a second state where only a positive current is enabled; (iii) a third state where only a negative current is enabled; and (iv) a fourth state where the current is completely conducted; and wherein the apparatus is adapted to switch the series connection of power switches between the four different states of the supply voltages of the AC supply-voltage source one after another in time to code the information on the single one of the lines adapted to transmit information between the control unit and the device. 51. A method for operating a system including an apparatus, having a control unit, connected to a multi-phase AC supply-voltage source, and a device connected to the apparatus via a plurality of lines, each line corresponding to a respective phase of the AC supply-voltage source, comprising:
supplying AC voltage from the apparatus to the device via the lines to power the device; transmitting information between the control unit and the device by a single one of the lines adapted to transmit information between the control unit and the device; measuring supply voltages of the lines; forming a difference between the measured supply voltage of the single one of the lines adapted to transmit information between the control unit and the device and the measured supply voltage of at least one other line; and performing a curve evaluation to evaluate the measured voltage associated with the single one of the lines adapted to transmit information between the control unit and the device, the curve evaluation including amplifying the measured supply voltage associated with the single one of the lines adapted to transmit information between the control unit and the device by a factor to an amplified value to uniquely identify information transmitted between the control unit and the device. 52. The method according to claim 50, wherein the apparatus includes two power switches connected to the control unit, each power switch connected in parallel to a respective diode that is external to the power switch and connected in series to each other, each diode being positioned on the single one of the lines adapted to transmit information between the control unit and the device, the method further comprising:
switching the two power switches among four different states of supply voltage of the single one of the lines adapted to transmit information between the control unit and the device: (i) a first state where current is blocked; (ii) a second state where only a positive current is enabled; (iii) a third state where only a negative current is enabled; and (iv) a fourth state where the current is completely conducted, one after another in time to code the information on the single one of the lines adapted to transmit information between the control unit and the device. | 2,800 |
11,975 | 11,975 | 14,359,550 | 2,859 | A hand tool case includes at least one first inductive charge receiving area and at least one first adjustment unit which is provided for changing a position and/or a size of at least the first inductive charge receiving area. | 1-9. (canceled) 10. A hand tool case, comprising:
at least one first inductive charge receiving area; and at least one first adjustment unit for changing at least one of a position and a size of at least the first inductive charge receiving area. 11. The hand tool case as recited in claim 10, wherein the at least one first inductive charge receiving area is situated at least partially in immediate proximity to a wall. 12. The hand tool case as recited in claim 11, wherein the at least one first adjustment unit presses at least one hand tool battery which is inserted into the at least one first inductive charge receiving area against the wall. 13. The hand tool case as recited in claim 12, wherein the at least one first adjustment unit has at least one spring element. 14. The hand tool case as recited in claim 12, further comprising:
at least one second inductive charge receiving area. 15. The hand tool case as recited in claim 14, further comprising:
a second adjustment unit provided for changing at least one of a position and a size of the at least one second inductive charge receiving area. 16. The hand tool case as recited in claim 14, wherein the first adjustment unit simultaneously adjusts distances between (i) each one of two hand tool batteries which are situated in the first and second inductive charge receiving areas and (ii) the wall. 17. A system comprising:
a hand tool case having at least one first inductive charge receiving area and at least one first adjustment unit for changing at least one of a position and a size of at least the first inductive charge receiving area; and at least one hand tool battery inserted into the at least one first inductive charge receiving area. | A hand tool case includes at least one first inductive charge receiving area and at least one first adjustment unit which is provided for changing a position and/or a size of at least the first inductive charge receiving area.1-9. (canceled) 10. A hand tool case, comprising:
at least one first inductive charge receiving area; and at least one first adjustment unit for changing at least one of a position and a size of at least the first inductive charge receiving area. 11. The hand tool case as recited in claim 10, wherein the at least one first inductive charge receiving area is situated at least partially in immediate proximity to a wall. 12. The hand tool case as recited in claim 11, wherein the at least one first adjustment unit presses at least one hand tool battery which is inserted into the at least one first inductive charge receiving area against the wall. 13. The hand tool case as recited in claim 12, wherein the at least one first adjustment unit has at least one spring element. 14. The hand tool case as recited in claim 12, further comprising:
at least one second inductive charge receiving area. 15. The hand tool case as recited in claim 14, further comprising:
a second adjustment unit provided for changing at least one of a position and a size of the at least one second inductive charge receiving area. 16. The hand tool case as recited in claim 14, wherein the first adjustment unit simultaneously adjusts distances between (i) each one of two hand tool batteries which are situated in the first and second inductive charge receiving areas and (ii) the wall. 17. A system comprising:
a hand tool case having at least one first inductive charge receiving area and at least one first adjustment unit for changing at least one of a position and a size of at least the first inductive charge receiving area; and at least one hand tool battery inserted into the at least one first inductive charge receiving area. | 2,800 |
11,976 | 11,976 | 13,617,584 | 2,819 | A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A first gate dielectric layer is disposed on the second active layer. A second gate dielectric layer is disposed on the first gate dielectric layer. A passivation layer is disposed over the second gate dielectric layer. A gate extends through the passivation layer to the second gate dielectric layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts. | 1. A heterostructure semiconductor device comprising:
a first active layer; a second active layer disposed on the first active layer, a two-dimensional electron gas layer forming between the first and second active layers; a first gate dielectric layer disposed on the second active layer; a second gate dielectric layer disposed on the first gate dielectric layer; a passivation layer disposed over the second gate dielectric layer; a gate that extends through the passivation layer to the second gate dielectric layer; first and second ohmic contacts that electrically connect to the second active layer, the first and second ohmic contacts being laterally spaced-apart, the gate being disposed between the first and second ohmic contacts. 2. The heterostructure semiconductor device of claim 1 wherein the second gate dielectric layer comprises aluminum oxide (Al2O3). 3. The heterostructure semiconductor device of claim 1 wherein the first gate dielectric layer has a first thickness and the second gate dielectric has a second thickness, the second thickness being larger than the first thickness. 4. The heterostructure semiconductor device of claim 1 wherein the first gate dielectric layer comprises a nitride-based compound. 5. The heterostructure semiconductor device of claim 1 wherein the first gate dielectric layer comprises silicon nitride (SiN). 6. The heterostructure semiconductor device of claim 1 wherein the first gate dielectric layer comprises carbon nitride (CN). 7. The heterostructure semiconductor device of claim 1 wherein the first gate dielectric layer comprises boron nitride (BN). 8. The heterostructure semiconductor device of claim 1 wherein the first gate dielectric layer has a first thickness in a range of about 1-5 nanometers thick. 9. The heterostructure semiconductor device of claim 1 wherein the second gate dielectric has a second thickness in a range of about 10-20 nanometers thick. 10. The heterostructure semiconductor device of claim 1 wherein the first gate dielectric layer has a first thickness and the second gate dielectric has a second thickness, the first thickness and the second thickness are set such that a leakage current through the gate is substantially constant versus temperature during normal operation of heterojunction semiconductor device. 11. The heterostructure semiconductor device of claim 1 wherein the first gate dielectric layer has a first thickness and the second gate dielectric has a second thickness, the first thickness and the second thickness are set such that a threshold voltage is substantially constant versus temperature during normal operation of heterojunction semiconductor device. 12. The heterostructure semiconductor device according to claim 1 wherein the first active layer comprises gallium nitride (GaN). 13. The heterostructure semiconductor device of claim 1 wherein the second active layer comprises aluminum gallium nitride (AlGaN). 14. The heterostructure semiconductor device of claim 1 wherein the first and second active layers are defined as an isolated mesa. 15. The heterostructure semiconductor device of claim 1 wherein the gate comprises a gate metal. 16. The heterostructure semiconductor device of claim 15 wherein the gate metal comprises a nickel gold (NiAu) alloy. 17. The heterostructure semiconductor device of claim 15 wherein the gate metal includes a gate field plate that extends toward the drain ohmic contact. 18. The heterostructure semiconductor device of claim 1 wherein the passivation layer comprises silicon nitride (SiN). 19. The heterostructure semiconductor device of claim 1 wherein the gate metal comprises titanium gold (TiAu) alloy or molybdenum gold MoAu alloy. 20. A method of fabricating a heterostructure semiconductor device comprising:
forming a first active layer on a substrate; forming a second active layer on the first active layer, the first active layer and the second active layer having different bandgaps such that a two-dimensional electron gas layer is formed therebetween; forming a first gate dielectric layer on the second active layer, the first gate dielectric layer having a first thickness; forming a second gate dielectric layer on the first gate dielectric layer, the second gate dielectric layer having a second thickness greater than the first thickness; forming first and second ohmic contacts that each extend vertically through the second gate dielectric layer, and the first gate dielectric layer, the first and second ohmic contacts being laterally spaced-apart and electrically connected to the second active layer; and forming a gate that contacts the second dielectric layer at a lateral position between the first and second ohmic contacts. 21. The method of claim 20 further comprising depositing, prior to the forming of the first and second ohmic contacts, a passivation layer over the second gate dielectric layer. 22. The method of claim 20 further comprising annealing the second gate dielectric layer. 23. The method of claim 20 further comprising annealing the first and second ohmic contacts. 24. The method of claim 20 wherein the first thickness and the second thickness are selected such that a gate leakage current remains substantially constant over temperature during a normal operation of the heterostructure semiconductor device. 25. The method of claim 20 wherein the first gate dielectric layer comprises silicon nitride. 26. The method of claim 20 wherein the second gate dielectric layer comprises aluminum oxide. 27. The method of claim 20 wherein the first active layer comprises gallium nitride. 28. The method of claim 20 wherein the second active layer comprises aluminum gallium nitride. 29. The method of claim 20 wherein the first gate dielectric layer is formed in-situ with the first and second active layers. 30. The method of claim 20 wherein the first gate dielectric layer is formed ex-situ with the first and second active layers. 31. The method of claim 20 wherein the first thickness is in a range of about 1-5 nanometers thick. 32. The method of claim 20 wherein the second thickness is in a range of about 10-20 nanometers thick. 33. The method of claim 20 wherein the forming of the second gate dielectric layer is performed using an Atomic Layer Deposition (ALD) reaction chamber with an Al(CH3)3 precursor and O2 plasma. 34. The method of claim 20 wherein the forming of the first and second ohmic contacts comprises depositing a metal which includes gold (Au). 35. The method of claim 34 wherein the metal comprises TiAlMoAu. | A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A first gate dielectric layer is disposed on the second active layer. A second gate dielectric layer is disposed on the first gate dielectric layer. A passivation layer is disposed over the second gate dielectric layer. A gate extends through the passivation layer to the second gate dielectric layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.1. A heterostructure semiconductor device comprising:
a first active layer; a second active layer disposed on the first active layer, a two-dimensional electron gas layer forming between the first and second active layers; a first gate dielectric layer disposed on the second active layer; a second gate dielectric layer disposed on the first gate dielectric layer; a passivation layer disposed over the second gate dielectric layer; a gate that extends through the passivation layer to the second gate dielectric layer; first and second ohmic contacts that electrically connect to the second active layer, the first and second ohmic contacts being laterally spaced-apart, the gate being disposed between the first and second ohmic contacts. 2. The heterostructure semiconductor device of claim 1 wherein the second gate dielectric layer comprises aluminum oxide (Al2O3). 3. The heterostructure semiconductor device of claim 1 wherein the first gate dielectric layer has a first thickness and the second gate dielectric has a second thickness, the second thickness being larger than the first thickness. 4. The heterostructure semiconductor device of claim 1 wherein the first gate dielectric layer comprises a nitride-based compound. 5. The heterostructure semiconductor device of claim 1 wherein the first gate dielectric layer comprises silicon nitride (SiN). 6. The heterostructure semiconductor device of claim 1 wherein the first gate dielectric layer comprises carbon nitride (CN). 7. The heterostructure semiconductor device of claim 1 wherein the first gate dielectric layer comprises boron nitride (BN). 8. The heterostructure semiconductor device of claim 1 wherein the first gate dielectric layer has a first thickness in a range of about 1-5 nanometers thick. 9. The heterostructure semiconductor device of claim 1 wherein the second gate dielectric has a second thickness in a range of about 10-20 nanometers thick. 10. The heterostructure semiconductor device of claim 1 wherein the first gate dielectric layer has a first thickness and the second gate dielectric has a second thickness, the first thickness and the second thickness are set such that a leakage current through the gate is substantially constant versus temperature during normal operation of heterojunction semiconductor device. 11. The heterostructure semiconductor device of claim 1 wherein the first gate dielectric layer has a first thickness and the second gate dielectric has a second thickness, the first thickness and the second thickness are set such that a threshold voltage is substantially constant versus temperature during normal operation of heterojunction semiconductor device. 12. The heterostructure semiconductor device according to claim 1 wherein the first active layer comprises gallium nitride (GaN). 13. The heterostructure semiconductor device of claim 1 wherein the second active layer comprises aluminum gallium nitride (AlGaN). 14. The heterostructure semiconductor device of claim 1 wherein the first and second active layers are defined as an isolated mesa. 15. The heterostructure semiconductor device of claim 1 wherein the gate comprises a gate metal. 16. The heterostructure semiconductor device of claim 15 wherein the gate metal comprises a nickel gold (NiAu) alloy. 17. The heterostructure semiconductor device of claim 15 wherein the gate metal includes a gate field plate that extends toward the drain ohmic contact. 18. The heterostructure semiconductor device of claim 1 wherein the passivation layer comprises silicon nitride (SiN). 19. The heterostructure semiconductor device of claim 1 wherein the gate metal comprises titanium gold (TiAu) alloy or molybdenum gold MoAu alloy. 20. A method of fabricating a heterostructure semiconductor device comprising:
forming a first active layer on a substrate; forming a second active layer on the first active layer, the first active layer and the second active layer having different bandgaps such that a two-dimensional electron gas layer is formed therebetween; forming a first gate dielectric layer on the second active layer, the first gate dielectric layer having a first thickness; forming a second gate dielectric layer on the first gate dielectric layer, the second gate dielectric layer having a second thickness greater than the first thickness; forming first and second ohmic contacts that each extend vertically through the second gate dielectric layer, and the first gate dielectric layer, the first and second ohmic contacts being laterally spaced-apart and electrically connected to the second active layer; and forming a gate that contacts the second dielectric layer at a lateral position between the first and second ohmic contacts. 21. The method of claim 20 further comprising depositing, prior to the forming of the first and second ohmic contacts, a passivation layer over the second gate dielectric layer. 22. The method of claim 20 further comprising annealing the second gate dielectric layer. 23. The method of claim 20 further comprising annealing the first and second ohmic contacts. 24. The method of claim 20 wherein the first thickness and the second thickness are selected such that a gate leakage current remains substantially constant over temperature during a normal operation of the heterostructure semiconductor device. 25. The method of claim 20 wherein the first gate dielectric layer comprises silicon nitride. 26. The method of claim 20 wherein the second gate dielectric layer comprises aluminum oxide. 27. The method of claim 20 wherein the first active layer comprises gallium nitride. 28. The method of claim 20 wherein the second active layer comprises aluminum gallium nitride. 29. The method of claim 20 wherein the first gate dielectric layer is formed in-situ with the first and second active layers. 30. The method of claim 20 wherein the first gate dielectric layer is formed ex-situ with the first and second active layers. 31. The method of claim 20 wherein the first thickness is in a range of about 1-5 nanometers thick. 32. The method of claim 20 wherein the second thickness is in a range of about 10-20 nanometers thick. 33. The method of claim 20 wherein the forming of the second gate dielectric layer is performed using an Atomic Layer Deposition (ALD) reaction chamber with an Al(CH3)3 precursor and O2 plasma. 34. The method of claim 20 wherein the forming of the first and second ohmic contacts comprises depositing a metal which includes gold (Au). 35. The method of claim 34 wherein the metal comprises TiAlMoAu. | 2,800 |
11,977 | 11,977 | 15,539,851 | 2,836 | An arrangement for power distribution on a vessel, having: a first DC bus operating at a first medium voltage; at least one second DC bus operating at a second medium voltage and having no direct connection with the first DC bus; a first AC bus operating at a low voltage; a first inverter coupled between the first DC bus and the first AC bus for allowing power flow from the first DC bus to the first AC bus in a first operation mode; a second AC bus operating at the low voltage; a second inverter coupled between the second DC bus and the second AC bus for allowing power flow from the second DC bus to the second AC bus in the first operation mode; a low voltage connection system for selectively connecting or disconnecting the first AC bus and the second AC bus. | 1. An arrangement for power distribution on a vessel, comprising:
a first DC bus operating at a first medium voltage; at least one second DC bus operating at a second medium voltage and having no direct connection with the first DC bus; a first AC bus operating at a low voltage; a first inverter coupled between the first DC bus and the first AC bus for allowing power flow from the first DC bus to the first AC bus in a first operation mode; a second AC bus operating at the low voltage; a second inverter coupled between the second DC bus and the second AC bus for allowing power flow from the second DC bus to the second AC bus in the first operation mode; a low voltage connection system for selectively connecting or disconnecting the first AC bus and the second AC bus; wherein the arrangement is adapted, in a second operation mode to connect the first AC bus and the second AC bus via the low voltage connection system and to control the first inverter and the second inverter, in order to supply power from the second DC bus via the second inverter to the second AC bus, from the second AC bus to the first AC bus and from the first AC bus via the first inverter to the first DC bus or vice versa. 2. The arrangement according to claim 1,
wherein the second operation mode is adopted when a power failure occurs in the first DC bus. 3. The arrangement according to claim 1, further comprising
a first transformer coupled between the first inverter and the first AC bus for transforming the first medium voltage to the low voltage; a second transformer coupled between the second inverter and the second AC bus for transforming the second medium voltage to the low voltage. 4. The arrangement according to claim 1, further comprising
at least one first and/or a second AC consumer; a first and/or second consumer inverter coupled to the first respectively second AC consumer and connectable to the first respectively second DC bus for providing power to the first respectively second AC consumer. 5. The arrangement according to claim 4, further comprising:
a first and/or second battery; a first and/or battery inverter coupled to the first respectively second battery and being connectable to the first respectively second AC bus, wherein, in a third operation mode, the first respectively second battery is connected to the first respectively second consumer inverter directly via or not via the first respectively second inverter, in order to supply power from the first respectively second battery to the first respectively second AC consumer. 6. The arrangement according to claim 5,
wherein, in a fourth operation mode, the first and/or second battery is connected via the first respectively second battery inverter, the first respectively second AC bus, the first respectively second transformer and the first respectively second inverter to the first respectively second DC bus, in order to allow power flow there between. 7. The arrangement according to claim 1, further comprising:
a first and/or second secondary AC bus operating at a very low voltage; a first and/or second secondary transformer connectable between the first respectively second AC bus and the first respectively second secondary AC bus. 8. The arrangement according to claim 1, further comprising:
a first and/or second UPS switchboard and a first and/or second uninterruptible power supply connectable between the first respectively second AC bus and the first respectively second UPS switchboard. 9. The arrangement according to claim 1, further comprising:
an low voltage emergency switchboard connectable to the first AC bus; an emergency generator connectable with the emergency switchboard; wherein one or more consumers are connectable to the low voltage emergency switchboard. 10. The arrangement according to claim 9, further comprising:
a very low voltage emergency switchboard connected to the low voltage emergency switchboard via a transformer; wherein one or more consumers are connectable to the very low voltage emergency switchboard. 11. The arrangement according to claim 1, further comprising:
a controller adapted to control breakers, inverters and/or generators, in dependence of power requirements of the consumers and failure state. 12. The arrangement according to claim 1,
wherein plural low voltage AC consumers are connectable to the first AC bus or the second AC bus. 13. The arrangement according to claim 7,
wherein first medium voltage is different from the second medium voltage. 14. A method for power distribution on a vessel, comprising:
operating a first DC bus at a first medium voltage; operating at least one second DC bus having no direct connection with the first DC bus at a second medium voltage; operating a first AC bus at a low voltage; allowing power flow from the first DC bus to the first AC bus in a first operation mode by using a first inverter coupled between the first DC bus and the first AC bus; operating a second AC bus at the low voltage; allowing power flow from the second DC bus to the second AC bus in the first operation mode by using a second inverter coupled between the second DC bus and the second AC bus; selectively connecting or disconnecting the first AC bus and the second AC bus by using a low voltage connection system; wherein in a second operation mode the first AC bus and the second AC bus are connected via the low voltage connection system and control the first inverter and the second inverter, in order to supply power from the second DC bus via the second inverter to the second AC bus, from the second AC bus to the first AC bus and from the first AC bus via the first inverter to the first DC bus or vice versa. 15. The arrangement according to claim 4,
wherein the at least one first and/or a second AC consumer comprises a thruster. 16. The arrangement according to claim 9,
wherein the one or more consumers, including pumps, are connectable to the low voltage emergency switchboard. 17. The arrangement according to claim 11,
wherein the controller is adapted, using frequency droop control, to control breakers, inverters and/or generators, including generator speed, in dependence of power requirements of the consumers and failure state. 18. The arrangement according to claim 13,
wherein the first medium voltage and the second medium voltage is between 1 kV and 10 kV. 19. The arrangement according to claim 13,
wherein the low voltage is between 500 V and 1 kV. 20. The arrangement according to claim 13,
wherein the very low voltage is between 300 V and 200 V. | An arrangement for power distribution on a vessel, having: a first DC bus operating at a first medium voltage; at least one second DC bus operating at a second medium voltage and having no direct connection with the first DC bus; a first AC bus operating at a low voltage; a first inverter coupled between the first DC bus and the first AC bus for allowing power flow from the first DC bus to the first AC bus in a first operation mode; a second AC bus operating at the low voltage; a second inverter coupled between the second DC bus and the second AC bus for allowing power flow from the second DC bus to the second AC bus in the first operation mode; a low voltage connection system for selectively connecting or disconnecting the first AC bus and the second AC bus.1. An arrangement for power distribution on a vessel, comprising:
a first DC bus operating at a first medium voltage; at least one second DC bus operating at a second medium voltage and having no direct connection with the first DC bus; a first AC bus operating at a low voltage; a first inverter coupled between the first DC bus and the first AC bus for allowing power flow from the first DC bus to the first AC bus in a first operation mode; a second AC bus operating at the low voltage; a second inverter coupled between the second DC bus and the second AC bus for allowing power flow from the second DC bus to the second AC bus in the first operation mode; a low voltage connection system for selectively connecting or disconnecting the first AC bus and the second AC bus; wherein the arrangement is adapted, in a second operation mode to connect the first AC bus and the second AC bus via the low voltage connection system and to control the first inverter and the second inverter, in order to supply power from the second DC bus via the second inverter to the second AC bus, from the second AC bus to the first AC bus and from the first AC bus via the first inverter to the first DC bus or vice versa. 2. The arrangement according to claim 1,
wherein the second operation mode is adopted when a power failure occurs in the first DC bus. 3. The arrangement according to claim 1, further comprising
a first transformer coupled between the first inverter and the first AC bus for transforming the first medium voltage to the low voltage; a second transformer coupled between the second inverter and the second AC bus for transforming the second medium voltage to the low voltage. 4. The arrangement according to claim 1, further comprising
at least one first and/or a second AC consumer; a first and/or second consumer inverter coupled to the first respectively second AC consumer and connectable to the first respectively second DC bus for providing power to the first respectively second AC consumer. 5. The arrangement according to claim 4, further comprising:
a first and/or second battery; a first and/or battery inverter coupled to the first respectively second battery and being connectable to the first respectively second AC bus, wherein, in a third operation mode, the first respectively second battery is connected to the first respectively second consumer inverter directly via or not via the first respectively second inverter, in order to supply power from the first respectively second battery to the first respectively second AC consumer. 6. The arrangement according to claim 5,
wherein, in a fourth operation mode, the first and/or second battery is connected via the first respectively second battery inverter, the first respectively second AC bus, the first respectively second transformer and the first respectively second inverter to the first respectively second DC bus, in order to allow power flow there between. 7. The arrangement according to claim 1, further comprising:
a first and/or second secondary AC bus operating at a very low voltage; a first and/or second secondary transformer connectable between the first respectively second AC bus and the first respectively second secondary AC bus. 8. The arrangement according to claim 1, further comprising:
a first and/or second UPS switchboard and a first and/or second uninterruptible power supply connectable between the first respectively second AC bus and the first respectively second UPS switchboard. 9. The arrangement according to claim 1, further comprising:
an low voltage emergency switchboard connectable to the first AC bus; an emergency generator connectable with the emergency switchboard; wherein one or more consumers are connectable to the low voltage emergency switchboard. 10. The arrangement according to claim 9, further comprising:
a very low voltage emergency switchboard connected to the low voltage emergency switchboard via a transformer; wherein one or more consumers are connectable to the very low voltage emergency switchboard. 11. The arrangement according to claim 1, further comprising:
a controller adapted to control breakers, inverters and/or generators, in dependence of power requirements of the consumers and failure state. 12. The arrangement according to claim 1,
wherein plural low voltage AC consumers are connectable to the first AC bus or the second AC bus. 13. The arrangement according to claim 7,
wherein first medium voltage is different from the second medium voltage. 14. A method for power distribution on a vessel, comprising:
operating a first DC bus at a first medium voltage; operating at least one second DC bus having no direct connection with the first DC bus at a second medium voltage; operating a first AC bus at a low voltage; allowing power flow from the first DC bus to the first AC bus in a first operation mode by using a first inverter coupled between the first DC bus and the first AC bus; operating a second AC bus at the low voltage; allowing power flow from the second DC bus to the second AC bus in the first operation mode by using a second inverter coupled between the second DC bus and the second AC bus; selectively connecting or disconnecting the first AC bus and the second AC bus by using a low voltage connection system; wherein in a second operation mode the first AC bus and the second AC bus are connected via the low voltage connection system and control the first inverter and the second inverter, in order to supply power from the second DC bus via the second inverter to the second AC bus, from the second AC bus to the first AC bus and from the first AC bus via the first inverter to the first DC bus or vice versa. 15. The arrangement according to claim 4,
wherein the at least one first and/or a second AC consumer comprises a thruster. 16. The arrangement according to claim 9,
wherein the one or more consumers, including pumps, are connectable to the low voltage emergency switchboard. 17. The arrangement according to claim 11,
wherein the controller is adapted, using frequency droop control, to control breakers, inverters and/or generators, including generator speed, in dependence of power requirements of the consumers and failure state. 18. The arrangement according to claim 13,
wherein the first medium voltage and the second medium voltage is between 1 kV and 10 kV. 19. The arrangement according to claim 13,
wherein the low voltage is between 500 V and 1 kV. 20. The arrangement according to claim 13,
wherein the very low voltage is between 300 V and 200 V. | 2,800 |
11,978 | 11,978 | 16,169,029 | 2,837 | Wireless communication system and method powered by an energy harvester. At least some of the example embodiments are methods including: receiving a burst of electrical energy from an energy harvester that produces the burst of electrical energy from mechanical energy, the burst of electrical energy the result of a single actuation of the energy harvester; rectifying the burst of electrical energy to create rectified energy; applying the rectified energy to the transceiver without applying the rectified energy to a switching power converter; and transmitting an electromagnetic switch including a frame of multiple bytes, the transmitting using the rectified energy. Additional embodiments can include a transceiver system including an energy harvester, a rectifier, a capacitor, and a transceiver, where the transceiver is configured to transmit an electromagnetic signal including a frame of a plurality of bytes during each burst of electrical energy. | 1. A method of operating a transceiver comprising:
receiving a burst of electrical energy from an energy harvester that produces the burst of electrical energy from mechanical energy, the burst of electrical energy the result of a single actuation of the energy harvester; rectifying the burst of electrical energy to create rectified energy; applying the rectified energy to the transceiver without applying the rectified energy to a switching power converter; and transmitting an electromagnetic signal comprising a frame of multiple bytes, the transmitting using the rectified energy. 2. The method of claim 1 wherein receiving the burst of electrical energy further comprises receiving the burst of electrical energy from a mechanical switch configured to produce the burst of electrical energy upon actuation. 3. The method of claim 1 wherein receiving the burst of electrical energy further comprises receiving the burst of electrical energy from a piezoelectric device configured to produce the burst of electrical energy upon being compressed. 4. The method of claim 1 wherein receiving the burst of electrical energy further comprises receiving no more than 500 micro-Joules. 5. The method of claim 4 wherein receiving the burst of electrical energy further comprises receiving the burst of electrical energy within a time window of 10 milliseconds or less, and the burst of electrical energy ceasing thereafter. 6. The method of claim 1 wherein receiving the burst of electrical energy further comprises receiving the burst of electrical energy within a time window of 10 milliseconds or less, and the burst of electrical energy ceasing thereafter. 7. The method of claim 1 wherein rectifying the burst of electrical energy further comprises rectifying by way of a full-wave bridge of Schottky diodes having a capacitor coupled across direct current (DC) outputs of the full-wave bridge. 8. A transceiver system comprising:
an energy harvester configured to produce a burst of electrical energy upon each actuation of the energy harvester, each burst of electrical energy having a duration of 10 milliseconds or less; a rectifier coupled to the energy harvester, the rectifier defining a direct current (DC) output and a return; a capacitor coupled across the DC output and the return; and a transceiver defining a power input coupled directly to the DC output of the rectifier; the transceiver configured to transmit an electromagnetic signal comprising a frame of a plurality of bytes during each burst of electrical energy. 9. The transceiver system of claim 8 wherein the energy harvester is a mechanical switch that moves a permanent magnet with each actuation. 10. The transceiver system of claim 8 wherein the energy harvester is a piezoelectric device configured to produce the burst of electrical energy upon being compressed. 11. The transceiver system of claim 8 wherein the energy harvester is configured to produce 500 micro-Joules or less of energy with each actuation. 12. The transceiver system of claim 8 wherein the energy harvester is configured to produce a peak voltage of 3 Volts or greater during each actuation. 13. The transceiver system of claim 8 wherein the rectifier further comprises a full-wave rectifier comprising four Schotkky diodes. 14. The transceiver system of claim 8 wherein the transceiver is configured to operate during periods of time when a voltage on the power input is between and including 1.0 and 1.6 volts. 15. The transceiver system of claim 8 further comprising a printed circuit board, and wherein the energy harvester, the rectifier, the capacitor, and the transceiver are mechanically and electrically coupled to the printed circuit board. 16. A transceiver module comprising:
a printed circuit board; a rectifier mechanically coupled to the printed circuit board, the rectifier defining alternating current (AC) inputs, a direct current (DC) output, and a return, the rectifier configured to receive at the AC inputs a burst of electrical energy having a duration of 10 milliseconds or less; and a transceiver mechanically coupled to the printed circuit board, the transceiver defining a power input coupled directly to the DC output of the rectifier; the transceiver configured to transmit an electromagnetic signal comprising a frame of a plurality of bytes during the burst of electrical energy. 17. The transceiver module of claim 16 further comprising a capacitor coupled across the DC output and the return. 18. The transceiver module of claim 16 wherein the rectifier is further configured to receive the burst of electrical energy of 500 micro-Joules or less. 19. The transceiver module of claim 16:
wherein the rectifier is configured to receive the burst of electrical energy of between and including 3 Volts and 7 Volts; and wherein the transceiver is configured to operate during periods of time when a voltage on the power input is between and including 1.0 and 1.6 volts. 20. The transceiver system of claim 16 wherein the rectifier further comprises a full-wave rectifier comprising four Schotkky diodes. | Wireless communication system and method powered by an energy harvester. At least some of the example embodiments are methods including: receiving a burst of electrical energy from an energy harvester that produces the burst of electrical energy from mechanical energy, the burst of electrical energy the result of a single actuation of the energy harvester; rectifying the burst of electrical energy to create rectified energy; applying the rectified energy to the transceiver without applying the rectified energy to a switching power converter; and transmitting an electromagnetic switch including a frame of multiple bytes, the transmitting using the rectified energy. Additional embodiments can include a transceiver system including an energy harvester, a rectifier, a capacitor, and a transceiver, where the transceiver is configured to transmit an electromagnetic signal including a frame of a plurality of bytes during each burst of electrical energy.1. A method of operating a transceiver comprising:
receiving a burst of electrical energy from an energy harvester that produces the burst of electrical energy from mechanical energy, the burst of electrical energy the result of a single actuation of the energy harvester; rectifying the burst of electrical energy to create rectified energy; applying the rectified energy to the transceiver without applying the rectified energy to a switching power converter; and transmitting an electromagnetic signal comprising a frame of multiple bytes, the transmitting using the rectified energy. 2. The method of claim 1 wherein receiving the burst of electrical energy further comprises receiving the burst of electrical energy from a mechanical switch configured to produce the burst of electrical energy upon actuation. 3. The method of claim 1 wherein receiving the burst of electrical energy further comprises receiving the burst of electrical energy from a piezoelectric device configured to produce the burst of electrical energy upon being compressed. 4. The method of claim 1 wherein receiving the burst of electrical energy further comprises receiving no more than 500 micro-Joules. 5. The method of claim 4 wherein receiving the burst of electrical energy further comprises receiving the burst of electrical energy within a time window of 10 milliseconds or less, and the burst of electrical energy ceasing thereafter. 6. The method of claim 1 wherein receiving the burst of electrical energy further comprises receiving the burst of electrical energy within a time window of 10 milliseconds or less, and the burst of electrical energy ceasing thereafter. 7. The method of claim 1 wherein rectifying the burst of electrical energy further comprises rectifying by way of a full-wave bridge of Schottky diodes having a capacitor coupled across direct current (DC) outputs of the full-wave bridge. 8. A transceiver system comprising:
an energy harvester configured to produce a burst of electrical energy upon each actuation of the energy harvester, each burst of electrical energy having a duration of 10 milliseconds or less; a rectifier coupled to the energy harvester, the rectifier defining a direct current (DC) output and a return; a capacitor coupled across the DC output and the return; and a transceiver defining a power input coupled directly to the DC output of the rectifier; the transceiver configured to transmit an electromagnetic signal comprising a frame of a plurality of bytes during each burst of electrical energy. 9. The transceiver system of claim 8 wherein the energy harvester is a mechanical switch that moves a permanent magnet with each actuation. 10. The transceiver system of claim 8 wherein the energy harvester is a piezoelectric device configured to produce the burst of electrical energy upon being compressed. 11. The transceiver system of claim 8 wherein the energy harvester is configured to produce 500 micro-Joules or less of energy with each actuation. 12. The transceiver system of claim 8 wherein the energy harvester is configured to produce a peak voltage of 3 Volts or greater during each actuation. 13. The transceiver system of claim 8 wherein the rectifier further comprises a full-wave rectifier comprising four Schotkky diodes. 14. The transceiver system of claim 8 wherein the transceiver is configured to operate during periods of time when a voltage on the power input is between and including 1.0 and 1.6 volts. 15. The transceiver system of claim 8 further comprising a printed circuit board, and wherein the energy harvester, the rectifier, the capacitor, and the transceiver are mechanically and electrically coupled to the printed circuit board. 16. A transceiver module comprising:
a printed circuit board; a rectifier mechanically coupled to the printed circuit board, the rectifier defining alternating current (AC) inputs, a direct current (DC) output, and a return, the rectifier configured to receive at the AC inputs a burst of electrical energy having a duration of 10 milliseconds or less; and a transceiver mechanically coupled to the printed circuit board, the transceiver defining a power input coupled directly to the DC output of the rectifier; the transceiver configured to transmit an electromagnetic signal comprising a frame of a plurality of bytes during the burst of electrical energy. 17. The transceiver module of claim 16 further comprising a capacitor coupled across the DC output and the return. 18. The transceiver module of claim 16 wherein the rectifier is further configured to receive the burst of electrical energy of 500 micro-Joules or less. 19. The transceiver module of claim 16:
wherein the rectifier is configured to receive the burst of electrical energy of between and including 3 Volts and 7 Volts; and wherein the transceiver is configured to operate during periods of time when a voltage on the power input is between and including 1.0 and 1.6 volts. 20. The transceiver system of claim 16 wherein the rectifier further comprises a full-wave rectifier comprising four Schotkky diodes. | 2,800 |
11,979 | 11,979 | 15,546,070 | 2,835 | In one implementation, a system for a memory cooling pad includes a first thermal interface material coupled to a second thermal interface material by a liner material configured to position the first thermal interface material on a first side of a memory unit and to position the second thermal interface material on a second side of the memory unit. | 1. A system for a memory cooling pad, comprising:
a first thermal interface material coupled to a second thermal interface material by a liner material configured to position the first thermal interface material on a first side of a memory unit and to position the second thermal interface material on a second side of the memory unit. 2. The system of claim 1, comprising a space between the first thermal interface material and the second thermal interface material. 3. The system of claim 2, wherein the space is positioned between the first side of the memory unit and the second side of the memory unit. 4. The system of claim 3, wherein the liner material is different than the first thermal interface material and the second thermal interface material. 5. The system of claim 3, wherein the space is between 4 millimeters and 6 millimeters. 6. The system of claim 3, wherein the space is configured to provide an non-interface area. 7. The system of claim 1, wherein the first thermal interface material and the second thermal interface material comprise an exterior side coupled to the liner material and an interior side not coupled to the liner material. 8. The system of claim 7, wherein the interior side of the first thermal interface material and the second thermal interface material comprises a non-adhesive material. 9. A system for a memory cooling pad, comprising:
a first side of a thermal interface material attached to a liner material configured to position a second side of the thermal interface material on to a first side of a memory device and a second side of the memory device. 10. The system of claim 9, wherein a portion of the thermal interface material is removed from the liner material. 11. The system of claim 10, wherein the portion is positioned between the first side of the memory device and the second side of the memory device. 12. The system of claim 10, wherein the portion is an interface between the memory device and a cooling assembly. 13. A system for a memory cooling pad, comprising:
a first side of a thermal interface material attached to a liner material configured to position a second side of the thermal interface material on to a first side of a memory device and a second side of the memory device, wherein a portion of the thermal interface material is removed from the liner material and configured to act as an interface between the memory device and a cooling assembly, wherein the memory cooling pad is configured to be compressed upon installation of the cooling assembly. 14. The system of claim 12, wherein the cooling pad is compressed by comb structures of the cooling assembly. 15. The system of claim 12, wherein the thermal interface material comprises a material that is electrically insulating and thermally conductive. | In one implementation, a system for a memory cooling pad includes a first thermal interface material coupled to a second thermal interface material by a liner material configured to position the first thermal interface material on a first side of a memory unit and to position the second thermal interface material on a second side of the memory unit.1. A system for a memory cooling pad, comprising:
a first thermal interface material coupled to a second thermal interface material by a liner material configured to position the first thermal interface material on a first side of a memory unit and to position the second thermal interface material on a second side of the memory unit. 2. The system of claim 1, comprising a space between the first thermal interface material and the second thermal interface material. 3. The system of claim 2, wherein the space is positioned between the first side of the memory unit and the second side of the memory unit. 4. The system of claim 3, wherein the liner material is different than the first thermal interface material and the second thermal interface material. 5. The system of claim 3, wherein the space is between 4 millimeters and 6 millimeters. 6. The system of claim 3, wherein the space is configured to provide an non-interface area. 7. The system of claim 1, wherein the first thermal interface material and the second thermal interface material comprise an exterior side coupled to the liner material and an interior side not coupled to the liner material. 8. The system of claim 7, wherein the interior side of the first thermal interface material and the second thermal interface material comprises a non-adhesive material. 9. A system for a memory cooling pad, comprising:
a first side of a thermal interface material attached to a liner material configured to position a second side of the thermal interface material on to a first side of a memory device and a second side of the memory device. 10. The system of claim 9, wherein a portion of the thermal interface material is removed from the liner material. 11. The system of claim 10, wherein the portion is positioned between the first side of the memory device and the second side of the memory device. 12. The system of claim 10, wherein the portion is an interface between the memory device and a cooling assembly. 13. A system for a memory cooling pad, comprising:
a first side of a thermal interface material attached to a liner material configured to position a second side of the thermal interface material on to a first side of a memory device and a second side of the memory device, wherein a portion of the thermal interface material is removed from the liner material and configured to act as an interface between the memory device and a cooling assembly, wherein the memory cooling pad is configured to be compressed upon installation of the cooling assembly. 14. The system of claim 12, wherein the cooling pad is compressed by comb structures of the cooling assembly. 15. The system of claim 12, wherein the thermal interface material comprises a material that is electrically insulating and thermally conductive. | 2,800 |
11,980 | 11,980 | 16,104,600 | 2,894 | In an embodiment, an assembly includes an electronic component, a fixing member, a resilient member and a substrate having a first surface. The electronic component includes a heat-generating semiconductor device, a die pad and a plastic housing. The heat-generating semiconductor device is mounted on a first surface of the die pad, and the die pad is at least partially embedded in the plastic housing. The resilient member is engaged under compression between an upper side of the electronic component and a lower surface of the fixing member and the fixing member secures the electronic component to the first surface of the substrate. | 1. An assembly, comprising:
an electronic component comprising:
a heat-generating semiconductor device;
a die pad; and
a plastic housing;
wherein the heat-generating semiconductor device is mounted on a first surface of the die pad and the die pad is at least partially embedded in the plastic housing;
a fixing member; a resilient member; and a substrate having a first surface;
wherein the resilient member is engaged under compression between an upper side of the electronic component and a lower surface of the fixing member, and the fixing member secures the electronic component to the first surface of the substrate. 2. The assembly of claim 1, wherein the electronic component further comprises an aperture and the fixing member is at least partially arranged in the aperture. 3. The assembly of claim 2, wherein the die pad extends from the plastic housing, and wherein the aperture is arranged in the die pad and adjacent the plastic housing. 4. The assembly of claim 2, wherein the fixing member includes a head and pin, wherein the pin is arranged in the aperture and extends through a further aperture in the substrate, and wherein the resilient member is engaged under compression between the upper side of the electronic component and an underside of the head of the pin. 5. The assembly of claim 4, wherein the assembly further comprises a securing member that engages with the fixing member on a second side of the substrate that opposes the first side of the substrate, to secure the electronic component to the first side of the substrate. 6. The assembly of claim 5, wherein the securing member comprises a screw having a threaded portion that engages with an inner threaded portion of the pin, or the securing member mechanically engages the outer surface of the pin. 7. The assembly of claim 1, wherein a second surface of the die pad that opposes the first surface is exposed from the plastic housing or covered by the plastic housing. 8. The assembly of claim 1, wherein the resilient member comprises a helical spring. 9. The assembly of claim 1, wherein the upper side of the electronic component further comprises an indentation for accommodating at least a portion of the resilient member. 10. The assembly of claim 1, wherein the fixing member comprises a clamp mounted on the first side of the substrate. 11. The assembly of claim 1, wherein the force applied to the electronic component by the fixing member and the resilient member is between 0.2 Nm and 2 Nm. 12. The assembly of claim 1, wherein the electronic component has a TO220 or TO247 package outline. 13. A Switched Mode Power Supply comprising the assembly of claim 1. 14. A method for mounting an electronic component to a substrate, the method comprising:
placing an electronic component on a first surface of a substrate, the electronic component comprising a heat-generating semiconductor device, a die pad and a plastic housing, wherein the heat-generating semiconductor device is mounted on a first surface of the die pad and the die pad is at least partially embedded in the plastic housing; placing a resilient member between an upper side of the electronic component and a lower surface of a fixing member; and securing the fixing member to the substrate such that the resilient member is compressed between the upper side of the electronic component and the lower surface of the fixing member, and such that a lower surface of the electronic component is pressed onto the first surface of the substrate to mount the electronic component on the substrate. 15. The method of claim 14, wherein a force of between 0.2 Nm and 2 Nm is applied to the electronic component by securing the fixing member to the substrate. 16. The method of claim 14, wherein a force of between 0.5 Nm and 1 Nm is applied to the electronic component by securing the fixing member to the substrate. 17. The method of claim 14, wherein the electronic component further comprises an aperture and the fixing member is at least partially arranged in the aperture. 18. The method of claim 14, wherein the die pad extends from the plastic housing, and wherein the aperture is arranged in the die pad and adjacent the plastic housing. 19. The method of claim 18, wherein the fixing member includes a head and pin, wherein the pin is arranged in the aperture and extends through a further aperture in the substrate, and wherein the resilient member is engaged under compression between the upper side of the electronic component and an underside of the head of the pin. 20. The method of claim 19, wherein the assembly further comprises a securing member that engages with the fixing member on a second side of the substrate that opposes the first side of the substrate, to secure the electronic component to the first side of the substrate. | In an embodiment, an assembly includes an electronic component, a fixing member, a resilient member and a substrate having a first surface. The electronic component includes a heat-generating semiconductor device, a die pad and a plastic housing. The heat-generating semiconductor device is mounted on a first surface of the die pad, and the die pad is at least partially embedded in the plastic housing. The resilient member is engaged under compression between an upper side of the electronic component and a lower surface of the fixing member and the fixing member secures the electronic component to the first surface of the substrate.1. An assembly, comprising:
an electronic component comprising:
a heat-generating semiconductor device;
a die pad; and
a plastic housing;
wherein the heat-generating semiconductor device is mounted on a first surface of the die pad and the die pad is at least partially embedded in the plastic housing;
a fixing member; a resilient member; and a substrate having a first surface;
wherein the resilient member is engaged under compression between an upper side of the electronic component and a lower surface of the fixing member, and the fixing member secures the electronic component to the first surface of the substrate. 2. The assembly of claim 1, wherein the electronic component further comprises an aperture and the fixing member is at least partially arranged in the aperture. 3. The assembly of claim 2, wherein the die pad extends from the plastic housing, and wherein the aperture is arranged in the die pad and adjacent the plastic housing. 4. The assembly of claim 2, wherein the fixing member includes a head and pin, wherein the pin is arranged in the aperture and extends through a further aperture in the substrate, and wherein the resilient member is engaged under compression between the upper side of the electronic component and an underside of the head of the pin. 5. The assembly of claim 4, wherein the assembly further comprises a securing member that engages with the fixing member on a second side of the substrate that opposes the first side of the substrate, to secure the electronic component to the first side of the substrate. 6. The assembly of claim 5, wherein the securing member comprises a screw having a threaded portion that engages with an inner threaded portion of the pin, or the securing member mechanically engages the outer surface of the pin. 7. The assembly of claim 1, wherein a second surface of the die pad that opposes the first surface is exposed from the plastic housing or covered by the plastic housing. 8. The assembly of claim 1, wherein the resilient member comprises a helical spring. 9. The assembly of claim 1, wherein the upper side of the electronic component further comprises an indentation for accommodating at least a portion of the resilient member. 10. The assembly of claim 1, wherein the fixing member comprises a clamp mounted on the first side of the substrate. 11. The assembly of claim 1, wherein the force applied to the electronic component by the fixing member and the resilient member is between 0.2 Nm and 2 Nm. 12. The assembly of claim 1, wherein the electronic component has a TO220 or TO247 package outline. 13. A Switched Mode Power Supply comprising the assembly of claim 1. 14. A method for mounting an electronic component to a substrate, the method comprising:
placing an electronic component on a first surface of a substrate, the electronic component comprising a heat-generating semiconductor device, a die pad and a plastic housing, wherein the heat-generating semiconductor device is mounted on a first surface of the die pad and the die pad is at least partially embedded in the plastic housing; placing a resilient member between an upper side of the electronic component and a lower surface of a fixing member; and securing the fixing member to the substrate such that the resilient member is compressed between the upper side of the electronic component and the lower surface of the fixing member, and such that a lower surface of the electronic component is pressed onto the first surface of the substrate to mount the electronic component on the substrate. 15. The method of claim 14, wherein a force of between 0.2 Nm and 2 Nm is applied to the electronic component by securing the fixing member to the substrate. 16. The method of claim 14, wherein a force of between 0.5 Nm and 1 Nm is applied to the electronic component by securing the fixing member to the substrate. 17. The method of claim 14, wherein the electronic component further comprises an aperture and the fixing member is at least partially arranged in the aperture. 18. The method of claim 14, wherein the die pad extends from the plastic housing, and wherein the aperture is arranged in the die pad and adjacent the plastic housing. 19. The method of claim 18, wherein the fixing member includes a head and pin, wherein the pin is arranged in the aperture and extends through a further aperture in the substrate, and wherein the resilient member is engaged under compression between the upper side of the electronic component and an underside of the head of the pin. 20. The method of claim 19, wherein the assembly further comprises a securing member that engages with the fixing member on a second side of the substrate that opposes the first side of the substrate, to secure the electronic component to the first side of the substrate. | 2,800 |
11,981 | 11,981 | 15,741,397 | 2,844 | The invention provides a lighting unit, comprising a light source and a light sensor arrangement. An optical feedback path is provided from the light source (or another light source in the same overall system) to the light sensor arrangement. The light source is turned on in response to an external input and is maintained on as a result of the optical feedback path. This lighting unit can be turned on using an signal such as an optical signal which is received from an external source, and then maintained on using optical feedback from the light source itself. This makes it possible to control a lighting unit area such as a wall using an external device such as a torch or laser pointer, without the need for complex electronic protocols. | 1. A lighting unit, comprising:
a light source; a light sensor arrangement; and an optical feedback path from the light source to the light sensor arrangement, wherein the lighting unit is adapted to receive a first external input from a source external to the lighting unit for turning on the light source; wherein the light sensor arrangement is adapted to maintain the light source switched on in response to light output from the light source sensed by the light sensor arrangement through the optical feedback path, wherein an output from the light sensor arrangement directly connects to an input of the light source, so as to directly controlling an on state of the light source without the use of an intermediate processing device. 2. A lighting unit a claimed in claim 1, wherein the light sensor arrangement is adapted to sense the first external input, said first external input being an external light input, and wherein the light sensor arrangement is further adapted:
to turn on the light source in response to the external light input with an intensity which exceeds the ambient light levels or a frequency which is distinguishable from ambient light; or to turn on the light source in response to the external light input with a recognizable pulse pattern. 3. A lighting unit as claimed in claim 1, comprising a further sensor arrangement for sensing the first external input in the form of a non-light input, wherein the further sensor arrangement is adapted to turn on the light source in response to the first external input. 4. A lighting unit as claimed in claim 1, wherein the optical feedback path comprises a diffuser or reflector. 5. A lighting unit as claimed in claim 1, wherein the light sensor arrangement is adapted to turn off the light source in response to a second external input different to the first external input. 6. A lighting unit as claimed in claim 5, wherein the first and second external inputs are optical. 7. A lighting arrangement comprising an array of lighting units according to claim 1, each lighting unit comprising a light source and associated light sensor arrangement. 8. A lighting arrangement as claimed in claim 7, wherein the first external input for the array of lighting units comprises a light pattern projected onto the array of lighting units. 9. A lighting arrangement as claimed in claim 7, comprising a data input adapted to provide a shared data setting for all light sources of the array. 10. A lighting system comprising:
a lighting unit as claimed in claim 1 or a lighting arrangement; and an external controller for providing a light output for reception by the light sensor arrangement for controlling at least the turning on of the light source of the lighting unit or light sources of the lighting arrangement. 11. A system as claimed in claim 10, wherein the external controller comprises a first light source for providing a first light output for turning on the light source or light sources, and a second source for providing a second light output for turning off the lighting source or light sources. 12. A system as claimed in claim 10, further comprising a power switch for interrupting power to the lighting unit or lighting arrangement for turning off the light source or light sources. 13. A method of controlling a lighting unit, comprising:
providing a first external input to the lighting unit; sensing the first external input; turning on a light source of the lighting unit in response to the first external input; and maintaining the light source on in response to sensing, with a light sensor arrangement, the light output from the light source, wherein an output from the light sensor arrangement directly connects to an input of the light source, so as to directly controlling an on state of the light source without using an intermediate processing device. 14. A method as claimed in claim 13, comprising turning on the light source in response to:
an external light input with an intensity which exceeds the ambient light levels; or an external light input with a recognizable pulse pattern or frequency; or a non-light external input. 15. A method as claimed in claim 13, comprising:
turning off the light source in response to: a second external light input different to the first external light input; or a switched interruption of power to the lighting unit; or a non-light external input. | The invention provides a lighting unit, comprising a light source and a light sensor arrangement. An optical feedback path is provided from the light source (or another light source in the same overall system) to the light sensor arrangement. The light source is turned on in response to an external input and is maintained on as a result of the optical feedback path. This lighting unit can be turned on using an signal such as an optical signal which is received from an external source, and then maintained on using optical feedback from the light source itself. This makes it possible to control a lighting unit area such as a wall using an external device such as a torch or laser pointer, without the need for complex electronic protocols.1. A lighting unit, comprising:
a light source; a light sensor arrangement; and an optical feedback path from the light source to the light sensor arrangement, wherein the lighting unit is adapted to receive a first external input from a source external to the lighting unit for turning on the light source; wherein the light sensor arrangement is adapted to maintain the light source switched on in response to light output from the light source sensed by the light sensor arrangement through the optical feedback path, wherein an output from the light sensor arrangement directly connects to an input of the light source, so as to directly controlling an on state of the light source without the use of an intermediate processing device. 2. A lighting unit a claimed in claim 1, wherein the light sensor arrangement is adapted to sense the first external input, said first external input being an external light input, and wherein the light sensor arrangement is further adapted:
to turn on the light source in response to the external light input with an intensity which exceeds the ambient light levels or a frequency which is distinguishable from ambient light; or to turn on the light source in response to the external light input with a recognizable pulse pattern. 3. A lighting unit as claimed in claim 1, comprising a further sensor arrangement for sensing the first external input in the form of a non-light input, wherein the further sensor arrangement is adapted to turn on the light source in response to the first external input. 4. A lighting unit as claimed in claim 1, wherein the optical feedback path comprises a diffuser or reflector. 5. A lighting unit as claimed in claim 1, wherein the light sensor arrangement is adapted to turn off the light source in response to a second external input different to the first external input. 6. A lighting unit as claimed in claim 5, wherein the first and second external inputs are optical. 7. A lighting arrangement comprising an array of lighting units according to claim 1, each lighting unit comprising a light source and associated light sensor arrangement. 8. A lighting arrangement as claimed in claim 7, wherein the first external input for the array of lighting units comprises a light pattern projected onto the array of lighting units. 9. A lighting arrangement as claimed in claim 7, comprising a data input adapted to provide a shared data setting for all light sources of the array. 10. A lighting system comprising:
a lighting unit as claimed in claim 1 or a lighting arrangement; and an external controller for providing a light output for reception by the light sensor arrangement for controlling at least the turning on of the light source of the lighting unit or light sources of the lighting arrangement. 11. A system as claimed in claim 10, wherein the external controller comprises a first light source for providing a first light output for turning on the light source or light sources, and a second source for providing a second light output for turning off the lighting source or light sources. 12. A system as claimed in claim 10, further comprising a power switch for interrupting power to the lighting unit or lighting arrangement for turning off the light source or light sources. 13. A method of controlling a lighting unit, comprising:
providing a first external input to the lighting unit; sensing the first external input; turning on a light source of the lighting unit in response to the first external input; and maintaining the light source on in response to sensing, with a light sensor arrangement, the light output from the light source, wherein an output from the light sensor arrangement directly connects to an input of the light source, so as to directly controlling an on state of the light source without using an intermediate processing device. 14. A method as claimed in claim 13, comprising turning on the light source in response to:
an external light input with an intensity which exceeds the ambient light levels; or an external light input with a recognizable pulse pattern or frequency; or a non-light external input. 15. A method as claimed in claim 13, comprising:
turning off the light source in response to: a second external light input different to the first external light input; or a switched interruption of power to the lighting unit; or a non-light external input. | 2,800 |
11,982 | 11,982 | 15,577,737 | 2,834 | A drive device includes an electric motor and a gear unit that is driven by the electric motor. The electric motor has a laminated stator core which includes stator windings and is accommodated in a stator housing. The stator housing has recesses that are axially uninterrupted, i.e. in particular in the direction of the rotor shaft axis, and the stator housing is surrounded, especially radially surrounded, by a housing of the drive device, in particular a tubular housing and/or a cup-shaped housing, and the housing is set apart from the stator housing, in particular such that an especially circulating airflow is able to be provided within the housing, the recesses in particular guiding the airflow through in the axial direction, and the airflow being returned in the opposite direction in the set-apart region between the stator housing part and the housing. | 1-15. (canceled) 16. A drive device, comprising:
a gear unit; and an electric motor adapted to drive the gear unit, the electric motor including a laminated stator core which has stator windings and is accommodated in a stator housing; wherein the stator housing includes recesses that are axially uninterrupted, the stator housing being surrounded and/or radially surrounded by a housing, a tubular housing, and/or a cup-shaped housing of the drive device, the housing being set apart from the stator housing, such that an airflow and/or a circulating airflow is generatable within the housing, the recesses adapted to guide the airflow through in an axial direction, the airflow returnable in an opposite direction in a set-apart region between the stator housing part and the housing. 17. The drive device according to claim 16, wherein the recesses are axially interrupted in a direction of a rotor shaft axis. 18. The drive device according to claim 16, wherein the stator housing includes a continuous casting component, and a drawing direction extends parallel to the axial direction and/or parallel to a direction of a rotor shaft axis. 19. The drive device according to claim 16, wherein the gear unit has a first housing part and a second housing part connected to each other, the stator housing being connected to and/or screw-connected to the second housing part, and the housing, the tubular housing, and/or the cup-shaped housing of the drive device being connected to and/or screw-connected to the second housing part. 20. The drive device according to claim 16, wherein the drive device is arranged such that the airflow flows from the recesses of the stator housing through individual recesses of the second housing part. 21. The drive device according to claim 20, wherein the individual recesses of the second housing part are at least partially delimited by fins that project from the second housing part. 22. The drive device according to claim 16, wherein the housing is made of a first material and the stator housing is made from a second material, the first material having a greater thermal conductivity than the second material. 23. The drive device according to claim 16, wherein (a) the stator housing includes a coating on a surface facing the housing and or on an external surface, to increase emitted heat output, and/or (b) the housing includes a coating on a surface facing the stator housing and/or on an internal surface, to increase absorbed heat output. 24. The drive device according to claim 16, wherein the airflow is driven convectively and/or solely convectively. 25. The drive device according to claim 16, further comprising at least one fan and/or two fans, adapted to drive the airflow, disposed on a bearing flange of the motor. 26. The drive device according to claim 25, wherein the bearing flange includes a circular base plate section and a separating wall section that is disposed on the base plate section, the separating wall section adapted to separate the airflow from a space region that surrounds a B-side axial end region of a rotor shaft facing away from the gear unit and/or that at least partially surrounds an angle sensor disposed in the B-side axial end region. 27. The drive device according to claim 25, wherein a bearing of a rotor shaft of the motor is accommodated in the bearing flange. 28. The drive device according to claim 26, wherein the separating wall section includes a smaller radial extension in a first peripheral angle direction than in a second peripheral angle direction that differs from the first peripheral angle direction. 29. The drive device according to claim 28, wherein the fan is disposed radially outside the separating wall section, and the fan is set apart from the second peripheral angle direction in the peripheral direction, a peripheral angle section covered by the fan encompassing the first peripheral angle. 30. The drive device according to claim 26, wherein the separating wall section is arranged on an axial side of the base plate section facing away from the gear unit, and/or a projection for axial delimitation of the fan is arranged on the separating wall section. 31. The drive device according to claim 26, wherein the base plate section has at least one and/or two recesses for feedthrough of cables, the stator housing having a coating on a surface facing the housing and/or on an external surface, to increase emitted heat radiation, the base plate section including a central recess adapted to accommodate a stator of an angle sensor. 32. The drive device according to claim 19, wherein the second housing part has pocket-type depressions at a surface along which the airflow flows, so that dirt and/or dust from the airflow is depositable in the pocket-type depressions and/or in air chambers of the second housing part, a connection element and/or a screw connecting the first housing part to the second housing part, and a space region required to operate the connection element using a tool is provided by the depression. | A drive device includes an electric motor and a gear unit that is driven by the electric motor. The electric motor has a laminated stator core which includes stator windings and is accommodated in a stator housing. The stator housing has recesses that are axially uninterrupted, i.e. in particular in the direction of the rotor shaft axis, and the stator housing is surrounded, especially radially surrounded, by a housing of the drive device, in particular a tubular housing and/or a cup-shaped housing, and the housing is set apart from the stator housing, in particular such that an especially circulating airflow is able to be provided within the housing, the recesses in particular guiding the airflow through in the axial direction, and the airflow being returned in the opposite direction in the set-apart region between the stator housing part and the housing.1-15. (canceled) 16. A drive device, comprising:
a gear unit; and an electric motor adapted to drive the gear unit, the electric motor including a laminated stator core which has stator windings and is accommodated in a stator housing; wherein the stator housing includes recesses that are axially uninterrupted, the stator housing being surrounded and/or radially surrounded by a housing, a tubular housing, and/or a cup-shaped housing of the drive device, the housing being set apart from the stator housing, such that an airflow and/or a circulating airflow is generatable within the housing, the recesses adapted to guide the airflow through in an axial direction, the airflow returnable in an opposite direction in a set-apart region between the stator housing part and the housing. 17. The drive device according to claim 16, wherein the recesses are axially interrupted in a direction of a rotor shaft axis. 18. The drive device according to claim 16, wherein the stator housing includes a continuous casting component, and a drawing direction extends parallel to the axial direction and/or parallel to a direction of a rotor shaft axis. 19. The drive device according to claim 16, wherein the gear unit has a first housing part and a second housing part connected to each other, the stator housing being connected to and/or screw-connected to the second housing part, and the housing, the tubular housing, and/or the cup-shaped housing of the drive device being connected to and/or screw-connected to the second housing part. 20. The drive device according to claim 16, wherein the drive device is arranged such that the airflow flows from the recesses of the stator housing through individual recesses of the second housing part. 21. The drive device according to claim 20, wherein the individual recesses of the second housing part are at least partially delimited by fins that project from the second housing part. 22. The drive device according to claim 16, wherein the housing is made of a first material and the stator housing is made from a second material, the first material having a greater thermal conductivity than the second material. 23. The drive device according to claim 16, wherein (a) the stator housing includes a coating on a surface facing the housing and or on an external surface, to increase emitted heat output, and/or (b) the housing includes a coating on a surface facing the stator housing and/or on an internal surface, to increase absorbed heat output. 24. The drive device according to claim 16, wherein the airflow is driven convectively and/or solely convectively. 25. The drive device according to claim 16, further comprising at least one fan and/or two fans, adapted to drive the airflow, disposed on a bearing flange of the motor. 26. The drive device according to claim 25, wherein the bearing flange includes a circular base plate section and a separating wall section that is disposed on the base plate section, the separating wall section adapted to separate the airflow from a space region that surrounds a B-side axial end region of a rotor shaft facing away from the gear unit and/or that at least partially surrounds an angle sensor disposed in the B-side axial end region. 27. The drive device according to claim 25, wherein a bearing of a rotor shaft of the motor is accommodated in the bearing flange. 28. The drive device according to claim 26, wherein the separating wall section includes a smaller radial extension in a first peripheral angle direction than in a second peripheral angle direction that differs from the first peripheral angle direction. 29. The drive device according to claim 28, wherein the fan is disposed radially outside the separating wall section, and the fan is set apart from the second peripheral angle direction in the peripheral direction, a peripheral angle section covered by the fan encompassing the first peripheral angle. 30. The drive device according to claim 26, wherein the separating wall section is arranged on an axial side of the base plate section facing away from the gear unit, and/or a projection for axial delimitation of the fan is arranged on the separating wall section. 31. The drive device according to claim 26, wherein the base plate section has at least one and/or two recesses for feedthrough of cables, the stator housing having a coating on a surface facing the housing and/or on an external surface, to increase emitted heat radiation, the base plate section including a central recess adapted to accommodate a stator of an angle sensor. 32. The drive device according to claim 19, wherein the second housing part has pocket-type depressions at a surface along which the airflow flows, so that dirt and/or dust from the airflow is depositable in the pocket-type depressions and/or in air chambers of the second housing part, a connection element and/or a screw connecting the first housing part to the second housing part, and a space region required to operate the connection element using a tool is provided by the depression. | 2,800 |
11,983 | 11,983 | 15,062,113 | 2,853 | There is described a sheet-fed or web-fed printing press for numbering and varnishing of security documents, including banknotes, comprising: —a numbering group ( 02 ) comprising at least one numbering unit ( 21, 22 ) for numbering printed material in the form of individual sheets or successive portions of a continuous web carrying multiple security imprints; and —a varnishing group ( 03; 03* ) located downstream of the numbering group ( 02 ) for applying varnish onto recto and verso sides of the printed material, the varnishing group ( 03; 03 *) comprising at least a first varnishing unit ( 31 ) disposed above a path of the printed material to apply varnish on the recto side of the printed material and at least a second varnishing unit ( 32 ) disposed below the path of the printed material to apply varnish on the verso side of the printed material. | 1.-21. (canceled) 22. A sheet-fed or web-fed printing press for numbering and varnishing of security documents, including banknotes, comprising:
a numbering group comprising at least one numbering unit for numbering printed material in the form of individual sheets or successive portions of a continuous web carrying multiple security imprints; and a varnishing group located downstream of the numbering group for applying varnish onto recto and verso sides of the printed material, the varnishing group comprising at least a first varnishing unit disposed above a path of the printed material to apply varnish on the recto side of the printed material and at least a second varnishing unit disposed below the path of the printed material to apply varnish on the verso side of the printed material. 23. The printing press as defined in claim 22, wherein the numbering group and varnishing group are constructed as modular groups that can easily be decoupled from one another. 24. The printing press as defined in claim 22, wherein numbering is carried out in the numbering group on a recto side of the printed material and wherein the numbered printed material is transferred directly to the varnishing group for varnishing of the recto side of the printed material by the at least first varnishing unit and, immediately after varnishing of the recto side, for varnishing of the verso side of the printed material by the at least second varnishing unit. 25. The printing press as defined in claim 24, wherein the numbering group is adapted to number the printed material on the recto side thereof with at least one ink selected from the group consisting of oxidative solvent-based inks and UV-curable inks. 26. The printing press as defined in claim 24, wherein the recto side of the printed material is not dried before being varnished by the at least first varnishing unit. 27. The printing press as defined in claim 22, wherein the varnishing group comprises:
a first cylinder or drum located below the path of the printed material and cooperating with the at least first varnishing unit which is disposed above the path of the printed material; and a second cylinder or drum located above the path of the printed material and cooperating with the at least second varnishing unit which is disposed below the path of the printed material, wherein the second cylinder or drum being located immediately after the first cylinder or drum to ensure direct transfer of the printed material from the first cylinder or drum to the second cylinder or drum. 28. The printing press as defined in claim 27, wherein the first and second cylinders or drums are two-segment cylinders or drums. 29. The printing press as defined in claim 27, further comprising at least a first drying unit cooperating with the first cylinder or drum for drying the recto side of the printed material following varnishing by the at least first varnishing unit prior to transfer of the printed material to the second cylinder or drum and at least a second drying unit cooperating with the second cylinder or drum for drying the verso side of the printed material following varnishing by the at least second varnishing unit. 30. The printing press as defined in claim 29, wherein the at least first and second varnishing units are designed to apply UV-curable varnish on the recto and verso sides of the printed material and wherein the first and second drying units are UV-curing units. 31. The printing press as defined in claim 22, wherein the at least first and second varnishing units are flexographic varnishing units each comprising an anilox roller inked by an associated ink chamber, which anilox roller cooperates with a flexographic forme cylinder. 32. The printing press as defined in claim 22, further comprising an inspection group placed upstream of the numbering group for carrying out inspection of the printed material and determining occurrence of defects affecting the quality of the printed material prior to numbering and varnishing. 33. The printing press as defined in claim 22, further comprising an intermediate UV-curing unit for curing the printed material, which intermediate UV-curing unit is located along the path of the printed material between the numbering group and varnishing group. 34. The printing press as defined in claim 22, wherein the printing press is configured such that the at least first varnishing unit is accessible by an operator from a first working space located upstream of the varnishing group, between the numbering group and the varnishing group, and such that the at least second varnishing unit is accessible by an operator from a second working space located downstream of the varnishing group. | There is described a sheet-fed or web-fed printing press for numbering and varnishing of security documents, including banknotes, comprising: —a numbering group ( 02 ) comprising at least one numbering unit ( 21, 22 ) for numbering printed material in the form of individual sheets or successive portions of a continuous web carrying multiple security imprints; and —a varnishing group ( 03; 03* ) located downstream of the numbering group ( 02 ) for applying varnish onto recto and verso sides of the printed material, the varnishing group ( 03; 03 *) comprising at least a first varnishing unit ( 31 ) disposed above a path of the printed material to apply varnish on the recto side of the printed material and at least a second varnishing unit ( 32 ) disposed below the path of the printed material to apply varnish on the verso side of the printed material.1.-21. (canceled) 22. A sheet-fed or web-fed printing press for numbering and varnishing of security documents, including banknotes, comprising:
a numbering group comprising at least one numbering unit for numbering printed material in the form of individual sheets or successive portions of a continuous web carrying multiple security imprints; and a varnishing group located downstream of the numbering group for applying varnish onto recto and verso sides of the printed material, the varnishing group comprising at least a first varnishing unit disposed above a path of the printed material to apply varnish on the recto side of the printed material and at least a second varnishing unit disposed below the path of the printed material to apply varnish on the verso side of the printed material. 23. The printing press as defined in claim 22, wherein the numbering group and varnishing group are constructed as modular groups that can easily be decoupled from one another. 24. The printing press as defined in claim 22, wherein numbering is carried out in the numbering group on a recto side of the printed material and wherein the numbered printed material is transferred directly to the varnishing group for varnishing of the recto side of the printed material by the at least first varnishing unit and, immediately after varnishing of the recto side, for varnishing of the verso side of the printed material by the at least second varnishing unit. 25. The printing press as defined in claim 24, wherein the numbering group is adapted to number the printed material on the recto side thereof with at least one ink selected from the group consisting of oxidative solvent-based inks and UV-curable inks. 26. The printing press as defined in claim 24, wherein the recto side of the printed material is not dried before being varnished by the at least first varnishing unit. 27. The printing press as defined in claim 22, wherein the varnishing group comprises:
a first cylinder or drum located below the path of the printed material and cooperating with the at least first varnishing unit which is disposed above the path of the printed material; and a second cylinder or drum located above the path of the printed material and cooperating with the at least second varnishing unit which is disposed below the path of the printed material, wherein the second cylinder or drum being located immediately after the first cylinder or drum to ensure direct transfer of the printed material from the first cylinder or drum to the second cylinder or drum. 28. The printing press as defined in claim 27, wherein the first and second cylinders or drums are two-segment cylinders or drums. 29. The printing press as defined in claim 27, further comprising at least a first drying unit cooperating with the first cylinder or drum for drying the recto side of the printed material following varnishing by the at least first varnishing unit prior to transfer of the printed material to the second cylinder or drum and at least a second drying unit cooperating with the second cylinder or drum for drying the verso side of the printed material following varnishing by the at least second varnishing unit. 30. The printing press as defined in claim 29, wherein the at least first and second varnishing units are designed to apply UV-curable varnish on the recto and verso sides of the printed material and wherein the first and second drying units are UV-curing units. 31. The printing press as defined in claim 22, wherein the at least first and second varnishing units are flexographic varnishing units each comprising an anilox roller inked by an associated ink chamber, which anilox roller cooperates with a flexographic forme cylinder. 32. The printing press as defined in claim 22, further comprising an inspection group placed upstream of the numbering group for carrying out inspection of the printed material and determining occurrence of defects affecting the quality of the printed material prior to numbering and varnishing. 33. The printing press as defined in claim 22, further comprising an intermediate UV-curing unit for curing the printed material, which intermediate UV-curing unit is located along the path of the printed material between the numbering group and varnishing group. 34. The printing press as defined in claim 22, wherein the printing press is configured such that the at least first varnishing unit is accessible by an operator from a first working space located upstream of the varnishing group, between the numbering group and the varnishing group, and such that the at least second varnishing unit is accessible by an operator from a second working space located downstream of the varnishing group. | 2,800 |
11,984 | 11,984 | 15,945,649 | 2,848 | In one embodiment, a semiconductor package may be formed having a first side and a second side that is substantially opposite to the first side. An embodiment may include forming an attachment clip extending substantially laterally between the first and second sides wherein the attachment clip is positioned near a distal end of the first and second sides. An embodiment may also include forming the attachment clip to have a flexible main portion that can bend away from a plane of the main portion toward a bottom side of the semiconductor package. | 1-12. (canceled) 13. A method of forming a semiconductor package comprising:
forming a first side of the package substantially parallel to a second side of the package; forming a first attachment clip extending between the first and second sides and positioned near a first end of the first and second sides wherein the first attachment clip is attached to the first and second sides, the first attachment clip having a first opening through the first attachment clip; forming a second attachment clip extending between the first and second sides and positioned near an opposite end of the first and second sides wherein the second attachment clip is attached to the first and second sides, the second attachment clip having a second opening through the second attachment clip; and forming a first loop in the first attachment clip and forming a second loop in the second attachment clip wherein the first loop is a portion of the first attachment clip that extends upward away from a plane of the first attachment clip and returns to substantially the plane of first attachment clip wherein the first loop is positioned between the first opening and the first side and the second loop is a portion of the second attachment clip that extends upward away from a plane of the second attachment clip and returns to substantially the plane of the second attachment clip wherein the second loop is positioned between the second opening and the first side. 14. The method of claim 13 including forming the first loop between the first opening of the first attachment clip and a first distal end of the first attachment clip. 15. The method of claim 14 further including forming a third loop between the first opening of the first attachment clip and a second distal end of the first attachment clip. 16. The method of claim 13 including forming the second loop between the second opening of the second attachment clip and a first distal end of the second attachment clip. 17. The method of claim 16 further including forming the first attachment clip extending between a first projection of the first side and a first projection of the second side, and forming the second attachment clip extending between a second projection of the first side and a second projection of the second side. 18. A method of forming a semiconductor package comprising:
forming a package having a first side and a second side that is substantially opposite to the first side; forming an attachment clip extending substantially laterally between the first and second sides wherein the attachment clip is positioned near a distal end of the first and second sides; forming the attachment clip to have a first end, a second end, and a flexible main portion that can bend away from a plane of the main portion toward a bottom side of the semiconductor package including forming material of the first side encasing the first end and forming material of the second side encasing the second end. 19. The method of claim 18 including forming a loop in the flexible main portion of the attachment clip wherein the loop is a first portion of the flexible main portion that is formed to extend away from the flexible main portion and away from the bottom of the package and to return to substantially the main portion. 20. The method of claim 18 including forming an opening in the loop wherein the opening has a length that is greater than a width of the opening. 21. A method of making a semiconductor package comprising:
providing a first attachment clip having a first end and a second end and a main portion that extends between the first and second ends; forming a housing of the semiconductor package including forming a first side, a second side opposite the first side, a third side extending at an angle from the first side toward the second side, a first projection extending from the first side a first distance past the third side, and a second projection portion extending from the second side a second distance past the third side, including forming the first end and the second end of the attachment clip imbedded within the respective first projection and second projection during the step of forming the respective first projection and second projection. 22. The method of claim 21 further including forming, during the step of forming the housing, a second attachment clip having a first end extending into and attached to a third projection extending from the first side of the housing, and the second attachment clip having a second end extending into and attached to a fourth projection extending from the second side of the housing, the second attachment clip having a main portion that extends between the first and second ends of the second attachment clip. 23. The method of claim 21 including forming a loop in the main portion of the first attachment clip wherein the loop is a first portion of the main portion that is formed to extend upwardly from the main portion and out of a plane of the main portion, and return back to substantially the plane of the main portion. 24. The method of 21 including forming the first projection with a first bottom surface and forming the second projection with a second bottom surface wherein the first end of the first attachment clip is attached substantially near the first bottom surface and wherein the second end of the first attachment clip is attached substantially near the second bottom surface. 25. The method of claim 21 including providing the first attachment clip having an opening through a central region of the main portion. 26. The method of claim 21 further including forming material of the first projection encasing the first end of the attachment clip and forming material of the second projection encasing the second end of the attachment clip. 27. The method of claim 21 wherein providing the first attachment clip includes providing the first attachment clip having a first loop having a first loop portion extending upward from a plane of the main portion wherein the first loop portion is positioned between a center of the main portion and one of the first projection or the second projection. 28. The method of claim 27 including providing the first loop having a second loop portion extending upward from distal to the central region of the main portion and out of a plane of the main portion toward and intersecting with the first loop portion. 29. The method of claim 27 including providing a second loop portion of the first loop that returns to substantially the plane of the main portion. 30. The method of claim 21 wherein forming the housing of the semiconductor package includes forming the first end of the first attachment clip a first distance away from a first bottom surface of the first projection and forming the second end of the first attachment clip a second distance away from a second bottom surface of the second projection. 30. The method of claim 30 including forming the first distance substantially equal to the second distance. 31. The method of claim 30 including forming the first distance and the second distance to be substantially equal and approximately in a plane of the first bottom surface. | In one embodiment, a semiconductor package may be formed having a first side and a second side that is substantially opposite to the first side. An embodiment may include forming an attachment clip extending substantially laterally between the first and second sides wherein the attachment clip is positioned near a distal end of the first and second sides. An embodiment may also include forming the attachment clip to have a flexible main portion that can bend away from a plane of the main portion toward a bottom side of the semiconductor package.1-12. (canceled) 13. A method of forming a semiconductor package comprising:
forming a first side of the package substantially parallel to a second side of the package; forming a first attachment clip extending between the first and second sides and positioned near a first end of the first and second sides wherein the first attachment clip is attached to the first and second sides, the first attachment clip having a first opening through the first attachment clip; forming a second attachment clip extending between the first and second sides and positioned near an opposite end of the first and second sides wherein the second attachment clip is attached to the first and second sides, the second attachment clip having a second opening through the second attachment clip; and forming a first loop in the first attachment clip and forming a second loop in the second attachment clip wherein the first loop is a portion of the first attachment clip that extends upward away from a plane of the first attachment clip and returns to substantially the plane of first attachment clip wherein the first loop is positioned between the first opening and the first side and the second loop is a portion of the second attachment clip that extends upward away from a plane of the second attachment clip and returns to substantially the plane of the second attachment clip wherein the second loop is positioned between the second opening and the first side. 14. The method of claim 13 including forming the first loop between the first opening of the first attachment clip and a first distal end of the first attachment clip. 15. The method of claim 14 further including forming a third loop between the first opening of the first attachment clip and a second distal end of the first attachment clip. 16. The method of claim 13 including forming the second loop between the second opening of the second attachment clip and a first distal end of the second attachment clip. 17. The method of claim 16 further including forming the first attachment clip extending between a first projection of the first side and a first projection of the second side, and forming the second attachment clip extending between a second projection of the first side and a second projection of the second side. 18. A method of forming a semiconductor package comprising:
forming a package having a first side and a second side that is substantially opposite to the first side; forming an attachment clip extending substantially laterally between the first and second sides wherein the attachment clip is positioned near a distal end of the first and second sides; forming the attachment clip to have a first end, a second end, and a flexible main portion that can bend away from a plane of the main portion toward a bottom side of the semiconductor package including forming material of the first side encasing the first end and forming material of the second side encasing the second end. 19. The method of claim 18 including forming a loop in the flexible main portion of the attachment clip wherein the loop is a first portion of the flexible main portion that is formed to extend away from the flexible main portion and away from the bottom of the package and to return to substantially the main portion. 20. The method of claim 18 including forming an opening in the loop wherein the opening has a length that is greater than a width of the opening. 21. A method of making a semiconductor package comprising:
providing a first attachment clip having a first end and a second end and a main portion that extends between the first and second ends; forming a housing of the semiconductor package including forming a first side, a second side opposite the first side, a third side extending at an angle from the first side toward the second side, a first projection extending from the first side a first distance past the third side, and a second projection portion extending from the second side a second distance past the third side, including forming the first end and the second end of the attachment clip imbedded within the respective first projection and second projection during the step of forming the respective first projection and second projection. 22. The method of claim 21 further including forming, during the step of forming the housing, a second attachment clip having a first end extending into and attached to a third projection extending from the first side of the housing, and the second attachment clip having a second end extending into and attached to a fourth projection extending from the second side of the housing, the second attachment clip having a main portion that extends between the first and second ends of the second attachment clip. 23. The method of claim 21 including forming a loop in the main portion of the first attachment clip wherein the loop is a first portion of the main portion that is formed to extend upwardly from the main portion and out of a plane of the main portion, and return back to substantially the plane of the main portion. 24. The method of 21 including forming the first projection with a first bottom surface and forming the second projection with a second bottom surface wherein the first end of the first attachment clip is attached substantially near the first bottom surface and wherein the second end of the first attachment clip is attached substantially near the second bottom surface. 25. The method of claim 21 including providing the first attachment clip having an opening through a central region of the main portion. 26. The method of claim 21 further including forming material of the first projection encasing the first end of the attachment clip and forming material of the second projection encasing the second end of the attachment clip. 27. The method of claim 21 wherein providing the first attachment clip includes providing the first attachment clip having a first loop having a first loop portion extending upward from a plane of the main portion wherein the first loop portion is positioned between a center of the main portion and one of the first projection or the second projection. 28. The method of claim 27 including providing the first loop having a second loop portion extending upward from distal to the central region of the main portion and out of a plane of the main portion toward and intersecting with the first loop portion. 29. The method of claim 27 including providing a second loop portion of the first loop that returns to substantially the plane of the main portion. 30. The method of claim 21 wherein forming the housing of the semiconductor package includes forming the first end of the first attachment clip a first distance away from a first bottom surface of the first projection and forming the second end of the first attachment clip a second distance away from a second bottom surface of the second projection. 30. The method of claim 30 including forming the first distance substantially equal to the second distance. 31. The method of claim 30 including forming the first distance and the second distance to be substantially equal and approximately in a plane of the first bottom surface. | 2,800 |
11,985 | 11,985 | 15,339,114 | 2,856 | Methods that provide wrinkle characterization and performance prediction for wrinkled composite structures using automated structural analysis. In accordance with some embodiments, the method combines the use of B-scan ultrasound data, automated optical measurement of wrinkles and geometry of cross-sections, and finite element analysis of wrinkled composite structure to provide the ability to assess the actual significance of a detected wrinkle relative to the intended performance of the structure. The disclosed method uses an ultrasonic inspection system that has been calibrated by correlating ultrasonic B-scan data acquired from reference standards with measurements of optical cross sections (e.g., micrographs) of those reference standards. | 1. A method for calibrating an ultrasonic inspection system, comprising:
(a) forming a multiplicity of reference standards made of composite material, each reference standard having at least one wrinkle; (b) collecting ultrasonic B-scan data from the multiplicity of reference standards using an ultrasonic inspection system; (c) cutting the reference standards to expose cross sections; (d) imaging the exposed cross sections to produce optical cross sections; (e) measuring features of the at least one wrinkle of each reference standard which appear in the optical cross sections to acquire optical cross-section measurement data; and (f) correlating the ultrasonic B-scan data with the optical cross-section measurement data. 2. The method as recited in claim 1, wherein the optical cross-section measurement data comprises data representing wavelengths and maximum depths of wrinkles in respective reference standards of the multiplicity of reference standards. 3. The method as recited in claim 2, wherein the optical cross-section measurement data further comprises data representing thicknesses of the respective reference standards. 4. The method as recited in claim 3, wherein step (f) comprises correlating time-of-flight measurements with material depths. 5. The method as recited in claim 4, further comprising selecting time and depth axes ranges and time-gate settings for a B-scan window based on results of step (f), including the correlating of the time-of-flight measurements with the material depths. 6. An ultrasonic imaging system having a B-scanning mode in which time and depth axes ranges and time-gate settings for a B-scan window are based on a correlation of ultrasonic B-scan data with optical cross-section measurement data. 7. The ultrasonic imaging system as recited in claim 6, wherein the optical cross-section measurement data comprises data representing wavelengths and maximum depths of wrinkles in respective reference standards. 8. The ultrasonic imaging system as recited in claim 7, wherein the optical cross-section measurement data further comprises data representing thicknesses of the respective reference standards. 9. A method for non-destructive inspection of composite structures, comprising:
(a) calibrating an ultrasonic inspection system based on correlation of ultrasonic B-scan data and optical cross-section measurement data acquired from reference standards made of composite material, each reference standard having at least one wrinkle; (b) collecting non-destructive inspection data from a part made of composite material using the ultrasonic inspection system after completion of step (a); (c) detecting the presence of a wrinkle in the part based on the non-destructive inspection data collected in step (b); (d) collecting ultrasonic B-scan data from the part using the ultrasonic inspection system; and (e) measuring dimensions of the wrinkle in the part based on the ultrasonic B-scan data collected in step (d). 10. The method as recited in claim 9, wherein the non-destructive inspection data is collected in step (b) using at least one of the following: an ultrasound technique, infrared thermography, or an X-ray backscatter technique. 11. The method as recited in claim 9, further comprising generating a structural model of the part and performing a structural analysis of the structural model. 12. The method as recited in claim 11, further comprising determining whether the part should be rejected or not based on results of the structural analysis. 13. The method as recited in claim 11, wherein the structural model is a finite element model and the structural analysis is a finite element model analysis. 14. A method for non-destructive inspection of composite structures, comprising:
(a) calibrating an ultrasonic inspection system based on correlation of ultrasonic B-scan data and optical cross-section measurement data acquired from reference standards made of composite material, each reference standard having at least one wrinkle; (b) collecting ultrasonic B-scan data from a part made of composite material using the ultrasonic inspection system after completion of step (a); (c) detecting the presence of a wrinkle in the part based on the ultrasonic B-scan data collected in step (b); and (d) measuring dimensions of the wrinkle in the part based on the ultrasonic B-scan data collected in step (b). 15. The method as recited in claim 14, further comprising generating a structural model of the part and performing a structural analysis of the structural model. 16. The method as recited in claim 15, further comprising determining whether the part should be rejected or not based on results of the structural analysis. 17. The method as recited in claim 15, wherein the structural model is a finite element model and the structural analysis is a finite element model analysis. 18. A method for predicting performance of a wrinkled composite structure, comprising:
(a) calibrating an ultrasonic inspection system based on correlation of ultrasonic B-scan data and optical cross-section measurement data acquired from reference standards made of composite material, each reference standard having at least one wrinkle; (b) collecting ultrasonic B-scan data from a wrinkled composite structure using the ultrasonic inspection system after completion of step (a); (c) measuring dimensions of a wrinkle in the wrinkled composite structure based on the ultrasonic B-scan data collected in step (b) to obtain wrinkle feature measurements; (d) generating a structural model of the wrinkled composite structure based on the wrinkle feature measurements obtained in step (c); and (e) performing a structural analysis of the structural model. 19. The method as recited in claim 18, further comprising determining whether the wrinkled composite structure should be rejected or not based on results of the structural analysis. 20. The method as recited in claim 18, wherein the structural model is a finite element model and the structural analysis is a finite element model analysis. | Methods that provide wrinkle characterization and performance prediction for wrinkled composite structures using automated structural analysis. In accordance with some embodiments, the method combines the use of B-scan ultrasound data, automated optical measurement of wrinkles and geometry of cross-sections, and finite element analysis of wrinkled composite structure to provide the ability to assess the actual significance of a detected wrinkle relative to the intended performance of the structure. The disclosed method uses an ultrasonic inspection system that has been calibrated by correlating ultrasonic B-scan data acquired from reference standards with measurements of optical cross sections (e.g., micrographs) of those reference standards.1. A method for calibrating an ultrasonic inspection system, comprising:
(a) forming a multiplicity of reference standards made of composite material, each reference standard having at least one wrinkle; (b) collecting ultrasonic B-scan data from the multiplicity of reference standards using an ultrasonic inspection system; (c) cutting the reference standards to expose cross sections; (d) imaging the exposed cross sections to produce optical cross sections; (e) measuring features of the at least one wrinkle of each reference standard which appear in the optical cross sections to acquire optical cross-section measurement data; and (f) correlating the ultrasonic B-scan data with the optical cross-section measurement data. 2. The method as recited in claim 1, wherein the optical cross-section measurement data comprises data representing wavelengths and maximum depths of wrinkles in respective reference standards of the multiplicity of reference standards. 3. The method as recited in claim 2, wherein the optical cross-section measurement data further comprises data representing thicknesses of the respective reference standards. 4. The method as recited in claim 3, wherein step (f) comprises correlating time-of-flight measurements with material depths. 5. The method as recited in claim 4, further comprising selecting time and depth axes ranges and time-gate settings for a B-scan window based on results of step (f), including the correlating of the time-of-flight measurements with the material depths. 6. An ultrasonic imaging system having a B-scanning mode in which time and depth axes ranges and time-gate settings for a B-scan window are based on a correlation of ultrasonic B-scan data with optical cross-section measurement data. 7. The ultrasonic imaging system as recited in claim 6, wherein the optical cross-section measurement data comprises data representing wavelengths and maximum depths of wrinkles in respective reference standards. 8. The ultrasonic imaging system as recited in claim 7, wherein the optical cross-section measurement data further comprises data representing thicknesses of the respective reference standards. 9. A method for non-destructive inspection of composite structures, comprising:
(a) calibrating an ultrasonic inspection system based on correlation of ultrasonic B-scan data and optical cross-section measurement data acquired from reference standards made of composite material, each reference standard having at least one wrinkle; (b) collecting non-destructive inspection data from a part made of composite material using the ultrasonic inspection system after completion of step (a); (c) detecting the presence of a wrinkle in the part based on the non-destructive inspection data collected in step (b); (d) collecting ultrasonic B-scan data from the part using the ultrasonic inspection system; and (e) measuring dimensions of the wrinkle in the part based on the ultrasonic B-scan data collected in step (d). 10. The method as recited in claim 9, wherein the non-destructive inspection data is collected in step (b) using at least one of the following: an ultrasound technique, infrared thermography, or an X-ray backscatter technique. 11. The method as recited in claim 9, further comprising generating a structural model of the part and performing a structural analysis of the structural model. 12. The method as recited in claim 11, further comprising determining whether the part should be rejected or not based on results of the structural analysis. 13. The method as recited in claim 11, wherein the structural model is a finite element model and the structural analysis is a finite element model analysis. 14. A method for non-destructive inspection of composite structures, comprising:
(a) calibrating an ultrasonic inspection system based on correlation of ultrasonic B-scan data and optical cross-section measurement data acquired from reference standards made of composite material, each reference standard having at least one wrinkle; (b) collecting ultrasonic B-scan data from a part made of composite material using the ultrasonic inspection system after completion of step (a); (c) detecting the presence of a wrinkle in the part based on the ultrasonic B-scan data collected in step (b); and (d) measuring dimensions of the wrinkle in the part based on the ultrasonic B-scan data collected in step (b). 15. The method as recited in claim 14, further comprising generating a structural model of the part and performing a structural analysis of the structural model. 16. The method as recited in claim 15, further comprising determining whether the part should be rejected or not based on results of the structural analysis. 17. The method as recited in claim 15, wherein the structural model is a finite element model and the structural analysis is a finite element model analysis. 18. A method for predicting performance of a wrinkled composite structure, comprising:
(a) calibrating an ultrasonic inspection system based on correlation of ultrasonic B-scan data and optical cross-section measurement data acquired from reference standards made of composite material, each reference standard having at least one wrinkle; (b) collecting ultrasonic B-scan data from a wrinkled composite structure using the ultrasonic inspection system after completion of step (a); (c) measuring dimensions of a wrinkle in the wrinkled composite structure based on the ultrasonic B-scan data collected in step (b) to obtain wrinkle feature measurements; (d) generating a structural model of the wrinkled composite structure based on the wrinkle feature measurements obtained in step (c); and (e) performing a structural analysis of the structural model. 19. The method as recited in claim 18, further comprising determining whether the wrinkled composite structure should be rejected or not based on results of the structural analysis. 20. The method as recited in claim 18, wherein the structural model is a finite element model and the structural analysis is a finite element model analysis. | 2,800 |
11,986 | 11,986 | 16,107,942 | 2,813 | A system for reconstructing wafer maps of semiconductor wafers includes: a processor; and memory having instructions stored thereon that, when executed by the processor, cause the processor to: receive test data of a wafer at sparse sampling locations of the wafer, the sparse sampling locations being selected based on a probing mask; and compute a reconstructed wafer map by performing compressed sensing with Zernike polynomials on the test data at sparse locations of the wafer. | 1. A system for reconstructing wafer maps of semiconductor wafers, comprising:
a processor; and memory having instructions stored thereon that, when executed by the processor, cause the processor to:
receive test data of a wafer at sparse sampling locations of the wafer, the sparse sampling locations being selected based on a probing mask; and
compute a reconstructed wafer map by performing compressed sensing with Zernike polynomials on the test data at sparse locations of the wafer. 2. The system of claim 1, wherein the sparse sampling locations of the probing mask are randomly selected. 3. The system of claim 1, wherein the sparse sampling locations of the probing mask are generated by:
receiving a training set of ground truth wafer maps; setting a probing mask based on an initial set of sparse sampling locations; selecting samples from the training set of ground truth wafer maps based on the probing mask; applying a genetic algorithm to compute a customized probing mask, the genetic algorithm iteratively, over a plurality of generations:
computing reconstructed wafer maps using compressed sensing based on the test data taken from the sparse sampling locations;
scoring the reconstructed wafer maps against the training set of ground truth wafer maps;
updating the sparse sampling locations of the probing mask in accordance with the scores; and
returning the updated sparse sampling locations of the probing mask from the genetic algorithm when a threshold error rate is satisfied or when the plurality of generations reaches a generation limit. 4. The system of claim 1, wherein the memory further stores instructions that, when executed by the processor, cause the processor to supply the reconstructed wafer map reconstructed by compressed sensing to a first convolutional neural network, the first convolutional neural network being configured to update the reconstructed wafer map. 5. The system of claim 4, wherein the first convolutional neural network is trained by:
receiving a training set of ground truth wafer maps; selecting samples from the training set of ground truth wafer maps based on the probing mask; computing training reconstructed wafer maps from the selected samples from the training set of ground truth wafer maps; and applying backpropagation to train the first convolutional neural network to compute the training set of ground truth wafer maps from the training reconstructed wafer maps. 6. The system of claim 1, wherein the memory further stores instructions that, when executed by the processor, cause the processor to classify the reconstructed wafer map with one of a plurality of labels using a classifier, and
wherein the classifier is trained using:
a training set of ground truth wafer maps; and
a plurality of labels of the training set of ground truth wafer maps, the plurality of labels being computed by applying an anomaly detection technique to the training set of ground truth wafer maps to identify one or more classes of wafers, the classes of wafers comprising anomalous wafers and non-anomalous wafers. 7. The system of claim 6, wherein the anomaly detection technique includes at least one of principal component analysis or biclustering. 8. The system of claim 6, wherein the memory further stores instructions that, when executed by the processor, cause the processor to supply a plurality of Zernike polynomial coefficients corresponding to the reconstructed wafer map to the classifier, and
wherein the classifier is trained by:
selecting samples from the training set of ground truth wafer maps based on the probing mask;
computing training reconstructed wafer maps from the selected samples from the training set of ground truth wafer maps; and
training the classifier to predict the plurality of labels based on a plurality of training Zernike polynomial coefficients from the training reconstructed wafer maps. 9. The system of claim 6, wherein the memory further stores instructions that, when executed by the processor, cause the processor to:
supply the reconstructed wafer map to a feature extractor to compute a feature map; and supply the feature map to a second trained classifier to classify the reconstructed wafer map with one of the plurality of labels, wherein the feature extractor is a second convolutional neural network, the second convolutional neural network being trained by training the classifier to predict the plurality of labels based on the training set of ground truth wafer maps. 10. The system of claim 1, wherein the system is configured to provide feedback to a run-to-run controller of a semiconductor fabrication process based on the reconstructed wafer map. 11. A method for reconstructing wafer maps of semiconductor wafers, comprising:
receiving, by a processor, test data of a wafer at sparse sampling locations of the wafer, the sparse sampling locations being selected based on a probing mask; and computing, by the processor, a reconstructed wafer map by performing compressed sensing with Zernike polynomials on the test data at sparse locations of the wafer. 12. The method of claim 11, wherein the sparse sampling locations of the probing mask are randomly selected. 13. The method of claim 11, wherein the sparse sampling locations of the probing mask are generated by:
receiving a training set of ground truth wafer maps; setting a probing mask based on an initial set of sparse sampling locations; selecting samples from the training set of ground truth wafer maps based on the probing mask; applying a genetic algorithm to compute a customized probing mask, the genetic algorithm iteratively, over a plurality of generations:
computing reconstructed wafer maps using compressed sensing based on the test data taken from the sparse sampling locations;
scoring the reconstructed wafer maps against the training set of ground truth wafer maps;
updating the sparse sampling locations of the probing mask in accordance with the scores; and
returning the updated sparse sampling locations of the probing mask from the genetic algorithm when a threshold error rate is satisfied or when the plurality of generations reaches a generation limit. 14. The method of claim 11, further comprising supplying the reconstructed wafer map reconstructed by compressed sensing to a first convolutional neural network, the first convolutional neural network being configured to update the reconstructed wafer map. 15. The method of claim 14, wherein the first convolutional neural network is trained by:
receiving a training set of ground truth wafer maps; selecting samples from the training set of ground truth wafer maps based on the probing mask; computing training reconstructed wafer maps from the selected samples from the training set of ground truth wafer maps; and applying backpropagation to train the first convolutional neural network to compute the training set of ground truth wafer maps from the training reconstructed wafer maps. 16. The method of claim 11, further comprising classifying the reconstructed wafer map with one of a plurality of labels using a classifier,
wherein the classifier is trained using:
a training set of ground truth wafer maps; and
a plurality of labels of the training set of ground truth wafer maps, the plurality of labels being computed by applying an anomaly detection technique to the training set of ground truth wafer maps to identify one or more classes of wafers, the classes of wafers comprising anomalous wafers and non-anomalous wafers. 17. The method of claim 16, wherein the anomaly detection technique includes at least one of principal component analysis or biclustering. 18. The method of claim 16, further comprising supplying a plurality of Zernike polynomial coefficients corresponding to the reconstructed wafer map to the classifier,
wherein the classifier is trained by:
selecting samples from the training set of ground truth wafer maps based on the probing mask;
computing training reconstructed wafer maps from the selected samples from the training set of ground truth wafer maps; and
training the classifier to predict the plurality of labels based on a plurality of training Zernike polynomial coefficients from the training reconstructed wafer maps. 19. The method of claim 16, further comprising:
supplying the reconstructed wafer map to a feature extractor to compute a feature map; and supplying the feature map to a second trained classifier to classify the reconstructed wafer map with one of the plurality of labels, wherein the feature extractor is a second convolutional neural network, the second convolutional neural network being trained by training the classifier to predict the plurality of labels based on the training set of ground truth wafer maps. 20. The method of claim 11, further comprising controlling a run-to-run controller of a semiconductor fabrication process based on the reconstructed wafer map. | A system for reconstructing wafer maps of semiconductor wafers includes: a processor; and memory having instructions stored thereon that, when executed by the processor, cause the processor to: receive test data of a wafer at sparse sampling locations of the wafer, the sparse sampling locations being selected based on a probing mask; and compute a reconstructed wafer map by performing compressed sensing with Zernike polynomials on the test data at sparse locations of the wafer.1. A system for reconstructing wafer maps of semiconductor wafers, comprising:
a processor; and memory having instructions stored thereon that, when executed by the processor, cause the processor to:
receive test data of a wafer at sparse sampling locations of the wafer, the sparse sampling locations being selected based on a probing mask; and
compute a reconstructed wafer map by performing compressed sensing with Zernike polynomials on the test data at sparse locations of the wafer. 2. The system of claim 1, wherein the sparse sampling locations of the probing mask are randomly selected. 3. The system of claim 1, wherein the sparse sampling locations of the probing mask are generated by:
receiving a training set of ground truth wafer maps; setting a probing mask based on an initial set of sparse sampling locations; selecting samples from the training set of ground truth wafer maps based on the probing mask; applying a genetic algorithm to compute a customized probing mask, the genetic algorithm iteratively, over a plurality of generations:
computing reconstructed wafer maps using compressed sensing based on the test data taken from the sparse sampling locations;
scoring the reconstructed wafer maps against the training set of ground truth wafer maps;
updating the sparse sampling locations of the probing mask in accordance with the scores; and
returning the updated sparse sampling locations of the probing mask from the genetic algorithm when a threshold error rate is satisfied or when the plurality of generations reaches a generation limit. 4. The system of claim 1, wherein the memory further stores instructions that, when executed by the processor, cause the processor to supply the reconstructed wafer map reconstructed by compressed sensing to a first convolutional neural network, the first convolutional neural network being configured to update the reconstructed wafer map. 5. The system of claim 4, wherein the first convolutional neural network is trained by:
receiving a training set of ground truth wafer maps; selecting samples from the training set of ground truth wafer maps based on the probing mask; computing training reconstructed wafer maps from the selected samples from the training set of ground truth wafer maps; and applying backpropagation to train the first convolutional neural network to compute the training set of ground truth wafer maps from the training reconstructed wafer maps. 6. The system of claim 1, wherein the memory further stores instructions that, when executed by the processor, cause the processor to classify the reconstructed wafer map with one of a plurality of labels using a classifier, and
wherein the classifier is trained using:
a training set of ground truth wafer maps; and
a plurality of labels of the training set of ground truth wafer maps, the plurality of labels being computed by applying an anomaly detection technique to the training set of ground truth wafer maps to identify one or more classes of wafers, the classes of wafers comprising anomalous wafers and non-anomalous wafers. 7. The system of claim 6, wherein the anomaly detection technique includes at least one of principal component analysis or biclustering. 8. The system of claim 6, wherein the memory further stores instructions that, when executed by the processor, cause the processor to supply a plurality of Zernike polynomial coefficients corresponding to the reconstructed wafer map to the classifier, and
wherein the classifier is trained by:
selecting samples from the training set of ground truth wafer maps based on the probing mask;
computing training reconstructed wafer maps from the selected samples from the training set of ground truth wafer maps; and
training the classifier to predict the plurality of labels based on a plurality of training Zernike polynomial coefficients from the training reconstructed wafer maps. 9. The system of claim 6, wherein the memory further stores instructions that, when executed by the processor, cause the processor to:
supply the reconstructed wafer map to a feature extractor to compute a feature map; and supply the feature map to a second trained classifier to classify the reconstructed wafer map with one of the plurality of labels, wherein the feature extractor is a second convolutional neural network, the second convolutional neural network being trained by training the classifier to predict the plurality of labels based on the training set of ground truth wafer maps. 10. The system of claim 1, wherein the system is configured to provide feedback to a run-to-run controller of a semiconductor fabrication process based on the reconstructed wafer map. 11. A method for reconstructing wafer maps of semiconductor wafers, comprising:
receiving, by a processor, test data of a wafer at sparse sampling locations of the wafer, the sparse sampling locations being selected based on a probing mask; and computing, by the processor, a reconstructed wafer map by performing compressed sensing with Zernike polynomials on the test data at sparse locations of the wafer. 12. The method of claim 11, wherein the sparse sampling locations of the probing mask are randomly selected. 13. The method of claim 11, wherein the sparse sampling locations of the probing mask are generated by:
receiving a training set of ground truth wafer maps; setting a probing mask based on an initial set of sparse sampling locations; selecting samples from the training set of ground truth wafer maps based on the probing mask; applying a genetic algorithm to compute a customized probing mask, the genetic algorithm iteratively, over a plurality of generations:
computing reconstructed wafer maps using compressed sensing based on the test data taken from the sparse sampling locations;
scoring the reconstructed wafer maps against the training set of ground truth wafer maps;
updating the sparse sampling locations of the probing mask in accordance with the scores; and
returning the updated sparse sampling locations of the probing mask from the genetic algorithm when a threshold error rate is satisfied or when the plurality of generations reaches a generation limit. 14. The method of claim 11, further comprising supplying the reconstructed wafer map reconstructed by compressed sensing to a first convolutional neural network, the first convolutional neural network being configured to update the reconstructed wafer map. 15. The method of claim 14, wherein the first convolutional neural network is trained by:
receiving a training set of ground truth wafer maps; selecting samples from the training set of ground truth wafer maps based on the probing mask; computing training reconstructed wafer maps from the selected samples from the training set of ground truth wafer maps; and applying backpropagation to train the first convolutional neural network to compute the training set of ground truth wafer maps from the training reconstructed wafer maps. 16. The method of claim 11, further comprising classifying the reconstructed wafer map with one of a plurality of labels using a classifier,
wherein the classifier is trained using:
a training set of ground truth wafer maps; and
a plurality of labels of the training set of ground truth wafer maps, the plurality of labels being computed by applying an anomaly detection technique to the training set of ground truth wafer maps to identify one or more classes of wafers, the classes of wafers comprising anomalous wafers and non-anomalous wafers. 17. The method of claim 16, wherein the anomaly detection technique includes at least one of principal component analysis or biclustering. 18. The method of claim 16, further comprising supplying a plurality of Zernike polynomial coefficients corresponding to the reconstructed wafer map to the classifier,
wherein the classifier is trained by:
selecting samples from the training set of ground truth wafer maps based on the probing mask;
computing training reconstructed wafer maps from the selected samples from the training set of ground truth wafer maps; and
training the classifier to predict the plurality of labels based on a plurality of training Zernike polynomial coefficients from the training reconstructed wafer maps. 19. The method of claim 16, further comprising:
supplying the reconstructed wafer map to a feature extractor to compute a feature map; and supplying the feature map to a second trained classifier to classify the reconstructed wafer map with one of the plurality of labels, wherein the feature extractor is a second convolutional neural network, the second convolutional neural network being trained by training the classifier to predict the plurality of labels based on the training set of ground truth wafer maps. 20. The method of claim 11, further comprising controlling a run-to-run controller of a semiconductor fabrication process based on the reconstructed wafer map. | 2,800 |
11,987 | 11,987 | 14,362,139 | 2,884 | The present invention relates to radiation detector ( 2 ) comprising a radiation sensitive semiconductor element ( 10 ) generating electron-hole pairs in response to an irradiation with radiation ( 3 ), an anode electrode( 20 ) arranged on a first surface ( 11 ) of the semiconductor element ( 10 ) facing away from the radiation, said anode electrode ( 20 ) being segmented into anode segments ( 21 ) representing anode pixels, wherein anode gaps ( 22 ) are arranged between said anode segments ( 21 ), a cathode electrode ( 30 ) arranged on a second surface ( 12 ) of the semiconductor element ( 10 ) opposite the first surface ( 11 ) and facing the radiation ( 3 ), said cathode electrode ( 30 ) being segmented into first and second cathode segments ( 31, 32 ), wherein said first cathode segments ( 31 ) are substantially arranged opposite said anode segments ( 21 ) and said second cathode segments ( 32 ) are substantially arranged opposite said anode gaps ( 22 ), and a cathode terminal ( 41, 42 ) providing electrical connections to said first cathode segments ( 31 ) and said second cathode segments ( 32 ) for coupling different electrical potentials to said first and second cathode segments ( 31, 32 ). By such an arrangement charge sharing can be effectively reduced. | 1. A radiation detector comprising:
a radiation sensitive semiconductor element generating electron-hole pairs in response to an irradiation with X-ray or gamma radiation, an anode electrode arranged on a first surface of the semiconductor element, said anode electrode being segmented into anode segments representing anode pixels, wherein anode gaps are arranged between said anode segments, a cathode electrode arranged on a second surface of the semiconductor element opposite the first surface, said cathode electrode being segmented into first and second cathode segments, wherein said first cathode segments are substantially arranged opposite said anode segments and said second cathode segments are substantially arranged opposite said anode gaps, and a cathode terminal providing electrical connections to said first cathode segments and said second cathode segments for coupling different electrical potentials to said first and second cathode segments. 2. The radiation detector as claimed in claim 1, wherein said first cathode segments are arranged as an array of first cathode segments. 3. The radiation detector as claimed in claim 1, wherein said first cathode segments (31) have substantially the same form in directions parallel to the second surface than said anode segments. 4. The radiation detector as claimed in claim 1, wherein said first cathode segments are separated from each other and are individually coupled to a first cathode terminal. 5. The radiation detector as claimed in claim 1, wherein said first cathode segments are coupled together in groups, in particular per row or per column, by cathode connection electrodes arranged on said second surface of said semiconductor element, said groups being individually coupled to a first cathode terminal. 6. The radiation detector as claimed in claim 1, wherein said second cathode segments arranged as a grid of second cathode segments. 7. The radiation detector as claimed in claim 1, wherein said second cathode segments are coupled together in a single or multiple groups being coupled to one or multiple second cathode terminals. 8. The radiation detector as claimed in claim 1, wherein said cathode electrode is segmented into at least three cathode segments, wherein said first cathode segments are substantially arranged opposite said anode segments and the further cathode segments are nested around said first cathode segments, and
wherein said cathode terminal provides electrical connections to different cathode segments for coupling different electrical potentials to said different cathode segments. 9. The radiation detector as claimed in claim 1, wherein said semiconductor element is adapted for generating electron-hole pairs in response to an irradiation with X-ray or gamma radiation. 10. The radiation detector as claimed in claim 1, wherein said semiconductor element is made from an elemental semiconductor material, in particular Si or Ge, a binary semiconductor material selected from the IV-group of the periodic system, in particular SiGe or SiC, a binary semiconductor material from the groups III and V of the periodic system, in particular InP, GaAs or GaN, a binary semiconductor material from the groups II and VI of the periodic system, in particular CdTe, HgTe, CdSe or ZnS, a binary semiconductor material from the groups IV and VI of the periodic system, in particular PbO or PbS, a ternary semiconductor material, in particular CdZnTe, HgCdTe, or AlGaAs or a quaternary semiconductor material, in particular InGaAsP or InGaAlP. 11. The radiation detector as claimed in claim 1, further comprising
anode gap segments arranged within said anode gaps between adjacent anode segments and an anode terminal providing electrical connections to said anode gap segments for coupling an electrical potential to said anode gap segments, in particular an electrical potential that is more negative than the electrical potential of said anode segments. 12. A radiation detection apparatus comprising:
a radiation detector as claimed in claim 1, and a voltage source coupled to said cathode terminal for coupling different electrical potentials to said first and second cathode segments. 13. The radiation detection apparatus as claimed in claim 12, wherein said voltage source is adapted for coupling an electrical potential to said second cathode segments that provides a larger voltage difference to said anode electrode than an electrical potential coupled to said first cathode segments. 14. The radiation detection apparatus as claimed in claim 12, wherein said voltage source is adapted for coupling electrical potentials to said first and second cathode segments having a voltage difference in the range between 10 V and 200 V. 15. The radiation detection apparatus as claimed in claim 12, wherein said voltage source is adapted for coupling electrical potentials to said first and second cathode segments having a voltage difference to the electrical potential of said anode electrode in the range between 50 V and 1000 V. 16. A radiation detector comprising:
a radiation sensitive semiconductor element generating electron-hole pairs in response to an irradiation with X-ray or gamma radiation; a cathode electrode arranged on a first surface of the semiconductor element, said cathode electrode being segmented into cathode segments representing cathode pixels, wherein cathode gaps are arranged between said cathode segments, an anode electrode arranged on a second surface of the semiconductor element opposite the first surface, said anode electrode being segmented into first and second anode segments, wherein said first anode segments are substantially arranged opposite said cathode segments and said second anode segments are substantially arranged opposite said cathode gaps, and an anode terminal providing electrical connections to said first anode segments and said second anode segments for coupling different electrical potentials to said first and second anode segments. 17. A radiation detection apparatus comprising:
a radiation detector as claimed in claim 16, and a voltage source coupled to said anode terminal for coupling different electrical potentials to said first and second anode segments. | The present invention relates to radiation detector ( 2 ) comprising a radiation sensitive semiconductor element ( 10 ) generating electron-hole pairs in response to an irradiation with radiation ( 3 ), an anode electrode( 20 ) arranged on a first surface ( 11 ) of the semiconductor element ( 10 ) facing away from the radiation, said anode electrode ( 20 ) being segmented into anode segments ( 21 ) representing anode pixels, wherein anode gaps ( 22 ) are arranged between said anode segments ( 21 ), a cathode electrode ( 30 ) arranged on a second surface ( 12 ) of the semiconductor element ( 10 ) opposite the first surface ( 11 ) and facing the radiation ( 3 ), said cathode electrode ( 30 ) being segmented into first and second cathode segments ( 31, 32 ), wherein said first cathode segments ( 31 ) are substantially arranged opposite said anode segments ( 21 ) and said second cathode segments ( 32 ) are substantially arranged opposite said anode gaps ( 22 ), and a cathode terminal ( 41, 42 ) providing electrical connections to said first cathode segments ( 31 ) and said second cathode segments ( 32 ) for coupling different electrical potentials to said first and second cathode segments ( 31, 32 ). By such an arrangement charge sharing can be effectively reduced.1. A radiation detector comprising:
a radiation sensitive semiconductor element generating electron-hole pairs in response to an irradiation with X-ray or gamma radiation, an anode electrode arranged on a first surface of the semiconductor element, said anode electrode being segmented into anode segments representing anode pixels, wherein anode gaps are arranged between said anode segments, a cathode electrode arranged on a second surface of the semiconductor element opposite the first surface, said cathode electrode being segmented into first and second cathode segments, wherein said first cathode segments are substantially arranged opposite said anode segments and said second cathode segments are substantially arranged opposite said anode gaps, and a cathode terminal providing electrical connections to said first cathode segments and said second cathode segments for coupling different electrical potentials to said first and second cathode segments. 2. The radiation detector as claimed in claim 1, wherein said first cathode segments are arranged as an array of first cathode segments. 3. The radiation detector as claimed in claim 1, wherein said first cathode segments (31) have substantially the same form in directions parallel to the second surface than said anode segments. 4. The radiation detector as claimed in claim 1, wherein said first cathode segments are separated from each other and are individually coupled to a first cathode terminal. 5. The radiation detector as claimed in claim 1, wherein said first cathode segments are coupled together in groups, in particular per row or per column, by cathode connection electrodes arranged on said second surface of said semiconductor element, said groups being individually coupled to a first cathode terminal. 6. The radiation detector as claimed in claim 1, wherein said second cathode segments arranged as a grid of second cathode segments. 7. The radiation detector as claimed in claim 1, wherein said second cathode segments are coupled together in a single or multiple groups being coupled to one or multiple second cathode terminals. 8. The radiation detector as claimed in claim 1, wherein said cathode electrode is segmented into at least three cathode segments, wherein said first cathode segments are substantially arranged opposite said anode segments and the further cathode segments are nested around said first cathode segments, and
wherein said cathode terminal provides electrical connections to different cathode segments for coupling different electrical potentials to said different cathode segments. 9. The radiation detector as claimed in claim 1, wherein said semiconductor element is adapted for generating electron-hole pairs in response to an irradiation with X-ray or gamma radiation. 10. The radiation detector as claimed in claim 1, wherein said semiconductor element is made from an elemental semiconductor material, in particular Si or Ge, a binary semiconductor material selected from the IV-group of the periodic system, in particular SiGe or SiC, a binary semiconductor material from the groups III and V of the periodic system, in particular InP, GaAs or GaN, a binary semiconductor material from the groups II and VI of the periodic system, in particular CdTe, HgTe, CdSe or ZnS, a binary semiconductor material from the groups IV and VI of the periodic system, in particular PbO or PbS, a ternary semiconductor material, in particular CdZnTe, HgCdTe, or AlGaAs or a quaternary semiconductor material, in particular InGaAsP or InGaAlP. 11. The radiation detector as claimed in claim 1, further comprising
anode gap segments arranged within said anode gaps between adjacent anode segments and an anode terminal providing electrical connections to said anode gap segments for coupling an electrical potential to said anode gap segments, in particular an electrical potential that is more negative than the electrical potential of said anode segments. 12. A radiation detection apparatus comprising:
a radiation detector as claimed in claim 1, and a voltage source coupled to said cathode terminal for coupling different electrical potentials to said first and second cathode segments. 13. The radiation detection apparatus as claimed in claim 12, wherein said voltage source is adapted for coupling an electrical potential to said second cathode segments that provides a larger voltage difference to said anode electrode than an electrical potential coupled to said first cathode segments. 14. The radiation detection apparatus as claimed in claim 12, wherein said voltage source is adapted for coupling electrical potentials to said first and second cathode segments having a voltage difference in the range between 10 V and 200 V. 15. The radiation detection apparatus as claimed in claim 12, wherein said voltage source is adapted for coupling electrical potentials to said first and second cathode segments having a voltage difference to the electrical potential of said anode electrode in the range between 50 V and 1000 V. 16. A radiation detector comprising:
a radiation sensitive semiconductor element generating electron-hole pairs in response to an irradiation with X-ray or gamma radiation; a cathode electrode arranged on a first surface of the semiconductor element, said cathode electrode being segmented into cathode segments representing cathode pixels, wherein cathode gaps are arranged between said cathode segments, an anode electrode arranged on a second surface of the semiconductor element opposite the first surface, said anode electrode being segmented into first and second anode segments, wherein said first anode segments are substantially arranged opposite said cathode segments and said second anode segments are substantially arranged opposite said cathode gaps, and an anode terminal providing electrical connections to said first anode segments and said second anode segments for coupling different electrical potentials to said first and second anode segments. 17. A radiation detection apparatus comprising:
a radiation detector as claimed in claim 16, and a voltage source coupled to said anode terminal for coupling different electrical potentials to said first and second anode segments. | 2,800 |
11,988 | 11,988 | 15,145,943 | 2,884 | A method is disclosed for generating an image. An embodiment of the method includes detecting a first projection data set via a first group of detector units, the first group including a first plurality of first detector units, each having more than a given number of detector elements; detecting a second projection data set via a second group of detector units, the second group including a second plurality of second detector units, each including, at most, the given number of detector elements; reconstructing first image data based on the first projection data set; reconstructing second image data based on the second projection data set; and combining the first image data and the second image data. A non-transitory computer readable medium, a data processing unit, and an imaging device including the data processing unit are also disclosed. | 1. A method for generating an image, comprising:
detecting a first projection data set via a first group of detector units, the first group including a first plurality of first detector units, the first detector units each including more than a given number of detector elements, wherein the first detector units are each designed for spectrally resolved detection of radiation quanta; detecting a second projection data set via a second group of detector units, the second group including a second plurality of second detector units, the second detector units each including, at most, the given number of detector elements, wherein the second detector units are each designed for spectrally resolved detection of radiation quanta; reconstructing first image data based on the first projection data set; reconstructing second image data based on the second projection data set; and combining the reconstructed first image data and the reconstructed second image data. 2. The method of claim 1, wherein the first image data is filtered via a first filter and the second image data is filtered via a second filter, the combining including adding the filtered first image data and the filtered second image data, pixel-by-pixel. 3. The method of claim 2, wherein the first filter includes a first transfer function and the second filter includes a second transfer function, a total of the first transfer function and the second transfer function being a constant function. 4. The method of claim 3, wherein the first filter includes a low pass filter and the second filter includes a high pass filter. 5. The method of claim 1, wherein the first image data and the second image data are multiplied pixel-by-pixel. 6. The method of claim 5, wherein the value of the pixel of the back projection data is divided by the total of the values of the pixels of the pixel group. 7. The method of claim 1, wherein a detector element is assignable to a first detector unit or a second detector unit or both a first detector unit and a second detector unit. 8. The method of claim 1, wherein at least one of the first detector units and the second detector units each include a respective spectral resolution, and wherein the respective spectral resolution is definable by the number of detector elements incorporated by the respective detector unit. 9. The method of claim 1, wherein at least one of the first detector units and the second detector units each include a respective spatial resolution, wherein the respective spatial resolution is definable by the number of detector elements incorporated by the respective detector unit. 10. A data processing unit, comprising:
a first group of detector units, the first group of detector units being designed to detect a first projection data set, wherein the first group includes a first plurality of first detector units, the first detector units each including more than a given number of detector elements, wherein the first detector units are each designed for spectrally resolved detection of radiation quanta; a second group of detector units, the second group of detector units being designed to detect a second projection data set, wherein the second group includes a second plurality of second detector units, the second detector units each including, at most, the given number of detector elements, wherein the second detector units are each designed for spectrally resolved detection of radiation quanta; a reconstruction unit, designed to reconstruct first image data based on the first projection data set and to reconstruct second image data based on the second projection data set; and a combination unit, designed to combine the reconstructed first image data and the reconstructed second image data. 11. The data processing unit of claim 10, wherein the reconstruction unit includes at least the following units:
a back projection unit, designed to generate back projection data based on the second projection data set, wherein a back projection path is assignable to a pixel of the back projection data, a normalizing unit, designed to normalize the back projection data, information based on a pixel group being used for the pixels of the back projection data, wherein the pixel group includes the pixels of the first image data assignable to the back projection path, and adding unit, designed to add the normalized back projection data pixel-by-pixel. 12. An imaging device comprising:
a radiation source; a detector; and the data processing unit of claim 10. 13. An imaging device comprising:
a radiation source; a detector; and the data processing unit of claim 11. 14. A non-transitory computer readable medium, including program sections stored thereon, the program sections being readable and executable by a data processing unit to carry out the method of claim 1, when the program sections are executed by the data processing unit. 15. A non-transitory computer readable medium, including program sections stored thereon, the program sections being readable and executable by a data processing unit to carry out the method of claim 2, when the program sections are executed by the data processing unit. 16. The method of claim 2, wherein the first filter includes a low pass filter and the second filter includes a high pass filter. 17. The method of claim 1, wherein the reconstructing of the second image data comprises:
generating back projection data based on the second projection data set, wherein a back projection path is assignable to a pixel of the back projection data, normalizing the back projection data, information based on a pixel group being used for the pixel of the back projection data, wherein the pixel group includes pixels of the first image data assignable to the back projection path, and pixel-by-pixel addition of the normalized back projection data. 18. The method of claim 5, wherein the reconstructing of the second image data comprises:
generating back projection data based on the second projection data set, wherein a back projection path is assignable to a pixel of the back projection data, normalizing the back projection data, information based on a pixel group being used for the pixel of the back projection data, wherein the pixel group includes pixels of the first image data assignable to the back projection path, and pixel-by-pixel addition of the normalized back projection data. 19. The method of claim 18, wherein the value of the pixel of the back projection data is divided by the total of the values of the pixels of the pixel group. 20. The method of claim 2, wherein at least one of the first detector units and the second detector units each include a respective spatial resolution, wherein the respective spatial resolution is definable by the number of detector elements incorporated by the respective detector unit. 21. The method of claim 3, wherein at least one of the first detector units and the second detector units each include a respective spatial resolution, wherein the respective spatial resolution is definable by the number of detector elements incorporated by the respective detector unit. | A method is disclosed for generating an image. An embodiment of the method includes detecting a first projection data set via a first group of detector units, the first group including a first plurality of first detector units, each having more than a given number of detector elements; detecting a second projection data set via a second group of detector units, the second group including a second plurality of second detector units, each including, at most, the given number of detector elements; reconstructing first image data based on the first projection data set; reconstructing second image data based on the second projection data set; and combining the first image data and the second image data. A non-transitory computer readable medium, a data processing unit, and an imaging device including the data processing unit are also disclosed.1. A method for generating an image, comprising:
detecting a first projection data set via a first group of detector units, the first group including a first plurality of first detector units, the first detector units each including more than a given number of detector elements, wherein the first detector units are each designed for spectrally resolved detection of radiation quanta; detecting a second projection data set via a second group of detector units, the second group including a second plurality of second detector units, the second detector units each including, at most, the given number of detector elements, wherein the second detector units are each designed for spectrally resolved detection of radiation quanta; reconstructing first image data based on the first projection data set; reconstructing second image data based on the second projection data set; and combining the reconstructed first image data and the reconstructed second image data. 2. The method of claim 1, wherein the first image data is filtered via a first filter and the second image data is filtered via a second filter, the combining including adding the filtered first image data and the filtered second image data, pixel-by-pixel. 3. The method of claim 2, wherein the first filter includes a first transfer function and the second filter includes a second transfer function, a total of the first transfer function and the second transfer function being a constant function. 4. The method of claim 3, wherein the first filter includes a low pass filter and the second filter includes a high pass filter. 5. The method of claim 1, wherein the first image data and the second image data are multiplied pixel-by-pixel. 6. The method of claim 5, wherein the value of the pixel of the back projection data is divided by the total of the values of the pixels of the pixel group. 7. The method of claim 1, wherein a detector element is assignable to a first detector unit or a second detector unit or both a first detector unit and a second detector unit. 8. The method of claim 1, wherein at least one of the first detector units and the second detector units each include a respective spectral resolution, and wherein the respective spectral resolution is definable by the number of detector elements incorporated by the respective detector unit. 9. The method of claim 1, wherein at least one of the first detector units and the second detector units each include a respective spatial resolution, wherein the respective spatial resolution is definable by the number of detector elements incorporated by the respective detector unit. 10. A data processing unit, comprising:
a first group of detector units, the first group of detector units being designed to detect a first projection data set, wherein the first group includes a first plurality of first detector units, the first detector units each including more than a given number of detector elements, wherein the first detector units are each designed for spectrally resolved detection of radiation quanta; a second group of detector units, the second group of detector units being designed to detect a second projection data set, wherein the second group includes a second plurality of second detector units, the second detector units each including, at most, the given number of detector elements, wherein the second detector units are each designed for spectrally resolved detection of radiation quanta; a reconstruction unit, designed to reconstruct first image data based on the first projection data set and to reconstruct second image data based on the second projection data set; and a combination unit, designed to combine the reconstructed first image data and the reconstructed second image data. 11. The data processing unit of claim 10, wherein the reconstruction unit includes at least the following units:
a back projection unit, designed to generate back projection data based on the second projection data set, wherein a back projection path is assignable to a pixel of the back projection data, a normalizing unit, designed to normalize the back projection data, information based on a pixel group being used for the pixels of the back projection data, wherein the pixel group includes the pixels of the first image data assignable to the back projection path, and adding unit, designed to add the normalized back projection data pixel-by-pixel. 12. An imaging device comprising:
a radiation source; a detector; and the data processing unit of claim 10. 13. An imaging device comprising:
a radiation source; a detector; and the data processing unit of claim 11. 14. A non-transitory computer readable medium, including program sections stored thereon, the program sections being readable and executable by a data processing unit to carry out the method of claim 1, when the program sections are executed by the data processing unit. 15. A non-transitory computer readable medium, including program sections stored thereon, the program sections being readable and executable by a data processing unit to carry out the method of claim 2, when the program sections are executed by the data processing unit. 16. The method of claim 2, wherein the first filter includes a low pass filter and the second filter includes a high pass filter. 17. The method of claim 1, wherein the reconstructing of the second image data comprises:
generating back projection data based on the second projection data set, wherein a back projection path is assignable to a pixel of the back projection data, normalizing the back projection data, information based on a pixel group being used for the pixel of the back projection data, wherein the pixel group includes pixels of the first image data assignable to the back projection path, and pixel-by-pixel addition of the normalized back projection data. 18. The method of claim 5, wherein the reconstructing of the second image data comprises:
generating back projection data based on the second projection data set, wherein a back projection path is assignable to a pixel of the back projection data, normalizing the back projection data, information based on a pixel group being used for the pixel of the back projection data, wherein the pixel group includes pixels of the first image data assignable to the back projection path, and pixel-by-pixel addition of the normalized back projection data. 19. The method of claim 18, wherein the value of the pixel of the back projection data is divided by the total of the values of the pixels of the pixel group. 20. The method of claim 2, wherein at least one of the first detector units and the second detector units each include a respective spatial resolution, wherein the respective spatial resolution is definable by the number of detector elements incorporated by the respective detector unit. 21. The method of claim 3, wherein at least one of the first detector units and the second detector units each include a respective spatial resolution, wherein the respective spatial resolution is definable by the number of detector elements incorporated by the respective detector unit. | 2,800 |
11,989 | 11,989 | 15,704,146 | 2,861 | The present disclosure relates to a method for monitoring the function of a sensor arrangement with at least two measuring points, wherein a sensor is arranged at each measuring point to determine at least one process variable of a medium, comprising the steps of contacting the medium with the sensors, determining a temporal load value for each measuring point from the at least one process variable that was determined at this measuring point, determining a total load value for each sensor from the temporal load value of the measuring point where the sensor was used and from the time during which the sensor was used at this measuring point, predicting a lifespan of a sensor at a certain measuring point based upon the temporal load value of this measuring point and the total load value of this sensor. | 1. A method for monitoring the function of a sensor arrangement with at least two measuring points, comprising the steps:
contacting a medium with a sensor of the sensor arrangement, wherein the sensor arrangement includes a sensor arranged at each measuring point to determine at least one process variable of the medium; operating the sensor arrangement such that the sensor determines the at least one process variable of the medium; determining a temporal load value for each measuring point from the at least one process variable that was determined at this measuring point; determining a total load value for the sensor from the temporal load value of the measuring point where the sensor was used and from a period during which the sensor was used at this measuring point; and predicting a remaining lifespan of the sensor at a certain measuring point based upon the temporal load value of the certain measuring point and the total load value of the sensor. 2. The method according to claim 1, wherein a change in the calibration values and/or the adjustment values of the sensors is an indication of a change in the total load values of the sensors. 3. The method of claim 1, wherein the at least one process variable is the pH value and/or the temperature. 4. The method of claim 1, wherein the total load value of the sensor is determined by multiplying the temporal load value of the measuring point where the sensor was used by the period during which the sensor was used at the measuring point, as in:
GB
=
(
B
t
)
·
t
wherein GB is the total load value of the sensor, B/t is the temporal load value of the measuring point where the sensor was used, and t is the period. 5. The method of claim 4, wherein the remaining lifespan (T) of the sensor at the certain measuring point is determined as follows:
T
=
GB
max
-
GB
(
B
t
)
wherein T is the remaining lifespan, and GBmax is the maximum total load of the sensor, at which the sensor is no longer functional. 6. The method of claim 1, wherein the prediction of the remaining lifespan of the sensor at all measuring points is carried out based upon the temporal load value of the respective measuring points and the total load value of the sensor. | The present disclosure relates to a method for monitoring the function of a sensor arrangement with at least two measuring points, wherein a sensor is arranged at each measuring point to determine at least one process variable of a medium, comprising the steps of contacting the medium with the sensors, determining a temporal load value for each measuring point from the at least one process variable that was determined at this measuring point, determining a total load value for each sensor from the temporal load value of the measuring point where the sensor was used and from the time during which the sensor was used at this measuring point, predicting a lifespan of a sensor at a certain measuring point based upon the temporal load value of this measuring point and the total load value of this sensor.1. A method for monitoring the function of a sensor arrangement with at least two measuring points, comprising the steps:
contacting a medium with a sensor of the sensor arrangement, wherein the sensor arrangement includes a sensor arranged at each measuring point to determine at least one process variable of the medium; operating the sensor arrangement such that the sensor determines the at least one process variable of the medium; determining a temporal load value for each measuring point from the at least one process variable that was determined at this measuring point; determining a total load value for the sensor from the temporal load value of the measuring point where the sensor was used and from a period during which the sensor was used at this measuring point; and predicting a remaining lifespan of the sensor at a certain measuring point based upon the temporal load value of the certain measuring point and the total load value of the sensor. 2. The method according to claim 1, wherein a change in the calibration values and/or the adjustment values of the sensors is an indication of a change in the total load values of the sensors. 3. The method of claim 1, wherein the at least one process variable is the pH value and/or the temperature. 4. The method of claim 1, wherein the total load value of the sensor is determined by multiplying the temporal load value of the measuring point where the sensor was used by the period during which the sensor was used at the measuring point, as in:
GB
=
(
B
t
)
·
t
wherein GB is the total load value of the sensor, B/t is the temporal load value of the measuring point where the sensor was used, and t is the period. 5. The method of claim 4, wherein the remaining lifespan (T) of the sensor at the certain measuring point is determined as follows:
T
=
GB
max
-
GB
(
B
t
)
wherein T is the remaining lifespan, and GBmax is the maximum total load of the sensor, at which the sensor is no longer functional. 6. The method of claim 1, wherein the prediction of the remaining lifespan of the sensor at all measuring points is carried out based upon the temporal load value of the respective measuring points and the total load value of the sensor. | 2,800 |
11,990 | 11,990 | 15,837,857 | 2,818 | Implementations of semiconductor packages may include: one or more die having a first side and a second side opposite the first side; the first side of the die may include one or more external connection points; a layer of one or more metals comprised on the second side of the one or more die; a second layer of one or more metals comprised on the first layer of one or more metals, wherein the second layer is thicker than the first layer; a molding compound encapsulating five sides of the one or more die and partially encapsulating the second layer of a metal; a plurality of interconnects coupled to the second layer of one or more metals; and two or more bumps coupled to the plurality of interconnects. At least a portion of each of the two or more bumps may be outside a perimeter of the one or more die. | 1. A semiconductor package comprising:
one or more die comprising a first side and a second side opposite the first side, the first side of the die comprising one or more external connection points; a layer of one or more metals comprised on the second side of the one or more die; a second layer of one or more metals comprised on a first layer of one or more metals comprised on the first side of the die wherein the second layer is thicker than the first layer; a molding compound encapsulating five sides of the one or more die and partially encapsulating the second layer of one or more metals; a plurality of interconnects coupled to the second layer of one or more metals; and two or more bumps coupled to the plurality of interconnects; wherein at least a portion of each of the two or more bumps is outside a perimeter of the one or more die. 2. The semiconductor of claim 1, wherein the two or more bumps comprise one of copper pillars, balls, solder printed pads, and pads. 3. The semiconductor package of claim 1, further comprising one of a first passivation layer and a redistribution layer (RDL). 4. The semiconductor package of claim 3, further comprising a second passivation layer. 5. The semiconductor package of claim 1, further comprising a second molding compound on the first side of the one of more die. 6. The semiconductor package of claim 1, further comprising a metal coating on the one or more external connection points of the first side of the one or more die, the metal coating selected from the group consisting of titanium, nickel, vanadium, silver, copper, gold, aluminum, and any combination thereof. 7. The semiconductor package of claim 1, further comprising one of a copper plating and a copper frame on the one or more external connection points of the first side of the die. 8. A semiconductor package comprising:
one or more die comprising a first side and a second side opposite the first side; two or more copper pillars coupled on the second side of the one or more die; a layer of aluminum coupled between the one or more die and each of the two or more copper pillars; a molding compound encapsulating five sides of the one or more die and partially encapsulating the two or more copper pillars; a routing layer of metal coupled to the two or more copper pillars; and a plurality of solder bumps coupled to the routing layer; wherein at least a portion of the solder bumps are outside a perimeter of the one or more die. 9. The semiconductor package of claim 8, further comprising one of a first passivation layer and a redistribution layer (RDL). 10. The semiconductor package of claim 9, further comprising a second passivation layer. 11. The semiconductor package of claim 8, further comprising a second molding compound on the first side of the one or more die. 12. The semiconductor package of claim 8, further comprising a metal coating on the first side of the die, the metal coating selected from the group consisting of titanium, nickel, vanadium, silver, copper, gold, aluminum, and any combination thereof. 13. The semiconductor package of claim 8, further comprising one of a copper plating and a copper frame on a first side of the die. 14.-20. (canceled) | Implementations of semiconductor packages may include: one or more die having a first side and a second side opposite the first side; the first side of the die may include one or more external connection points; a layer of one or more metals comprised on the second side of the one or more die; a second layer of one or more metals comprised on the first layer of one or more metals, wherein the second layer is thicker than the first layer; a molding compound encapsulating five sides of the one or more die and partially encapsulating the second layer of a metal; a plurality of interconnects coupled to the second layer of one or more metals; and two or more bumps coupled to the plurality of interconnects. At least a portion of each of the two or more bumps may be outside a perimeter of the one or more die.1. A semiconductor package comprising:
one or more die comprising a first side and a second side opposite the first side, the first side of the die comprising one or more external connection points; a layer of one or more metals comprised on the second side of the one or more die; a second layer of one or more metals comprised on a first layer of one or more metals comprised on the first side of the die wherein the second layer is thicker than the first layer; a molding compound encapsulating five sides of the one or more die and partially encapsulating the second layer of one or more metals; a plurality of interconnects coupled to the second layer of one or more metals; and two or more bumps coupled to the plurality of interconnects; wherein at least a portion of each of the two or more bumps is outside a perimeter of the one or more die. 2. The semiconductor of claim 1, wherein the two or more bumps comprise one of copper pillars, balls, solder printed pads, and pads. 3. The semiconductor package of claim 1, further comprising one of a first passivation layer and a redistribution layer (RDL). 4. The semiconductor package of claim 3, further comprising a second passivation layer. 5. The semiconductor package of claim 1, further comprising a second molding compound on the first side of the one of more die. 6. The semiconductor package of claim 1, further comprising a metal coating on the one or more external connection points of the first side of the one or more die, the metal coating selected from the group consisting of titanium, nickel, vanadium, silver, copper, gold, aluminum, and any combination thereof. 7. The semiconductor package of claim 1, further comprising one of a copper plating and a copper frame on the one or more external connection points of the first side of the die. 8. A semiconductor package comprising:
one or more die comprising a first side and a second side opposite the first side; two or more copper pillars coupled on the second side of the one or more die; a layer of aluminum coupled between the one or more die and each of the two or more copper pillars; a molding compound encapsulating five sides of the one or more die and partially encapsulating the two or more copper pillars; a routing layer of metal coupled to the two or more copper pillars; and a plurality of solder bumps coupled to the routing layer; wherein at least a portion of the solder bumps are outside a perimeter of the one or more die. 9. The semiconductor package of claim 8, further comprising one of a first passivation layer and a redistribution layer (RDL). 10. The semiconductor package of claim 9, further comprising a second passivation layer. 11. The semiconductor package of claim 8, further comprising a second molding compound on the first side of the one or more die. 12. The semiconductor package of claim 8, further comprising a metal coating on the first side of the die, the metal coating selected from the group consisting of titanium, nickel, vanadium, silver, copper, gold, aluminum, and any combination thereof. 13. The semiconductor package of claim 8, further comprising one of a copper plating and a copper frame on a first side of the die. 14.-20. (canceled) | 2,800 |
11,991 | 11,991 | 15,825,493 | 2,811 | OLED device structures are provided that include an OLED, a high index optical layer (HOL), a thin film barrier disposed over the high index optical layer, and a low index optical layer (LOL) disposed over the thin film barrier. It is shown that such devices provide acceptable color emission that is at least comparable to a conventional device, while also exhibiting improved efficiency and luminance. | 1. A device comprising:
a substrate; an OLED disposed over the substrate and comprising a first emissive layer configured to emit light of a first color; a high index optical layer having a refractive index of not less than 1.7 disposed over the OLED; a thin film barrier disposed over the high index optical layer; and a low index optical layer having a refractive index of not more than 1.6 disposed over the thin film barrier. 2. The device of claim 1, wherein the low index optical layer comprises an optically clear adhesive layer. 3. The device of claim 2, wherein the optically clear adhesive layer comprises a pressure sensitive adhesive. 4. The device of claim 1, wherein the thin film barrier comprises a plurality of layers. 5. The device of claim 4, wherein the thin film barrier comprises:
a first layer comprising a first material having a first refractive index n1; and a second layer comprising a second material having a second refractive index n2; wherein |n1−n2|<0.2. 6. The device of claim 5, wherein |n1−n2|≤0.15. 7. The device of claim 5, wherein |n1−n2|≤0.1. 8. The device of claim 4, wherein the refractive index between any two regions of the thin film barrier is not more than 0.25. 9. The device of claim 1, wherein the thin film barrier has a refractive index of not more than 1.5. 10. The device of claim 9, wherein the thin film barrier has a refractive index of not more than 1.46. 11. The device of claim 1, wherein the high index optical layer has a refractive index of not less than 1.8. 12. The device of claim 1, wherein the low index optical layer has a thickness of about one quarter of a wavelength of the first color, according to the 1931 CIE chart. 13. The device of claim 1, wherein the low index optical layer has a refractive index of not more than 1.53. 14. The device of claim 1 further comprising a touch sensor disposed above the thin film barrier and below the low index optical layer. 15. The device of claim 1 further comprising a polarizer disposed above the thin film barrier and below the low index optical layer. | OLED device structures are provided that include an OLED, a high index optical layer (HOL), a thin film barrier disposed over the high index optical layer, and a low index optical layer (LOL) disposed over the thin film barrier. It is shown that such devices provide acceptable color emission that is at least comparable to a conventional device, while also exhibiting improved efficiency and luminance.1. A device comprising:
a substrate; an OLED disposed over the substrate and comprising a first emissive layer configured to emit light of a first color; a high index optical layer having a refractive index of not less than 1.7 disposed over the OLED; a thin film barrier disposed over the high index optical layer; and a low index optical layer having a refractive index of not more than 1.6 disposed over the thin film barrier. 2. The device of claim 1, wherein the low index optical layer comprises an optically clear adhesive layer. 3. The device of claim 2, wherein the optically clear adhesive layer comprises a pressure sensitive adhesive. 4. The device of claim 1, wherein the thin film barrier comprises a plurality of layers. 5. The device of claim 4, wherein the thin film barrier comprises:
a first layer comprising a first material having a first refractive index n1; and a second layer comprising a second material having a second refractive index n2; wherein |n1−n2|<0.2. 6. The device of claim 5, wherein |n1−n2|≤0.15. 7. The device of claim 5, wherein |n1−n2|≤0.1. 8. The device of claim 4, wherein the refractive index between any two regions of the thin film barrier is not more than 0.25. 9. The device of claim 1, wherein the thin film barrier has a refractive index of not more than 1.5. 10. The device of claim 9, wherein the thin film barrier has a refractive index of not more than 1.46. 11. The device of claim 1, wherein the high index optical layer has a refractive index of not less than 1.8. 12. The device of claim 1, wherein the low index optical layer has a thickness of about one quarter of a wavelength of the first color, according to the 1931 CIE chart. 13. The device of claim 1, wherein the low index optical layer has a refractive index of not more than 1.53. 14. The device of claim 1 further comprising a touch sensor disposed above the thin film barrier and below the low index optical layer. 15. The device of claim 1 further comprising a polarizer disposed above the thin film barrier and below the low index optical layer. | 2,800 |
11,992 | 11,992 | 12,850,940 | 2,878 | A photon engine and variations thereof and methods of operating the photon engines, the photon engines comprising a primary prism and a secondary prism, the method and apparatus repeatedly imparting linear momentum to multiple reflective surfaces of the photon engine communicating with an energy system. | 1. A method of operating a photon engine to produce linear momentum, the method comprising:
positioning a primary back face of a primary prism comprising a first transparent optical medium having a first index of refraction adjacent to and spaced apart from a secondary back face of a secondary prism comprising a second transparent optical medium having a second index of refraction, the secondary prism comprising multiple lateral faces; providing a containment chamber comprising the secondary prism and multiple reflective surfaces oriented substantially parallel to corresponding multiple lateral faces; directing a light beam into a light expander/contractor device communicating with the primary prism, thereby expanding, reflecting, contracting, and redirecting the light beam upon itself, producing a processed light beam; compressing the secondary back face of the secondary prism relative to the primary back face of the primary prism, forming a transparent interface therebetween; communicating the processed light beam through the transparent interface from the primary prism into the secondary prism, splitting the processed light beam multiple times into multiple processed light beams comprising a higher power output than the light beam; decompressing the secondary back face relative to the primary back face of the primary prism after communicating the multiple processed light beams into the containment chamber, thereby minimizing communication of the multiple processed light beams from the containment chamber; repeatedly propagating the multiple processed light beams in the containment chamber along a predetermined reflective light path extending from the secondary back face at a first predetermined angle, through the multiple lateral faces at a generally normal angle to corresponding substantially parallel multiple reflective surfaces, and repeatedly back to the secondary back face at a second predetermined angle effective to reflect the multiple processed light beams from the secondary back face at the first predetermined angle; the multiple processed light beams thereby repeatedly imparting linear momentum to the multiple reflective surfaces communicating with an energy system. 2. The method of claim 1 further comprising:
directing an additional light beam into the light expander/contractor device, thereby expanding, reflecting, contracting, and redirecting the additional light beam upon itself, producing an additional processed light beam; compressing the secondary back face of the secondary prism relative to the primary back face of the primary prism, forming the transparent interface therebetween; communicating the additional processed light beam through the transparent interface from the primary prism into the secondary prism, splitting the additional processed light beam multiple times into multiple additional processed light beams comprising a higher power output than the additional light beam; decompressing the secondary back face relative to the primary back face of the primary prism after communicating the multiple additional processed light beams into the containment chamber, thereby minimizing communication of the multiple additional processed light beams from the containment chamber; repeatedly propagating the multiple additional processed light beams along the predetermined light path, thereby repeatedly imparting additional linear momentum to the multiple reflective surfaces communicating with the energy system. 3. The method of claim 2 wherein the energy system produces mechanical work. 4. The method of claim 3 wherein the energy system is a crank shaft assembly and the linear momentum imparted to the multiple reflective surfaces causes the crank shaft assembly to reciprocate. 5. The method of claim 2 wherein the energy system is a spring device. 6. The method of claim 2 further comprising performing the method substantially simultaneously in multiple cylinders comprising multiple containment chambers. 7. A method of operating a photon engine to produce linear momentum, the method comprising:
positioning a primary back face of a primary prism comprising a first transparent optical medium having a first index of refraction adjacent to and spaced apart from a secondary back face of a secondary prism comprising a second transparent optical medium having a second index of refraction, the secondary prism comprising multiple lateral faces; providing a containment chamber comprising the secondary prism and multiple reflective surfaces oriented substantially parallel to corresponding multiple lateral faces; collecting and concentrating light using one or more collective mirrors to produce concentrated light; communicating the concentrated light to the primary prism; compressing the secondary back face of the secondary prism relative to the primary back face of the primary prism, forming a transparent interface therebetween; communicating the concentrated light through the transparent interface from the primary prism into the secondary prism, splitting the concentrated light multiple times into multiple concentrated light beams comprising a higher power output than the light beam; decompressing the secondary back face relative to the primary back face of the primary prism after communicating the multiple concentrated light beams into the containment chamber, thereby minimizing communication of the multiple concentrated light beams from the containment chamber; repeatedly propagating the multiple concentrated light beams in the containment chamber along a predetermined reflective light path extending from the secondary back face at a first predetermined angle, through the multiple lateral faces at a generally normal angle to corresponding substantially parallel multiple reflective surfaces, and repeatedly back to the secondary back face at a second predetermined angle effective to reflect the multiple concentrated light beams from the secondary back face at the first predetermined angle; the multiple concentrated light beams thereby repeatedly imparting linear momentum to the multiple reflective surfaces communicating with an energy system. 8. The method of claim 7 further comprising:
collecting additional concentrated light in the primary prism; recompressing the secondary back face of the secondary prism relative to the primary back face of the primary prism, thereby reforming the transparent interface therebetween and communicating the additional concentrated light through the transparent interface from the primary prism into the secondary prism, splitting the additional concentrated light into multiple additional concentrated light beams comprising a higher power output than the additional light beam; and, repeatedly propagating the multiple additional concentrated light beams along the predetermined light path, thereby repeatedly imparting additional linear momentum to the multiple reflective surfaces communicating with the energy system. 9. The method of claim 8 wherein the energy system produces mechanical work. 10. The method of claim 9 wherein the energy system is a crank shaft assembly and the linear momentum imparted to the multiple reflective surfaces causes the crank shaft assembly to reciprocate. 11. The method of claim 8 wherein the energy system is a spring device. 12. The method of claim 8 comprising performing the method substantially simultaneously in multiple cylinders comprising multiple containment chambers. 13. A method of operating a photon engine to produce linear momentum, the method comprising:
positioning a primary back face of a primary prism comprising a first transparent optical medium having a first index of refraction adjacent to and spaced apart from a secondary back face of a secondary prism comprising a second transparent optical medium having a second index of refraction, the secondary prism comprising multiple lateral faces; providing a containment chamber comprising the secondary prism and multiple reflective surfaces oriented substantially parallel to corresponding multiple lateral faces; collecting and concentrating light using one or more collective mirrors to produce concentrated light; directing the concentrated light into a light expander/contractor device communicating with the primary prism, thereby expanding, reflecting, contracting, and redirecting the concentrated light upon itself, producing processed concentrated light; compressing the secondary back face of the secondary prism relative to the primary back face of the primary prism, forming a transparent interface therebetween; communicating the processed concentrated light through the transparent interface from the primary prism into the secondary prism, splitting the processed concentrated light multiple times into multiple processed concentrated light beams comprising a higher power output than the processed concentrated light; decompressing the secondary back face relative to the primary back face of the primary prism after communicating the multiple processed concentrated light beams into the containment chamber, thereby minimizing communication of the multiple processed concentrated light beams from the containment chamber; repeatedly propagating the multiple processed concentrated light beams in the containment chamber along a predetermined reflective light path extending from the secondary back face at a first predetermined angle, through the multiple lateral faces at a generally normal angle to corresponding substantially parallel multiple reflective surfaces, and repeatedly back to the secondary back face at a second predetermined angle effective to reflect the multiple processed concentrated light beams from the secondary back face at the first predetermined angle; the multiple processed concentrated light beams thereby repeatedly imparting linear momentum to the multiple reflective surfaces communicating with an energy system. 14. The method of claim 13 further comprising:
directing additional concentrated into the light expander/contractor device, thereby expanding, reflecting, contracting, and redirecting the additional concentrated light beam upon itself, producing an additional processed concentrated light beam; compressing the secondary back face of the secondary prism relative to the primary back face of the primary prism, forming the transparent interface therebetween; communicating the additional processed concentrated light beam through the transparent interface from the primary prism into the secondary prism, splitting the additional processed concentrated light beam multiple times into multiple additional processed concentrated light beams comprising a higher power output than the additional processed concentrated light beam; decompressing the secondary back face relative to the primary back face of the primary prism after communicating the multiple additional processed concentrated light beams into the containment chamber, thereby minimizing communication of the multiple additional processed concentrated light beams from the containment chamber; repeatedly propagating the multiple additional processed concentrated light beams along the predetermined light path, thereby repeatedly imparting additional linear momentum to the multiple reflective surfaces communicating with the energy system. 15. The method of claim 14 wherein the energy system produces mechanical work. 16. The method of claim 15 wherein the energy system is a crank shaft assembly and the linear momentum imparted to the multiple reflective surfaces causes the crank shaft assembly to reciprocate. 17. The method of claim 14 wherein the energy system is a spring device. 18. The method of claim 14 further comprising performing the method substantially simultaneously in multiple cylinders comprising multiple containment chambers. 19. A photon engine comprising one or more cylinders comprising:
a primary prism comprising polished crystalline quartz having a first index of refraction, the primary prism comprising one or more light beam inlets and a primary back face; one or more light expander/contractor devices communicating with the one or more light beam inlets, the one or more light expander/contractor devices being adapted to expand, reflect, and contract a light beam and to redirect the light beam upon itself, thereby producing a processed light beam; a secondary prism comprising polished crystalline quartz having a second index of refraction that is substantially the same as the first index of refraction, the secondary prism comprising multiple lateral faces and having a secondary back face positioned adjacent to and spaced apart from the primary back face, forming a non-transparent interface therebetween; a piezoelectric actuator operatively coupled with the primary prism and/or the secondary prism and adapted to compress the secondary back face relative to the primary back face to form a transparent interface therebetween adapted to transmit the processed light beam from the primary prism to the secondary prism and to split the processed light beam multiple times, producing multiple processed light beams comprising a higher power output than the light beam; and, a containment chamber comprising the secondary prism and multiple reflective surfaces separated from and oriented substantially parallel to corresponding multiple lateral faces, the containment chamber being adapted to contain propagation of the multiple processed light beams along a predetermined reflective light path extending from the secondary back face at a first predetermined angle, through the multiple lateral faces at a generally normal angle to the corresponding substantially parallel multiple reflective surfaces, and repeatedly back to the secondary back face at a second predetermined angle adapted to reflect the multiple processed light beams from the secondary back face at the first predetermined angle; wherein the multiple reflective surfaces communicate with an energy system. 20. The photon engine of claim 19 wherein the energy system is a piston and a crank shaft assembly. 21. The photon engine of claim 19 wherein the energy system is a spring device. 22. The photon engine of claim 19 wherein:
the first index of refraction is greater than 1.45; and, the second index of refraction is greater than 1.45. 23. The photon engine of claim 19 comprising multiple cylinders. 24. A photon engine comprising one or more cylinders, each comprising:
a primary prism comprising polished crystalline quartz having a first index of refraction and comprising a primary back face, the primary prism communicating with one or more collective mirrors comprising one or more reflective surfaces adapted to collect and concentrate light and to communicate concentrated light to the primary prism; a secondary prism comprising polished crystalline quartz having a second index of refraction that is substantially the same as the first index of refraction, the secondary prism comprising multiple lateral faces and having a secondary back face positioned adjacent to and spaced apart from the primary back face; a piezoelectric actuator operatively coupled with the primary prism and/or the secondary prism and adapted to compress the secondary back face relative to the primary back face to form a transparent interface therebetween adapted to transmit the concentrated light from the primary prism to the secondary prism and to split the concentrated light multiple times, producing multiple concentrated light beams comprising a higher power output than the concentrated light; and, a containment chamber comprising the secondary prism and multiple reflective surfaces separated from and oriented substantially parallel to corresponding multiple lateral faces, the containment chamber being adapted to contain propagation of the multiple concentrated light beams along a predetermined reflective light path extending from the secondary back face at a first predetermined angle, through the multiple lateral faces at a generally normal angle to corresponding substantially parallel multiple reflective surfaces, and repeatedly back to the secondary back face at a second predetermined angle adapted to reflect the multiple concentrated light beams from the secondary back face at the first predetermined angle; wherein the multiple reflective surfaces communicate with an energy system. 25. The photon engine of claim 24 wherein the energy system is a piston and a crank shaft assembly. 26. The photon engine of claim 24 wherein the energy system is a spring device. 27. The photon engine of claim 24 wherein:
the first index of refraction is greater than 1.45; and, the second index of refraction is greater than 1.45. 28. The photon engine of claim 24 comprising multiple cylinders. 29. A photon engine comprising:
a primary prism comprising polished crystalline quartz having a first index of refraction, the primary prism comprising a primary back face and communicating with one or more light beam inlets; the one or more light beam inlets communicating with one or more collective mirrors comprising one or more reflective surfaces adapted to collect and produce concentrated light; a light expander/contractor device communicating with the concentrated light, the light expander/contractor device being adapted to expand, reflect, and contract the concentrated light and to redirect the concentrated light upon itself, producing processed concentrated light; a secondary prism comprising polished crystalline quartz having a second index of refraction that is substantially the same as the first index of refraction, the secondary prism comprising multiple lateral faces and having a secondary back face positioned adjacent to and spaced apart from the primary back face, forming a non-transparent interface therebetween; a piezoelectric actuator operatively coupled with the primary prism and/or the secondary prism and adapted to compress the secondary back face relative to the primary back face and to form a transparent interface therebetween effective to communicate the processed concentrated light from the primary prism to the secondary prism and to split the processed concentrated light multiple times, producing multiple processed concentrated light beams comprising a higher power output than the concentrated light; and, a containment chamber comprising the secondary prism and multiple reflective surfaces separated from and oriented substantially parallel to corresponding multiple lateral faces, the containment chamber being adapted to contain propagation of the multiple processed concentrated light beams along a predetermined reflective light path extending from the secondary back face at a first predetermined angle, through the multiple lateral faces at a generally normal angle to the corresponding multiple reflective surfaces, and repeatedly back to the secondary back face at a second predetermined angle effective to reflect the multiple processed concentrated light beams from the secondary back face at the first predetermined angle; wherein the multiple reflective surfaces communicate with an energy system. 30. The photon engine of claim 29 wherein the energy system is a piston and a crank shaft assembly. 31. The photon engine of claim 29 wherein the energy system is a spring device. 32. The photon engine of claim 29 wherein:
the first index of refraction is greater than 1.45; and, the second index of refraction is greater than 1.45. 33. The photon engine of claim 29 comprising multiple cylinders. | A photon engine and variations thereof and methods of operating the photon engines, the photon engines comprising a primary prism and a secondary prism, the method and apparatus repeatedly imparting linear momentum to multiple reflective surfaces of the photon engine communicating with an energy system.1. A method of operating a photon engine to produce linear momentum, the method comprising:
positioning a primary back face of a primary prism comprising a first transparent optical medium having a first index of refraction adjacent to and spaced apart from a secondary back face of a secondary prism comprising a second transparent optical medium having a second index of refraction, the secondary prism comprising multiple lateral faces; providing a containment chamber comprising the secondary prism and multiple reflective surfaces oriented substantially parallel to corresponding multiple lateral faces; directing a light beam into a light expander/contractor device communicating with the primary prism, thereby expanding, reflecting, contracting, and redirecting the light beam upon itself, producing a processed light beam; compressing the secondary back face of the secondary prism relative to the primary back face of the primary prism, forming a transparent interface therebetween; communicating the processed light beam through the transparent interface from the primary prism into the secondary prism, splitting the processed light beam multiple times into multiple processed light beams comprising a higher power output than the light beam; decompressing the secondary back face relative to the primary back face of the primary prism after communicating the multiple processed light beams into the containment chamber, thereby minimizing communication of the multiple processed light beams from the containment chamber; repeatedly propagating the multiple processed light beams in the containment chamber along a predetermined reflective light path extending from the secondary back face at a first predetermined angle, through the multiple lateral faces at a generally normal angle to corresponding substantially parallel multiple reflective surfaces, and repeatedly back to the secondary back face at a second predetermined angle effective to reflect the multiple processed light beams from the secondary back face at the first predetermined angle; the multiple processed light beams thereby repeatedly imparting linear momentum to the multiple reflective surfaces communicating with an energy system. 2. The method of claim 1 further comprising:
directing an additional light beam into the light expander/contractor device, thereby expanding, reflecting, contracting, and redirecting the additional light beam upon itself, producing an additional processed light beam; compressing the secondary back face of the secondary prism relative to the primary back face of the primary prism, forming the transparent interface therebetween; communicating the additional processed light beam through the transparent interface from the primary prism into the secondary prism, splitting the additional processed light beam multiple times into multiple additional processed light beams comprising a higher power output than the additional light beam; decompressing the secondary back face relative to the primary back face of the primary prism after communicating the multiple additional processed light beams into the containment chamber, thereby minimizing communication of the multiple additional processed light beams from the containment chamber; repeatedly propagating the multiple additional processed light beams along the predetermined light path, thereby repeatedly imparting additional linear momentum to the multiple reflective surfaces communicating with the energy system. 3. The method of claim 2 wherein the energy system produces mechanical work. 4. The method of claim 3 wherein the energy system is a crank shaft assembly and the linear momentum imparted to the multiple reflective surfaces causes the crank shaft assembly to reciprocate. 5. The method of claim 2 wherein the energy system is a spring device. 6. The method of claim 2 further comprising performing the method substantially simultaneously in multiple cylinders comprising multiple containment chambers. 7. A method of operating a photon engine to produce linear momentum, the method comprising:
positioning a primary back face of a primary prism comprising a first transparent optical medium having a first index of refraction adjacent to and spaced apart from a secondary back face of a secondary prism comprising a second transparent optical medium having a second index of refraction, the secondary prism comprising multiple lateral faces; providing a containment chamber comprising the secondary prism and multiple reflective surfaces oriented substantially parallel to corresponding multiple lateral faces; collecting and concentrating light using one or more collective mirrors to produce concentrated light; communicating the concentrated light to the primary prism; compressing the secondary back face of the secondary prism relative to the primary back face of the primary prism, forming a transparent interface therebetween; communicating the concentrated light through the transparent interface from the primary prism into the secondary prism, splitting the concentrated light multiple times into multiple concentrated light beams comprising a higher power output than the light beam; decompressing the secondary back face relative to the primary back face of the primary prism after communicating the multiple concentrated light beams into the containment chamber, thereby minimizing communication of the multiple concentrated light beams from the containment chamber; repeatedly propagating the multiple concentrated light beams in the containment chamber along a predetermined reflective light path extending from the secondary back face at a first predetermined angle, through the multiple lateral faces at a generally normal angle to corresponding substantially parallel multiple reflective surfaces, and repeatedly back to the secondary back face at a second predetermined angle effective to reflect the multiple concentrated light beams from the secondary back face at the first predetermined angle; the multiple concentrated light beams thereby repeatedly imparting linear momentum to the multiple reflective surfaces communicating with an energy system. 8. The method of claim 7 further comprising:
collecting additional concentrated light in the primary prism; recompressing the secondary back face of the secondary prism relative to the primary back face of the primary prism, thereby reforming the transparent interface therebetween and communicating the additional concentrated light through the transparent interface from the primary prism into the secondary prism, splitting the additional concentrated light into multiple additional concentrated light beams comprising a higher power output than the additional light beam; and, repeatedly propagating the multiple additional concentrated light beams along the predetermined light path, thereby repeatedly imparting additional linear momentum to the multiple reflective surfaces communicating with the energy system. 9. The method of claim 8 wherein the energy system produces mechanical work. 10. The method of claim 9 wherein the energy system is a crank shaft assembly and the linear momentum imparted to the multiple reflective surfaces causes the crank shaft assembly to reciprocate. 11. The method of claim 8 wherein the energy system is a spring device. 12. The method of claim 8 comprising performing the method substantially simultaneously in multiple cylinders comprising multiple containment chambers. 13. A method of operating a photon engine to produce linear momentum, the method comprising:
positioning a primary back face of a primary prism comprising a first transparent optical medium having a first index of refraction adjacent to and spaced apart from a secondary back face of a secondary prism comprising a second transparent optical medium having a second index of refraction, the secondary prism comprising multiple lateral faces; providing a containment chamber comprising the secondary prism and multiple reflective surfaces oriented substantially parallel to corresponding multiple lateral faces; collecting and concentrating light using one or more collective mirrors to produce concentrated light; directing the concentrated light into a light expander/contractor device communicating with the primary prism, thereby expanding, reflecting, contracting, and redirecting the concentrated light upon itself, producing processed concentrated light; compressing the secondary back face of the secondary prism relative to the primary back face of the primary prism, forming a transparent interface therebetween; communicating the processed concentrated light through the transparent interface from the primary prism into the secondary prism, splitting the processed concentrated light multiple times into multiple processed concentrated light beams comprising a higher power output than the processed concentrated light; decompressing the secondary back face relative to the primary back face of the primary prism after communicating the multiple processed concentrated light beams into the containment chamber, thereby minimizing communication of the multiple processed concentrated light beams from the containment chamber; repeatedly propagating the multiple processed concentrated light beams in the containment chamber along a predetermined reflective light path extending from the secondary back face at a first predetermined angle, through the multiple lateral faces at a generally normal angle to corresponding substantially parallel multiple reflective surfaces, and repeatedly back to the secondary back face at a second predetermined angle effective to reflect the multiple processed concentrated light beams from the secondary back face at the first predetermined angle; the multiple processed concentrated light beams thereby repeatedly imparting linear momentum to the multiple reflective surfaces communicating with an energy system. 14. The method of claim 13 further comprising:
directing additional concentrated into the light expander/contractor device, thereby expanding, reflecting, contracting, and redirecting the additional concentrated light beam upon itself, producing an additional processed concentrated light beam; compressing the secondary back face of the secondary prism relative to the primary back face of the primary prism, forming the transparent interface therebetween; communicating the additional processed concentrated light beam through the transparent interface from the primary prism into the secondary prism, splitting the additional processed concentrated light beam multiple times into multiple additional processed concentrated light beams comprising a higher power output than the additional processed concentrated light beam; decompressing the secondary back face relative to the primary back face of the primary prism after communicating the multiple additional processed concentrated light beams into the containment chamber, thereby minimizing communication of the multiple additional processed concentrated light beams from the containment chamber; repeatedly propagating the multiple additional processed concentrated light beams along the predetermined light path, thereby repeatedly imparting additional linear momentum to the multiple reflective surfaces communicating with the energy system. 15. The method of claim 14 wherein the energy system produces mechanical work. 16. The method of claim 15 wherein the energy system is a crank shaft assembly and the linear momentum imparted to the multiple reflective surfaces causes the crank shaft assembly to reciprocate. 17. The method of claim 14 wherein the energy system is a spring device. 18. The method of claim 14 further comprising performing the method substantially simultaneously in multiple cylinders comprising multiple containment chambers. 19. A photon engine comprising one or more cylinders comprising:
a primary prism comprising polished crystalline quartz having a first index of refraction, the primary prism comprising one or more light beam inlets and a primary back face; one or more light expander/contractor devices communicating with the one or more light beam inlets, the one or more light expander/contractor devices being adapted to expand, reflect, and contract a light beam and to redirect the light beam upon itself, thereby producing a processed light beam; a secondary prism comprising polished crystalline quartz having a second index of refraction that is substantially the same as the first index of refraction, the secondary prism comprising multiple lateral faces and having a secondary back face positioned adjacent to and spaced apart from the primary back face, forming a non-transparent interface therebetween; a piezoelectric actuator operatively coupled with the primary prism and/or the secondary prism and adapted to compress the secondary back face relative to the primary back face to form a transparent interface therebetween adapted to transmit the processed light beam from the primary prism to the secondary prism and to split the processed light beam multiple times, producing multiple processed light beams comprising a higher power output than the light beam; and, a containment chamber comprising the secondary prism and multiple reflective surfaces separated from and oriented substantially parallel to corresponding multiple lateral faces, the containment chamber being adapted to contain propagation of the multiple processed light beams along a predetermined reflective light path extending from the secondary back face at a first predetermined angle, through the multiple lateral faces at a generally normal angle to the corresponding substantially parallel multiple reflective surfaces, and repeatedly back to the secondary back face at a second predetermined angle adapted to reflect the multiple processed light beams from the secondary back face at the first predetermined angle; wherein the multiple reflective surfaces communicate with an energy system. 20. The photon engine of claim 19 wherein the energy system is a piston and a crank shaft assembly. 21. The photon engine of claim 19 wherein the energy system is a spring device. 22. The photon engine of claim 19 wherein:
the first index of refraction is greater than 1.45; and, the second index of refraction is greater than 1.45. 23. The photon engine of claim 19 comprising multiple cylinders. 24. A photon engine comprising one or more cylinders, each comprising:
a primary prism comprising polished crystalline quartz having a first index of refraction and comprising a primary back face, the primary prism communicating with one or more collective mirrors comprising one or more reflective surfaces adapted to collect and concentrate light and to communicate concentrated light to the primary prism; a secondary prism comprising polished crystalline quartz having a second index of refraction that is substantially the same as the first index of refraction, the secondary prism comprising multiple lateral faces and having a secondary back face positioned adjacent to and spaced apart from the primary back face; a piezoelectric actuator operatively coupled with the primary prism and/or the secondary prism and adapted to compress the secondary back face relative to the primary back face to form a transparent interface therebetween adapted to transmit the concentrated light from the primary prism to the secondary prism and to split the concentrated light multiple times, producing multiple concentrated light beams comprising a higher power output than the concentrated light; and, a containment chamber comprising the secondary prism and multiple reflective surfaces separated from and oriented substantially parallel to corresponding multiple lateral faces, the containment chamber being adapted to contain propagation of the multiple concentrated light beams along a predetermined reflective light path extending from the secondary back face at a first predetermined angle, through the multiple lateral faces at a generally normal angle to corresponding substantially parallel multiple reflective surfaces, and repeatedly back to the secondary back face at a second predetermined angle adapted to reflect the multiple concentrated light beams from the secondary back face at the first predetermined angle; wherein the multiple reflective surfaces communicate with an energy system. 25. The photon engine of claim 24 wherein the energy system is a piston and a crank shaft assembly. 26. The photon engine of claim 24 wherein the energy system is a spring device. 27. The photon engine of claim 24 wherein:
the first index of refraction is greater than 1.45; and, the second index of refraction is greater than 1.45. 28. The photon engine of claim 24 comprising multiple cylinders. 29. A photon engine comprising:
a primary prism comprising polished crystalline quartz having a first index of refraction, the primary prism comprising a primary back face and communicating with one or more light beam inlets; the one or more light beam inlets communicating with one or more collective mirrors comprising one or more reflective surfaces adapted to collect and produce concentrated light; a light expander/contractor device communicating with the concentrated light, the light expander/contractor device being adapted to expand, reflect, and contract the concentrated light and to redirect the concentrated light upon itself, producing processed concentrated light; a secondary prism comprising polished crystalline quartz having a second index of refraction that is substantially the same as the first index of refraction, the secondary prism comprising multiple lateral faces and having a secondary back face positioned adjacent to and spaced apart from the primary back face, forming a non-transparent interface therebetween; a piezoelectric actuator operatively coupled with the primary prism and/or the secondary prism and adapted to compress the secondary back face relative to the primary back face and to form a transparent interface therebetween effective to communicate the processed concentrated light from the primary prism to the secondary prism and to split the processed concentrated light multiple times, producing multiple processed concentrated light beams comprising a higher power output than the concentrated light; and, a containment chamber comprising the secondary prism and multiple reflective surfaces separated from and oriented substantially parallel to corresponding multiple lateral faces, the containment chamber being adapted to contain propagation of the multiple processed concentrated light beams along a predetermined reflective light path extending from the secondary back face at a first predetermined angle, through the multiple lateral faces at a generally normal angle to the corresponding multiple reflective surfaces, and repeatedly back to the secondary back face at a second predetermined angle effective to reflect the multiple processed concentrated light beams from the secondary back face at the first predetermined angle; wherein the multiple reflective surfaces communicate with an energy system. 30. The photon engine of claim 29 wherein the energy system is a piston and a crank shaft assembly. 31. The photon engine of claim 29 wherein the energy system is a spring device. 32. The photon engine of claim 29 wherein:
the first index of refraction is greater than 1.45; and, the second index of refraction is greater than 1.45. 33. The photon engine of claim 29 comprising multiple cylinders. | 2,800 |
11,993 | 11,993 | 14,766,346 | 2,865 | A method, system, and sensor for air flow sensing. The system can include a cantilever, a transducer, and a processing module. The method can include measuring beam deflections of one or more cantilevers, extracting information about air flow, and determining one or more of an airspeed, an angle of attack, and a sideslip, based on extracted information. The system and method can exploit nonlinearities in the behavior of the cantilever in fluid flow. | 1. A method for air flow sensing, comprising:
measuring beam deflections of a cantilever; extracting information about air flow; and determining one or more of an airspeed, an angle of attack, and a sideslip, from the extracted information. 2. The method of claim 1, further comprising generating calibration data from bending amplitudes or torsion amplitudes of the cantilever, wherein one or more of the bending amplitudes and the torsion amplitudes corresponds to a freestream velocity and the angle of attack, wherein the calibration data is used in the determining step. 3. The method of claim 1, wherein the cantilever comprises a cantilever surface;
wherein measuring beam deflections comprises measuring deformation of the cantilever surface; and wherein determining the airspeed and the angle of attack comprises an unsteady vortex lattice method, solving beam displacements and rotation, and determining convergence with one or more criteria. 4. The method of claim 3, wherein the unsteady vortex lattice method comprises:
discretizing the cantilever surface into a lattice of vortex rings; imposing a no-penetration condition at collocation points; computing velocities; introducing voracity to wakes; evaluating pressure at the collocation points; and integrating over the cantilever surface. 5. The method of claim 1, wherein determining the airspeed and the angle of attack further comprises solving potential flow based on an unsteady vortex lattice method. 6. The method of claim 1, wherein determining the airspeed and the angle of attack are based on a nonlinear displacement beam model. 7. The airflow sensing system of claim 1, further comprising: measuring deformation of the cantilever surface. 8. The airflow sensing system of claim 7, wherein deformation of the cantilever surface is due to beam displacement or rotation or both. 9. The airflow sensing system of claim 8, further comprising: iteratively determining whether convergence has been achieved 10. The airflow sensing system of claim 1, further comprising: iteratively determine whether convergence has been achieved. 11. An airflow sensing system for measuring flight data, comprising:
a cantilever having a cantilever surface, the cantilever being positioned on a surface of a vehicle; a transducer configured to detected deflections of the cantilever and produce an output based the deflections; a processing module in communication with the cantilever; wherein the processing module is calibrated to translate the output from the transducer into one or more of an airspeed, an angle of attack, and a sideslip. 12. The airflow sensing system of claim 11, wherein the cantilever is configured to be supercritical beyond the Hopf bifurcation point for providing a stable response to a disturbance below a flutter boundary. 13. The airflow sensing system of claim 11, further comprising:
at least one more cantilever; at least one more transducer configured to detected deflections of the at least one more cantilever and produce at least one more output to the processing module. 14. The airflow sensing system of claim 13, wherein the cantilever and the at least one more cantilever comprise a cantilever array. 15. The airflow sensing system of claim 14, wherein the cantilever array is a two-dimensional array with each of the two dimensions less than twenty centimeters. 16. The airflow sensing system of claim 15, wherein each of the two dimensions less than ten centimeters. 17. The airflow sensing system of claim 15, wherein each of the two dimensions less than three centimeters. 18. The airflow sensing system of claim 15, wherein each of the two dimensions less than one centimeter. 19. The airflow sensing system of claim 11, wherein the processing module is configured to determine the airspeed and the angle of attack based on calibration data generated from bending amplitudes and/or torsion amplitudes of the cantilever, wherein one or more of the bending amplitudes and the torsion amplitudes corresponds to a freestream velocity and/or the angle of attack. 20. The airflow sensing system of claim 11, wherein the processing module is configured to measure deformation of the cantilever surface. 21. The airflow sensing system of claim 20, wherein deformation of the cantilever surface includes beam displacement or rotation or both. 22. The airflow sensing system of claim 21, wherein the processing module is configured to iteratively determine whether convergence has been achieved 23. The airflow sensing system of claim 11, wherein the processing module is configured to iteratively determine whether convergence has been achieved. 24. The airflow sensing system of claim 11, wherein the processing module is configured to:
discretize the surface into a lattice of vortex rings; impose a no-penetration condition at collocation points; compute velocities; introduce vorticity to wakes; evaluate pressure at the collocation points; and integrate over the surface. 25. The airflow sensing system of claim 11, wherein the cantilever has three mutually orthogonal dimensions, and wherein the longest dimension of the cantilever is less than ten centimeters. 26. The airflow sensing system of claim 11, wherein the longest dimension of the cantilever is less than three centimeters. 27. The airflow sensing system of claim 11, wherein the longest dimension of the cantilever is less than one centimeter. 28. The airflow sensing system of claim 11, wherein the longest dimension of the cantilever is less than one millimeter. | A method, system, and sensor for air flow sensing. The system can include a cantilever, a transducer, and a processing module. The method can include measuring beam deflections of one or more cantilevers, extracting information about air flow, and determining one or more of an airspeed, an angle of attack, and a sideslip, based on extracted information. The system and method can exploit nonlinearities in the behavior of the cantilever in fluid flow.1. A method for air flow sensing, comprising:
measuring beam deflections of a cantilever; extracting information about air flow; and determining one or more of an airspeed, an angle of attack, and a sideslip, from the extracted information. 2. The method of claim 1, further comprising generating calibration data from bending amplitudes or torsion amplitudes of the cantilever, wherein one or more of the bending amplitudes and the torsion amplitudes corresponds to a freestream velocity and the angle of attack, wherein the calibration data is used in the determining step. 3. The method of claim 1, wherein the cantilever comprises a cantilever surface;
wherein measuring beam deflections comprises measuring deformation of the cantilever surface; and wherein determining the airspeed and the angle of attack comprises an unsteady vortex lattice method, solving beam displacements and rotation, and determining convergence with one or more criteria. 4. The method of claim 3, wherein the unsteady vortex lattice method comprises:
discretizing the cantilever surface into a lattice of vortex rings; imposing a no-penetration condition at collocation points; computing velocities; introducing voracity to wakes; evaluating pressure at the collocation points; and integrating over the cantilever surface. 5. The method of claim 1, wherein determining the airspeed and the angle of attack further comprises solving potential flow based on an unsteady vortex lattice method. 6. The method of claim 1, wherein determining the airspeed and the angle of attack are based on a nonlinear displacement beam model. 7. The airflow sensing system of claim 1, further comprising: measuring deformation of the cantilever surface. 8. The airflow sensing system of claim 7, wherein deformation of the cantilever surface is due to beam displacement or rotation or both. 9. The airflow sensing system of claim 8, further comprising: iteratively determining whether convergence has been achieved 10. The airflow sensing system of claim 1, further comprising: iteratively determine whether convergence has been achieved. 11. An airflow sensing system for measuring flight data, comprising:
a cantilever having a cantilever surface, the cantilever being positioned on a surface of a vehicle; a transducer configured to detected deflections of the cantilever and produce an output based the deflections; a processing module in communication with the cantilever; wherein the processing module is calibrated to translate the output from the transducer into one or more of an airspeed, an angle of attack, and a sideslip. 12. The airflow sensing system of claim 11, wherein the cantilever is configured to be supercritical beyond the Hopf bifurcation point for providing a stable response to a disturbance below a flutter boundary. 13. The airflow sensing system of claim 11, further comprising:
at least one more cantilever; at least one more transducer configured to detected deflections of the at least one more cantilever and produce at least one more output to the processing module. 14. The airflow sensing system of claim 13, wherein the cantilever and the at least one more cantilever comprise a cantilever array. 15. The airflow sensing system of claim 14, wherein the cantilever array is a two-dimensional array with each of the two dimensions less than twenty centimeters. 16. The airflow sensing system of claim 15, wherein each of the two dimensions less than ten centimeters. 17. The airflow sensing system of claim 15, wherein each of the two dimensions less than three centimeters. 18. The airflow sensing system of claim 15, wherein each of the two dimensions less than one centimeter. 19. The airflow sensing system of claim 11, wherein the processing module is configured to determine the airspeed and the angle of attack based on calibration data generated from bending amplitudes and/or torsion amplitudes of the cantilever, wherein one or more of the bending amplitudes and the torsion amplitudes corresponds to a freestream velocity and/or the angle of attack. 20. The airflow sensing system of claim 11, wherein the processing module is configured to measure deformation of the cantilever surface. 21. The airflow sensing system of claim 20, wherein deformation of the cantilever surface includes beam displacement or rotation or both. 22. The airflow sensing system of claim 21, wherein the processing module is configured to iteratively determine whether convergence has been achieved 23. The airflow sensing system of claim 11, wherein the processing module is configured to iteratively determine whether convergence has been achieved. 24. The airflow sensing system of claim 11, wherein the processing module is configured to:
discretize the surface into a lattice of vortex rings; impose a no-penetration condition at collocation points; compute velocities; introduce vorticity to wakes; evaluate pressure at the collocation points; and integrate over the surface. 25. The airflow sensing system of claim 11, wherein the cantilever has three mutually orthogonal dimensions, and wherein the longest dimension of the cantilever is less than ten centimeters. 26. The airflow sensing system of claim 11, wherein the longest dimension of the cantilever is less than three centimeters. 27. The airflow sensing system of claim 11, wherein the longest dimension of the cantilever is less than one centimeter. 28. The airflow sensing system of claim 11, wherein the longest dimension of the cantilever is less than one millimeter. | 2,800 |
11,994 | 11,994 | 14,120,486 | 2,853 | An improved device for exposing an emulsion-coated screen to light comprises an array of ultraviolet light-emitting diodes (UV-LEDs); a positive impression of the artwork to be printed; a relatively-flat transparent plate disposed between the array of UV-LEDs and the positive impression; a screen coated with a light-curable emulsion; the positive impression disposed on the side of the screen having the emulsion coat; a holding means, disposed on the side of the screen opposite the positive impression, for holding the screen in a planar position; and a means for electrically driving the UV-LEDs to emit ultraviolet light for a predetermined time period. The device can be formed into a compact device having a lid comprising the UV-LED array and a flat transparent plate of transparent material (such as glass), and driving and timing means for electrically driving the array of UV-LEDs to emit ultraviolet light for a predetermined period of time. | 1. A device for exposing an emulsion stratum to light comprising plural sources of ultraviolet light closely adjacent the emulsion stratum. 2. A device for exposing an emulsion-coated screen to light comprising plural ultraviolet light-emitting diodes closely adjacent the emulsion-coated screen. 3. Plural ultraviolet light-emitting diodes disposed in an array such that each diode's emission is aimed in the same direction and each diode's emission is aimed orthogonally with respect to the plane of the array; a flat stratum of emulsion that is disposed near and parallel to the array of diodes; and an image that is opaque to ultraviolet radiation disposed between the array of diodes and the flat stratum of emulsion. 4. Curing a layer of curable emulsion coated on a relatively flat screen by disposing over the emulsion layer a positive image of a design on a sheet, with the image comprising various transparent and opaque areas, and causing plural light sources to emit electromagnetic radiation in the direction of the emulsion, which radiation passes through only the transparent areas of the sheet, whereby only areas of the emulsion directly adjacent the transparent areas of the sheet are cured, and those areas of the sheet which are directly adjacent the opaque areas of the sheet remain uncured. 5. A device for curing an emulsion, comprising:
1) plural ultraviolet light sources, all arranged to direct the light produced in one direction; 2) a stratum of light-curable emulsion; 3) a positive image in or on a sheet comprising various areas of the sheet that are transparent and opaque, said transparent and opaque areas arranged in a design that comprises at least one of letters, numbers, symbols, art, a design, and a composition; 4) wherein the positive image is placed between the stratum of light-curable emulsion and the plural ultraviolet light sources, and the plural ultraviolet light sources are driven to emit ultraviolet light for a predetermined period of time, whereby the ultraviolet light passes through the transparent portions of the positive image and cures that part of the emulsion it strikes, and whereby the ultraviolet light that strikes the opaque portions of the positive image is absorbed by the positive image, leaving the part of the emulsion not, illuminated by the ultraviolet light uncured. 6. The device of claim 5 further comprising a flat sheet of hard transparent material interposed between the plural ultraviolet light sources and the positive image. 7. The device of claim 6 wherein the sheet of transparent material is one of glass and plastic. 8. An improved device for exposing an emulsion-coated screen to light comprises:
1) an array of ultraviolet light-emitting diodes (UV-LEDs); 2) a positive, impression of the artwork to be printed; 3) a relatively-flat transparent plate disposed between the array of UV-LEDs and the positive impression; 4) a screen coated with a light-curable emulsion; 5) the positive impression disposed on the side of the screen having the emulsion coat; a holding means, disposed on the side of the screen opposite the positive impression, for holding the screen in a planar position; and 6) a means for electrically driving the UV-LEDs to emit ultraviolet light for a predetermined time period. 9. A method comprising the steps of:
1) forming an emulsion into a stratum; and 2) curing at least a part of the emulsion stratum with ultraviolet light. 10. A method comprising the steps of;
1) disposing an emulsion onto a relatively flat screen; 2) disposing an array of ultraviolet light-emitting diodes such that the array of diodes is parallel to and adjacent the emulsion on the screen; 3) disposing an opaque image between the emulsion and the array of diodes; and 4) causing the array of diodes to emit ultraviolet light for a predetermined time. 11. The method of claim 10 wherein during the step of causing the array of light-emitting diodes to emit ultraviolet light for a predetermined time, all light-emitting diodes emit ultraviolet light simultaneously. 12. The method of claim 10 wherein during the step of causing the array of diodes to emit ultraviolet light for a predetermined time, all diodes emit ultraviolet light sequentially, such that at least one diode of the array emits ultraviolet light during a time period after at least one other diode of the array has emitted ultraviolet light. 13. A device for exposing an emulsion stratum to light comprising a light source which cures exposed emulsion in less than ten seconds. 14. A device for exposing an emulsion stratum to light comprising an emulsion-coated screen having a positive film disposed on top of it, and having a light source disposed over the positive film. 15. A device for exposing an emulsion stratum to light comprising:
1) an emulsion-coated screen; 2) a positive film disposed adjacent to the emulsion-coated screen; 3) a transparent plate; and 4) an array of individual light sources; wherein the array of individual light sources is disposed apart from, but very near to the emulsion-coated screen. 16. The device of claim 15 wherein the number of individual light sources exceeds 10. 17. The device of claim 15 wherein the number of individual light sources exceeds 20. 18. The device of claim 15 wherein the distance between the array of individual light sources and the plane of the emulsion-coated screen is substantially less than the length or width of the emulsion coating on the screen. 19. The device of claim 15 wherein the distance between the array of individual light sources and the plane of the emulsion-coated screen is ten inches or less. 20. The use of plural ultraviolet light emitting diodes in the curing of a photopolymer emulsion. | An improved device for exposing an emulsion-coated screen to light comprises an array of ultraviolet light-emitting diodes (UV-LEDs); a positive impression of the artwork to be printed; a relatively-flat transparent plate disposed between the array of UV-LEDs and the positive impression; a screen coated with a light-curable emulsion; the positive impression disposed on the side of the screen having the emulsion coat; a holding means, disposed on the side of the screen opposite the positive impression, for holding the screen in a planar position; and a means for electrically driving the UV-LEDs to emit ultraviolet light for a predetermined time period. The device can be formed into a compact device having a lid comprising the UV-LED array and a flat transparent plate of transparent material (such as glass), and driving and timing means for electrically driving the array of UV-LEDs to emit ultraviolet light for a predetermined period of time.1. A device for exposing an emulsion stratum to light comprising plural sources of ultraviolet light closely adjacent the emulsion stratum. 2. A device for exposing an emulsion-coated screen to light comprising plural ultraviolet light-emitting diodes closely adjacent the emulsion-coated screen. 3. Plural ultraviolet light-emitting diodes disposed in an array such that each diode's emission is aimed in the same direction and each diode's emission is aimed orthogonally with respect to the plane of the array; a flat stratum of emulsion that is disposed near and parallel to the array of diodes; and an image that is opaque to ultraviolet radiation disposed between the array of diodes and the flat stratum of emulsion. 4. Curing a layer of curable emulsion coated on a relatively flat screen by disposing over the emulsion layer a positive image of a design on a sheet, with the image comprising various transparent and opaque areas, and causing plural light sources to emit electromagnetic radiation in the direction of the emulsion, which radiation passes through only the transparent areas of the sheet, whereby only areas of the emulsion directly adjacent the transparent areas of the sheet are cured, and those areas of the sheet which are directly adjacent the opaque areas of the sheet remain uncured. 5. A device for curing an emulsion, comprising:
1) plural ultraviolet light sources, all arranged to direct the light produced in one direction; 2) a stratum of light-curable emulsion; 3) a positive image in or on a sheet comprising various areas of the sheet that are transparent and opaque, said transparent and opaque areas arranged in a design that comprises at least one of letters, numbers, symbols, art, a design, and a composition; 4) wherein the positive image is placed between the stratum of light-curable emulsion and the plural ultraviolet light sources, and the plural ultraviolet light sources are driven to emit ultraviolet light for a predetermined period of time, whereby the ultraviolet light passes through the transparent portions of the positive image and cures that part of the emulsion it strikes, and whereby the ultraviolet light that strikes the opaque portions of the positive image is absorbed by the positive image, leaving the part of the emulsion not, illuminated by the ultraviolet light uncured. 6. The device of claim 5 further comprising a flat sheet of hard transparent material interposed between the plural ultraviolet light sources and the positive image. 7. The device of claim 6 wherein the sheet of transparent material is one of glass and plastic. 8. An improved device for exposing an emulsion-coated screen to light comprises:
1) an array of ultraviolet light-emitting diodes (UV-LEDs); 2) a positive, impression of the artwork to be printed; 3) a relatively-flat transparent plate disposed between the array of UV-LEDs and the positive impression; 4) a screen coated with a light-curable emulsion; 5) the positive impression disposed on the side of the screen having the emulsion coat; a holding means, disposed on the side of the screen opposite the positive impression, for holding the screen in a planar position; and 6) a means for electrically driving the UV-LEDs to emit ultraviolet light for a predetermined time period. 9. A method comprising the steps of:
1) forming an emulsion into a stratum; and 2) curing at least a part of the emulsion stratum with ultraviolet light. 10. A method comprising the steps of;
1) disposing an emulsion onto a relatively flat screen; 2) disposing an array of ultraviolet light-emitting diodes such that the array of diodes is parallel to and adjacent the emulsion on the screen; 3) disposing an opaque image between the emulsion and the array of diodes; and 4) causing the array of diodes to emit ultraviolet light for a predetermined time. 11. The method of claim 10 wherein during the step of causing the array of light-emitting diodes to emit ultraviolet light for a predetermined time, all light-emitting diodes emit ultraviolet light simultaneously. 12. The method of claim 10 wherein during the step of causing the array of diodes to emit ultraviolet light for a predetermined time, all diodes emit ultraviolet light sequentially, such that at least one diode of the array emits ultraviolet light during a time period after at least one other diode of the array has emitted ultraviolet light. 13. A device for exposing an emulsion stratum to light comprising a light source which cures exposed emulsion in less than ten seconds. 14. A device for exposing an emulsion stratum to light comprising an emulsion-coated screen having a positive film disposed on top of it, and having a light source disposed over the positive film. 15. A device for exposing an emulsion stratum to light comprising:
1) an emulsion-coated screen; 2) a positive film disposed adjacent to the emulsion-coated screen; 3) a transparent plate; and 4) an array of individual light sources; wherein the array of individual light sources is disposed apart from, but very near to the emulsion-coated screen. 16. The device of claim 15 wherein the number of individual light sources exceeds 10. 17. The device of claim 15 wherein the number of individual light sources exceeds 20. 18. The device of claim 15 wherein the distance between the array of individual light sources and the plane of the emulsion-coated screen is substantially less than the length or width of the emulsion coating on the screen. 19. The device of claim 15 wherein the distance between the array of individual light sources and the plane of the emulsion-coated screen is ten inches or less. 20. The use of plural ultraviolet light emitting diodes in the curing of a photopolymer emulsion. | 2,800 |
11,995 | 11,995 | 15,503,115 | 2,896 | Method and apparatus for hardware coil compression is disclosed. The coils in an array configured for the same region of interest are grouped into sub-arrays. The coils of each sub-array are pre-combined with a hardware combiner before further processing. The pre-combination converter composed of the pre-combiners is flexible, i.e., applicable to for example non-cylindrical coils; simpler than direct implementation of the software compression algorithm; and commercially feasible. | 1-13. (canceled) 14. A method of channel compression for magnetic resonance imaging (MRI), comprising:
pre-combining, using n′ pre-combiners, n outputs (C1, C2, . . . Cn) from n coils of an n coil array configured for imaging the same region of interest (ROI) to obtain fewer n′ pre-combination outputs, where n′ is an integer greater than 1, wherein the n coils are grouped into n′ sub-arrays based on an order of importance of each of the n coils represented by the contribution of the output of the coil to the signal-to-noise ratio (SNR) of the signal obtained by combining the outputs of the n coils and each pre-combiner is configured to pre-combine outputs from a respective one of the n′ sub-arrays to obtain one of the n′ pre-combination outputs; compressing the n′ pre-combination outputs of the n′ pre-combiners into fewer virtual outputs with highest signal-to-noise ratios (SNRs) for image reconstruction. 15. The method of claim 14, wherein the n coils are grouped into the n′ sub-arrays by:
ordering the n coils by the importance from the highest to the lowest;
assigning the first n′ coils of the n coils into the n′ sub-arrays, respectively;
and repeating the assignment of the remaining n−n′ coils until all the n coils are assigned. 16. The method of claim 14, wherein the sub-arrays and pre-combination coefficients for the sub-arrays are determined by:
constructing a channel conversion matrix M of n×n which converts signals s=(s1, s2, . . . , sn)T output from the coils of the array to conversion outputs s′=(s1′, s2′, . . . , sn′)T, s′=Ms, wherein T represents matrix transpose operation; selecting rows of the channel conversion matrix M corresponding to a number of conversion outputs with the highest signal-to-noise ratios (SNRs); and optimizing the pre-combination coefficients or both the grouping and the pre-combination coefficients such that the pre-combination coefficients span a space which approaches the space spanned by all or the selected rows of M. 17. The method of claim 16, wherein the channel conversion matrix is a whitening matrix. 18. An apparatus of channel compression for Magnetic Resonance Imaging (MRI) comprising a converter, the apparatus further comprising:
n′ pre-combiners configured to pre-combine n outputs (C1, C2, . . . Cn) from n coils of an n coil array configured for imaging the same region of interest (ROI) to obtain fewer n′ pre-combination outputs , where n′ is an integer greater than 1, wherein the n coils are grouped into n′ sub-arrays based on an order of importance of each of the n coils represented by the contribution of the output of the coil to the signal-to-noise ratio (SNR) of the signal obtained by combining the outputs of the n coils and each pre-combiner is configured to pre-combine outputs from one of the n′ sub-arrays to obtain one of the n′ pre-combination outputs, wherein the converter is coupled to the n′ pre-combiners and configured to compress the n′ pre-combination outputs into fewer virtual outputs with highest signal-to-noise ratios (SNRs) for image reconstruction. 19. The apparatus of claim 18, wherein the coils are grouped into sub-arrays by:
ordering the n coils by the importance from the highest to the lowest; assigning the first n′ coils of the n coils into the n′ sub-arrays, respectively; and repeating the assignment of the remaining n−n′ coils until all the n coils are assigned. 20. The apparatus of claim 18, wherein the sub-arrays and pre-combination coefficients for the sub-arrays are determined by:
constructing a channel conversion matrix M of n×n which converts signals s=(s1, s2, . . . , sn)T output from the coils of the array to conversion outputs s′=(s′1, s′2, . . . , sn′)T, s′=Ms, wherein T represents matrix transpose operation; selecting rows of the channel conversion matrix M corresponding to a number of conversion outputs with the highest signal-to-noise ratios (SNRs); and optimizing the pre-combination coefficients or both the grouping and the pre-combination coefficients such that the pre-combination coefficients span a space which approaches the space spanned by all or the selected rows of M. 21. The apparatus of claim 17, wherein the channel conversion matrix is a whitening matrix. 22. The apparatus of claim 18, wherein the converter further comprises:
a plurality of splitters configured to split each of the n′ pre-combination outputs to a number of output copies; a plurality of combiners coupled to the splitters and configured to combine the split output copies to the virtual outputs, wherein each combiner is characterized by a set of complex combination coefficients whose amplitudes represent amplitude weights and angles represent phase shifts. | Method and apparatus for hardware coil compression is disclosed. The coils in an array configured for the same region of interest are grouped into sub-arrays. The coils of each sub-array are pre-combined with a hardware combiner before further processing. The pre-combination converter composed of the pre-combiners is flexible, i.e., applicable to for example non-cylindrical coils; simpler than direct implementation of the software compression algorithm; and commercially feasible.1-13. (canceled) 14. A method of channel compression for magnetic resonance imaging (MRI), comprising:
pre-combining, using n′ pre-combiners, n outputs (C1, C2, . . . Cn) from n coils of an n coil array configured for imaging the same region of interest (ROI) to obtain fewer n′ pre-combination outputs, where n′ is an integer greater than 1, wherein the n coils are grouped into n′ sub-arrays based on an order of importance of each of the n coils represented by the contribution of the output of the coil to the signal-to-noise ratio (SNR) of the signal obtained by combining the outputs of the n coils and each pre-combiner is configured to pre-combine outputs from a respective one of the n′ sub-arrays to obtain one of the n′ pre-combination outputs; compressing the n′ pre-combination outputs of the n′ pre-combiners into fewer virtual outputs with highest signal-to-noise ratios (SNRs) for image reconstruction. 15. The method of claim 14, wherein the n coils are grouped into the n′ sub-arrays by:
ordering the n coils by the importance from the highest to the lowest;
assigning the first n′ coils of the n coils into the n′ sub-arrays, respectively;
and repeating the assignment of the remaining n−n′ coils until all the n coils are assigned. 16. The method of claim 14, wherein the sub-arrays and pre-combination coefficients for the sub-arrays are determined by:
constructing a channel conversion matrix M of n×n which converts signals s=(s1, s2, . . . , sn)T output from the coils of the array to conversion outputs s′=(s1′, s2′, . . . , sn′)T, s′=Ms, wherein T represents matrix transpose operation; selecting rows of the channel conversion matrix M corresponding to a number of conversion outputs with the highest signal-to-noise ratios (SNRs); and optimizing the pre-combination coefficients or both the grouping and the pre-combination coefficients such that the pre-combination coefficients span a space which approaches the space spanned by all or the selected rows of M. 17. The method of claim 16, wherein the channel conversion matrix is a whitening matrix. 18. An apparatus of channel compression for Magnetic Resonance Imaging (MRI) comprising a converter, the apparatus further comprising:
n′ pre-combiners configured to pre-combine n outputs (C1, C2, . . . Cn) from n coils of an n coil array configured for imaging the same region of interest (ROI) to obtain fewer n′ pre-combination outputs , where n′ is an integer greater than 1, wherein the n coils are grouped into n′ sub-arrays based on an order of importance of each of the n coils represented by the contribution of the output of the coil to the signal-to-noise ratio (SNR) of the signal obtained by combining the outputs of the n coils and each pre-combiner is configured to pre-combine outputs from one of the n′ sub-arrays to obtain one of the n′ pre-combination outputs, wherein the converter is coupled to the n′ pre-combiners and configured to compress the n′ pre-combination outputs into fewer virtual outputs with highest signal-to-noise ratios (SNRs) for image reconstruction. 19. The apparatus of claim 18, wherein the coils are grouped into sub-arrays by:
ordering the n coils by the importance from the highest to the lowest; assigning the first n′ coils of the n coils into the n′ sub-arrays, respectively; and repeating the assignment of the remaining n−n′ coils until all the n coils are assigned. 20. The apparatus of claim 18, wherein the sub-arrays and pre-combination coefficients for the sub-arrays are determined by:
constructing a channel conversion matrix M of n×n which converts signals s=(s1, s2, . . . , sn)T output from the coils of the array to conversion outputs s′=(s′1, s′2, . . . , sn′)T, s′=Ms, wherein T represents matrix transpose operation; selecting rows of the channel conversion matrix M corresponding to a number of conversion outputs with the highest signal-to-noise ratios (SNRs); and optimizing the pre-combination coefficients or both the grouping and the pre-combination coefficients such that the pre-combination coefficients span a space which approaches the space spanned by all or the selected rows of M. 21. The apparatus of claim 17, wherein the channel conversion matrix is a whitening matrix. 22. The apparatus of claim 18, wherein the converter further comprises:
a plurality of splitters configured to split each of the n′ pre-combination outputs to a number of output copies; a plurality of combiners coupled to the splitters and configured to combine the split output copies to the virtual outputs, wherein each combiner is characterized by a set of complex combination coefficients whose amplitudes represent amplitude weights and angles represent phase shifts. | 2,800 |
11,996 | 11,996 | 15,707,257 | 2,839 | A power converter circuit includes a power stage that includes a transformer and a switch. The switch can be controlled in response to a PWM signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage. The power stage includes a switching node between the switch and the primary winding having a switching voltage. The circuit also includes a switching controller configured to generate the PWM signal in response to a ramp signal. The ramp signal can have an amplitude of a slope that is proportional to a decay rate of a magnetizing current of the transformer and generated in response to feedback from the power stage. The switch can be activated in response to the switching voltage having an amplitude of approximately zero volts based on the amplitude of the ramp signal. | 1. A power converter circuit comprising:
a power stage comprising a transformer and a switch, the switch being controlled in response to a pulse-width modulation (PWM) signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage, the power stage comprising a switching node between the switch and the primary winding having a switching voltage; and a switching controller configured to generate the PWM signal in response to a ramp signal, the ramp signal having a slope that is proportional to a decay rate of a magnetizing current associated with the transformer and generated in response to at least one feedback voltage from the power stage, the switch being activated in response to the switching voltage having an amplitude of approximately zero volts based on the amplitude of the ramp signal. 2. The circuit of claim 1, wherein the transformer further comprises an auxiliary winding that is configured to generate an auxiliary voltage, wherein the switching controller comprises a sampling circuit configured to sample the auxiliary voltage, the ramp signal being generated based on the sampled auxiliary voltage. 3. The circuit of claim 2, wherein the switching controller comprises a ramp generator configured to generate the ramp signal, the ramp generator comprising a transconductance amplifier having a transconductance constant that is set via an external resistor and is configured to generate the ramp signal based on the sampled auxiliary voltage. 4. The circuit of claim 2, wherein the switching controller comprises a zero-voltage switching (ZVS) optimizer circuit configured to set a ramp threshold having an amplitude that is associated with the amplitude of the ramp signal that corresponds to a negative peak amplitude of the magnetizing current to set the switching voltage to approximately zero volts, such that the switching controller is configured to control the PWM signal to thereby activate the switch in response to the ramp signal increasing to approximately the amplitude of the ramp threshold. 5. The circuit of claim 1, wherein the PWM signal is a first PWM signal, and wherein the switch is a first switch, wherein the power stage further comprises an LC resonator formed by the primary winding and a capacitor and a second switch that is alternately activated via a second PWM signal to circulate the magnetizing current via the LC resonator,
wherein the switching controller comprises a zero-voltage switching (ZVS) optimizer circuit configured to set a ramp threshold having an amplitude that is associated with an amplitude of the ramp signal that corresponds to a negative peak amplitude of the magnetizing current to decrease capacitive charge at the switching node, wherein the switching controller is configured to deactivate the second switch via the second PWM signal in response to the ramp signal increasing to approximate the ramp threshold, and wherein the switching controller is configured to activate the first switch via the first PWM signal in response to the switching voltage decreasing to less than an activation threshold voltage to activate the first switch in response to the switching voltage having an amplitude of approximately zero volts. 6. The circuit of claim 5, wherein the ZVS optimizer circuit comprises a transconductance amplifier having a transconductance constant that is set via an external resistor and is configured to generate the ramp threshold as a difference voltage that is added to a switching threshold having an amplitude that is based on a predetermined power stage parameter corresponding to a ratio of switching node capacitance and magnetizing inductance. 7. The circuit of claim 5, further comprising a ZVS discriminator circuit that is configured to generate an activation signal in response to comparing the switching voltage with the activation threshold voltage, and is further configured to monitor an on-time associated with the second PWM signal via a timer, wherein the ZVS optimizer circuit is further configured to tune the amplitude of the ramp threshold in response to the timer counting to a predetermined time duration. 8. The circuit of claim 7, wherein the ZVS discriminator circuit comprises a high-voltage blocking circuit configured to block an amplitude of the switching voltage that is greater than a predetermined threshold, wherein the high-voltage blocking circuit comprises one of a JFET, an LDMOS device, and a diode interconnecting the switching voltage and an input of a comparator that is configured to compare the switching voltage with the activation threshold voltage. 9. The circuit of claim 6, wherein the transformer further comprises an auxiliary winding that is configured to generate an auxiliary voltage, wherein the switching controller comprises a sampling circuit configured to sample the auxiliary voltage based on the second PWM signal to generate the ramp signal, and to sample the auxiliary voltage based on the first PWM signal to generate the ramp threshold. 10. An integrated circuit (IC) chip comprising at least a portion of the power converter circuit of claim 1. 11. A power converter circuit comprising:
a power stage comprising a transformer, a first switch, and a second switch, the first switch being controlled via a first pulse-width modulation (PWM) signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage, and the second switch being controlled via a second PWM signal to re-circulate a magnetizing current associated with the transformer via an LC resonator formed by the primary winding and a capacitor; and a switching controller configured to generate the first PWM signal and the second PWM signal and to generate a ramp signal in response to feedback from the power stage such that a slope of the ramp signal is proportional to a decay rate of the magnetizing current to provide zero-volt switching (ZVS) activation of the first switch via the first PWM signal. 12. The circuit of claim 11, wherein the switching controller comprises a ZVS optimizer circuit configured to set a ramp threshold that has an amplitude that is associated with an amplitude of the ramp signal, which corresponds to a negative peak amplitude of the magnetizing current to decrease capacitive charge at a switching node associated with the first switch,
wherein the switching controller is configured to deactivate the second switch via the second PWM signal in response to the ramp signal increasing to approximately equal to the ramp threshold, and wherein the switching controller is configured to activate the first switch via the first PWM signal in response to the switching voltage decreasing to less than an activation threshold voltage to provide the ZVS activation of the first switch. 13. The circuit of claim 12, wherein the ZVS optimizer circuit comprises a transconductance amplifier having a transconductance constant that is set via an external resistor and is configured to generate the ramp threshold as a difference voltage that is added to a switching threshold having an amplitude that is based on a predetermined output voltage threshold. 14. The circuit of claim 13, further comprising a ZVS discriminator circuit that is configured to generate an activation signal in response to comparing the switching voltage with the activation threshold voltage, and is further configured to monitor an on-time associated with the second PWM signal via a timer, wherein the ZVS optimizer circuit is further configured to tune the amplitude of the difference voltage in response to the timer counting to a predetermined time duration. 15. The circuit of claim 12, wherein the transformer further comprises an auxiliary winding that is configured to generate an auxiliary voltage, wherein the switching controller comprises a sampling circuit configured to sample the auxiliary voltage via the second PWM signal to generate the ramp signal and to sample the auxiliary voltage via the first PWM signal to generate the ramp threshold. 16. An integrated circuit (IC) chip comprising a power converter circuit, the power converter circuit comprising:
a gate driver stage configured to generate a first switching signal in response to a first pulse-width modulation (PWM) signal and a second switching signal in response to a second PWM signal; a power stage comprising a transformer, a first switch, and a second switch, the first switch being controlled via the first switching signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage and induce an auxiliary voltage in an auxiliary winding of the transformer, and the second switch being controlled via the second switching signal to re-circulate a magnetizing current associated with the transformer via an LC resonator formed by the primary winding and a capacitor; and a switching controller configured to generate the first and second PWM signals and to generate a ramp signal based on the auxiliary voltage, the ramp signal having a slope that is proportional to a decay rate of the magnetizing current to provide zero-volt switching (ZVS) activation of the first switch via the first PWM signal. 17. The circuit of claim 16, wherein the switching controller comprises a ZVS optimizer circuit configured to set a ramp threshold that has an amplitude that is approximately associated with an amplitude of the ramp signal that corresponds to a negative peak amplitude of the magnetizing current to decrease capacitive charge at a switching node associated with the first switch, wherein the switching controller is configured to deactivate the second switch via the second PWM signal in response to the ramp signal increasing to approximately equal to the ramp threshold, and wherein the switching controller is configured to activate the first switch via the first PWM signal in response to a switching voltage at the switching node decreasing to less than an activation threshold voltage to activate the first switch in response to the switching voltage having an amplitude of approximately zero volts. 18. The circuit of claim 17, wherein the ZVS optimizer circuit comprises a transconductance amplifier having a transconductance constant that is set via an external resistor and is configured to generate the ramp threshold as a difference voltage that is added to a switching threshold having an amplitude that is based on a predetermined output voltage threshold. 19. The circuit of claim 18, further comprising a ZVS discriminator circuit that is configured to generate an activation signal in response to comparing the switching voltage with the activation threshold voltage, and is further configured to monitor an on-time associated with the second PWM signal via a timer, wherein the ZVS optimizer circuit is further configured to tune the amplitude of the difference voltage in response to the timer counting to a predetermined time duration. 20. The circuit of claim 17, wherein the switching controller comprises a sampling circuit configured to sample the auxiliary voltage from the auxiliary winding in response to the second PWM signal to generate the ramp signal and to sample the auxiliary voltage via the first PWM signal to generate the ramp threshold. | A power converter circuit includes a power stage that includes a transformer and a switch. The switch can be controlled in response to a PWM signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage. The power stage includes a switching node between the switch and the primary winding having a switching voltage. The circuit also includes a switching controller configured to generate the PWM signal in response to a ramp signal. The ramp signal can have an amplitude of a slope that is proportional to a decay rate of a magnetizing current of the transformer and generated in response to feedback from the power stage. The switch can be activated in response to the switching voltage having an amplitude of approximately zero volts based on the amplitude of the ramp signal.1. A power converter circuit comprising:
a power stage comprising a transformer and a switch, the switch being controlled in response to a pulse-width modulation (PWM) signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage, the power stage comprising a switching node between the switch and the primary winding having a switching voltage; and a switching controller configured to generate the PWM signal in response to a ramp signal, the ramp signal having a slope that is proportional to a decay rate of a magnetizing current associated with the transformer and generated in response to at least one feedback voltage from the power stage, the switch being activated in response to the switching voltage having an amplitude of approximately zero volts based on the amplitude of the ramp signal. 2. The circuit of claim 1, wherein the transformer further comprises an auxiliary winding that is configured to generate an auxiliary voltage, wherein the switching controller comprises a sampling circuit configured to sample the auxiliary voltage, the ramp signal being generated based on the sampled auxiliary voltage. 3. The circuit of claim 2, wherein the switching controller comprises a ramp generator configured to generate the ramp signal, the ramp generator comprising a transconductance amplifier having a transconductance constant that is set via an external resistor and is configured to generate the ramp signal based on the sampled auxiliary voltage. 4. The circuit of claim 2, wherein the switching controller comprises a zero-voltage switching (ZVS) optimizer circuit configured to set a ramp threshold having an amplitude that is associated with the amplitude of the ramp signal that corresponds to a negative peak amplitude of the magnetizing current to set the switching voltage to approximately zero volts, such that the switching controller is configured to control the PWM signal to thereby activate the switch in response to the ramp signal increasing to approximately the amplitude of the ramp threshold. 5. The circuit of claim 1, wherein the PWM signal is a first PWM signal, and wherein the switch is a first switch, wherein the power stage further comprises an LC resonator formed by the primary winding and a capacitor and a second switch that is alternately activated via a second PWM signal to circulate the magnetizing current via the LC resonator,
wherein the switching controller comprises a zero-voltage switching (ZVS) optimizer circuit configured to set a ramp threshold having an amplitude that is associated with an amplitude of the ramp signal that corresponds to a negative peak amplitude of the magnetizing current to decrease capacitive charge at the switching node, wherein the switching controller is configured to deactivate the second switch via the second PWM signal in response to the ramp signal increasing to approximate the ramp threshold, and wherein the switching controller is configured to activate the first switch via the first PWM signal in response to the switching voltage decreasing to less than an activation threshold voltage to activate the first switch in response to the switching voltage having an amplitude of approximately zero volts. 6. The circuit of claim 5, wherein the ZVS optimizer circuit comprises a transconductance amplifier having a transconductance constant that is set via an external resistor and is configured to generate the ramp threshold as a difference voltage that is added to a switching threshold having an amplitude that is based on a predetermined power stage parameter corresponding to a ratio of switching node capacitance and magnetizing inductance. 7. The circuit of claim 5, further comprising a ZVS discriminator circuit that is configured to generate an activation signal in response to comparing the switching voltage with the activation threshold voltage, and is further configured to monitor an on-time associated with the second PWM signal via a timer, wherein the ZVS optimizer circuit is further configured to tune the amplitude of the ramp threshold in response to the timer counting to a predetermined time duration. 8. The circuit of claim 7, wherein the ZVS discriminator circuit comprises a high-voltage blocking circuit configured to block an amplitude of the switching voltage that is greater than a predetermined threshold, wherein the high-voltage blocking circuit comprises one of a JFET, an LDMOS device, and a diode interconnecting the switching voltage and an input of a comparator that is configured to compare the switching voltage with the activation threshold voltage. 9. The circuit of claim 6, wherein the transformer further comprises an auxiliary winding that is configured to generate an auxiliary voltage, wherein the switching controller comprises a sampling circuit configured to sample the auxiliary voltage based on the second PWM signal to generate the ramp signal, and to sample the auxiliary voltage based on the first PWM signal to generate the ramp threshold. 10. An integrated circuit (IC) chip comprising at least a portion of the power converter circuit of claim 1. 11. A power converter circuit comprising:
a power stage comprising a transformer, a first switch, and a second switch, the first switch being controlled via a first pulse-width modulation (PWM) signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage, and the second switch being controlled via a second PWM signal to re-circulate a magnetizing current associated with the transformer via an LC resonator formed by the primary winding and a capacitor; and a switching controller configured to generate the first PWM signal and the second PWM signal and to generate a ramp signal in response to feedback from the power stage such that a slope of the ramp signal is proportional to a decay rate of the magnetizing current to provide zero-volt switching (ZVS) activation of the first switch via the first PWM signal. 12. The circuit of claim 11, wherein the switching controller comprises a ZVS optimizer circuit configured to set a ramp threshold that has an amplitude that is associated with an amplitude of the ramp signal, which corresponds to a negative peak amplitude of the magnetizing current to decrease capacitive charge at a switching node associated with the first switch,
wherein the switching controller is configured to deactivate the second switch via the second PWM signal in response to the ramp signal increasing to approximately equal to the ramp threshold, and wherein the switching controller is configured to activate the first switch via the first PWM signal in response to the switching voltage decreasing to less than an activation threshold voltage to provide the ZVS activation of the first switch. 13. The circuit of claim 12, wherein the ZVS optimizer circuit comprises a transconductance amplifier having a transconductance constant that is set via an external resistor and is configured to generate the ramp threshold as a difference voltage that is added to a switching threshold having an amplitude that is based on a predetermined output voltage threshold. 14. The circuit of claim 13, further comprising a ZVS discriminator circuit that is configured to generate an activation signal in response to comparing the switching voltage with the activation threshold voltage, and is further configured to monitor an on-time associated with the second PWM signal via a timer, wherein the ZVS optimizer circuit is further configured to tune the amplitude of the difference voltage in response to the timer counting to a predetermined time duration. 15. The circuit of claim 12, wherein the transformer further comprises an auxiliary winding that is configured to generate an auxiliary voltage, wherein the switching controller comprises a sampling circuit configured to sample the auxiliary voltage via the second PWM signal to generate the ramp signal and to sample the auxiliary voltage via the first PWM signal to generate the ramp threshold. 16. An integrated circuit (IC) chip comprising a power converter circuit, the power converter circuit comprising:
a gate driver stage configured to generate a first switching signal in response to a first pulse-width modulation (PWM) signal and a second switching signal in response to a second PWM signal; a power stage comprising a transformer, a first switch, and a second switch, the first switch being controlled via the first switching signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage and induce an auxiliary voltage in an auxiliary winding of the transformer, and the second switch being controlled via the second switching signal to re-circulate a magnetizing current associated with the transformer via an LC resonator formed by the primary winding and a capacitor; and a switching controller configured to generate the first and second PWM signals and to generate a ramp signal based on the auxiliary voltage, the ramp signal having a slope that is proportional to a decay rate of the magnetizing current to provide zero-volt switching (ZVS) activation of the first switch via the first PWM signal. 17. The circuit of claim 16, wherein the switching controller comprises a ZVS optimizer circuit configured to set a ramp threshold that has an amplitude that is approximately associated with an amplitude of the ramp signal that corresponds to a negative peak amplitude of the magnetizing current to decrease capacitive charge at a switching node associated with the first switch, wherein the switching controller is configured to deactivate the second switch via the second PWM signal in response to the ramp signal increasing to approximately equal to the ramp threshold, and wherein the switching controller is configured to activate the first switch via the first PWM signal in response to a switching voltage at the switching node decreasing to less than an activation threshold voltage to activate the first switch in response to the switching voltage having an amplitude of approximately zero volts. 18. The circuit of claim 17, wherein the ZVS optimizer circuit comprises a transconductance amplifier having a transconductance constant that is set via an external resistor and is configured to generate the ramp threshold as a difference voltage that is added to a switching threshold having an amplitude that is based on a predetermined output voltage threshold. 19. The circuit of claim 18, further comprising a ZVS discriminator circuit that is configured to generate an activation signal in response to comparing the switching voltage with the activation threshold voltage, and is further configured to monitor an on-time associated with the second PWM signal via a timer, wherein the ZVS optimizer circuit is further configured to tune the amplitude of the difference voltage in response to the timer counting to a predetermined time duration. 20. The circuit of claim 17, wherein the switching controller comprises a sampling circuit configured to sample the auxiliary voltage from the auxiliary winding in response to the second PWM signal to generate the ramp signal and to sample the auxiliary voltage via the first PWM signal to generate the ramp threshold. | 2,800 |
11,997 | 11,997 | 12,875,873 | 2,829 | LED packages and LED displays utilizing the LED packages are disclosed, with the LED packages arranged to provide good contrast between the different pixels in an LED display while not reducing the perceived luminous flux or brightness of the display. One embodiment of an LED package comprises an LED chip and conversion material arranged to convert at least some light emitted from the LED chip. The package emits light from the conversion material or a combination of light from the conversion material and the LED chip. A reflective area is included around the LED chip that substantially reflects the package light and a contrasting area is included outside the reflective area and has a color that contrasts with the package light. LED displays according to the present invention comprise a plurality of LED packages arranged in relation to one another to produce messages or images, with the package providing improved pixel contrast. | 1. A light emitting diode (LED) package, comprising:
an LED chip and conversion material arranged to convert at least some light emitted from said LED chip, said package emitting light from said conversion material or a combination of light from said conversion material and said LED chip; a reflective area around said LED chip that substantially reflects said package light; and a contrasting area outside said reflective area having a color that contrasts with said package light. 2. The LED package of claim 1, wherein said package light comprises a blue shifted yellow (BSY) light. 3. The LED package of claim 1, wherein said package light comprises a white light. 4. The LED package of claim 1, further comprising a casing with a lead frame, said LED chip electrically coupled to said lead frame 5. The LED package of claim 1, further comprising a casing, wherein said reflective area comprises a cavity in said casing, said LED chip mounted within said cavity. 6. The LED package of claim 5, wherein said cavity forms a reflective cup around said LED chip. 7. The LED package of claim 1, comprising a surface mount device (SMD). 8. The LED package of claim 1, wherein said reflective area comprises a reflective cup. 9. The LED package of claim 1, wherein said contrasting area is black. 10. The LED package of claim 1, wherein said contrasting area is around said reflective area. 11. The LED package of claim 1, wherein said contrasting area is at a level above said LED chip. 12. The LED package of claim 11, wherein said contrasting area and said LED chip are arranged so that said LED light emits from said package without emitting directly on said contrasting area. 13. A light emitting diode (LED) display, comprising:
a plurality of LED packages mounted in relation to one another to generate a message or image, at least some of said LED packages comprising an LED chip and conversion material arranged in a reflective cup with said conversion material converting at least some light emitted from said LED chip, said at least some packages emitting package light from said conversion material or a combination of light from said conversion material and said LED chip, said reflective area substantially reflecting said package light, said package further comprising a contrasting area that is outside said reflective area and having a color that contrasts with said package light. 14. The LED display of claim 13, wherein said LED display comprises higher pixel contrast compared to the same LED display having LED packages without a contrasting area. 15. The LED display of claim 13, wherein said reflective area of each of said at least some LED packages comprises a reflective cup around said LED chip. 16. The LED display of claim 13, wherein each of said at least some LED packages comprises a surface mount device (SMD). 17. The LED display of claim 13, wherein each of said at least some LED packages emits white light. 18. The LED display of claim 13, wherein each of said at least some LED packages emits blue shifted yellow (BSY) light. 19. The LED display of claim 13, wherein said contrasting area in each of said at least some LED packages is black. 20. The LED display of claim 13, wherein said contrasting area in each of said at least some LED packages is around said reflective area. 21. The LED display of claim 13, wherein said contrasting area in each of said at least some LED packages is at a level above said LED chip. 22. The LED display of claim 13, wherein said contrasting area is arranged in each of said at least some LED packages so that LED light emits from said package without emitting directly on said contrasting area. 23. A light emitting diode (LED) package, comprising:
an LED chip and a conversion material arranged to absorb light from said LED chip and re-emit light at a different wavelength, said package emitting a package light comprising said re-emitted light or a combination of light from said LED chip and said re-emitted light, said LED chip mounted within a reflective cup having upper surface with a color that contrasts with the light emitted from said LED chip. 24. The LED package of claim 23, wherein surfaces of said reflective cup are substantially reflective of said package light. 25. The LED package of claim 23, wherein surfaces of said reflective cup are white. 26. The LED package of claim 23, wherein said upper surface is black. 27. The LED package of claim 23, comprising a surface mount device (SMD). 28. The LED package of claim 23, wherein said upper surface and said LED chip are arranged so that LED light emits from said package without emitting directly on said upper surface. 29. A light emitting diode (LED) package, comprising:
a plurality of LED chips electrically coupled in a single circuit, wherein surfaces directly around said LED chips comprise a reflective area that substantially reflects light emitted from said LED chips, and a contrasting area that is outside said reflective area having a color that contrasts with the light emitted from said LED chips. 30. The LED package of claim 29, wherein said single circuit comprises a single anode and single cathode for applying an electrical signal to said LED chips. 31. The LED package of claim 29, wherein at least some of said LED chips emit white light. 32. The LED package of claim 29, wherein at least some of said LED chips emit blue shifted yellow (BSY) light. 33. The LED package of claim 29, further comprising a casing, wherein said reflective area comprises a cavity in said casing, said LED chips mounted within said cavity. 34. The LED package of claim 33, wherein said cavity forms a reflective cup around said LED chip. 35. The LED package of claim 29, comprising a surface mount device (SMD). 36. The LED package of claim 29, wherein said reflective area comprises a reflective cup. 37. The LED package of claim 29, wherein said contrasting area is black. 38. The LED package of claim 29, wherein said contrasting area is around said reflective area. 39. The LED package of claim 29, wherein said contrasting area is at a level above said LED chip. | LED packages and LED displays utilizing the LED packages are disclosed, with the LED packages arranged to provide good contrast between the different pixels in an LED display while not reducing the perceived luminous flux or brightness of the display. One embodiment of an LED package comprises an LED chip and conversion material arranged to convert at least some light emitted from the LED chip. The package emits light from the conversion material or a combination of light from the conversion material and the LED chip. A reflective area is included around the LED chip that substantially reflects the package light and a contrasting area is included outside the reflective area and has a color that contrasts with the package light. LED displays according to the present invention comprise a plurality of LED packages arranged in relation to one another to produce messages or images, with the package providing improved pixel contrast.1. A light emitting diode (LED) package, comprising:
an LED chip and conversion material arranged to convert at least some light emitted from said LED chip, said package emitting light from said conversion material or a combination of light from said conversion material and said LED chip; a reflective area around said LED chip that substantially reflects said package light; and a contrasting area outside said reflective area having a color that contrasts with said package light. 2. The LED package of claim 1, wherein said package light comprises a blue shifted yellow (BSY) light. 3. The LED package of claim 1, wherein said package light comprises a white light. 4. The LED package of claim 1, further comprising a casing with a lead frame, said LED chip electrically coupled to said lead frame 5. The LED package of claim 1, further comprising a casing, wherein said reflective area comprises a cavity in said casing, said LED chip mounted within said cavity. 6. The LED package of claim 5, wherein said cavity forms a reflective cup around said LED chip. 7. The LED package of claim 1, comprising a surface mount device (SMD). 8. The LED package of claim 1, wherein said reflective area comprises a reflective cup. 9. The LED package of claim 1, wherein said contrasting area is black. 10. The LED package of claim 1, wherein said contrasting area is around said reflective area. 11. The LED package of claim 1, wherein said contrasting area is at a level above said LED chip. 12. The LED package of claim 11, wherein said contrasting area and said LED chip are arranged so that said LED light emits from said package without emitting directly on said contrasting area. 13. A light emitting diode (LED) display, comprising:
a plurality of LED packages mounted in relation to one another to generate a message or image, at least some of said LED packages comprising an LED chip and conversion material arranged in a reflective cup with said conversion material converting at least some light emitted from said LED chip, said at least some packages emitting package light from said conversion material or a combination of light from said conversion material and said LED chip, said reflective area substantially reflecting said package light, said package further comprising a contrasting area that is outside said reflective area and having a color that contrasts with said package light. 14. The LED display of claim 13, wherein said LED display comprises higher pixel contrast compared to the same LED display having LED packages without a contrasting area. 15. The LED display of claim 13, wherein said reflective area of each of said at least some LED packages comprises a reflective cup around said LED chip. 16. The LED display of claim 13, wherein each of said at least some LED packages comprises a surface mount device (SMD). 17. The LED display of claim 13, wherein each of said at least some LED packages emits white light. 18. The LED display of claim 13, wherein each of said at least some LED packages emits blue shifted yellow (BSY) light. 19. The LED display of claim 13, wherein said contrasting area in each of said at least some LED packages is black. 20. The LED display of claim 13, wherein said contrasting area in each of said at least some LED packages is around said reflective area. 21. The LED display of claim 13, wherein said contrasting area in each of said at least some LED packages is at a level above said LED chip. 22. The LED display of claim 13, wherein said contrasting area is arranged in each of said at least some LED packages so that LED light emits from said package without emitting directly on said contrasting area. 23. A light emitting diode (LED) package, comprising:
an LED chip and a conversion material arranged to absorb light from said LED chip and re-emit light at a different wavelength, said package emitting a package light comprising said re-emitted light or a combination of light from said LED chip and said re-emitted light, said LED chip mounted within a reflective cup having upper surface with a color that contrasts with the light emitted from said LED chip. 24. The LED package of claim 23, wherein surfaces of said reflective cup are substantially reflective of said package light. 25. The LED package of claim 23, wherein surfaces of said reflective cup are white. 26. The LED package of claim 23, wherein said upper surface is black. 27. The LED package of claim 23, comprising a surface mount device (SMD). 28. The LED package of claim 23, wherein said upper surface and said LED chip are arranged so that LED light emits from said package without emitting directly on said upper surface. 29. A light emitting diode (LED) package, comprising:
a plurality of LED chips electrically coupled in a single circuit, wherein surfaces directly around said LED chips comprise a reflective area that substantially reflects light emitted from said LED chips, and a contrasting area that is outside said reflective area having a color that contrasts with the light emitted from said LED chips. 30. The LED package of claim 29, wherein said single circuit comprises a single anode and single cathode for applying an electrical signal to said LED chips. 31. The LED package of claim 29, wherein at least some of said LED chips emit white light. 32. The LED package of claim 29, wherein at least some of said LED chips emit blue shifted yellow (BSY) light. 33. The LED package of claim 29, further comprising a casing, wherein said reflective area comprises a cavity in said casing, said LED chips mounted within said cavity. 34. The LED package of claim 33, wherein said cavity forms a reflective cup around said LED chip. 35. The LED package of claim 29, comprising a surface mount device (SMD). 36. The LED package of claim 29, wherein said reflective area comprises a reflective cup. 37. The LED package of claim 29, wherein said contrasting area is black. 38. The LED package of claim 29, wherein said contrasting area is around said reflective area. 39. The LED package of claim 29, wherein said contrasting area is at a level above said LED chip. | 2,800 |
11,998 | 11,998 | 15,204,096 | 2,872 | A dielectrophoretic display is shifted from a low frequency closed state to a high frequency open state via at least one, and preferably several, intermediate frequency states; the use of such multiple frequency steps reduces flicker during the transition. A second type of dielectrophoretic display has a light-transmissive electrode through which the dielectrophoretic medium can be viewed and a conductor connected to the light-transmissive electrode at several points to reduce voltage variations within the light-transmissive electrode. | 1. A dielectrophoretic display comprising:
a dielectrophoretic medium comprising a fluid and a plurality of at least one type of particle within the fluid, the particles being movable through the fluid on application of an electric field to the dielectrophoretic medium; at least one light-transmissive electrode disposed adjacent the dielectrophoretic medium so that the dielectrophoretic medium can be viewed through the light-transmissive electrode; and a conductor extending from the light-transmissive electrode to a voltage source, the conductor having a higher electrical conductivity than the light-transmissive electrode, the conductor contacting the light-transmissive electrode at at least two spaced points. 2. A dielectrophoretic display according to claim 1 wherein the dielectrophoretic medium and the light-transmissive electrode are rectangular and the conductor is arranged to contact the light-transmissive electrode substantially at the mid-point of each edge of the electrode. 3. A dielectrophoretic display according to claim 1 wherein the dielectrophoretic medium and the light-transmissive electrode are sufficiently large that, if the conductor was connected to the light-transmissive electrode at only a single point, there would be at least one point on the dielectrophoretic medium which was at least about 200 mm from said single point. 4. A dielectrophoretic display according to claim 1 wherein the conductor has the form of a conductive trace which extends around substantially the entire periphery of the light-transmissive electrode. 5. A dielectrophoretic display according to claim 1 wherein the conductor has a resistivity not greater than about 1 ohms/square. 6. A dielectrophoretic display according to claim 1 wherein the light-transmissive electrode comprises indium tin oxide. 7. A dielectrophoretic display according to claim 1 in the form of a variable transmission window having light-transmissive electrodes on both sides of the dielectrophoretic medium. 8. A light modulator, electronic book reader, portable computer, tablet computer, cellular telephone, smart card, sign, watch, shelf label or flash drive comprising a display according to claim 1. | A dielectrophoretic display is shifted from a low frequency closed state to a high frequency open state via at least one, and preferably several, intermediate frequency states; the use of such multiple frequency steps reduces flicker during the transition. A second type of dielectrophoretic display has a light-transmissive electrode through which the dielectrophoretic medium can be viewed and a conductor connected to the light-transmissive electrode at several points to reduce voltage variations within the light-transmissive electrode.1. A dielectrophoretic display comprising:
a dielectrophoretic medium comprising a fluid and a plurality of at least one type of particle within the fluid, the particles being movable through the fluid on application of an electric field to the dielectrophoretic medium; at least one light-transmissive electrode disposed adjacent the dielectrophoretic medium so that the dielectrophoretic medium can be viewed through the light-transmissive electrode; and a conductor extending from the light-transmissive electrode to a voltage source, the conductor having a higher electrical conductivity than the light-transmissive electrode, the conductor contacting the light-transmissive electrode at at least two spaced points. 2. A dielectrophoretic display according to claim 1 wherein the dielectrophoretic medium and the light-transmissive electrode are rectangular and the conductor is arranged to contact the light-transmissive electrode substantially at the mid-point of each edge of the electrode. 3. A dielectrophoretic display according to claim 1 wherein the dielectrophoretic medium and the light-transmissive electrode are sufficiently large that, if the conductor was connected to the light-transmissive electrode at only a single point, there would be at least one point on the dielectrophoretic medium which was at least about 200 mm from said single point. 4. A dielectrophoretic display according to claim 1 wherein the conductor has the form of a conductive trace which extends around substantially the entire periphery of the light-transmissive electrode. 5. A dielectrophoretic display according to claim 1 wherein the conductor has a resistivity not greater than about 1 ohms/square. 6. A dielectrophoretic display according to claim 1 wherein the light-transmissive electrode comprises indium tin oxide. 7. A dielectrophoretic display according to claim 1 in the form of a variable transmission window having light-transmissive electrodes on both sides of the dielectrophoretic medium. 8. A light modulator, electronic book reader, portable computer, tablet computer, cellular telephone, smart card, sign, watch, shelf label or flash drive comprising a display according to claim 1. | 2,800 |
11,999 | 11,999 | 15,605,356 | 2,835 | A power fuse assembly includes a fuse mounting, a fuse unit, and a hinge assembly. The fuse unit is configured to carry current from a line connection to a load connection. The hinge assembly is configured to be removeably coupled to the fuse unit and to allow rotation of the fuse unit relative to the fuse mounting. The hinge assembly including: an inlet configured to accept incoming gases produced by the fuse unit in response to an overload event, the inlet having a first orientation; an outlet in fluid communication with the inlet, the outlet having a second orientation that is not equal to the first orientation; and a diverter component disposed between the inlet and the outlet, the diverter configured to guide the flow of the gases between the inlet and the outlet. | 1. A power fuse assembly comprising:
a fuse mounting; a fuse unit configured to carry current from a line connection to a load connection; a hinge assembly removably coupling the fuse unit to the fuse mounting to allow rotation of the fuse unit relative to the fuse mounting, the hinge assembly including:
an inlet configured to accept incoming gases produced by the fuse unit in response to an overload event, the inlet having a first orientation;
an outlet in fluid communication with the inlet, the outlet having a second orientation that is not equal to the first orientation; and
a diverter component disposed between the inlet and the outlet, the diverter configured to guide the flow of the gases from the inlet in the first orientation to the outlet in the second orientation. 2. The power fuse assembly of claim 1, wherein the fuse unit has a longitudinal axis, the orientation of the outlet has a predetermined angle in a range between 40 and 50 degrees with respect to the longitudinal axis. 3. The power fuse assembly of claim 2, wherein the orientation of the outlet faces away from a front region of the power fuse assembly. 4. The power fuse assembly of claim 2, further comprising a silencer component coupled to the outlet of the hinge assembly. 5. The power fuse assembly of claim 4, wherein the orientation of the outlet faces toward a front region of the power fuse assembly. 6. The power fuse assembly of claim 1, wherein the hinge assembly further comprises a cap component rotatably coupled to the hinge assembly, the cap component configured to substantially block the outlet when the hinge assembly is rotated to a first orientation, and configured to reveal the outlet when the hinge assembly is rotated to a second orientation. 7. The power fuse assembly of claim 6, wherein the cap component comprises a covering portion configured to cover the outlet, and a counterweight portion opposite the covering portion, the counterweight portion and covering portion cooperating to to cause rotation of the cap component in response to a change in the orientation of the hinge assembly. 8. The power fuse assembly of claim 1, wherein the hinge assembly comprises an inner chamber between the inlet and the outlet, and the diverter component comprises an airfoil-shaped component extending from a first wall of the inner chamber to an opposite second wall of the inner chamber. 9. The power fuse assembly of claim 1, wherein the hinge assembly further comprises a plate structure configured to impede the flow of gases upward toward the fuse element. 10. A hinge assembly configured to removably couple a fuse unit to a power fuse assembly, the hinge assembly comprising:
an inlet configured to accept incoming gases produced by the fuse in response to an overload event, the inlet having a first orientation; an outlet in fluid communication with the inlet, the outlet having a second orientation that is not equal to the first orientation; and a diverter component disposed between the inlet and the outlet, the diverter configured to guide the flow of the gases from the inlet in the first orientation to the outlet in the second orientation. 11. The hinge assembly of claim 10, wherein the orientation of the outlet has a predetermined angle with respect to a longitudinal axis of the fuse unit of between approximately 40 and 50 degrees. 12. The hinge assembly of claim 10, wherein the orientation of the outlet faces away from a front region of the fuse mounting. 13. The hinge assembly of claim 10, further comprising a silencer component coupled to the outlet. 14. The hinge assembly of claim 10, further comprising a cap component rotateably coupled to the hinge assembly, the cap component configured to substantially block the outlet when the hinge assembly is rotated to a first orientation, and configured to not substantially block the outlet when the hinge assembly is rotated to a second orientation. 15. The hinge assembly of claim 14, wherein the cap component comprises a covering portion configured to cover the outlet, and a counterweight portion opposite the covering portion, the counterweight portion and covering portion cooperating to cause rotation of the cap component in response to a change in the orientation of the hinge assembly. 16. The hinge assembly of claim 10, further comprising an inner chamber between the inlet and the outlet, wherein the diverter component includes an airfoil-shaped component extending from a first wall of the inner chamber to an opposite second wall of the inner chamber. 17. The hinge assembly of claim 10, further comprising a plate structure configured to impede the flow of gases upward toward the mounting. 18. A power fuse assembly comprising:
a mount having an upper contact assembly, a lower contact assembly and an insulator body extending therebetween; a fuse tube defining a longitudinal axis and having first and second ends; a fitting disposed on the first end of the fuse tube and releasably retained in the upper contact assembly of the mount; a hinge assembly disposed on the second end of the fuse tube and pivotally coupled to the lower contact assembly to allow rotation of the fuse tube relative to the mount, wherein the fuse tube is positionable between a first position with the fitting retained in the upper contact assembly for closing a current path from a line connection to a load connection and a second position with the fitting released from the upper contact assembly for opening the current path; and a diverter housing extending from the hinge assembly and housing having a curved conduit with an inlet arranged in a first orientation in fluid communication with the fuse tube and an outlet arranged in a second orientation that is different than the first orientation, and a diverter vane disposed in the conduit between the inlet and the outlet, wherein the curved conduit and the diverter vane are configured to direct the flow of the gases from the inlet to the outlet. 19. The power fuse assembly of claim 18 further comprising a cap component coupled to the hinge assembly and configured to substantially reveal the outlet when the fuse tube is in the first position and to substantially block the outlet when the fuse tube is in the second position. 20. The power fuse assembly of claim 18, further comprising a plate structure extending from the hinge assembly generally perpendicular to the longitudinal axis for impeding the flow of gases in a direction parallel to the longitudinal axis. | A power fuse assembly includes a fuse mounting, a fuse unit, and a hinge assembly. The fuse unit is configured to carry current from a line connection to a load connection. The hinge assembly is configured to be removeably coupled to the fuse unit and to allow rotation of the fuse unit relative to the fuse mounting. The hinge assembly including: an inlet configured to accept incoming gases produced by the fuse unit in response to an overload event, the inlet having a first orientation; an outlet in fluid communication with the inlet, the outlet having a second orientation that is not equal to the first orientation; and a diverter component disposed between the inlet and the outlet, the diverter configured to guide the flow of the gases between the inlet and the outlet.1. A power fuse assembly comprising:
a fuse mounting; a fuse unit configured to carry current from a line connection to a load connection; a hinge assembly removably coupling the fuse unit to the fuse mounting to allow rotation of the fuse unit relative to the fuse mounting, the hinge assembly including:
an inlet configured to accept incoming gases produced by the fuse unit in response to an overload event, the inlet having a first orientation;
an outlet in fluid communication with the inlet, the outlet having a second orientation that is not equal to the first orientation; and
a diverter component disposed between the inlet and the outlet, the diverter configured to guide the flow of the gases from the inlet in the first orientation to the outlet in the second orientation. 2. The power fuse assembly of claim 1, wherein the fuse unit has a longitudinal axis, the orientation of the outlet has a predetermined angle in a range between 40 and 50 degrees with respect to the longitudinal axis. 3. The power fuse assembly of claim 2, wherein the orientation of the outlet faces away from a front region of the power fuse assembly. 4. The power fuse assembly of claim 2, further comprising a silencer component coupled to the outlet of the hinge assembly. 5. The power fuse assembly of claim 4, wherein the orientation of the outlet faces toward a front region of the power fuse assembly. 6. The power fuse assembly of claim 1, wherein the hinge assembly further comprises a cap component rotatably coupled to the hinge assembly, the cap component configured to substantially block the outlet when the hinge assembly is rotated to a first orientation, and configured to reveal the outlet when the hinge assembly is rotated to a second orientation. 7. The power fuse assembly of claim 6, wherein the cap component comprises a covering portion configured to cover the outlet, and a counterweight portion opposite the covering portion, the counterweight portion and covering portion cooperating to to cause rotation of the cap component in response to a change in the orientation of the hinge assembly. 8. The power fuse assembly of claim 1, wherein the hinge assembly comprises an inner chamber between the inlet and the outlet, and the diverter component comprises an airfoil-shaped component extending from a first wall of the inner chamber to an opposite second wall of the inner chamber. 9. The power fuse assembly of claim 1, wherein the hinge assembly further comprises a plate structure configured to impede the flow of gases upward toward the fuse element. 10. A hinge assembly configured to removably couple a fuse unit to a power fuse assembly, the hinge assembly comprising:
an inlet configured to accept incoming gases produced by the fuse in response to an overload event, the inlet having a first orientation; an outlet in fluid communication with the inlet, the outlet having a second orientation that is not equal to the first orientation; and a diverter component disposed between the inlet and the outlet, the diverter configured to guide the flow of the gases from the inlet in the first orientation to the outlet in the second orientation. 11. The hinge assembly of claim 10, wherein the orientation of the outlet has a predetermined angle with respect to a longitudinal axis of the fuse unit of between approximately 40 and 50 degrees. 12. The hinge assembly of claim 10, wherein the orientation of the outlet faces away from a front region of the fuse mounting. 13. The hinge assembly of claim 10, further comprising a silencer component coupled to the outlet. 14. The hinge assembly of claim 10, further comprising a cap component rotateably coupled to the hinge assembly, the cap component configured to substantially block the outlet when the hinge assembly is rotated to a first orientation, and configured to not substantially block the outlet when the hinge assembly is rotated to a second orientation. 15. The hinge assembly of claim 14, wherein the cap component comprises a covering portion configured to cover the outlet, and a counterweight portion opposite the covering portion, the counterweight portion and covering portion cooperating to cause rotation of the cap component in response to a change in the orientation of the hinge assembly. 16. The hinge assembly of claim 10, further comprising an inner chamber between the inlet and the outlet, wherein the diverter component includes an airfoil-shaped component extending from a first wall of the inner chamber to an opposite second wall of the inner chamber. 17. The hinge assembly of claim 10, further comprising a plate structure configured to impede the flow of gases upward toward the mounting. 18. A power fuse assembly comprising:
a mount having an upper contact assembly, a lower contact assembly and an insulator body extending therebetween; a fuse tube defining a longitudinal axis and having first and second ends; a fitting disposed on the first end of the fuse tube and releasably retained in the upper contact assembly of the mount; a hinge assembly disposed on the second end of the fuse tube and pivotally coupled to the lower contact assembly to allow rotation of the fuse tube relative to the mount, wherein the fuse tube is positionable between a first position with the fitting retained in the upper contact assembly for closing a current path from a line connection to a load connection and a second position with the fitting released from the upper contact assembly for opening the current path; and a diverter housing extending from the hinge assembly and housing having a curved conduit with an inlet arranged in a first orientation in fluid communication with the fuse tube and an outlet arranged in a second orientation that is different than the first orientation, and a diverter vane disposed in the conduit between the inlet and the outlet, wherein the curved conduit and the diverter vane are configured to direct the flow of the gases from the inlet to the outlet. 19. The power fuse assembly of claim 18 further comprising a cap component coupled to the hinge assembly and configured to substantially reveal the outlet when the fuse tube is in the first position and to substantially block the outlet when the fuse tube is in the second position. 20. The power fuse assembly of claim 18, further comprising a plate structure extending from the hinge assembly generally perpendicular to the longitudinal axis for impeding the flow of gases in a direction parallel to the longitudinal axis. | 2,800 |
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