Unnamed: 0 int64 0 350k | level_0 int64 0 351k | ApplicationNumber int64 9.75M 96.1M | ArtUnit int64 1.6k 3.99k | Abstract stringlengths 1 8.37k | Claims stringlengths 3 292k | abstract-claims stringlengths 68 293k | TechCenter int64 1.6k 3.9k |
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12,100 | 12,100 | 15,660,038 | 2,853 | A system and method to determine a remaining useful life estimation of a material under evaluation. The equipment comprises at least one computer and a material features acquisition system operable to detect a plurality of material features. The features are then evaluated according to rules captured from of experts and inputted into the computer. The computer iterations are processed until an acceptable conclusion is made regarding the condition of the material under evaluation. The remaining useful life estimation capability may also be retrofitted into conventional inspection systems by extracting pertinent features through spectral frequency analysis and sensor normalization and utilizing those features in the autonomous remaining useful life estimation system. | 1. A method to evaluate material wherein said material under evaluation comprises a tubular, said method comprising:
providing a material features acquisition system operable to detect a plurality of material features in a material under evaluation, said material features acquisition system comprising a sensor with an output indicative of at least one of said plurality of material features from said material under evaluation; providing that said material features acquisition system is responsive to a known degradation mechanism or another material feature for calibrating said material features acquisition system from a calibration sample and is adjustable based on said calibration sample; providing that said sensor is movable axially with respect to said tubular; providing that said material features acquisition system is operable to evaluate said output to detect new material features and monitor previously detected material features in said material under evaluation; providing programming for determining a degradation mechanism from a plurality of possible degradation mechanisms or changes affecting said material under evaluation; and providing a database operable for storage of a history of said material under evaluation. 2. The method of claim 1, further comprising that said material features acquisition system is programmed to evaluate said tubular when said tubular comprises at least one of comprising an oil country tubular good, a pipeline, a BOP, a riser or subsea device. 3. The method of claim 1, further comprising providing data derived from said method to produce a finite element analysis of said material. 4. The method of claim 1 further comprising providing at least one database comprising material features recognition equations. 5. The method of claim 4 further comprising providing programming for determining coefficients of said material features recognition equations. 6. The method of claim 1, further comprising providing programming to recommend a preventative action to inhibit said degradation mechanism. 7. The method of claim 1 wherein said material features comprise at least one of fatigue, corrosion, pitting, cracks, stress concentrations, grooves, dents, or wall thickness changes, geometry irregularity, hardness, other material features, or combinations thereof. 8. The method of claim 1, wherein said plurality of material features comprising at least tapers, welds, wall thickness, and other material features. 9. The method of claim 1, further comprising providing programming for at least one of making a determination of a fitness-for-service of said material or a determination of a remaining-useful-life of said material. 10. The method of claim 1, further comprising using said history of said material under evaluation to determine changes in said material under evaluation. 11. The method of claim 1, further comprising using voice as an input to said material features acquisition system. 12. The method of claim 1, further comprising providing that said calibration sample comprises at least two known degradation mechanisms or material features and scanning said calibration sample and adjusting said evaluation from said material features acquisition system to match said at least two known degradation mechanisms or material features. 13. The method of claim 1 further comprising:
programming said material features acquisition system to determine at least three degradation mechanisms or material features from a plurality of possible degradation mechanisms or a plurality of material features. 14. A system to evaluate material wherein said material under evaluation comprises a tubular, said system comprising:
a material features acquisition system programmed to detect a plurality of material features in a material under evaluation, said material features acquisition system comprising a sensor with an output indicative of at least one of said plurality of material features from said material under evaluation; said material features acquisition system is programmed to be responsive to a known degradation mechanism or another material feature for calibrating said material features acquisition system from a calibration sample and is adjustable based on said calibration sample; said sensor is movable axially with respect to said tubular; said material features acquisition system is programmed to evaluate said output to detect new material features and monitor previously detected material features in said material under evaluation; said material features system is programed for determining a degradation mechanism from a plurality of possible degradation mechanisms or changes affecting said material under evaluation; and a database operable for storage of a history of said material under evaluation. 15. The system of claim 14, further comprising said system is programmed to produce data to produce a finite element analysis of said material. 16. The system of claim 14 further comprising a database comprising material features recognition equations and programming for determining coefficients of said material features recognition equations. 17. The system of claim 14 wherein said material features comprise at least one of fatigue, corrosion, pitting, cracks, stress concentrations, grooves, dents, or wall thickness changes, geometry irregularity, hardness, other material features, or combinations thereof. 18. The system of claim 14, wherein said plurality of material features comprising at least tapers, welds, wall thickness, and other material features. 19. The system of claim 14, further comprising programming for at least one of making a determination of a fitness-for-service of said material or a determination of a remaining-useful-life of said material. 20. The system of claim 14, further comprising programming for using said history of said material under evaluation to determine changes in said material under evaluation. 21. The system of claim 14, further comprising that said calibration sample comprises at least two known degradation mechanisms or material features, programming allowing adjusting said evaluation from said material features acquisition system to match said at least two known degradation mechanisms or material features. 22. The system of claim 14 further comprising:
said material features acquisition system being programmed to determine at least three degradation mechanisms or material features from a plurality of possible degradation mechanisms or a plurality of material features. | A system and method to determine a remaining useful life estimation of a material under evaluation. The equipment comprises at least one computer and a material features acquisition system operable to detect a plurality of material features. The features are then evaluated according to rules captured from of experts and inputted into the computer. The computer iterations are processed until an acceptable conclusion is made regarding the condition of the material under evaluation. The remaining useful life estimation capability may also be retrofitted into conventional inspection systems by extracting pertinent features through spectral frequency analysis and sensor normalization and utilizing those features in the autonomous remaining useful life estimation system.1. A method to evaluate material wherein said material under evaluation comprises a tubular, said method comprising:
providing a material features acquisition system operable to detect a plurality of material features in a material under evaluation, said material features acquisition system comprising a sensor with an output indicative of at least one of said plurality of material features from said material under evaluation; providing that said material features acquisition system is responsive to a known degradation mechanism or another material feature for calibrating said material features acquisition system from a calibration sample and is adjustable based on said calibration sample; providing that said sensor is movable axially with respect to said tubular; providing that said material features acquisition system is operable to evaluate said output to detect new material features and monitor previously detected material features in said material under evaluation; providing programming for determining a degradation mechanism from a plurality of possible degradation mechanisms or changes affecting said material under evaluation; and providing a database operable for storage of a history of said material under evaluation. 2. The method of claim 1, further comprising that said material features acquisition system is programmed to evaluate said tubular when said tubular comprises at least one of comprising an oil country tubular good, a pipeline, a BOP, a riser or subsea device. 3. The method of claim 1, further comprising providing data derived from said method to produce a finite element analysis of said material. 4. The method of claim 1 further comprising providing at least one database comprising material features recognition equations. 5. The method of claim 4 further comprising providing programming for determining coefficients of said material features recognition equations. 6. The method of claim 1, further comprising providing programming to recommend a preventative action to inhibit said degradation mechanism. 7. The method of claim 1 wherein said material features comprise at least one of fatigue, corrosion, pitting, cracks, stress concentrations, grooves, dents, or wall thickness changes, geometry irregularity, hardness, other material features, or combinations thereof. 8. The method of claim 1, wherein said plurality of material features comprising at least tapers, welds, wall thickness, and other material features. 9. The method of claim 1, further comprising providing programming for at least one of making a determination of a fitness-for-service of said material or a determination of a remaining-useful-life of said material. 10. The method of claim 1, further comprising using said history of said material under evaluation to determine changes in said material under evaluation. 11. The method of claim 1, further comprising using voice as an input to said material features acquisition system. 12. The method of claim 1, further comprising providing that said calibration sample comprises at least two known degradation mechanisms or material features and scanning said calibration sample and adjusting said evaluation from said material features acquisition system to match said at least two known degradation mechanisms or material features. 13. The method of claim 1 further comprising:
programming said material features acquisition system to determine at least three degradation mechanisms or material features from a plurality of possible degradation mechanisms or a plurality of material features. 14. A system to evaluate material wherein said material under evaluation comprises a tubular, said system comprising:
a material features acquisition system programmed to detect a plurality of material features in a material under evaluation, said material features acquisition system comprising a sensor with an output indicative of at least one of said plurality of material features from said material under evaluation; said material features acquisition system is programmed to be responsive to a known degradation mechanism or another material feature for calibrating said material features acquisition system from a calibration sample and is adjustable based on said calibration sample; said sensor is movable axially with respect to said tubular; said material features acquisition system is programmed to evaluate said output to detect new material features and monitor previously detected material features in said material under evaluation; said material features system is programed for determining a degradation mechanism from a plurality of possible degradation mechanisms or changes affecting said material under evaluation; and a database operable for storage of a history of said material under evaluation. 15. The system of claim 14, further comprising said system is programmed to produce data to produce a finite element analysis of said material. 16. The system of claim 14 further comprising a database comprising material features recognition equations and programming for determining coefficients of said material features recognition equations. 17. The system of claim 14 wherein said material features comprise at least one of fatigue, corrosion, pitting, cracks, stress concentrations, grooves, dents, or wall thickness changes, geometry irregularity, hardness, other material features, or combinations thereof. 18. The system of claim 14, wherein said plurality of material features comprising at least tapers, welds, wall thickness, and other material features. 19. The system of claim 14, further comprising programming for at least one of making a determination of a fitness-for-service of said material or a determination of a remaining-useful-life of said material. 20. The system of claim 14, further comprising programming for using said history of said material under evaluation to determine changes in said material under evaluation. 21. The system of claim 14, further comprising that said calibration sample comprises at least two known degradation mechanisms or material features, programming allowing adjusting said evaluation from said material features acquisition system to match said at least two known degradation mechanisms or material features. 22. The system of claim 14 further comprising:
said material features acquisition system being programmed to determine at least three degradation mechanisms or material features from a plurality of possible degradation mechanisms or a plurality of material features. | 2,800 |
12,101 | 12,101 | 15,032,609 | 2,875 | An LED light module for illuminating a target plane is provided. The LED light module includes a first LED source, a second LED source disposed adjacent the first LED source, a first lens covering the first LED source, and a second lens covering the second LED source. The first lens is configured to direct first light beams emitted from the first light source to the target plane. The second lens is configured to direct second light beams emitted from the second light source to the target plane. At least one of the first and second lenses is shaped to have an asymmetrical profile. A backlighting system and a fixture incorporating the LED light module are also provided. | 1. An LED light module for illuminating a target plane, comprising:
a first LED source; a second LED source disposed adjacent the first LED source; a first lens covering the first LED source, the first lens configured to direct first light beams emitted from the first light source to the target plane; and a second lens covering the second LED source, the second lens configured to direct second light beams emitted from the second light source to the target plane; wherein at least one of the first and second lenses is shaped to have an asymmetrical profile. 2. The LED light module of claim 1, wherein the first lens and the second lens are integrally formed. 3. The LED light module of claim 1, wherein at least one of the first and second lenses comprises:
a curved outer surface; a curved inner surface defining a wall having a varying thickness with respect to the curved outer surface, the curved inner surface and the curved outer surface cooperating with each other to direct at least a part of the light beams emitted from the first and second LED sources to the target plane; and a planar side surface connected to the curved outer surface and the curved inner surface, the planar side surface configured to direct at least a part of the light beams emitted from the first and second LED sources away from the target plane. 4. The LED light module of claim 3, wherein the curved outer surface and the curved inner surface are arranged to have a uniform width measured along one direction in the target plane. 5. (canceled) 6. The LED light module of claim 5, wherein the compound curve surface comprises a spherical surface or an ellipsoidal surface. 7. The LED light module of claim 1, further comprising:
a third LED source disposed adjacent the second LED source; and a third lens covering the third LED source, the third lens configured to direct third light beams emitted from the third light LED source to the target plane; wherein at least one of the first, second, and third lenses is shaped to have an asymmetrical profile. 8. A backlighting system, comprising:
a plurality of LED light modules electrically coupled with one another, one of the plurality of LED light modules comprising:
a circuit board;
a first LED source mounted on the circuit board;
a second LED source mounted on the circuit board; and
an optical element mounted on the circuit board and covering both the first LED source and the second LED source, the optical element configured to distribute the light beams emitted from at least one of the first and second LED sources into asymmetrical light patterns. 9. The backlighting system of claim 8, wherein the optical element comprises:
a first lens covering the first LED source and for asymmetrically distributing first light beams emitted from the first LED source; and a second lens covering the second LED source and for asymmetrically distributing the second light beams emitted from the second LED source. 10. The backlighting system of claim 8, wherein the first lens and the second lens are integrally formed, and at least one of the first lens and the second lens comprises:
a curved outer surface; a curved inner surface defining a wall having a varying thickness with respect to the curved outer surface, the curved inner surface and the curved outer surface cooperating with each other to direct the light beams emitted from the first and second LED sources to a target plane; and a planar side surface connected to the curved outer surface and the curved inner surface, the planar side surface configured to direct light beams emitted from the LED sources to the target plane to generate the asymmetrical light patterns on the target plane. 11. The backlighting system of claim 8, wherein the curved outer surface has a compound curve surface. 12. The backlighting system of claim 11, wherein the compound curve surface comprises a spherical surface or an ellipsoidal surface. 13. The backlighting system of claim 8, wherein the optical element further comprises a supporting member integrally formed with the first lens and the second lens, the supporting member comprises at least one post extending from one surface of the supporting member for fitting into a corresponding recess or hole defined in the circuit board. 14. The backlighting system of claim 8, wherein one of the plurality of LED light modules further comprises a third LED source mounted on the circuit board; and the optical element is further configured to cover the third LED source and distribute the light beams emitted from at least one of the first, second, and third LED sources into asymmetrical light patterns. 15. A fixture for presenting a visible sign to a viewer, the fixture comprising:
a target plane; and a backlighting system for directing light beams to the target plane, the backlighting system comprising a plurality of LED light modules electrically coupled with one another, one of the plurality of LED light modules comprising:
a circuit board;
a first LED source mounted on the circuit board;
a second LED source mounted on the circuit board; and
an optical element mounted on the circuit board and covering both the first LED source and the second LED source, the optical element configured to distribute the light beams emitted from at least one of the first and second LED sources into a first light pattern and a second light pattern different than the first light pattern. 16. The fixture of claim 15, wherein the first light pattern has a substantially strip-shaped pattern, and the second light pattern has a substantially strip-shaped pattern. 17. The fixture of claim 15, wherein the first light pattern is substantially perpendicular to the second light pattern. 18. The fixture of claim 15, wherein the optical element comprises:
a first lens covering the first LED source and for asymmetrically distributing first light beams emitted from the first LED source; and a second lens covering the second LED source and for asymmetrically distributing the second light beams emitted from the second LED source. 19. The fixture of claim 18, wherein the first lens and the second lens are integrally formed, and at least one of the first lens and the second lens comprises:
a curved outer surface; a curved inner surface defining a wall having a varying thickness with respect to the curved outer surface, the curved inner surface and the curved outer surface cooperating with each other to direct the light beams emitted from the LED sources to a target plane; and a planar side surface connected to the curved outer surface and the curved inner surface, the planar side surface configured to direct light beams emitted from the LED sources to the target plane to generate the asymmetrical light patterns on the target plane. 20. (canceled) 21. (canceled) 22. The fixture of claim 15, wherein the fixture comprises a channel letter sign. 23. The fixture of claim 15, wherein the fixture comprises a display lighting device. | An LED light module for illuminating a target plane is provided. The LED light module includes a first LED source, a second LED source disposed adjacent the first LED source, a first lens covering the first LED source, and a second lens covering the second LED source. The first lens is configured to direct first light beams emitted from the first light source to the target plane. The second lens is configured to direct second light beams emitted from the second light source to the target plane. At least one of the first and second lenses is shaped to have an asymmetrical profile. A backlighting system and a fixture incorporating the LED light module are also provided.1. An LED light module for illuminating a target plane, comprising:
a first LED source; a second LED source disposed adjacent the first LED source; a first lens covering the first LED source, the first lens configured to direct first light beams emitted from the first light source to the target plane; and a second lens covering the second LED source, the second lens configured to direct second light beams emitted from the second light source to the target plane; wherein at least one of the first and second lenses is shaped to have an asymmetrical profile. 2. The LED light module of claim 1, wherein the first lens and the second lens are integrally formed. 3. The LED light module of claim 1, wherein at least one of the first and second lenses comprises:
a curved outer surface; a curved inner surface defining a wall having a varying thickness with respect to the curved outer surface, the curved inner surface and the curved outer surface cooperating with each other to direct at least a part of the light beams emitted from the first and second LED sources to the target plane; and a planar side surface connected to the curved outer surface and the curved inner surface, the planar side surface configured to direct at least a part of the light beams emitted from the first and second LED sources away from the target plane. 4. The LED light module of claim 3, wherein the curved outer surface and the curved inner surface are arranged to have a uniform width measured along one direction in the target plane. 5. (canceled) 6. The LED light module of claim 5, wherein the compound curve surface comprises a spherical surface or an ellipsoidal surface. 7. The LED light module of claim 1, further comprising:
a third LED source disposed adjacent the second LED source; and a third lens covering the third LED source, the third lens configured to direct third light beams emitted from the third light LED source to the target plane; wherein at least one of the first, second, and third lenses is shaped to have an asymmetrical profile. 8. A backlighting system, comprising:
a plurality of LED light modules electrically coupled with one another, one of the plurality of LED light modules comprising:
a circuit board;
a first LED source mounted on the circuit board;
a second LED source mounted on the circuit board; and
an optical element mounted on the circuit board and covering both the first LED source and the second LED source, the optical element configured to distribute the light beams emitted from at least one of the first and second LED sources into asymmetrical light patterns. 9. The backlighting system of claim 8, wherein the optical element comprises:
a first lens covering the first LED source and for asymmetrically distributing first light beams emitted from the first LED source; and a second lens covering the second LED source and for asymmetrically distributing the second light beams emitted from the second LED source. 10. The backlighting system of claim 8, wherein the first lens and the second lens are integrally formed, and at least one of the first lens and the second lens comprises:
a curved outer surface; a curved inner surface defining a wall having a varying thickness with respect to the curved outer surface, the curved inner surface and the curved outer surface cooperating with each other to direct the light beams emitted from the first and second LED sources to a target plane; and a planar side surface connected to the curved outer surface and the curved inner surface, the planar side surface configured to direct light beams emitted from the LED sources to the target plane to generate the asymmetrical light patterns on the target plane. 11. The backlighting system of claim 8, wherein the curved outer surface has a compound curve surface. 12. The backlighting system of claim 11, wherein the compound curve surface comprises a spherical surface or an ellipsoidal surface. 13. The backlighting system of claim 8, wherein the optical element further comprises a supporting member integrally formed with the first lens and the second lens, the supporting member comprises at least one post extending from one surface of the supporting member for fitting into a corresponding recess or hole defined in the circuit board. 14. The backlighting system of claim 8, wherein one of the plurality of LED light modules further comprises a third LED source mounted on the circuit board; and the optical element is further configured to cover the third LED source and distribute the light beams emitted from at least one of the first, second, and third LED sources into asymmetrical light patterns. 15. A fixture for presenting a visible sign to a viewer, the fixture comprising:
a target plane; and a backlighting system for directing light beams to the target plane, the backlighting system comprising a plurality of LED light modules electrically coupled with one another, one of the plurality of LED light modules comprising:
a circuit board;
a first LED source mounted on the circuit board;
a second LED source mounted on the circuit board; and
an optical element mounted on the circuit board and covering both the first LED source and the second LED source, the optical element configured to distribute the light beams emitted from at least one of the first and second LED sources into a first light pattern and a second light pattern different than the first light pattern. 16. The fixture of claim 15, wherein the first light pattern has a substantially strip-shaped pattern, and the second light pattern has a substantially strip-shaped pattern. 17. The fixture of claim 15, wherein the first light pattern is substantially perpendicular to the second light pattern. 18. The fixture of claim 15, wherein the optical element comprises:
a first lens covering the first LED source and for asymmetrically distributing first light beams emitted from the first LED source; and a second lens covering the second LED source and for asymmetrically distributing the second light beams emitted from the second LED source. 19. The fixture of claim 18, wherein the first lens and the second lens are integrally formed, and at least one of the first lens and the second lens comprises:
a curved outer surface; a curved inner surface defining a wall having a varying thickness with respect to the curved outer surface, the curved inner surface and the curved outer surface cooperating with each other to direct the light beams emitted from the LED sources to a target plane; and a planar side surface connected to the curved outer surface and the curved inner surface, the planar side surface configured to direct light beams emitted from the LED sources to the target plane to generate the asymmetrical light patterns on the target plane. 20. (canceled) 21. (canceled) 22. The fixture of claim 15, wherein the fixture comprises a channel letter sign. 23. The fixture of claim 15, wherein the fixture comprises a display lighting device. | 2,800 |
12,102 | 12,102 | 15,985,380 | 2,813 | A lead frame includes a first side having a first die attach pad that is bondable to a die, and a second side that has a second die attach pad that is bondable to another die. The lead frame includes multiple leads on the edges of the lead frame to connect the die. As part of a no-leads device, such as a quad flat no leads (QFN) or dual flat no-leads (DFN), one of the die attach pads is used in binding to a die, and the other die attach pad is used for thermal dissipation and mounting to a structure such as printed circuit board (PCB). | 1. A semiconductor package comprising:
a lead frame comprising:
a first side and a second side, wherein the first side includes a first die attach pad and the second side opposite to the first side includes a second die attach pad;
a die attached to the first die attach pad via a die attach material and electrically connected to at least one of multiple leads; and
multiple leads; and a molding that covers portions of the lead frame, the die attach material, and the die, wherein a portion of the second die attach pad is exposed from the package. 2. The semiconductor package of claim 1, wherein as viewed from a cross section of the lead frame, a middle section of the lead frame, the first side, and second side are on different planes. 3. The semiconductor package of claim 1, wherein as viewed from a cross section of the lead frame, the leads of the multiple leads are shaped with an indentation on a top plane of the lead frame and an indentation on a bottom plane of the lead frame. 4. The semiconductor package of claim 1, wherein as viewed from a cross section of the lead frame, the lead frame has a total thickness of about 0.2 millimeters and the first die attach pad and second die attach pad are each about 0.05 millimeters in thickness. 5. The semiconductor package of claim 1, wherein the first die attach pad is different in area than the second die attach pad. 6. The semiconductor package of claim 1, wherein the first die attach pad and second die attach pad are about square in area. 7. The semiconductor package of claim 1, wherein the die attach material is made of epoxy, laminate film, or other adhesion material. 8. A semiconductor package comprising:
a lead frame comprising:
a first side that includes a first die attach pad bondable to a die;
a second side that includes a second die attach pad bondable to another die; and
multiple leads on the edges of the lead frame used for die connection; and
encapsulation that covers the lead frame and exposes at least one of the first die attach pad or the second die attach pad and the multiple leads. 9. The semiconductor package of claim 8 wherein the first die attach pad and second die attach pad are different in size by area and provide different thermal dissipation characteristics. 10. The semiconductor package of claim 8, wherein binding of either the first die attach pad to the die or the second die attach to the another die, uses one of an epoxy, laminate film, or adhesion material. 11. The semiconductor package of claim 8, wherein as viewed from a top or bottom view the first side, the second side, first die attach pad, and second die attach pad are rectangular in area. 12. The semiconductor package of claim 8, wherein the multiple leads are shaped with an indentation on a top plane of the lead frame and an indentation on a bottom plane of the lead frame, wherein the indentation are curved or have a right angled cut. 13. The semiconductor package of claim 8 further comprising through holes for connections for bond pads for a die bound on either the first die attach pad or the second die attach pad. 14. The semiconductor package of claim 8, wherein the semiconductor package is either a quad flat no-leads (QFN) or a dual flat no-leads (DFN). 15. A method of fabricating a no-leads device comprising:
etching a first side of a lead frame to form a first die attach pad; etching a second side of the lead frame to form a second die attach pad; determining which of the first die attach pad or the second die attach pad to bind a die to; binding the die to the die attach pad that is determined to bind the die to; connecting bond pads on the die to specific leads of a set of leads that are part of the lead frame; and adding a molding over portions of the lead frame and the die, wherein the set of leads and the pad that is not used to bind the die are exposed from the no-leads device. 16. The method of claim 15, wherein the etching is a chemical etching. 17. The method of claim 15, wherein each lead of the set of leads has an indentation coplanar to the first side and an indentation coplanar to the second side, wherein the indentations are generally curved in shape or right angle in shape. 18. The method of claim 15, wherein the first die attach pad provides a different thermal dissipation than the second die attach pad. 19. The method of 15, wherein the etching the first die attach pad defines edges of the first die attach pad and through holes for wire connections from the bond pads of a die bound to the first die attach pad, and the etching of the second die attach pad defines edges of the second die attach pad and through holes for wire connections from the bond pads of another die bound to the second die attach pad. 20. The method of 15 further comprising plating and polishing the lead frame after etching the first die attach pad and the second die attach pad. | A lead frame includes a first side having a first die attach pad that is bondable to a die, and a second side that has a second die attach pad that is bondable to another die. The lead frame includes multiple leads on the edges of the lead frame to connect the die. As part of a no-leads device, such as a quad flat no leads (QFN) or dual flat no-leads (DFN), one of the die attach pads is used in binding to a die, and the other die attach pad is used for thermal dissipation and mounting to a structure such as printed circuit board (PCB).1. A semiconductor package comprising:
a lead frame comprising:
a first side and a second side, wherein the first side includes a first die attach pad and the second side opposite to the first side includes a second die attach pad;
a die attached to the first die attach pad via a die attach material and electrically connected to at least one of multiple leads; and
multiple leads; and a molding that covers portions of the lead frame, the die attach material, and the die, wherein a portion of the second die attach pad is exposed from the package. 2. The semiconductor package of claim 1, wherein as viewed from a cross section of the lead frame, a middle section of the lead frame, the first side, and second side are on different planes. 3. The semiconductor package of claim 1, wherein as viewed from a cross section of the lead frame, the leads of the multiple leads are shaped with an indentation on a top plane of the lead frame and an indentation on a bottom plane of the lead frame. 4. The semiconductor package of claim 1, wherein as viewed from a cross section of the lead frame, the lead frame has a total thickness of about 0.2 millimeters and the first die attach pad and second die attach pad are each about 0.05 millimeters in thickness. 5. The semiconductor package of claim 1, wherein the first die attach pad is different in area than the second die attach pad. 6. The semiconductor package of claim 1, wherein the first die attach pad and second die attach pad are about square in area. 7. The semiconductor package of claim 1, wherein the die attach material is made of epoxy, laminate film, or other adhesion material. 8. A semiconductor package comprising:
a lead frame comprising:
a first side that includes a first die attach pad bondable to a die;
a second side that includes a second die attach pad bondable to another die; and
multiple leads on the edges of the lead frame used for die connection; and
encapsulation that covers the lead frame and exposes at least one of the first die attach pad or the second die attach pad and the multiple leads. 9. The semiconductor package of claim 8 wherein the first die attach pad and second die attach pad are different in size by area and provide different thermal dissipation characteristics. 10. The semiconductor package of claim 8, wherein binding of either the first die attach pad to the die or the second die attach to the another die, uses one of an epoxy, laminate film, or adhesion material. 11. The semiconductor package of claim 8, wherein as viewed from a top or bottom view the first side, the second side, first die attach pad, and second die attach pad are rectangular in area. 12. The semiconductor package of claim 8, wherein the multiple leads are shaped with an indentation on a top plane of the lead frame and an indentation on a bottom plane of the lead frame, wherein the indentation are curved or have a right angled cut. 13. The semiconductor package of claim 8 further comprising through holes for connections for bond pads for a die bound on either the first die attach pad or the second die attach pad. 14. The semiconductor package of claim 8, wherein the semiconductor package is either a quad flat no-leads (QFN) or a dual flat no-leads (DFN). 15. A method of fabricating a no-leads device comprising:
etching a first side of a lead frame to form a first die attach pad; etching a second side of the lead frame to form a second die attach pad; determining which of the first die attach pad or the second die attach pad to bind a die to; binding the die to the die attach pad that is determined to bind the die to; connecting bond pads on the die to specific leads of a set of leads that are part of the lead frame; and adding a molding over portions of the lead frame and the die, wherein the set of leads and the pad that is not used to bind the die are exposed from the no-leads device. 16. The method of claim 15, wherein the etching is a chemical etching. 17. The method of claim 15, wherein each lead of the set of leads has an indentation coplanar to the first side and an indentation coplanar to the second side, wherein the indentations are generally curved in shape or right angle in shape. 18. The method of claim 15, wherein the first die attach pad provides a different thermal dissipation than the second die attach pad. 19. The method of 15, wherein the etching the first die attach pad defines edges of the first die attach pad and through holes for wire connections from the bond pads of a die bound to the first die attach pad, and the etching of the second die attach pad defines edges of the second die attach pad and through holes for wire connections from the bond pads of another die bound to the second die attach pad. 20. The method of 15 further comprising plating and polishing the lead frame after etching the first die attach pad and the second die attach pad. | 2,800 |
12,103 | 12,103 | 15,656,937 | 2,881 | A system for treating a patient during radiation therapy includes range compensators. Each of the range compensators shapes a distribution of a dose delivered to the patient by a beam emitted from a nozzle of a radiation treatment system. A positioning component holds the range compensator in place relative to the patient such that the range compensator lies on a path of the beam. | 1. A system for treating a patient during radiation therapy, the system comprising:
a plurality of range compensators, wherein each range compensator of the plurality of range compensators respectively shapes a distribution of a dose delivered to the patient by a respective beam of a plurality of beams emitted from a nozzle of a radiation treatment system; and a positioning component coupled to a range compensator of the plurality of range compensators and that holds the range compensator in place relative to the patient such that the range compensator lies on a path of at least one of the beams. 2. The system of claim 1, wherein the range compensator has a non-uniform thickness measured in the direction of the path of a beam. 3. The system of claim 1, wherein the plurality of beams comprises beams selected from the group consisting of proton beams and ion beams, and wherein said each range compensator is configured to locate a Bragg peak of the respective beam inside a target in the patient. 4. The system of claim 1, wherein the range compensator is part of an immobilization device that limits movement of the patient on a patient support device relative to the beams. 5. The system of claim 4, wherein the positioning component fastens the immobilization device to the patient. 6. The system of claim 4, wherein the positioning component fastens the immobilization device to an item worn by the patient. 7. The system of claim 1, wherein the positioning component is further coupled to each range compensator of the plurality of range compensators and holds said each range compensator in place relative to the patient such that said each range compensator lies on a path of at least one of the beams. 8. The system of claim 1, wherein each range compensator of the plurality of range compensators is coupled to a respective positioning component. 9. The system of claim 1, wherein the positioning component has a shape that fits contours of the patient. 10. The system of claim 1, wherein the range compensator and the positioning component are fabricated as a single piece. 11. A computer-implemented method of radiation treatment planning, the method comprising:
accessing, from a memory of the computer, parameters for a radiation treatment plan, the parameters comprising a number of beams and paths of the beams relative to a position of a patient on a patient support device; and identifying locations on the patient for a plurality of range compensators, wherein each range compensator of the plurality of range compensators is located on the patient so that said each range compensator lies on at least one of the beam paths and respectively shapes a distribution of a dose to be delivered to the patient by at least one of the beams. 12. The method of claim 11, wherein said each range compensator has a non-uniform thickness measured in the direction of a path of a beam. 13. The method of claim 11, wherein the beams comprise beams selected from the group consisting of proton beams and ion beams, and wherein said each range compensator is configured to locate a Bragg peak of the at least one beam inside a target in the patient. 14. The method of claim 11, wherein a positioning component is coupled to each range compensator of the plurality of range compensators and holds said each range compensator in place relative to the patient. 15. The method of claim 14, wherein the range compensators comprise a range compensator that is part of an immobilization device that limits movement of the patient on a patient support device relative to the beams. 16. The method of claim 15, further comprising:
accessing, from a memory of the computer, a printing plan for the immobilization device; and controlling a three-dimensional printer using the printing plan to fabricate the immobilization device. 17. A computer-implemented radiation treatment method, comprising:
accessing, from a memory of the computer, a radiation treatment plan that prescribes a distribution of a dose to be delivered to a target in a patient by a plurality of beams emitted from a nozzle of a radiation treatment system; and controlling the nozzle to aim the beams at a plurality of range compensators positioned at different locations on the patient, wherein each range compensator of the plurality of range compensators respectively shapes a distribution of a dose delivered to the patient by a respective beam of the plurality of beams, wherein said controlling comprises:
aiming the nozzle at a first range compensator of the plurality of range compensators and then turning on and emitting a first beam at the first range compensator; and
turning off the first beam and then: aiming the nozzle at a second range compensator of the plurality of range compensators and turning on and emitting a second beam at the second range compensator. 18. The method of claim 17, wherein said each range compensator has a non-uniform thickness measured in the direction of a path of a beam. 19. The method of claim 17, wherein the beams comprise beams selected from the group consisting of proton beams and ion beams, and wherein said each range compensator is configured to locate a Bragg peak of the respective beam inside the target. 20. The method of claim 17, wherein a positioning component is coupled to the plurality of range compensators and holds each of the range compensators in place relative to the patient such that each of the range compensators lies on a path of at least one of the beams, and wherein the range compensators comprise a range compensator that is part of an immobilization device that limits movement of the patient on a patient support device relative to the beams. | A system for treating a patient during radiation therapy includes range compensators. Each of the range compensators shapes a distribution of a dose delivered to the patient by a beam emitted from a nozzle of a radiation treatment system. A positioning component holds the range compensator in place relative to the patient such that the range compensator lies on a path of the beam.1. A system for treating a patient during radiation therapy, the system comprising:
a plurality of range compensators, wherein each range compensator of the plurality of range compensators respectively shapes a distribution of a dose delivered to the patient by a respective beam of a plurality of beams emitted from a nozzle of a radiation treatment system; and a positioning component coupled to a range compensator of the plurality of range compensators and that holds the range compensator in place relative to the patient such that the range compensator lies on a path of at least one of the beams. 2. The system of claim 1, wherein the range compensator has a non-uniform thickness measured in the direction of the path of a beam. 3. The system of claim 1, wherein the plurality of beams comprises beams selected from the group consisting of proton beams and ion beams, and wherein said each range compensator is configured to locate a Bragg peak of the respective beam inside a target in the patient. 4. The system of claim 1, wherein the range compensator is part of an immobilization device that limits movement of the patient on a patient support device relative to the beams. 5. The system of claim 4, wherein the positioning component fastens the immobilization device to the patient. 6. The system of claim 4, wherein the positioning component fastens the immobilization device to an item worn by the patient. 7. The system of claim 1, wherein the positioning component is further coupled to each range compensator of the plurality of range compensators and holds said each range compensator in place relative to the patient such that said each range compensator lies on a path of at least one of the beams. 8. The system of claim 1, wherein each range compensator of the plurality of range compensators is coupled to a respective positioning component. 9. The system of claim 1, wherein the positioning component has a shape that fits contours of the patient. 10. The system of claim 1, wherein the range compensator and the positioning component are fabricated as a single piece. 11. A computer-implemented method of radiation treatment planning, the method comprising:
accessing, from a memory of the computer, parameters for a radiation treatment plan, the parameters comprising a number of beams and paths of the beams relative to a position of a patient on a patient support device; and identifying locations on the patient for a plurality of range compensators, wherein each range compensator of the plurality of range compensators is located on the patient so that said each range compensator lies on at least one of the beam paths and respectively shapes a distribution of a dose to be delivered to the patient by at least one of the beams. 12. The method of claim 11, wherein said each range compensator has a non-uniform thickness measured in the direction of a path of a beam. 13. The method of claim 11, wherein the beams comprise beams selected from the group consisting of proton beams and ion beams, and wherein said each range compensator is configured to locate a Bragg peak of the at least one beam inside a target in the patient. 14. The method of claim 11, wherein a positioning component is coupled to each range compensator of the plurality of range compensators and holds said each range compensator in place relative to the patient. 15. The method of claim 14, wherein the range compensators comprise a range compensator that is part of an immobilization device that limits movement of the patient on a patient support device relative to the beams. 16. The method of claim 15, further comprising:
accessing, from a memory of the computer, a printing plan for the immobilization device; and controlling a three-dimensional printer using the printing plan to fabricate the immobilization device. 17. A computer-implemented radiation treatment method, comprising:
accessing, from a memory of the computer, a radiation treatment plan that prescribes a distribution of a dose to be delivered to a target in a patient by a plurality of beams emitted from a nozzle of a radiation treatment system; and controlling the nozzle to aim the beams at a plurality of range compensators positioned at different locations on the patient, wherein each range compensator of the plurality of range compensators respectively shapes a distribution of a dose delivered to the patient by a respective beam of the plurality of beams, wherein said controlling comprises:
aiming the nozzle at a first range compensator of the plurality of range compensators and then turning on and emitting a first beam at the first range compensator; and
turning off the first beam and then: aiming the nozzle at a second range compensator of the plurality of range compensators and turning on and emitting a second beam at the second range compensator. 18. The method of claim 17, wherein said each range compensator has a non-uniform thickness measured in the direction of a path of a beam. 19. The method of claim 17, wherein the beams comprise beams selected from the group consisting of proton beams and ion beams, and wherein said each range compensator is configured to locate a Bragg peak of the respective beam inside the target. 20. The method of claim 17, wherein a positioning component is coupled to the plurality of range compensators and holds each of the range compensators in place relative to the patient such that each of the range compensators lies on a path of at least one of the beams, and wherein the range compensators comprise a range compensator that is part of an immobilization device that limits movement of the patient on a patient support device relative to the beams. | 2,800 |
12,104 | 12,104 | 15,583,569 | 2,822 | An image sensor is provided. The image sensor includes a substrate having a first region and a second region adjacent to each other; and a first photoelectric conversion component disposed on the first region of the substrate, and the first photoelectric conversion component includes: a first metal layer formed on the substrate; a first photoelectric conversion layer formed on the first metal layer; and a second metal layer formed on the first photoelectric conversion layer. | 1. An image sensor, comprising:
a substrate having a first region and a second region adjacent to each other; and a first photoelectric conversion component disposed on the first region of the substrate, wherein the first photoelectric conversion component comprises: a first metal layer formed on the substrate; a first photoelectric conversion layer formed on the first metal layer; and a second metal layer formed on the first photoelectric conversion layer. 2. The image sensor as claimed in claim 1, wherein the first photoelectric conversion layer comprises a doped semiconductor layer or a quantum film. 3. The image sensor as claimed in claim 1, wherein the first metal layer and the second metal layer independently comprises Ag, Au, Cu, W, Al, Mo, Ti, Pt, Ir, Ni, Cr, Rh, alloys thereof, or a combination thereof. 4. The image sensor as claimed in claim 1, wherein the first metal layer is thicker than the second metal layer. 5. The image sensor as claimed in claim 1, wherein the first metal layer and the second metal layer have substantially the same thickness. 6. The image sensor as claimed in claim 1, further comprising:
a second photoelectric conversion component disposed in the second region of the substrate, wherein the second photoelectric conversion component is embedded in the substrate; a high-k dielectric layer disposed on the second photoelectric conversion component; and a transparent layer disposed on the high-k dielectric layer. 7. The image sensor as claimed in claim 6, wherein the second photoelectric conversion component is spaced apart from the first metal layer of the first photoelectric conversion component. 8. The image sensor as claimed in claim 6, wherein the transparent layer extends over the first photoelectric conversion component. 9. The image sensor as claimed in claim 6, wherein the high-k dielectric layer is formed on both the first region and the second region of the substrate. 10. The image sensor as claimed in claim 6, wherein a top surface of the first photoelectric conversion component is higher than a top surface of the transparent layer. 11. The image sensor as claimed in claim 1, further comprising:
a cover layer disposed on the first photoelectric conversion component, wherein the cover layer comprises a semiconductor material or a dielectric material. 12. The image sensor as claimed in claim 1, further comprising:
a microlens disposed on the first photoelectric conversion component. 13. The image sensor as claimed in claim 1, wherein the first photoelectric conversion component further comprises:
a first additional photoelectric conversion layer disposed on the second metal layer; and a third metal layer disposed on the first additional photoelectric conversion layer. 14. The image sensor as claimed in claim 13, wherein the first photoelectric conversion component further comprises:
a second additional photoelectric conversion layer disposed on the third metal layer; and a fourth metal layer disposed on the second additional photoelectric conversion layer. 15. An image sensor, comprising:
a substrate having a first region and a second region, wherein the second region is adjacent to the first region; a first photoelectric conversion component disposed on the first region of the substrate, wherein the first photoelectric conversion component comprises: a first bottom metal layer formed on the substrate; a first photoelectric conversion layer formed on the first bottom metal layer, wherein the first photoelectric conversion layer has a first thickness; and a first top metal layer formed on the first photoelectric conversion layer; and a second photoelectric conversion component disposed on the second region of the substrate, wherein the second photoelectric conversion component comprises: a second bottom metal layer formed on the substrate; a second photoelectric conversion layer formed on the second bottom metal layer, wherein the second photoelectric conversion layer has a second thickness; and a second top metal layer formed on the second photoelectric conversion layer, wherein the first thickness is greater than the second thickness. 16. The image sensor as claimed in claim 15, further comprising:
a third photoelectric conversion component disposed on a third region of the substrate, wherein the third region is adjacent to the second region, wherein the third photoelectric conversion component comprises: a third bottom metal layer formed on the substrate; a third photoelectric conversion layer formed on the third bottom metal layer, wherein the third photoelectric conversion layer has a third thickness; and a third top metal layer formed on the third photoelectric conversion layer, wherein the second thickness is greater than the third thickness. 17. The image sensor as claimed in claim 16, further comprising:
a fourth photoelectric conversion component disposed on a fourth region of the substrate, wherein the fourth region is adjacent to the third region, wherein the fourth photoelectric conversion component comprises: a fourth bottom metal layer formed on the substrate; a fourth photoelectric conversion layer formed on the fourth bottom metal layer, wherein the fourth photoelectric conversion layer has a fourth thickness; and a fourth top metal layer formed on the fourth photoelectric conversion layer, wherein the third thickness is greater than the fourth thickness. 18. The image sensor as claimed in claim 17, further comprising:
a first microlens disposed on the first photoelectric conversion component; a second microlens disposed on the second photoelectric conversion component; a third microlens disposed on the third photoelectric conversion component; and a fourth microlens disposed on the fourth photoelectric conversion component. 19. The image sensor as claimed in claim 15, wherein a top surface of the first top metal layer of the first photoelectric conversion component is higher than a top surface of the second top metal layer of the second photoelectric conversion component. 20. The image sensor as claimed in claim 15, wherein the second photoelectric conversion component further comprises a transparent layer disposed between the second photoelectric conversion layer and the second top metal layer, wherein a top surface of the first top metal layer of the first photoelectric conversion component is substantially coplanar with a top surface of the second top metal layer of the second photoelectric conversion component. | An image sensor is provided. The image sensor includes a substrate having a first region and a second region adjacent to each other; and a first photoelectric conversion component disposed on the first region of the substrate, and the first photoelectric conversion component includes: a first metal layer formed on the substrate; a first photoelectric conversion layer formed on the first metal layer; and a second metal layer formed on the first photoelectric conversion layer.1. An image sensor, comprising:
a substrate having a first region and a second region adjacent to each other; and a first photoelectric conversion component disposed on the first region of the substrate, wherein the first photoelectric conversion component comprises: a first metal layer formed on the substrate; a first photoelectric conversion layer formed on the first metal layer; and a second metal layer formed on the first photoelectric conversion layer. 2. The image sensor as claimed in claim 1, wherein the first photoelectric conversion layer comprises a doped semiconductor layer or a quantum film. 3. The image sensor as claimed in claim 1, wherein the first metal layer and the second metal layer independently comprises Ag, Au, Cu, W, Al, Mo, Ti, Pt, Ir, Ni, Cr, Rh, alloys thereof, or a combination thereof. 4. The image sensor as claimed in claim 1, wherein the first metal layer is thicker than the second metal layer. 5. The image sensor as claimed in claim 1, wherein the first metal layer and the second metal layer have substantially the same thickness. 6. The image sensor as claimed in claim 1, further comprising:
a second photoelectric conversion component disposed in the second region of the substrate, wherein the second photoelectric conversion component is embedded in the substrate; a high-k dielectric layer disposed on the second photoelectric conversion component; and a transparent layer disposed on the high-k dielectric layer. 7. The image sensor as claimed in claim 6, wherein the second photoelectric conversion component is spaced apart from the first metal layer of the first photoelectric conversion component. 8. The image sensor as claimed in claim 6, wherein the transparent layer extends over the first photoelectric conversion component. 9. The image sensor as claimed in claim 6, wherein the high-k dielectric layer is formed on both the first region and the second region of the substrate. 10. The image sensor as claimed in claim 6, wherein a top surface of the first photoelectric conversion component is higher than a top surface of the transparent layer. 11. The image sensor as claimed in claim 1, further comprising:
a cover layer disposed on the first photoelectric conversion component, wherein the cover layer comprises a semiconductor material or a dielectric material. 12. The image sensor as claimed in claim 1, further comprising:
a microlens disposed on the first photoelectric conversion component. 13. The image sensor as claimed in claim 1, wherein the first photoelectric conversion component further comprises:
a first additional photoelectric conversion layer disposed on the second metal layer; and a third metal layer disposed on the first additional photoelectric conversion layer. 14. The image sensor as claimed in claim 13, wherein the first photoelectric conversion component further comprises:
a second additional photoelectric conversion layer disposed on the third metal layer; and a fourth metal layer disposed on the second additional photoelectric conversion layer. 15. An image sensor, comprising:
a substrate having a first region and a second region, wherein the second region is adjacent to the first region; a first photoelectric conversion component disposed on the first region of the substrate, wherein the first photoelectric conversion component comprises: a first bottom metal layer formed on the substrate; a first photoelectric conversion layer formed on the first bottom metal layer, wherein the first photoelectric conversion layer has a first thickness; and a first top metal layer formed on the first photoelectric conversion layer; and a second photoelectric conversion component disposed on the second region of the substrate, wherein the second photoelectric conversion component comprises: a second bottom metal layer formed on the substrate; a second photoelectric conversion layer formed on the second bottom metal layer, wherein the second photoelectric conversion layer has a second thickness; and a second top metal layer formed on the second photoelectric conversion layer, wherein the first thickness is greater than the second thickness. 16. The image sensor as claimed in claim 15, further comprising:
a third photoelectric conversion component disposed on a third region of the substrate, wherein the third region is adjacent to the second region, wherein the third photoelectric conversion component comprises: a third bottom metal layer formed on the substrate; a third photoelectric conversion layer formed on the third bottom metal layer, wherein the third photoelectric conversion layer has a third thickness; and a third top metal layer formed on the third photoelectric conversion layer, wherein the second thickness is greater than the third thickness. 17. The image sensor as claimed in claim 16, further comprising:
a fourth photoelectric conversion component disposed on a fourth region of the substrate, wherein the fourth region is adjacent to the third region, wherein the fourth photoelectric conversion component comprises: a fourth bottom metal layer formed on the substrate; a fourth photoelectric conversion layer formed on the fourth bottom metal layer, wherein the fourth photoelectric conversion layer has a fourth thickness; and a fourth top metal layer formed on the fourth photoelectric conversion layer, wherein the third thickness is greater than the fourth thickness. 18. The image sensor as claimed in claim 17, further comprising:
a first microlens disposed on the first photoelectric conversion component; a second microlens disposed on the second photoelectric conversion component; a third microlens disposed on the third photoelectric conversion component; and a fourth microlens disposed on the fourth photoelectric conversion component. 19. The image sensor as claimed in claim 15, wherein a top surface of the first top metal layer of the first photoelectric conversion component is higher than a top surface of the second top metal layer of the second photoelectric conversion component. 20. The image sensor as claimed in claim 15, wherein the second photoelectric conversion component further comprises a transparent layer disposed between the second photoelectric conversion layer and the second top metal layer, wherein a top surface of the first top metal layer of the first photoelectric conversion component is substantially coplanar with a top surface of the second top metal layer of the second photoelectric conversion component. | 2,800 |
12,105 | 12,105 | 13,508,495 | 2,865 | The present invention may include acquiring a plurality of overlay metrology measurement signals from a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers, determining a plurality of overlay estimates for each of the plurality of overlay metrology measurement signals using a plurality of overlay algorithms, generating a plurality of overlay estimate distributions, and generating a first plurality of quality metrics utilizing the generated plurality of overlay estimate distributions, wherein each quality metric corresponds with one overlay estimate distribution of the generated plurality of overlay estimate distributions, each quality metric a function of a width of a corresponding generated overlay estimate distribution, each quality metric further being a function of asymmetry present in an overlay metrology measurement signal from an associated metrology target. | 1. A computer-implemented method for providing a quality metric suitable for improving process control in a semiconductor wafer fabrication, comprising process:
acquiring a plurality of overlay metrology measurement signals from a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers, each overlay metrology measurement signal corresponding with a metrology target of the plurality of metrology targets, the plurality of overlay metrology measurement signals acquired utilizing a first measurement recipe; determining a plurality of overlay estimates for each of the plurality of overlay metrology measurement signals by applying a plurality of overlay algorithms to each overlay metrology measurement signal, each overlay estimate determined utilizing one of the overlay algorithms; generating a plurality of overlay estimate distributions by generating an overlay estimate distribution for each of the plurality of overlay metrology measurement signals from the plurality of metrology targets utilizing the plurality of overlay estimates; and generating a first plurality of quality metrics utilizing the generated plurality of overlay estimate distributions, wherein each quality metric corresponds with one overlay estimate distribution of the generated plurality of overlay estimate distributions, each quality metric a function of a width of a corresponding generated overlay estimate distribution, each quality metric further being a function of asymmetry present in an overlay metrology measurement signal from an associated metrology target. 2. The method of claim 1, wherein acquiring a plurality of overlay metrology measurement signals from a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers comprises:
performing an overlay metrology measurement on a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers. 3. The method of claim 1, further comprising:
performing a tool induced shift (TIS) correction process to at least some of the acquired plurality of overlay metrology measurement signals. 4. The method of claim 1, wherein each of the plurality of generated quality metrics is configured to identify an overlay deviation from a metrology target having substantially symmetric target structures. 5. The method of claim 1, further comprising:
identifying one or more metrology targets of the plurality of metrology targets having a quality metric larger than a selected outlier level along at least one direction from a distribution of the plurality of quality metrics generated for the plurality of metrology targets; determining a corrected plurality of metrology targets, wherein the corrected plurality of metrology targets excludes the identified one or more metrology targets having a quality metric deviating beyond a selected outlier level from the plurality of metrology targets; and calculating a set of correctables utilizing the determined corrected plurality of metrology targets. 6. The method of claim 1, further comprising:
transmitting the set of correctables to one or more process tools. 7. The method of claim 1, further comprising:
acquiring at least an additional plurality of overlay metrology measurement signals from the plurality of metrology targets distributed across the one or more fields of the wafer of the lot of wafers, each overlay metrology measurement signal of the at least an additional plurality of overlay metrology measurement signals corresponding with a metrology target of the plurality of metrology targets, the at least an additional plurality of overlay metrology measurement signals acquired utilizing at least an additional measurement recipe; determining at least an additional plurality of overlay estimates for each of the at least an additional plurality of overlay measurement signals by applying the plurality of overlay algorithms to each overlay measurement signal of the at least an additional plurality of measurement signals, each of the at least an additional plurality of overlay estimates determined utilizing one of the overlay algorithms; generating at least an additional plurality of overlay estimate distributions by generating an overlay estimate distribution for each of the at least an additional plurality of overlay measurement signals from the plurality of metrology targets utilizing the plurality of overlay estimates; and generating at least an additional plurality of quality metrics utilizing the generated at least an additional plurality of overlay estimate distributions, wherein each quality metric of the at least an additional plurality of quality metrics corresponds with one overlay estimate distribution of the generated at least an additional plurality of overlay estimate distributions, each quality metric of the at least an additional plurality of quality metrics a function of a width of a corresponding generated overlay estimate distribution of the at least an additional plurality of overlay estimate distributions; determining a process measurement recipe by comparing a distribution of the first plurality of quality metrics associated with the first measurement recipe to a distribution of the at least an additional plurality of quality metrics associated with the at least one additional measurement recipe. 8. The method of claim 7, wherein the determining a process measurement recipe by comparing a distribution of the first plurality of quality metrics associated with the first measurement recipe to a distribution of the at least an additional plurality of quality metrics associated with the at least one additional measurement recipe comprises:
determining an optimum measurement recipe by comparing a distribution of the first plurality of quality metrics associated with the first measurement recipe to a distribution of the at least an additional plurality of quality metrics associated with the at least one additional measurement recipe, the optimum measurement recipe associated with a plurality of quality metrics of the first plurality of metrics and the at least an additional plurality of metrics having a substantially minimum distribution in at least one direction. 9. The method of claim 7, wherein at least one of the first measurement recipe or the at least an additional measurement recipe comprise:
at least one of a wavelength of illumination, a filter configuration, a direction of illumination, a focus position, or polarization configuration. 10. A computer-implemented method for determining a quality metric suitable for improving process control in a semiconductor wafer fabrication process:
acquiring a metrology measurement signal from one or more metrology targets of one or more fields of a wafer of a lot of wafers; determining a plurality of overlay estimates by applying a plurality of overlay algorithms to the acquired metrology measurement signal, each overlay estimate determined utilizing one of the overlay algorithms; generating an overlay estimate distribution utilizing the plurality of overlay estimates; and generating a quality metric for the one or more metrology targets utilizing the generated overlay estimate distribution, the quality metric a function of a width of the generated overlay estimate distribution, the quality metric configured to be non-zero for asymmetric overlay measurement signals, the quality metric a function of a width of the generated overlay estimate distribution, the quality metric further being a function of asymmetry present in the metrology measurement signal acquired from an associated metrology target. 11. A computer-implemented method for providing a set of process tool correctables, comprising:
acquiring an overlay metrology result for each metrology target of a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers; acquiring a quality metric associated with each acquired overlay metrology result; determining a plurality of modified overlay values for the plurality of metrology targets utilizing the acquired overlay metrology result and the associated quality metric result for each metrology target, wherein the modified overlay function is a function of at least one material parameter factor; generating a process tool correctable function and a set of residuals corresponding with the process tool correctable function for a plurality of material parameter factors; determining a value of the material parameter factor suitable for at least substantially minimizing the set of residuals; and determining a set of process correctables associated with the at least substantially minimized set of residuals. 12. The method of claim 11, wherein the acquiring a quality metric associated with each acquired overlay metrology result, comprises:
generating a quality metric for each acquired overlay metrology result utilizing a quality metric generation process. 13. The method of claim 11, wherein the acquiring an overlay metrology result for each metrology target of a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers, comprises:
performing an overlay measurement on each metrology target of a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers. 14. The method of claim 11, further comprising:
transmitting the set of process tool correctables associated with the at least substantially minimized set of residuals to one or more process tools. 15. The method of claim 11, further comprising:
performing a tool induced shift (TIS) correction process to at least some of the acquired plurality of overlay metrology measurement signals. 16. The method of claim 11, wherein the modified overlay function is a linear function of at least one material parameter factor. 17. The method of claim 11, wherein the modified overlay function is a function of at least one of a wavelength of illumination, a focus position, a direction of illumination, a polarization configuration, or a filter configuration. 18. A computer-implemented method for identifying a variation in process tool correctables, comprising:
acquiring an overlay metrology result for each metrology target of a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers; acquiring a quality metric associated with each acquired overlay metrology result; determining a plurality of modified overlay values for the plurality of metrology targets utilizing the acquired overlay metrology result for each metrology target and a quality function, the quality function being a function of the acquired quality metric of each metrology target; generating a plurality of sets of process tool correctables by determining a set of process tool correctables for each of a plurality of randomly selected samplings of the acquired overlay metrology results and the associated quality metrics of the plurality of metrology targets utilizing the plurality of modified overlay values, wherein each of the random samplings is of the same size; and identifying a variation in the plurality of sets of process tool correctables. 19. The method of claim 18, wherein the acquiring a quality metric associated with each acquired overlay metrology result, comprises:
generating a quality metric for each acquired overlay metrology result utilizing a quality metric generation process. 20. The method of claim 18, wherein the acquiring an overlay metrology result for each metrology target of a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers, comprises:
performing an overlay measurement on each metrology target of a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers. 21. A computer-implemented method for generating a metrology sampling plan, comprising:
acquiring a plurality of overlay metrology measurement signals from a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers, each overlay metrology measurement signal corresponding with a metrology target of the plurality of metrology targets; determining a plurality of overlay estimates for each of the plurality of overlay metrology measurement signals by applying a plurality of overlay algorithms to each overlay metrology measurement signal, each overlay estimate determined utilizing one of the overlay algorithms; generating a plurality of overlay estimate distributions by generating an overlay estimate distribution for each of the plurality of overlay metrology measurement signals from the plurality of metrology targets utilizing the plurality of overlay estimates; generating a first plurality of quality metrics utilizing the generated plurality of overlay estimate distributions, wherein each quality metric corresponds with one overlay estimate distribution of the generated plurality of overlay estimate distributions, each quality metric further being a function of asymmetry present in an overlay metrology measurement signal from an associated metrology target; and generating one or more metrology sampling plans utilizing the generated first plurality of quality metrics of the plurality of metrology targets. 22. The method of claim 21, wherein the generating one or more metrology sampling plans utilizing the generated first plurality of quality metrics of the plurality of metrology targets, comprises:
generating one or more metrology sampling plans utilizing the generated first plurality of quality metrics of the plurality of metrology targets to identify one or more low quality targets, wherein the one or more low quality targets are excluded from the generated one or more metrology sampling plan. 23. The method of claim 21, wherein the generating one or more metrology sampling plans utilizing the generated first plurality of quality metrics of the plurality of metrology targets, comprises:
generating one or more metrology sampling plans utilizing the generated first plurality of quality metrics of the plurality of metrology targets to identify one or more low quality targets of the wafer, wherein the one or more low quality targets are excluded from the generated one or more metrology sampling plans and one or more additional metrology targets located proximate to the one or more low quality targets are utilized to replace the one or more low quality targets. 24. The method of claim 21, further comprising:
identifying a plurality of quality zones of the wafer utilizing the first plurality of quality metrics, each of the quality zones including a plurality of metrology targets having substantially similar quality levels. 25. The method of claim 24, wherein a metrology sampling rate at one or more locations across the wafer is defined by each of the plurality of quality zones. 26. The method of claim 21, further comprising:
performing one or more metrology measurements on a subsequent wafer utilizing the generated sampling plan. 27. A computer-implemented method for providing process signature mapping, comprising:
forming a plurality of proxy targets on a reticle; forming a plurality of device correlation targets on a wafer; determining a first process signature as a function of position across the wafer by comparing a first set of metrology results acquired from the plurality of proxy targets following a lithography process and prior to a first etching process of the wafer and at least a second set of metrology results acquired from the plurality of proxy targets following the first etching process of the wafer; correlating the first process signature with a specific process path; measuring a device correlation bias following the first etching process by performing a first set of metrology measurements on the plurality of device correlation targets of the wafer, the device correlation bias being the bias between a metrology structure and a device of the wafer; determining an additional etch signature for each additional process layer and for each additional non-lithographic process path of the wafer as a function of position across the wafer; measuring an additional device correlation bias following each additional process layer and each additional non-lithographic process path of the wafer; and generating a process signature map database utilizing the determined first etch signature and each of the additional etch signatures and the first measured device correlation bias and each additional device correlation bias. 28. The method of claim 27, wherein the comparing a first set of metrology results acquired from the plurality of proxy targets following a lithography process and prior to a first etching process of the wafer and at least a second set of metrology results acquired from the plurality of proxy targets following the first etching process of the wafer comprises:
determining a difference between a first set of metrology results acquired from the plurality of proxy targets following a lithography process and prior to a first etching process of the wafer and at least a second set of metrology results acquired from the plurality of proxy targets following the first etching process of the wafer. 29. The method of claim 27, wherein the first set of metrology results from the plurality of proxy targets are acquired following a lithography process by performing a first set of metrology measurements on the plurality of proxy targets following a lithography process. 30. The method of claim 27, wherein the at least a second set of metrology results from the plurality of proxy targets are acquired following the first etching process of the wafer by performing at least a second set of metrology measurements on the plurality of proxy targets following the first etching process of the wafer. 31. The method of claim 27, wherein at least one of the first set of metrology results from the plurality of proxy targets or the at least a second set of metrology results from the plurality of proxy targets are acquired utilizing one or more overlay metrology processes. 32. The method of claim 27, wherein the measuring a device correlation bias following the first etching process by performing a first set of metrology measurements on the plurality of device correlation targets of the wafer comprises:
measuring a device correlation bias following the first etching process by performing a first set metrology measurements on the plurality of device correlation targets of the wafer, the first set of metrology measurements performed utilizing at least one of a CD-SEM based metrology system or an AFM-based metrology system. 33. The method of claim 27, wherein the reticle is at least one of a test reticle or a product reticle. 34. The method of claim 27, further comprising:
operating an advance process control loop utilizing the generated process signature map database. 35. The method of claim 27, further comprising:
generating a set of process signature mapping correctables. 36. A system for providing a quality metric suitable for improving process control in a semiconductor wafer fabrication, comprising process:
a metrology system configured to acquire a plurality of overlay metrology measurement signals from a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers, each overlay metrology measurement signal corresponding with a metrology target of the plurality of metrology targets, the plurality of overlay metrology measurement signals acquired utilizing a first measurement recipe; and a computing system configured to:
determine a plurality of overlay estimates for each of the plurality of overlay metrology measurement signals by applying a plurality of overlay algorithms to each overlay metrology measurement signal, each overlay estimate determined utilizing one of the overlay algorithms;
generate a plurality of overlay estimate distributions by generating an overlay estimate distribution for each of the plurality of overlay metrology measurement signals from the plurality of metrology targets utilizing the plurality of overlay estimates; and
generate a first plurality of quality metrics utilizing the generated plurality of overlay estimate distributions, wherein each quality metric corresponds with one overlay estimate distribution of the generated plurality of overlay estimate distributions, each quality metric a function of a width of a corresponding generated overlay estimate distribution, each quality metric further being a function of asymmetry present in an overlay metrology measurement signal from an associated metrology target. 37. The system of claim 36, wherein the computing system is further configured to identify one or more outlier metrology targets utilizing the generated first plurality of quality metrics. 38. The system of claim 36, wherein the computing system is further configured to determine an optimum overlay measurement recipe utilizing the generated first plurality of quality metrics. 39. The system of claim 36, wherein the computing system is further configured to generate one or more process tool correctables utilizing the generated first plurality of quality metrics. 40. The system of claim 36, wherein the computing system is further configured to generate one or more sampling plans utilizing the generated first plurality of quality metrics. 41. The system of claim 36, wherein the computing system is further configured to generate a process signature mapping database. | The present invention may include acquiring a plurality of overlay metrology measurement signals from a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers, determining a plurality of overlay estimates for each of the plurality of overlay metrology measurement signals using a plurality of overlay algorithms, generating a plurality of overlay estimate distributions, and generating a first plurality of quality metrics utilizing the generated plurality of overlay estimate distributions, wherein each quality metric corresponds with one overlay estimate distribution of the generated plurality of overlay estimate distributions, each quality metric a function of a width of a corresponding generated overlay estimate distribution, each quality metric further being a function of asymmetry present in an overlay metrology measurement signal from an associated metrology target.1. A computer-implemented method for providing a quality metric suitable for improving process control in a semiconductor wafer fabrication, comprising process:
acquiring a plurality of overlay metrology measurement signals from a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers, each overlay metrology measurement signal corresponding with a metrology target of the plurality of metrology targets, the plurality of overlay metrology measurement signals acquired utilizing a first measurement recipe; determining a plurality of overlay estimates for each of the plurality of overlay metrology measurement signals by applying a plurality of overlay algorithms to each overlay metrology measurement signal, each overlay estimate determined utilizing one of the overlay algorithms; generating a plurality of overlay estimate distributions by generating an overlay estimate distribution for each of the plurality of overlay metrology measurement signals from the plurality of metrology targets utilizing the plurality of overlay estimates; and generating a first plurality of quality metrics utilizing the generated plurality of overlay estimate distributions, wherein each quality metric corresponds with one overlay estimate distribution of the generated plurality of overlay estimate distributions, each quality metric a function of a width of a corresponding generated overlay estimate distribution, each quality metric further being a function of asymmetry present in an overlay metrology measurement signal from an associated metrology target. 2. The method of claim 1, wherein acquiring a plurality of overlay metrology measurement signals from a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers comprises:
performing an overlay metrology measurement on a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers. 3. The method of claim 1, further comprising:
performing a tool induced shift (TIS) correction process to at least some of the acquired plurality of overlay metrology measurement signals. 4. The method of claim 1, wherein each of the plurality of generated quality metrics is configured to identify an overlay deviation from a metrology target having substantially symmetric target structures. 5. The method of claim 1, further comprising:
identifying one or more metrology targets of the plurality of metrology targets having a quality metric larger than a selected outlier level along at least one direction from a distribution of the plurality of quality metrics generated for the plurality of metrology targets; determining a corrected plurality of metrology targets, wherein the corrected plurality of metrology targets excludes the identified one or more metrology targets having a quality metric deviating beyond a selected outlier level from the plurality of metrology targets; and calculating a set of correctables utilizing the determined corrected plurality of metrology targets. 6. The method of claim 1, further comprising:
transmitting the set of correctables to one or more process tools. 7. The method of claim 1, further comprising:
acquiring at least an additional plurality of overlay metrology measurement signals from the plurality of metrology targets distributed across the one or more fields of the wafer of the lot of wafers, each overlay metrology measurement signal of the at least an additional plurality of overlay metrology measurement signals corresponding with a metrology target of the plurality of metrology targets, the at least an additional plurality of overlay metrology measurement signals acquired utilizing at least an additional measurement recipe; determining at least an additional plurality of overlay estimates for each of the at least an additional plurality of overlay measurement signals by applying the plurality of overlay algorithms to each overlay measurement signal of the at least an additional plurality of measurement signals, each of the at least an additional plurality of overlay estimates determined utilizing one of the overlay algorithms; generating at least an additional plurality of overlay estimate distributions by generating an overlay estimate distribution for each of the at least an additional plurality of overlay measurement signals from the plurality of metrology targets utilizing the plurality of overlay estimates; and generating at least an additional plurality of quality metrics utilizing the generated at least an additional plurality of overlay estimate distributions, wherein each quality metric of the at least an additional plurality of quality metrics corresponds with one overlay estimate distribution of the generated at least an additional plurality of overlay estimate distributions, each quality metric of the at least an additional plurality of quality metrics a function of a width of a corresponding generated overlay estimate distribution of the at least an additional plurality of overlay estimate distributions; determining a process measurement recipe by comparing a distribution of the first plurality of quality metrics associated with the first measurement recipe to a distribution of the at least an additional plurality of quality metrics associated with the at least one additional measurement recipe. 8. The method of claim 7, wherein the determining a process measurement recipe by comparing a distribution of the first plurality of quality metrics associated with the first measurement recipe to a distribution of the at least an additional plurality of quality metrics associated with the at least one additional measurement recipe comprises:
determining an optimum measurement recipe by comparing a distribution of the first plurality of quality metrics associated with the first measurement recipe to a distribution of the at least an additional plurality of quality metrics associated with the at least one additional measurement recipe, the optimum measurement recipe associated with a plurality of quality metrics of the first plurality of metrics and the at least an additional plurality of metrics having a substantially minimum distribution in at least one direction. 9. The method of claim 7, wherein at least one of the first measurement recipe or the at least an additional measurement recipe comprise:
at least one of a wavelength of illumination, a filter configuration, a direction of illumination, a focus position, or polarization configuration. 10. A computer-implemented method for determining a quality metric suitable for improving process control in a semiconductor wafer fabrication process:
acquiring a metrology measurement signal from one or more metrology targets of one or more fields of a wafer of a lot of wafers; determining a plurality of overlay estimates by applying a plurality of overlay algorithms to the acquired metrology measurement signal, each overlay estimate determined utilizing one of the overlay algorithms; generating an overlay estimate distribution utilizing the plurality of overlay estimates; and generating a quality metric for the one or more metrology targets utilizing the generated overlay estimate distribution, the quality metric a function of a width of the generated overlay estimate distribution, the quality metric configured to be non-zero for asymmetric overlay measurement signals, the quality metric a function of a width of the generated overlay estimate distribution, the quality metric further being a function of asymmetry present in the metrology measurement signal acquired from an associated metrology target. 11. A computer-implemented method for providing a set of process tool correctables, comprising:
acquiring an overlay metrology result for each metrology target of a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers; acquiring a quality metric associated with each acquired overlay metrology result; determining a plurality of modified overlay values for the plurality of metrology targets utilizing the acquired overlay metrology result and the associated quality metric result for each metrology target, wherein the modified overlay function is a function of at least one material parameter factor; generating a process tool correctable function and a set of residuals corresponding with the process tool correctable function for a plurality of material parameter factors; determining a value of the material parameter factor suitable for at least substantially minimizing the set of residuals; and determining a set of process correctables associated with the at least substantially minimized set of residuals. 12. The method of claim 11, wherein the acquiring a quality metric associated with each acquired overlay metrology result, comprises:
generating a quality metric for each acquired overlay metrology result utilizing a quality metric generation process. 13. The method of claim 11, wherein the acquiring an overlay metrology result for each metrology target of a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers, comprises:
performing an overlay measurement on each metrology target of a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers. 14. The method of claim 11, further comprising:
transmitting the set of process tool correctables associated with the at least substantially minimized set of residuals to one or more process tools. 15. The method of claim 11, further comprising:
performing a tool induced shift (TIS) correction process to at least some of the acquired plurality of overlay metrology measurement signals. 16. The method of claim 11, wherein the modified overlay function is a linear function of at least one material parameter factor. 17. The method of claim 11, wherein the modified overlay function is a function of at least one of a wavelength of illumination, a focus position, a direction of illumination, a polarization configuration, or a filter configuration. 18. A computer-implemented method for identifying a variation in process tool correctables, comprising:
acquiring an overlay metrology result for each metrology target of a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers; acquiring a quality metric associated with each acquired overlay metrology result; determining a plurality of modified overlay values for the plurality of metrology targets utilizing the acquired overlay metrology result for each metrology target and a quality function, the quality function being a function of the acquired quality metric of each metrology target; generating a plurality of sets of process tool correctables by determining a set of process tool correctables for each of a plurality of randomly selected samplings of the acquired overlay metrology results and the associated quality metrics of the plurality of metrology targets utilizing the plurality of modified overlay values, wherein each of the random samplings is of the same size; and identifying a variation in the plurality of sets of process tool correctables. 19. The method of claim 18, wherein the acquiring a quality metric associated with each acquired overlay metrology result, comprises:
generating a quality metric for each acquired overlay metrology result utilizing a quality metric generation process. 20. The method of claim 18, wherein the acquiring an overlay metrology result for each metrology target of a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers, comprises:
performing an overlay measurement on each metrology target of a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers. 21. A computer-implemented method for generating a metrology sampling plan, comprising:
acquiring a plurality of overlay metrology measurement signals from a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers, each overlay metrology measurement signal corresponding with a metrology target of the plurality of metrology targets; determining a plurality of overlay estimates for each of the plurality of overlay metrology measurement signals by applying a plurality of overlay algorithms to each overlay metrology measurement signal, each overlay estimate determined utilizing one of the overlay algorithms; generating a plurality of overlay estimate distributions by generating an overlay estimate distribution for each of the plurality of overlay metrology measurement signals from the plurality of metrology targets utilizing the plurality of overlay estimates; generating a first plurality of quality metrics utilizing the generated plurality of overlay estimate distributions, wherein each quality metric corresponds with one overlay estimate distribution of the generated plurality of overlay estimate distributions, each quality metric further being a function of asymmetry present in an overlay metrology measurement signal from an associated metrology target; and generating one or more metrology sampling plans utilizing the generated first plurality of quality metrics of the plurality of metrology targets. 22. The method of claim 21, wherein the generating one or more metrology sampling plans utilizing the generated first plurality of quality metrics of the plurality of metrology targets, comprises:
generating one or more metrology sampling plans utilizing the generated first plurality of quality metrics of the plurality of metrology targets to identify one or more low quality targets, wherein the one or more low quality targets are excluded from the generated one or more metrology sampling plan. 23. The method of claim 21, wherein the generating one or more metrology sampling plans utilizing the generated first plurality of quality metrics of the plurality of metrology targets, comprises:
generating one or more metrology sampling plans utilizing the generated first plurality of quality metrics of the plurality of metrology targets to identify one or more low quality targets of the wafer, wherein the one or more low quality targets are excluded from the generated one or more metrology sampling plans and one or more additional metrology targets located proximate to the one or more low quality targets are utilized to replace the one or more low quality targets. 24. The method of claim 21, further comprising:
identifying a plurality of quality zones of the wafer utilizing the first plurality of quality metrics, each of the quality zones including a plurality of metrology targets having substantially similar quality levels. 25. The method of claim 24, wherein a metrology sampling rate at one or more locations across the wafer is defined by each of the plurality of quality zones. 26. The method of claim 21, further comprising:
performing one or more metrology measurements on a subsequent wafer utilizing the generated sampling plan. 27. A computer-implemented method for providing process signature mapping, comprising:
forming a plurality of proxy targets on a reticle; forming a plurality of device correlation targets on a wafer; determining a first process signature as a function of position across the wafer by comparing a first set of metrology results acquired from the plurality of proxy targets following a lithography process and prior to a first etching process of the wafer and at least a second set of metrology results acquired from the plurality of proxy targets following the first etching process of the wafer; correlating the first process signature with a specific process path; measuring a device correlation bias following the first etching process by performing a first set of metrology measurements on the plurality of device correlation targets of the wafer, the device correlation bias being the bias between a metrology structure and a device of the wafer; determining an additional etch signature for each additional process layer and for each additional non-lithographic process path of the wafer as a function of position across the wafer; measuring an additional device correlation bias following each additional process layer and each additional non-lithographic process path of the wafer; and generating a process signature map database utilizing the determined first etch signature and each of the additional etch signatures and the first measured device correlation bias and each additional device correlation bias. 28. The method of claim 27, wherein the comparing a first set of metrology results acquired from the plurality of proxy targets following a lithography process and prior to a first etching process of the wafer and at least a second set of metrology results acquired from the plurality of proxy targets following the first etching process of the wafer comprises:
determining a difference between a first set of metrology results acquired from the plurality of proxy targets following a lithography process and prior to a first etching process of the wafer and at least a second set of metrology results acquired from the plurality of proxy targets following the first etching process of the wafer. 29. The method of claim 27, wherein the first set of metrology results from the plurality of proxy targets are acquired following a lithography process by performing a first set of metrology measurements on the plurality of proxy targets following a lithography process. 30. The method of claim 27, wherein the at least a second set of metrology results from the plurality of proxy targets are acquired following the first etching process of the wafer by performing at least a second set of metrology measurements on the plurality of proxy targets following the first etching process of the wafer. 31. The method of claim 27, wherein at least one of the first set of metrology results from the plurality of proxy targets or the at least a second set of metrology results from the plurality of proxy targets are acquired utilizing one or more overlay metrology processes. 32. The method of claim 27, wherein the measuring a device correlation bias following the first etching process by performing a first set of metrology measurements on the plurality of device correlation targets of the wafer comprises:
measuring a device correlation bias following the first etching process by performing a first set metrology measurements on the plurality of device correlation targets of the wafer, the first set of metrology measurements performed utilizing at least one of a CD-SEM based metrology system or an AFM-based metrology system. 33. The method of claim 27, wherein the reticle is at least one of a test reticle or a product reticle. 34. The method of claim 27, further comprising:
operating an advance process control loop utilizing the generated process signature map database. 35. The method of claim 27, further comprising:
generating a set of process signature mapping correctables. 36. A system for providing a quality metric suitable for improving process control in a semiconductor wafer fabrication, comprising process:
a metrology system configured to acquire a plurality of overlay metrology measurement signals from a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers, each overlay metrology measurement signal corresponding with a metrology target of the plurality of metrology targets, the plurality of overlay metrology measurement signals acquired utilizing a first measurement recipe; and a computing system configured to:
determine a plurality of overlay estimates for each of the plurality of overlay metrology measurement signals by applying a plurality of overlay algorithms to each overlay metrology measurement signal, each overlay estimate determined utilizing one of the overlay algorithms;
generate a plurality of overlay estimate distributions by generating an overlay estimate distribution for each of the plurality of overlay metrology measurement signals from the plurality of metrology targets utilizing the plurality of overlay estimates; and
generate a first plurality of quality metrics utilizing the generated plurality of overlay estimate distributions, wherein each quality metric corresponds with one overlay estimate distribution of the generated plurality of overlay estimate distributions, each quality metric a function of a width of a corresponding generated overlay estimate distribution, each quality metric further being a function of asymmetry present in an overlay metrology measurement signal from an associated metrology target. 37. The system of claim 36, wherein the computing system is further configured to identify one or more outlier metrology targets utilizing the generated first plurality of quality metrics. 38. The system of claim 36, wherein the computing system is further configured to determine an optimum overlay measurement recipe utilizing the generated first plurality of quality metrics. 39. The system of claim 36, wherein the computing system is further configured to generate one or more process tool correctables utilizing the generated first plurality of quality metrics. 40. The system of claim 36, wherein the computing system is further configured to generate one or more sampling plans utilizing the generated first plurality of quality metrics. 41. The system of claim 36, wherein the computing system is further configured to generate a process signature mapping database. | 2,800 |
12,106 | 12,106 | 16,313,419 | 2,847 | A cable sealing device for an electrical junction box includes a centering frame mountable at a hole in a wall of the junction box, a first clamping plate having a plurality of cable passage holes, the first clamping plate being disposed on a first side of the centering frame within the first seat, a second clamping plate having an equal plurality of cable passage holes, the second clamping plate being disposed on a second side of the centering frame opposite the first side wherein the cable passage holes of the first clamping plate are aligned with the cable passage holes of the second clamping plate to define a plurality of cable passages and, a sealing membrane disposed between the first clamping plate and the flange of the centering frame, wherein portions of the sealing membrane are exposed at the plurality of cable passages and wherein at least one exposed membrane portion has a perforation to accept a cable. | 1. A cable sealing device for an electrical junction box, comprising:
a centering frame mountable at a hole in a wall of the junction box, the centering frame including a first rim and a flange defining a first seat, an edge of the flange defining a central opening; a first clamping plate having a plurality of cable passage holes, the first clamping plate being disposed on a first side of the centering frame within the first seat; a second clamping plate having an equal plurality of cable passage holes, the second clamping plate being disposed on a second side of the centering frame opposite the first side wherein the cable passage holes of the first clamping plate are aligned with the cable passage holes of the second clamping plate to define a plurality of cable passages; and, a sealing membrane disposed between the first clamping plate and the flange of the centering frame, wherein portions of the sealing membrane are exposed at the plurality of cable passages and wherein at least one exposed membrane portion has a perforation to accept a cable. 2. The cable sealing device of claim 1, wherein the first clamping plate has a fastening post extending from a surface thereof, the first clamping plate being disposed on a first side of the centering frame within the first seat with the fastening post extending through the central opening. 3. The cable sealing device of claim 2, wherein the second clamping plate has an aperture to receive the fastening post. 4. The cable sealing device of claim 3, wherein the fastening post is threaded and wherein the device comprises a threaded nut engaged on a portion of the fastening post extending from the second clamping plate, the post and nut applying clamping force to the first clamping plate and second clamping plate. 5. The cable sealing device of claim 2, wherein the sealing membrane has an aperture to receive the fastening post. 6. The cable sealing device of claim 2, wherein the fastening post is molded into the first clamping plate. 7. The cable sealing device of claim 2, wherein the fastening post is carried in a post hole formed in the first clamping plate. 8. The cable sealing device of claim 1, wherein the centering frame comprises a second rim opposite the first rim, the flange being disposed between the first rim and the second rim, the second rim defining a second seat. 9. The cable sealing device of claim 8, wherein the second clamping plate is disposed in the second seat. 10. The cable sealing device of claim 1, wherein the first clamping plate comprises a cable support cradle at each of the cable passage holes. 11. The cable sealing device of claim 1, wherein the second clamping plate comprises a cable support cradle at each of the cable passage holes. 12. The cable sealing device of claim 1, wherein the perforation in the membrane is configured for a press fit with a cable for that cable passage to provide a water-tight seal. 13. The cable sealing device of claim 1, wherein the first clamping plate and the second clamping plate are disc shaped and comprising a fastening post extending from the first clamping plate through an aperture in the second clamping plate, wherein the fastening post and aperture are centrally located. 14. The cable sealing device of claim 1, wherein the first clamping plate and the second clamping plate are triangular, and comprising a fastening post extending from the first clamping plate through an aperture in the second clamping plate, wherein the fastening post and the aperture are centrally located. 15. The cable sealing device off claim 1, wherein the first clamping plate and the second clamping plate are rectangular, and comprising a first fastening post and a second fastening post extending from the first clamping plate through a respective first aperture and second aperture in the second clamping plate, the first fastening post and the second fastening post being located at a central portion of the first clamping plate, and the first aperture and the second aperture being located at a central portion of the second clamping plate. 16. An electrical junction box for a vehicle, comprising:
a box having walls defining an enclosed interior space and a door allowing access to the interior space, one of said walls having a hole; a centering frame mounted at the hole in the wall, the centering frame including a first rim extending perpendicular to an exterior surface of the wall, a flange extending parallel to the wall within the first rim and defining a central opening, and a second rim extending perpendicular to an interior surface of the wall; a first clamping plate having a plurality of cable passage holes and having a post extending from a surface thereof, the first clamping plate being disposed on a first side of the centering frame within the rim and with the post extending through the central opening; a second clamping plate having an equal plurality of cable passage holes and a centrally-located aperture to receive the post, the second clamping plate being disposed on a second side of the centering frame opposite the first side with the post received in the aperture and wherein the cable passage holes of the first clamping plate are aligned with the cable passage holes of the second clamping plate to define a plurality of cable passages; and, a sealing membrane disposed between the first clamping plate and the flange of the centering ring, wherein the sealing membrane has a centrally-located aperture to receive the post, wherein portions of the sealing membrane are exposed at the plurality of cable passages and wherein at least one exposed membrane portion has a perforation to accept a cable. | A cable sealing device for an electrical junction box includes a centering frame mountable at a hole in a wall of the junction box, a first clamping plate having a plurality of cable passage holes, the first clamping plate being disposed on a first side of the centering frame within the first seat, a second clamping plate having an equal plurality of cable passage holes, the second clamping plate being disposed on a second side of the centering frame opposite the first side wherein the cable passage holes of the first clamping plate are aligned with the cable passage holes of the second clamping plate to define a plurality of cable passages and, a sealing membrane disposed between the first clamping plate and the flange of the centering frame, wherein portions of the sealing membrane are exposed at the plurality of cable passages and wherein at least one exposed membrane portion has a perforation to accept a cable.1. A cable sealing device for an electrical junction box, comprising:
a centering frame mountable at a hole in a wall of the junction box, the centering frame including a first rim and a flange defining a first seat, an edge of the flange defining a central opening; a first clamping plate having a plurality of cable passage holes, the first clamping plate being disposed on a first side of the centering frame within the first seat; a second clamping plate having an equal plurality of cable passage holes, the second clamping plate being disposed on a second side of the centering frame opposite the first side wherein the cable passage holes of the first clamping plate are aligned with the cable passage holes of the second clamping plate to define a plurality of cable passages; and, a sealing membrane disposed between the first clamping plate and the flange of the centering frame, wherein portions of the sealing membrane are exposed at the plurality of cable passages and wherein at least one exposed membrane portion has a perforation to accept a cable. 2. The cable sealing device of claim 1, wherein the first clamping plate has a fastening post extending from a surface thereof, the first clamping plate being disposed on a first side of the centering frame within the first seat with the fastening post extending through the central opening. 3. The cable sealing device of claim 2, wherein the second clamping plate has an aperture to receive the fastening post. 4. The cable sealing device of claim 3, wherein the fastening post is threaded and wherein the device comprises a threaded nut engaged on a portion of the fastening post extending from the second clamping plate, the post and nut applying clamping force to the first clamping plate and second clamping plate. 5. The cable sealing device of claim 2, wherein the sealing membrane has an aperture to receive the fastening post. 6. The cable sealing device of claim 2, wherein the fastening post is molded into the first clamping plate. 7. The cable sealing device of claim 2, wherein the fastening post is carried in a post hole formed in the first clamping plate. 8. The cable sealing device of claim 1, wherein the centering frame comprises a second rim opposite the first rim, the flange being disposed between the first rim and the second rim, the second rim defining a second seat. 9. The cable sealing device of claim 8, wherein the second clamping plate is disposed in the second seat. 10. The cable sealing device of claim 1, wherein the first clamping plate comprises a cable support cradle at each of the cable passage holes. 11. The cable sealing device of claim 1, wherein the second clamping plate comprises a cable support cradle at each of the cable passage holes. 12. The cable sealing device of claim 1, wherein the perforation in the membrane is configured for a press fit with a cable for that cable passage to provide a water-tight seal. 13. The cable sealing device of claim 1, wherein the first clamping plate and the second clamping plate are disc shaped and comprising a fastening post extending from the first clamping plate through an aperture in the second clamping plate, wherein the fastening post and aperture are centrally located. 14. The cable sealing device of claim 1, wherein the first clamping plate and the second clamping plate are triangular, and comprising a fastening post extending from the first clamping plate through an aperture in the second clamping plate, wherein the fastening post and the aperture are centrally located. 15. The cable sealing device off claim 1, wherein the first clamping plate and the second clamping plate are rectangular, and comprising a first fastening post and a second fastening post extending from the first clamping plate through a respective first aperture and second aperture in the second clamping plate, the first fastening post and the second fastening post being located at a central portion of the first clamping plate, and the first aperture and the second aperture being located at a central portion of the second clamping plate. 16. An electrical junction box for a vehicle, comprising:
a box having walls defining an enclosed interior space and a door allowing access to the interior space, one of said walls having a hole; a centering frame mounted at the hole in the wall, the centering frame including a first rim extending perpendicular to an exterior surface of the wall, a flange extending parallel to the wall within the first rim and defining a central opening, and a second rim extending perpendicular to an interior surface of the wall; a first clamping plate having a plurality of cable passage holes and having a post extending from a surface thereof, the first clamping plate being disposed on a first side of the centering frame within the rim and with the post extending through the central opening; a second clamping plate having an equal plurality of cable passage holes and a centrally-located aperture to receive the post, the second clamping plate being disposed on a second side of the centering frame opposite the first side with the post received in the aperture and wherein the cable passage holes of the first clamping plate are aligned with the cable passage holes of the second clamping plate to define a plurality of cable passages; and, a sealing membrane disposed between the first clamping plate and the flange of the centering ring, wherein the sealing membrane has a centrally-located aperture to receive the post, wherein portions of the sealing membrane are exposed at the plurality of cable passages and wherein at least one exposed membrane portion has a perforation to accept a cable. | 2,800 |
12,107 | 12,107 | 15,771,183 | 2,844 | This illumination device (4) is configured so as to display, outside a vehicle (1) capable of traveling in an automatic driving mode, information related to the automatic driving of the vehicle (1), and is provided with an illumination unit (42) which is configured so as to shine light outside the vehicle (1) and around the entire periphery of the vehicle (1) in the horizontal direction. | 1. A vehicle illumination device configured to display information relating to automatic driving of a vehicle toward an outside of the vehicle capable of travelling in an automatic driving mode, the vehicle illumination device comprising:
an illumination unit configured to irradiate light toward the outside of the vehicle and over an entire circumference of the vehicle in a horizontal direction. 2. The vehicle illumination device according to claim 1, further comprising:
an illumination control unit configured to set an illumination state of the illumination unit to a predetermined illumination state in accordance with the information relating to the automatic driving of the vehicle. 3. The vehicle illumination device according to claim 2,
wherein the illumination control unit is configured to turn on or turn off the illumination unit in accordance with the information relating to the automatic driving of the vehicle. 4. The vehicle illumination device according to claim 1, further comprising:
an illumination control unit configured to set an illumination state of the illumination unit to a predetermined illumination state in accordance with illuminance of surrounding environment of the vehicle. 5. The vehicle illumination device according to claim 1,
wherein the information relating to the automatic driving of the vehicle includes information indicating a transition state of a driving mode of the vehicle. 6. The vehicle illumination device according to claim 1,
wherein the illumination unit is disposed on a vehicle body roof of the vehicle. 7. The vehicle illumination device according to claim 1, wherein the illumination unit is disposed on a vehicle body side surface of the vehicle. 8. The vehicle illumination device according to claim 7,
wherein the illumination unit includes: a first illumination part disposed on a left surface of the vehicle; a second illumination part disposed on a right surface of the vehicle; a third illumination part disposed on a front surface of the vehicle; and a fourth illumination part disposed on a rear surface of the vehicle. 9. The vehicle illumination device according to claim 7,
wherein the illumination unit is arranged to surround the vehicle body side surface. 10. The vehicle illumination device according to claim 7,
wherein the illumination unit includes a plurality of illumination parts, and wherein each of the plurality of illumination parts is disposed at a corresponding one of four corners of the vehicle body side surface. 11. The vehicle illumination device according to claim 1,
wherein the illumination unit is disposed on a bottom surface of the vehicle facing a road surface, and wherein the illumination unit is configured to irradiate light over the entire circumference in the horizontal direction via the road surface. 12. A vehicle capable of travelling in an automatic driving mode comprising the vehicle illumination device according to claim 1. | This illumination device (4) is configured so as to display, outside a vehicle (1) capable of traveling in an automatic driving mode, information related to the automatic driving of the vehicle (1), and is provided with an illumination unit (42) which is configured so as to shine light outside the vehicle (1) and around the entire periphery of the vehicle (1) in the horizontal direction.1. A vehicle illumination device configured to display information relating to automatic driving of a vehicle toward an outside of the vehicle capable of travelling in an automatic driving mode, the vehicle illumination device comprising:
an illumination unit configured to irradiate light toward the outside of the vehicle and over an entire circumference of the vehicle in a horizontal direction. 2. The vehicle illumination device according to claim 1, further comprising:
an illumination control unit configured to set an illumination state of the illumination unit to a predetermined illumination state in accordance with the information relating to the automatic driving of the vehicle. 3. The vehicle illumination device according to claim 2,
wherein the illumination control unit is configured to turn on or turn off the illumination unit in accordance with the information relating to the automatic driving of the vehicle. 4. The vehicle illumination device according to claim 1, further comprising:
an illumination control unit configured to set an illumination state of the illumination unit to a predetermined illumination state in accordance with illuminance of surrounding environment of the vehicle. 5. The vehicle illumination device according to claim 1,
wherein the information relating to the automatic driving of the vehicle includes information indicating a transition state of a driving mode of the vehicle. 6. The vehicle illumination device according to claim 1,
wherein the illumination unit is disposed on a vehicle body roof of the vehicle. 7. The vehicle illumination device according to claim 1, wherein the illumination unit is disposed on a vehicle body side surface of the vehicle. 8. The vehicle illumination device according to claim 7,
wherein the illumination unit includes: a first illumination part disposed on a left surface of the vehicle; a second illumination part disposed on a right surface of the vehicle; a third illumination part disposed on a front surface of the vehicle; and a fourth illumination part disposed on a rear surface of the vehicle. 9. The vehicle illumination device according to claim 7,
wherein the illumination unit is arranged to surround the vehicle body side surface. 10. The vehicle illumination device according to claim 7,
wherein the illumination unit includes a plurality of illumination parts, and wherein each of the plurality of illumination parts is disposed at a corresponding one of four corners of the vehicle body side surface. 11. The vehicle illumination device according to claim 1,
wherein the illumination unit is disposed on a bottom surface of the vehicle facing a road surface, and wherein the illumination unit is configured to irradiate light over the entire circumference in the horizontal direction via the road surface. 12. A vehicle capable of travelling in an automatic driving mode comprising the vehicle illumination device according to claim 1. | 2,800 |
12,108 | 12,108 | 15,094,316 | 2,836 | An embodiment electronic circuit includes an electronic switch comprising a load path, and a control circuit configured to drive the electronic switch. The control circuit is configured to operate in one of at least two operation modes. The at least two operation modes comprise a first operation mode and a second operation mode. The control circuit, in the second operation mode, is configured to perform a set of basic functions and, in the first operation mode, is configured to perform the set of basic functions and at least one additional function. The at least one additional function comprises generating a first protection signal based on a current-time-characteristic of a load current of the electronic switch and driving the electronic switch based on the first protection signal. | 1. An electronic circuit, comprising:
an electronic switch comprising a load path; and a control circuit configured to drive the electronic switch, wherein the control circuit is configured to operate in one of at least two operation modes, wherein the at least two operation modes comprise a first operation mode and a second operation mode, wherein the control circuit, in the second operation mode, is configured to perform a set of basic functions and, in the first operation mode, is configured to perform the set of basic functions and at least one additional function, and wherein the at least one additional function comprises generating a first protection signal based on a current-time-characteristic of a load current of the electronic switch and driving the electronic switch based on the first protection signal. 2. The electronic circuit of claim 1,
wherein the control circuit is configured to drive the electronic switch based on an input signal in the first operation mode and the second operation mode. 3. The electronic circuit of claim 1,
wherein the control circuit is configured to drive the electronic switch based on a supply voltage received by the control circuit in the first operation mode and the second operation mode, wherein the supply voltage is configured to power the control circuit. 4. The electronic circuit of claim 1, wherein the set of basic functions comprises:
monitoring the load current and switching off the electronic switch when the load current reaches a predefined overcurrent threshold. 5. The electronic circuit of claim 1, wherein the set of basic functions comprises:
monitoring a temperature of the electronic switch and switching off the electronic switch when the temperature reaches a predefined overtemperature threshold. 6. The electronic circuit of claim 4,
wherein the at least two operation modes further comprise a third operation mode, wherein in the third operation mode the control circuit is configured to monitor the load current and regulate the load current when the load current reaches the overcurrent threshold. 7. The electronic circuit of claim 6, wherein the control circuit being configured to regulate the load current comprises the control circuit being configured to regulate the load current to have a target level that substantially equals the overcurrent threshold. 8. The electronic circuit of claim 1,
wherein the control circuit comprises a first protection circuit configured to generate the first protection signal and comprising: an analog-to-digital converter (ADC) configured to receive an ADC input signal representing the load current and to output an ADC output signal, a filter configured to filter the ADC output signal and output a filter output signal, and a comparator circuit configured to generate the first protection signal based on comparing the filter output signal with a predefined threshold. 9. The electronic circuit of claim 8, further comprising:
a further input configured to receive a signal representing the predefined threshold. 10. The electronic circuit of claim 1,
wherein the control circuit further comprises a status output, and wherein the control circuit is further configured to generate a wakeup pulse at the status output when operation changes from the second operation mode to the first operation mode. 11. The electronic circuit of claim 1, wherein the control circuit is configured to enter the second operation mode based on the load current and at least one other parameter. 12. The electronic circuit of claim 11, wherein the at least one other parameter is selected from the group consisting of:
a filter output signal in a filter of a first protection circuit configured to generate the first protection signal; a temperature difference between a temperature in the electronic switch and a temperature in the control circuit; an ambient temperature of the electronic circuit; and an on-resistance of the electronic switch. 13. A method, comprising:
operating a control circuit configured to drive an electronic switch in one of at least two operation modes, wherein the at least two operation modes comprise a first operation mode and a second operation mode, wherein operating in the second operation mode comprises performing a set of basic functions by the control circuit and operating in the first operation mode comprises performing the set of basic functions and at least one additional function by the control circuit, wherein the at least one additional function comprises generating a first protection signal based on a current-time-characteristic of a load current of the electronic switch and driving the electronic switch based on the first protection signal. 14. The method of claim 13, wherein operating in the first operation mode and the second operation mode comprises driving the electronic switch based on an input signal by the control circuit. 15. The method of claim 13, wherein operating in the first operation mode and the second operation mode comprises driving the electronic switch based on a supply voltage received by the control circuit,
wherein the supply voltage is configured to power the control circuit. 16. The method of claim 13, wherein the set of basic functions comprises:
monitoring the load current and switching off the electronic switch when the load current reaches a predefined overcurrent threshold. 17. The method of claim 13, wherein the set of basic functions comprises:
monitoring a temperature of the electronic switch and switching off the electronic switch when the temperature reaches a predefined overtemperature threshold. 18. The method of claim 16,
wherein the at least two operation modes further comprise a third operation mode, wherein operating in the third operation mode comprises monitoring the load current and regulating the load current when the load current reaches the overcurrent threshold by the control circuit. 19. The method of claim 18, wherein regulating the load current comprises regulating the load current to have a target level that substantially equals the overcurrent threshold. 20. The method of claim 13, further comprising:
generating a wakeup pulse at a status output by the control circuit when operation changes from the second operation mode to the first operation mode. 21. The method of claim 13, further comprising:
entering the second operation mode by the control circuit based on the load current and at least one other parameter. 22. The method of claim 21, wherein the at least one other parameter is selected from the group consisting of:
a filter output signal in a filter of a first protection circuit configured to generate the first protection signal; a temperature difference between a temperature in the electronic switch and a temperature in the control circuit; an ambient temperature of the control circuit; and an on-resistance of the electronic switch. | An embodiment electronic circuit includes an electronic switch comprising a load path, and a control circuit configured to drive the electronic switch. The control circuit is configured to operate in one of at least two operation modes. The at least two operation modes comprise a first operation mode and a second operation mode. The control circuit, in the second operation mode, is configured to perform a set of basic functions and, in the first operation mode, is configured to perform the set of basic functions and at least one additional function. The at least one additional function comprises generating a first protection signal based on a current-time-characteristic of a load current of the electronic switch and driving the electronic switch based on the first protection signal.1. An electronic circuit, comprising:
an electronic switch comprising a load path; and a control circuit configured to drive the electronic switch, wherein the control circuit is configured to operate in one of at least two operation modes, wherein the at least two operation modes comprise a first operation mode and a second operation mode, wherein the control circuit, in the second operation mode, is configured to perform a set of basic functions and, in the first operation mode, is configured to perform the set of basic functions and at least one additional function, and wherein the at least one additional function comprises generating a first protection signal based on a current-time-characteristic of a load current of the electronic switch and driving the electronic switch based on the first protection signal. 2. The electronic circuit of claim 1,
wherein the control circuit is configured to drive the electronic switch based on an input signal in the first operation mode and the second operation mode. 3. The electronic circuit of claim 1,
wherein the control circuit is configured to drive the electronic switch based on a supply voltage received by the control circuit in the first operation mode and the second operation mode, wherein the supply voltage is configured to power the control circuit. 4. The electronic circuit of claim 1, wherein the set of basic functions comprises:
monitoring the load current and switching off the electronic switch when the load current reaches a predefined overcurrent threshold. 5. The electronic circuit of claim 1, wherein the set of basic functions comprises:
monitoring a temperature of the electronic switch and switching off the electronic switch when the temperature reaches a predefined overtemperature threshold. 6. The electronic circuit of claim 4,
wherein the at least two operation modes further comprise a third operation mode, wherein in the third operation mode the control circuit is configured to monitor the load current and regulate the load current when the load current reaches the overcurrent threshold. 7. The electronic circuit of claim 6, wherein the control circuit being configured to regulate the load current comprises the control circuit being configured to regulate the load current to have a target level that substantially equals the overcurrent threshold. 8. The electronic circuit of claim 1,
wherein the control circuit comprises a first protection circuit configured to generate the first protection signal and comprising: an analog-to-digital converter (ADC) configured to receive an ADC input signal representing the load current and to output an ADC output signal, a filter configured to filter the ADC output signal and output a filter output signal, and a comparator circuit configured to generate the first protection signal based on comparing the filter output signal with a predefined threshold. 9. The electronic circuit of claim 8, further comprising:
a further input configured to receive a signal representing the predefined threshold. 10. The electronic circuit of claim 1,
wherein the control circuit further comprises a status output, and wherein the control circuit is further configured to generate a wakeup pulse at the status output when operation changes from the second operation mode to the first operation mode. 11. The electronic circuit of claim 1, wherein the control circuit is configured to enter the second operation mode based on the load current and at least one other parameter. 12. The electronic circuit of claim 11, wherein the at least one other parameter is selected from the group consisting of:
a filter output signal in a filter of a first protection circuit configured to generate the first protection signal; a temperature difference between a temperature in the electronic switch and a temperature in the control circuit; an ambient temperature of the electronic circuit; and an on-resistance of the electronic switch. 13. A method, comprising:
operating a control circuit configured to drive an electronic switch in one of at least two operation modes, wherein the at least two operation modes comprise a first operation mode and a second operation mode, wherein operating in the second operation mode comprises performing a set of basic functions by the control circuit and operating in the first operation mode comprises performing the set of basic functions and at least one additional function by the control circuit, wherein the at least one additional function comprises generating a first protection signal based on a current-time-characteristic of a load current of the electronic switch and driving the electronic switch based on the first protection signal. 14. The method of claim 13, wherein operating in the first operation mode and the second operation mode comprises driving the electronic switch based on an input signal by the control circuit. 15. The method of claim 13, wherein operating in the first operation mode and the second operation mode comprises driving the electronic switch based on a supply voltage received by the control circuit,
wherein the supply voltage is configured to power the control circuit. 16. The method of claim 13, wherein the set of basic functions comprises:
monitoring the load current and switching off the electronic switch when the load current reaches a predefined overcurrent threshold. 17. The method of claim 13, wherein the set of basic functions comprises:
monitoring a temperature of the electronic switch and switching off the electronic switch when the temperature reaches a predefined overtemperature threshold. 18. The method of claim 16,
wherein the at least two operation modes further comprise a third operation mode, wherein operating in the third operation mode comprises monitoring the load current and regulating the load current when the load current reaches the overcurrent threshold by the control circuit. 19. The method of claim 18, wherein regulating the load current comprises regulating the load current to have a target level that substantially equals the overcurrent threshold. 20. The method of claim 13, further comprising:
generating a wakeup pulse at a status output by the control circuit when operation changes from the second operation mode to the first operation mode. 21. The method of claim 13, further comprising:
entering the second operation mode by the control circuit based on the load current and at least one other parameter. 22. The method of claim 21, wherein the at least one other parameter is selected from the group consisting of:
a filter output signal in a filter of a first protection circuit configured to generate the first protection signal; a temperature difference between a temperature in the electronic switch and a temperature in the control circuit; an ambient temperature of the control circuit; and an on-resistance of the electronic switch. | 2,800 |
12,109 | 12,109 | 15,360,498 | 2,811 | Provided is a method for manufacturing a thin SiC wafer by which a SiC wafer is thinned using a method without generating crack or the like, the method in which polishing after adjusting the thickness of the SiC wafer can be omitted. The method for manufacturing the thin SiC wafer 40 includes a thinning step. In the thinning step, the thickness of the SiC wafer 40 can be decreased to 100 μm or less by performing the Si vapor pressure etching in which the surface of the SiC wafer 40 is etched by heating the SiC wafer 40 after cutting out of an ingot 4 under Si vapor pressure. | 1. A method for manufacturing a thin SiC wafer by processing a SiC wafer after cutting out of an ingot comprising:
a thinning step for thinning a thickness of the SiC wafer after cutting out of the ingot; wherein in the thinning step, performing a Si vapor pressure etching in which a surface of the SiC wafer is etched by heating the SiC wafer enables to decrease the thickness of the SiC wafer to 100 μm or less. 2. The method for manufacturing the thin SiC wafer according to claim 1, wherein
in the thinning step, the Si vapor pressure etching is performed to the SiC wafer after cutting out of the ingot, the SiC wafer that has not been subjected to mechanically grinding for adjusting the thickness of the SiC wafer. 3. The method for manufacturing the thin SiC wafer according to claim 1, wherein
in the thinning step, the thickness of the SiC wafer is decreased while removing the surface roughness of the SiC wafer formed at a time of cutting out of the ingot. 4. The method for manufacturing the thin SiC wafer according to claim 1, wherein
in the thinning step, the thickness of the SiC wafer is removed by 100 μm or more. 5. The method for manufacturing the thin SiC wafer according to claim 1, wherein
in the thinning step, at least the Si vapor pressure etching in which an etching rate of a surface to be treated is 500 nm/min or more is performed. 6. The method for manufacturing the thin SiC wafer according to claim 1, wherein
when one surface for forming an epitaxial layer in the SiC wafer is specified as a main surface, in the thinning step, both of the main surface of the SiC wafer and a back surface of the main surface are etched. 7. The method for manufacturing the thin SiC wafer according to claim 1, wherein
in the thinning step, the Si vapor pressure etching is performed to the SiC wafer in which a mark is formed, the mark that shows information by removing the surface to be formed into a predetermined shape. 8. The method for manufacturing the thin SiC wafer according to claim 7, wherein
prior to the thinning step, a mark forming step for forming the mark on the SiC wafer is performed. 9. The method for manufacturing the thin SiC wafer according to claim 1, wherein
in the thinning step, the Si vapor pressure etching is performed such that an amount of etching is varied depending on a position of the SiC wafer. 10. The method for manufacturing the thin SiC wafer according to claim 9, wherein
in the thinning step, the Si vapor pressure etching is performed such that the thickness in an outer edge part of the SiC wafer is larger than the thickness in the central region and the thickness in the central region is 100 μm or less. 11. The method for manufacturing the thin SiC wafer according to claim 9, wherein
in the thinning step, the SiC wafer is chamfered while decreasing the thickness of the SiC wafer. 12. A method for manufacturing a thin SiC wafer by processing a SiC wafer after cutting out of an ingot comprising:
a thinning step for thinning a thickness of the SiC wafer after cutting out of the ingot; wherein in the thinning step, after the thickness of the SiC wafer is decreased by mechanically grinding, the thickness is further decreased by performing a Si vapor pressure etching in which a surface of the SiC wafer is etched by heating the SiC wafer under Si vapor pressure, which decreases the thickness of the SiC wafer to 100 μm or less. 13. A SiC wafer, in its surface, having a mark showing information depending on a removed shape that is formed into a predetermined shape by removing, and having the thin thickness of 100 μm or less. 14. The SiC wafer according to claim 13, the wafer before forming an epitaxial layer, including a region having a hardness of 27 GPa or more when the surface is measured by using nano indentation method under a condition that the load is 500 mN or the indentation is 1 μm. 15. The SiC wafer according to claim 13, on its surface, having an epitaxial layer, including a region having the hardness of 29.5 GPa or more when the surface of the epitaxial layer is measured by using nano indentation method under a condition that the load is 500 mN or the indentation is 1 μm. 16. The SiC wafer according to claim 13, the wafer before forming an epitaxial layer, having a higher hardness, when the surface is measured by using nano indentation method under a condition that the load is 500 mN or the indentation is 1 μm, than the hardness of the SiC wafer after performing a chemical mechanical polishing. 17. The SiC wafer according to claim 13, wherein
a central region and an outer edge part are provided, the thickness of the outer edge part is larger than the thickness of the central region. | Provided is a method for manufacturing a thin SiC wafer by which a SiC wafer is thinned using a method without generating crack or the like, the method in which polishing after adjusting the thickness of the SiC wafer can be omitted. The method for manufacturing the thin SiC wafer 40 includes a thinning step. In the thinning step, the thickness of the SiC wafer 40 can be decreased to 100 μm or less by performing the Si vapor pressure etching in which the surface of the SiC wafer 40 is etched by heating the SiC wafer 40 after cutting out of an ingot 4 under Si vapor pressure.1. A method for manufacturing a thin SiC wafer by processing a SiC wafer after cutting out of an ingot comprising:
a thinning step for thinning a thickness of the SiC wafer after cutting out of the ingot; wherein in the thinning step, performing a Si vapor pressure etching in which a surface of the SiC wafer is etched by heating the SiC wafer enables to decrease the thickness of the SiC wafer to 100 μm or less. 2. The method for manufacturing the thin SiC wafer according to claim 1, wherein
in the thinning step, the Si vapor pressure etching is performed to the SiC wafer after cutting out of the ingot, the SiC wafer that has not been subjected to mechanically grinding for adjusting the thickness of the SiC wafer. 3. The method for manufacturing the thin SiC wafer according to claim 1, wherein
in the thinning step, the thickness of the SiC wafer is decreased while removing the surface roughness of the SiC wafer formed at a time of cutting out of the ingot. 4. The method for manufacturing the thin SiC wafer according to claim 1, wherein
in the thinning step, the thickness of the SiC wafer is removed by 100 μm or more. 5. The method for manufacturing the thin SiC wafer according to claim 1, wherein
in the thinning step, at least the Si vapor pressure etching in which an etching rate of a surface to be treated is 500 nm/min or more is performed. 6. The method for manufacturing the thin SiC wafer according to claim 1, wherein
when one surface for forming an epitaxial layer in the SiC wafer is specified as a main surface, in the thinning step, both of the main surface of the SiC wafer and a back surface of the main surface are etched. 7. The method for manufacturing the thin SiC wafer according to claim 1, wherein
in the thinning step, the Si vapor pressure etching is performed to the SiC wafer in which a mark is formed, the mark that shows information by removing the surface to be formed into a predetermined shape. 8. The method for manufacturing the thin SiC wafer according to claim 7, wherein
prior to the thinning step, a mark forming step for forming the mark on the SiC wafer is performed. 9. The method for manufacturing the thin SiC wafer according to claim 1, wherein
in the thinning step, the Si vapor pressure etching is performed such that an amount of etching is varied depending on a position of the SiC wafer. 10. The method for manufacturing the thin SiC wafer according to claim 9, wherein
in the thinning step, the Si vapor pressure etching is performed such that the thickness in an outer edge part of the SiC wafer is larger than the thickness in the central region and the thickness in the central region is 100 μm or less. 11. The method for manufacturing the thin SiC wafer according to claim 9, wherein
in the thinning step, the SiC wafer is chamfered while decreasing the thickness of the SiC wafer. 12. A method for manufacturing a thin SiC wafer by processing a SiC wafer after cutting out of an ingot comprising:
a thinning step for thinning a thickness of the SiC wafer after cutting out of the ingot; wherein in the thinning step, after the thickness of the SiC wafer is decreased by mechanically grinding, the thickness is further decreased by performing a Si vapor pressure etching in which a surface of the SiC wafer is etched by heating the SiC wafer under Si vapor pressure, which decreases the thickness of the SiC wafer to 100 μm or less. 13. A SiC wafer, in its surface, having a mark showing information depending on a removed shape that is formed into a predetermined shape by removing, and having the thin thickness of 100 μm or less. 14. The SiC wafer according to claim 13, the wafer before forming an epitaxial layer, including a region having a hardness of 27 GPa or more when the surface is measured by using nano indentation method under a condition that the load is 500 mN or the indentation is 1 μm. 15. The SiC wafer according to claim 13, on its surface, having an epitaxial layer, including a region having the hardness of 29.5 GPa or more when the surface of the epitaxial layer is measured by using nano indentation method under a condition that the load is 500 mN or the indentation is 1 μm. 16. The SiC wafer according to claim 13, the wafer before forming an epitaxial layer, having a higher hardness, when the surface is measured by using nano indentation method under a condition that the load is 500 mN or the indentation is 1 μm, than the hardness of the SiC wafer after performing a chemical mechanical polishing. 17. The SiC wafer according to claim 13, wherein
a central region and an outer edge part are provided, the thickness of the outer edge part is larger than the thickness of the central region. | 2,800 |
12,110 | 12,110 | 16,601,424 | 2,875 | A vehicle lighting system includes a light processing unit, a non-uniform projection unit, a sensing unit, a judgment unit, and an operation unit. The light processing unit is capable of changing an intensity profile of a light beam, and the judgment unit receives an image signal from the sensing unit to determine whether to change the intensity profile of the light beam according to the image signal. When the intensity profile needs to be changed in accordance with the judgment result, the operation unit calculates out a desired intensity profile and outputs a control signal containing information about the desired intensity profile to the light processing unit, and the light processing unit changes the intensity profile of the light beam according to the control signal and sends out the light beam with the desired intensity profile. | 1. A vehicle lighting system, comprising:
a light processing unit capable of changing an intensity profile of a light beam; a non-uniform projection unit capable of converting the light beam processed by the light processing unit into a light beam having a non-uniform intensity profile; a sensing unit for detecting surrounding conditions and outputting at least one image signal in response to the detected surrounding conditions; a judgment unit for receiving the image signal from the sensing unit to determine whether to change the intensity profile of the light beam according to the image signal; and an operation unit for receiving a judgment result of the judgment unit, wherein, when the intensity profile needs to be changed in accordance with the judgment result, the operation unit calculates out a desired intensity profile and outputs a control signal containing information about the desired intensity profile to the light processing unit, and the light processing unit changes the intensity profile of the light beam according to the control signal and sends out the light beam with the desired intensity profile. 2. The vehicle lighting system as claimed in claim 1, wherein the sensing unit is a camera. 3. The vehicle lighting system as claimed in claim 1, wherein the sensing unit is a thermal image camera capable of sensing ambient energy to generate the image signal. 4. The vehicle lighting system as claimed in claim 1, wherein, when the intensity profile needs not to be changed in accordance with the judgment result, the operation unit outputs a recovery signal to the light processing unit. 5. The vehicle lighting system as claimed in claim 1, wherein the light processing unit receives a control signal of the judgment unit and adjusts the intensity profile of the light beam according to the control signal. 6. The vehicle lighting system as claimed in claim 1, wherein the light processing unit is a light valve. 7. The vehicle lighting system as claimed in claim 6, wherein the light processing unit comprises a digital micro mirror device. 8. The vehicle lighting system as claimed in claim 1, wherein the non-uniform projection unit is a vehicle lamp cover comprised of at least one lens. 9. The vehicle lighting system as claimed in claim 1, wherein the non-uniform projection unit is a singlet lens or a lens module. 10. The vehicle lighting system as claimed in claim 1, wherein the light beam processed by the light processing unit has a Gaussian intensity profile, and the non-uniform projection unit coverts the Gaussian intensity profile into a non-uniform intensity profile. 11. The vehicle lighting system as claimed in claim 1, further comprising:
a light source for emitting the light beam; and a beam expander disposed downstream from the light source in a light path. 12. The vehicle lighting system as claimed in claim 11, wherein the light processing unit is disposed downstream from the beam expander in the light path. 13. The vehicle lighting system as claimed in claim 11, wherein the non-uniform projection unit is disposed downstream from the light processing unit in the light path. 14. The vehicle lighting system as claimed in claim 11, wherein the beam expander comprises at least two lenses, and focus points of the two lenses are substantially the same. 15. The vehicle lighting system as claimed in claim 11, further comprising:
a beam homogenizer disposed between the light source and the light processing unit along the light path. 16. The vehicle lighting system as claimed in claim 15, wherein the beam homogenizer is a diffuser. 17. The vehicle lighting system as claimed in claim 11, further comprising a beam shaper disposed between the beam expander and the light processing unit along the light path. 18. The vehicle lighting system as claimed in claim 11, wherein the light source is capable of outputting a first light beam having first speckle size, the light processing unit receives a second light beam having a second speckle size, and the second speckle size is substantially larger than the first speckle size. 19. A vehicle lighting system, comprising:
a camera, capable of outputting an image signal in response to at least one detected object outside a vehicle; a judgment unit, electronically coupled to the camera, the judgment unit is capable of determining whether to change an intensity profile of a light beam according to the image signal and providing a judgment result; an operation unit, electronically coupled to the judgment unit, the operation unit being capable of receiving the judgment result, obtaining a desired intensity profile by calculation, and outputting a control signal; a light valve electronically coupled to the operation unit and sending out the light beam with the desired intensity profile according to the control signal; and a non-uniform projection unit capable of converting the light beam processed by the light processing unit into a light beam having a non-uniform intensity profile. 20. The vehicle lighting system as claimed in claim 19, wherein the operation unit calculates out a distance, an angle and a luminous intensity distribution of a dynamic object relative to the vehicle lighting system. | A vehicle lighting system includes a light processing unit, a non-uniform projection unit, a sensing unit, a judgment unit, and an operation unit. The light processing unit is capable of changing an intensity profile of a light beam, and the judgment unit receives an image signal from the sensing unit to determine whether to change the intensity profile of the light beam according to the image signal. When the intensity profile needs to be changed in accordance with the judgment result, the operation unit calculates out a desired intensity profile and outputs a control signal containing information about the desired intensity profile to the light processing unit, and the light processing unit changes the intensity profile of the light beam according to the control signal and sends out the light beam with the desired intensity profile.1. A vehicle lighting system, comprising:
a light processing unit capable of changing an intensity profile of a light beam; a non-uniform projection unit capable of converting the light beam processed by the light processing unit into a light beam having a non-uniform intensity profile; a sensing unit for detecting surrounding conditions and outputting at least one image signal in response to the detected surrounding conditions; a judgment unit for receiving the image signal from the sensing unit to determine whether to change the intensity profile of the light beam according to the image signal; and an operation unit for receiving a judgment result of the judgment unit, wherein, when the intensity profile needs to be changed in accordance with the judgment result, the operation unit calculates out a desired intensity profile and outputs a control signal containing information about the desired intensity profile to the light processing unit, and the light processing unit changes the intensity profile of the light beam according to the control signal and sends out the light beam with the desired intensity profile. 2. The vehicle lighting system as claimed in claim 1, wherein the sensing unit is a camera. 3. The vehicle lighting system as claimed in claim 1, wherein the sensing unit is a thermal image camera capable of sensing ambient energy to generate the image signal. 4. The vehicle lighting system as claimed in claim 1, wherein, when the intensity profile needs not to be changed in accordance with the judgment result, the operation unit outputs a recovery signal to the light processing unit. 5. The vehicle lighting system as claimed in claim 1, wherein the light processing unit receives a control signal of the judgment unit and adjusts the intensity profile of the light beam according to the control signal. 6. The vehicle lighting system as claimed in claim 1, wherein the light processing unit is a light valve. 7. The vehicle lighting system as claimed in claim 6, wherein the light processing unit comprises a digital micro mirror device. 8. The vehicle lighting system as claimed in claim 1, wherein the non-uniform projection unit is a vehicle lamp cover comprised of at least one lens. 9. The vehicle lighting system as claimed in claim 1, wherein the non-uniform projection unit is a singlet lens or a lens module. 10. The vehicle lighting system as claimed in claim 1, wherein the light beam processed by the light processing unit has a Gaussian intensity profile, and the non-uniform projection unit coverts the Gaussian intensity profile into a non-uniform intensity profile. 11. The vehicle lighting system as claimed in claim 1, further comprising:
a light source for emitting the light beam; and a beam expander disposed downstream from the light source in a light path. 12. The vehicle lighting system as claimed in claim 11, wherein the light processing unit is disposed downstream from the beam expander in the light path. 13. The vehicle lighting system as claimed in claim 11, wherein the non-uniform projection unit is disposed downstream from the light processing unit in the light path. 14. The vehicle lighting system as claimed in claim 11, wherein the beam expander comprises at least two lenses, and focus points of the two lenses are substantially the same. 15. The vehicle lighting system as claimed in claim 11, further comprising:
a beam homogenizer disposed between the light source and the light processing unit along the light path. 16. The vehicle lighting system as claimed in claim 15, wherein the beam homogenizer is a diffuser. 17. The vehicle lighting system as claimed in claim 11, further comprising a beam shaper disposed between the beam expander and the light processing unit along the light path. 18. The vehicle lighting system as claimed in claim 11, wherein the light source is capable of outputting a first light beam having first speckle size, the light processing unit receives a second light beam having a second speckle size, and the second speckle size is substantially larger than the first speckle size. 19. A vehicle lighting system, comprising:
a camera, capable of outputting an image signal in response to at least one detected object outside a vehicle; a judgment unit, electronically coupled to the camera, the judgment unit is capable of determining whether to change an intensity profile of a light beam according to the image signal and providing a judgment result; an operation unit, electronically coupled to the judgment unit, the operation unit being capable of receiving the judgment result, obtaining a desired intensity profile by calculation, and outputting a control signal; a light valve electronically coupled to the operation unit and sending out the light beam with the desired intensity profile according to the control signal; and a non-uniform projection unit capable of converting the light beam processed by the light processing unit into a light beam having a non-uniform intensity profile. 20. The vehicle lighting system as claimed in claim 19, wherein the operation unit calculates out a distance, an angle and a luminous intensity distribution of a dynamic object relative to the vehicle lighting system. | 2,800 |
12,111 | 12,111 | 15,444,731 | 2,872 | An emergency vision apparatus comprises an inflatable enclosure to enable a user to see through the enclosure when expanded and observe a source of information at a distal end of the enclosure while smoke or other particulate matter is in the environment. The enclosure includes an opening configured for insertion of a user's hand into the interior of the enclosure to allow the user to operate a touch sensitive screen or hardware visible through the second clear member disposed toward a user and a sealable closure for closing the opening and sealing the opening around the user's hand. The sealable closure includes flexible first and second sheets covering the opening, the first and second sheets including respective first and second slits disposed transversely to each other, the first and second slits being configured to allow insertion of the user's hand into the interior of the enclosure. | 1. An emergency vision apparatus, comprising:
a) an inflatable enclosure being made of airtight material and having an expanded form when deployed and a deflated form when not in use; b) first and second clear members disposed at respective first and second ends of said first enclosure to enable a user to see through said enclosure when expanded and observe a source of information at a distal end of said enclosure while smoke or other particulate matter is in the environment; c) said enclosure including an opening configured for insertion of a user's hand into the interior of said enclosure to allow the user to operate a touch sensitive screen or hardware visible through said second clear member disposed toward a user; and d) a sealable closure for closing said opening and sealing said opening around the user's hand; and e) said sealable closure including flexible first and second sheets covering said opening, said first and second sheets including respective first and second slits disposed transversely to each other, said first and second slits being configured to allow insertion of the user's hand into the interior of said enclosure. 2. An emergency vision apparatus as in claim 1, wherein said first and second sheets are stretchable. 3. An emergency vision apparatus as in claim 1, and further comprising a third sheet disposed within said enclosure overlying an intersection of said first and second slits. 4. An emergency vision apparatus, comprising:
a) an inflatable enclosure being made of airtight material and having an expanded form when deployed and a deflated form when not in use; b) first and second clear members disposed at respective first and second ends of said first enclosure to enable a user to see through said enclosure when expanded and observe a source of information at a distal end of said enclosure while smoke or other particulate matter is in the environment; c) said enclosure including wall opening configured for insertion of a user's hand into the interior of said enclosure to allow the user to operate a touch sensitive screen or hardware visible through said second clear member disposed toward a user; and d) a sealable closure for closing said wall opening and sealing said wall opening around the user's hand; and e) said sealable closure including flexible tube with first and second ends including first and second openings disposed at respective said first and second ends, said first opening encompassing said wall opening, said second opening being configured to allow the user's thumb and index finger together to extend through said second opening. 5. An emergency vision apparatus as in claim 4, wherein said tube is stretchable. 6. An emergency vision apparatus as in claim 4, wherein said second opening is smaller than said first opening. | An emergency vision apparatus comprises an inflatable enclosure to enable a user to see through the enclosure when expanded and observe a source of information at a distal end of the enclosure while smoke or other particulate matter is in the environment. The enclosure includes an opening configured for insertion of a user's hand into the interior of the enclosure to allow the user to operate a touch sensitive screen or hardware visible through the second clear member disposed toward a user and a sealable closure for closing the opening and sealing the opening around the user's hand. The sealable closure includes flexible first and second sheets covering the opening, the first and second sheets including respective first and second slits disposed transversely to each other, the first and second slits being configured to allow insertion of the user's hand into the interior of the enclosure.1. An emergency vision apparatus, comprising:
a) an inflatable enclosure being made of airtight material and having an expanded form when deployed and a deflated form when not in use; b) first and second clear members disposed at respective first and second ends of said first enclosure to enable a user to see through said enclosure when expanded and observe a source of information at a distal end of said enclosure while smoke or other particulate matter is in the environment; c) said enclosure including an opening configured for insertion of a user's hand into the interior of said enclosure to allow the user to operate a touch sensitive screen or hardware visible through said second clear member disposed toward a user; and d) a sealable closure for closing said opening and sealing said opening around the user's hand; and e) said sealable closure including flexible first and second sheets covering said opening, said first and second sheets including respective first and second slits disposed transversely to each other, said first and second slits being configured to allow insertion of the user's hand into the interior of said enclosure. 2. An emergency vision apparatus as in claim 1, wherein said first and second sheets are stretchable. 3. An emergency vision apparatus as in claim 1, and further comprising a third sheet disposed within said enclosure overlying an intersection of said first and second slits. 4. An emergency vision apparatus, comprising:
a) an inflatable enclosure being made of airtight material and having an expanded form when deployed and a deflated form when not in use; b) first and second clear members disposed at respective first and second ends of said first enclosure to enable a user to see through said enclosure when expanded and observe a source of information at a distal end of said enclosure while smoke or other particulate matter is in the environment; c) said enclosure including wall opening configured for insertion of a user's hand into the interior of said enclosure to allow the user to operate a touch sensitive screen or hardware visible through said second clear member disposed toward a user; and d) a sealable closure for closing said wall opening and sealing said wall opening around the user's hand; and e) said sealable closure including flexible tube with first and second ends including first and second openings disposed at respective said first and second ends, said first opening encompassing said wall opening, said second opening being configured to allow the user's thumb and index finger together to extend through said second opening. 5. An emergency vision apparatus as in claim 4, wherein said tube is stretchable. 6. An emergency vision apparatus as in claim 4, wherein said second opening is smaller than said first opening. | 2,800 |
12,112 | 12,112 | 15,856,350 | 2,837 | A device comprises: a first spiral coil laid out on a first metal layer of a multi-layer structure, the first spiral coil spiraling inward from a first end to a second end in a clockwise direction from a first perspective that is perpendicular to the first metal layer; a second spiral coil laid out on the first metal layer, the second spiral coil spiraling outward from a third end to a fourth end in a counterclockwise direction from the first perspective, wherein the first spiral coil and the second spiral coil are substantially symmetrical with respect to a central line perpendicular to the multi-layer structure; a twin-spiral coil laid out on a second metal layer of the multi-layer structure, the twin-spiral coil spiraling outward from a fifth end to the central line in a clockwise direction from the first perspective and then spiraling inward from the central line to a sixth end in a counterclockwise direction from the first perspective, wherein the twin-spiral coil is substantially symmetrical with respect to the central line; a first via configured to electrically connect the second end to the fifth end; and a second via configured to electrically connect the third end to the sixth end. | 1. A device comprising:
a first spiral coil laid out on a first metal layer of a multi-layer structure, the first spiral coil spiraling inward from a first end to a second end in a clockwise direction from a first perspective that is perpendicular to the first metal layer; a second spiral coil laid out on the first metal layer, the second spiral coil spiraling outward from a third end to a fourth end in a counterclockwise direction from the first perspective, wherein the first spiral coil and the second spiral coil are substantially symmetrical with respect to a central line perpendicular to the multi-layer structure; a twin-spiral coil laid out on a second metal layer of the multi-layer structure, the twin-spiral coil spiraling outward from a fifth end to the central line in a clockwise direction from the first perspective and then spiraling inward from the central line to a sixth end in a counterclockwise direction from the first perspective, wherein the twin-spiral coil is substantially symmetrical with respect to the central line; a first via configured to electrically connect the second end to the fifth end; and a second via configured to electrically connect the third end to the sixth end. 2. The device of claim 1, wherein the multi-layer structure includes a dielectric slab configured to provide a housing for the first metal layer and the second metal layer 3. The device of claim 2, wherein the dielectric slab is laid out on top of a substrate. 4. The device of claim 3, wherein another device is laid out on the substrate, said another device being a mirror image of the device of claim 3 with respect to a plane of symmetry, the plane of symmetry being perpendicular to the multi-layer structure. 5. A method comprising:
deploying a first spiral coil on a first metal layer of a multi-layer structure, the first spiral coil spiraling inward from a first end to a second end in a clockwise direction from a first perspective that is perpendicular to the first metal layer; deploying a second spiral coil on the first metal layer, the second spiral coil spiraling outward from a third end to a fourth end in a counterclockwise direction from the first perspective, wherein the first spiral coil and the second spiral coil are substantially symmetrical with respect to a central line perpendicular to the multi-layer structure; interposing a first via between the second end on the first metal layer and a fifth end on a second metal layer of the multi-layer structure; interposing a second via between the third end on the first metal layer and a sixth end on the second metal layer; deploying a first twin-spiral coil on the second metal layer, the first twin-spiral coil spiraling outward from the fifth end to the central line in a clockwise direction from the first perspective and then spiraling inward from the central line to the sixth end in a counterclockwise direction from the first perspective, wherein the first twin-spiral coil is substantially symmetrical with respect to the central line. 6. The method of claim 5, wherein the multi-layer structure includes a dielectric slab configured to provide a housing for the first metal layer and the second metal layer 7. The method of claim 6, wherein the dielectric slab is laid out on top of a substrate. 8. The method of claim 7 further comprising: deploying a third spiral coil and a fourth spiral coil, interposing a third via and a fourth via, and deploying a second twin-spiral coil in a way such that the third spiral coil, the fourth spiraling coil, the third via, the fourth via, and the second twin-spiral coil are mirror images of the first spiral coil, the second spiral coil, the first via, the second via, and the first twin-spiral coil with respect to a plane of symmetry perpendicular to the multi-layer structure. | A device comprises: a first spiral coil laid out on a first metal layer of a multi-layer structure, the first spiral coil spiraling inward from a first end to a second end in a clockwise direction from a first perspective that is perpendicular to the first metal layer; a second spiral coil laid out on the first metal layer, the second spiral coil spiraling outward from a third end to a fourth end in a counterclockwise direction from the first perspective, wherein the first spiral coil and the second spiral coil are substantially symmetrical with respect to a central line perpendicular to the multi-layer structure; a twin-spiral coil laid out on a second metal layer of the multi-layer structure, the twin-spiral coil spiraling outward from a fifth end to the central line in a clockwise direction from the first perspective and then spiraling inward from the central line to a sixth end in a counterclockwise direction from the first perspective, wherein the twin-spiral coil is substantially symmetrical with respect to the central line; a first via configured to electrically connect the second end to the fifth end; and a second via configured to electrically connect the third end to the sixth end.1. A device comprising:
a first spiral coil laid out on a first metal layer of a multi-layer structure, the first spiral coil spiraling inward from a first end to a second end in a clockwise direction from a first perspective that is perpendicular to the first metal layer; a second spiral coil laid out on the first metal layer, the second spiral coil spiraling outward from a third end to a fourth end in a counterclockwise direction from the first perspective, wherein the first spiral coil and the second spiral coil are substantially symmetrical with respect to a central line perpendicular to the multi-layer structure; a twin-spiral coil laid out on a second metal layer of the multi-layer structure, the twin-spiral coil spiraling outward from a fifth end to the central line in a clockwise direction from the first perspective and then spiraling inward from the central line to a sixth end in a counterclockwise direction from the first perspective, wherein the twin-spiral coil is substantially symmetrical with respect to the central line; a first via configured to electrically connect the second end to the fifth end; and a second via configured to electrically connect the third end to the sixth end. 2. The device of claim 1, wherein the multi-layer structure includes a dielectric slab configured to provide a housing for the first metal layer and the second metal layer 3. The device of claim 2, wherein the dielectric slab is laid out on top of a substrate. 4. The device of claim 3, wherein another device is laid out on the substrate, said another device being a mirror image of the device of claim 3 with respect to a plane of symmetry, the plane of symmetry being perpendicular to the multi-layer structure. 5. A method comprising:
deploying a first spiral coil on a first metal layer of a multi-layer structure, the first spiral coil spiraling inward from a first end to a second end in a clockwise direction from a first perspective that is perpendicular to the first metal layer; deploying a second spiral coil on the first metal layer, the second spiral coil spiraling outward from a third end to a fourth end in a counterclockwise direction from the first perspective, wherein the first spiral coil and the second spiral coil are substantially symmetrical with respect to a central line perpendicular to the multi-layer structure; interposing a first via between the second end on the first metal layer and a fifth end on a second metal layer of the multi-layer structure; interposing a second via between the third end on the first metal layer and a sixth end on the second metal layer; deploying a first twin-spiral coil on the second metal layer, the first twin-spiral coil spiraling outward from the fifth end to the central line in a clockwise direction from the first perspective and then spiraling inward from the central line to the sixth end in a counterclockwise direction from the first perspective, wherein the first twin-spiral coil is substantially symmetrical with respect to the central line. 6. The method of claim 5, wherein the multi-layer structure includes a dielectric slab configured to provide a housing for the first metal layer and the second metal layer 7. The method of claim 6, wherein the dielectric slab is laid out on top of a substrate. 8. The method of claim 7 further comprising: deploying a third spiral coil and a fourth spiral coil, interposing a third via and a fourth via, and deploying a second twin-spiral coil in a way such that the third spiral coil, the fourth spiraling coil, the third via, the fourth via, and the second twin-spiral coil are mirror images of the first spiral coil, the second spiral coil, the first via, the second via, and the first twin-spiral coil with respect to a plane of symmetry perpendicular to the multi-layer structure. | 2,800 |
12,113 | 12,113 | 16,169,843 | 2,822 | In a described example, an apparatus includes a substrate with a first surface and an opposing second surface. The substrate includes a trench extending into the substrate from the first surface, a die mounting area adjacent to the trench, a first plurality of leads, and a second plurality of leads. The second plurality of leads are spaced from the trench to electrically isolate the second plurality of leads. The apparatus further includes a first mold compound in the trench forming a filled trench and in the space between the trench and the second plurality of leads. A first die is attached to the first surface of the substrate and a second die is attached to a surface of the first mold compound in the filled trench. | 1. An apparatus comprising:
a substrate comprising:
a first surface and an opposing second surface;
a trench extending into the substrate from the first surface;
a die mounting area adjacent to the trench;
a first plurality of leads;
a second plurality of leads, wherein the second plurality of leads are spaced from the trench to electrically isolate the second plurality of leads;
a first mold compound filling the trench to form a filled trench and in the space between the filled trench and the second plurality of leads;
a first die attached to the first surface of the substrate in the die mounting area, and electrically connected to at least one of the first plurality of leads; and a second die attached to a surface of the first mold compound in the filled trench. 2. The apparatus of claim 1, wherein the trench is a partial etch forming a recess that extends partially into the substrate and having a bottom of the substrate. 3. The apparatus of claim 1, wherein the first die is attached to the die mounting area of the substrate by a conductive die attach. 4. The apparatus of claim 1, wherein the second die is attached to the first mold compound in the filled trench by an adhesive. 5. The apparatus of claim 1, wherein the filled trench has a first width greater than a second width of the second die. 6. The apparatus of claim 1, wherein the first surface of the substrate and a surface of the first mold compound are substantially coplanar. 7. The apparatus of claim 1, wherein a depth of the first mold compound is between 1 and 100 microns, wherein a width of the first mold compound is wider than a width of the second die, and wherein the first surface of the substrate and the surface of the first mold compound is substantially coplanar. 8. The apparatus of claim 1 further comprising:
electrical connections between the first die and the second die, and the second die and at least one of the second plurality of leads; and
a second mold compound over at least a portion of the substrate. 9. The apparatus of claim 8, wherein the second mold compound and the first mold compound are of the same material. 10. A packaged device, comprising:
a substrate having a first surface and an opposing second surface, the substrate comprising:
a die pad having a trench formed therein and a die mounting area spaced from the trench, and wherein the trench extends partially into the die pad;
a first plurality of leads, and a second plurality of leads, the second plurality of leads being spaced from, and electrically isolated from, the die pad;
a first mold compound in the trench to form a filled trench and in the space between the second plurality of leads and the die pad, the first mold compound having a surface coplanar with a first surface of the die pad;
a first die attached to the die mounting area of the die pad;
a second die attached to the first mold compound in the filled trench, wherein the first mold compound in the filled trench electrically isolates the second die from the first die;
electrical connections between the first die and the second die, the first die and the first plurality of leads, and the second die and the second plurality of leads; and
a second mold compound covering the first die, the second die, and at least portions of the substrate. 11. The packaged device of claim 10, wherein a surface of the second mold compound is coterminous with a surface of the first mold compound. 12. The packaged device of claim 10, wherein the space between the second plurality of leads and the die pad is at least 100 microns. 13. The packaged device of claim 10, wherein an outer perimeter of the filled trench extends beyond an outer perimeter of the second die. 14. The packaged device of claim 13, wherein a distance between the outer perimeter of the filled trench and the outer perimeter of the second die is at least 100 microns. 15. The packaged device of claim 10, wherein the substrate has a height of approximately 200 microns between the first surface and the second surface. 16. The packaged device of claim 10, wherein a depth of the trench is approximately 80 to 100 microns. 17. A method comprising:
attaching a first die to a first surface of a substrate, the substrate comprising the first surface and an opposing second surface, a first plurality of leads and a second plurality of leads; attaching a second die to a first mold compound in a filled trench, the trench including a recess extending into the first surface of the substrate and having a bottom within the substrate; electrically connecting the first die to the second die, the first die to the first plurality of leads, and the second die to the second plurality of leads; and covering the first die, the second die, the first mold compound and at least a portion of the substrate with a second mold compound. 18. The method of claim 17, wherein the trench extends into the substrate, the substrate is a conductive lead frame, the substrate is a pre-molded lead frame with a die pad portion and leads spaced from one another by additional portions of the first mold compound that fills the filled trench. 19. The method of claim 17, wherein the first mold compound is a pre-mold that fills the trench prior to attaching the first die and the second die, and wherein the second mold compound is an overmold that is covers the first die, the second die and at least a portion of the substrate after attaching the first and second dies. 20. The method of claim 17, wherein the substrate is conductive, and wherein the second die is electrically isolated from the substrate by the first mold compound. 21. A method comprising:
forming a trench in a substrate having a recess extending into the substrate and having a bottom within the substrate, the substrate comprising a die pad, a first plurality of leads and a second plurality of leads; inserting a first mold compound into the trench to form a filled trench; inserting the first mold compound between the die pad and the leads; attaching a first die to a die mounting area, wherein the die mounting area and the filled trench are on the die pad, and wherein the die mounting area is spaced from the filled trench; attaching a second die to a surface of the first mold compound in the filled trench; electrically connecting the first die to the second die, the first die to the first plurality of leads, and the second die to the second plurality of leads; and covering the first die, the second die, at least a portion of the substrate and the first mold compound with a second mold compound. 22. The method of claim 21, wherein the trench extends partially through the substrate. 23. The method of claim 21, wherein the substrate is a conductive lead frame, and wherein the first mold compound electrically isolates the die pad from the leads. | In a described example, an apparatus includes a substrate with a first surface and an opposing second surface. The substrate includes a trench extending into the substrate from the first surface, a die mounting area adjacent to the trench, a first plurality of leads, and a second plurality of leads. The second plurality of leads are spaced from the trench to electrically isolate the second plurality of leads. The apparatus further includes a first mold compound in the trench forming a filled trench and in the space between the trench and the second plurality of leads. A first die is attached to the first surface of the substrate and a second die is attached to a surface of the first mold compound in the filled trench.1. An apparatus comprising:
a substrate comprising:
a first surface and an opposing second surface;
a trench extending into the substrate from the first surface;
a die mounting area adjacent to the trench;
a first plurality of leads;
a second plurality of leads, wherein the second plurality of leads are spaced from the trench to electrically isolate the second plurality of leads;
a first mold compound filling the trench to form a filled trench and in the space between the filled trench and the second plurality of leads;
a first die attached to the first surface of the substrate in the die mounting area, and electrically connected to at least one of the first plurality of leads; and a second die attached to a surface of the first mold compound in the filled trench. 2. The apparatus of claim 1, wherein the trench is a partial etch forming a recess that extends partially into the substrate and having a bottom of the substrate. 3. The apparatus of claim 1, wherein the first die is attached to the die mounting area of the substrate by a conductive die attach. 4. The apparatus of claim 1, wherein the second die is attached to the first mold compound in the filled trench by an adhesive. 5. The apparatus of claim 1, wherein the filled trench has a first width greater than a second width of the second die. 6. The apparatus of claim 1, wherein the first surface of the substrate and a surface of the first mold compound are substantially coplanar. 7. The apparatus of claim 1, wherein a depth of the first mold compound is between 1 and 100 microns, wherein a width of the first mold compound is wider than a width of the second die, and wherein the first surface of the substrate and the surface of the first mold compound is substantially coplanar. 8. The apparatus of claim 1 further comprising:
electrical connections between the first die and the second die, and the second die and at least one of the second plurality of leads; and
a second mold compound over at least a portion of the substrate. 9. The apparatus of claim 8, wherein the second mold compound and the first mold compound are of the same material. 10. A packaged device, comprising:
a substrate having a first surface and an opposing second surface, the substrate comprising:
a die pad having a trench formed therein and a die mounting area spaced from the trench, and wherein the trench extends partially into the die pad;
a first plurality of leads, and a second plurality of leads, the second plurality of leads being spaced from, and electrically isolated from, the die pad;
a first mold compound in the trench to form a filled trench and in the space between the second plurality of leads and the die pad, the first mold compound having a surface coplanar with a first surface of the die pad;
a first die attached to the die mounting area of the die pad;
a second die attached to the first mold compound in the filled trench, wherein the first mold compound in the filled trench electrically isolates the second die from the first die;
electrical connections between the first die and the second die, the first die and the first plurality of leads, and the second die and the second plurality of leads; and
a second mold compound covering the first die, the second die, and at least portions of the substrate. 11. The packaged device of claim 10, wherein a surface of the second mold compound is coterminous with a surface of the first mold compound. 12. The packaged device of claim 10, wherein the space between the second plurality of leads and the die pad is at least 100 microns. 13. The packaged device of claim 10, wherein an outer perimeter of the filled trench extends beyond an outer perimeter of the second die. 14. The packaged device of claim 13, wherein a distance between the outer perimeter of the filled trench and the outer perimeter of the second die is at least 100 microns. 15. The packaged device of claim 10, wherein the substrate has a height of approximately 200 microns between the first surface and the second surface. 16. The packaged device of claim 10, wherein a depth of the trench is approximately 80 to 100 microns. 17. A method comprising:
attaching a first die to a first surface of a substrate, the substrate comprising the first surface and an opposing second surface, a first plurality of leads and a second plurality of leads; attaching a second die to a first mold compound in a filled trench, the trench including a recess extending into the first surface of the substrate and having a bottom within the substrate; electrically connecting the first die to the second die, the first die to the first plurality of leads, and the second die to the second plurality of leads; and covering the first die, the second die, the first mold compound and at least a portion of the substrate with a second mold compound. 18. The method of claim 17, wherein the trench extends into the substrate, the substrate is a conductive lead frame, the substrate is a pre-molded lead frame with a die pad portion and leads spaced from one another by additional portions of the first mold compound that fills the filled trench. 19. The method of claim 17, wherein the first mold compound is a pre-mold that fills the trench prior to attaching the first die and the second die, and wherein the second mold compound is an overmold that is covers the first die, the second die and at least a portion of the substrate after attaching the first and second dies. 20. The method of claim 17, wherein the substrate is conductive, and wherein the second die is electrically isolated from the substrate by the first mold compound. 21. A method comprising:
forming a trench in a substrate having a recess extending into the substrate and having a bottom within the substrate, the substrate comprising a die pad, a first plurality of leads and a second plurality of leads; inserting a first mold compound into the trench to form a filled trench; inserting the first mold compound between the die pad and the leads; attaching a first die to a die mounting area, wherein the die mounting area and the filled trench are on the die pad, and wherein the die mounting area is spaced from the filled trench; attaching a second die to a surface of the first mold compound in the filled trench; electrically connecting the first die to the second die, the first die to the first plurality of leads, and the second die to the second plurality of leads; and covering the first die, the second die, at least a portion of the substrate and the first mold compound with a second mold compound. 22. The method of claim 21, wherein the trench extends partially through the substrate. 23. The method of claim 21, wherein the substrate is a conductive lead frame, and wherein the first mold compound electrically isolates the die pad from the leads. | 2,800 |
12,114 | 12,114 | 15,316,575 | 2,881 | A method of mass spectrometry is disclosed comprising mass analysing an eluent from a chromatography device and obtaining parent ion data sets and corresponding product ion data sets, and determining whether, in a first product ion data set, one or more product ions are present that are related to one or more parent ions in a corresponding first parent ion data set, based on the mass or mass to charge ratio and/or intensity of the one or more product ions and the one or more parent ions. If it is determined that the one or more product ions are present, the method further comprises removing the one or more product ions from one or more second product ion data sets to produce one or more second modified product ion data sets and/or removing ions other than the one or more product ions from the first product ion data set to produce a first modified product ion data set. | 1. A method of mass spectrometry comprising:
mass analysing an eluent from a chromatography device and obtaining a plurality of parent ion data sets and a plurality of corresponding product ion data sets; and determining whether, in a first product ion data set of said plurality of product ions data sets, one or more product ions are present that are related to one or more parent ions in a corresponding first parent ion data set of said plurality of parent ion data sets, based on the masses or mass to charge ratios and/or intensities of said one or more product ions and said one or more parent ions; wherein if it is determined that said one or more product ions are present, the method further comprises removing said one or more product ions from one or more second product ion data sets of said plurality of product ion data sets to produce one or more second modified product ion data sets. 2. A method as claimed in claim 1, wherein if it is determined that said one or more product ions are present, the method further comprises removing ions other than said one or more product ions from said first product ion data set to produce a first modified product ion data set. 3. A method of mass spectrometry comprising:
mass analysing an eluent from a chromatography device and obtaining one or more parent ion data sets and one or more corresponding product ion data sets; and determining whether, in a first product ion data set of said one or more product ion data sets, one or more product ions are present that are related to one or more parent ions in a corresponding first parent ion data set of said one or more parent ion data sets, based on the masses or mass to charge ratios and/or intensities of said one or more product ions and said one or more parent ions; wherein if it is determined that said one or more product ions are present, the method further comprises removing ions other than said one or more product ions from said first product ion data set to produce a first modified product ion data set. 4-5. (canceled) 6. A method as claimed claim in claim 1, wherein mass analysing said eluent comprises ionising said eluent to produce a plurality of ions and mass analysing said plurality of ions to obtain said one or more parent ion data sets. 7. (canceled) 8. A method as claimed claim 1, wherein mass analysing said eluent comprises ionising said eluent to produce a plurality of ions, fragmenting or reacting said plurality of ions in a fragmentation, collision or reaction device to produce a plurality of product ions, and mass analysing said plurality of product ions to obtain said one or more product ion data sets. 9-10. (canceled) 11. A method as claimed in claim 1, wherein mass analysing said eluent comprises ionising said eluent to produce a plurality of ions and the method further comprising comprises:
separating said plurality of ions according to their ion mobility; obtaining said plurality of parent ion data sets and said plurality of corresponding product ion data sets using ion mobility drift alignment. 12. (canceled) 13. A method as claimed in claim 1, further comprising obtaining said plurality of parent ion data sets and said plurality of corresponding product ion data sets using retention time alignment. 14. A method as claimed in claim 1, further comprising obtaining said plurality of parent ion data sets and said plurality of corresponding product ion data sets using Data Dependent Acquisition. 15. A method as claimed in claim 1, wherein:
said one or more second product ion data sets comprise product ion data sets acquired at the same time, immediately before or immediately after said first product ion data set; and/or one or more second parent ion data sets comprise parent ion data sets acquired at the same time, immediately before or immediately after said first parent ion data set. 16. (canceled) 17. A method as claimed in claim 1, wherein the step of determining whether, in said first product ion data set, one or more product ions are present that are related to one or more parent ions in said corresponding first parent ion data set comprises determining whether, in said first product ion data set, one or more ions are present that must be related to or that are likely to be related to said one or more parent ions in said corresponding first parent ion data set. 18. A method as claimed in claim 1, wherein the step of determining whether, in said first product ion data set, one or more product ions are present that are related to one or more parent ions in said corresponding first parent ion data set comprises determining whether one or more anchor ions are present in said corresponding first product ion data set. 19. A method as claimed in claim 1, wherein the step of determining whether, in said first product ion data set, one or more product ions are present that are related to one or more parent ions in said corresponding first parent ion data set comprises determining whether: (i) one or more unfragmented parent ions; (ii) one or more neutral loss ions; (iii) one or more complementary product ion pairs; (iv) one or more extended complementary product ion pairs; (v) one or more charge replicates; and/or (vi) one or more in-source replicate ions; are present in said first product ion data set. 20. A method as claimed in claim 1, further comprising determining whether, in said first product ion data set, one or more additional product ions are present that are related to said one or more parent ions in said corresponding first parent ion data set by identifying ions in said first product ion data set that have a mass or mass to charge ratio value differing from the mass or mass to charge ratio value of said one or more product ions by an amount substantially equal to the mass or mass to charge ratio of one or more known fragmentation subunits. 21. A method as claimed in claim 1, further comprising identifying one or more virtual anchor ions for said first product ion data set. 22-26. (canceled) 27. A method as claimed in claim 1, further comprising removing, from said first product ion data set, ions that cannot be related to said one or more parent ions in said corresponding first parent ion data set to produce said a first modified product ion data set. 28. A method as claimed in claim 1, further comprising:
removing said one or more parent ions from said first parent ion data set and/or from one or more second parent ion data sets; or removing ions other than said one or more parent ions from said first parent ion data set and/or from one or more second parent ion data sets. 29. A method as claimed in claim 1, wherein:
said first parent ion data set is attributed to one or more first parent ions; and one or more second parent ion data sets are attributed to one or more second, different parent ions. 30. A method as claimed in claim 1, further comprising:
determining whether, in said first product ion data set, one or more ions are present that have an intensity greater than or less than a portion of the intensity of said one or more parent ions in said corresponding first parent ion data set; and if it is determined that said one or more ions are present, removing said one or more ions from said first product ion data set to produce said a first modified product ion data set. 31. A method as claimed in claim 1, further comprising:
submitting said one or more data sets to a search engine to determine the composition of said eluent. 32-33. (canceled) 34. A mass spectrometer comprising:
a chromatography device and a mass analyser; and a control system arranged and adapted: (i) to cause said mass spectrometer to mass analyse an eluent from said chromatography device and to obtain a plurality of parent ion data sets and a plurality of corresponding product ion data sets; and (ii) to determine whether, in a first product ion data set of said plurality of product ion data sets, one or more product ions are present that are related to one or more parent ions in a corresponding first parent ion data set of said plurality of parent ion data sets based on the masses or mass to charge ratios and/or intensities of said one or more product ions and said one or more parent ions; wherein if it is determined that said one or more product ions are present, said control system is further arranged and adapted to remove said one or more product ions from one or more second product ion data sets of said plurality of product ion data sets to produce one or more second modified product ion data sets. 35-41. (canceled) | A method of mass spectrometry is disclosed comprising mass analysing an eluent from a chromatography device and obtaining parent ion data sets and corresponding product ion data sets, and determining whether, in a first product ion data set, one or more product ions are present that are related to one or more parent ions in a corresponding first parent ion data set, based on the mass or mass to charge ratio and/or intensity of the one or more product ions and the one or more parent ions. If it is determined that the one or more product ions are present, the method further comprises removing the one or more product ions from one or more second product ion data sets to produce one or more second modified product ion data sets and/or removing ions other than the one or more product ions from the first product ion data set to produce a first modified product ion data set.1. A method of mass spectrometry comprising:
mass analysing an eluent from a chromatography device and obtaining a plurality of parent ion data sets and a plurality of corresponding product ion data sets; and determining whether, in a first product ion data set of said plurality of product ions data sets, one or more product ions are present that are related to one or more parent ions in a corresponding first parent ion data set of said plurality of parent ion data sets, based on the masses or mass to charge ratios and/or intensities of said one or more product ions and said one or more parent ions; wherein if it is determined that said one or more product ions are present, the method further comprises removing said one or more product ions from one or more second product ion data sets of said plurality of product ion data sets to produce one or more second modified product ion data sets. 2. A method as claimed in claim 1, wherein if it is determined that said one or more product ions are present, the method further comprises removing ions other than said one or more product ions from said first product ion data set to produce a first modified product ion data set. 3. A method of mass spectrometry comprising:
mass analysing an eluent from a chromatography device and obtaining one or more parent ion data sets and one or more corresponding product ion data sets; and determining whether, in a first product ion data set of said one or more product ion data sets, one or more product ions are present that are related to one or more parent ions in a corresponding first parent ion data set of said one or more parent ion data sets, based on the masses or mass to charge ratios and/or intensities of said one or more product ions and said one or more parent ions; wherein if it is determined that said one or more product ions are present, the method further comprises removing ions other than said one or more product ions from said first product ion data set to produce a first modified product ion data set. 4-5. (canceled) 6. A method as claimed claim in claim 1, wherein mass analysing said eluent comprises ionising said eluent to produce a plurality of ions and mass analysing said plurality of ions to obtain said one or more parent ion data sets. 7. (canceled) 8. A method as claimed claim 1, wherein mass analysing said eluent comprises ionising said eluent to produce a plurality of ions, fragmenting or reacting said plurality of ions in a fragmentation, collision or reaction device to produce a plurality of product ions, and mass analysing said plurality of product ions to obtain said one or more product ion data sets. 9-10. (canceled) 11. A method as claimed in claim 1, wherein mass analysing said eluent comprises ionising said eluent to produce a plurality of ions and the method further comprising comprises:
separating said plurality of ions according to their ion mobility; obtaining said plurality of parent ion data sets and said plurality of corresponding product ion data sets using ion mobility drift alignment. 12. (canceled) 13. A method as claimed in claim 1, further comprising obtaining said plurality of parent ion data sets and said plurality of corresponding product ion data sets using retention time alignment. 14. A method as claimed in claim 1, further comprising obtaining said plurality of parent ion data sets and said plurality of corresponding product ion data sets using Data Dependent Acquisition. 15. A method as claimed in claim 1, wherein:
said one or more second product ion data sets comprise product ion data sets acquired at the same time, immediately before or immediately after said first product ion data set; and/or one or more second parent ion data sets comprise parent ion data sets acquired at the same time, immediately before or immediately after said first parent ion data set. 16. (canceled) 17. A method as claimed in claim 1, wherein the step of determining whether, in said first product ion data set, one or more product ions are present that are related to one or more parent ions in said corresponding first parent ion data set comprises determining whether, in said first product ion data set, one or more ions are present that must be related to or that are likely to be related to said one or more parent ions in said corresponding first parent ion data set. 18. A method as claimed in claim 1, wherein the step of determining whether, in said first product ion data set, one or more product ions are present that are related to one or more parent ions in said corresponding first parent ion data set comprises determining whether one or more anchor ions are present in said corresponding first product ion data set. 19. A method as claimed in claim 1, wherein the step of determining whether, in said first product ion data set, one or more product ions are present that are related to one or more parent ions in said corresponding first parent ion data set comprises determining whether: (i) one or more unfragmented parent ions; (ii) one or more neutral loss ions; (iii) one or more complementary product ion pairs; (iv) one or more extended complementary product ion pairs; (v) one or more charge replicates; and/or (vi) one or more in-source replicate ions; are present in said first product ion data set. 20. A method as claimed in claim 1, further comprising determining whether, in said first product ion data set, one or more additional product ions are present that are related to said one or more parent ions in said corresponding first parent ion data set by identifying ions in said first product ion data set that have a mass or mass to charge ratio value differing from the mass or mass to charge ratio value of said one or more product ions by an amount substantially equal to the mass or mass to charge ratio of one or more known fragmentation subunits. 21. A method as claimed in claim 1, further comprising identifying one or more virtual anchor ions for said first product ion data set. 22-26. (canceled) 27. A method as claimed in claim 1, further comprising removing, from said first product ion data set, ions that cannot be related to said one or more parent ions in said corresponding first parent ion data set to produce said a first modified product ion data set. 28. A method as claimed in claim 1, further comprising:
removing said one or more parent ions from said first parent ion data set and/or from one or more second parent ion data sets; or removing ions other than said one or more parent ions from said first parent ion data set and/or from one or more second parent ion data sets. 29. A method as claimed in claim 1, wherein:
said first parent ion data set is attributed to one or more first parent ions; and one or more second parent ion data sets are attributed to one or more second, different parent ions. 30. A method as claimed in claim 1, further comprising:
determining whether, in said first product ion data set, one or more ions are present that have an intensity greater than or less than a portion of the intensity of said one or more parent ions in said corresponding first parent ion data set; and if it is determined that said one or more ions are present, removing said one or more ions from said first product ion data set to produce said a first modified product ion data set. 31. A method as claimed in claim 1, further comprising:
submitting said one or more data sets to a search engine to determine the composition of said eluent. 32-33. (canceled) 34. A mass spectrometer comprising:
a chromatography device and a mass analyser; and a control system arranged and adapted: (i) to cause said mass spectrometer to mass analyse an eluent from said chromatography device and to obtain a plurality of parent ion data sets and a plurality of corresponding product ion data sets; and (ii) to determine whether, in a first product ion data set of said plurality of product ion data sets, one or more product ions are present that are related to one or more parent ions in a corresponding first parent ion data set of said plurality of parent ion data sets based on the masses or mass to charge ratios and/or intensities of said one or more product ions and said one or more parent ions; wherein if it is determined that said one or more product ions are present, said control system is further arranged and adapted to remove said one or more product ions from one or more second product ion data sets of said plurality of product ion data sets to produce one or more second modified product ion data sets. 35-41. (canceled) | 2,800 |
12,115 | 12,115 | 15,932,286 | 2,813 | The disclosure relates to chips scale packages and methods of forming such packages or an array of such packages. The semiconductor chip scale package comprises: a semiconductor die, comprising: a first major surface opposing a second major surface; a plurality side walls extending between the first major surface and the second major surface; a plurality of electrical contacts arranged on the second major surface of the semiconductor die; and an inorganic insulating material arranged on the plurality of side walls and on the first major surface. | 1. A semiconductor chip scale package comprising:
a semiconductor die, the semiconductor die comprising: a first major surface opposing a second major surface; a plurality side walls extending between the first major surface and the second major surface; a plurality of electrical contacts arranged on the second major surface of the semiconductor die; and an inorganic insulating material arranged on the plurality of side walls and on the first major surface. 2. The semiconductor chip scale package of claim 1, wherein the insulating material comprises a metal oxide material. 3. The semiconductor chip scale package of claim 2, wherein the insulating material comprises an aluminium oxide, such as Al2O3. 4. The semiconductor chip scale package of claim 2, wherein the insulating material comprises an Al2O3 layer and a TiO2 layer. 5. The semiconductor chip scale package according to claim 4, wherein the insulating material comprises an alternating arrangement of Al2O3 layers and TiO2 layers. 6. The semiconductor chip scale package of claim 1, wherein the inorganic insulating material is arranged on the second major surface such that the electrical contacts are free of insulating material. 7. The semiconductor chip scale package of claim 1, wherein the second major surface is free of insulating material. 8. The semiconductor chip scale package of claim 1, wherein a thickness of the insulating material is proportional to an operating voltage of the semiconductor die. 9. The semiconductor chip scale package of claim 1, wherein the insulating material is formed as a conformal layer on the semiconductor die by atomic layer deposition or low temperature PECVD. 10. An array of semiconductor chip scale packages of claim 1, comprising a plurality of chip scale packages formed on a carrier, wherein the electrical contacts are in contact with the carrier. 11. A method of forming an array of chip scale packages, the method comprising:
mounting a semiconductor wafer on a carrier; and singulating the semiconductor wafer to form a plurality semiconductor dies, wherein each of said plurality of singulated semiconductor dies comprises:
a first major surface opposing a second major surface; a plurality side walls extending between the first major surface and the second major surface;
a plurality of electrical contacts arranged on the second major surface of the semiconductor die; and
an inorganic insulating material arranged on the plurality of side walls and on the first major surface. 12. The method of forming an array of chip scale packages of claim 11, wherein the insulating material comprises a metal oxide material. 13. The method of forming an array of chip scale packages of claim 12, wherein the insulating material comprises an aluminium oxide. 14. The method of forming an array of chip scale packages of claim 12, wherein the insulating material comprises an Al2O3 layer and a TiO2 layer. 15. The method of forming an array of chip scale packages according to of claim 10, wherein the insulating material is formed as a conformal layer on the semiconductor die by atomic layer deposition or low temperature PECVD. | The disclosure relates to chips scale packages and methods of forming such packages or an array of such packages. The semiconductor chip scale package comprises: a semiconductor die, comprising: a first major surface opposing a second major surface; a plurality side walls extending between the first major surface and the second major surface; a plurality of electrical contacts arranged on the second major surface of the semiconductor die; and an inorganic insulating material arranged on the plurality of side walls and on the first major surface.1. A semiconductor chip scale package comprising:
a semiconductor die, the semiconductor die comprising: a first major surface opposing a second major surface; a plurality side walls extending between the first major surface and the second major surface; a plurality of electrical contacts arranged on the second major surface of the semiconductor die; and an inorganic insulating material arranged on the plurality of side walls and on the first major surface. 2. The semiconductor chip scale package of claim 1, wherein the insulating material comprises a metal oxide material. 3. The semiconductor chip scale package of claim 2, wherein the insulating material comprises an aluminium oxide, such as Al2O3. 4. The semiconductor chip scale package of claim 2, wherein the insulating material comprises an Al2O3 layer and a TiO2 layer. 5. The semiconductor chip scale package according to claim 4, wherein the insulating material comprises an alternating arrangement of Al2O3 layers and TiO2 layers. 6. The semiconductor chip scale package of claim 1, wherein the inorganic insulating material is arranged on the second major surface such that the electrical contacts are free of insulating material. 7. The semiconductor chip scale package of claim 1, wherein the second major surface is free of insulating material. 8. The semiconductor chip scale package of claim 1, wherein a thickness of the insulating material is proportional to an operating voltage of the semiconductor die. 9. The semiconductor chip scale package of claim 1, wherein the insulating material is formed as a conformal layer on the semiconductor die by atomic layer deposition or low temperature PECVD. 10. An array of semiconductor chip scale packages of claim 1, comprising a plurality of chip scale packages formed on a carrier, wherein the electrical contacts are in contact with the carrier. 11. A method of forming an array of chip scale packages, the method comprising:
mounting a semiconductor wafer on a carrier; and singulating the semiconductor wafer to form a plurality semiconductor dies, wherein each of said plurality of singulated semiconductor dies comprises:
a first major surface opposing a second major surface; a plurality side walls extending between the first major surface and the second major surface;
a plurality of electrical contacts arranged on the second major surface of the semiconductor die; and
an inorganic insulating material arranged on the plurality of side walls and on the first major surface. 12. The method of forming an array of chip scale packages of claim 11, wherein the insulating material comprises a metal oxide material. 13. The method of forming an array of chip scale packages of claim 12, wherein the insulating material comprises an aluminium oxide. 14. The method of forming an array of chip scale packages of claim 12, wherein the insulating material comprises an Al2O3 layer and a TiO2 layer. 15. The method of forming an array of chip scale packages according to of claim 10, wherein the insulating material is formed as a conformal layer on the semiconductor die by atomic layer deposition or low temperature PECVD. | 2,800 |
12,116 | 12,116 | 15,708,553 | 2,865 | Disclosed examples include methods and systems to measure fluid flow, including a transmit circuit to provide a transducer transmit signal based on a transmit pulse signal, a receive circuit to receive a transducer receive signal, an ADC to sample a receive signal from the receive circuit and provide a sampled signal, and a processing circuit that computes a transit time based on the sampled signal, and provides the transmit pulse signal including a first portion with a frequency in a first frequency band, and a second portion with a second frequency outside the first frequency band to mitigate undesired transducer vibration, where the second frequency is outside a transducer frequency bandwidth of the transducer. | 1. A system to measure fluid flow, comprising:
first and second transducers spaced from one another to transmit and receive ultrasonic signals in a pipe, the first transducer including a first electrical terminal, and the second transducer including a second electrical terminal, the first transducer having a transducer frequency bandwidth for which a transducer response is within a non-zero predetermined value of a peak transducer response; a transmit circuit, including a transmit circuit output to provide a transducer transmit signal to the first electrical terminal based on a transmit pulse signal; a receive circuit, including a receive circuit input to receive a transducer receive signal from the second electrical terminal; an analog-to-digital converter (ADC) arranged to sample a receive signal from the receive circuit and provide a sampled signal; and a processing circuit, including an output to provide the transmit pulse signal to the transmit circuit, the transmit pulse signal including a first portion with a frequency in a first frequency band, and a second portion with a second frequency outside the first frequency band, the processing circuit configured to compute a transit time of ultrasonic signals travelling between the first and second transducers based on the sampled signal, the second frequency being outside the transducer frequency bandwidth. 2. The system of claim 1, further comprising a switching circuit operative in a first state to connect the transmit circuit output to the first electrical terminal of the first transducer, and to connect the receive circuit input to the second electrical terminal of the second transducer, the switching circuit operative in a different second state to connect the transmit circuit output to the second electrical terminal of the second transducer, and to connect the receive circuit input to the first electrical terminal of the first transducer. 3. The system of claim 2, wherein the frequency of the first portion ramps up from a start frequency in the first frequency band to a higher end frequency in the first frequency band, and wherein the second frequency of the second portion is different from the end frequency. 4. The system of claim 3, wherein the second frequency is greater than the end frequency. 5. The system of claim 4, wherein the second frequency of the second portion is constant. 6. The system of claim 3, wherein the first portion has a duration greater than twice a duration of the second portion. 7. The system of claim 1, wherein the non-zero predetermined value is 10 dB. 8. The system of claim 1, wherein the frequency of the first portion ramps up from a start frequency in the first frequency band to a higher end frequency in the first frequency band, and wherein the second frequency of the second portion is different from the end frequency. 9. The system of claim 1, wherein the first portion has a duration greater than twice a duration of the second portion. 10. The system of claim 1, wherein the second frequency of the second portion is constant. 11. The system of claim 1, wherein the frequency of the first portion is constant. 12. A flow sensor interface circuit, comprising:
a transmit circuit, including a transmit circuit output to provide a transducer transmit signal to a connected transmit transducer based on a transmit pulse signal; a receive circuit, including a receive circuit input to receive a transducer receive signal; an analog-to-digital converter (ADC) configured to sample a receive signal from the receive circuit, and to provide a sampled signal based on the receive signal; and a processing circuit, including an output to provide the transmit pulse signal to the transmit circuit, the transmit pulse signal including a first portion with a frequency in a first frequency band, and a second portion with a second frequency outside the first frequency band, the second frequency being outside a transducer frequency bandwidth of the transmit transducer. 13. The flow sensor interface circuit of claim 12, further comprising a switching circuit operative in a first state to connect the transmit circuit output to a first transducer, and to connect the receive circuit input to a second transducer, the switching circuit operative in a different second state to connect the transmit circuit output to the second transducer, and to connect the receive circuit input to the first transducer. 14. The flow sensor interface circuit of claim 12, wherein the frequency of the first portion ramps up from a start frequency in the first frequency band to a higher end frequency in the first frequency band, and wherein the second frequency of the second portion is different from the end frequency. 15. The flow sensor interface circuit of claim 14, wherein the second frequency is greater than the end frequency. 16. The flow sensor interface circuit of claim 12, wherein the first portion has a duration greater than twice a duration of the second portion. 17. A method to measure fluid flow in a pipe, comprising:
providing a first transducer transmit signal to a first transducer, the first transducer transmit signal including a first portion with a frequency in a first frequency band, and a second portion with a second frequency outside the first frequency band, the second frequency being outside a transducer frequency bandwidth of the first transducer; sampling a first transducer receive signal from a second transducer to generate a first sampled signal; computing a first transit time representing transit of ultrasonic signals from the first transducer to the second transducer based on the first sampled signal; providing a second transducer transmit signal to the second transducer, the second transducer transmit signal including the first portion with the frequency in the first frequency band, and the second portion with the second frequency outside the first frequency band; sampling a second transducer receive signal from the first transducer to generate a second sampled signal; computing a second transit time representing transit of ultrasonic signals from the second transducer to the first transducer based on the second sampled signal; and computing a velocity of fluid flow in the pipe based on the first and second transit times. 18. The method of claim 17, wherein the frequency of the first portion ramps up from a start frequency in the first frequency band to a higher end frequency in the first frequency band, and wherein the second frequency of the second portion is different from the end frequency. 19. The method of claim 18, wherein the second frequency is greater than the end frequency. 20. The method of claim 17, wherein the first portion has a duration greater than twice a duration of the second portion. | Disclosed examples include methods and systems to measure fluid flow, including a transmit circuit to provide a transducer transmit signal based on a transmit pulse signal, a receive circuit to receive a transducer receive signal, an ADC to sample a receive signal from the receive circuit and provide a sampled signal, and a processing circuit that computes a transit time based on the sampled signal, and provides the transmit pulse signal including a first portion with a frequency in a first frequency band, and a second portion with a second frequency outside the first frequency band to mitigate undesired transducer vibration, where the second frequency is outside a transducer frequency bandwidth of the transducer.1. A system to measure fluid flow, comprising:
first and second transducers spaced from one another to transmit and receive ultrasonic signals in a pipe, the first transducer including a first electrical terminal, and the second transducer including a second electrical terminal, the first transducer having a transducer frequency bandwidth for which a transducer response is within a non-zero predetermined value of a peak transducer response; a transmit circuit, including a transmit circuit output to provide a transducer transmit signal to the first electrical terminal based on a transmit pulse signal; a receive circuit, including a receive circuit input to receive a transducer receive signal from the second electrical terminal; an analog-to-digital converter (ADC) arranged to sample a receive signal from the receive circuit and provide a sampled signal; and a processing circuit, including an output to provide the transmit pulse signal to the transmit circuit, the transmit pulse signal including a first portion with a frequency in a first frequency band, and a second portion with a second frequency outside the first frequency band, the processing circuit configured to compute a transit time of ultrasonic signals travelling between the first and second transducers based on the sampled signal, the second frequency being outside the transducer frequency bandwidth. 2. The system of claim 1, further comprising a switching circuit operative in a first state to connect the transmit circuit output to the first electrical terminal of the first transducer, and to connect the receive circuit input to the second electrical terminal of the second transducer, the switching circuit operative in a different second state to connect the transmit circuit output to the second electrical terminal of the second transducer, and to connect the receive circuit input to the first electrical terminal of the first transducer. 3. The system of claim 2, wherein the frequency of the first portion ramps up from a start frequency in the first frequency band to a higher end frequency in the first frequency band, and wherein the second frequency of the second portion is different from the end frequency. 4. The system of claim 3, wherein the second frequency is greater than the end frequency. 5. The system of claim 4, wherein the second frequency of the second portion is constant. 6. The system of claim 3, wherein the first portion has a duration greater than twice a duration of the second portion. 7. The system of claim 1, wherein the non-zero predetermined value is 10 dB. 8. The system of claim 1, wherein the frequency of the first portion ramps up from a start frequency in the first frequency band to a higher end frequency in the first frequency band, and wherein the second frequency of the second portion is different from the end frequency. 9. The system of claim 1, wherein the first portion has a duration greater than twice a duration of the second portion. 10. The system of claim 1, wherein the second frequency of the second portion is constant. 11. The system of claim 1, wherein the frequency of the first portion is constant. 12. A flow sensor interface circuit, comprising:
a transmit circuit, including a transmit circuit output to provide a transducer transmit signal to a connected transmit transducer based on a transmit pulse signal; a receive circuit, including a receive circuit input to receive a transducer receive signal; an analog-to-digital converter (ADC) configured to sample a receive signal from the receive circuit, and to provide a sampled signal based on the receive signal; and a processing circuit, including an output to provide the transmit pulse signal to the transmit circuit, the transmit pulse signal including a first portion with a frequency in a first frequency band, and a second portion with a second frequency outside the first frequency band, the second frequency being outside a transducer frequency bandwidth of the transmit transducer. 13. The flow sensor interface circuit of claim 12, further comprising a switching circuit operative in a first state to connect the transmit circuit output to a first transducer, and to connect the receive circuit input to a second transducer, the switching circuit operative in a different second state to connect the transmit circuit output to the second transducer, and to connect the receive circuit input to the first transducer. 14. The flow sensor interface circuit of claim 12, wherein the frequency of the first portion ramps up from a start frequency in the first frequency band to a higher end frequency in the first frequency band, and wherein the second frequency of the second portion is different from the end frequency. 15. The flow sensor interface circuit of claim 14, wherein the second frequency is greater than the end frequency. 16. The flow sensor interface circuit of claim 12, wherein the first portion has a duration greater than twice a duration of the second portion. 17. A method to measure fluid flow in a pipe, comprising:
providing a first transducer transmit signal to a first transducer, the first transducer transmit signal including a first portion with a frequency in a first frequency band, and a second portion with a second frequency outside the first frequency band, the second frequency being outside a transducer frequency bandwidth of the first transducer; sampling a first transducer receive signal from a second transducer to generate a first sampled signal; computing a first transit time representing transit of ultrasonic signals from the first transducer to the second transducer based on the first sampled signal; providing a second transducer transmit signal to the second transducer, the second transducer transmit signal including the first portion with the frequency in the first frequency band, and the second portion with the second frequency outside the first frequency band; sampling a second transducer receive signal from the first transducer to generate a second sampled signal; computing a second transit time representing transit of ultrasonic signals from the second transducer to the first transducer based on the second sampled signal; and computing a velocity of fluid flow in the pipe based on the first and second transit times. 18. The method of claim 17, wherein the frequency of the first portion ramps up from a start frequency in the first frequency band to a higher end frequency in the first frequency band, and wherein the second frequency of the second portion is different from the end frequency. 19. The method of claim 18, wherein the second frequency is greater than the end frequency. 20. The method of claim 17, wherein the first portion has a duration greater than twice a duration of the second portion. | 2,800 |
12,117 | 12,117 | 15,210,333 | 2,864 | Methods of combining mineral composition and laboratory test results for reservoir rock samples to predict future responses to secondary and tertiary oil recovery treatments are disclosed. Particular, SEM and EDS will be combined to produce a mineral map, including mineral distribution around the rock's pore space, for comparison with laboratory data to predict and/or interpret how certain mineral distributions will respond to various fluid-rock interactions. | 1) A method of predicting fluid-rock interactions for reservoir rock, comprising:
a) obtaining a reservoir rock sample; b) obtaining scanning electron microscopy (SEM) image data in back-scattered electron (BSE) mode and energy dispersive spectral (EDS) data of said reservoir rock sample; c) assigning chemical mineralogy of each pixel using the EDS spectra compared to mineral standards; d) generating a mineral map by combining said SEM image data and said EDS-based mineral assignments on an individual pixel basis; e) determining a spatial profile of chemical analysis-based mineralogy of one or more pore walls in said reservoir rock sample; f) evaluating said reservoir rock sample's response to one or more enhanced oil recovery (EOR) tests, wherein said one or more EOR test focuses on interactions between a fluid and said reservoir rock sample; g) comparing said spatial profile with results from said evaluating step e) to identify the composition of one or more critical region of pore walls; and, h) predicting fluid-rock interactions for reservoir rocks having the same critical region of pore walls composition as said reservoir rock sample based on the results of step f and g. 2) The method of claim 1), wherein said EOR test is a secondary recovery test. 3) The method of claim 1), wherein said EOR test is a tertiary recovery test. 4) The method of claim 1), wherein said spatial profile includes chemical mineralogy of the interface between solid mineral grains and void space that defines a pore in said pore walls. 5) The method of claim 1), wherein said response can be wettability distribution, formation damage, electrical conductivity, permeability, and other single or multiple fluid phase transport properties. 6) A method of correlating mineral composition of a reservoir rock at a pore-wall interface with fluid interactions, comprising:
a) obtaining a reservoir rock sample; b) obtaining SEM image data in a BSE mode; c) obtaining EDS spectral data of said reservoir rock sample; d) assigning chemical mineralogy of each pixel using the EDS spectra compared to mineral standards; e) generating a mineral map by combining said SEM image data and said EDS-based mineral assignments on an individual pixel basis; f) determining a spatial profile of chemical-analysis based mineralogy of one or more pore walls in said reservoir rock sample; g) evaluating said reservoir rock sample's response to an EOR test, wherein said EOR test focuses on interactions between a fluid and said reservoir rock sample; h) comparing said spatial profile with results from said evaluating step g) to identify a composition of one or more critical region of pore walls; and, i) correlating said pore mineral composition to said critical region. 7) The method of claim 6), wherein said EOR test is a secondary recovery test. 8) The method of claim 6), wherein said EOR test is a tertiary recovery test. 9) The method of claim 6), wherein said spatial profile includes chemical mineralogy of interface between solid mineral grains and void space that defines the pore in said pore walls. 10) A method for predicting flow distribution in a reservoir rock comprising:
a) obtaining SEM image data in a BSE mode and obtaining EDS spectral data of a reservoir rock sample; b) generating a mineral map by combining said SEM image data and said EDS spectral data on an individual pixel basis; c) assigning a chemical mineralogy of each pixel in said mineral map; d) determining a spatial profile of chemical mineralogy of one or more pore walls in said reservoir rock sample; e) evaluating said reservoir rock sample's response to an EOR process, wherein said one or more EOR process focuses on interactions between a fluid and said reservoir rock sample; f) comparing said spatial profile with results from said evaluating step e) to identify the composition of one or more critical region of pore walls; and, g) predicting flow distribution for reservoir rocks having the same critical region of pore walls composition as said reservoir rock sample. 11) A method for predicting reservoir wettability, the method comprising
a) obtaining SEM image data in BSE mode and EDS spectral data of a reservoir rock sample; b) generating a mineral map by combining said SEM image data and said EDS spectral data on an individual pixel basis; c) assigning a chemical mineralogy of each pixel in said mineral map; d) determining a spatial profile of chemical mineralogy of one or more pore walls in said reservoir rock sample; e) evaluating said reservoir rock sample's response to one or more wettability laboratory tests; f) comparing said spatial profile with results from said evaluating step e) to identify the composition of one or more critical region of pore walls; and, g) predicting reservoir wettability for reservoir rocks having the same critical region of pore walls composition as said reservoir rock sample based on said reservoir rock sample's response to one or more wettability laboratory tests. 12) A method for forecasting an enhanced oil recovery process for a reservoir comprising:
a) acquiring a reservoir rock sample from a reservoir of interest; b) obtaining SEM image data in BSE mode and EDS spectral data of said reservoir rock sample; c) generating a mineral map by combining said SEM image data and said EDS spectral data on an individual pixel basis; d) assigning a chemical mineralogy of each pixel in said mineral map; e) determining a spatial profile of chemical mineralogy of one or more pore walls in said reservoir rock sample; f) evaluating said reservoir rock sample's response to one or more EOR laboratory tests on said reservoir rock sample; g) comparing said spatial profile with results from said evaluating step e) to identify the composition of one or more critical region of pore walls; and, h) forecasting enhanced oil recovery for one or more regions in said reservoir of interest having the same critical region of pore walls composition as said reservoir rock sample based on said response in step f. | Methods of combining mineral composition and laboratory test results for reservoir rock samples to predict future responses to secondary and tertiary oil recovery treatments are disclosed. Particular, SEM and EDS will be combined to produce a mineral map, including mineral distribution around the rock's pore space, for comparison with laboratory data to predict and/or interpret how certain mineral distributions will respond to various fluid-rock interactions.1) A method of predicting fluid-rock interactions for reservoir rock, comprising:
a) obtaining a reservoir rock sample; b) obtaining scanning electron microscopy (SEM) image data in back-scattered electron (BSE) mode and energy dispersive spectral (EDS) data of said reservoir rock sample; c) assigning chemical mineralogy of each pixel using the EDS spectra compared to mineral standards; d) generating a mineral map by combining said SEM image data and said EDS-based mineral assignments on an individual pixel basis; e) determining a spatial profile of chemical analysis-based mineralogy of one or more pore walls in said reservoir rock sample; f) evaluating said reservoir rock sample's response to one or more enhanced oil recovery (EOR) tests, wherein said one or more EOR test focuses on interactions between a fluid and said reservoir rock sample; g) comparing said spatial profile with results from said evaluating step e) to identify the composition of one or more critical region of pore walls; and, h) predicting fluid-rock interactions for reservoir rocks having the same critical region of pore walls composition as said reservoir rock sample based on the results of step f and g. 2) The method of claim 1), wherein said EOR test is a secondary recovery test. 3) The method of claim 1), wherein said EOR test is a tertiary recovery test. 4) The method of claim 1), wherein said spatial profile includes chemical mineralogy of the interface between solid mineral grains and void space that defines a pore in said pore walls. 5) The method of claim 1), wherein said response can be wettability distribution, formation damage, electrical conductivity, permeability, and other single or multiple fluid phase transport properties. 6) A method of correlating mineral composition of a reservoir rock at a pore-wall interface with fluid interactions, comprising:
a) obtaining a reservoir rock sample; b) obtaining SEM image data in a BSE mode; c) obtaining EDS spectral data of said reservoir rock sample; d) assigning chemical mineralogy of each pixel using the EDS spectra compared to mineral standards; e) generating a mineral map by combining said SEM image data and said EDS-based mineral assignments on an individual pixel basis; f) determining a spatial profile of chemical-analysis based mineralogy of one or more pore walls in said reservoir rock sample; g) evaluating said reservoir rock sample's response to an EOR test, wherein said EOR test focuses on interactions between a fluid and said reservoir rock sample; h) comparing said spatial profile with results from said evaluating step g) to identify a composition of one or more critical region of pore walls; and, i) correlating said pore mineral composition to said critical region. 7) The method of claim 6), wherein said EOR test is a secondary recovery test. 8) The method of claim 6), wherein said EOR test is a tertiary recovery test. 9) The method of claim 6), wherein said spatial profile includes chemical mineralogy of interface between solid mineral grains and void space that defines the pore in said pore walls. 10) A method for predicting flow distribution in a reservoir rock comprising:
a) obtaining SEM image data in a BSE mode and obtaining EDS spectral data of a reservoir rock sample; b) generating a mineral map by combining said SEM image data and said EDS spectral data on an individual pixel basis; c) assigning a chemical mineralogy of each pixel in said mineral map; d) determining a spatial profile of chemical mineralogy of one or more pore walls in said reservoir rock sample; e) evaluating said reservoir rock sample's response to an EOR process, wherein said one or more EOR process focuses on interactions between a fluid and said reservoir rock sample; f) comparing said spatial profile with results from said evaluating step e) to identify the composition of one or more critical region of pore walls; and, g) predicting flow distribution for reservoir rocks having the same critical region of pore walls composition as said reservoir rock sample. 11) A method for predicting reservoir wettability, the method comprising
a) obtaining SEM image data in BSE mode and EDS spectral data of a reservoir rock sample; b) generating a mineral map by combining said SEM image data and said EDS spectral data on an individual pixel basis; c) assigning a chemical mineralogy of each pixel in said mineral map; d) determining a spatial profile of chemical mineralogy of one or more pore walls in said reservoir rock sample; e) evaluating said reservoir rock sample's response to one or more wettability laboratory tests; f) comparing said spatial profile with results from said evaluating step e) to identify the composition of one or more critical region of pore walls; and, g) predicting reservoir wettability for reservoir rocks having the same critical region of pore walls composition as said reservoir rock sample based on said reservoir rock sample's response to one or more wettability laboratory tests. 12) A method for forecasting an enhanced oil recovery process for a reservoir comprising:
a) acquiring a reservoir rock sample from a reservoir of interest; b) obtaining SEM image data in BSE mode and EDS spectral data of said reservoir rock sample; c) generating a mineral map by combining said SEM image data and said EDS spectral data on an individual pixel basis; d) assigning a chemical mineralogy of each pixel in said mineral map; e) determining a spatial profile of chemical mineralogy of one or more pore walls in said reservoir rock sample; f) evaluating said reservoir rock sample's response to one or more EOR laboratory tests on said reservoir rock sample; g) comparing said spatial profile with results from said evaluating step e) to identify the composition of one or more critical region of pore walls; and, h) forecasting enhanced oil recovery for one or more regions in said reservoir of interest having the same critical region of pore walls composition as said reservoir rock sample based on said response in step f. | 2,800 |
12,118 | 12,118 | 15,178,869 | 2,875 | An illumination assembly includes a polymeric substrate, an electrical circuit including two conductors supported by the polymeric substrate, an LED electrically coupled to the two conductors, and a heat spreader thermally coupled to the LED. The two conductors can be printed on the polymeric substrate, embedded within the polymeric substrate, or lie atop the polymeric substrate. The illumination assembly may be fabricated in three-dimensional form factors. | 1. An illumination assembly comprising:
a polymeric substrate; an electrical circuit including two conductors supported by the polymeric substrate; a light source electrically coupled to the two conductors; a heat spreader thermally coupled to the LED light source; and a first polymeric layer comprising a thermoplastic material over-molded around at least portions of the polymeric substrate, the two conductors, the light source, and the heat spreader. 2. The illumination assembly of claim 1 wherein the polymeric substrate defines an aperture and wherein the heat spreader is thermally coupled to the light source through the aperture. 3. (canceled) 4. The illumination assembly of claim 1 wherein the light source is not in direct contact with the heat spreader. 5. The illumination assembly of claim 1 comprising a thermally conductive and electrically insulating material between the light source and the heat spreader. 6. The illumination assembly of claim 1 wherein the two conductors are one of printed on the first polymeric substrate and at least partially embedded within the first polymeric substrate. 7. An illumination assembly comprising:
a polymeric substrate; an electrical circuit including:
a first pair of conductors at least partially embedded within the polymeric substrate; and
a second pair of conductors printed on the polymeric substrate;
a light source electrically coupled to the electrical circuit; a heat spreader thermally coupled to the light source; and a first polymeric layer over-molded around at least portions of the polymeric substrate, the electrical circuit, the lights source, and the heat spreader. 8. The illumination assembly of claim 7 wherein the second pair of conductors is electrically coupled to the first pair of conductors. 9. The illumination assembly of claim 7 wherein the light source is not in direct contact with the heat spreader. 10. The illumination assembly of claim 9 comprising a thermally conductive and electrically insulating material between the light source and the heat spreader. 11. (canceled) 12. The illumination assembly of claim 7 wherein the first polymeric layer forms at least one of a mechanical seal and a moisture seal around the light source, the first pair of conductors, and the second pair of conductors. 13. (canceled) 14. The illumination assembly of claim 7 wherein a first portion of the electrical circuit is disposed in a first plane, and a second portion of the electrical circuit is disposed in a second plane, different than the first plane. 15. The illumination assembly of claim 7 wherein the light source is electrically coupled to the first pair of conductors. 16. A method of forming an illumination assembly comprising:
forming a polymeric substrate having opposing first and second sides; forming an electrical circuit including two conductors supported on the first side of the polymeric substrate; electrically coupling a light source with the two conductors; thermally coupling a heat spreader with the light source, the heat spreader at least primarily disposed on the second side of the polymeric substrate; and over-molding a first polymeric layer over at least portions of the light source, the two conductors, the polymeric substrate, and the heat spreader. 17. (canceled) 18. The method of claim 16 wherein the over-molding of the first polymeric layer forms at least one of a mechanical seal and a moisture seal between the light source, the two conductors, and the polymeric substrate. 19. The method of claim 16 wherein the heat spreader is entirely on the second side of the polymeric substrate, and the light source is not in direct contact with the heat spreader. 20. The method of claim 16 wherein the forming an electrical circuit comprises printing the two conductors onto the first side of the polymeric substrate. | An illumination assembly includes a polymeric substrate, an electrical circuit including two conductors supported by the polymeric substrate, an LED electrically coupled to the two conductors, and a heat spreader thermally coupled to the LED. The two conductors can be printed on the polymeric substrate, embedded within the polymeric substrate, or lie atop the polymeric substrate. The illumination assembly may be fabricated in three-dimensional form factors.1. An illumination assembly comprising:
a polymeric substrate; an electrical circuit including two conductors supported by the polymeric substrate; a light source electrically coupled to the two conductors; a heat spreader thermally coupled to the LED light source; and a first polymeric layer comprising a thermoplastic material over-molded around at least portions of the polymeric substrate, the two conductors, the light source, and the heat spreader. 2. The illumination assembly of claim 1 wherein the polymeric substrate defines an aperture and wherein the heat spreader is thermally coupled to the light source through the aperture. 3. (canceled) 4. The illumination assembly of claim 1 wherein the light source is not in direct contact with the heat spreader. 5. The illumination assembly of claim 1 comprising a thermally conductive and electrically insulating material between the light source and the heat spreader. 6. The illumination assembly of claim 1 wherein the two conductors are one of printed on the first polymeric substrate and at least partially embedded within the first polymeric substrate. 7. An illumination assembly comprising:
a polymeric substrate; an electrical circuit including:
a first pair of conductors at least partially embedded within the polymeric substrate; and
a second pair of conductors printed on the polymeric substrate;
a light source electrically coupled to the electrical circuit; a heat spreader thermally coupled to the light source; and a first polymeric layer over-molded around at least portions of the polymeric substrate, the electrical circuit, the lights source, and the heat spreader. 8. The illumination assembly of claim 7 wherein the second pair of conductors is electrically coupled to the first pair of conductors. 9. The illumination assembly of claim 7 wherein the light source is not in direct contact with the heat spreader. 10. The illumination assembly of claim 9 comprising a thermally conductive and electrically insulating material between the light source and the heat spreader. 11. (canceled) 12. The illumination assembly of claim 7 wherein the first polymeric layer forms at least one of a mechanical seal and a moisture seal around the light source, the first pair of conductors, and the second pair of conductors. 13. (canceled) 14. The illumination assembly of claim 7 wherein a first portion of the electrical circuit is disposed in a first plane, and a second portion of the electrical circuit is disposed in a second plane, different than the first plane. 15. The illumination assembly of claim 7 wherein the light source is electrically coupled to the first pair of conductors. 16. A method of forming an illumination assembly comprising:
forming a polymeric substrate having opposing first and second sides; forming an electrical circuit including two conductors supported on the first side of the polymeric substrate; electrically coupling a light source with the two conductors; thermally coupling a heat spreader with the light source, the heat spreader at least primarily disposed on the second side of the polymeric substrate; and over-molding a first polymeric layer over at least portions of the light source, the two conductors, the polymeric substrate, and the heat spreader. 17. (canceled) 18. The method of claim 16 wherein the over-molding of the first polymeric layer forms at least one of a mechanical seal and a moisture seal between the light source, the two conductors, and the polymeric substrate. 19. The method of claim 16 wherein the heat spreader is entirely on the second side of the polymeric substrate, and the light source is not in direct contact with the heat spreader. 20. The method of claim 16 wherein the forming an electrical circuit comprises printing the two conductors onto the first side of the polymeric substrate. | 2,800 |
12,119 | 12,119 | 15,309,125 | 2,864 | Some aspects of what is described here relate to seismic profiling techniques. A seismic excitation is generated in a first directional section of a first wellbore in a subterranean region. Seismic responses associated with the seismic excitation are detected in directional sections of a plurality of other wellbores in the subterranean region. A fracture treatment of the subterranean region is analyzed based on the seismic responses. In some instances, a multi-dimensional seismic velocity model of the subterranean region is generated based on the seismic responses. | 1. A seismic profiling method comprising:
detecting seismic responses associated with a seismic excitation in a subterranean region, the seismic excitation generated in a first directional section of a first wellbore in the subterranean region, the seismic responses detected at directional sections of a plurality of other wellbores in the subterranean region; and analyzing a fracture treatment of the subterranean region based on the seismic responses. 2. The method of claim 1, wherein the seismic responses are detected by fiber optic distributed acoustic sensing arrays in the directional sections of the other wellbores. 3. The method of claim 2, wherein the first directional section is defined in a reservoir in the subterranean region, and the directional section of at least one of the other wellbores is defined in the reservoir. 4. The method of claim 2, wherein the first directional section is defined in a reservoir in the subterranean region, and the directional section of at least one of the other wellbores is defined in a subsurface layer above or below the reservoir. 5. The method of claim 2, wherein the first directional section is substantially parallel to at least one of the directional sections of the other wellbores. 6. The method of claim 2, further comprising generating the seismic excitations by perforating a wellbore wall in the first directional section. 7. The method of claim 1, wherein the first wellbore comprises a fracture treatment injection wellbore, and the fracture treatment comprises fluid injection through the fracture treatment injection wellbore. 8. The method of claim 1, wherein analyzing the fracture treatment comprises generating a three-dimensional seismic velocity model of the subterranean region based on the seismic responses. 9. The method of claim 1, comprising detecting a time-sequence of seismic responses associated with a time-sequence of seismic excitations in the subterranean region, wherein analyzing the fracture treatment comprises generating a four-dimensional seismic velocity model of the subterranean region based on the seismic responses. 10. The method of claim 9, comprising identifying changes in the subterranean region based on the four-dimensional seismic velocity model, the changes comprising at least one of:
fracture propagation in the subterranean region; movement of fluid in the subterranean region; or geomechanical changes in the subterranean region. 11. The method of claim 1, wherein analyzing the fracture treatment comprises determining geomechanical properties of the subterranean region. 12. The method of claim 1, comprising analyzing the fracture treatment based on the seismic responses in real time during application of the fracture treatment. 13. A seismic profiling system comprising:
a seismic source system comprising a seismic source in a first directional section of a first wellbore in a subterranean region, the seismic source system adapted to generate a seismic excitation in connection with a fracture treatment of the subterranean region; and a seismic sensor system comprising seismic sensors in directional sections of a plurality of other wellbores in the subterranean region, the seismic sensor system adapted to detect seismic responses based on the seismic excitation, each seismic response being detected at a respective one of the other wellbores. 14. The seismic profiling system of claim 13, wherein the seismic source system comprises an array of seismic sources distributed among multiple completion intervals of the first directional section. 15. The seismic profiling system of claim 13, wherein the seismic sensor system comprises a plurality of fiber optic distributed acoustic sensing arrays in the directional sections of the other wellbores. 16. The seismic profiling system of claim 13, further comprising a computing system comprising:
data processing apparatus; and memory storing computer-readable instructions that, when executed by the data processing apparatus, cause the data processing apparatus to perform operations comprising analyzing the fracture treatment based on seismic response data for the seismic responses. 17. The seismic profiling system of claim 16, wherein the first wellbore comprises a fracture treatment injection wellbore, and the fracture treatment is applied through the fracture treatment injection wellbore. 18. A seismic analysis method comprising:
receiving seismic response data for seismic responses associated with a seismic excitation in a subterranean region, the seismic excitation generated in a first directional section of a first wellbore in the subterranean region, the seismic responses detected at directional sections of a plurality of other wellbores in the subterranean region; and analyzing, by operation of a computer system, a fracture treatment of the subterranean region based on the seismic responses. 19. The seismic analysis method of claim 18, wherein the first wellbore comprises a fracture treatment injection wellbore, and the fracture treatment is applied through the fracture treatment injection wellbore. 20. The seismic analysis method of claim 18, wherein analyzing the fracture treatment comprises generating a three-dimensional seismic velocity model based on the seismic data. 21. The seismic analysis method of claim 18, wherein analyzing the fracture treatment comprises computing geomechanical properties of the subterranean region. | Some aspects of what is described here relate to seismic profiling techniques. A seismic excitation is generated in a first directional section of a first wellbore in a subterranean region. Seismic responses associated with the seismic excitation are detected in directional sections of a plurality of other wellbores in the subterranean region. A fracture treatment of the subterranean region is analyzed based on the seismic responses. In some instances, a multi-dimensional seismic velocity model of the subterranean region is generated based on the seismic responses.1. A seismic profiling method comprising:
detecting seismic responses associated with a seismic excitation in a subterranean region, the seismic excitation generated in a first directional section of a first wellbore in the subterranean region, the seismic responses detected at directional sections of a plurality of other wellbores in the subterranean region; and analyzing a fracture treatment of the subterranean region based on the seismic responses. 2. The method of claim 1, wherein the seismic responses are detected by fiber optic distributed acoustic sensing arrays in the directional sections of the other wellbores. 3. The method of claim 2, wherein the first directional section is defined in a reservoir in the subterranean region, and the directional section of at least one of the other wellbores is defined in the reservoir. 4. The method of claim 2, wherein the first directional section is defined in a reservoir in the subterranean region, and the directional section of at least one of the other wellbores is defined in a subsurface layer above or below the reservoir. 5. The method of claim 2, wherein the first directional section is substantially parallel to at least one of the directional sections of the other wellbores. 6. The method of claim 2, further comprising generating the seismic excitations by perforating a wellbore wall in the first directional section. 7. The method of claim 1, wherein the first wellbore comprises a fracture treatment injection wellbore, and the fracture treatment comprises fluid injection through the fracture treatment injection wellbore. 8. The method of claim 1, wherein analyzing the fracture treatment comprises generating a three-dimensional seismic velocity model of the subterranean region based on the seismic responses. 9. The method of claim 1, comprising detecting a time-sequence of seismic responses associated with a time-sequence of seismic excitations in the subterranean region, wherein analyzing the fracture treatment comprises generating a four-dimensional seismic velocity model of the subterranean region based on the seismic responses. 10. The method of claim 9, comprising identifying changes in the subterranean region based on the four-dimensional seismic velocity model, the changes comprising at least one of:
fracture propagation in the subterranean region; movement of fluid in the subterranean region; or geomechanical changes in the subterranean region. 11. The method of claim 1, wherein analyzing the fracture treatment comprises determining geomechanical properties of the subterranean region. 12. The method of claim 1, comprising analyzing the fracture treatment based on the seismic responses in real time during application of the fracture treatment. 13. A seismic profiling system comprising:
a seismic source system comprising a seismic source in a first directional section of a first wellbore in a subterranean region, the seismic source system adapted to generate a seismic excitation in connection with a fracture treatment of the subterranean region; and a seismic sensor system comprising seismic sensors in directional sections of a plurality of other wellbores in the subterranean region, the seismic sensor system adapted to detect seismic responses based on the seismic excitation, each seismic response being detected at a respective one of the other wellbores. 14. The seismic profiling system of claim 13, wherein the seismic source system comprises an array of seismic sources distributed among multiple completion intervals of the first directional section. 15. The seismic profiling system of claim 13, wherein the seismic sensor system comprises a plurality of fiber optic distributed acoustic sensing arrays in the directional sections of the other wellbores. 16. The seismic profiling system of claim 13, further comprising a computing system comprising:
data processing apparatus; and memory storing computer-readable instructions that, when executed by the data processing apparatus, cause the data processing apparatus to perform operations comprising analyzing the fracture treatment based on seismic response data for the seismic responses. 17. The seismic profiling system of claim 16, wherein the first wellbore comprises a fracture treatment injection wellbore, and the fracture treatment is applied through the fracture treatment injection wellbore. 18. A seismic analysis method comprising:
receiving seismic response data for seismic responses associated with a seismic excitation in a subterranean region, the seismic excitation generated in a first directional section of a first wellbore in the subterranean region, the seismic responses detected at directional sections of a plurality of other wellbores in the subterranean region; and analyzing, by operation of a computer system, a fracture treatment of the subterranean region based on the seismic responses. 19. The seismic analysis method of claim 18, wherein the first wellbore comprises a fracture treatment injection wellbore, and the fracture treatment is applied through the fracture treatment injection wellbore. 20. The seismic analysis method of claim 18, wherein analyzing the fracture treatment comprises generating a three-dimensional seismic velocity model based on the seismic data. 21. The seismic analysis method of claim 18, wherein analyzing the fracture treatment comprises computing geomechanical properties of the subterranean region. | 2,800 |
12,120 | 12,120 | 16,034,385 | 2,891 | An electronic module includes a substrate that includes a first main surface and a second main surface, at least one first electronic component that includes electrodes on a mounting surface thereof on the substrate and that includes a hollow portion, at least one second electronic component that includes electrodes on a mounting surface thereof on the substrate and that includes no hollow portion, and a sealing resin. The at least one first electronic component is mounted on the first main surface of the substrate and sealed with the sealing resin. The at least one second electronic component is mounted on the second main surface of the substrate and is not sealed with the sealing resin. | 1. An electronic module comprising:
a substrate that includes a first main surface and a second main surface; at least one first electronic component that includes electrodes provided on a mounting surface thereof on the substrate and that includes a hollow portion; at least one second electronic component that includes electrodes provided on a mounting surface thereof on the substrate and that includes no hollow portion; and a sealing resin; wherein the at least one first electronic component is mounted on the first main surface of the substrate and sealed with the sealing resin; and the at least one second electronic component has a narrowest pitch between the electrodes that are provided on the mounting surface and is mounted on the second main surface of the substrate, and at least a portion of the at least one second electronic component that is joined to the substrate is not sealed with the sealing resin. 2. The electronic module according to claim 1, wherein the sealing resin includes a filler. 3. The electronic module according to claim 1, wherein an outer electrode that is defined by a metal piece is mounted on the second main surface of the substrate. 4. The electronic module according to claim 1, wherein the at least one first electronic component is an elastic wave device. 5. The electronic module according to claim 1, wherein the at least one second electronic component that has the narrowest pitch between the electrodes on the mounting surface includes an exterior resin that defines outer surfaces thereof. 6. The electronic module according to claim 1, wherein the at least one second electronic component that has the narrowest pitch between the electrodes on the mounting surface is a semiconductor device. 7. The electronic module according to claim 1, wherein a shield electrode is provided on at least a portion of an outer surface of the sealing resin. 8. The electronic module according to claim 1, wherein the substrate is a resin substrate. 9. The electronic module according to claim 8, wherein the resin substrate is made of polychlorinated biphenyl. 10. The electronic module according to claim 1, wherein the substrate is a ceramic substrate. 11. The electronic module according to claim 10, wherein the ceramic substrate is made of low temperature co-fired ceramics. 12. The electronic module according to claim 1, wherein the electrodes of the at least one first electronic component are made of Cu or Ni. 13. The electronic module according to claim 1, wherein the sealing resin does not include filler. 14. The electronic module according to claim 1, wherein narrowest pitch between the electrodes of the at least one second electronic component is about 0.3 mm. 15. The electronic module according to claim 1, wherein the at least one first electronic component and the at least one second electronic component are chip components. 16. The electronic module according to claim 1, wherein the sealing resin is an epoxy resin defining a base material. 17. The electronic module according to claim 16, wherein the sealing resin includes silica powder defining a filler. 18. The electronic module according to claim 17, wherein the silica powder has an average particle diameter of about 30 μm in an amount of about 80% by volume. | An electronic module includes a substrate that includes a first main surface and a second main surface, at least one first electronic component that includes electrodes on a mounting surface thereof on the substrate and that includes a hollow portion, at least one second electronic component that includes electrodes on a mounting surface thereof on the substrate and that includes no hollow portion, and a sealing resin. The at least one first electronic component is mounted on the first main surface of the substrate and sealed with the sealing resin. The at least one second electronic component is mounted on the second main surface of the substrate and is not sealed with the sealing resin.1. An electronic module comprising:
a substrate that includes a first main surface and a second main surface; at least one first electronic component that includes electrodes provided on a mounting surface thereof on the substrate and that includes a hollow portion; at least one second electronic component that includes electrodes provided on a mounting surface thereof on the substrate and that includes no hollow portion; and a sealing resin; wherein the at least one first electronic component is mounted on the first main surface of the substrate and sealed with the sealing resin; and the at least one second electronic component has a narrowest pitch between the electrodes that are provided on the mounting surface and is mounted on the second main surface of the substrate, and at least a portion of the at least one second electronic component that is joined to the substrate is not sealed with the sealing resin. 2. The electronic module according to claim 1, wherein the sealing resin includes a filler. 3. The electronic module according to claim 1, wherein an outer electrode that is defined by a metal piece is mounted on the second main surface of the substrate. 4. The electronic module according to claim 1, wherein the at least one first electronic component is an elastic wave device. 5. The electronic module according to claim 1, wherein the at least one second electronic component that has the narrowest pitch between the electrodes on the mounting surface includes an exterior resin that defines outer surfaces thereof. 6. The electronic module according to claim 1, wherein the at least one second electronic component that has the narrowest pitch between the electrodes on the mounting surface is a semiconductor device. 7. The electronic module according to claim 1, wherein a shield electrode is provided on at least a portion of an outer surface of the sealing resin. 8. The electronic module according to claim 1, wherein the substrate is a resin substrate. 9. The electronic module according to claim 8, wherein the resin substrate is made of polychlorinated biphenyl. 10. The electronic module according to claim 1, wherein the substrate is a ceramic substrate. 11. The electronic module according to claim 10, wherein the ceramic substrate is made of low temperature co-fired ceramics. 12. The electronic module according to claim 1, wherein the electrodes of the at least one first electronic component are made of Cu or Ni. 13. The electronic module according to claim 1, wherein the sealing resin does not include filler. 14. The electronic module according to claim 1, wherein narrowest pitch between the electrodes of the at least one second electronic component is about 0.3 mm. 15. The electronic module according to claim 1, wherein the at least one first electronic component and the at least one second electronic component are chip components. 16. The electronic module according to claim 1, wherein the sealing resin is an epoxy resin defining a base material. 17. The electronic module according to claim 16, wherein the sealing resin includes silica powder defining a filler. 18. The electronic module according to claim 17, wherein the silica powder has an average particle diameter of about 30 μm in an amount of about 80% by volume. | 2,800 |
12,121 | 12,121 | 15,507,986 | 2,865 | Computing device, computer instructions and method for processing energy at a free-surface reflection relating to an air-water interface. The method includes receiving input seismic data recorded with seismic sensors; receiving wave-height data that describes an actual shape of a top surface of a body of water; processing up-going energy at a receiver and down-going energy following a reflection at the sea-surface, using the input seismic data and a linear operator modified to take into account the wave-height data; and generating an image of the subsurface based on the up-going energy or the down-going energy or a combination of the input seismic data and one of the up-going or down-going energy. | 1. A method for processing energy at a free-surface reflection relating to an air-water interface, the method comprising:
receiving input seismic data recorded with seismic sensors; receiving wave-height data that describes an actual shape of a top surface of a body of water; processing up-going energy at a receiver and down-going energy following a reflection at the sea-surface, using the input seismic data and a linear operator modified to take into account the wave-height data; and generating an image of the subsurface based on the up-going energy or the down-going energy or a combination of the input seismic data and one of the up-going or down-going energy. 2. The method of claim 1, wherein the down-going energy is subsequently reflected or refracted in a subsurface and then recorded by another seismic sensor. 3. The method of claim 1, wherein the up-going energy and/or the down-going energy is representative of a wave-field at hypothetical receiver positions, not at a position of an input trace. 4. The method of claim 1, wherein the linear operator contains separate terms representing primary and ghost energy. 5. The method of claim 1, wherein the linear operator includes a reverse model transform. 6. The method of claim 1, wherein the linear operator is a multiple prediction operator, and the method further comprising:
modifying the multiple prediction operator based on the wave-height data, convolving, with a computing device, the modified operator with the seismic data to generate modified seismic data; and generating an image of the subsurface based on the modified seismic data. 7. The method of claim 6, wherein the multiple prediction operator predicts multiples associated with the input seismic data. 8. The method of claim 1, wherein the input seismic data is single or multi-component data. 9. The method of claim 1, wherein the step of receiving wave-height data comprises:
calculating a height of a wave that describes the top surface of the body of water, for each seismic sensor. 10. The method of claim 9, wherein the step of calculating a height of the wave comprises:
extrapolating the input seismic data to align primary and ghost wave fields; cross-correlating the aligned primary and ghost wave fields; and calculating the height of the wave based on a lag produced by the step of cross-correlating. 11. The method of claim 9, wherein the step of calculating a height of the wave comprises:
calculating up-going and down-going wave fields based on a deghosting method; aligning the up-going and down-going fields using a wave field extrapolation method based on a horizontal top surface; cross-correlating the aligned up-going and down-going wave fields; and calculating the height of the wave based on a lag produced by the cross-correlating step. 12. The method of claim 9, wherein the input data is filtered, and the data before and after filtering are cross-correlated to determine a wave height. 13. A computing device for processing energy at a free-surface reflection relating to an air-water interface, the computing device comprising:
an interface for receiving input seismic data recorded with seismic sensors and for receiving wave-height data that describes an actual shape of a top surface of a body of water; and a processor connected to the interface and configured to, process up-going energy at a receiver and down-going energy following a reflection at the sea-surface, using the input seismic data and a linear operator modified to take into account the wave-height data, and generate an image of the subsurface based on the up-going energy or the down-going energy or a combination of the input seismic data and one of the up-going or down-going energy. 14. The computing device of claim 13, wherein the down-going energy is subsequently reflected or refracted in a subsurface and then recorded by another seismic sensor. 15. The computing device of claim 13, wherein the up-going energy and/or the down-going energy is representative of a wave-field at hypothetical receiver positions, not at a position of an input trace. 16. The computing device of claim 13, wherein the linear operator contains separate terms representing primary and ghost energy. 17. The computing device of claim 13, wherein the linear operator includes a reverse model transform. 18. The computing device of claim 1, wherein the linear operator is a multiple prediction operator, and the processor is further configured to:
modify the multiple prediction operator based on the wave-height data, convolve, with a computing device, the modified operator with the seismic data to generate modified seismic data; and generate an image of the subsurface based on the modified seismic data. 19. The computing device of claim 18, wherein the multiple prediction operator predicts multiples associated with the input seismic data. 20. A non-transitory computer readable medium including computer executable instructions, wherein the instructions, when executed by a processor, implement instructions for processing energy at a free-surface reflection relating to an air-water interface, the instructions comprising:
receiving input seismic data recorded with seismic sensors; receiving wave-height data that describes an actual shape of a top surface of a body of water; processing up-going energy at a receiver and down-going energy following a reflection at the sea-surface, using the input seismic data and a linear operator modified to take into account the wave-height data; and generating an image of the subsurface based on the up-going energy or the down-going energy or a combination of the input seismic data and one of the up-going or down-going energy. | Computing device, computer instructions and method for processing energy at a free-surface reflection relating to an air-water interface. The method includes receiving input seismic data recorded with seismic sensors; receiving wave-height data that describes an actual shape of a top surface of a body of water; processing up-going energy at a receiver and down-going energy following a reflection at the sea-surface, using the input seismic data and a linear operator modified to take into account the wave-height data; and generating an image of the subsurface based on the up-going energy or the down-going energy or a combination of the input seismic data and one of the up-going or down-going energy.1. A method for processing energy at a free-surface reflection relating to an air-water interface, the method comprising:
receiving input seismic data recorded with seismic sensors; receiving wave-height data that describes an actual shape of a top surface of a body of water; processing up-going energy at a receiver and down-going energy following a reflection at the sea-surface, using the input seismic data and a linear operator modified to take into account the wave-height data; and generating an image of the subsurface based on the up-going energy or the down-going energy or a combination of the input seismic data and one of the up-going or down-going energy. 2. The method of claim 1, wherein the down-going energy is subsequently reflected or refracted in a subsurface and then recorded by another seismic sensor. 3. The method of claim 1, wherein the up-going energy and/or the down-going energy is representative of a wave-field at hypothetical receiver positions, not at a position of an input trace. 4. The method of claim 1, wherein the linear operator contains separate terms representing primary and ghost energy. 5. The method of claim 1, wherein the linear operator includes a reverse model transform. 6. The method of claim 1, wherein the linear operator is a multiple prediction operator, and the method further comprising:
modifying the multiple prediction operator based on the wave-height data, convolving, with a computing device, the modified operator with the seismic data to generate modified seismic data; and generating an image of the subsurface based on the modified seismic data. 7. The method of claim 6, wherein the multiple prediction operator predicts multiples associated with the input seismic data. 8. The method of claim 1, wherein the input seismic data is single or multi-component data. 9. The method of claim 1, wherein the step of receiving wave-height data comprises:
calculating a height of a wave that describes the top surface of the body of water, for each seismic sensor. 10. The method of claim 9, wherein the step of calculating a height of the wave comprises:
extrapolating the input seismic data to align primary and ghost wave fields; cross-correlating the aligned primary and ghost wave fields; and calculating the height of the wave based on a lag produced by the step of cross-correlating. 11. The method of claim 9, wherein the step of calculating a height of the wave comprises:
calculating up-going and down-going wave fields based on a deghosting method; aligning the up-going and down-going fields using a wave field extrapolation method based on a horizontal top surface; cross-correlating the aligned up-going and down-going wave fields; and calculating the height of the wave based on a lag produced by the cross-correlating step. 12. The method of claim 9, wherein the input data is filtered, and the data before and after filtering are cross-correlated to determine a wave height. 13. A computing device for processing energy at a free-surface reflection relating to an air-water interface, the computing device comprising:
an interface for receiving input seismic data recorded with seismic sensors and for receiving wave-height data that describes an actual shape of a top surface of a body of water; and a processor connected to the interface and configured to, process up-going energy at a receiver and down-going energy following a reflection at the sea-surface, using the input seismic data and a linear operator modified to take into account the wave-height data, and generate an image of the subsurface based on the up-going energy or the down-going energy or a combination of the input seismic data and one of the up-going or down-going energy. 14. The computing device of claim 13, wherein the down-going energy is subsequently reflected or refracted in a subsurface and then recorded by another seismic sensor. 15. The computing device of claim 13, wherein the up-going energy and/or the down-going energy is representative of a wave-field at hypothetical receiver positions, not at a position of an input trace. 16. The computing device of claim 13, wherein the linear operator contains separate terms representing primary and ghost energy. 17. The computing device of claim 13, wherein the linear operator includes a reverse model transform. 18. The computing device of claim 1, wherein the linear operator is a multiple prediction operator, and the processor is further configured to:
modify the multiple prediction operator based on the wave-height data, convolve, with a computing device, the modified operator with the seismic data to generate modified seismic data; and generate an image of the subsurface based on the modified seismic data. 19. The computing device of claim 18, wherein the multiple prediction operator predicts multiples associated with the input seismic data. 20. A non-transitory computer readable medium including computer executable instructions, wherein the instructions, when executed by a processor, implement instructions for processing energy at a free-surface reflection relating to an air-water interface, the instructions comprising:
receiving input seismic data recorded with seismic sensors; receiving wave-height data that describes an actual shape of a top surface of a body of water; processing up-going energy at a receiver and down-going energy following a reflection at the sea-surface, using the input seismic data and a linear operator modified to take into account the wave-height data; and generating an image of the subsurface based on the up-going energy or the down-going energy or a combination of the input seismic data and one of the up-going or down-going energy. | 2,800 |
12,122 | 12,122 | 14,828,062 | 2,866 | Apparatus and methods for detecting stray voltage anomalies in electric fields are provided herein. In some embodiments, an apparatus for detecting an electrical field may comprise: at least one sensor probe for generating data corresponding to an electrical field detected by the at least one sensor probe, wherein the at least one sensor probe comprises at least one electrode; a processor, coupled to the at least one sensor probe, for analyzing the data to identify a voltage anomaly in the electric field; and an indicator, coupled to the processor, for alerting a user to a presence of the voltage anomaly in the electric field. | 1. A mobile apparatus mounted to a motor vehicle for identifying a hazardously energized object, the apparatus comprising:
one or more sensor probes that detect electric field and provide an analog signal corresponding to the electric field; a signal converter for generating a digital signal from the analog signal; a processor that calculates a strength of the electric field; and a display that displays a rise, peak and fall of the strength of the digital signal when the mobile apparatus moves past the hazardously energized object. 2. The apparatus of claim 1, wherein parameters of the mobile apparatus are variable to account for background noise in the electric field and false alarms. 3. The apparatus of claim 1, wherein the signal converter is an analog to digital converter that digitizes the signal to provide a transformation of the signal, the transformation comprising a plurality of time domain samples, each sample representing an amplitude of the electric field strength. 4. The apparatus of claim 3, wherein the processor filters the plurality of time domain samples according to a desired frequency pertaining to the hazardously energized object and to provide a second signal representing a magnitude of the electric field at the desired frequency; and
wherein the apparatus further comprises a computer to receive the second signal and to provide an indication of a magnitude of the electric field at the desired frequency. 5. The apparatus of claim 4, wherein the plurality of time domain samples are subject, by the processor, to a filter to yield a frequency domain representation of the plurality of time domain samples. 6. The apparatus of claim 5, wherein the processor applies the filter on most recent digitized signals at a rate sufficient to produce a continuous output proportional to the strength of the digital signal. 7. The apparatus of claim 6, wherein the processor produces a continuous pitch audio tone proportional to a magnitude of the electric field strength. 8. The apparatus of claim 7, wherein the processor converts a magnitude of the plurality of time domain samples to a logarithmic scale. 9. The apparatus of claim 1, further comprising:
a support frame for mounting the one or more sensor probes to the motor vehicle. 10. The apparatus of claim 1, further comprising:
an audio indicator, coupled to the display, that emits an audio signal corresponding to the rise, peak and fall of the strength of the electric field. 11. The apparatus of claim 10, further comprising:
a computer for capturing the rise, peak and fall to gather additional information to review a potentially hazardous object. 12. A method for detecting a hazardously energized object using a mobile detection apparatus, the method comprising:
moving the mobile detection apparatus; detecting an electric field using one or more sensor probes of the mobile detection apparatus and generating an analog signal corresponding to the electric field; converting the analog signal into a digital signal; and displaying a rise, peak and fall of a strength of the digital signal on a display when the apparatus moves past the hazardous object. 13. The method of claim 12, further comprising:
adjusting parameters of the mobile apparatus according to background noise in the electric field and false alarms. 14. The method of claim 12, wherein the digital signal is a transformation of the electric field comprising a plurality of time domain samples, each sample representing amplitude of the electric field. 15. The method of claim 14, further comprising:
filtering the plurality of time domain samples according to a desired frequency pertaining to the hazardously energized object and to provide a second signal representing a magnitude of the electric field at the desired frequency; and wherein the apparatus further comprises a computer to receive the second signal and to provide an indication of the magnitude of the electric field at the desired frequency. 16. The method of claim 15 wherein the plurality of time domain samples are subject to a filter to yield a frequency domain representation of the plurality of time domain samples. 17. The method of claim 16 further comprising applying the filter on most recent digitized signals at a rate sufficient to produce a continuous output proportional to the strength of the digital signal. 18. The method of claim 17, further comprising producing a continuous pitch audio tone proportional to the strength of the digital signal. 19. The method of claim 18, further comprising converting the plurality of time domain samples to a logarithmic scale. 20. The method of claim 12, further comprising mounting the one or more sensor probe to the motor vehicle via a support frame. | Apparatus and methods for detecting stray voltage anomalies in electric fields are provided herein. In some embodiments, an apparatus for detecting an electrical field may comprise: at least one sensor probe for generating data corresponding to an electrical field detected by the at least one sensor probe, wherein the at least one sensor probe comprises at least one electrode; a processor, coupled to the at least one sensor probe, for analyzing the data to identify a voltage anomaly in the electric field; and an indicator, coupled to the processor, for alerting a user to a presence of the voltage anomaly in the electric field.1. A mobile apparatus mounted to a motor vehicle for identifying a hazardously energized object, the apparatus comprising:
one or more sensor probes that detect electric field and provide an analog signal corresponding to the electric field; a signal converter for generating a digital signal from the analog signal; a processor that calculates a strength of the electric field; and a display that displays a rise, peak and fall of the strength of the digital signal when the mobile apparatus moves past the hazardously energized object. 2. The apparatus of claim 1, wherein parameters of the mobile apparatus are variable to account for background noise in the electric field and false alarms. 3. The apparatus of claim 1, wherein the signal converter is an analog to digital converter that digitizes the signal to provide a transformation of the signal, the transformation comprising a plurality of time domain samples, each sample representing an amplitude of the electric field strength. 4. The apparatus of claim 3, wherein the processor filters the plurality of time domain samples according to a desired frequency pertaining to the hazardously energized object and to provide a second signal representing a magnitude of the electric field at the desired frequency; and
wherein the apparatus further comprises a computer to receive the second signal and to provide an indication of a magnitude of the electric field at the desired frequency. 5. The apparatus of claim 4, wherein the plurality of time domain samples are subject, by the processor, to a filter to yield a frequency domain representation of the plurality of time domain samples. 6. The apparatus of claim 5, wherein the processor applies the filter on most recent digitized signals at a rate sufficient to produce a continuous output proportional to the strength of the digital signal. 7. The apparatus of claim 6, wherein the processor produces a continuous pitch audio tone proportional to a magnitude of the electric field strength. 8. The apparatus of claim 7, wherein the processor converts a magnitude of the plurality of time domain samples to a logarithmic scale. 9. The apparatus of claim 1, further comprising:
a support frame for mounting the one or more sensor probes to the motor vehicle. 10. The apparatus of claim 1, further comprising:
an audio indicator, coupled to the display, that emits an audio signal corresponding to the rise, peak and fall of the strength of the electric field. 11. The apparatus of claim 10, further comprising:
a computer for capturing the rise, peak and fall to gather additional information to review a potentially hazardous object. 12. A method for detecting a hazardously energized object using a mobile detection apparatus, the method comprising:
moving the mobile detection apparatus; detecting an electric field using one or more sensor probes of the mobile detection apparatus and generating an analog signal corresponding to the electric field; converting the analog signal into a digital signal; and displaying a rise, peak and fall of a strength of the digital signal on a display when the apparatus moves past the hazardous object. 13. The method of claim 12, further comprising:
adjusting parameters of the mobile apparatus according to background noise in the electric field and false alarms. 14. The method of claim 12, wherein the digital signal is a transformation of the electric field comprising a plurality of time domain samples, each sample representing amplitude of the electric field. 15. The method of claim 14, further comprising:
filtering the plurality of time domain samples according to a desired frequency pertaining to the hazardously energized object and to provide a second signal representing a magnitude of the electric field at the desired frequency; and wherein the apparatus further comprises a computer to receive the second signal and to provide an indication of the magnitude of the electric field at the desired frequency. 16. The method of claim 15 wherein the plurality of time domain samples are subject to a filter to yield a frequency domain representation of the plurality of time domain samples. 17. The method of claim 16 further comprising applying the filter on most recent digitized signals at a rate sufficient to produce a continuous output proportional to the strength of the digital signal. 18. The method of claim 17, further comprising producing a continuous pitch audio tone proportional to the strength of the digital signal. 19. The method of claim 18, further comprising converting the plurality of time domain samples to a logarithmic scale. 20. The method of claim 12, further comprising mounting the one or more sensor probe to the motor vehicle via a support frame. | 2,800 |
12,123 | 12,123 | 14,062,319 | 2,822 | This invention discloses a semiconductor power device formed in a semiconductor substrate comprises a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region. The semiconductor power device further comprises a body region, a source region and a gate disposed near the top surface of the semiconductor substrate and a drain disposed at a bottom surface of the semiconductor substrate. Source trenches are opened into the highly doped region filled with a conductive trench filling material in electrical contact with the source region near the top surface. A buried field ring regions is disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. In an alternate embodiment, there are doped regions doped with a dopant of a same conductivity type of the buried field ring regions surrounding the sidewalls of the source trenches to function as a charge supply path. | 1. A method for manufacturing a semiconductor power device in a semiconductor substrate comprising:
doping the semiconductor substrate to form a lightly doped lower layer and a highly doped upper layer near a top surface on top of the lightly doped lower layer; opening a plurality of source connecting trenches into the highly doped upper layer; implanting buried field ring regions below the source connecting trenches with a dopant of opposite conductivity from the highly doped upper layer; padding the source connecting trenches with a trench insulation layer and filling the source connecting trenches with a conductive trench filling material; and forming a body region, a source region and a gate near the top surface of the semiconductor substrate and forming a source electrode metal layer connecting to the source region and the conducting trench filling material in the source connecting trenches. 2. The method of claim 1 wherein:
the step of forming the highly doped upper layer and the lightly doped lower layer comprising a step of forming the highly doped upper layer and the lightly doped lower layer as N type doped layers and implanting the buried field ring regions as P type buried field ring regions. 3. The semiconductor power device of claim 1 further comprising:
forming the semiconductor power device on the semiconductor substrate with a heavily doped N bottom layer to function as the drain of the semiconductor substrate. 4. The semiconductor power device of claim 2 wherein:
the step of forming the highly doped upper layer and the lightly doped lower layer as N type doped layers further comprises a step of forming the highly doped upper layer having a dopant concentration ranging approximately between 1e15 cm−3 to 5e16 cm−3 and the lower lightly doped lower layer having a dopant concentration ranging approximately between 1e14 cm−3 to 5e15 cm−3. 5. The method of claim 3 wherein:
the step of forming the semiconductor power device on the semiconductor substrate with a heavily doped N bottom layer further comprises a step of forming the semiconductor power device on the heavily doped N bottom layer having a dopant concentration ranging approximately between 1e19 cm−3 to 1e21 cm−3. 6. The method of claim 1 wherein:
the step of forming the highly doped upper layer and the lightly doped lower layer further comprises a step of doping the highly doped upper layer and the lightly doped lower layer respectively with an arsenic dopant and a phosphorous dopant. 7. The method of claim 1 wherein:
the step of padding the source connecting trenches with a trench insulation layer further comprises a step of padding the source connecting trenching with an oxide layer and filling the source connecting trenches with a polysilicon as the conductive trench filling material. 8. The method of claim 1 wherein:
the step of opening the source connecting trenches further comprises a step of opening the source connecting trenches into a depth approximately 6 micrometers into the highly doped upper layer and padding the source connecting trenches with an oxide layer having a thickness of approximately 5500 Angstroms. 9. The method of claim 1 wherein:
the step of implanting the buried field ring regions below the source trenches further comprises a step of implanting a P-type dopant to form the buried field ring regions having a dopant concentration ranging approximately between 1e14 cm−3 to 1e16 cm−3. 10. The method of claim 1 wherein:
The step of implanting the buried field ring regions below the source trenches further comprises a step of carrying out a tilt angle implant to form charge supply path regions surrounding sidewalls of the source trenches with a dopant of the same conductivity type as the buried field regions | This invention discloses a semiconductor power device formed in a semiconductor substrate comprises a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region. The semiconductor power device further comprises a body region, a source region and a gate disposed near the top surface of the semiconductor substrate and a drain disposed at a bottom surface of the semiconductor substrate. Source trenches are opened into the highly doped region filled with a conductive trench filling material in electrical contact with the source region near the top surface. A buried field ring regions is disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. In an alternate embodiment, there are doped regions doped with a dopant of a same conductivity type of the buried field ring regions surrounding the sidewalls of the source trenches to function as a charge supply path.1. A method for manufacturing a semiconductor power device in a semiconductor substrate comprising:
doping the semiconductor substrate to form a lightly doped lower layer and a highly doped upper layer near a top surface on top of the lightly doped lower layer; opening a plurality of source connecting trenches into the highly doped upper layer; implanting buried field ring regions below the source connecting trenches with a dopant of opposite conductivity from the highly doped upper layer; padding the source connecting trenches with a trench insulation layer and filling the source connecting trenches with a conductive trench filling material; and forming a body region, a source region and a gate near the top surface of the semiconductor substrate and forming a source electrode metal layer connecting to the source region and the conducting trench filling material in the source connecting trenches. 2. The method of claim 1 wherein:
the step of forming the highly doped upper layer and the lightly doped lower layer comprising a step of forming the highly doped upper layer and the lightly doped lower layer as N type doped layers and implanting the buried field ring regions as P type buried field ring regions. 3. The semiconductor power device of claim 1 further comprising:
forming the semiconductor power device on the semiconductor substrate with a heavily doped N bottom layer to function as the drain of the semiconductor substrate. 4. The semiconductor power device of claim 2 wherein:
the step of forming the highly doped upper layer and the lightly doped lower layer as N type doped layers further comprises a step of forming the highly doped upper layer having a dopant concentration ranging approximately between 1e15 cm−3 to 5e16 cm−3 and the lower lightly doped lower layer having a dopant concentration ranging approximately between 1e14 cm−3 to 5e15 cm−3. 5. The method of claim 3 wherein:
the step of forming the semiconductor power device on the semiconductor substrate with a heavily doped N bottom layer further comprises a step of forming the semiconductor power device on the heavily doped N bottom layer having a dopant concentration ranging approximately between 1e19 cm−3 to 1e21 cm−3. 6. The method of claim 1 wherein:
the step of forming the highly doped upper layer and the lightly doped lower layer further comprises a step of doping the highly doped upper layer and the lightly doped lower layer respectively with an arsenic dopant and a phosphorous dopant. 7. The method of claim 1 wherein:
the step of padding the source connecting trenches with a trench insulation layer further comprises a step of padding the source connecting trenching with an oxide layer and filling the source connecting trenches with a polysilicon as the conductive trench filling material. 8. The method of claim 1 wherein:
the step of opening the source connecting trenches further comprises a step of opening the source connecting trenches into a depth approximately 6 micrometers into the highly doped upper layer and padding the source connecting trenches with an oxide layer having a thickness of approximately 5500 Angstroms. 9. The method of claim 1 wherein:
the step of implanting the buried field ring regions below the source trenches further comprises a step of implanting a P-type dopant to form the buried field ring regions having a dopant concentration ranging approximately between 1e14 cm−3 to 1e16 cm−3. 10. The method of claim 1 wherein:
The step of implanting the buried field ring regions below the source trenches further comprises a step of carrying out a tilt angle implant to form charge supply path regions surrounding sidewalls of the source trenches with a dopant of the same conductivity type as the buried field regions | 2,800 |
12,124 | 12,124 | 15,023,104 | 2,863 | A method is disclosed for determining a mechanical-technological characteristic variable of ferromagnetic metals, preferably ferromagnetic steels, and in particular fine-grained steels, which are used in pipelines. A magnetization apparatus, which has at least one permanent magnet or solenoid, magnetizes the metal which is to be determined, and a sensor apparatus comprising a transmission coil generates a magnetic field which interacts with the magnetic field which is generated by the magnetization apparatus in the metal, and which generates an eddy current. The eddy current is generated in the magnetically at least substantially saturated metal, and the eddy current is measured by an eddy current sensor of the sensor apparatus. A magnetic field strength sensor measures the magnetic field of the metal at least close to the surface, and the electrical conductivity or the specific electrical resistance of the metal is ascertained from the data from the eddy current sensor on the basis of reference data by means of an evaluation apparatus. The characteristic variable of the metal is derived from the conductivity or the resistance, and also an inspection gauge for carrying out a method of this kind. | 1. A method for determining a mechanical-technological characteristic variable of ferromagnetic metals comprising the steps of:
magnetizing a metal that is to be determined with a magnetization apparatus which has at least one permanent magnet or solenoid; generating a magnetic field via a sensor apparatus comprising a transmission coil, said magnetic field interacting with the magnetic field which is generated in the metal by the magnetization apparatus, wherein said interaction generates an eddy current in the metal; measuring the eddy current by an eddy current sensor of the sensor apparatus; measuring a magnetic field strength sensor measures the magnetic field of the metal at least close to the surface ascertaining the electrical conductivity or the specific electrical resistance of the metal from the data from the eddy current sensor on the basis of reference data via an evaluation apparatus; and deriving the characteristic variable of the metal from the conductivity or the resistance. 2. The method as claimed in claim 1, further including the step of moving the sensor apparatus within a pipeline and along the inside surface of said pipeline as part of an inspection gauge. 3. The method as claimed in claim 2, further including the step of recording data with a plurality of the sensor apparatuses for detecting the characteristic variable of the pipeline wall in the circumferential direction around a longitudinal center axis of the inspection gauge. 4. The method of claim 1 wherein the characteristic variable is at least one of the hardness, the yield strength and the tensile strength. 5. The method of claim 1 wherein the magnetic field for generating the eddy current is generated at least by a first coil of the sensor apparatus, wherein the sensor apparatus also comprises a further coil, and the eddy current is measured on the basis of a voltage difference and phase difference in a bridge circuit comprising the two coils. 6. The method of claim 1 wherein the metal is magnetically saturated by the magnetization apparatus in order to minimize the influence of the relative permeability. 7. The method of claim 1 wherein a magnetic field which has a strength of more than 4 kA/m, preferably more than 5 kA/m, is generated in the metal by the magnetization apparatus. 8. The method of claim 1 wherein the distance of the eddy current sensor is recorded and/or prespecified, in order to remove the dependence of the eddy current signal on the lift-off. 9. The method of claim 1 wherein the temperature is measured by a temperature sensor, in order to correct the electrical conductivity or the specific electrical resistance and/or the eddy current signal in respect of the temperature. 10. The method of claim 1 wherein the evaluation apparatus accesses a reference database in which the electrical conductivity and/or the specific electrical resistance of various metals together with their mechanical-technological characteristic variables, in particular comprising at least the tensile strength, the yield strength and/or the hardness, are stored. 11. The method of claim 1 wherein the sensor apparatus has at least two, preferably three eddy current sensors, in particular which are arranged on a common sensor support, which measure the eddy current at various frequencies. 12. The method of claim 1 wherein a plurality of sensor apparatuses are arranged next to one another in the circumferential direction and such that they can move with respect to a longitudinal center axis in the radial direction, in such a way that the sensor apparatuses are arranged on the inside of a metal pipeline and measure the characteristic variable of said metal pipeline in the circumferential direction. 13. An inspection gauge for pipeline pipes, said inspection gauge comprising:
at least one magnetization apparatus, which is in the form of a magnet yoke; a sensor apparatus which has a transmission coil, said sensor apparatus comprising an eddy current sensor; wherein in order to detect a mechanical-technological characteristic variable of the pipeline pipe the inspection gauge has an eddy current sensor which is arranged between poles of the magnetization apparatus, and also a magnetic field strength sensor. 14. The inspection gauge as claimed in claim 13, wherein the magnetization apparatus has at least one permanent magnet, and the magnetic field strength sensor is arranged between the poles of said magnetization apparatus or a further, adjacent magnetization apparatus. 15. The inspection gauge as claimed in claim 14, wherein the inspection gauge has a temperature sensor. 16. The inspection gauge as claimed in claim 13 wherein the sensor apparatus is arranged on a sensor support which, when force is applied, can move in the radial direction in relation to a longitudinal axis of the inspection gauge. 17. The inspection gauge as claimed in claim 13 wherein the inspection gauge has a large number of sensor apparatuses which are arranged next to one another in the circumferential direction. 18. The inspection gauge as claimed in claim 13 wherein the sensor apparatus has in each case three eddy current sensors which comprise two coils, wherein each eddy current sensor is designed for a different frequency. | A method is disclosed for determining a mechanical-technological characteristic variable of ferromagnetic metals, preferably ferromagnetic steels, and in particular fine-grained steels, which are used in pipelines. A magnetization apparatus, which has at least one permanent magnet or solenoid, magnetizes the metal which is to be determined, and a sensor apparatus comprising a transmission coil generates a magnetic field which interacts with the magnetic field which is generated by the magnetization apparatus in the metal, and which generates an eddy current. The eddy current is generated in the magnetically at least substantially saturated metal, and the eddy current is measured by an eddy current sensor of the sensor apparatus. A magnetic field strength sensor measures the magnetic field of the metal at least close to the surface, and the electrical conductivity or the specific electrical resistance of the metal is ascertained from the data from the eddy current sensor on the basis of reference data by means of an evaluation apparatus. The characteristic variable of the metal is derived from the conductivity or the resistance, and also an inspection gauge for carrying out a method of this kind.1. A method for determining a mechanical-technological characteristic variable of ferromagnetic metals comprising the steps of:
magnetizing a metal that is to be determined with a magnetization apparatus which has at least one permanent magnet or solenoid; generating a magnetic field via a sensor apparatus comprising a transmission coil, said magnetic field interacting with the magnetic field which is generated in the metal by the magnetization apparatus, wherein said interaction generates an eddy current in the metal; measuring the eddy current by an eddy current sensor of the sensor apparatus; measuring a magnetic field strength sensor measures the magnetic field of the metal at least close to the surface ascertaining the electrical conductivity or the specific electrical resistance of the metal from the data from the eddy current sensor on the basis of reference data via an evaluation apparatus; and deriving the characteristic variable of the metal from the conductivity or the resistance. 2. The method as claimed in claim 1, further including the step of moving the sensor apparatus within a pipeline and along the inside surface of said pipeline as part of an inspection gauge. 3. The method as claimed in claim 2, further including the step of recording data with a plurality of the sensor apparatuses for detecting the characteristic variable of the pipeline wall in the circumferential direction around a longitudinal center axis of the inspection gauge. 4. The method of claim 1 wherein the characteristic variable is at least one of the hardness, the yield strength and the tensile strength. 5. The method of claim 1 wherein the magnetic field for generating the eddy current is generated at least by a first coil of the sensor apparatus, wherein the sensor apparatus also comprises a further coil, and the eddy current is measured on the basis of a voltage difference and phase difference in a bridge circuit comprising the two coils. 6. The method of claim 1 wherein the metal is magnetically saturated by the magnetization apparatus in order to minimize the influence of the relative permeability. 7. The method of claim 1 wherein a magnetic field which has a strength of more than 4 kA/m, preferably more than 5 kA/m, is generated in the metal by the magnetization apparatus. 8. The method of claim 1 wherein the distance of the eddy current sensor is recorded and/or prespecified, in order to remove the dependence of the eddy current signal on the lift-off. 9. The method of claim 1 wherein the temperature is measured by a temperature sensor, in order to correct the electrical conductivity or the specific electrical resistance and/or the eddy current signal in respect of the temperature. 10. The method of claim 1 wherein the evaluation apparatus accesses a reference database in which the electrical conductivity and/or the specific electrical resistance of various metals together with their mechanical-technological characteristic variables, in particular comprising at least the tensile strength, the yield strength and/or the hardness, are stored. 11. The method of claim 1 wherein the sensor apparatus has at least two, preferably three eddy current sensors, in particular which are arranged on a common sensor support, which measure the eddy current at various frequencies. 12. The method of claim 1 wherein a plurality of sensor apparatuses are arranged next to one another in the circumferential direction and such that they can move with respect to a longitudinal center axis in the radial direction, in such a way that the sensor apparatuses are arranged on the inside of a metal pipeline and measure the characteristic variable of said metal pipeline in the circumferential direction. 13. An inspection gauge for pipeline pipes, said inspection gauge comprising:
at least one magnetization apparatus, which is in the form of a magnet yoke; a sensor apparatus which has a transmission coil, said sensor apparatus comprising an eddy current sensor; wherein in order to detect a mechanical-technological characteristic variable of the pipeline pipe the inspection gauge has an eddy current sensor which is arranged between poles of the magnetization apparatus, and also a magnetic field strength sensor. 14. The inspection gauge as claimed in claim 13, wherein the magnetization apparatus has at least one permanent magnet, and the magnetic field strength sensor is arranged between the poles of said magnetization apparatus or a further, adjacent magnetization apparatus. 15. The inspection gauge as claimed in claim 14, wherein the inspection gauge has a temperature sensor. 16. The inspection gauge as claimed in claim 13 wherein the sensor apparatus is arranged on a sensor support which, when force is applied, can move in the radial direction in relation to a longitudinal axis of the inspection gauge. 17. The inspection gauge as claimed in claim 13 wherein the inspection gauge has a large number of sensor apparatuses which are arranged next to one another in the circumferential direction. 18. The inspection gauge as claimed in claim 13 wherein the sensor apparatus has in each case three eddy current sensors which comprise two coils, wherein each eddy current sensor is designed for a different frequency. | 2,800 |
12,125 | 12,125 | 15,625,230 | 2,836 | A circuit interrupter is structured to protect a protected circuit. The circuit interrupter includes a ground fault current sensor structured to sense a ground fault current in the protected circuit and a processor including a routine structured to perform a ground fault output self-test. The ground fault output self-test includes to output a trip signal within a predetermined phase angle of a zero-crossing of current flowing through the protected circuit, to stop outputting the trip signal before the zero-crossing, to determine whether the trip signal caused a pulse in the ground fault current, and to determine whether the circuit interrupter passed the ground fault output self-test based on whether the trip signal caused a pulse in the ground fault current. | 1. A circuit interrupter structured to protect a protected circuit, the circuit interrupter comprising:
a ground fault current sensor structured to sense a ground fault current in the protected circuit; a processor including a routine structured to perform a ground fault output self-test, the ground fault output self-test including:
to output a trip signal within a predetermined phase angle of a zero-crossing of current flowing through the protected circuit;
to stop outputting the trip signal before the zero-crossing;
to determine whether the trip signal caused a pulse in the ground fault current; and
to determine whether the circuit interrupter passed the ground fault output self-test based on whether the trip signal caused a pulse in the ground fault current. 2. The circuit interrupter of claim 1, wherein the processor is structured to determine that the circuit interrupter passed the ground fault output self-test when it is determined that the trip signal caused the pulse in the ground fault current; and wherein the processor is structured to determine that the circuit interrupter failed the ground fault output self-test when it is determined that the trip signal did not cause the pulse in the ground fault current. 3. The circuit interrupter of claim 2, wherein the processor is structured to repeat the ground fault output self-test if the circuit interrupter fails the ground fault output self-test; and wherein the processor is structured to output an error signal if the circuit interrupter fails the ground fault output self-test a predetermined consecutive number of times. 4. The circuit interrupter of claim 3, further comprising:
an indicator structured to activate in response to the processor outputting the error signal. 5. The circuit interrupter of claim 1, wherein the ground fault output self-test further includes:
to perform a first integration on the ground fault current for a first predetermined period of time where the pulse is expected to be present; to perform a second integration on the ground fault current for a second predetermined period of time where the pulse is not expected to be present; and to compare the first and second integrations, and wherein the processor is structured to determine that the trip signal caused the pulse in the ground fault current if a difference between the first and second integrations is above a threshold level. 6. The circuit interrupter of claim 1, wherein the processor is structured to determine whether the trip signal caused a pulse in the ground fault current by tracking a peak value of the ground fault current. 7. The circuit interrupter of claim 1, further comprising:
separable contacts; a solenoid structured to activate to trip open the separable contacts; and a silicon controlled rectifier (SCR) structured to allow current from the protected circuit to flow through a coil of the solenoid when the processor outputs the trip signal, wherein the current flowing through the protected circuit within the predetermined phase angle of the zero-crossing is insufficient to cause the solenoid to activate and trip open the separable contacts. 8. The circuit interrupter of claim 7, wherein the predetermined phase angle is about 15 degrees. 9. The circuit interrupter of claim 1, wherein the processor is structured to perform the ground fault output self-test at predetermined intervals. 10. The circuit interrupter of claim 1, wherein the processor is structured to perform a ground fault input self-test prior to performing the ground fault output self-test. 11. A method of performing a ground fault output self-test in a circuit interrupter, the method comprising:
outputting a trip signal within a predetermined phase angle of a zero-crossing of current flowing through a protected circuit; stopping output of the trip signal before the zero-crossing; determining whether the trip signal caused a pulse in the ground fault current; and determining whether the ground fault output self-test has been passed based on whether the trip signal caused a pulse in the ground fault current. 12. The method of claim 11, further comprising:
determining that the ground fault output self-test has been passed when it is determined that the trip signal caused the pulse in the ground fault current; and determining that the ground fault output self-test has been failed when it is determined that the trip signal did not cause the pulse in the ground fault current. 13. The method of claim 12, further comprising:
repeating the ground fault output self-test if the ground fault output self-test has been failed; and outputting an error signal if the ground fault output self-test has been failed a predetermined consecutive number of times. 14. The method of claim 13, further comprising:
activating an indicator in response to outputting the error signal. 15. The method of claim 11, wherein determining whether the trip signal caused a pulse in the ground fault current includes:
performing a first integration on the ground fault current for a first predetermined period of time where the pulse is expected to be present; performing a second integration on the ground fault current for a second predetermined period of time where the pulse is not expected to be present; and comparing the first and second integrations; and determining that the trip signal caused the pulse in the ground fault current if a difference between the first and second integrations is above a threshold level. 16. The method of claim 11, wherein determining whether the trip signal caused a pulse in the ground fault current includes:
determining whether the trip signal caused a pulse in the ground fault current by tracking a peak value of the ground fault current. 17. The method of claim 11, wherein the current flowing through the protected circuit within the predetermined phase angle of the zero-crossing is insufficient to cause a solenoid to activate and trip open separable contacts of the circuit interrupter. 18. The method of claim 17, wherein the predetermined phase angle is about 15 degrees. 19. A non-transitory computer readable medium storing one or more programs, including instructions, which when executed by a computer, causes the computer to perform a method of performing a ground fault output self-test in a circuit interrupter, the method comprising:
outputting a trip signal within a predetermined phase angle of a zero-crossing of current flowing through a protected circuit; stopping output of the trip signal before the zero-crossing; determining whether the trip signal caused a pulse in the ground fault current; and determining whether the ground fault output self-test has been passed based on whether the trip signal caused a pulse in the ground fault current. 20. The non-transitory computer readable medium of claim 19, wherein the method further comprises:
determining that the ground fault output self-test has been passed when it is determined that the trip signal caused the pulse in the ground fault current; and determining that the ground fault output self-test has been failed when it is determined that the trip signal did not cause the pulse in the ground fault current. | A circuit interrupter is structured to protect a protected circuit. The circuit interrupter includes a ground fault current sensor structured to sense a ground fault current in the protected circuit and a processor including a routine structured to perform a ground fault output self-test. The ground fault output self-test includes to output a trip signal within a predetermined phase angle of a zero-crossing of current flowing through the protected circuit, to stop outputting the trip signal before the zero-crossing, to determine whether the trip signal caused a pulse in the ground fault current, and to determine whether the circuit interrupter passed the ground fault output self-test based on whether the trip signal caused a pulse in the ground fault current.1. A circuit interrupter structured to protect a protected circuit, the circuit interrupter comprising:
a ground fault current sensor structured to sense a ground fault current in the protected circuit; a processor including a routine structured to perform a ground fault output self-test, the ground fault output self-test including:
to output a trip signal within a predetermined phase angle of a zero-crossing of current flowing through the protected circuit;
to stop outputting the trip signal before the zero-crossing;
to determine whether the trip signal caused a pulse in the ground fault current; and
to determine whether the circuit interrupter passed the ground fault output self-test based on whether the trip signal caused a pulse in the ground fault current. 2. The circuit interrupter of claim 1, wherein the processor is structured to determine that the circuit interrupter passed the ground fault output self-test when it is determined that the trip signal caused the pulse in the ground fault current; and wherein the processor is structured to determine that the circuit interrupter failed the ground fault output self-test when it is determined that the trip signal did not cause the pulse in the ground fault current. 3. The circuit interrupter of claim 2, wherein the processor is structured to repeat the ground fault output self-test if the circuit interrupter fails the ground fault output self-test; and wherein the processor is structured to output an error signal if the circuit interrupter fails the ground fault output self-test a predetermined consecutive number of times. 4. The circuit interrupter of claim 3, further comprising:
an indicator structured to activate in response to the processor outputting the error signal. 5. The circuit interrupter of claim 1, wherein the ground fault output self-test further includes:
to perform a first integration on the ground fault current for a first predetermined period of time where the pulse is expected to be present; to perform a second integration on the ground fault current for a second predetermined period of time where the pulse is not expected to be present; and to compare the first and second integrations, and wherein the processor is structured to determine that the trip signal caused the pulse in the ground fault current if a difference between the first and second integrations is above a threshold level. 6. The circuit interrupter of claim 1, wherein the processor is structured to determine whether the trip signal caused a pulse in the ground fault current by tracking a peak value of the ground fault current. 7. The circuit interrupter of claim 1, further comprising:
separable contacts; a solenoid structured to activate to trip open the separable contacts; and a silicon controlled rectifier (SCR) structured to allow current from the protected circuit to flow through a coil of the solenoid when the processor outputs the trip signal, wherein the current flowing through the protected circuit within the predetermined phase angle of the zero-crossing is insufficient to cause the solenoid to activate and trip open the separable contacts. 8. The circuit interrupter of claim 7, wherein the predetermined phase angle is about 15 degrees. 9. The circuit interrupter of claim 1, wherein the processor is structured to perform the ground fault output self-test at predetermined intervals. 10. The circuit interrupter of claim 1, wherein the processor is structured to perform a ground fault input self-test prior to performing the ground fault output self-test. 11. A method of performing a ground fault output self-test in a circuit interrupter, the method comprising:
outputting a trip signal within a predetermined phase angle of a zero-crossing of current flowing through a protected circuit; stopping output of the trip signal before the zero-crossing; determining whether the trip signal caused a pulse in the ground fault current; and determining whether the ground fault output self-test has been passed based on whether the trip signal caused a pulse in the ground fault current. 12. The method of claim 11, further comprising:
determining that the ground fault output self-test has been passed when it is determined that the trip signal caused the pulse in the ground fault current; and determining that the ground fault output self-test has been failed when it is determined that the trip signal did not cause the pulse in the ground fault current. 13. The method of claim 12, further comprising:
repeating the ground fault output self-test if the ground fault output self-test has been failed; and outputting an error signal if the ground fault output self-test has been failed a predetermined consecutive number of times. 14. The method of claim 13, further comprising:
activating an indicator in response to outputting the error signal. 15. The method of claim 11, wherein determining whether the trip signal caused a pulse in the ground fault current includes:
performing a first integration on the ground fault current for a first predetermined period of time where the pulse is expected to be present; performing a second integration on the ground fault current for a second predetermined period of time where the pulse is not expected to be present; and comparing the first and second integrations; and determining that the trip signal caused the pulse in the ground fault current if a difference between the first and second integrations is above a threshold level. 16. The method of claim 11, wherein determining whether the trip signal caused a pulse in the ground fault current includes:
determining whether the trip signal caused a pulse in the ground fault current by tracking a peak value of the ground fault current. 17. The method of claim 11, wherein the current flowing through the protected circuit within the predetermined phase angle of the zero-crossing is insufficient to cause a solenoid to activate and trip open separable contacts of the circuit interrupter. 18. The method of claim 17, wherein the predetermined phase angle is about 15 degrees. 19. A non-transitory computer readable medium storing one or more programs, including instructions, which when executed by a computer, causes the computer to perform a method of performing a ground fault output self-test in a circuit interrupter, the method comprising:
outputting a trip signal within a predetermined phase angle of a zero-crossing of current flowing through a protected circuit; stopping output of the trip signal before the zero-crossing; determining whether the trip signal caused a pulse in the ground fault current; and determining whether the ground fault output self-test has been passed based on whether the trip signal caused a pulse in the ground fault current. 20. The non-transitory computer readable medium of claim 19, wherein the method further comprises:
determining that the ground fault output self-test has been passed when it is determined that the trip signal caused the pulse in the ground fault current; and determining that the ground fault output self-test has been failed when it is determined that the trip signal did not cause the pulse in the ground fault current. | 2,800 |
12,126 | 12,126 | 15,179,322 | 2,837 | A magnetic actuator or liner actuator with improved plunger control and a simplified construction technique is provided. | 1. A linear actuator, comprising:
a housing that has an upper surface, a circumferential wall, and a cover that define an interior space, the upper surface and the cover have apertures on a common centerline, and the cover has a base that fits within and closes the aperture in the cover; the base has a floor, a first wall of a predetermined height and a second wall that is interior to and spaced from the first wall and has a predetermined height that is less than the predetermined height of the first wall so there is open space between the first and second walls and open space that is above the second wall and within the first wall; an electrical element that is positioned between the first wall of the base and the circumferential wall of the housing; a plunger having an exterior configuration that fits within the space defined by the first and second walls of the base, an internal relief that receives the second wall of the base, and a central opening that receives a plunger rod; and, a plunger rod that is connected to the plunger and has a height sufficient to extend from the floor of the base to an aperture in the upper surface of the housing; whereby the electrical element controls movement of the plunger and the plunger rod and causes the plunge rod to extend outwardly and retract inwardly through the aperture in the upper surface of the housing. 2. An actuation element for a magnetic actuator having a housing that encloses an electrical element and upper and lower surfaces that have apertures on a common centerline, the actuation element comprising:
a base that fits within and closes the aperture in the lower surface and has a floor, a first wall of a predetermined height and a second wall that is interior to and spaced from the first wall and has a predetermined height that is less than the predetermined height of the first wall so there is open space between the first and second walls and open space that is above the second wall and within the first wall; and, a plunger and a rod member wherein the plunger has an exterior configuration that fits within the space defined by the first and second walls and a central relief dimensioned to receive the second wall within the relief, and a plunger rod having a height sufficient to extend from the floor of the base to the aperture in the upper surface of the housing. 3. A linear actuator, comprising:
a housing that has a first member with a planar surface defining a central opening and a circumferential wall defining an open interior space, and a second member that joins the circumferential wall and closes the interior space, the second member has a central opening on a centerline with the central opening of the planar surface; a magnet element that encircles the central opening; a base that defines a lower interior surface for the housing and fits within and closes an aperture in the second member, the base has a first wall of a predetermined height and a second wall that is spaced from the first wall and has a smaller predetermined height than the first wall so there is open space between the first and second walls and open space that is above the second wall and within the first wall; and, a plunger and a rod combination where the plunger has an exterior configuration that fits within the space defined by the first and second walls and a central relief configured to receive the second wall within the relief, and the rod has a height sufficient to extend from the lower interior surface of the base to the aperture in an upper surface of the housing. 4. A linear actuator, comprising:
a housing that has an upper surface, a circumferential wall, and a cover that define an interior space, the upper surface and the cover have apertures on a common centerline, and the cover has a base that fits within and closes the aperture in the cover; the base has a floor, a first wall of a predetermined height and a second wall that is interior to and spaced from the first wall and has a predetermined height that is less than the predetermined height of the first wall so there is open space between the first and second walls and open space that is above the second wall and within the first wall; an electrical element that is positioned between the first wall of the base and the circumferential wall of the housing and generates a current; a plunger having a body with an exterior that fits within the first wall of the base and an interior relief that fits over the second wall of the base, and a plunger rod extending through the center of the plunger body; the plunger rod having a height sufficient to extend from the floor of the base to an aperture in the upper surface of the housing, and moves outwardly and inwardly through the aperture in the upper surface of the housing in response to current generated by the electrical element. 5. The linear actuator of claim 4 wherein, the first and second wall of the base and the plunder body are tubular. 6. The linear actuator of claim 4 wherein, a bearing at the upper surface of the housing and a bearing mounted on the second wall of the base guide the movement of the plunger rod. 7. The linear actuator of claim 4 wherein, the cover is positioned within the circumferential wall of the housing and the circumferential wall of the housing has a plurality of dependent tabs that maintain the cover's position within the circumferential wall of the housing. 8. The linear actuator of claim 4 wherein, the plunger has a predetermined diameter that is less than a predetermined interior diameter of the second wall of the base and there is an interior void formed between them. 9. The linear actuator of claim 8 wherein, the second wall of the base has an aperture that extends between the interior void and the interior relief of the plunger body. 10. A linear actuator container for containing an electrical element, a plunger that is controlled by the electrical element and a plunger rod that guides the plunger movement within the container, the container comprising:
a housing with an upper surface and a dependent circumferential wall with a lower portion that includes a plurality of tabs, the circumferential wall has a predetermined height between the upper surface and the lower portion that includes the plurality of tabs; and a lower surface member that joins with the dependent circumferential wall, at the predetermined height to enclose an electrical element, a plunger and a plunger rod, and is locked in place by the plurality of tabs. | A magnetic actuator or liner actuator with improved plunger control and a simplified construction technique is provided.1. A linear actuator, comprising:
a housing that has an upper surface, a circumferential wall, and a cover that define an interior space, the upper surface and the cover have apertures on a common centerline, and the cover has a base that fits within and closes the aperture in the cover; the base has a floor, a first wall of a predetermined height and a second wall that is interior to and spaced from the first wall and has a predetermined height that is less than the predetermined height of the first wall so there is open space between the first and second walls and open space that is above the second wall and within the first wall; an electrical element that is positioned between the first wall of the base and the circumferential wall of the housing; a plunger having an exterior configuration that fits within the space defined by the first and second walls of the base, an internal relief that receives the second wall of the base, and a central opening that receives a plunger rod; and, a plunger rod that is connected to the plunger and has a height sufficient to extend from the floor of the base to an aperture in the upper surface of the housing; whereby the electrical element controls movement of the plunger and the plunger rod and causes the plunge rod to extend outwardly and retract inwardly through the aperture in the upper surface of the housing. 2. An actuation element for a magnetic actuator having a housing that encloses an electrical element and upper and lower surfaces that have apertures on a common centerline, the actuation element comprising:
a base that fits within and closes the aperture in the lower surface and has a floor, a first wall of a predetermined height and a second wall that is interior to and spaced from the first wall and has a predetermined height that is less than the predetermined height of the first wall so there is open space between the first and second walls and open space that is above the second wall and within the first wall; and, a plunger and a rod member wherein the plunger has an exterior configuration that fits within the space defined by the first and second walls and a central relief dimensioned to receive the second wall within the relief, and a plunger rod having a height sufficient to extend from the floor of the base to the aperture in the upper surface of the housing. 3. A linear actuator, comprising:
a housing that has a first member with a planar surface defining a central opening and a circumferential wall defining an open interior space, and a second member that joins the circumferential wall and closes the interior space, the second member has a central opening on a centerline with the central opening of the planar surface; a magnet element that encircles the central opening; a base that defines a lower interior surface for the housing and fits within and closes an aperture in the second member, the base has a first wall of a predetermined height and a second wall that is spaced from the first wall and has a smaller predetermined height than the first wall so there is open space between the first and second walls and open space that is above the second wall and within the first wall; and, a plunger and a rod combination where the plunger has an exterior configuration that fits within the space defined by the first and second walls and a central relief configured to receive the second wall within the relief, and the rod has a height sufficient to extend from the lower interior surface of the base to the aperture in an upper surface of the housing. 4. A linear actuator, comprising:
a housing that has an upper surface, a circumferential wall, and a cover that define an interior space, the upper surface and the cover have apertures on a common centerline, and the cover has a base that fits within and closes the aperture in the cover; the base has a floor, a first wall of a predetermined height and a second wall that is interior to and spaced from the first wall and has a predetermined height that is less than the predetermined height of the first wall so there is open space between the first and second walls and open space that is above the second wall and within the first wall; an electrical element that is positioned between the first wall of the base and the circumferential wall of the housing and generates a current; a plunger having a body with an exterior that fits within the first wall of the base and an interior relief that fits over the second wall of the base, and a plunger rod extending through the center of the plunger body; the plunger rod having a height sufficient to extend from the floor of the base to an aperture in the upper surface of the housing, and moves outwardly and inwardly through the aperture in the upper surface of the housing in response to current generated by the electrical element. 5. The linear actuator of claim 4 wherein, the first and second wall of the base and the plunder body are tubular. 6. The linear actuator of claim 4 wherein, a bearing at the upper surface of the housing and a bearing mounted on the second wall of the base guide the movement of the plunger rod. 7. The linear actuator of claim 4 wherein, the cover is positioned within the circumferential wall of the housing and the circumferential wall of the housing has a plurality of dependent tabs that maintain the cover's position within the circumferential wall of the housing. 8. The linear actuator of claim 4 wherein, the plunger has a predetermined diameter that is less than a predetermined interior diameter of the second wall of the base and there is an interior void formed between them. 9. The linear actuator of claim 8 wherein, the second wall of the base has an aperture that extends between the interior void and the interior relief of the plunger body. 10. A linear actuator container for containing an electrical element, a plunger that is controlled by the electrical element and a plunger rod that guides the plunger movement within the container, the container comprising:
a housing with an upper surface and a dependent circumferential wall with a lower portion that includes a plurality of tabs, the circumferential wall has a predetermined height between the upper surface and the lower portion that includes the plurality of tabs; and a lower surface member that joins with the dependent circumferential wall, at the predetermined height to enclose an electrical element, a plunger and a plunger rod, and is locked in place by the plurality of tabs. | 2,800 |
12,127 | 12,127 | 15,965,175 | 2,884 | A sensing probe may be formed of a diamond material comprising one or more spin defects that are configured to emit fluorescent light and are located no more than 50 nm from a sensing surface of the sensing probe. The sensing probe may include an optical outcoupling structure formed by the diamond material and configured to optically guide the fluorescent light toward an output end of the optical outcoupling structure. An optical detector may detect the fluorescent light that is emitted from the spin defects and that exits through the output end of the optical outcoupling structure after being optically guided therethrough. A mounting system may hold the sensing probe and control a distance between the sensing surface of the sensing probe and a surface of a sample while permitting relative motion between the sensing surface and the sample surface. | 1. A sensing probe formed of a diamond material, the sensing probe comprising:
one or more spin defects configured to emit fluorescent light; and an optical outcoupling structure formed by the diamond material, the optical outcoupling structure configured to optically guide the fluorescent light emitted by the one or more spin defects toward an output end of the optical outcoupling structure, wherein the one or more spin defects are located no more than 50 nm from a sensing surface of the sensing probe, and a decoherence time of the one or more spin defects is greater than 10 μsec; and wherein the sensing probe including the optical outcoupling structure is formed of a diamond component having at least one linear dimension greater than 1 μm in length. 2. The sensing probe of claim 1, wherein the one or more spin defects are located no more than 40 nm, 30 nm, 20 nm, 15 nm, 12 nm, or 10 nm from the sensing surface of the sensing probe. 3. The sensing probe of claim 1, wherein the one or more spin defects are NV− (nitrogen-vacancy) defects. 4. The sensing probe of claim 1, wherein a decoherence time of the one or more spin defects is greater than 50 μsec, 100 μsec, 200 μsec, 300 μsec, 500 μsec, or 700 μsec. 5. The sensing probe of claim 1, wherein the sensing probe including the optical outcoupling structure is formed of a single crystal diamond material. 6. The sensing probe of claim 1, wherein the optical outcoupling structure is formed by one of: a nanopillar, a solid immersion lens; or via internal reflection. 7. The sensing probe of claim 6, wherein the optical outcoupling structure is formed of a nanopillar. 8. The sensing probe of claim 7, wherein the nanopillar has a diameter between 100 nm and 300 nm, and a length between 0.5 μm and 5 μm. 9. The sensing probe of claim 1, wherein the sensing probe comprises no more than 50, 30, 10, 5, 3, 2, or 1 spin defects located no more than 50 nm from the sensing surface and optically coupled to the optical outcoupling structure. 10. The sensing probe of claim 1, wherein the sensing probe comprises more than 50 spin defects in the form of a layer located no more than 50 nm from the sensing surface and optically coupled to the optical outcoupling structure. 11. A system comprising:
a sensing probe formed of a diamond material, the sensing probe comprising one or more spin defects configured to emit fluorescent light, and an optical outcoupling structure formed by the diamond material, the optical outcoupling structure configured to optically guide the fluorescent light emitted by the one or more spin defects toward an output end of the optical outcoupling structure,
wherein the one or more spin defects are located no more than 50 nm from a sensing surface of the sensing probe, and a decoherence time of the one or more spin defects is greater than 10 μsec, and wherein the sensing probe including the optical outcoupling structure is formed of a diamond component having at least one linear dimension greater than 1 μm in length;
an optical excitation source configured to generate excitation light directed to the one or more spin defects causing the one or more spin defects to fluoresce;
an optical detector configured to detect the fluorescent light that is emitted from the one or more spin defects and that exits through the output end of the optical outcoupling structure after being optically guided therethough; and
a mounting system configured to hold the sensing probe and control a distance between the sensing surface of the sensing probe and a surface of a sample while permitting relative motion between the sensing surface of the sensing probe and the sample surface. 12. The system of claim 11, wherein the mounting system comprises an AFM (atomic force microscope). 13. The system of claim 11, comprising an optical microscope coupled to the mounting system and configured to optically address and readout the one or more spin defects. 14. The system of claim 11, further comprising a microwave source, and wherein the microwave source is configured to generate microwaves tuned to a resonant frequency of at least one of the spin defects. 15. The system of claim 14, wherein the one or more spin defects are NV defects, and wherein the system is configured to detect an external magnetic field by measuring a Zeeman shift of a spin state of the NV defects. 16. The system of claim 15, wherein the microwaves comprise a spin-decoupling sequence of pulses, and wherein the sequence includes at least one of:
a Hahn spin-echo pulse sequence;
a CPMG (Carr Purcell Meiboom Gill) pulse sequence;
an XY pulse sequence; and
a MREVB pulse sequence. 17. The system of claim 1, wherein the system is configured to have an AC magnetic field detection sensitivity better than 200, 100, 75, 60, 50, 25, 10, or 5 nT Hz −1/2. 18. The system of claim 11, wherein the system is configured to have a DC magnetic field detection sensitivity better than 50, 20, 10, 6, 4, 1, or 0.5 μT Hz −1/2. 19. The system of claim 11, wherein the system is configured to resolve single spin defects in a sample. 20. The system of claim 11, wherein required integration time for single spin imaging with a signal to noise ratio of 2 is less than 5 mins, 3 mins, 2 mins, 1 min, 30 seconds, 15 seconds, 10 seconds, 5 seconds, 2 seconds, 1 second, or 0.5 second. | A sensing probe may be formed of a diamond material comprising one or more spin defects that are configured to emit fluorescent light and are located no more than 50 nm from a sensing surface of the sensing probe. The sensing probe may include an optical outcoupling structure formed by the diamond material and configured to optically guide the fluorescent light toward an output end of the optical outcoupling structure. An optical detector may detect the fluorescent light that is emitted from the spin defects and that exits through the output end of the optical outcoupling structure after being optically guided therethrough. A mounting system may hold the sensing probe and control a distance between the sensing surface of the sensing probe and a surface of a sample while permitting relative motion between the sensing surface and the sample surface.1. A sensing probe formed of a diamond material, the sensing probe comprising:
one or more spin defects configured to emit fluorescent light; and an optical outcoupling structure formed by the diamond material, the optical outcoupling structure configured to optically guide the fluorescent light emitted by the one or more spin defects toward an output end of the optical outcoupling structure, wherein the one or more spin defects are located no more than 50 nm from a sensing surface of the sensing probe, and a decoherence time of the one or more spin defects is greater than 10 μsec; and wherein the sensing probe including the optical outcoupling structure is formed of a diamond component having at least one linear dimension greater than 1 μm in length. 2. The sensing probe of claim 1, wherein the one or more spin defects are located no more than 40 nm, 30 nm, 20 nm, 15 nm, 12 nm, or 10 nm from the sensing surface of the sensing probe. 3. The sensing probe of claim 1, wherein the one or more spin defects are NV− (nitrogen-vacancy) defects. 4. The sensing probe of claim 1, wherein a decoherence time of the one or more spin defects is greater than 50 μsec, 100 μsec, 200 μsec, 300 μsec, 500 μsec, or 700 μsec. 5. The sensing probe of claim 1, wherein the sensing probe including the optical outcoupling structure is formed of a single crystal diamond material. 6. The sensing probe of claim 1, wherein the optical outcoupling structure is formed by one of: a nanopillar, a solid immersion lens; or via internal reflection. 7. The sensing probe of claim 6, wherein the optical outcoupling structure is formed of a nanopillar. 8. The sensing probe of claim 7, wherein the nanopillar has a diameter between 100 nm and 300 nm, and a length between 0.5 μm and 5 μm. 9. The sensing probe of claim 1, wherein the sensing probe comprises no more than 50, 30, 10, 5, 3, 2, or 1 spin defects located no more than 50 nm from the sensing surface and optically coupled to the optical outcoupling structure. 10. The sensing probe of claim 1, wherein the sensing probe comprises more than 50 spin defects in the form of a layer located no more than 50 nm from the sensing surface and optically coupled to the optical outcoupling structure. 11. A system comprising:
a sensing probe formed of a diamond material, the sensing probe comprising one or more spin defects configured to emit fluorescent light, and an optical outcoupling structure formed by the diamond material, the optical outcoupling structure configured to optically guide the fluorescent light emitted by the one or more spin defects toward an output end of the optical outcoupling structure,
wherein the one or more spin defects are located no more than 50 nm from a sensing surface of the sensing probe, and a decoherence time of the one or more spin defects is greater than 10 μsec, and wherein the sensing probe including the optical outcoupling structure is formed of a diamond component having at least one linear dimension greater than 1 μm in length;
an optical excitation source configured to generate excitation light directed to the one or more spin defects causing the one or more spin defects to fluoresce;
an optical detector configured to detect the fluorescent light that is emitted from the one or more spin defects and that exits through the output end of the optical outcoupling structure after being optically guided therethough; and
a mounting system configured to hold the sensing probe and control a distance between the sensing surface of the sensing probe and a surface of a sample while permitting relative motion between the sensing surface of the sensing probe and the sample surface. 12. The system of claim 11, wherein the mounting system comprises an AFM (atomic force microscope). 13. The system of claim 11, comprising an optical microscope coupled to the mounting system and configured to optically address and readout the one or more spin defects. 14. The system of claim 11, further comprising a microwave source, and wherein the microwave source is configured to generate microwaves tuned to a resonant frequency of at least one of the spin defects. 15. The system of claim 14, wherein the one or more spin defects are NV defects, and wherein the system is configured to detect an external magnetic field by measuring a Zeeman shift of a spin state of the NV defects. 16. The system of claim 15, wherein the microwaves comprise a spin-decoupling sequence of pulses, and wherein the sequence includes at least one of:
a Hahn spin-echo pulse sequence;
a CPMG (Carr Purcell Meiboom Gill) pulse sequence;
an XY pulse sequence; and
a MREVB pulse sequence. 17. The system of claim 1, wherein the system is configured to have an AC magnetic field detection sensitivity better than 200, 100, 75, 60, 50, 25, 10, or 5 nT Hz −1/2. 18. The system of claim 11, wherein the system is configured to have a DC magnetic field detection sensitivity better than 50, 20, 10, 6, 4, 1, or 0.5 μT Hz −1/2. 19. The system of claim 11, wherein the system is configured to resolve single spin defects in a sample. 20. The system of claim 11, wherein required integration time for single spin imaging with a signal to noise ratio of 2 is less than 5 mins, 3 mins, 2 mins, 1 min, 30 seconds, 15 seconds, 10 seconds, 5 seconds, 2 seconds, 1 second, or 0.5 second. | 2,800 |
12,128 | 12,128 | 16,409,488 | 2,896 | In a method for monitoring a rotating electric machine (1) that is fed by a converter and for diagnosing faults of said rotating electric machine, a current signature (I1, I2, I3) of output signals of the converter is recorded, the current signature (I1, I2, I3) is transformed, and the transformed current signature (A) is evaluated in at least one frequency band in order to detect damage to the machine (1). | 1. A method for monitoring and fault diagnosis of a rotating electric machine, including:
receiving input from a converter; recording a current signature of output signals of the converter; performing a transformation of the current signature to yield a transformed current signature, including performing at least one fast Fourier transform using a filter function; determining a transformed reference current signature, the transformed reference current signature representing a damage-free state of the machine; and evaluating the transformed current signature in at least one frequency band in order to detect damage to the machine, including:
applying a frequency dependent tolerance band predetermined in a value range of the transformed current signature, wherein the frequency dependent tolerance band is predetermined such that the transformed reference current signature lies within the frequency dependent tolerance band; and
determining that damage has occurred based on a determination that transformed current signature lies outside the frequency dependent tolerance band in the case of at least one frequency. 2. The method according to claim 1, wherein, in the evaluation for the transformed current signature at least one particular type of damage is determined for a current transformed feature. 3. The method according to claim 2, wherein the current transformed feature is determined by comparing transformed current signature with a reference in the evaluation of the transformation. 4. The method according to claim 1, wherein the damage determined to the machine includes determining a rotor bar break of rotor bars of a rotor, field asymmetries of an electric field of a rotor, or eccentricities of a rotor based on upon particular current characteristics to the type of damage. 5. The method according to claim 1, wherein the input is a three-phase converter current and the transformed current signature includes a component formed by the symmetrical three-phase current. 6. The method according to claim 5, wherein the transformed current signature includes components of a symmetrical three-phase current. 7. The method according to claim 1, wherein a characteristic of the input comprises amplitude modulation. 8. The method according to claim 1, further comprising performing a fast Fourier transform of Hilbert transform of amplitude modulation of the input. 9. The method according to claim 1, further comprising automatically and continuously monitoring the machine, and when damage is detected, automatically generating an alert. | In a method for monitoring a rotating electric machine (1) that is fed by a converter and for diagnosing faults of said rotating electric machine, a current signature (I1, I2, I3) of output signals of the converter is recorded, the current signature (I1, I2, I3) is transformed, and the transformed current signature (A) is evaluated in at least one frequency band in order to detect damage to the machine (1).1. A method for monitoring and fault diagnosis of a rotating electric machine, including:
receiving input from a converter; recording a current signature of output signals of the converter; performing a transformation of the current signature to yield a transformed current signature, including performing at least one fast Fourier transform using a filter function; determining a transformed reference current signature, the transformed reference current signature representing a damage-free state of the machine; and evaluating the transformed current signature in at least one frequency band in order to detect damage to the machine, including:
applying a frequency dependent tolerance band predetermined in a value range of the transformed current signature, wherein the frequency dependent tolerance band is predetermined such that the transformed reference current signature lies within the frequency dependent tolerance band; and
determining that damage has occurred based on a determination that transformed current signature lies outside the frequency dependent tolerance band in the case of at least one frequency. 2. The method according to claim 1, wherein, in the evaluation for the transformed current signature at least one particular type of damage is determined for a current transformed feature. 3. The method according to claim 2, wherein the current transformed feature is determined by comparing transformed current signature with a reference in the evaluation of the transformation. 4. The method according to claim 1, wherein the damage determined to the machine includes determining a rotor bar break of rotor bars of a rotor, field asymmetries of an electric field of a rotor, or eccentricities of a rotor based on upon particular current characteristics to the type of damage. 5. The method according to claim 1, wherein the input is a three-phase converter current and the transformed current signature includes a component formed by the symmetrical three-phase current. 6. The method according to claim 5, wherein the transformed current signature includes components of a symmetrical three-phase current. 7. The method according to claim 1, wherein a characteristic of the input comprises amplitude modulation. 8. The method according to claim 1, further comprising performing a fast Fourier transform of Hilbert transform of amplitude modulation of the input. 9. The method according to claim 1, further comprising automatically and continuously monitoring the machine, and when damage is detected, automatically generating an alert. | 2,800 |
12,129 | 12,129 | 16,685,074 | 2,822 | Embodiments of the disclosure generally relate to a layer stack containing a dielectric layer having a high K value capable of improving semiconductor display device electrical performance. The layer stack includes a channel layer containing an amorphous silicon layer disposed on a substrate and a gate insulating layer disposed on the channel layer. The gate insulating layer contains a silicon dioxide layer disposed on the channel layer, a zirconium dioxide layer disposed on the silicon dioxide layer, and an interface layer disposed on the zirconium dioxide layer and containing titanium oxide or aluminum oxide. The zirconium dioxide layer is disposed between the silicon dioxide layer and the interface layer and has a thickness of about 250 Å or greater, the gate insulating layer has a K value of about 20 to about 50, and the silicon dioxide layer is disposed between the channel layer and the zirconium dioxide layer. | 1. A layer stack, comprising:
a channel layer comprising an amorphous silicon layer and disposed on a substrate; and a gate insulating layer disposed on the channel layer, wherein the gate insulating layer comprises:
a silicon dioxide layer disposed on the channel layer;
a zirconium dioxide layer disposed on the silicon dioxide layer; and
an interface layer disposed on the zirconium dioxide layer and comprising titanium oxide or aluminum oxide,
wherein the zirconium dioxide layer is disposed between the silicon dioxide layer and the interface layer and has a thickness of about 250 Å or greater,
wherein the gate insulating layer has a K value ranging from about 20 to about 50, and
wherein the silicon dioxide layer is disposed between the channel layer and the zirconium dioxide layer. 2. The layer stack of claim 1, wherein the interface layer comprises titanium oxide. 3. The layer stack of claim 1, wherein the interface layer comprises aluminum oxide. 4. The layer stack of claim 1, wherein the interface layer has a thickness ranging from about 2 Å to about 100 Å. 5. The layer stack of claim 1, wherein the zirconium dioxide layer has a thickness ranging from about 250 Å to about 600 Å. 6. The layer stack of claim 1, further comprising a metal gate layer, wherein the metal gate layer is disposed on top of the zirconium dioxide layer, and wherein the zirconium dioxide layer is disposed between the silicon dioxide layer and the metal gate layer. 7. The layer stack of claim 6, wherein the metal gate layer comprises aluminum, titanium, or copper. 8. The layer stack of claim 1, wherein the silicon dioxide layer has a thickness ranging from about 2 Å to about 100 Å. 9. The layer stack of claim 1, wherein the silicon dioxide layer has a K value ranging from about 3 to about 5, and wherein the zirconium dioxide layer has a K value ranging from about 20 to about 50. 10. A layer stack, comprising:
a substrate; a channel layer disposed on the substrate; and a gate insulating layer disposed on the channel layer, wherein the gate insulating layer comprises:
a first interface layer;
a second interface layer; and
a high k dielectric layer between the first interface layer and the second interface layer, wherein the gate insulating layer has a K value ranging from about 20 to about 50. 11. The layer stack of claim 10, wherein the first interface layer comprises silicon dioxide, and wherein the second interface layer comprises titanium dioxide or aluminum oxide. 12. The layer stack of claim 10, wherein the high k dielectric layer is a material selected from the group consisting of zirconium dioxide, hafnium dioxide, titanium dioxide, and aluminum oxide. 13. The layer stack of claim 12, wherein the high k dielectric layer has a thickness ranging from about 250 Å to about 900 Å. 14. The layer stack of claim 10, wherein the channel layer comprises amorphous silicon, low-temperature polycrystalline silicon (LTPS), or other metal oxide semiconductor material. 15. The layer stack of claim 10, wherein the first interface layer has a thickness ranging from about 2 Å to about 100 Å. 16. A layer stack, comprising:
a substrate; a channel layer disposed on the substrate; and a gate insulating layer disposed on the channel layer, wherein the gate insulating layer comprises:
an interface layer disposed on the channel layer; and
a high k dielectric layer disposed on the interface layer, wherein the gate insulating layer has a K value ranging from about 20 to about 50. 17. The layer stack of claim 16, wherein the interface layer comprises silicon dioxide and has a thickness ranging from about 2 Å to about 100 Å. 18. The layer stack of claim 16, wherein the high k dielectric layer is a material selected from the group consisting of zirconium dioxide, hafnium dioxide, titanium dioxide, and aluminum oxide, and wherein the high k dielectric layer has a thickness ranging from about 250 Å to about 900 Å. 19. The layer stack of claim 16, wherein the channel layer comprises amorphous silicon, low-temperature polycrystalline silicon (LTPS), or other metal oxide semiconductor material. 20. The layer stack of claim 16, further comprising a metal layer disposed on the gate insulating layer. | Embodiments of the disclosure generally relate to a layer stack containing a dielectric layer having a high K value capable of improving semiconductor display device electrical performance. The layer stack includes a channel layer containing an amorphous silicon layer disposed on a substrate and a gate insulating layer disposed on the channel layer. The gate insulating layer contains a silicon dioxide layer disposed on the channel layer, a zirconium dioxide layer disposed on the silicon dioxide layer, and an interface layer disposed on the zirconium dioxide layer and containing titanium oxide or aluminum oxide. The zirconium dioxide layer is disposed between the silicon dioxide layer and the interface layer and has a thickness of about 250 Å or greater, the gate insulating layer has a K value of about 20 to about 50, and the silicon dioxide layer is disposed between the channel layer and the zirconium dioxide layer.1. A layer stack, comprising:
a channel layer comprising an amorphous silicon layer and disposed on a substrate; and a gate insulating layer disposed on the channel layer, wherein the gate insulating layer comprises:
a silicon dioxide layer disposed on the channel layer;
a zirconium dioxide layer disposed on the silicon dioxide layer; and
an interface layer disposed on the zirconium dioxide layer and comprising titanium oxide or aluminum oxide,
wherein the zirconium dioxide layer is disposed between the silicon dioxide layer and the interface layer and has a thickness of about 250 Å or greater,
wherein the gate insulating layer has a K value ranging from about 20 to about 50, and
wherein the silicon dioxide layer is disposed between the channel layer and the zirconium dioxide layer. 2. The layer stack of claim 1, wherein the interface layer comprises titanium oxide. 3. The layer stack of claim 1, wherein the interface layer comprises aluminum oxide. 4. The layer stack of claim 1, wherein the interface layer has a thickness ranging from about 2 Å to about 100 Å. 5. The layer stack of claim 1, wherein the zirconium dioxide layer has a thickness ranging from about 250 Å to about 600 Å. 6. The layer stack of claim 1, further comprising a metal gate layer, wherein the metal gate layer is disposed on top of the zirconium dioxide layer, and wherein the zirconium dioxide layer is disposed between the silicon dioxide layer and the metal gate layer. 7. The layer stack of claim 6, wherein the metal gate layer comprises aluminum, titanium, or copper. 8. The layer stack of claim 1, wherein the silicon dioxide layer has a thickness ranging from about 2 Å to about 100 Å. 9. The layer stack of claim 1, wherein the silicon dioxide layer has a K value ranging from about 3 to about 5, and wherein the zirconium dioxide layer has a K value ranging from about 20 to about 50. 10. A layer stack, comprising:
a substrate; a channel layer disposed on the substrate; and a gate insulating layer disposed on the channel layer, wherein the gate insulating layer comprises:
a first interface layer;
a second interface layer; and
a high k dielectric layer between the first interface layer and the second interface layer, wherein the gate insulating layer has a K value ranging from about 20 to about 50. 11. The layer stack of claim 10, wherein the first interface layer comprises silicon dioxide, and wherein the second interface layer comprises titanium dioxide or aluminum oxide. 12. The layer stack of claim 10, wherein the high k dielectric layer is a material selected from the group consisting of zirconium dioxide, hafnium dioxide, titanium dioxide, and aluminum oxide. 13. The layer stack of claim 12, wherein the high k dielectric layer has a thickness ranging from about 250 Å to about 900 Å. 14. The layer stack of claim 10, wherein the channel layer comprises amorphous silicon, low-temperature polycrystalline silicon (LTPS), or other metal oxide semiconductor material. 15. The layer stack of claim 10, wherein the first interface layer has a thickness ranging from about 2 Å to about 100 Å. 16. A layer stack, comprising:
a substrate; a channel layer disposed on the substrate; and a gate insulating layer disposed on the channel layer, wherein the gate insulating layer comprises:
an interface layer disposed on the channel layer; and
a high k dielectric layer disposed on the interface layer, wherein the gate insulating layer has a K value ranging from about 20 to about 50. 17. The layer stack of claim 16, wherein the interface layer comprises silicon dioxide and has a thickness ranging from about 2 Å to about 100 Å. 18. The layer stack of claim 16, wherein the high k dielectric layer is a material selected from the group consisting of zirconium dioxide, hafnium dioxide, titanium dioxide, and aluminum oxide, and wherein the high k dielectric layer has a thickness ranging from about 250 Å to about 900 Å. 19. The layer stack of claim 16, wherein the channel layer comprises amorphous silicon, low-temperature polycrystalline silicon (LTPS), or other metal oxide semiconductor material. 20. The layer stack of claim 16, further comprising a metal layer disposed on the gate insulating layer. | 2,800 |
12,130 | 12,130 | 16,503,982 | 2,818 | The present disclosure relates to semiconductor structures and, more particularly, to stacked gate transistors and methods of manufacture. The structure includes a stacked gate structure having a plurality of transistors with at least one floating node and at least one node to either ground or a supply voltage, and a contact to either of the ground or supply voltage and the at least one floating node being devoid of any contact. | 1. A structure comprising a stacked gate structure comprising a plurality of transistors with at least one floating node and at least one node to either ground or a supply voltage, and a contact to either of the ground or supply voltage and the at least one floating node being devoid of any contact. 2. The structure of claim 1, wherein the at least one floating node is a diffusion region. 3. The structure of claim 2, wherein the diffusion region is a doped epitaxial region. 4. The structure of claim 3, wherein the plurality of transistors are in series. 5. The structure of claim 4, wherein the plurality of transistors in series includes a first transistor having the node for the voltage and a last transistor having a node for the ground, with separate contacts being provided to the nodes for the supply voltage and the ground, respectively, and any floating nodes being devoid of a contact. 6. The structure of claim 5, wherein the node for the supply voltage and the node for the ground are diffusion regions. 7. The structure of claim 1, wherein the transistors are NFETs in series. 8. The structure of claim 1, wherein the transistors are PFETs in series. 9. The structure of claim 1, wherein the transistors are finFETs. 10. The structure of claim 9, wherein the at least one floating node, the node to ground and the node to the supply voltage are provided in a fin composed of substrate material. 11. A structure comprising:
multiple FET devices connected in series, including a first FET having a diffusion region and a last FET device having a diffusion region; a first contact to the diffusion region of the first FET and a second contact to the diffusion region of the last FET; and at least one floating diffusion region between the multiple FET devices, the at least one floating diffusion region being devoid of contacts. 12. The structure of claim 11, wherein the diffusion regions of the first FET and the second FET and the at least one floating diffusion region are raised epitaxial material. 13. The structure of claim 12, wherein the raised epitaxial material are raised source and drain regions. 14. The structure of claim 12, wherein the first FET device and the last FET are at opposite ends of the series. 15. The structure of claim 14, wherein the first contact to the diffusion region of the first FET connects to a voltage supply and the second contact to the diffusion region of the last FET connects to ground. 16. The structure of claim 15, wherein the at least one floating diffusion region are multiple floating nodes in series, between the first FET and the last FET. 17. The structure of claim 16, wherein the multiple floating nodes are associated with multiple respective transistors. 18. The structure of claim 11, wherein the multiple FET devices are finFET devices. 19. The structure of claim 18, wherein the diffusion region of the first FET, the diffusion region of the last FET and the at least one floating diffusion are provided in a fin composed of substrate material. 20. A structure comprising:
a first FET having an epitaxial diffusion region connecting to a voltage supply; a second FET having an epitaxial diffusion region connected to ground; at least one additional FET connecting in series with the first FET and the second FET and having a floating node devoid of any contacts; a first contact connecting the epitaxial diffusion region of the first FET to the voltage supply; and a second contact connecting the epitaxial diffusion region of the second FET to the voltage supply. | The present disclosure relates to semiconductor structures and, more particularly, to stacked gate transistors and methods of manufacture. The structure includes a stacked gate structure having a plurality of transistors with at least one floating node and at least one node to either ground or a supply voltage, and a contact to either of the ground or supply voltage and the at least one floating node being devoid of any contact.1. A structure comprising a stacked gate structure comprising a plurality of transistors with at least one floating node and at least one node to either ground or a supply voltage, and a contact to either of the ground or supply voltage and the at least one floating node being devoid of any contact. 2. The structure of claim 1, wherein the at least one floating node is a diffusion region. 3. The structure of claim 2, wherein the diffusion region is a doped epitaxial region. 4. The structure of claim 3, wherein the plurality of transistors are in series. 5. The structure of claim 4, wherein the plurality of transistors in series includes a first transistor having the node for the voltage and a last transistor having a node for the ground, with separate contacts being provided to the nodes for the supply voltage and the ground, respectively, and any floating nodes being devoid of a contact. 6. The structure of claim 5, wherein the node for the supply voltage and the node for the ground are diffusion regions. 7. The structure of claim 1, wherein the transistors are NFETs in series. 8. The structure of claim 1, wherein the transistors are PFETs in series. 9. The structure of claim 1, wherein the transistors are finFETs. 10. The structure of claim 9, wherein the at least one floating node, the node to ground and the node to the supply voltage are provided in a fin composed of substrate material. 11. A structure comprising:
multiple FET devices connected in series, including a first FET having a diffusion region and a last FET device having a diffusion region; a first contact to the diffusion region of the first FET and a second contact to the diffusion region of the last FET; and at least one floating diffusion region between the multiple FET devices, the at least one floating diffusion region being devoid of contacts. 12. The structure of claim 11, wherein the diffusion regions of the first FET and the second FET and the at least one floating diffusion region are raised epitaxial material. 13. The structure of claim 12, wherein the raised epitaxial material are raised source and drain regions. 14. The structure of claim 12, wherein the first FET device and the last FET are at opposite ends of the series. 15. The structure of claim 14, wherein the first contact to the diffusion region of the first FET connects to a voltage supply and the second contact to the diffusion region of the last FET connects to ground. 16. The structure of claim 15, wherein the at least one floating diffusion region are multiple floating nodes in series, between the first FET and the last FET. 17. The structure of claim 16, wherein the multiple floating nodes are associated with multiple respective transistors. 18. The structure of claim 11, wherein the multiple FET devices are finFET devices. 19. The structure of claim 18, wherein the diffusion region of the first FET, the diffusion region of the last FET and the at least one floating diffusion are provided in a fin composed of substrate material. 20. A structure comprising:
a first FET having an epitaxial diffusion region connecting to a voltage supply; a second FET having an epitaxial diffusion region connected to ground; at least one additional FET connecting in series with the first FET and the second FET and having a floating node devoid of any contacts; a first contact connecting the epitaxial diffusion region of the first FET to the voltage supply; and a second contact connecting the epitaxial diffusion region of the second FET to the voltage supply. | 2,800 |
12,131 | 12,131 | 15,940,999 | 2,882 | A manufacturing method of a projection apparatus is provided. The manufacturing method of the projection apparatus includes: classifying a light valve by an optical jig; selecting an aperture stop with a size corresponding to classification of the light valve; and assembling the light valve and the aperture stop to form the projection apparatus. | 1. A manufacturing method of a projection apparatus comprising:
classifying a plurality of digital micro-mirror devices (DMDs) into a first group and a second group according to off-state brightness of each of the DMDs, wherein each of micro-mirrors of the DMDs has two different tilting axes; and assembling one of following sets into the projection apparatus: Set (1): a DMD of the first group with a first aperture stop; Set (2): a DMD of the second group with a second aperture stop, wherein off-state brightness of the first group is less than off-state brightness of the second group, and a light blocking area of the first aperture stop is less than a light blocking area of the second aperture stop. 2. The manufacturing method of the projection apparatus according to claim 1, wherein the DMDs are classified into the first group, the second group, and a third group according to the off-state brightness of each of the DMDs, and said following sets further comprises Set (3): a DMD of the third group with a third aperture stop, and wherein off-state brightness of the third group is between the off-state brightness of the first group and the off-state brightness of the second group, and a light blocking area of the third aperture stop is between the light blocking area of the first aperture stop and the light blocking area of the second aperture stop. 3. The manufacturing method of the projection apparatus according to claim 1, wherein the DMDs are classified by an optical jig, and the optical jig comprises a lens with a constant aperture to project light from each of the DMDs onto an image plane. 4. The manufacturing method of the projection apparatus according to claim 3, wherein the optical jig further comprises an optical meter configured to measure the off-state brightness of the DMD on the image plane. 5. The manufacturing method of the projection apparatus according to claim 4, wherein the optical meter is configured to measure illuminance at a center of the light from each of the DMDs on the image plane. 6. The manufacturing method of the projection apparatus according to claim 1, wherein the aperture stop has an aperture having two straight sides, a rotation direction of an on-state light beam to an off-state light beam of the DMD parallel to the DMD and an extension direction of each of the two straight sides make an included angle, and the included angle is substantially 45 degrees. 7. The manufacturing method of the projection apparatus according to claim 1 further comprising:
after classifying the DMD into the first group and the second group, respectively assigning a first part number and a second part number to the first group and the second group; and
putting the first group with the first part number and the second group with the second part number into storage. 8. A manufacturing method of a projection apparatus comprising:
classifying a plurality of digital micro-mirror devices (DMDs) into a first group and a second group according to off-state brightness of each of the DMDs, wherein a diffracted light of an off-state of each of the DMDs overlaps a path of an on-state light beam of the DMD; and assembling one of following sets into the projection apparatus: Set (1): a DMD of the first group with a first aperture stop; Set (2): a DMD of the second group with a second aperture stop, wherein off-state brightness of the first group is less than off-state brightness of the second group, and a light blocking area of the first aperture stop is less than a light blocking area of the second aperture stop. 9. The manufacturing method of the projection apparatus according to claim 8, wherein the DMDs are classified into the first group, the second group, and a third group according to the off-state brightness of each of the DMDs, and said following sets further comprises Set (3): a DMD of the third group with a third aperture stop, and wherein off-state brightness of the third group is between the off-state brightness of the first group and the off-state brightness of the second group, and a light blocking area of the third aperture stop is between the light blocking area of the first aperture stop and the light blocking area of the second aperture stop. 10. The manufacturing method of the projection apparatus according to claim 8, wherein the DMDs are classified by an optical jig, and the optical jig comprises a lens with a constant aperture to project light from each of the DMDs onto an image plane. 11. The manufacturing method of the projection apparatus according to claim 10, wherein the optical jig further comprises an optical meter configured to measure the off-state brightness of the DMD on the image plane. 12. The manufacturing method of the projection apparatus according to claim 11, wherein the optical meter is configured to measure illuminance at a center of the light from each of the DMDs on the image plane. 13. The manufacturing method of the projection apparatus according to claim 8, wherein the aperture stop has an aperture having two straight sides, a rotation direction of an on-state light beam to an off-state light beam of the DMD parallel to the DMD and an extension direction of each of the two straight sides make an included angle, and the included angle is substantially 45 degrees. 14. The manufacturing method of the projection apparatus according to claim 8 further comprising:
after classifying the DMD into the first group and the second group, respectively assigning a first part number and a second part number to the first group and the second group; and
putting the first group with the first part number and the second group with the second part number into storage. 15. A manufacturing method of a projection apparatus comprising:
putting a light valve on an optical jig; providing a light beam to the light valve, wherein the light valve converts the light beam into an image beam, and the optical jig projects the image beam onto an image plane; measuring brightness on the image plane when the light valve in the off-state; classifying the light valve according to the brightness on the image plane; selecting an aperture stop with a size corresponding to classification of the light valve; and assembling the light valve and the aperture stop to form the projection apparatus. 16. The manufacturing method of the projection apparatus according to claim 15, wherein the optical jig comprises a lens with a constant aperture to project the image beam from the light valve onto the image plane, and an optical meter is configured to measure the brightness on the image plane. 17. The manufacturing method of the projection apparatus according to claim 15, wherein each class of the light valve corresponds to a different brightness range, and a class of the light valve corresponding to a brightness range having greater brightness corresponds to an aperture stop having a smaller aperture. 18. The manufacturing method of the projection apparatus according to claim 15, wherein the light valve is a digital micro-mirror device. 19. The manufacturing method of the projection apparatus according to claim 18, wherein the aperture stop has an aperture having two straight sides, a rotation direction of an on-state light beam to an off-state light beam of the light valve parallel to the light valve and an extension direction of each of the two straight sides make an included angle, and the included angle is substantially 45 degrees. 20. The manufacturing method of the projection apparatus according to claim 15 further comprising:
after classifying the light valve, assigning a part number to the light valve, wherein the part number corresponds to the classification of the light valve; and
putting the light valve with the part number into storage, wherein selecting the aperture stop with the size corresponding to the classification of the light valve is selecting the aperture stop with the size corresponding to the part number. | A manufacturing method of a projection apparatus is provided. The manufacturing method of the projection apparatus includes: classifying a light valve by an optical jig; selecting an aperture stop with a size corresponding to classification of the light valve; and assembling the light valve and the aperture stop to form the projection apparatus.1. A manufacturing method of a projection apparatus comprising:
classifying a plurality of digital micro-mirror devices (DMDs) into a first group and a second group according to off-state brightness of each of the DMDs, wherein each of micro-mirrors of the DMDs has two different tilting axes; and assembling one of following sets into the projection apparatus: Set (1): a DMD of the first group with a first aperture stop; Set (2): a DMD of the second group with a second aperture stop, wherein off-state brightness of the first group is less than off-state brightness of the second group, and a light blocking area of the first aperture stop is less than a light blocking area of the second aperture stop. 2. The manufacturing method of the projection apparatus according to claim 1, wherein the DMDs are classified into the first group, the second group, and a third group according to the off-state brightness of each of the DMDs, and said following sets further comprises Set (3): a DMD of the third group with a third aperture stop, and wherein off-state brightness of the third group is between the off-state brightness of the first group and the off-state brightness of the second group, and a light blocking area of the third aperture stop is between the light blocking area of the first aperture stop and the light blocking area of the second aperture stop. 3. The manufacturing method of the projection apparatus according to claim 1, wherein the DMDs are classified by an optical jig, and the optical jig comprises a lens with a constant aperture to project light from each of the DMDs onto an image plane. 4. The manufacturing method of the projection apparatus according to claim 3, wherein the optical jig further comprises an optical meter configured to measure the off-state brightness of the DMD on the image plane. 5. The manufacturing method of the projection apparatus according to claim 4, wherein the optical meter is configured to measure illuminance at a center of the light from each of the DMDs on the image plane. 6. The manufacturing method of the projection apparatus according to claim 1, wherein the aperture stop has an aperture having two straight sides, a rotation direction of an on-state light beam to an off-state light beam of the DMD parallel to the DMD and an extension direction of each of the two straight sides make an included angle, and the included angle is substantially 45 degrees. 7. The manufacturing method of the projection apparatus according to claim 1 further comprising:
after classifying the DMD into the first group and the second group, respectively assigning a first part number and a second part number to the first group and the second group; and
putting the first group with the first part number and the second group with the second part number into storage. 8. A manufacturing method of a projection apparatus comprising:
classifying a plurality of digital micro-mirror devices (DMDs) into a first group and a second group according to off-state brightness of each of the DMDs, wherein a diffracted light of an off-state of each of the DMDs overlaps a path of an on-state light beam of the DMD; and assembling one of following sets into the projection apparatus: Set (1): a DMD of the first group with a first aperture stop; Set (2): a DMD of the second group with a second aperture stop, wherein off-state brightness of the first group is less than off-state brightness of the second group, and a light blocking area of the first aperture stop is less than a light blocking area of the second aperture stop. 9. The manufacturing method of the projection apparatus according to claim 8, wherein the DMDs are classified into the first group, the second group, and a third group according to the off-state brightness of each of the DMDs, and said following sets further comprises Set (3): a DMD of the third group with a third aperture stop, and wherein off-state brightness of the third group is between the off-state brightness of the first group and the off-state brightness of the second group, and a light blocking area of the third aperture stop is between the light blocking area of the first aperture stop and the light blocking area of the second aperture stop. 10. The manufacturing method of the projection apparatus according to claim 8, wherein the DMDs are classified by an optical jig, and the optical jig comprises a lens with a constant aperture to project light from each of the DMDs onto an image plane. 11. The manufacturing method of the projection apparatus according to claim 10, wherein the optical jig further comprises an optical meter configured to measure the off-state brightness of the DMD on the image plane. 12. The manufacturing method of the projection apparatus according to claim 11, wherein the optical meter is configured to measure illuminance at a center of the light from each of the DMDs on the image plane. 13. The manufacturing method of the projection apparatus according to claim 8, wherein the aperture stop has an aperture having two straight sides, a rotation direction of an on-state light beam to an off-state light beam of the DMD parallel to the DMD and an extension direction of each of the two straight sides make an included angle, and the included angle is substantially 45 degrees. 14. The manufacturing method of the projection apparatus according to claim 8 further comprising:
after classifying the DMD into the first group and the second group, respectively assigning a first part number and a second part number to the first group and the second group; and
putting the first group with the first part number and the second group with the second part number into storage. 15. A manufacturing method of a projection apparatus comprising:
putting a light valve on an optical jig; providing a light beam to the light valve, wherein the light valve converts the light beam into an image beam, and the optical jig projects the image beam onto an image plane; measuring brightness on the image plane when the light valve in the off-state; classifying the light valve according to the brightness on the image plane; selecting an aperture stop with a size corresponding to classification of the light valve; and assembling the light valve and the aperture stop to form the projection apparatus. 16. The manufacturing method of the projection apparatus according to claim 15, wherein the optical jig comprises a lens with a constant aperture to project the image beam from the light valve onto the image plane, and an optical meter is configured to measure the brightness on the image plane. 17. The manufacturing method of the projection apparatus according to claim 15, wherein each class of the light valve corresponds to a different brightness range, and a class of the light valve corresponding to a brightness range having greater brightness corresponds to an aperture stop having a smaller aperture. 18. The manufacturing method of the projection apparatus according to claim 15, wherein the light valve is a digital micro-mirror device. 19. The manufacturing method of the projection apparatus according to claim 18, wherein the aperture stop has an aperture having two straight sides, a rotation direction of an on-state light beam to an off-state light beam of the light valve parallel to the light valve and an extension direction of each of the two straight sides make an included angle, and the included angle is substantially 45 degrees. 20. The manufacturing method of the projection apparatus according to claim 15 further comprising:
after classifying the light valve, assigning a part number to the light valve, wherein the part number corresponds to the classification of the light valve; and
putting the light valve with the part number into storage, wherein selecting the aperture stop with the size corresponding to the classification of the light valve is selecting the aperture stop with the size corresponding to the part number. | 2,800 |
12,132 | 12,132 | 15,749,550 | 2,846 | An actuator (1) comprises an electric motor (11) for moving an actuated part (2) to an actuated position. The actuator (1) further comprises a controller (10) connected to the electric motor (11) and configured to determine a motor current of the electric motor (11) and to detect motor rotations. The controller (10) is further configured to determine the actuated position by counting the motor rotations detected while the motor current is at or above a current threshold indicative of a load torque, and by not counting motor rotations detected while the motor current is below said current threshold. | 1. An actuator (1) comprising an electric motor for moving an actuated part (2) to an actuated position, and a controller (10) connected to the electric motor (11) and configured to detect motor rotations,
wherein the controller (10) is further configured to determine the actuated position by counting the motor rotations detected while the motor (11) is operating at or above a threshold indicative of a load torque, and by not counting motor rotations detected while the motor (11) is operating below said threshold. 2. The actuator (1) of claim 1, wherein the controller (10) is configured to determine a motor current of the electric motor (11), and to determine the actuated position by counting the motor rotations detected while the motor current is at or above a current threshold indicative of the load torque, and by not counting motor rotations detected while the motor current is below said current threshold. 3. The actuator (1) of claim 1, wherein the controller (10) is further configured to record a course of the motor current while the electric motor (11) moves the actuated part (2) from a first actuated position in a forward direction to a second actuated position, and from the second actuated position in a reverse direction to the first actuated position, and to define the current threshold from the recorded course of the motor current. 4. The actuator (1) of claim 3, wherein the controller (10) is configured to repeatedly record the course of the motor current, and to repeatedly define the current threshold from the recorded course of the motor current. 5. The actuator (1) of claim 2, wherein the controller (10) is further configured to detect a malfunctioning actuation of the actuated part (2) by checking whether the present motor current deviates by more than a set tolerance level from a reference value of the motor current expected at the present actuated position. 6. The actuator (1) of claim 2, wherein the controller (10) is further configured to detect a malfunctioning actuation of the actuated part (2) by checking whether the motor current exceeds a current threshold indicative of excessive torque while the actuated part (2) is being moved to the actuated position. 7. The actuator (1) of claim 2, wherein the controller (10) is further configured to detect a malfunctioning actuation of the actuated part (2) by checking whether the motor current reaches or exceeds a current threshold indicative of an end position when the actuated position is not the said end position. 8. The actuator (1) of claim 1, wherein the controller (10) is configured to determine a fluid flow through a valve controlled by the actuator (1), using a flow sensor, and to determine the actuated position by counting motor rotations detected while the fluid flow changes with a movement of the electric motor (11), and by not counting motor rotations detected while the fluid flow remains constant with a movement of the electric motor (11). 9. The actuator (1) of claim 1, wherein the controller (10) is further configured to detect a malfunctioning actuation of the actuated part (2) by checking whether an actuation time for moving the actuated part (2) from a first actuated position to a second actuated position exceeds a time threshold indicative of normal actuation time. 10. The actuator (1) of claim 1, wherein the controller (10) is further configured to detect an idle operation of the electric motor (11) by checking whether the motor rotations exceed a rotation threshold indicative of an end position of the motor (11). 11. The actuator (1) of claim 1, wherein the controller (10) is further configured to control the motor (11) to operate at a higher speed while the motor (11) is operating below said threshold, and to control the motor (11) to operate at a lower speed while the motor (11) is operating at or above said threshold. 12. A method for operating an actuator (1) which comprises an electric motor (11) for moving an actuated part (2) to an actuated position, and a controller (10) connected to the electric motor (11) and configured to detect motor rotations, wherein the method comprises:
determining in the controller (10) the actuated position by counting the motor rotations detected while the motor (11) is operating at or above a threshold indicative of a load torque, and by not counting motor rotations detected while the motor (11) is operating below said threshold. 13. The method of claim 12, wherein the method further comprises the controller (10) determining a motor current of the electric motor (11), and determining the actuated position by counting the motor rotations detected while the motor current is at or above a current threshold indicative of the load torque, and by not counting motor rotations detected while the motor current is below said current threshold. 14. The method of claim 13, wherein the method further comprises the controller (10) recording a course of the motor current while the electric motor (11) moves the actuated part (2) from a first actuated position in a forward direction to a second actuated position, and from the second actuated position in a reverse direction to the first actuated position, and defining the current threshold from the recorded course of the motor current. 15. The method of claim 14, wherein the method further comprises the controller (10) repeatedly recording the course of the motor current, and repeatedly defining the current threshold from the recorded course of the motor current. 16. The method of claim 13, wherein the method further comprises the controller (10) detecting a malfunctioning actuation of the actuated part (2) by checking whether the present motor current deviates by more than a set tolerance level from a reference value of the motor current expected at the present actuated position. 17. The method of claim 13, wherein the method further comprises the controller (10) detecting a malfunctioning actuation of the actuated part (2) by checking whether the motor current exceeds a current threshold indicative of excessive torque while the actuated part (2) is being moved to the actuated position. 18. The method of claim 13, wherein the method further comprises the controller (10) detecting a malfunctioning actuation of the actuated part (2) by checking whether the motor current reaches or exceeds a current threshold indicative of an end position when the actuated position is not the said end position. 19. The method of claim 12, wherein the method further comprises the controller (10) determining a fluid flow through a valve controlled by the actuator (1), using a flow sensor, and determining the actuated position by counting the motor rotations detected while the fluid flow changes with a movement of the electric motor (11), and by not counting motor rotations detected while the fluid flow remains constant with a movement of the electric motor (11). 20. The method of claim 12, wherein the method further comprises the controller (10) detecting a malfunctioning actuation of the actuated part (2) by checking whether an actuation time for moving the actuated part (2) from a first actuated position to a second actuated position exceeds a time threshold indicative of normal actuation time. 21. The method of claim 12, wherein the method further comprises the controller (10) detecting an idle operation of the electric motor (11) by checking whether the motor rotations exceed a rotation threshold indicative of an end position of the motor (11). 22. The method of claim 12, wherein the method further comprises the controller (10) controlling the motor (11) to operate at a higher speed while the motor (11) is operating below said threshold, and controlling the motor (11) to operate at a lower speed while the motor (11) is operating at or above said threshold. | An actuator (1) comprises an electric motor (11) for moving an actuated part (2) to an actuated position. The actuator (1) further comprises a controller (10) connected to the electric motor (11) and configured to determine a motor current of the electric motor (11) and to detect motor rotations. The controller (10) is further configured to determine the actuated position by counting the motor rotations detected while the motor current is at or above a current threshold indicative of a load torque, and by not counting motor rotations detected while the motor current is below said current threshold.1. An actuator (1) comprising an electric motor for moving an actuated part (2) to an actuated position, and a controller (10) connected to the electric motor (11) and configured to detect motor rotations,
wherein the controller (10) is further configured to determine the actuated position by counting the motor rotations detected while the motor (11) is operating at or above a threshold indicative of a load torque, and by not counting motor rotations detected while the motor (11) is operating below said threshold. 2. The actuator (1) of claim 1, wherein the controller (10) is configured to determine a motor current of the electric motor (11), and to determine the actuated position by counting the motor rotations detected while the motor current is at or above a current threshold indicative of the load torque, and by not counting motor rotations detected while the motor current is below said current threshold. 3. The actuator (1) of claim 1, wherein the controller (10) is further configured to record a course of the motor current while the electric motor (11) moves the actuated part (2) from a first actuated position in a forward direction to a second actuated position, and from the second actuated position in a reverse direction to the first actuated position, and to define the current threshold from the recorded course of the motor current. 4. The actuator (1) of claim 3, wherein the controller (10) is configured to repeatedly record the course of the motor current, and to repeatedly define the current threshold from the recorded course of the motor current. 5. The actuator (1) of claim 2, wherein the controller (10) is further configured to detect a malfunctioning actuation of the actuated part (2) by checking whether the present motor current deviates by more than a set tolerance level from a reference value of the motor current expected at the present actuated position. 6. The actuator (1) of claim 2, wherein the controller (10) is further configured to detect a malfunctioning actuation of the actuated part (2) by checking whether the motor current exceeds a current threshold indicative of excessive torque while the actuated part (2) is being moved to the actuated position. 7. The actuator (1) of claim 2, wherein the controller (10) is further configured to detect a malfunctioning actuation of the actuated part (2) by checking whether the motor current reaches or exceeds a current threshold indicative of an end position when the actuated position is not the said end position. 8. The actuator (1) of claim 1, wherein the controller (10) is configured to determine a fluid flow through a valve controlled by the actuator (1), using a flow sensor, and to determine the actuated position by counting motor rotations detected while the fluid flow changes with a movement of the electric motor (11), and by not counting motor rotations detected while the fluid flow remains constant with a movement of the electric motor (11). 9. The actuator (1) of claim 1, wherein the controller (10) is further configured to detect a malfunctioning actuation of the actuated part (2) by checking whether an actuation time for moving the actuated part (2) from a first actuated position to a second actuated position exceeds a time threshold indicative of normal actuation time. 10. The actuator (1) of claim 1, wherein the controller (10) is further configured to detect an idle operation of the electric motor (11) by checking whether the motor rotations exceed a rotation threshold indicative of an end position of the motor (11). 11. The actuator (1) of claim 1, wherein the controller (10) is further configured to control the motor (11) to operate at a higher speed while the motor (11) is operating below said threshold, and to control the motor (11) to operate at a lower speed while the motor (11) is operating at or above said threshold. 12. A method for operating an actuator (1) which comprises an electric motor (11) for moving an actuated part (2) to an actuated position, and a controller (10) connected to the electric motor (11) and configured to detect motor rotations, wherein the method comprises:
determining in the controller (10) the actuated position by counting the motor rotations detected while the motor (11) is operating at or above a threshold indicative of a load torque, and by not counting motor rotations detected while the motor (11) is operating below said threshold. 13. The method of claim 12, wherein the method further comprises the controller (10) determining a motor current of the electric motor (11), and determining the actuated position by counting the motor rotations detected while the motor current is at or above a current threshold indicative of the load torque, and by not counting motor rotations detected while the motor current is below said current threshold. 14. The method of claim 13, wherein the method further comprises the controller (10) recording a course of the motor current while the electric motor (11) moves the actuated part (2) from a first actuated position in a forward direction to a second actuated position, and from the second actuated position in a reverse direction to the first actuated position, and defining the current threshold from the recorded course of the motor current. 15. The method of claim 14, wherein the method further comprises the controller (10) repeatedly recording the course of the motor current, and repeatedly defining the current threshold from the recorded course of the motor current. 16. The method of claim 13, wherein the method further comprises the controller (10) detecting a malfunctioning actuation of the actuated part (2) by checking whether the present motor current deviates by more than a set tolerance level from a reference value of the motor current expected at the present actuated position. 17. The method of claim 13, wherein the method further comprises the controller (10) detecting a malfunctioning actuation of the actuated part (2) by checking whether the motor current exceeds a current threshold indicative of excessive torque while the actuated part (2) is being moved to the actuated position. 18. The method of claim 13, wherein the method further comprises the controller (10) detecting a malfunctioning actuation of the actuated part (2) by checking whether the motor current reaches or exceeds a current threshold indicative of an end position when the actuated position is not the said end position. 19. The method of claim 12, wherein the method further comprises the controller (10) determining a fluid flow through a valve controlled by the actuator (1), using a flow sensor, and determining the actuated position by counting the motor rotations detected while the fluid flow changes with a movement of the electric motor (11), and by not counting motor rotations detected while the fluid flow remains constant with a movement of the electric motor (11). 20. The method of claim 12, wherein the method further comprises the controller (10) detecting a malfunctioning actuation of the actuated part (2) by checking whether an actuation time for moving the actuated part (2) from a first actuated position to a second actuated position exceeds a time threshold indicative of normal actuation time. 21. The method of claim 12, wherein the method further comprises the controller (10) detecting an idle operation of the electric motor (11) by checking whether the motor rotations exceed a rotation threshold indicative of an end position of the motor (11). 22. The method of claim 12, wherein the method further comprises the controller (10) controlling the motor (11) to operate at a higher speed while the motor (11) is operating below said threshold, and controlling the motor (11) to operate at a lower speed while the motor (11) is operating at or above said threshold. | 2,800 |
12,133 | 12,133 | 15,349,779 | 2,865 | A system and methods for monitoring an impact of geomagnetic disturbances (GMDs) or an E3 component of electromagnetic pulses (EMP-E3), involving a transducer generating a transduced signal in response to a magnetic field of a current carrying element of a transmission line. The transduced signal reflects harmonic characteristics of the current carrying element, and is amplified and filtered, then digitally converted. Excessive impact is detected when a threshold condition is met with respect to a total harmonic distortion (THD) and/or a change in THD. The THD can be calculated from amplitudes of harmonic components of interest. The amplitudes can be calculated in various ways, including Fourier transforming the digital signal to locate peaks in the resulting spectral lines, or using a phase sensitive detection algorithm in which the digital signal is multiplied by a phase swept reference signal and then integrated. | 1. A monitoring device for monitoring an impact of Geomagnetic disturbances (GMDs) or an E3 component of electromagnetic pulses (EMP-E3), the monitoring device comprising:
a transducer to generate a transduced signal in response to a magnetic field of a current carrying element of a transmission line, wherein the transduced signal reflects harmonic characteristics of the current carrying element; an amplifier to generate an amplified signal from the transduced signal; a low pass filter to generate a filtered signal by low pass filtering the amplified signal; and a microprocessor configured to detect excessive GMD/EMP-E3 impact when an analysis of a digital signal representing the filtered signal indicates a threshold condition is met. 2. The monitoring device of claim 1, wherein the microprocessor includes:
a harmonic measurement module to receive the digital signal and to calculate amplitudes of harmonic components within the digital signal; and a threshold detection module to detect whether the harmonic components meet the threshold condition. 3. The monitoring device of claim 2, wherein the digital signal is formed by an analog-to-digital (A/D) converter, and wherein the microprocessor synchronizes a sampling activity of the A/D converter using a timing signal. 4. The monitoring device of claim 3, wherein the timing signal is a pulse per second signal formed using a global positioning system. 5. The monitoring device of claim 2, wherein the threshold detection module determines at least one of whether a total harmonic distortion (THD) calculated from the amplitudes meets a threshold THD value, and whether a change in the THD meets a threshold THD change value. 6. The monitoring device of claim 2, wherein the harmonic measurement module is configured to:
weight the digital signal using a window function; apply a fast Fourier transform to the weighted digital signal, thereby forming a transformed signal; interpolate the transformed signal, thereby forming an interpolated signal; and calculate the amplitudes from the interpolated signal. 7. The monitoring device of claim 6, wherein the window function is a Kaiser window. 8. The monitoring device of claim 6, wherein the interpolation is performed for individual harmonics, between maximum and sub-maximum spectral lines associated with an individual harmonic. 9. The monitoring device of claim 6, wherein the interpolation uses a polynomial fitting, and wherein the amplitudes are calculated using an inverse fitting. 10. The monitoring device of claim 2, wherein the harmonic measurement module is configured to:
estimate a fundamental frequency of the digital signal; generate a reference signal from the estimated fundamental frequency and a phase signal, wherein the reference signal has a frequency equal to the frequency of a harmonic component whose amplitude is to be calculated; multiply the digital signal with the reference signal, thereby forming a demodulated signal; integrate the demodulated signal, thereby forming an integrated signal; phase sweep the integrated signal, thereby forming the phase signal; and calculate the amplitudes from the integrated signal. 11. A processor-implemented method for monitoring an impact of Geomagnetic disturbances (GMDs) or an E3 component of electromagnetic pulses (EMP-E3), the method comprising:
converting an analog signal from a transducer into a digital signal, wherein the analog signal is transduced in response to a magnetic field of a current carrying element of a transmission line, and wherein the analog signal reflects harmonic characteristics of the current carrying element; and analyzing the digital signal by a microprocessor to detect excessive GMD/EMP-E3 impact when the analysis indicates a threshold condition is met. 12. The method of claim 11, further comprising:
calculating amplitudes of harmonic components within the digital signal; and detecting whether the harmonic components meet the threshold condition. 13. The method of claim 12, further comprising:
synchronizing a sampling activity of an analog-to-digital (A/D) converter that forms the digital signal, using a timing signal. 14. The method of claim 13, wherein the timing signal is a pulse per second signal formed using a global positioning system. 15. The method of claim 12, further comprising:
determining at least one of whether a total harmonic distortion (THD) calculated from the amplitudes meets a threshold THD value, and whether a change in the THD meets a threshold THD change value. 16. The method of claim 12, further comprising:
weighting the digital signal using a window function; applying a fast Fourier transform to the weighted digital signal, thereby forming a transformed signal; interpolating the transformed signal, thereby forming an interpolated signal; and calculating the amplitudes from the interpolated signal. 17. The method of claim 16, wherein the window function is a Kaiser window. 18. The method of claim 16, wherein the interpolation is performed for individual harmonics, between maximum and sub-maximum spectral lines associated with an individual harmonic. 19. The method of claim 16, wherein the interpolation uses a polynomial fitting, and wherein the amplitudes are calculated using an inverse fitting. 20. The method of claim 12, further comprising:
estimating a fundamental frequency of the digital signal; generating a reference signal from the estimated fundamental frequency and a phase signal, wherein the reference signal has a frequency equal to the frequency of a harmonic component whose amplitude is to be calculated; multiplying the digital signal with the reference signal, thereby forming a demodulated signal; integrating the demodulated signal, thereby forming an integrated signal; phase sweeping the integrated signal, thereby forming the phase signal; and calculating the amplitudes from the integrated signal. | A system and methods for monitoring an impact of geomagnetic disturbances (GMDs) or an E3 component of electromagnetic pulses (EMP-E3), involving a transducer generating a transduced signal in response to a magnetic field of a current carrying element of a transmission line. The transduced signal reflects harmonic characteristics of the current carrying element, and is amplified and filtered, then digitally converted. Excessive impact is detected when a threshold condition is met with respect to a total harmonic distortion (THD) and/or a change in THD. The THD can be calculated from amplitudes of harmonic components of interest. The amplitudes can be calculated in various ways, including Fourier transforming the digital signal to locate peaks in the resulting spectral lines, or using a phase sensitive detection algorithm in which the digital signal is multiplied by a phase swept reference signal and then integrated.1. A monitoring device for monitoring an impact of Geomagnetic disturbances (GMDs) or an E3 component of electromagnetic pulses (EMP-E3), the monitoring device comprising:
a transducer to generate a transduced signal in response to a magnetic field of a current carrying element of a transmission line, wherein the transduced signal reflects harmonic characteristics of the current carrying element; an amplifier to generate an amplified signal from the transduced signal; a low pass filter to generate a filtered signal by low pass filtering the amplified signal; and a microprocessor configured to detect excessive GMD/EMP-E3 impact when an analysis of a digital signal representing the filtered signal indicates a threshold condition is met. 2. The monitoring device of claim 1, wherein the microprocessor includes:
a harmonic measurement module to receive the digital signal and to calculate amplitudes of harmonic components within the digital signal; and a threshold detection module to detect whether the harmonic components meet the threshold condition. 3. The monitoring device of claim 2, wherein the digital signal is formed by an analog-to-digital (A/D) converter, and wherein the microprocessor synchronizes a sampling activity of the A/D converter using a timing signal. 4. The monitoring device of claim 3, wherein the timing signal is a pulse per second signal formed using a global positioning system. 5. The monitoring device of claim 2, wherein the threshold detection module determines at least one of whether a total harmonic distortion (THD) calculated from the amplitudes meets a threshold THD value, and whether a change in the THD meets a threshold THD change value. 6. The monitoring device of claim 2, wherein the harmonic measurement module is configured to:
weight the digital signal using a window function; apply a fast Fourier transform to the weighted digital signal, thereby forming a transformed signal; interpolate the transformed signal, thereby forming an interpolated signal; and calculate the amplitudes from the interpolated signal. 7. The monitoring device of claim 6, wherein the window function is a Kaiser window. 8. The monitoring device of claim 6, wherein the interpolation is performed for individual harmonics, between maximum and sub-maximum spectral lines associated with an individual harmonic. 9. The monitoring device of claim 6, wherein the interpolation uses a polynomial fitting, and wherein the amplitudes are calculated using an inverse fitting. 10. The monitoring device of claim 2, wherein the harmonic measurement module is configured to:
estimate a fundamental frequency of the digital signal; generate a reference signal from the estimated fundamental frequency and a phase signal, wherein the reference signal has a frequency equal to the frequency of a harmonic component whose amplitude is to be calculated; multiply the digital signal with the reference signal, thereby forming a demodulated signal; integrate the demodulated signal, thereby forming an integrated signal; phase sweep the integrated signal, thereby forming the phase signal; and calculate the amplitudes from the integrated signal. 11. A processor-implemented method for monitoring an impact of Geomagnetic disturbances (GMDs) or an E3 component of electromagnetic pulses (EMP-E3), the method comprising:
converting an analog signal from a transducer into a digital signal, wherein the analog signal is transduced in response to a magnetic field of a current carrying element of a transmission line, and wherein the analog signal reflects harmonic characteristics of the current carrying element; and analyzing the digital signal by a microprocessor to detect excessive GMD/EMP-E3 impact when the analysis indicates a threshold condition is met. 12. The method of claim 11, further comprising:
calculating amplitudes of harmonic components within the digital signal; and detecting whether the harmonic components meet the threshold condition. 13. The method of claim 12, further comprising:
synchronizing a sampling activity of an analog-to-digital (A/D) converter that forms the digital signal, using a timing signal. 14. The method of claim 13, wherein the timing signal is a pulse per second signal formed using a global positioning system. 15. The method of claim 12, further comprising:
determining at least one of whether a total harmonic distortion (THD) calculated from the amplitudes meets a threshold THD value, and whether a change in the THD meets a threshold THD change value. 16. The method of claim 12, further comprising:
weighting the digital signal using a window function; applying a fast Fourier transform to the weighted digital signal, thereby forming a transformed signal; interpolating the transformed signal, thereby forming an interpolated signal; and calculating the amplitudes from the interpolated signal. 17. The method of claim 16, wherein the window function is a Kaiser window. 18. The method of claim 16, wherein the interpolation is performed for individual harmonics, between maximum and sub-maximum spectral lines associated with an individual harmonic. 19. The method of claim 16, wherein the interpolation uses a polynomial fitting, and wherein the amplitudes are calculated using an inverse fitting. 20. The method of claim 12, further comprising:
estimating a fundamental frequency of the digital signal; generating a reference signal from the estimated fundamental frequency and a phase signal, wherein the reference signal has a frequency equal to the frequency of a harmonic component whose amplitude is to be calculated; multiplying the digital signal with the reference signal, thereby forming a demodulated signal; integrating the demodulated signal, thereby forming an integrated signal; phase sweeping the integrated signal, thereby forming the phase signal; and calculating the amplitudes from the integrated signal. | 2,800 |
12,134 | 12,134 | 16,327,058 | 2,877 | A measuring device is provided for measuring the absorption of gases. The measuring device (1) includes a radiation source (2), a first detector element (3), a second detector element (9) and a reflector array (4). The reflector array (4) defines a first optical path (5) between the radiation source (2) and the first detector element (3) and defines a second optical path (10) between the radiation source (2) and the second detector element (9). The first optical path (5) has at least two points of intersection with itself and the second detector element (9) is arranged outside of a first plane which is defined by the radiation source (2) and two points of intersection (6) of the first optical path (5). | 1. A measuring device for measuring the absorption of gases, the measuring device comprising:
a radiation source; a first detector element; a second detector element; and a reflector array, the reflector array defining a first optical path between the radiation source and the first detector element and the reflector array defining a second optical path between the radiation source and the second detector element, wherein the first optical path has at least two points of intersection with itself, the second detector element is arranged outside of a plane that is defined by the radiation source and the at least two points of intersection of the first optical path. 2. A measuring device in accordance with claim 1, wherein the first optical path has at least three points of intersection with itself. 3. A measuring device in accordance with claim 1, further comprising a wall element enclosing a measuring chamber, wherein the radiation source, the first detector element and the reflector array are arranged at the wall element. 4. A measuring device in accordance with claim 3, wherein the wall element extends in a plane, in which the first optical path has a pentagonal or hexagonal cross section. 5. A measuring device in accordance with claim 1, wherein the second optical path has no point of intersection with itself. 6. A measuring device in accordance with claim 1, wherein:
the reflector array has a first mirror element and a second mirror element as well as a first concave mirror element and a second concave mirror element for the first optical path; a focus of the reflector array is located on the radiation source and another focus of the reflector array is located on the first detector element; and the concave mirror elements are parabolic. 7. A measuring device in accordance with claim 6, wherein the reflector array comprises in the second optical path a third concave mirror element, which images the radiation source onto the second detector element. 8. A measuring device in accordance with claim 7, wherein the third concave mirror element is arranged between the first concave mirror element and the second concave mirror element. 9. A measuring device in accordance with claim 7, wherein the third concave mirror element, the first concave mirror element and the second concave mirror element are arranged in a triangle. 10. A measuring device in accordance with claim 1, wherein an optical filter element is arranged between the measuring chamber and the first detector element or between the measuring chamber and the second detector element or between the measuring chamber and the first detector element and the second detector element. 11. A gas absorption measuring device comprising:
a reflector array at least partially defining a measuring space; a radiation source; a first detector element; and a second detector element, wherein: the reflector array is configured in cooperation with a position of the radiation source and the first detector element to define a first optical path within the measuring space, between the radiation source and the first detector element, with the first optical path intersecting the first optical path at least at two points; a plane is defined by the radiation source and the at least two points of intersection; the reflector array is configured in cooperation with the position of the radiation source and a position of the second detector element to define a second optical path; the position of the second detector element is outside of the plane. 12. A gas absorption measuring device in accordance with claim 11, wherein the first optical path intersects the first optical path at least at three points. 13. A gas absorption measuring device in accordance with claim 11, further comprising a wall element enclosing a measuring chamber, wherein the radiation source, the first detector element and the reflector array are arranged at the wall element. 14. A gas absorption measuring device in accordance with claim 13, wherein the wall element has an essentially pentagonal or hexagonal cross section. 15. A gas absorption measuring device in accordance with claim 11, wherein the second optical path does not intersect the second optical path. 16. A gas absorption measuring device in accordance with claim 11, wherein:
the reflector array comprises a first mirror element and a second mirror element, a first concave mirror element and a second concave mirror element configured to at least partially define the first optical path; a focus of the reflector array is located on the radiation source; another focus of the reflector array is located on the first detector element; the first concave mirror element is parabolic; and the second concave mirror element is parabolic. 17. A gas absorption measuring device in accordance with claim 16, wherein the reflector array further comprises a third concave mirror element, which images the radiation source onto the second detector element and defines the second optical path. 18. A gas absorption measuring device in accordance with claim 17, wherein the third concave mirror element is arranged between the first concave mirror element and the second concave mirror element. 19. A gas absorption measuring device in accordance with claim 17, wherein the third concave mirror element, the first concave mirror element and the second concave mirror element are arranged in a triangle. 20. A gas absorption measuring device in accordance with claim 11, further comprising:
an optical filter element arranged along the first optical path upstream of the first detector element and downstream of the measuring space; or an optical filter element arranged along the second optical path upstream of the first detector element and downstream of the measuring space; or an optical filter element arranged along the first optical path upstream of the first detector element and downstream of the measuring space and an optical filter element arranged along the second optical path upstream of the first detector element and downstream of the measuring space; or an optical filter element arranged along the first optical path upstream of the first detector element and downstream of the measuring space and arranged along the second optical path upstream of the first detector element and downstream of the measuring space. | A measuring device is provided for measuring the absorption of gases. The measuring device (1) includes a radiation source (2), a first detector element (3), a second detector element (9) and a reflector array (4). The reflector array (4) defines a first optical path (5) between the radiation source (2) and the first detector element (3) and defines a second optical path (10) between the radiation source (2) and the second detector element (9). The first optical path (5) has at least two points of intersection with itself and the second detector element (9) is arranged outside of a first plane which is defined by the radiation source (2) and two points of intersection (6) of the first optical path (5).1. A measuring device for measuring the absorption of gases, the measuring device comprising:
a radiation source; a first detector element; a second detector element; and a reflector array, the reflector array defining a first optical path between the radiation source and the first detector element and the reflector array defining a second optical path between the radiation source and the second detector element, wherein the first optical path has at least two points of intersection with itself, the second detector element is arranged outside of a plane that is defined by the radiation source and the at least two points of intersection of the first optical path. 2. A measuring device in accordance with claim 1, wherein the first optical path has at least three points of intersection with itself. 3. A measuring device in accordance with claim 1, further comprising a wall element enclosing a measuring chamber, wherein the radiation source, the first detector element and the reflector array are arranged at the wall element. 4. A measuring device in accordance with claim 3, wherein the wall element extends in a plane, in which the first optical path has a pentagonal or hexagonal cross section. 5. A measuring device in accordance with claim 1, wherein the second optical path has no point of intersection with itself. 6. A measuring device in accordance with claim 1, wherein:
the reflector array has a first mirror element and a second mirror element as well as a first concave mirror element and a second concave mirror element for the first optical path; a focus of the reflector array is located on the radiation source and another focus of the reflector array is located on the first detector element; and the concave mirror elements are parabolic. 7. A measuring device in accordance with claim 6, wherein the reflector array comprises in the second optical path a third concave mirror element, which images the radiation source onto the second detector element. 8. A measuring device in accordance with claim 7, wherein the third concave mirror element is arranged between the first concave mirror element and the second concave mirror element. 9. A measuring device in accordance with claim 7, wherein the third concave mirror element, the first concave mirror element and the second concave mirror element are arranged in a triangle. 10. A measuring device in accordance with claim 1, wherein an optical filter element is arranged between the measuring chamber and the first detector element or between the measuring chamber and the second detector element or between the measuring chamber and the first detector element and the second detector element. 11. A gas absorption measuring device comprising:
a reflector array at least partially defining a measuring space; a radiation source; a first detector element; and a second detector element, wherein: the reflector array is configured in cooperation with a position of the radiation source and the first detector element to define a first optical path within the measuring space, between the radiation source and the first detector element, with the first optical path intersecting the first optical path at least at two points; a plane is defined by the radiation source and the at least two points of intersection; the reflector array is configured in cooperation with the position of the radiation source and a position of the second detector element to define a second optical path; the position of the second detector element is outside of the plane. 12. A gas absorption measuring device in accordance with claim 11, wherein the first optical path intersects the first optical path at least at three points. 13. A gas absorption measuring device in accordance with claim 11, further comprising a wall element enclosing a measuring chamber, wherein the radiation source, the first detector element and the reflector array are arranged at the wall element. 14. A gas absorption measuring device in accordance with claim 13, wherein the wall element has an essentially pentagonal or hexagonal cross section. 15. A gas absorption measuring device in accordance with claim 11, wherein the second optical path does not intersect the second optical path. 16. A gas absorption measuring device in accordance with claim 11, wherein:
the reflector array comprises a first mirror element and a second mirror element, a first concave mirror element and a second concave mirror element configured to at least partially define the first optical path; a focus of the reflector array is located on the radiation source; another focus of the reflector array is located on the first detector element; the first concave mirror element is parabolic; and the second concave mirror element is parabolic. 17. A gas absorption measuring device in accordance with claim 16, wherein the reflector array further comprises a third concave mirror element, which images the radiation source onto the second detector element and defines the second optical path. 18. A gas absorption measuring device in accordance with claim 17, wherein the third concave mirror element is arranged between the first concave mirror element and the second concave mirror element. 19. A gas absorption measuring device in accordance with claim 17, wherein the third concave mirror element, the first concave mirror element and the second concave mirror element are arranged in a triangle. 20. A gas absorption measuring device in accordance with claim 11, further comprising:
an optical filter element arranged along the first optical path upstream of the first detector element and downstream of the measuring space; or an optical filter element arranged along the second optical path upstream of the first detector element and downstream of the measuring space; or an optical filter element arranged along the first optical path upstream of the first detector element and downstream of the measuring space and an optical filter element arranged along the second optical path upstream of the first detector element and downstream of the measuring space; or an optical filter element arranged along the first optical path upstream of the first detector element and downstream of the measuring space and arranged along the second optical path upstream of the first detector element and downstream of the measuring space. | 2,800 |
12,135 | 12,135 | 15,762,459 | 2,846 | A method for preventing a frequency component of a voltage from occurring in an electrical machine including the steps of: obtaining, either by measuring a voltage signal or a current signal from the electrical machine in time domain and transforming the measured signal into frequency domain, by simulating or deducing a first frequency component present in the electrical machine in absence of a grounding, the first frequency component representing a first undesired frequency higher than a limit frequency of 500 Hz; and providing the electrical machine with a first grounding at a grounding location, the first grounding including a resonant circuit resonating at the first undesired frequency. In order to get rid of harmful shaft voltages in the form of sharp voltage peaks at high frequencies, it is first necessary to determine at which undesired frequency or frequencies these voltage peaks occur. Only thereafter can a low impedance grounding be provided that works satisfactorily at the undesired frequency or frequencies. | 1. A method for preventing at least one frequency component of a voltage from occurring in an electrical machine, the method comprising the steps of:
obtaining, either by measuring a voltage signal or a current signal from the electrical machine in time domain and transforming the measured signal into frequency domain, by simulating the electrical machine, or by deducing from operation settings of an inverter, a first frequency component present in the electrical machine in absence of a grounding, the first frequency component representing a first undesired frequency higher than a limit frequency of 500 Hz; and providing the electrical machine with a first grounding at a grounding location, the first grounding comprising a resonant circuit resonating at the first undesired frequency. 2. The method according to claim 1, wherein the limit frequency is 1 kHz, 2 kHz, 4 kHz or 8 kHz. 3. The method according to claim 1, wherein the grounding location is at a stator core lamination or at a shaft of the electrical machine. 4. The method according to claim 1, wherein the first undesired frequency emerges from a common mode voltage. 5. The method according to claim 1, wherein the first frequency component is that with the highest voltage amplitude at frequencies above the limit frequency. 6. The method according to claim 1, wherein grounding impedance at the first undesired frequency is essentially zero. 7. The method according to claim 1, wherein resonant frequency of the resonant circuit is configured to be adjustable. 8. The method according to claim 1, wherein the resonant circuit comprises a capacitor and an inductor. 9. The method according to claim 1, wherein the method further comprises the steps of:
obtaining a second frequency component present in the electrical machine in absence of a grounding, the second frequency component representing a second undesired frequency higher than the limit frequency and different from the first undesired frequency; and providing the electrical machine with a second grounding, the second grounding comprising a resonant circuit resonating at the second undesired frequency. 10. The method according to claim 1, wherein the obtaining of the first frequency component occurs during operation of the electrical machine. 11. The method according to claim 1, wherein the electrical machine comprises an inverter. 12. The method according to claim 11, wherein a switching frequency of the inverter is configured to change during operation of the electrical machine. 13. An electrical machine comprising:
a frequency component identifier configured to obtain, either by measuring a voltage signal or a current signal from the electrical machine in time domain and transforming the measured signal into frequency domain, by simulating the electrical machine, or by deducing from operation settings of an inverter, a first frequency component of a voltage present in the electrical machine in absence of a grounding, the first frequency component representing a first undesired frequency higher than a limit frequency of 500 Hz, a first grounding at a grounding location, the first grounding preventing the first undesired frequency from occurring in the electrical machine, and the first grounding comprising a resonant circuit resonating at the first undesired frequency. 14. The electrical machine according to claim 13, wherein the limit frequency is 1 kHz, 2 kHz, 4 kHz or 8 kHz. 15. The electrical machine according to claim 13, wherein the frequency component identifier is configured to obtain the first frequency component during operation of the electrical machine. 16. The electrical machine according to claim 14, wherein the frequency component identifier is configured to obtain the first frequency component during operation of the electrical machine. 17. The method according to claim 2, wherein the grounding location is at a stator core lamination or at a shaft of the electrical machine 18. The method according to claim 2, wherein the first undesired frequency emerges from a common mode voltage 19. The method according to claim 2, wherein the first frequency component is that with the highest voltage amplitude at frequencies above the limit frequency | A method for preventing a frequency component of a voltage from occurring in an electrical machine including the steps of: obtaining, either by measuring a voltage signal or a current signal from the electrical machine in time domain and transforming the measured signal into frequency domain, by simulating or deducing a first frequency component present in the electrical machine in absence of a grounding, the first frequency component representing a first undesired frequency higher than a limit frequency of 500 Hz; and providing the electrical machine with a first grounding at a grounding location, the first grounding including a resonant circuit resonating at the first undesired frequency. In order to get rid of harmful shaft voltages in the form of sharp voltage peaks at high frequencies, it is first necessary to determine at which undesired frequency or frequencies these voltage peaks occur. Only thereafter can a low impedance grounding be provided that works satisfactorily at the undesired frequency or frequencies.1. A method for preventing at least one frequency component of a voltage from occurring in an electrical machine, the method comprising the steps of:
obtaining, either by measuring a voltage signal or a current signal from the electrical machine in time domain and transforming the measured signal into frequency domain, by simulating the electrical machine, or by deducing from operation settings of an inverter, a first frequency component present in the electrical machine in absence of a grounding, the first frequency component representing a first undesired frequency higher than a limit frequency of 500 Hz; and providing the electrical machine with a first grounding at a grounding location, the first grounding comprising a resonant circuit resonating at the first undesired frequency. 2. The method according to claim 1, wherein the limit frequency is 1 kHz, 2 kHz, 4 kHz or 8 kHz. 3. The method according to claim 1, wherein the grounding location is at a stator core lamination or at a shaft of the electrical machine. 4. The method according to claim 1, wherein the first undesired frequency emerges from a common mode voltage. 5. The method according to claim 1, wherein the first frequency component is that with the highest voltage amplitude at frequencies above the limit frequency. 6. The method according to claim 1, wherein grounding impedance at the first undesired frequency is essentially zero. 7. The method according to claim 1, wherein resonant frequency of the resonant circuit is configured to be adjustable. 8. The method according to claim 1, wherein the resonant circuit comprises a capacitor and an inductor. 9. The method according to claim 1, wherein the method further comprises the steps of:
obtaining a second frequency component present in the electrical machine in absence of a grounding, the second frequency component representing a second undesired frequency higher than the limit frequency and different from the first undesired frequency; and providing the electrical machine with a second grounding, the second grounding comprising a resonant circuit resonating at the second undesired frequency. 10. The method according to claim 1, wherein the obtaining of the first frequency component occurs during operation of the electrical machine. 11. The method according to claim 1, wherein the electrical machine comprises an inverter. 12. The method according to claim 11, wherein a switching frequency of the inverter is configured to change during operation of the electrical machine. 13. An electrical machine comprising:
a frequency component identifier configured to obtain, either by measuring a voltage signal or a current signal from the electrical machine in time domain and transforming the measured signal into frequency domain, by simulating the electrical machine, or by deducing from operation settings of an inverter, a first frequency component of a voltage present in the electrical machine in absence of a grounding, the first frequency component representing a first undesired frequency higher than a limit frequency of 500 Hz, a first grounding at a grounding location, the first grounding preventing the first undesired frequency from occurring in the electrical machine, and the first grounding comprising a resonant circuit resonating at the first undesired frequency. 14. The electrical machine according to claim 13, wherein the limit frequency is 1 kHz, 2 kHz, 4 kHz or 8 kHz. 15. The electrical machine according to claim 13, wherein the frequency component identifier is configured to obtain the first frequency component during operation of the electrical machine. 16. The electrical machine according to claim 14, wherein the frequency component identifier is configured to obtain the first frequency component during operation of the electrical machine. 17. The method according to claim 2, wherein the grounding location is at a stator core lamination or at a shaft of the electrical machine 18. The method according to claim 2, wherein the first undesired frequency emerges from a common mode voltage 19. The method according to claim 2, wherein the first frequency component is that with the highest voltage amplitude at frequencies above the limit frequency | 2,800 |
12,136 | 12,136 | 15,517,748 | 2,836 | A system for providing wireless power transfer includes a primary antenna having a primary lens surrounding the primary antenna and a secondary antenna having a secondary lens surrounding the secondary antenna. The secondary antenna is operatively connected to power at least one sensor. A mains power source is operatively connected to power the primary antenna. The primary and secondary antennas are separated a distance apart to wirelessly transfer power from the primary antenna to the secondary antenna. | 1. A system for providing wireless power transfer for a security and access control system, comprising:
a primary antenna having a primary lens surrounding the primary antenna; a secondary antenna having a secondary lens surrounding the secondary antenna, wherein the secondary antenna is operatively connected to at least device receptive of power; and a main power source operatively connected to power the primary antenna, wherein the primary and secondary antennas are separated a distance apart to wirelessly transfer power from the primary antenna to the secondary antenna. 2. The system of claim 1, wherein the primary antenna is an electromagnetic transmitter. 3. The system of claim 1, wherein the secondary antenna is an electromagnetic receiver. 4. The system of claim 1, wherein the primary lens and secondary lens is comprised of an array of resonators. 5. The system of claim 1, wherein the primary antenna and lens directs electromagnetic energy towards the secondary antenna and lens in a manner to reduce the field self-cancellation. 6. The system of claim 1, wherein the primary and secondary antennas are partial toroidal helix configurations and including light pipes configured to improve the power transfer efficiency. 7. The system of claim 1, wherein the primary and secondary antennas are meander line antennas. 8. The system of claim 1, wherein the primary and secondary antennas are linear antennas. 9. The system of claim 1, further comprising a primary transceiver operatively connected to the primary antenna and a secondary transceiver operatively connected to the secondary antenna, the first and second transceivers configured to communicate data between the primary and secondary antennas. 10. A device for providing wireless power transfer, comprising:
a primary antenna having a first lens surrounding a first end portion thereof and a second lens surrounding a second end portion thereof. 11. The device of claim 10, further including a secondary antenna having a first lens surrounding a first end portion of the secondary antenna and a second lens surround a second end portion of the secondary antenna. 12. The device of claim 11, wherein the primary antenna is an electromagnetic transmitter coil and the secondary antenna is an electromagnetic receiver. 13. The device of claim 12, further including a mains power source operatively connected to power the primary antenna, wherein the primary and secondary antennas are separated a distance apart to wirelessly transfer power from the primary antenna to the secondary antenna. 14. The device of claim 13, wherein the first end portion and the second end portion of the primary antenna are directed towards the first end portion and second end portion of the secondary antenna. 15. The device of claim 13, wherein the first and second lens of each of the primary and secondary antennas are comprised of an array of resonators. 16. The device of claim 13, wherein the primary antenna and lens force electromagnetic energy towards the secondary antenna and lens in a manner which prevents field self-cancellation. 17. A system for providing one or more of the following: wireless power, backup wireless power for critical building functions, infrastructure and cities, long-range magnetic levitation; levitating and powering automobiles and other vehicles, data communication, passive radar; and active radar, the system comprising:
a primary antenna having a meander type configuration having a primary lens surrounding the primary antenna wherein the primary antenna is an electromagnetic transmitter and the lens is comprised of an array of resonators; and a secondary antenna having a meander type configuration having a secondary lens surrounding the secondary antenna wherein the secondary antenna is an electromagnetic receiver and the lens is comprised of an array of resonators, wherein the primary antenna and lens force electromagnetic energy towards the secondary antenna and lens in a manner which minimizes field self-cancellation. 18. A system for providing one or more of the following: long-range magnetic levitation, levitating and powering automobiles and other vehicles, electromagnetic armor, directed energy weapons, artificial long-range magnetospheres, passive radar, active radar, long wavelength radio astronomy instrumentation, and search for extra-terrestrial intelligence (SETI) instrumentation, the system comprising:
a primary antenna having a meander type configuration having a primary lens surrounding the primary antenna wherein the primary antenna is an electromagnetic transmitter and the lens is comprised of an array of resonators, wherein the primary antenna and manipulate electromagnetic energy in a manner which minimizes field self-cancellation. 19. A system for providing one or more of the following: wireless power, backup wireless power for critical building functions, infrastructure and cities, long-range magnetic levitation; levitating and powering automobiles and other vehicles, data communication, passive radar; and active radar, the system comprising:
a primary antenna having a linear configuration having a primary lens surrounding the primary antenna wherein the primary antenna is an electromagnetic transmitter and the lens is comprised of an array of resonators; and a secondary antenna having a linear configuration having a secondary lens surrounding the secondary antenna wherein the secondary antenna is an electromagnetic receiver and the lens is comprised of an array of resonators, wherein the primary antenna and lens force electromagnetic energy towards the secondary antenna and lens in a manner which minimizes field self-cancellation. 20. A system for providing one or more of the following: long-range magnetic levitation, levitating and powering automobiles and other vehicles, electromagnetic armor, directed energy weapons, artificial long-range magnetospheres, passive radar, active radar, long wavelength radio astronomy instrumentation, and search for extra-terrestrial intelligence (SETI) instrumentation, the system comprising:
a primary antenna having a linear configuration having a primary lens surrounding the primary antenna wherein the primary antenna is an electromagnetic transmitter and the lens is comprised of an array of resonators, wherein the primary antenna and manipulate electromagnetic energy in a manner which minimizes field self-cancellation. | A system for providing wireless power transfer includes a primary antenna having a primary lens surrounding the primary antenna and a secondary antenna having a secondary lens surrounding the secondary antenna. The secondary antenna is operatively connected to power at least one sensor. A mains power source is operatively connected to power the primary antenna. The primary and secondary antennas are separated a distance apart to wirelessly transfer power from the primary antenna to the secondary antenna.1. A system for providing wireless power transfer for a security and access control system, comprising:
a primary antenna having a primary lens surrounding the primary antenna; a secondary antenna having a secondary lens surrounding the secondary antenna, wherein the secondary antenna is operatively connected to at least device receptive of power; and a main power source operatively connected to power the primary antenna, wherein the primary and secondary antennas are separated a distance apart to wirelessly transfer power from the primary antenna to the secondary antenna. 2. The system of claim 1, wherein the primary antenna is an electromagnetic transmitter. 3. The system of claim 1, wherein the secondary antenna is an electromagnetic receiver. 4. The system of claim 1, wherein the primary lens and secondary lens is comprised of an array of resonators. 5. The system of claim 1, wherein the primary antenna and lens directs electromagnetic energy towards the secondary antenna and lens in a manner to reduce the field self-cancellation. 6. The system of claim 1, wherein the primary and secondary antennas are partial toroidal helix configurations and including light pipes configured to improve the power transfer efficiency. 7. The system of claim 1, wherein the primary and secondary antennas are meander line antennas. 8. The system of claim 1, wherein the primary and secondary antennas are linear antennas. 9. The system of claim 1, further comprising a primary transceiver operatively connected to the primary antenna and a secondary transceiver operatively connected to the secondary antenna, the first and second transceivers configured to communicate data between the primary and secondary antennas. 10. A device for providing wireless power transfer, comprising:
a primary antenna having a first lens surrounding a first end portion thereof and a second lens surrounding a second end portion thereof. 11. The device of claim 10, further including a secondary antenna having a first lens surrounding a first end portion of the secondary antenna and a second lens surround a second end portion of the secondary antenna. 12. The device of claim 11, wherein the primary antenna is an electromagnetic transmitter coil and the secondary antenna is an electromagnetic receiver. 13. The device of claim 12, further including a mains power source operatively connected to power the primary antenna, wherein the primary and secondary antennas are separated a distance apart to wirelessly transfer power from the primary antenna to the secondary antenna. 14. The device of claim 13, wherein the first end portion and the second end portion of the primary antenna are directed towards the first end portion and second end portion of the secondary antenna. 15. The device of claim 13, wherein the first and second lens of each of the primary and secondary antennas are comprised of an array of resonators. 16. The device of claim 13, wherein the primary antenna and lens force electromagnetic energy towards the secondary antenna and lens in a manner which prevents field self-cancellation. 17. A system for providing one or more of the following: wireless power, backup wireless power for critical building functions, infrastructure and cities, long-range magnetic levitation; levitating and powering automobiles and other vehicles, data communication, passive radar; and active radar, the system comprising:
a primary antenna having a meander type configuration having a primary lens surrounding the primary antenna wherein the primary antenna is an electromagnetic transmitter and the lens is comprised of an array of resonators; and a secondary antenna having a meander type configuration having a secondary lens surrounding the secondary antenna wherein the secondary antenna is an electromagnetic receiver and the lens is comprised of an array of resonators, wherein the primary antenna and lens force electromagnetic energy towards the secondary antenna and lens in a manner which minimizes field self-cancellation. 18. A system for providing one or more of the following: long-range magnetic levitation, levitating and powering automobiles and other vehicles, electromagnetic armor, directed energy weapons, artificial long-range magnetospheres, passive radar, active radar, long wavelength radio astronomy instrumentation, and search for extra-terrestrial intelligence (SETI) instrumentation, the system comprising:
a primary antenna having a meander type configuration having a primary lens surrounding the primary antenna wherein the primary antenna is an electromagnetic transmitter and the lens is comprised of an array of resonators, wherein the primary antenna and manipulate electromagnetic energy in a manner which minimizes field self-cancellation. 19. A system for providing one or more of the following: wireless power, backup wireless power for critical building functions, infrastructure and cities, long-range magnetic levitation; levitating and powering automobiles and other vehicles, data communication, passive radar; and active radar, the system comprising:
a primary antenna having a linear configuration having a primary lens surrounding the primary antenna wherein the primary antenna is an electromagnetic transmitter and the lens is comprised of an array of resonators; and a secondary antenna having a linear configuration having a secondary lens surrounding the secondary antenna wherein the secondary antenna is an electromagnetic receiver and the lens is comprised of an array of resonators, wherein the primary antenna and lens force electromagnetic energy towards the secondary antenna and lens in a manner which minimizes field self-cancellation. 20. A system for providing one or more of the following: long-range magnetic levitation, levitating and powering automobiles and other vehicles, electromagnetic armor, directed energy weapons, artificial long-range magnetospheres, passive radar, active radar, long wavelength radio astronomy instrumentation, and search for extra-terrestrial intelligence (SETI) instrumentation, the system comprising:
a primary antenna having a linear configuration having a primary lens surrounding the primary antenna wherein the primary antenna is an electromagnetic transmitter and the lens is comprised of an array of resonators, wherein the primary antenna and manipulate electromagnetic energy in a manner which minimizes field self-cancellation. | 2,800 |
12,137 | 12,137 | 15,202,245 | 2,811 | A semiconductor package including a premold which is used to define support structure for a semiconductor die which is mounted to the premold by a layer of suitable adhesive. Embedded within the premold are lands which each include oppose upper and lower surfaces exposed in respective ones of upper and lower surfaces define by the premold. The semiconductor die, which is attached to the upper surface of the premold by the adhesive layer, is electrically connected to the exposed upper surfaces of the lands through the use of conductive wires. The semiconductor die, conductive wires, and the upper surface of the premold are covered or encapsulated by a package body. The package body does not cover any portion of the lower surface of the premold, thus allowing the exposed lower surfaces of the lands to be placed into electrical connection or communication with an underlying substrate such as a PCB or motherboard. | 1-20. (canceled) 21. A method for forming a semiconductor package comprising:
providing a premold substrate comprising:
a first conductive portion having a side surface at least partially encapsulated with a molded insulating material;
a second conductive portion having a surface exposed to the outside of the molded insulating material;
electrically connecting a semiconductor die to the second conductive portion; and forming a package body covering at least the semiconductor die and at least a portion of the surface of the second conductive portion exposed to the outside of the molded insulating material. 22. The method of claim 21, wherein providing the premold substrate comprises:
providing the first conductive portion having a first width; and providing the second conductive portion having a second width greater than the first width. 23. The method of claim 21, wherein providing the premold substrate comprises:
providing the first conductive portion comprising a first material; and providing the second conductive portion comprising a second material. 24. The method of claim 21, wherein providing the premold substrate comprises:
providing a conductive substrate comprising a first conductive material and having generally planar upper and lower surfaces; selectively forming the second conductive portion on the upper surface; attaching the lower surface of the conductive substrate to a support substrate; removing portions of the conductive substrate leaving a remaining portion of the conductive substrate to provide the first conductive portion adjoining the second conductive portion; thereafter providing the molded insulating material; and removing the support substrate. 25. The method of claim 21, wherein providing the premold substrate comprises providing the second conductive portion having an upper surface exposed to the outside of the molded insulating material. 26. The method of claim 21, wherein providing the premold substrate comprises providing the second conductive portion having a top surface exposed to the outside of the molded insulating material. 27. The method of claim 21, wherein providing the premold substrate comprises providing the second conductive portion extending to a lower surface of the premold substrate. 28. The method of claim 27, wherein providing the premold substrate further comprises providing a third conductive portion contiguous with the lower surface of the premold substrate and contiguous with the second conductive portion. 29. The method of claim 21, wherein providing the premold substrate comprises:
providing the first conductive portion at least partially encapsulated with an epoxy mold compound formed using a transfer mold process; and providing the premold substrate devoid of a die attach pad. 30. The method of claim 21, wherein electrically connecting the semiconductor die comprises:
attaching the semiconductor die to the premold substrate; and electrically connecting the semiconductor die to the second conductive portion with a conductive connective structure. 31. A method for forming a semiconductor package comprising:
providing a premolded substrate comprising:
a first conductive portion having an insulating material molded onto a side surface of the first conductive portion; and
a second conductive portion having a surface exposed to the outside of the insulating material;
electrically coupling a semiconductor die to the second conductive portion; and forming a package body covering at least the semiconductor die, at least a portion of the semiconductor die, and at least a portion of the second conductive portion surface exposed to the outside of the insulating material. 32. The method of claim 31, wherein providing the premolded substrate comprises:
providing an epoxy mold compound molded onto the side surface of the first conductive portion using a transfer molding process; and providing the epoxy mold compound comprises providing the epoxy mold compound recessed relative to an upper surface of the second conductive portion. 33. The method of claim 31, wherein providing the premolded substrate comprises:
providing the first conductive portion having a first width; and providing the second conductive portion having a second width greater than the first width. 34. The method of claim 31, wherein providing the premolded substrate comprises providing the second conductive portion having an upper surface exposed to the outside of the insulating material. 35. The method of claim 31, wherein providing the premolded substrate comprises:
providing a conductive substrate comprising a first conductive material and having generally planar upper and lower surfaces; selectively forming the second conductive portion on the upper surface; attaching the lower surface of the conductive substrate to a support substrate; removing portions of the conductive substrate leaving a remaining portion of the conductive substrate to provide the first conductive portion affixed to the second conductive portion; thereafter molding the insulating material onto the side surface of the first conductive portion; and removing the support substrate. 36. A method for forming a semiconductor package comprising:
providing a substrate premolded with a mold compound comprising:
a first conductive portion having the mold compound molded onto at least a side surface of the first conductive portion; and
a second conductive portion having a surface exposed to the outside of the mold compound;
electrically coupling a semiconductor die to the second conductive portion; and forming a package body covering at least the semiconductor die and at least a portion of the semiconductor die and at least a portion of the second conductive portion surface exposed to the outside of the mold compound. 37. The method of claim 36, wherein providing the substrate comprises:
providing the first conductive portion having a first width; and providing the second conductive portion having a second width greater than the first width. 38. The method of claim 31, wherein providing the substrate comprises providing the second conductive portion having an upper surface exposed to the outside of the mold compound. 39. The method of claim 31, wherein providing the substrate comprises providing the second conductive portion having a top surface exposed to the outside of the mold compound. 40. The method of claim 31, wherein providing the substrate comprises:
providing a conductive substrate having generally planar upper and lower surfaces; selectively forming the second conductive portion on the upper surface; attaching the lower surface of the conductive substrate to a support substrate; removing portions of the conductive substrate to form the first conductive portion; and molding the mold compound to the side surface of the first conductive portion. | A semiconductor package including a premold which is used to define support structure for a semiconductor die which is mounted to the premold by a layer of suitable adhesive. Embedded within the premold are lands which each include oppose upper and lower surfaces exposed in respective ones of upper and lower surfaces define by the premold. The semiconductor die, which is attached to the upper surface of the premold by the adhesive layer, is electrically connected to the exposed upper surfaces of the lands through the use of conductive wires. The semiconductor die, conductive wires, and the upper surface of the premold are covered or encapsulated by a package body. The package body does not cover any portion of the lower surface of the premold, thus allowing the exposed lower surfaces of the lands to be placed into electrical connection or communication with an underlying substrate such as a PCB or motherboard.1-20. (canceled) 21. A method for forming a semiconductor package comprising:
providing a premold substrate comprising:
a first conductive portion having a side surface at least partially encapsulated with a molded insulating material;
a second conductive portion having a surface exposed to the outside of the molded insulating material;
electrically connecting a semiconductor die to the second conductive portion; and forming a package body covering at least the semiconductor die and at least a portion of the surface of the second conductive portion exposed to the outside of the molded insulating material. 22. The method of claim 21, wherein providing the premold substrate comprises:
providing the first conductive portion having a first width; and providing the second conductive portion having a second width greater than the first width. 23. The method of claim 21, wherein providing the premold substrate comprises:
providing the first conductive portion comprising a first material; and providing the second conductive portion comprising a second material. 24. The method of claim 21, wherein providing the premold substrate comprises:
providing a conductive substrate comprising a first conductive material and having generally planar upper and lower surfaces; selectively forming the second conductive portion on the upper surface; attaching the lower surface of the conductive substrate to a support substrate; removing portions of the conductive substrate leaving a remaining portion of the conductive substrate to provide the first conductive portion adjoining the second conductive portion; thereafter providing the molded insulating material; and removing the support substrate. 25. The method of claim 21, wherein providing the premold substrate comprises providing the second conductive portion having an upper surface exposed to the outside of the molded insulating material. 26. The method of claim 21, wherein providing the premold substrate comprises providing the second conductive portion having a top surface exposed to the outside of the molded insulating material. 27. The method of claim 21, wherein providing the premold substrate comprises providing the second conductive portion extending to a lower surface of the premold substrate. 28. The method of claim 27, wherein providing the premold substrate further comprises providing a third conductive portion contiguous with the lower surface of the premold substrate and contiguous with the second conductive portion. 29. The method of claim 21, wherein providing the premold substrate comprises:
providing the first conductive portion at least partially encapsulated with an epoxy mold compound formed using a transfer mold process; and providing the premold substrate devoid of a die attach pad. 30. The method of claim 21, wherein electrically connecting the semiconductor die comprises:
attaching the semiconductor die to the premold substrate; and electrically connecting the semiconductor die to the second conductive portion with a conductive connective structure. 31. A method for forming a semiconductor package comprising:
providing a premolded substrate comprising:
a first conductive portion having an insulating material molded onto a side surface of the first conductive portion; and
a second conductive portion having a surface exposed to the outside of the insulating material;
electrically coupling a semiconductor die to the second conductive portion; and forming a package body covering at least the semiconductor die, at least a portion of the semiconductor die, and at least a portion of the second conductive portion surface exposed to the outside of the insulating material. 32. The method of claim 31, wherein providing the premolded substrate comprises:
providing an epoxy mold compound molded onto the side surface of the first conductive portion using a transfer molding process; and providing the epoxy mold compound comprises providing the epoxy mold compound recessed relative to an upper surface of the second conductive portion. 33. The method of claim 31, wherein providing the premolded substrate comprises:
providing the first conductive portion having a first width; and providing the second conductive portion having a second width greater than the first width. 34. The method of claim 31, wherein providing the premolded substrate comprises providing the second conductive portion having an upper surface exposed to the outside of the insulating material. 35. The method of claim 31, wherein providing the premolded substrate comprises:
providing a conductive substrate comprising a first conductive material and having generally planar upper and lower surfaces; selectively forming the second conductive portion on the upper surface; attaching the lower surface of the conductive substrate to a support substrate; removing portions of the conductive substrate leaving a remaining portion of the conductive substrate to provide the first conductive portion affixed to the second conductive portion; thereafter molding the insulating material onto the side surface of the first conductive portion; and removing the support substrate. 36. A method for forming a semiconductor package comprising:
providing a substrate premolded with a mold compound comprising:
a first conductive portion having the mold compound molded onto at least a side surface of the first conductive portion; and
a second conductive portion having a surface exposed to the outside of the mold compound;
electrically coupling a semiconductor die to the second conductive portion; and forming a package body covering at least the semiconductor die and at least a portion of the semiconductor die and at least a portion of the second conductive portion surface exposed to the outside of the mold compound. 37. The method of claim 36, wherein providing the substrate comprises:
providing the first conductive portion having a first width; and providing the second conductive portion having a second width greater than the first width. 38. The method of claim 31, wherein providing the substrate comprises providing the second conductive portion having an upper surface exposed to the outside of the mold compound. 39. The method of claim 31, wherein providing the substrate comprises providing the second conductive portion having a top surface exposed to the outside of the mold compound. 40. The method of claim 31, wherein providing the substrate comprises:
providing a conductive substrate having generally planar upper and lower surfaces; selectively forming the second conductive portion on the upper surface; attaching the lower surface of the conductive substrate to a support substrate; removing portions of the conductive substrate to form the first conductive portion; and molding the mold compound to the side surface of the first conductive portion. | 2,800 |
12,138 | 12,138 | 13,842,707 | 2,846 | A mining machine including a motor, an adjustable speed drive providing a voltage to the motor, the voltage having an excitation component comprising a magnitude and a frequency for operating the motor at a desired speed and including an additional voltage component for use in detecting a ground fault condition, and a ground fault relay for detecting a ground fault current when the ground fault current exceeds a predetermined threshold. | 1. A mining machine comprising:
a motor; an adjustable speed drive providing a voltage to the motor, the voltage having an excitation component comprising a magnitude and a frequency for operating the motor at a desired speed and including an additional voltage component for use in detecting a ground fault condition; and wherein the mining machine receives an indication from a ground fault relay when a ground fault current exceeds a predetermined threshold. 2. The mining machine of claim 1, wherein the additional voltage component modifies the ground fault current by increasing a magnitude of the ground fault current. 3. The mining machine of claim 1, wherein the additional voltage signal is one of a low-frequency alternating current waveform and a direct current. 4. The mining machine of claim 1, wherein the voltage is a three-phase voltage. 5. The mining machine of claim 1, wherein each phase of the three-phase voltage includes the additional voltage signal. 6. The mining machine of claim 1, wherein the adjustable speed drive is a variable-frequency drive. 7. The mining machine of claim 1, wherein the motor is an alternating current motor. 8. A method for detecting a ground fault of a mining machine including a motor, an adjustable speed drive, and a ground fault relay, the method comprising:
generating, at the adjustable speed drive, a three-phase voltage for the motor, each phase of the three-phase voltage including an additional voltage signal, the additional voltage signal effecting a ground fault current; providing the three-phase voltage to the motor; detecting a ground fault current between the motor and the adjustable speed drive; and outputting an indication of a ground fault when the ground fault current exceeds a predetermined threshold. 9. The method of claim 8, wherein the additional voltage signal modifies a ground fault current by increasing a magnitude of the ground fault current. 10. The method of claim 8, wherein the additional voltage signal is one of a low-frequency alternating current waveform and a direct current. 11. A system for generating variable frequency voltage for an alternating current motor, the system comprising:
a controller including at least one processor, the at least one processor configured to
generate a three-phase voltage for the motor;
generate an additional voltage component, the additional voltage component added onto each phase of the three-phase voltage to increase a magnitude of a ground fault current; and
provide the three-phase voltage injected with the additional voltage signal to the motor. 12. The system of claim 11, further comprising a user interface configured to receive instructions from a user, the instructions including an operating speed for the motor. 13. The system of claim 12, wherein the at least one processor is configured to receive the instructions from the user interface and generate the three-phase voltage for the motor based on the instructions. 14. The system of claim 11, further comprising a ground fault relay configured to detect a ground fault, measure the magnitude of the ground fault current, and output an indication of a ground fault to the controller when the magnitude exceeds a predetermined value. | A mining machine including a motor, an adjustable speed drive providing a voltage to the motor, the voltage having an excitation component comprising a magnitude and a frequency for operating the motor at a desired speed and including an additional voltage component for use in detecting a ground fault condition, and a ground fault relay for detecting a ground fault current when the ground fault current exceeds a predetermined threshold.1. A mining machine comprising:
a motor; an adjustable speed drive providing a voltage to the motor, the voltage having an excitation component comprising a magnitude and a frequency for operating the motor at a desired speed and including an additional voltage component for use in detecting a ground fault condition; and wherein the mining machine receives an indication from a ground fault relay when a ground fault current exceeds a predetermined threshold. 2. The mining machine of claim 1, wherein the additional voltage component modifies the ground fault current by increasing a magnitude of the ground fault current. 3. The mining machine of claim 1, wherein the additional voltage signal is one of a low-frequency alternating current waveform and a direct current. 4. The mining machine of claim 1, wherein the voltage is a three-phase voltage. 5. The mining machine of claim 1, wherein each phase of the three-phase voltage includes the additional voltage signal. 6. The mining machine of claim 1, wherein the adjustable speed drive is a variable-frequency drive. 7. The mining machine of claim 1, wherein the motor is an alternating current motor. 8. A method for detecting a ground fault of a mining machine including a motor, an adjustable speed drive, and a ground fault relay, the method comprising:
generating, at the adjustable speed drive, a three-phase voltage for the motor, each phase of the three-phase voltage including an additional voltage signal, the additional voltage signal effecting a ground fault current; providing the three-phase voltage to the motor; detecting a ground fault current between the motor and the adjustable speed drive; and outputting an indication of a ground fault when the ground fault current exceeds a predetermined threshold. 9. The method of claim 8, wherein the additional voltage signal modifies a ground fault current by increasing a magnitude of the ground fault current. 10. The method of claim 8, wherein the additional voltage signal is one of a low-frequency alternating current waveform and a direct current. 11. A system for generating variable frequency voltage for an alternating current motor, the system comprising:
a controller including at least one processor, the at least one processor configured to
generate a three-phase voltage for the motor;
generate an additional voltage component, the additional voltage component added onto each phase of the three-phase voltage to increase a magnitude of a ground fault current; and
provide the three-phase voltage injected with the additional voltage signal to the motor. 12. The system of claim 11, further comprising a user interface configured to receive instructions from a user, the instructions including an operating speed for the motor. 13. The system of claim 12, wherein the at least one processor is configured to receive the instructions from the user interface and generate the three-phase voltage for the motor based on the instructions. 14. The system of claim 11, further comprising a ground fault relay configured to detect a ground fault, measure the magnitude of the ground fault current, and output an indication of a ground fault to the controller when the magnitude exceeds a predetermined value. | 2,800 |
12,139 | 12,139 | 16,721,649 | 2,884 | A processing device determines a plurality of angles from which tracking images can be generated by an imaging device. The processing device generates a plurality of projections of a treatment planning image of a patient, the treatment planning image comprising a delineated target, wherein each projection of the plurality of projections has an angle that corresponds to one of the plurality of angles from which the tracking images can be taken. The processing device determines, for each angle of the plurality of angles, a value of a tracking quality metric for tracking the target based on an analysis of a projection generated at that angle. The processing device selects a subset of the plurality of angles that have a tracking quality metric value that satisfies a tracking quality metric criterion. | 1. A method comprising:
determining, by a processing device, a plurality of angles from which tracking images can be generated by an imaging device; generating, by the processing device, a plurality of projections of a treatment planning image, the treatment planning image comprising a delineated target, wherein each projection of the plurality of projections has an angle that corresponds to one of the plurality of angles from which the tracking images can be taken; determining, for each angle of the plurality of angles, a value of a tracking quality metric for tracking the target based on an analysis of a projection generated at that angle; and selecting, by the processing device, a subset of the plurality of angles that have a tracking quality metric value that satisfies a tracking quality metric criterion, one or more angles of the subset to be used to generate a tracking image of the target during a treatment stage. 2. The method of claim 1, wherein the treatment planning image comprises a magnetic resonance imaging (MRI) scan or a computer tomography (CT) scan of the patient, the method further comprising:
generating the MRI scan or the CT scan of the patient; and receiving a delineation of the target in the MRI scan or the CT scan. 3. The method of claim 1, wherein generating the plurality of projections comprises generating a plurality of digitally reconstructed radiographs (DRRs). 4. The method of claim 3, wherein the treatment planning image is a three-dimensional (3D) treatment planning image, and wherein generating a DRR for a particular angle of the plurality of angles comprises:
generating a target region DRR for the particular angle based on tracing rays at the particular angle through a region of the 3D treatment planning image that includes the delineated target, wherein additional regions of the 3D treatment planning image that do not include the delineated target are excluded from the traced rays; and generating a standard DRR for the particular angle based on tracing rays at the particular angle through the 3D treatment planning image. 5. The method of claim 4, wherein determining the tracking quality metric for the particular angle comprises:
searching for the target in the standard DRR using the target region DRR based on a target tracking algorithm that will be used to track the target from tracking images during the treatment of the patient, wherein a failure to identify the target in the standard DRR from the searching causes the particular angle to have a particular tracking quality metric value that fails to satisfy the tracking quality metric criterion. 6. The method of claim 5, wherein searching for the target in the standard DRR using the target region DRR comprises performing pattern matching to find one or more patterns in the standard DRR that match a pattern of the target in the target region DRR, wherein identification of multiple patterns in the standard DRR that match the pattern of the target in the target region DRR causes the particular angle to have a particular tracking quality metric value that fails to satisfy the tracking quality metric criterion. 7. The method of claim 5, wherein searching for the target in the standard DRR using the target region DRR comprises performing pattern matching to find a first pattern in the standard DRR that matches a second pattern of the target in the target region DRR, wherein the tracking quality metric value is proportional to a degree of similarity between the first pattern and the second pattern. 8. The method of claim 3, wherein determining the tracking quality metric value for a particular angle of the plurality of angles comprises:
determining a contrast between the delineated target and a surrounding region of the delineated target in a DRR of the plurality of DRRs that is generated for the particular angle; and determining the tracking quality metric value for the particular angle based at least in part on the contrast, wherein the tracking quality metric criterion comprises at least one of a minimum acceptable contrast or a minimum acceptable contrast to noise ratio. 9. The method of claim 3, wherein determining the tracking quality metric value for a particular angle of the plurality of angles comprises:
determining an edge of the delineated target in a DRR of the plurality of DRRs that is generated for the particular angle; determining an edge strength for the edge; and determining the tracking quality metric value for the particular angle based at least in part on the edge strength, wherein the tracking quality metric criterion comprises a minimum acceptable edge strength. 10. The method of claim 3, wherein the treatment planning image further comprises an additional delineated structure, and wherein determining the tracking quality metric value for the particular angle comprises:
determining whether there is an overlap between the delineated target and the additional delineated structure in a DRR of the plurality of DRRs that is generated for the particular angle, wherein an overlap between the delineated target and the additional delineated structure causes the tracking quality metric value for the particular angle to fail to satisfy the tracking quality metric criterion. 11. The method of claim 1, wherein the treatment planning image comprises a computer tomography (CT) scan, and wherein generating a projection of the plurality of projections for a particular angle of the plurality of angles comprises:
tracing a ray through the CT scan at the particular angle, wherein the ray passes through the delineated target; accumulating CT values for the ray as the ray traverses the CT scan; and generating an effective depth value based on an accumulation of the CT values, wherein the effective depth value represents a total accumulated density of material traversed by the ray, and wherein the tracking quality metric criterion comprises a maximum acceptable effective depth value. 12. The method of claim 1, wherein the plurality of angles is in a 360 degree arc around the patient. 13. The method of claim 1, wherein the treatment planning image is a three-dimensional (3D) treatment planning image, and wherein the target comprises a plurality of fiducials, and wherein generating a projection of the plurality of projections for a particular angle of the plurality of angles comprises:
projecting positions of the plurality of fiducials from a 3D space of the 3D treatment planning image at the particular angle onto a two-dimensional (2D) virtual detector plane. 14. The method of claim 1, wherein determining the tracking quality metric value for the particular angle comprises:
determining whether a first fiducial of the plurality of fiducials overlaps a second fiducial of the plurality of fiducials in the virtual 2D detector plane, wherein an overlap between the first fiducial and the second fiducial causes the tracking quality metric value for the particular angle to fail to satisfy the tracking quality metric criterion. 15. The method of claim 13, wherein determining the tracking quality metric value for the particular angle comprises determining an amount of separation between the plurality of fiducials in the virtual 2D detector plane, and wherein the angles in the subset are angles having a maximum amount of separation between the plurality of fiducials. 16. The method of claim 1, further comprising:
ordering the plurality of angles based on the tracking quality metric, wherein the subset of the plurality of angles comprises angles having highest tracking quality metric values. 17. A computing device comprising:
a memory; and a processing device operatively coupled to the memory, the processing device to:
determine a plurality of angles from which tracking images can be generated by an imaging device;
generate a plurality of projections of a treatment planning image of a patient, the treatment planning image comprising a delineated target, wherein each projection of the plurality of projections has an angle that corresponds to one of the plurality of angles from which the tracking images can be taken;
determine, for each angle of the plurality of angles, a value of a tracking quality metric for tracking the target based on an analysis of a projection generated at that angle; and
select a subset of the plurality of angles that have a tracking quality metric value that satisfies a tracking quality metric criterion, one or more angles from the subset to be used to generate a tracking image of the target during a treatment stage. 18. The computing device of claim 17, wherein generating the plurality of projections comprises generating a plurality of digitally reconstructed radiographs (DRRs), and wherein to the processing device is to:
generate a target region DRR for a particular angle of the plurality of angles based on tracing rays at the particular angle through a region of the treatment planning image that includes the delineated target, wherein additional regions of the treatment planning image that do not include the delineated target are excluded from the traced rays; generate a standard DRR for the particular angle based on tracing rays at the particular angle through the treatment planning image; and determine the tracking quality metric for the particular angle based on searching for the target in the standard DRR using the target region DRR based on a target tracking algorithm that will be used to track the target from tracking images during the treatment stage, wherein a failure to identify the target in the standard DRR from the searching causes the particular angle to have a particular tracking quality metric value that fails to satisfy the tracking quality metric criterion. 19. The computing device of claim 17, wherein the treatment planning image comprises a computer tomography (CT) scan, and wherein to generate a projection of the plurality of projections for a particular angle of the plurality of angles the processing device is to:
trace a ray through the CT scan at the particular angle, wherein the ray passes through the delineated target; accumulate CT values for the ray as the ray traverses the CT scan; and generate an effective depth value based on an accumulation of the CT values, wherein the effective depth value represents a total accumulated density of material traversed by the ray, wherein the tracking quality metric criterion comprises a maximum acceptable effective depth value. 20. The computing device of claim 17, wherein the treatment planning image is a three-dimensional (3D) treatment planning image, and wherein:
the target comprises a plurality of fiducials; to generate a projection of the plurality of projections for a particular angle of the plurality of angles the processing device is to project positions of the plurality of fiducials from a 3D space of the 3D treatment planning image at the particular angle onto a two-dimensional (2D) virtual detector plane; and to determine the tracking quality metric for the particular angle the processing device is to determine whether a first fiducial of the plurality of fiducials overlaps a second fiducial of the plurality of fiducials in the virtual 2D detector plane, wherein an overlap between the first fiducial and the second fiducial causes the tracking quality metric value for the particular angle to fail to satisfy the tracking quality metric criterion. | A processing device determines a plurality of angles from which tracking images can be generated by an imaging device. The processing device generates a plurality of projections of a treatment planning image of a patient, the treatment planning image comprising a delineated target, wherein each projection of the plurality of projections has an angle that corresponds to one of the plurality of angles from which the tracking images can be taken. The processing device determines, for each angle of the plurality of angles, a value of a tracking quality metric for tracking the target based on an analysis of a projection generated at that angle. The processing device selects a subset of the plurality of angles that have a tracking quality metric value that satisfies a tracking quality metric criterion.1. A method comprising:
determining, by a processing device, a plurality of angles from which tracking images can be generated by an imaging device; generating, by the processing device, a plurality of projections of a treatment planning image, the treatment planning image comprising a delineated target, wherein each projection of the plurality of projections has an angle that corresponds to one of the plurality of angles from which the tracking images can be taken; determining, for each angle of the plurality of angles, a value of a tracking quality metric for tracking the target based on an analysis of a projection generated at that angle; and selecting, by the processing device, a subset of the plurality of angles that have a tracking quality metric value that satisfies a tracking quality metric criterion, one or more angles of the subset to be used to generate a tracking image of the target during a treatment stage. 2. The method of claim 1, wherein the treatment planning image comprises a magnetic resonance imaging (MRI) scan or a computer tomography (CT) scan of the patient, the method further comprising:
generating the MRI scan or the CT scan of the patient; and receiving a delineation of the target in the MRI scan or the CT scan. 3. The method of claim 1, wherein generating the plurality of projections comprises generating a plurality of digitally reconstructed radiographs (DRRs). 4. The method of claim 3, wherein the treatment planning image is a three-dimensional (3D) treatment planning image, and wherein generating a DRR for a particular angle of the plurality of angles comprises:
generating a target region DRR for the particular angle based on tracing rays at the particular angle through a region of the 3D treatment planning image that includes the delineated target, wherein additional regions of the 3D treatment planning image that do not include the delineated target are excluded from the traced rays; and generating a standard DRR for the particular angle based on tracing rays at the particular angle through the 3D treatment planning image. 5. The method of claim 4, wherein determining the tracking quality metric for the particular angle comprises:
searching for the target in the standard DRR using the target region DRR based on a target tracking algorithm that will be used to track the target from tracking images during the treatment of the patient, wherein a failure to identify the target in the standard DRR from the searching causes the particular angle to have a particular tracking quality metric value that fails to satisfy the tracking quality metric criterion. 6. The method of claim 5, wherein searching for the target in the standard DRR using the target region DRR comprises performing pattern matching to find one or more patterns in the standard DRR that match a pattern of the target in the target region DRR, wherein identification of multiple patterns in the standard DRR that match the pattern of the target in the target region DRR causes the particular angle to have a particular tracking quality metric value that fails to satisfy the tracking quality metric criterion. 7. The method of claim 5, wherein searching for the target in the standard DRR using the target region DRR comprises performing pattern matching to find a first pattern in the standard DRR that matches a second pattern of the target in the target region DRR, wherein the tracking quality metric value is proportional to a degree of similarity between the first pattern and the second pattern. 8. The method of claim 3, wherein determining the tracking quality metric value for a particular angle of the plurality of angles comprises:
determining a contrast between the delineated target and a surrounding region of the delineated target in a DRR of the plurality of DRRs that is generated for the particular angle; and determining the tracking quality metric value for the particular angle based at least in part on the contrast, wherein the tracking quality metric criterion comprises at least one of a minimum acceptable contrast or a minimum acceptable contrast to noise ratio. 9. The method of claim 3, wherein determining the tracking quality metric value for a particular angle of the plurality of angles comprises:
determining an edge of the delineated target in a DRR of the plurality of DRRs that is generated for the particular angle; determining an edge strength for the edge; and determining the tracking quality metric value for the particular angle based at least in part on the edge strength, wherein the tracking quality metric criterion comprises a minimum acceptable edge strength. 10. The method of claim 3, wherein the treatment planning image further comprises an additional delineated structure, and wherein determining the tracking quality metric value for the particular angle comprises:
determining whether there is an overlap between the delineated target and the additional delineated structure in a DRR of the plurality of DRRs that is generated for the particular angle, wherein an overlap between the delineated target and the additional delineated structure causes the tracking quality metric value for the particular angle to fail to satisfy the tracking quality metric criterion. 11. The method of claim 1, wherein the treatment planning image comprises a computer tomography (CT) scan, and wherein generating a projection of the plurality of projections for a particular angle of the plurality of angles comprises:
tracing a ray through the CT scan at the particular angle, wherein the ray passes through the delineated target; accumulating CT values for the ray as the ray traverses the CT scan; and generating an effective depth value based on an accumulation of the CT values, wherein the effective depth value represents a total accumulated density of material traversed by the ray, and wherein the tracking quality metric criterion comprises a maximum acceptable effective depth value. 12. The method of claim 1, wherein the plurality of angles is in a 360 degree arc around the patient. 13. The method of claim 1, wherein the treatment planning image is a three-dimensional (3D) treatment planning image, and wherein the target comprises a plurality of fiducials, and wherein generating a projection of the plurality of projections for a particular angle of the plurality of angles comprises:
projecting positions of the plurality of fiducials from a 3D space of the 3D treatment planning image at the particular angle onto a two-dimensional (2D) virtual detector plane. 14. The method of claim 1, wherein determining the tracking quality metric value for the particular angle comprises:
determining whether a first fiducial of the plurality of fiducials overlaps a second fiducial of the plurality of fiducials in the virtual 2D detector plane, wherein an overlap between the first fiducial and the second fiducial causes the tracking quality metric value for the particular angle to fail to satisfy the tracking quality metric criterion. 15. The method of claim 13, wherein determining the tracking quality metric value for the particular angle comprises determining an amount of separation between the plurality of fiducials in the virtual 2D detector plane, and wherein the angles in the subset are angles having a maximum amount of separation between the plurality of fiducials. 16. The method of claim 1, further comprising:
ordering the plurality of angles based on the tracking quality metric, wherein the subset of the plurality of angles comprises angles having highest tracking quality metric values. 17. A computing device comprising:
a memory; and a processing device operatively coupled to the memory, the processing device to:
determine a plurality of angles from which tracking images can be generated by an imaging device;
generate a plurality of projections of a treatment planning image of a patient, the treatment planning image comprising a delineated target, wherein each projection of the plurality of projections has an angle that corresponds to one of the plurality of angles from which the tracking images can be taken;
determine, for each angle of the plurality of angles, a value of a tracking quality metric for tracking the target based on an analysis of a projection generated at that angle; and
select a subset of the plurality of angles that have a tracking quality metric value that satisfies a tracking quality metric criterion, one or more angles from the subset to be used to generate a tracking image of the target during a treatment stage. 18. The computing device of claim 17, wherein generating the plurality of projections comprises generating a plurality of digitally reconstructed radiographs (DRRs), and wherein to the processing device is to:
generate a target region DRR for a particular angle of the plurality of angles based on tracing rays at the particular angle through a region of the treatment planning image that includes the delineated target, wherein additional regions of the treatment planning image that do not include the delineated target are excluded from the traced rays; generate a standard DRR for the particular angle based on tracing rays at the particular angle through the treatment planning image; and determine the tracking quality metric for the particular angle based on searching for the target in the standard DRR using the target region DRR based on a target tracking algorithm that will be used to track the target from tracking images during the treatment stage, wherein a failure to identify the target in the standard DRR from the searching causes the particular angle to have a particular tracking quality metric value that fails to satisfy the tracking quality metric criterion. 19. The computing device of claim 17, wherein the treatment planning image comprises a computer tomography (CT) scan, and wherein to generate a projection of the plurality of projections for a particular angle of the plurality of angles the processing device is to:
trace a ray through the CT scan at the particular angle, wherein the ray passes through the delineated target; accumulate CT values for the ray as the ray traverses the CT scan; and generate an effective depth value based on an accumulation of the CT values, wherein the effective depth value represents a total accumulated density of material traversed by the ray, wherein the tracking quality metric criterion comprises a maximum acceptable effective depth value. 20. The computing device of claim 17, wherein the treatment planning image is a three-dimensional (3D) treatment planning image, and wherein:
the target comprises a plurality of fiducials; to generate a projection of the plurality of projections for a particular angle of the plurality of angles the processing device is to project positions of the plurality of fiducials from a 3D space of the 3D treatment planning image at the particular angle onto a two-dimensional (2D) virtual detector plane; and to determine the tracking quality metric for the particular angle the processing device is to determine whether a first fiducial of the plurality of fiducials overlaps a second fiducial of the plurality of fiducials in the virtual 2D detector plane, wherein an overlap between the first fiducial and the second fiducial causes the tracking quality metric value for the particular angle to fail to satisfy the tracking quality metric criterion. | 2,800 |
12,140 | 12,140 | 15,824,177 | 2,822 | An electronic device includes a plurality of pixel electrodes, an active layer on the plurality of pixel electrodes, an opposed electrode on the active layer and covering an entirety of an upper surface of the active layer, and a first encapsulation film on the opposed electrode wherein the opposed electrode and the first encapsulation film have a common planar shapes. | 1. An electronic device, comprising:
a plurality of pixel electrodes; an active layer on the plurality of pixel electrodes; an opposed electrode on the active layer and covering an entirety of an upper surface of the active layer; and a first encapsulation film on the opposed electrode, wherein the opposed electrode and the first encapsulation film have a common planar shape. 2. The electronic device of claim 1, wherein a vertical area of the opposed electrode is larger than a vertical area of the active layer. 3. The electronic device of claim 2, wherein a gap between one edge of the opposed electrode and one edge of the active layer is about 1 μm to about 100 μm. 4. The electronic device of claim 2, wherein the opposed electrode covers the upper surface of the active layer and a plurality of side surfaces of the active layer. 5. The electronic device of claim 1, wherein the first encapsulation film includes a material that is one material of an oxide, a nitride, or an oxynitride. 6. The electronic device of claim 5, wherein the material includes at least one element of aluminum, titanium, zirconium, hafnium, tantalum, and silicon. 7. The electronic device of claim 1, wherein the first encapsulation film has a thickness of about 2 nm to about 30 nm. 8. The electronic device of claim 1, further comprising a second encapsulation film on the first encapsulation film. 9. The electronic device of claim 8, wherein the second encapsulation film has a common planar shape as the opposed electrode and the first encapsulation film. 10. The electronic device of claim 8, wherein the second encapsulation film includes a common material in relation to the first encapsulation film. 11. The electronic device of claim 10, wherein the second encapsulation film has a different film quality in relation to a film quality of the first encapsulation film. 12. The electronic device of claim 11, wherein the second encapsulation film has a greater film density than a film density of the first encapsulation film. 13. The electronic device of claim 8, wherein the second encapsulation film includes a different material from a material of the first encapsulation film. 14. The electronic device of claim 13, wherein
the first encapsulation film includes one material of an oxide, a nitride, or an oxynitride, the one material included in the first encapsulation film including at least one element of aluminum, titanium, zirconium, hafnium, and tantalum, and the second encapsulation film including one material of an oxide, a nitride, or an oxynitride, the one material included in the second encapsulation film including silicon. 15. The electronic device of claim 8, wherein the second encapsulation film is thicker than the first encapsulation film, and the second encapsulation film has a thickness of about 10 nm to about 200 nm. 16. The electronic device of claim 8, further comprising a third encapsulation film covering the second encapsulation film. 17. The electronic device of claim 16, wherein the third encapsulation film includes one material of an oxide, a nitride, an oxynitride, an organic material, or an organic/inorganic composite. 18. The electronic device of claim 1, wherein the active layer is a light-absorbing layer that is configured to selectively absorb light in one wavelength spectrum of light of a red wavelength spectrum of light, a green wavelength spectrum of light, and a blue wavelength spectrum of light. 19. The electronic device of claim 1, further comprising:
a semiconductor substrate under the plurality of pixel electrodes, wherein the semiconductor substrate includes a plurality of photo-sensing devices vertically overlapping with the plurality of pixel electrodes. 20. The electronic device of claim 19, further comprising a color filter layer between the plurality of pixel electrodes and the semiconductor substrate. 21. A method of manufacturing an electronic device, the method comprising:
forming a pixel electrode; forming an active layer on the pixel electrode; forming a conductive layer associated with an opposed electrode on the active layer; forming a thin film associated with a first encapsulation film on the conductive layer associated with the opposed electrode; and simultaneously or sequentially etching the thin film associated with the first encapsulation film and the conductive layer associated with the opposed electrode to form the first encapsulation film and the opposed electrode, such that the first encapsulation film and the opposed electrode have a common planar shape. 22. The method of claim 21, wherein the etching is performed based on at least one process of photolithography and dry etching. 23. The method of claim 21, further comprising:
forming a thin film associated with a second encapsulation film subsequently to forming the thin film associated with the first encapsulation film. 24. The method of claim 23, wherein the thin film associated with the second encapsulation film, the thin film associated with the first encapsulation film, and the conductive layer associated with the opposed electrode are simultaneously or sequentially etched to form the second encapsulation film, the first encapsulation film, and the opposed electrode such that the second encapsulation film, the first encapsulation film, and the opposed electrode have the common planar shape. 25. The method of claim 23, wherein the second encapsulation film is formed at a higher temperature than the first encapsulation film. 26. The method of claim 25, wherein
the first encapsulation film is formed at less than or equal to about 110° C., and the second encapsulation film is formed at less than or equal to about 220° C. 27. The method of claim 24, further comprising forming a third encapsulation film on the second encapsulation film. 28. An electronic apparatus comprising the electronic device according to claim 1. 29. An electronic device, comprising:
a semiconductor substrate; a plurality of photo-sensing devices integrated into the semiconductor substrate; a photoelectric device on the semiconductor substrate, the photoelectric device including
a plurality of pixel electrodes on the semiconductor substrate, each pixel electrode vertically overlapping a separate set of one or more photo-sensing devices of the plurality of photo-sensing devices,
an active layer on the plurality of pixel electrodes, and
an opposed electrode on the active layer and covering an entirety of an upper surface of the active layer; and
a first encapsulation film on the opposed electrode, wherein the opposed electrode and the first encapsulation film have a common planar shape. 30. The electronic device of claim 29, further comprising:
a color filter layer on the semiconductor substrate, the color filter layer including a plurality of color filters, each color filter of the plurality of color filters vertically overlapping a separate photo-sensing device of the plurality of photo-sensing devices. 31. The electronic device of claim 30, wherein
the photoelectric device is between the color filter layer and the plurality of photo-sensing devices, the active layer is a light-absorbing layer that is configured to selectively absorb light in one wavelength spectrum of light of a red wavelength spectrum of light, a green wavelength spectrum of light, and a blue wavelength spectrum of light, and adjacent color filters of the plurality of color filters are configured to selectively transmit different wavelength spectra of mixed light of a plurality of wavelength spectra of mixed light, the different wavelength spectra of mixed light including both the one wavelength spectrum of light and different additional wavelength spectra of light, respectively. 32. The electronic device of claim 29, wherein a vertical area of the opposed electrode is larger than a vertical area of the active layer. 33. The electronic device of claim 29, wherein the first encapsulation film includes an oxide, a nitride, or an oxynitride. 34. The electronic device of claim 29, wherein the first encapsulation film has a thickness of about 2 nm to about 30 nm. 35. The electronic device of claim 29, further comprising a second encapsulation film on the first encapsulation film. | An electronic device includes a plurality of pixel electrodes, an active layer on the plurality of pixel electrodes, an opposed electrode on the active layer and covering an entirety of an upper surface of the active layer, and a first encapsulation film on the opposed electrode wherein the opposed electrode and the first encapsulation film have a common planar shapes.1. An electronic device, comprising:
a plurality of pixel electrodes; an active layer on the plurality of pixel electrodes; an opposed electrode on the active layer and covering an entirety of an upper surface of the active layer; and a first encapsulation film on the opposed electrode, wherein the opposed electrode and the first encapsulation film have a common planar shape. 2. The electronic device of claim 1, wherein a vertical area of the opposed electrode is larger than a vertical area of the active layer. 3. The electronic device of claim 2, wherein a gap between one edge of the opposed electrode and one edge of the active layer is about 1 μm to about 100 μm. 4. The electronic device of claim 2, wherein the opposed electrode covers the upper surface of the active layer and a plurality of side surfaces of the active layer. 5. The electronic device of claim 1, wherein the first encapsulation film includes a material that is one material of an oxide, a nitride, or an oxynitride. 6. The electronic device of claim 5, wherein the material includes at least one element of aluminum, titanium, zirconium, hafnium, tantalum, and silicon. 7. The electronic device of claim 1, wherein the first encapsulation film has a thickness of about 2 nm to about 30 nm. 8. The electronic device of claim 1, further comprising a second encapsulation film on the first encapsulation film. 9. The electronic device of claim 8, wherein the second encapsulation film has a common planar shape as the opposed electrode and the first encapsulation film. 10. The electronic device of claim 8, wherein the second encapsulation film includes a common material in relation to the first encapsulation film. 11. The electronic device of claim 10, wherein the second encapsulation film has a different film quality in relation to a film quality of the first encapsulation film. 12. The electronic device of claim 11, wherein the second encapsulation film has a greater film density than a film density of the first encapsulation film. 13. The electronic device of claim 8, wherein the second encapsulation film includes a different material from a material of the first encapsulation film. 14. The electronic device of claim 13, wherein
the first encapsulation film includes one material of an oxide, a nitride, or an oxynitride, the one material included in the first encapsulation film including at least one element of aluminum, titanium, zirconium, hafnium, and tantalum, and the second encapsulation film including one material of an oxide, a nitride, or an oxynitride, the one material included in the second encapsulation film including silicon. 15. The electronic device of claim 8, wherein the second encapsulation film is thicker than the first encapsulation film, and the second encapsulation film has a thickness of about 10 nm to about 200 nm. 16. The electronic device of claim 8, further comprising a third encapsulation film covering the second encapsulation film. 17. The electronic device of claim 16, wherein the third encapsulation film includes one material of an oxide, a nitride, an oxynitride, an organic material, or an organic/inorganic composite. 18. The electronic device of claim 1, wherein the active layer is a light-absorbing layer that is configured to selectively absorb light in one wavelength spectrum of light of a red wavelength spectrum of light, a green wavelength spectrum of light, and a blue wavelength spectrum of light. 19. The electronic device of claim 1, further comprising:
a semiconductor substrate under the plurality of pixel electrodes, wherein the semiconductor substrate includes a plurality of photo-sensing devices vertically overlapping with the plurality of pixel electrodes. 20. The electronic device of claim 19, further comprising a color filter layer between the plurality of pixel electrodes and the semiconductor substrate. 21. A method of manufacturing an electronic device, the method comprising:
forming a pixel electrode; forming an active layer on the pixel electrode; forming a conductive layer associated with an opposed electrode on the active layer; forming a thin film associated with a first encapsulation film on the conductive layer associated with the opposed electrode; and simultaneously or sequentially etching the thin film associated with the first encapsulation film and the conductive layer associated with the opposed electrode to form the first encapsulation film and the opposed electrode, such that the first encapsulation film and the opposed electrode have a common planar shape. 22. The method of claim 21, wherein the etching is performed based on at least one process of photolithography and dry etching. 23. The method of claim 21, further comprising:
forming a thin film associated with a second encapsulation film subsequently to forming the thin film associated with the first encapsulation film. 24. The method of claim 23, wherein the thin film associated with the second encapsulation film, the thin film associated with the first encapsulation film, and the conductive layer associated with the opposed electrode are simultaneously or sequentially etched to form the second encapsulation film, the first encapsulation film, and the opposed electrode such that the second encapsulation film, the first encapsulation film, and the opposed electrode have the common planar shape. 25. The method of claim 23, wherein the second encapsulation film is formed at a higher temperature than the first encapsulation film. 26. The method of claim 25, wherein
the first encapsulation film is formed at less than or equal to about 110° C., and the second encapsulation film is formed at less than or equal to about 220° C. 27. The method of claim 24, further comprising forming a third encapsulation film on the second encapsulation film. 28. An electronic apparatus comprising the electronic device according to claim 1. 29. An electronic device, comprising:
a semiconductor substrate; a plurality of photo-sensing devices integrated into the semiconductor substrate; a photoelectric device on the semiconductor substrate, the photoelectric device including
a plurality of pixel electrodes on the semiconductor substrate, each pixel electrode vertically overlapping a separate set of one or more photo-sensing devices of the plurality of photo-sensing devices,
an active layer on the plurality of pixel electrodes, and
an opposed electrode on the active layer and covering an entirety of an upper surface of the active layer; and
a first encapsulation film on the opposed electrode, wherein the opposed electrode and the first encapsulation film have a common planar shape. 30. The electronic device of claim 29, further comprising:
a color filter layer on the semiconductor substrate, the color filter layer including a plurality of color filters, each color filter of the plurality of color filters vertically overlapping a separate photo-sensing device of the plurality of photo-sensing devices. 31. The electronic device of claim 30, wherein
the photoelectric device is between the color filter layer and the plurality of photo-sensing devices, the active layer is a light-absorbing layer that is configured to selectively absorb light in one wavelength spectrum of light of a red wavelength spectrum of light, a green wavelength spectrum of light, and a blue wavelength spectrum of light, and adjacent color filters of the plurality of color filters are configured to selectively transmit different wavelength spectra of mixed light of a plurality of wavelength spectra of mixed light, the different wavelength spectra of mixed light including both the one wavelength spectrum of light and different additional wavelength spectra of light, respectively. 32. The electronic device of claim 29, wherein a vertical area of the opposed electrode is larger than a vertical area of the active layer. 33. The electronic device of claim 29, wherein the first encapsulation film includes an oxide, a nitride, or an oxynitride. 34. The electronic device of claim 29, wherein the first encapsulation film has a thickness of about 2 nm to about 30 nm. 35. The electronic device of claim 29, further comprising a second encapsulation film on the first encapsulation film. | 2,800 |
12,141 | 12,141 | 13,702,169 | 2,865 | Described are techniques for processing data. Sample analysis is performed generating scans of data. Each scan comprises a set of data elements each associating an ion intensity count with a plurality of dimensions including a retention time dimension and a mass to charge ratio dimension. The scans are analyzed to identify one or more ion peaks. Analyzing includes filtering a first plurality of the scans producing a first plurality of filtered output scans. The filtering including first filtering producing a first filtering output, wherein the first filtering includes executing a plurality of threads in parallel which apply a first filter to the first plurality of scans to produce the first filtering output. Each of the plurality of threads computes at least one filtered output point for at least one corresponding input point included in the plurality of scans. Analyzing includes detecting one or more peaks using the filtered output scans. | 1. A method for processing data comprising:
performing sample analysis and generating scans of data, each of said scans comprising a set of data elements each associating an ion intensity count with a plurality of dimensions including a retention time dimension and a mass to charge ratio dimension; and analyzing said scans to identify one or more ion peaks, said analyzing including:
filtering a first plurality of said scans producing a first plurality of filtered output scans, said filtering including first filtering producing a first filtering output, wherein said first filtering includes executing a plurality of threads in parallel which apply a first filter to said first plurality of scans to produce said first filtering output, wherein each of said plurality of threads computes at least one filtered output point for at least one corresponding input point included in said plurality of scans; and
detecting one or more peaks using said filtered output scans. 2. The method of claim 1, wherein said first filtering includes:
performing first processing by a first of said plurality of threads, said first processing including applying a smoothing filter to a first input point in a mass-to-charge ratio dimension to produce a first filtered output point and applying a second derivative filter to the first input point in a mass-to-charge ratio dimension to produce a second filtered output point; and performing second processing by a second of said plurality of threads, said second processing including applying said smoothing filter to a second input point in a mass-to-charge ratio dimension to produce a third filtered output point and applying the second derivative filter to the second input point in a mass-to-charge ratio dimension to produce a fourth filtered output point, wherein said first thread and said second thread execute concurrently and said first thread and said second thread are included in a same block of threads accessing a plurality of input points including said first point and said second point from a portion of memory shared by said block of threads. 3. The method of claim 2, wherein said first plurality of threads are included in a two-dimensional grid of thread blocks, each of said thread blocks including a two-dimensional configuration of threads, each of said thread blocks being identified in said grid using a thread block identifier having an “x” dimension indexing said each thread block along the mass to charge ratio axis and having a “y” dimension indexing said each thread block along the retention time axis. 4. The method of claim 3, wherein said first thread determines a first input point to which said smoothing filter is applied by said first thread and said first thread determines a first output point identifying a location at which a corresponding filtered output point for said first input is stored, said first input point being identified in said first plurality of scans in accordance with coordinates (m, s), wherein “m” is a mass coordinate mapping to a mass to charge ratio of said first input point and “s” identifies a scan in which said first input point is included, wherein said first output point is also identified using the coordinates (m,s). 5. The method of claim 4, wherein said first thread is included in a first thread block having a first thread block identifier, said first thread having a first thread identifier identifying a position of said first thread within said first thread block, wherein said first thread determines the coordinates (m,s) using said first thread block identifier and said first thread identifier. 6. The method of claim 2, wherein said first filtering uses filtering coefficients bound to a texture. 7. The method of claim 6, wherein said filtering coefficients are used in connection with filtering a portion of less than all mass to charge ratio values in said first plurality of scans. 8. The method of claim 1, wherein said filtering includes executing a second plurality of threads concurrently, wherein each of said second plurality of threads applies a second filter in a retention time dimension to at least one data point. 9. The method of claim 8, wherein said second filter is any of a smoothing filter and second derivative filter. 10. The method of claim 8, wherein said second filter uses a same set of filter coefficients for all data points to which the second filter is applied. 11. The method of claim 10, wherein the filter coefficients are stored in constant memory used by a graphics processing unit, said graphics processing unit and said constant memory being included in a separate device configured for used with a computer. 12. The method of claim 8, wherein said second plurality of threads is included in a two-dimensional grid of thread blocks, each of said thread blocks being a two-dimensional block of threads. 13. The method of claim 1, further comprising:
determining first thread block dimensions of a first block of threads configured for parallel execution and each thread in said first block configured to apply a filter in a mass to charge ratio dimension to at least one data point; determining second thread block dimensions of a second block of threads configured for parallel execution and each thread in said second block configured to apply a filter in a retention time dimension to at least one data point; determining third thread block dimensions, wherein each dimension of said third thread block is a least common multiple of corresponding ones of said each dimension of said first thread block and said second thread block; and selecting scan pack dimensions in accordance with said third block dimensions, wherein said scan pack dimensions indicate sizing with respect to a number of said scans of data and a number of mass to charge ratio values per scan, wherein said analyzing is performed on a first scan pack before performing said analyzing with respect to a second scan pack, said first scan pack including a first portion of said scans of data and having said scan pack dimensions, said second scan pack including a second portion of said scans of data and having said scan pack dimensions. 14. The method of claim 13, wherein said first scan pack includes said first plurality of scans, and the method further comprising:
reading, by executing code on a processing unit of a computer which executes instructions serially, said first scan pack; storing said first scan pack in a first memory of said computer; copying said first scan pack into a second memory of a device, said device including a graphics processing unit that performs parallel processing, wherein said second memory is configured for use by said graphics processing unit when performing parallel processing and wherein said first memory is not configured for use by said graphics processing unit; performing said first filtering by executing said plurality of threads in parallel on said graphics processor using said first scan pack to identify one or more peaks in said first scan pack; storing, by said graphics processing unit in said second memory, output data identifying said one or more peaks; and copying said output data from said second memory to said first memory. 15. The method of claim 1, wherein said detecting one or more peaks is performed by concurrently executing threads included in a two-dimensional grid of thread blocks, each of said thread blocks including a two-dimensional configuration of threads, wherein threads included in a same first thread block have access to data stored in a portion of memory shared by all threads in the first thread block, wherein each of said threads included in said two-dimensional grid determines whether at least one filtered output point included in said filtered output scans is a peak. 16. The method of claim 15, wherein each of said thread blocks has first dimensions selected in accordance with utilization of a processing unit which performs concurrent processing, a number of threads included in said thread block having said first dimensions, and an approximation of said first dimensions to a square. 17. The method of claim 15, wherein said one or more peaks identified by said detecting are identified with respect to retention time and mass to charge ratio dimensions. 18. The method of claim 17, wherein said plurality of dimensions includes an ion mobility dimension and the method includes identifying peaks with respect the ion mobility dimension. 19. The method of claim 18, wherein said analyzing includes identifying one or more properties for each of said one or more ion peaks identified and wherein, at least a first of said properties is determined by concurrently executing threads included in a grid of thread blocks, each of said threads determining said first property for at least one of peaks identified by said detecting. 20. The method of claim 1, wherein said method is performed in real-time while said scans are generated as a result of sample analysis by a mass spectrometer. 21. The method of claim 18, wherein said one or more peaks are a first set of peaks and said analyzing further comprising:
determining a scan pack size comprising a number of scans having different retention times; determining, for each peak in said first set, a data volume having dimensions in accordance with data used for filtering with respect to said each peak and an output volume having dimensions in accordance with said a starting and ending location of said each peak with respect to retention time and m/z dimensions and covering an ion mobility range; determining a buffer volume having each dimension thereof which is at least a same size as a largest corresponding dimension with respect to all data volumes for all peaks in said first set; determining a first portion of peaks of said first set which are included in a first scan pack of said scan pack size, said first scan pack including a partition of said scans; partitioning said first portion into one or more groups of peaks and, for each group, performing first processing, said first processing including:
reading, for each peak in said each group, first data from said first scan pack in accordance with the data volume for said each peak and storing the first data into a buffer having a size in accordance with said buffer volume;
filtering the first data for each peak in said each group, wherein said filtering the first data includes a second plurality of threads executing concurrently, wherein for said each peak, each of said second plurality of threads applies a filter and computes a single filtered output point for a corresponding data point in the buffer for said each peak if said corresponding data point is in included within appropriate ones of the output volume and the data volume for said each peak; and
identifying child peaks for said each group. 22. The method of claim 21, wherein, if said filter is applied in a retention time dimension, each of said second plurality of threads computes a single filtered output point for a corresponding data point in the buffer for said each peak if said corresponding data point is within the output volume with respect to the retention time axis and within the data volume with respect to the m/z and the ion mobility axes. 23. The method of claim 21, wherein, if said filter is applied in a retention time dimension, each of said second plurality of threads computes a single filtered output point for a corresponding data point in the buffer for said each peak if said corresponding data point is within the output volume with respect to the retention time and the m/z axes and within the data volume with respect to the ion mobility axis. 24. The method of claim 21, wherein, if said filter is applied in a retention time dimension, each of said second plurality of threads computes a single filtered output point for a corresponding data point in the buffer for said each peak if said corresponding data point is within the output volume with respect to the retention time, the m/z, and the ion mobility axes. 25. The method of claim 18, wherein said analyzing for a first peak further comprises:
applying a smoothing filter in the retention time dimension to first data stored in the first buffer to produce second data stored in a second buffer; applying a second derivative filter in the retention time dimension to the first data stored in the first buffer to produce third data stored in a third buffer; applying, after producing said second data and said third data, a smoothing filter in the mass to charge ratio dimension to the third data to produce fourth data stored in said first buffer; applying, after producing said fourth data, a smoothing filter in the ion mobility dimension to the fourth data to produce fifth data stored in said third buffer; applying, after producing said fifth data, a second derivative filter in the mass to charge ratio dimension to said second data to produce sixth data stored in the first buffer; applying, after producing said sixth data, a smoothing filter in the ion mobility dimension to said sixth data to produce seventh data which is combined with said fifth data to produce a first combined result stored in said third buffer; applying, after producing said first combined result, a smoothing filter in the mass to charge ratio dimension to the second data to produce eighth data stored in the first buffer; and applying, after producing said eighth data, a second derivative filter in the ion mobility dimension to the eighth data to produce ninth data which is combined with said first combined result to produce a second combined result stored in the third buffer. 26. The method of claim 21, wherein said filtering the first data for each peak includes applying a sequence of three filters, a first of the filters being applied with respect to a first dimension or first axis to the first data to produce a first output, a second of the filters being applied with respect to a second dimension or second axis to the first output to produce a second output, a third of the filters being applied with respect to a third dimension or third axis to the second output to produce a third output, 27. The method of claim 26, wherein said first output has a first size with respect to said first dimension which is less than a second size of the first data with respect to the first dimension, wherein said second output has a third size with respect to said second dimension which is less than fourth size of the first output with respect to the second dimension, and wherein said third output has a fourth size with respect to said third dimension which is less than fifth size of the second output with respect to the third dimension 28. A method for processing data from sample analysis comprising:
performing mass spectrometry and generating one or more spectra; and analyzing the one or more spectra to generate a peak list of one or more ion peaks identified in the one or more spectra, said analyzing including performing, in parallel, at least a first filtering step and a second filtering step. 29. The method of claim 28, wherein said analyzing includes filtering the one or more spectra and the first filtering step computes a first filtered output point and said second filtering step computes a second filtered output point. 30. The method of claim 29, wherein said filtering is performed in one of a plurality of dimensions, said plurality of dimensions including retention time, mass or m/z, and ion mobility. 31. A system that performs mass spectrometry comprising:
a parallel processing unit; and a computer readable medium comprising code stored thereon which, when executed, performs steps including:
receiving one or more spectra produced as a result of mass analyzing a sample; and
analyzing the one or more spectra to generate a peak list of one or more ion peaks identified in the one or more spectra, said analyzing including performing, in parallel using said parallel processing unit, at least a first filtering step and a second filtering step. 32. The system of claim 31, wherein said analyzing includes filtering the one or more spectra and the first filtering step computes a first filtered output point and said second filtering step computes a second filtered output point. 33. The system of claim 32, wherein said filtering performs filtering in one of a plurality of dimensions, said plurality of dimensions including retention time, mass or m/z, and ion mobility. 34. The system of claim 31, further comprising a processor which executes instructions serially, wherein said computer readable medium further includes code for:
performing preprocessing; obtaining said one or more spectra as input from a memory; performing peak detection to identify said one or more peaks; performing peak properties computation on said one or more peaks included in said peak list to generate peak property information; and writing said peak list and said peak property information to a memory; and
wherein said performing preprocessing, said obtaining, and said writing are performed by code executing in said processor and wherein said performing peak detection, said performing peak property computation are performed by code executing in the parallel processing unit. 35. The system of claim 34, wherein, in connection with performing said obtaining, said processor executes code that reads said one or more spectra, stores said one or more spectra in a first memory that is configured for access by said processor and is not configured for access by the parallel processing unit, and copies said one or more spectra from said first memory to a second memory included on a device comprising said parallel processing unit. 36. The system of claim 31, wherein said system output the peak list and stores the peak list to non-volatile memory, and wherein said one or more spectra are stored in volatile memory during said analyzing and said one or more spectra are not stored to non-volatile memory for output as a result of said analyzing. | Described are techniques for processing data. Sample analysis is performed generating scans of data. Each scan comprises a set of data elements each associating an ion intensity count with a plurality of dimensions including a retention time dimension and a mass to charge ratio dimension. The scans are analyzed to identify one or more ion peaks. Analyzing includes filtering a first plurality of the scans producing a first plurality of filtered output scans. The filtering including first filtering producing a first filtering output, wherein the first filtering includes executing a plurality of threads in parallel which apply a first filter to the first plurality of scans to produce the first filtering output. Each of the plurality of threads computes at least one filtered output point for at least one corresponding input point included in the plurality of scans. Analyzing includes detecting one or more peaks using the filtered output scans.1. A method for processing data comprising:
performing sample analysis and generating scans of data, each of said scans comprising a set of data elements each associating an ion intensity count with a plurality of dimensions including a retention time dimension and a mass to charge ratio dimension; and analyzing said scans to identify one or more ion peaks, said analyzing including:
filtering a first plurality of said scans producing a first plurality of filtered output scans, said filtering including first filtering producing a first filtering output, wherein said first filtering includes executing a plurality of threads in parallel which apply a first filter to said first plurality of scans to produce said first filtering output, wherein each of said plurality of threads computes at least one filtered output point for at least one corresponding input point included in said plurality of scans; and
detecting one or more peaks using said filtered output scans. 2. The method of claim 1, wherein said first filtering includes:
performing first processing by a first of said plurality of threads, said first processing including applying a smoothing filter to a first input point in a mass-to-charge ratio dimension to produce a first filtered output point and applying a second derivative filter to the first input point in a mass-to-charge ratio dimension to produce a second filtered output point; and performing second processing by a second of said plurality of threads, said second processing including applying said smoothing filter to a second input point in a mass-to-charge ratio dimension to produce a third filtered output point and applying the second derivative filter to the second input point in a mass-to-charge ratio dimension to produce a fourth filtered output point, wherein said first thread and said second thread execute concurrently and said first thread and said second thread are included in a same block of threads accessing a plurality of input points including said first point and said second point from a portion of memory shared by said block of threads. 3. The method of claim 2, wherein said first plurality of threads are included in a two-dimensional grid of thread blocks, each of said thread blocks including a two-dimensional configuration of threads, each of said thread blocks being identified in said grid using a thread block identifier having an “x” dimension indexing said each thread block along the mass to charge ratio axis and having a “y” dimension indexing said each thread block along the retention time axis. 4. The method of claim 3, wherein said first thread determines a first input point to which said smoothing filter is applied by said first thread and said first thread determines a first output point identifying a location at which a corresponding filtered output point for said first input is stored, said first input point being identified in said first plurality of scans in accordance with coordinates (m, s), wherein “m” is a mass coordinate mapping to a mass to charge ratio of said first input point and “s” identifies a scan in which said first input point is included, wherein said first output point is also identified using the coordinates (m,s). 5. The method of claim 4, wherein said first thread is included in a first thread block having a first thread block identifier, said first thread having a first thread identifier identifying a position of said first thread within said first thread block, wherein said first thread determines the coordinates (m,s) using said first thread block identifier and said first thread identifier. 6. The method of claim 2, wherein said first filtering uses filtering coefficients bound to a texture. 7. The method of claim 6, wherein said filtering coefficients are used in connection with filtering a portion of less than all mass to charge ratio values in said first plurality of scans. 8. The method of claim 1, wherein said filtering includes executing a second plurality of threads concurrently, wherein each of said second plurality of threads applies a second filter in a retention time dimension to at least one data point. 9. The method of claim 8, wherein said second filter is any of a smoothing filter and second derivative filter. 10. The method of claim 8, wherein said second filter uses a same set of filter coefficients for all data points to which the second filter is applied. 11. The method of claim 10, wherein the filter coefficients are stored in constant memory used by a graphics processing unit, said graphics processing unit and said constant memory being included in a separate device configured for used with a computer. 12. The method of claim 8, wherein said second plurality of threads is included in a two-dimensional grid of thread blocks, each of said thread blocks being a two-dimensional block of threads. 13. The method of claim 1, further comprising:
determining first thread block dimensions of a first block of threads configured for parallel execution and each thread in said first block configured to apply a filter in a mass to charge ratio dimension to at least one data point; determining second thread block dimensions of a second block of threads configured for parallel execution and each thread in said second block configured to apply a filter in a retention time dimension to at least one data point; determining third thread block dimensions, wherein each dimension of said third thread block is a least common multiple of corresponding ones of said each dimension of said first thread block and said second thread block; and selecting scan pack dimensions in accordance with said third block dimensions, wherein said scan pack dimensions indicate sizing with respect to a number of said scans of data and a number of mass to charge ratio values per scan, wherein said analyzing is performed on a first scan pack before performing said analyzing with respect to a second scan pack, said first scan pack including a first portion of said scans of data and having said scan pack dimensions, said second scan pack including a second portion of said scans of data and having said scan pack dimensions. 14. The method of claim 13, wherein said first scan pack includes said first plurality of scans, and the method further comprising:
reading, by executing code on a processing unit of a computer which executes instructions serially, said first scan pack; storing said first scan pack in a first memory of said computer; copying said first scan pack into a second memory of a device, said device including a graphics processing unit that performs parallel processing, wherein said second memory is configured for use by said graphics processing unit when performing parallel processing and wherein said first memory is not configured for use by said graphics processing unit; performing said first filtering by executing said plurality of threads in parallel on said graphics processor using said first scan pack to identify one or more peaks in said first scan pack; storing, by said graphics processing unit in said second memory, output data identifying said one or more peaks; and copying said output data from said second memory to said first memory. 15. The method of claim 1, wherein said detecting one or more peaks is performed by concurrently executing threads included in a two-dimensional grid of thread blocks, each of said thread blocks including a two-dimensional configuration of threads, wherein threads included in a same first thread block have access to data stored in a portion of memory shared by all threads in the first thread block, wherein each of said threads included in said two-dimensional grid determines whether at least one filtered output point included in said filtered output scans is a peak. 16. The method of claim 15, wherein each of said thread blocks has first dimensions selected in accordance with utilization of a processing unit which performs concurrent processing, a number of threads included in said thread block having said first dimensions, and an approximation of said first dimensions to a square. 17. The method of claim 15, wherein said one or more peaks identified by said detecting are identified with respect to retention time and mass to charge ratio dimensions. 18. The method of claim 17, wherein said plurality of dimensions includes an ion mobility dimension and the method includes identifying peaks with respect the ion mobility dimension. 19. The method of claim 18, wherein said analyzing includes identifying one or more properties for each of said one or more ion peaks identified and wherein, at least a first of said properties is determined by concurrently executing threads included in a grid of thread blocks, each of said threads determining said first property for at least one of peaks identified by said detecting. 20. The method of claim 1, wherein said method is performed in real-time while said scans are generated as a result of sample analysis by a mass spectrometer. 21. The method of claim 18, wherein said one or more peaks are a first set of peaks and said analyzing further comprising:
determining a scan pack size comprising a number of scans having different retention times; determining, for each peak in said first set, a data volume having dimensions in accordance with data used for filtering with respect to said each peak and an output volume having dimensions in accordance with said a starting and ending location of said each peak with respect to retention time and m/z dimensions and covering an ion mobility range; determining a buffer volume having each dimension thereof which is at least a same size as a largest corresponding dimension with respect to all data volumes for all peaks in said first set; determining a first portion of peaks of said first set which are included in a first scan pack of said scan pack size, said first scan pack including a partition of said scans; partitioning said first portion into one or more groups of peaks and, for each group, performing first processing, said first processing including:
reading, for each peak in said each group, first data from said first scan pack in accordance with the data volume for said each peak and storing the first data into a buffer having a size in accordance with said buffer volume;
filtering the first data for each peak in said each group, wherein said filtering the first data includes a second plurality of threads executing concurrently, wherein for said each peak, each of said second plurality of threads applies a filter and computes a single filtered output point for a corresponding data point in the buffer for said each peak if said corresponding data point is in included within appropriate ones of the output volume and the data volume for said each peak; and
identifying child peaks for said each group. 22. The method of claim 21, wherein, if said filter is applied in a retention time dimension, each of said second plurality of threads computes a single filtered output point for a corresponding data point in the buffer for said each peak if said corresponding data point is within the output volume with respect to the retention time axis and within the data volume with respect to the m/z and the ion mobility axes. 23. The method of claim 21, wherein, if said filter is applied in a retention time dimension, each of said second plurality of threads computes a single filtered output point for a corresponding data point in the buffer for said each peak if said corresponding data point is within the output volume with respect to the retention time and the m/z axes and within the data volume with respect to the ion mobility axis. 24. The method of claim 21, wherein, if said filter is applied in a retention time dimension, each of said second plurality of threads computes a single filtered output point for a corresponding data point in the buffer for said each peak if said corresponding data point is within the output volume with respect to the retention time, the m/z, and the ion mobility axes. 25. The method of claim 18, wherein said analyzing for a first peak further comprises:
applying a smoothing filter in the retention time dimension to first data stored in the first buffer to produce second data stored in a second buffer; applying a second derivative filter in the retention time dimension to the first data stored in the first buffer to produce third data stored in a third buffer; applying, after producing said second data and said third data, a smoothing filter in the mass to charge ratio dimension to the third data to produce fourth data stored in said first buffer; applying, after producing said fourth data, a smoothing filter in the ion mobility dimension to the fourth data to produce fifth data stored in said third buffer; applying, after producing said fifth data, a second derivative filter in the mass to charge ratio dimension to said second data to produce sixth data stored in the first buffer; applying, after producing said sixth data, a smoothing filter in the ion mobility dimension to said sixth data to produce seventh data which is combined with said fifth data to produce a first combined result stored in said third buffer; applying, after producing said first combined result, a smoothing filter in the mass to charge ratio dimension to the second data to produce eighth data stored in the first buffer; and applying, after producing said eighth data, a second derivative filter in the ion mobility dimension to the eighth data to produce ninth data which is combined with said first combined result to produce a second combined result stored in the third buffer. 26. The method of claim 21, wherein said filtering the first data for each peak includes applying a sequence of three filters, a first of the filters being applied with respect to a first dimension or first axis to the first data to produce a first output, a second of the filters being applied with respect to a second dimension or second axis to the first output to produce a second output, a third of the filters being applied with respect to a third dimension or third axis to the second output to produce a third output, 27. The method of claim 26, wherein said first output has a first size with respect to said first dimension which is less than a second size of the first data with respect to the first dimension, wherein said second output has a third size with respect to said second dimension which is less than fourth size of the first output with respect to the second dimension, and wherein said third output has a fourth size with respect to said third dimension which is less than fifth size of the second output with respect to the third dimension 28. A method for processing data from sample analysis comprising:
performing mass spectrometry and generating one or more spectra; and analyzing the one or more spectra to generate a peak list of one or more ion peaks identified in the one or more spectra, said analyzing including performing, in parallel, at least a first filtering step and a second filtering step. 29. The method of claim 28, wherein said analyzing includes filtering the one or more spectra and the first filtering step computes a first filtered output point and said second filtering step computes a second filtered output point. 30. The method of claim 29, wherein said filtering is performed in one of a plurality of dimensions, said plurality of dimensions including retention time, mass or m/z, and ion mobility. 31. A system that performs mass spectrometry comprising:
a parallel processing unit; and a computer readable medium comprising code stored thereon which, when executed, performs steps including:
receiving one or more spectra produced as a result of mass analyzing a sample; and
analyzing the one or more spectra to generate a peak list of one or more ion peaks identified in the one or more spectra, said analyzing including performing, in parallel using said parallel processing unit, at least a first filtering step and a second filtering step. 32. The system of claim 31, wherein said analyzing includes filtering the one or more spectra and the first filtering step computes a first filtered output point and said second filtering step computes a second filtered output point. 33. The system of claim 32, wherein said filtering performs filtering in one of a plurality of dimensions, said plurality of dimensions including retention time, mass or m/z, and ion mobility. 34. The system of claim 31, further comprising a processor which executes instructions serially, wherein said computer readable medium further includes code for:
performing preprocessing; obtaining said one or more spectra as input from a memory; performing peak detection to identify said one or more peaks; performing peak properties computation on said one or more peaks included in said peak list to generate peak property information; and writing said peak list and said peak property information to a memory; and
wherein said performing preprocessing, said obtaining, and said writing are performed by code executing in said processor and wherein said performing peak detection, said performing peak property computation are performed by code executing in the parallel processing unit. 35. The system of claim 34, wherein, in connection with performing said obtaining, said processor executes code that reads said one or more spectra, stores said one or more spectra in a first memory that is configured for access by said processor and is not configured for access by the parallel processing unit, and copies said one or more spectra from said first memory to a second memory included on a device comprising said parallel processing unit. 36. The system of claim 31, wherein said system output the peak list and stores the peak list to non-volatile memory, and wherein said one or more spectra are stored in volatile memory during said analyzing and said one or more spectra are not stored to non-volatile memory for output as a result of said analyzing. | 2,800 |
12,142 | 12,142 | 14,768,077 | 2,884 | A danger detector, for example a flame detector, includes an alarm housing with an alarm cover. The housing part of the alarm cover is permeable to heat radiation in the central infrared range. A non-contact, optical heat radiation sensor which is sensitive to the incoming heat radiation and optically oriented to the housing part is arranged in the alarm housing. A processing unit for further processing a sensor signal emitted by the heat radiation sensor is mounted downstream of the heat radiation sensor. The processing unit is designed to monitor the signal emitted by the sensor with respect to significant fluctuations or flicker frequencies for open flames and to determine, based on a direct component of the signal emitted by the sensor, a temperature value for the ambient temperature in the surroundings of the danger detector. The heat radiation sensor may be a thermopile or a bolometer. | 1. A danger detector, comprising:
an alarm housing with an alarm cover, wherein a housing part of the alarm cover is transparent for heat radiation in the mid-infrared range, wherein a non-contact heat radiation sensor that is optically aligned to the housing part and sensitive for the incident heat radiation is disposed in the alarm housing, wherein the heat radiation sensor comprises a processing unit and computer-readable instructions stored in non-transitory computer-readable media and executable by the processing unit to:
process a sensor signal output by the heat radiation sensor connected downstream from it,
based on the processing of the sensor signal:
monitor for an occurrence of significant fluctuations or flicker frequencies corresponding to an open fire, and
determine, based on a steady component of the sensor signal, a temperature value for an ambient temperature in an environment of the danger detector. 2. The danger detector of claim 1, wherein the alarm cover comprises:
a housing part permeable to heat radiation in the mid-infrared range, and an adjoining, remaining part embodied light-tight. 3. The danger detector of claim 1, wherein the housing part comprises a material that is permeable for light in the mid-infrared range. 4. The danger detector of claim 3, wherein heat radiation particles with a degree of emission for the heat radiation in the infrared range of at least 0.75 are introduced into the housing material of the housing part. 5. The danger detector of claim 3, wherein stray particles are introduced into the material of the housing part, the stray particles having a volume proportion and a size distribution sufficient to scatter the visible light and let a majority of the infrared light pass. 6. The danger detector of claim 1, wherein the housing part is located at a central position of the housing to thereby provide direction-independent acquisition of the ambient temperature. 7. The danger detector of claim 1, wherein the computer-readable instructions are further executable by the processing unit computationally derive the temperature value based on (a) the steady component of the sensor signal and (b) a stored value for a degree of emission of the housing part. 8. The danger detector of claim 7, wherein the heat radiation sensor and the processing unit are integrated in a single component in a non-contact temperature/flame sensor. 9. The danger detector of claim 1, wherein:
the heat radiation sensor has a heat radiation-sensitive sensor surface, and at least one of an optical lens transparent for light in the mid-infrared range or an optical waveguide transparent for light in the mid-infrared range is disposed between the sensor surface and the housing part. 10. The danger detector of claim 1, wherein the heat radiation sensor comprises a thermopile or a bolometer. 11. The danger detector of claim 1, wherein the computer-readable instructions are further executable by the processing unit is configured to output a first message in the event of detected significant fluctuations or flicker frequencies and to output a second message if the established temperature value for the environment of the danger detector exceeds a predetermined temperature comparison value. 12. The danger detector of claim 1, wherein:
at least one of a gas sensor configured to detect fire flue gases or a measurement chamber with a stray light arrangement configured to detect smoke particles is provided in the danger detector, and wherein at least one entry opening for the fire flue gases or smoke particles is disposed in the housing. 13. A method for detection of open fire and for establishing a temperature value in the environment of a danger detector, the method comprising:
generate, by a non-contact heat radiation sensor, a sensor signal corresponding to a heat radiation entering a housing part transparent for heat radiation in the mid-infrared range, analyzing the sensor signal to detect fluctuations of flicker frequencies corresponding to an open fire, outputting a first message upon detecting fluctuations or flicker frequencies corresponding to an open fire, analyzing the sensor signal to determine, in a pyrotechnic manner, a temperature value for an ambient temperature in the environment of the danger detector, comparing the determined temperature value to a predetermined temperature comparison value, and outputting at least one of the determined temperature value or a second message in response to determining that the determined temperature value exceeds the predetermined temperature comparison value. 14. The method of claim 13, wherein the temperature value is determined computationally based at least on a degree of heat radiation in the mid-infrared range of at least one of a material or a surface property of the housing part. 15. The method of claim 13, wherein the temperature value is determined based on a ratio pyrometry. 16. The method of claim 13, wherein the sensor signal is generated by a thermopile or a bolometer. 17. The method of claim 13, wherein the generated sensor signal corresponds to a heat radiation entering a housing part transparent for heat radiation in a range from 3 μm to 20 μm. 18. The danger detector of claim 1, wherein the housing part comprises a material that is permeable for light in A range from 3 μm to 20 μm. 19. The danger detector of claim 3, wherein heat radiation particles with a degree of emission for the heat radiation in the infrared range of at least 0.9 are introduced into the housing material of the housing part. | A danger detector, for example a flame detector, includes an alarm housing with an alarm cover. The housing part of the alarm cover is permeable to heat radiation in the central infrared range. A non-contact, optical heat radiation sensor which is sensitive to the incoming heat radiation and optically oriented to the housing part is arranged in the alarm housing. A processing unit for further processing a sensor signal emitted by the heat radiation sensor is mounted downstream of the heat radiation sensor. The processing unit is designed to monitor the signal emitted by the sensor with respect to significant fluctuations or flicker frequencies for open flames and to determine, based on a direct component of the signal emitted by the sensor, a temperature value for the ambient temperature in the surroundings of the danger detector. The heat radiation sensor may be a thermopile or a bolometer.1. A danger detector, comprising:
an alarm housing with an alarm cover, wherein a housing part of the alarm cover is transparent for heat radiation in the mid-infrared range, wherein a non-contact heat radiation sensor that is optically aligned to the housing part and sensitive for the incident heat radiation is disposed in the alarm housing, wherein the heat radiation sensor comprises a processing unit and computer-readable instructions stored in non-transitory computer-readable media and executable by the processing unit to:
process a sensor signal output by the heat radiation sensor connected downstream from it,
based on the processing of the sensor signal:
monitor for an occurrence of significant fluctuations or flicker frequencies corresponding to an open fire, and
determine, based on a steady component of the sensor signal, a temperature value for an ambient temperature in an environment of the danger detector. 2. The danger detector of claim 1, wherein the alarm cover comprises:
a housing part permeable to heat radiation in the mid-infrared range, and an adjoining, remaining part embodied light-tight. 3. The danger detector of claim 1, wherein the housing part comprises a material that is permeable for light in the mid-infrared range. 4. The danger detector of claim 3, wherein heat radiation particles with a degree of emission for the heat radiation in the infrared range of at least 0.75 are introduced into the housing material of the housing part. 5. The danger detector of claim 3, wherein stray particles are introduced into the material of the housing part, the stray particles having a volume proportion and a size distribution sufficient to scatter the visible light and let a majority of the infrared light pass. 6. The danger detector of claim 1, wherein the housing part is located at a central position of the housing to thereby provide direction-independent acquisition of the ambient temperature. 7. The danger detector of claim 1, wherein the computer-readable instructions are further executable by the processing unit computationally derive the temperature value based on (a) the steady component of the sensor signal and (b) a stored value for a degree of emission of the housing part. 8. The danger detector of claim 7, wherein the heat radiation sensor and the processing unit are integrated in a single component in a non-contact temperature/flame sensor. 9. The danger detector of claim 1, wherein:
the heat radiation sensor has a heat radiation-sensitive sensor surface, and at least one of an optical lens transparent for light in the mid-infrared range or an optical waveguide transparent for light in the mid-infrared range is disposed between the sensor surface and the housing part. 10. The danger detector of claim 1, wherein the heat radiation sensor comprises a thermopile or a bolometer. 11. The danger detector of claim 1, wherein the computer-readable instructions are further executable by the processing unit is configured to output a first message in the event of detected significant fluctuations or flicker frequencies and to output a second message if the established temperature value for the environment of the danger detector exceeds a predetermined temperature comparison value. 12. The danger detector of claim 1, wherein:
at least one of a gas sensor configured to detect fire flue gases or a measurement chamber with a stray light arrangement configured to detect smoke particles is provided in the danger detector, and wherein at least one entry opening for the fire flue gases or smoke particles is disposed in the housing. 13. A method for detection of open fire and for establishing a temperature value in the environment of a danger detector, the method comprising:
generate, by a non-contact heat radiation sensor, a sensor signal corresponding to a heat radiation entering a housing part transparent for heat radiation in the mid-infrared range, analyzing the sensor signal to detect fluctuations of flicker frequencies corresponding to an open fire, outputting a first message upon detecting fluctuations or flicker frequencies corresponding to an open fire, analyzing the sensor signal to determine, in a pyrotechnic manner, a temperature value for an ambient temperature in the environment of the danger detector, comparing the determined temperature value to a predetermined temperature comparison value, and outputting at least one of the determined temperature value or a second message in response to determining that the determined temperature value exceeds the predetermined temperature comparison value. 14. The method of claim 13, wherein the temperature value is determined computationally based at least on a degree of heat radiation in the mid-infrared range of at least one of a material or a surface property of the housing part. 15. The method of claim 13, wherein the temperature value is determined based on a ratio pyrometry. 16. The method of claim 13, wherein the sensor signal is generated by a thermopile or a bolometer. 17. The method of claim 13, wherein the generated sensor signal corresponds to a heat radiation entering a housing part transparent for heat radiation in a range from 3 μm to 20 μm. 18. The danger detector of claim 1, wherein the housing part comprises a material that is permeable for light in A range from 3 μm to 20 μm. 19. The danger detector of claim 3, wherein heat radiation particles with a degree of emission for the heat radiation in the infrared range of at least 0.9 are introduced into the housing material of the housing part. | 2,800 |
12,143 | 12,143 | 14,865,795 | 2,853 | A system for identifying a corrosion risk during the design of a mechanical assembly, the system comprising: a design data unit for storing design data representing the mechanical assembly; a corrosion data unit for storing corrosion data; and a processor configured to: obtain design data from the design data unit; obtain, from the corrosion data unit, corrosion data relevant to the obtained design data; make a comparison of the obtained design data with the obtained corrosion data to identify a corrosion risk associated with the design; and provide, based on said comparison, an indication of the corrosion risk. | 1. A system for identifying a corrosion risk during the design of a mechanical assembly, the system comprising:
a design data unit for storing design data representing the mechanical assembly; a corrosion data unit for storing corrosion data; and a processor configured to: obtain design data from the design data unit; obtain, from the corrosion data unit, corrosion data relevant to the obtained design data; make a comparison of the obtained design data with the obtained corrosion data to identify a corrosion risk associated with the design; and provide, based on said comparison, an indication of the corrosion risk. 2. A system according to claim 1, wherein the obtained design data comprises at least one part of the mechanical assembly and at least one constituent material associated with the at least one part. 3. A system according to claim 2, wherein the at least one part of the mechanical assembly is in contact with at least one environment. 4. A system according to claim 3, wherein the processor is further configured to identify all parts in contact with each environment and all environments in contact with each part, using the obtained design data. 5. A system according to claim 3, wherein the indication of the corrosion risk comprises an indication of a general corrosion risk associated with the at least one material in contact with the at least one environment. 6. A system according to claim 3, wherein the obtained design data comprises at least one pair of parts, and wherein making a comparison comprises:
determining the existence of a galvanic circuit through the at least one pair of parts and the at least one environment that is a conductor of electricity; and determining a galvanic corrosion risk associated with the at least one pair of parts based on the galvanic potential difference between their respective constituent materials. 7. A system according to claim 6, wherein determining the existence of a galvanic circuit comprises:
determining whether the parts in said pair are made of distinct constituent materials; determining whether at least one of the parts in said pair has a greater galvanic potential than the other; and determining whether the at least one environment is in contact with both parts in said pair. 8. A system according to claim 6, wherein determining the existence of a galvanic circuit comprises determining a direct or indirect electrical connection between the parts in said pair. 9. A system according to claim 3, wherein the obtained design data comprises two or more parts, and wherein making a comparison comprises determining the existence of one or more electrical connections through the two or more parts and the at least one environment. 10. A system according to claim 9, wherein determining the existence of one or more electrical connections comprises determining a direct or indirect electrical connection. 11. A system according to claim 1, wherein obtaining design data from the design data unit comprises generating a design data output file. 12. A system according to claim 10, wherein making a comparison comprises mapping, information from the design data unit to the obtained corrosion data. 13. A system according to claim 1, the system further comprising a report generator. 14. A system according to claim 13, wherein the processor is further configured to assess the level of the indicated corrosion risk. 15. A system according to claim 13, wherein the report includes at least one of a galvanic risk, a general corrosion risk, and a risk rating. 16. A system according to claim 13, wherein the obtained corrosion data comprises at least one corrosion case and advice data, and wherein the report includes the at least one corrosion case and advice data. 17. A system according to claim 1, wherein the obtained corrosion data comprises at least one of a material name, environmental durability level associated with a material-environment combination and a galvanic potential associated with a material. 18. A system according to claim 1, wherein, in use, the system forms a plug-in component in a CAD system. 19. A method of identifying a corrosion risk during the design of a mechanical assembly, the method comprising the steps of:
obtaining design data representing the mechanical assembly; obtaining corrosion data relevant to the obtained design data; making a comparison of the obtained design data with the obtained corrosion data to identify a corrosion risk associated with the design; and providing, based on said comparison, an indication of the corrosion risk. 20. A method according to claim 19, wherein the obtained design data comprises at least one part of the mechanical assembly and at least one constituent material associated with the at least one part. 21-34. (canceled) | A system for identifying a corrosion risk during the design of a mechanical assembly, the system comprising: a design data unit for storing design data representing the mechanical assembly; a corrosion data unit for storing corrosion data; and a processor configured to: obtain design data from the design data unit; obtain, from the corrosion data unit, corrosion data relevant to the obtained design data; make a comparison of the obtained design data with the obtained corrosion data to identify a corrosion risk associated with the design; and provide, based on said comparison, an indication of the corrosion risk.1. A system for identifying a corrosion risk during the design of a mechanical assembly, the system comprising:
a design data unit for storing design data representing the mechanical assembly; a corrosion data unit for storing corrosion data; and a processor configured to: obtain design data from the design data unit; obtain, from the corrosion data unit, corrosion data relevant to the obtained design data; make a comparison of the obtained design data with the obtained corrosion data to identify a corrosion risk associated with the design; and provide, based on said comparison, an indication of the corrosion risk. 2. A system according to claim 1, wherein the obtained design data comprises at least one part of the mechanical assembly and at least one constituent material associated with the at least one part. 3. A system according to claim 2, wherein the at least one part of the mechanical assembly is in contact with at least one environment. 4. A system according to claim 3, wherein the processor is further configured to identify all parts in contact with each environment and all environments in contact with each part, using the obtained design data. 5. A system according to claim 3, wherein the indication of the corrosion risk comprises an indication of a general corrosion risk associated with the at least one material in contact with the at least one environment. 6. A system according to claim 3, wherein the obtained design data comprises at least one pair of parts, and wherein making a comparison comprises:
determining the existence of a galvanic circuit through the at least one pair of parts and the at least one environment that is a conductor of electricity; and determining a galvanic corrosion risk associated with the at least one pair of parts based on the galvanic potential difference between their respective constituent materials. 7. A system according to claim 6, wherein determining the existence of a galvanic circuit comprises:
determining whether the parts in said pair are made of distinct constituent materials; determining whether at least one of the parts in said pair has a greater galvanic potential than the other; and determining whether the at least one environment is in contact with both parts in said pair. 8. A system according to claim 6, wherein determining the existence of a galvanic circuit comprises determining a direct or indirect electrical connection between the parts in said pair. 9. A system according to claim 3, wherein the obtained design data comprises two or more parts, and wherein making a comparison comprises determining the existence of one or more electrical connections through the two or more parts and the at least one environment. 10. A system according to claim 9, wherein determining the existence of one or more electrical connections comprises determining a direct or indirect electrical connection. 11. A system according to claim 1, wherein obtaining design data from the design data unit comprises generating a design data output file. 12. A system according to claim 10, wherein making a comparison comprises mapping, information from the design data unit to the obtained corrosion data. 13. A system according to claim 1, the system further comprising a report generator. 14. A system according to claim 13, wherein the processor is further configured to assess the level of the indicated corrosion risk. 15. A system according to claim 13, wherein the report includes at least one of a galvanic risk, a general corrosion risk, and a risk rating. 16. A system according to claim 13, wherein the obtained corrosion data comprises at least one corrosion case and advice data, and wherein the report includes the at least one corrosion case and advice data. 17. A system according to claim 1, wherein the obtained corrosion data comprises at least one of a material name, environmental durability level associated with a material-environment combination and a galvanic potential associated with a material. 18. A system according to claim 1, wherein, in use, the system forms a plug-in component in a CAD system. 19. A method of identifying a corrosion risk during the design of a mechanical assembly, the method comprising the steps of:
obtaining design data representing the mechanical assembly; obtaining corrosion data relevant to the obtained design data; making a comparison of the obtained design data with the obtained corrosion data to identify a corrosion risk associated with the design; and providing, based on said comparison, an indication of the corrosion risk. 20. A method according to claim 19, wherein the obtained design data comprises at least one part of the mechanical assembly and at least one constituent material associated with the at least one part. 21-34. (canceled) | 2,800 |
12,144 | 12,144 | 12,909,613 | 2,844 | A task light that includes a plurality of light emitting diodes (LED's) adapted for providing a variable intensity of emitted light; a light directing member for directing light from the LED's onto a work surface; a control logic, electrically connected to a light intensity selector, an ambient light sensor, and the plurality of LED's and wherein the control logic compares the intensity of ambient light in the area surrounding the work surface with the desired intensity of light to be provided at the work surface and adjusts the supply of electrical power to the LED's so that the total of the variable intensity of emitted light and the intensity of ambient light in the area surrounding the work surface is approximately equal to the desired intensity of light to be provided at the work surface. | 1. An LED task light comprising:
a plurality of light emitting diodes (LED's) mounted on at least one substrate, and adapted for providing a variable intensity of emitted light; a housing, adapted for receiving the at least one substrate; a light directing member retained in the housing, wherein said light directing member is adapted for directing light emitted by the LED's onto a work surface; a power supply, adapted to provide a supply of electrical power to the LED's; a light intensity selector, adapted to allow a user to input a desired intensity of light to be provided at the work surface; an ambient light sensor, adapted to determine an intensity of ambient light in the area surrounding the work surface; a control logic, electrically connected to the power supply, the light intensity selector, the ambient light sensor, and the plurality of LED's and wherein the control logic compares the intensity of ambient light in the area surrounding the work surface with the desired intensity of light to be provided at the work surface and adjusts the supply of electrical power to the LED's so that the total of the variable intensity of emitted light and the,intensity of ambient light in the area surrounding the work surface is approximately equal to the desired intensity of light to be provided at the work surface; an adjustable arm, having a first end and a second end and wherein the first end is attached to the housing; and a mounting member, connected to the second end of the adjustable arm. 2. The LED task light of claim 1 wherein the mounting member is a base. 3. The LED task light of claim 2 wherein the base further comprises at least one electrical outlet. 4. The LED task light of claim 1 wherein the housing is formed from a thermally conductive material and is adapted to dissipate heat generated by the plurality of LED's. 5. The LED task light of claim 1 wherein the mounting member is selected from the group consisting of a C-clamp, a through-bolt mount, and an adjustable slatwall bracket. 6. The LED task light of claim 1 wherein the light directing member is selected from the group consisting of a light-guide board, a lens, a reflector, a collimator, a window, a diffuser, or combinations thereof. 7. The LED task light of claim 1 wherein the task light further comprises an indicator adapted to indicate to a user that the task light is operating. 8. The LED task light of claim 1 wherein the control logic provides a nominal amount of electrical power to the LED's when it determines that the intensity of ambient light in the area surrounding the work surface is equal to or greater than the desired intensity of light to be provided at the work surface. 9. A task light comprising:
at least one light source, adapted for providing a variable intensity of emitted light; a housing adapted for receiving the at least one light source; a light directing member retained in the housing, wherein said light directing member is adapted for directing light emitted by the at least one light source onto a work surface; a power supply, adapted to provide a supply of electrical power to the at least one light source; a light intensity selector, adapted to allow a user to input a desired intensity of light to be provided at the work surface; an ambient light sensor, adapted to determine an intensity of ambient light in the area surrounding the work surface; a control logic, electrically connected to the power supply, the light intensity selector, the ambient light sensor, and the at least one light source and wherein the control logic compares the intensity of ambient light in the area surrounding the work surface with the desired intensity of light to be provided at the work surface and adjusts the supply of electrical power to the at least one light source so that the total of the variable intensity of emitted light and the intensity of ambient light in the area surrounding the work surface is approximately equal to the desired intensity of light to be provided at the work surface; an adjustable arm, having a first end and a second end and wherein the first end is attached to the housing; and a mounting member, connected to the second end of the adjustable arm. 10. The task light of claim 9 wherein the at least one light source is selected from the group consisting of an LED, an incandescent bulb, a fluorescent bulb and an organic LED. 11. The task light of claim 9 wherein the mounting member is selected from a group consisting of a C-clamp, a through-bolt mount, and an adjustable slatwall bracket. 12. The task light of claim 9 wherein the light directing member is selected from the group consisting of a light-guide board, a lens, a reflector, a collimator, a window, a diffuser, or combinations thereof. 13. The task light of claim 9 wherein the task light further comprises a an occupancy sensor adapted to detect the presence of a person in the area adjacent to the task light and to turn the light off when a person is not present in the area adjacent to the task light. 14. The task light of claim 9 wherein the control logic provides a nominal amount of electrical power to the at least one light source when it determines that the intensity of ambient light in the area surrounding the work surface is equal to or greater than the desired intensity of light to be provided at the work surface. 15. The task light of claim 9 wherein the task light further comprises an indicator adapted to indicate to a user that the task light is operating. 16. A task light comprising:
at least one light source, adapted for providing a variable intensity of emitted light; a housing adapted for receiving the at least one light source; a light directing member retained in the housing, wherein said light directing member is adapted for directing light emitted by the at least one light source onto a work surface; a power supply, adapted to provide a supply of electrical power to the at least one light source; a light intensity selector, adapted to allow a user to input a desired intensity of light to be provided at the work surface; an ambient light sensor, adapted to determine an intensity of ambient light in the area surrounding the work surface; a control logic, electrically connected to the power supply, the light intensity selector, the ambient light sensor, and the at least one light source and wherein the control logic compares the intensity of ambient light in the area surrounding the work surface with the desired intensity of light to be provided at the work surface and adjusts the supply of electrical power to the at least one light source so that the total of the variable intensity emitted light and the intensity of ambient light in the area surrounding the work surface is approximately equal to the desired intensity of light to be provided at the work surface. 17. The task light of claim 16 wherein the at least one light source is selected from the group consisting of an LED, an incandescent bulb, a fluorescent bulb and an organic LED. 18. The task light of claim 16 wherein the task light further comprises an occupancy sensor adapted to detect the presence of a person in the area adjacent to the task light and to turn the task light off when a person is not present in the area adjacent to the task light. 19. The task light of claim 16 wherein the light directing member is selected from the group consisting of a light-guide board, a lens, a reflector, a collimator, a window, a diffuser, or combinations thereof. 20. The task light of claim 16 wherein the control logic provides a nominal amount of electrical power to the at least one light source when it determines that the intensity of ambient light in the area surrounding the work surface is equal to or greater than the desired intensity of light to be provided at the work surface. 21. The task light of claim 16 wherein the task light further comprises an indicator adapted to indicate to a user that the task light is operating. 22. The task light of claim 16 wherein the housing is adapted for under-cabinet mounting. 23. A task light comprising:
at least one light source, adapted for providing a variable intensity of emitted light; a housing adapted for receiving the at least one light source; a light directing member retained in the housing, wherein said light directing member is adapted for directing light emitted by the at least one light source onto a work surface; a power supply, adapted to provide a supply of electrical power to the at least one light source; a light intensity selector, adapted to allow a user to input a desired intensity of light to be provided at the work surface; a work surface light sensor, adapted to determine an intensity of light impinging upon the work surface; and a control logic, electrically connected to the power supply, the light intensity selector, the work surface light sensor, and the at least one light source and wherein the control logic compares the intensity of light impinging upon the work surface with the desired intensity of light to be provided at the work surface and adjusts the supply of electrical power to the at least one light source so that the total of the variable intensity of emitted light and the intensity of light impinging on the work surface is approximately equal to the desired intensity of light to be provided at the work surface. 24. The task light of claim 23 wherein the at least one light source is selected from the group consisting of an LED, an incandescent bulb, a fluorescent bulb and an organic LED. 25. The task light of claim 23 wherein the light directing member is selected from the group consisting of a light-guide board, a lens, a reflector, a collimator, a window, a diffuser, or combinations thereof. 26. The task light of claim 23 wherein the control logic provides a nominal amount of electrical power to the at least one light source when it determines that the intensity of light impinging upon the work surface is equal to or greater than the desired intensity of light to be provided at the work surface. 27. The task light of claim 23 wherein the mounting member is selected from a group consisting of a C-clamp, a through-bolt mount, and an adjustable slatwall bracket. 28. The LED task light of claim 23 wherein the task light further comprises an indicator adapted to indicate to a user that the task light is operating. 29. The task light of claim 23 wherein the task light further comprises an occupancy sensor adapted to detect the presence of a person in the area adjacent to the task light and to turn the task light off when a person is not present in the area adjacent to the task light. 30. The task light of claim 23 wherein the task light further comprises an adjustable arm, having a first end and a second end and wherein the first end is attached to the housing and a mounting member, connected to the second end of the adjustable arm. | A task light that includes a plurality of light emitting diodes (LED's) adapted for providing a variable intensity of emitted light; a light directing member for directing light from the LED's onto a work surface; a control logic, electrically connected to a light intensity selector, an ambient light sensor, and the plurality of LED's and wherein the control logic compares the intensity of ambient light in the area surrounding the work surface with the desired intensity of light to be provided at the work surface and adjusts the supply of electrical power to the LED's so that the total of the variable intensity of emitted light and the intensity of ambient light in the area surrounding the work surface is approximately equal to the desired intensity of light to be provided at the work surface.1. An LED task light comprising:
a plurality of light emitting diodes (LED's) mounted on at least one substrate, and adapted for providing a variable intensity of emitted light; a housing, adapted for receiving the at least one substrate; a light directing member retained in the housing, wherein said light directing member is adapted for directing light emitted by the LED's onto a work surface; a power supply, adapted to provide a supply of electrical power to the LED's; a light intensity selector, adapted to allow a user to input a desired intensity of light to be provided at the work surface; an ambient light sensor, adapted to determine an intensity of ambient light in the area surrounding the work surface; a control logic, electrically connected to the power supply, the light intensity selector, the ambient light sensor, and the plurality of LED's and wherein the control logic compares the intensity of ambient light in the area surrounding the work surface with the desired intensity of light to be provided at the work surface and adjusts the supply of electrical power to the LED's so that the total of the variable intensity of emitted light and the,intensity of ambient light in the area surrounding the work surface is approximately equal to the desired intensity of light to be provided at the work surface; an adjustable arm, having a first end and a second end and wherein the first end is attached to the housing; and a mounting member, connected to the second end of the adjustable arm. 2. The LED task light of claim 1 wherein the mounting member is a base. 3. The LED task light of claim 2 wherein the base further comprises at least one electrical outlet. 4. The LED task light of claim 1 wherein the housing is formed from a thermally conductive material and is adapted to dissipate heat generated by the plurality of LED's. 5. The LED task light of claim 1 wherein the mounting member is selected from the group consisting of a C-clamp, a through-bolt mount, and an adjustable slatwall bracket. 6. The LED task light of claim 1 wherein the light directing member is selected from the group consisting of a light-guide board, a lens, a reflector, a collimator, a window, a diffuser, or combinations thereof. 7. The LED task light of claim 1 wherein the task light further comprises an indicator adapted to indicate to a user that the task light is operating. 8. The LED task light of claim 1 wherein the control logic provides a nominal amount of electrical power to the LED's when it determines that the intensity of ambient light in the area surrounding the work surface is equal to or greater than the desired intensity of light to be provided at the work surface. 9. A task light comprising:
at least one light source, adapted for providing a variable intensity of emitted light; a housing adapted for receiving the at least one light source; a light directing member retained in the housing, wherein said light directing member is adapted for directing light emitted by the at least one light source onto a work surface; a power supply, adapted to provide a supply of electrical power to the at least one light source; a light intensity selector, adapted to allow a user to input a desired intensity of light to be provided at the work surface; an ambient light sensor, adapted to determine an intensity of ambient light in the area surrounding the work surface; a control logic, electrically connected to the power supply, the light intensity selector, the ambient light sensor, and the at least one light source and wherein the control logic compares the intensity of ambient light in the area surrounding the work surface with the desired intensity of light to be provided at the work surface and adjusts the supply of electrical power to the at least one light source so that the total of the variable intensity of emitted light and the intensity of ambient light in the area surrounding the work surface is approximately equal to the desired intensity of light to be provided at the work surface; an adjustable arm, having a first end and a second end and wherein the first end is attached to the housing; and a mounting member, connected to the second end of the adjustable arm. 10. The task light of claim 9 wherein the at least one light source is selected from the group consisting of an LED, an incandescent bulb, a fluorescent bulb and an organic LED. 11. The task light of claim 9 wherein the mounting member is selected from a group consisting of a C-clamp, a through-bolt mount, and an adjustable slatwall bracket. 12. The task light of claim 9 wherein the light directing member is selected from the group consisting of a light-guide board, a lens, a reflector, a collimator, a window, a diffuser, or combinations thereof. 13. The task light of claim 9 wherein the task light further comprises a an occupancy sensor adapted to detect the presence of a person in the area adjacent to the task light and to turn the light off when a person is not present in the area adjacent to the task light. 14. The task light of claim 9 wherein the control logic provides a nominal amount of electrical power to the at least one light source when it determines that the intensity of ambient light in the area surrounding the work surface is equal to or greater than the desired intensity of light to be provided at the work surface. 15. The task light of claim 9 wherein the task light further comprises an indicator adapted to indicate to a user that the task light is operating. 16. A task light comprising:
at least one light source, adapted for providing a variable intensity of emitted light; a housing adapted for receiving the at least one light source; a light directing member retained in the housing, wherein said light directing member is adapted for directing light emitted by the at least one light source onto a work surface; a power supply, adapted to provide a supply of electrical power to the at least one light source; a light intensity selector, adapted to allow a user to input a desired intensity of light to be provided at the work surface; an ambient light sensor, adapted to determine an intensity of ambient light in the area surrounding the work surface; a control logic, electrically connected to the power supply, the light intensity selector, the ambient light sensor, and the at least one light source and wherein the control logic compares the intensity of ambient light in the area surrounding the work surface with the desired intensity of light to be provided at the work surface and adjusts the supply of electrical power to the at least one light source so that the total of the variable intensity emitted light and the intensity of ambient light in the area surrounding the work surface is approximately equal to the desired intensity of light to be provided at the work surface. 17. The task light of claim 16 wherein the at least one light source is selected from the group consisting of an LED, an incandescent bulb, a fluorescent bulb and an organic LED. 18. The task light of claim 16 wherein the task light further comprises an occupancy sensor adapted to detect the presence of a person in the area adjacent to the task light and to turn the task light off when a person is not present in the area adjacent to the task light. 19. The task light of claim 16 wherein the light directing member is selected from the group consisting of a light-guide board, a lens, a reflector, a collimator, a window, a diffuser, or combinations thereof. 20. The task light of claim 16 wherein the control logic provides a nominal amount of electrical power to the at least one light source when it determines that the intensity of ambient light in the area surrounding the work surface is equal to or greater than the desired intensity of light to be provided at the work surface. 21. The task light of claim 16 wherein the task light further comprises an indicator adapted to indicate to a user that the task light is operating. 22. The task light of claim 16 wherein the housing is adapted for under-cabinet mounting. 23. A task light comprising:
at least one light source, adapted for providing a variable intensity of emitted light; a housing adapted for receiving the at least one light source; a light directing member retained in the housing, wherein said light directing member is adapted for directing light emitted by the at least one light source onto a work surface; a power supply, adapted to provide a supply of electrical power to the at least one light source; a light intensity selector, adapted to allow a user to input a desired intensity of light to be provided at the work surface; a work surface light sensor, adapted to determine an intensity of light impinging upon the work surface; and a control logic, electrically connected to the power supply, the light intensity selector, the work surface light sensor, and the at least one light source and wherein the control logic compares the intensity of light impinging upon the work surface with the desired intensity of light to be provided at the work surface and adjusts the supply of electrical power to the at least one light source so that the total of the variable intensity of emitted light and the intensity of light impinging on the work surface is approximately equal to the desired intensity of light to be provided at the work surface. 24. The task light of claim 23 wherein the at least one light source is selected from the group consisting of an LED, an incandescent bulb, a fluorescent bulb and an organic LED. 25. The task light of claim 23 wherein the light directing member is selected from the group consisting of a light-guide board, a lens, a reflector, a collimator, a window, a diffuser, or combinations thereof. 26. The task light of claim 23 wherein the control logic provides a nominal amount of electrical power to the at least one light source when it determines that the intensity of light impinging upon the work surface is equal to or greater than the desired intensity of light to be provided at the work surface. 27. The task light of claim 23 wherein the mounting member is selected from a group consisting of a C-clamp, a through-bolt mount, and an adjustable slatwall bracket. 28. The LED task light of claim 23 wherein the task light further comprises an indicator adapted to indicate to a user that the task light is operating. 29. The task light of claim 23 wherein the task light further comprises an occupancy sensor adapted to detect the presence of a person in the area adjacent to the task light and to turn the task light off when a person is not present in the area adjacent to the task light. 30. The task light of claim 23 wherein the task light further comprises an adjustable arm, having a first end and a second end and wherein the first end is attached to the housing and a mounting member, connected to the second end of the adjustable arm. | 2,800 |
12,145 | 12,145 | 15,301,226 | 2,855 | A membrane-based sensor in one embodiment includes a membrane layer including an upper surface and a lower surface, a backside trench defined on one side by the lower surface, a central cavity defined on a first side by the upper surface, a cap layer positioned above the central cavity, and a first spacer extending from the upper surface to the cap layer and integrally formed with the cap layer, the first spacer defining a second side of the central cavity and an inner membrane portion of the membrane layer. | 1. A membrane-based sensor comprising:
a membrane layer including an upper surface and a lower surface; a backside trench defined on one side by the lower surface; a central cavity defined on a first side by the upper surface; a cap layer positioned above the central cavity; and a first spacer extending from the upper surface to the cap layer and integrally formed with the cap layer, the first spacer defining a second side of the central cavity and an inner membrane portion of the membrane layer. 2. The membrane-based sensor of claim 1, wherein an area of the upper surface surrounded by the first spacer is smaller than an area of the lower surface that defines the one side of the backside trench. 3. The membrane-based sensor of claim 1, further comprising:
a cap electrode defined in a portion of the cap layer directly above the central cavity. 4. The membrane-based sensor of claim 1, further comprising:
a peripheral cavity defined on a third side by the upper surface and defined on a fourth side by the first spacer; and a second spacer extending from the upper surface to the cap layer and integrally formed with the cap layer, the second spacer defining a fifth side of the peripheral cavity and an outer membrane portion of the membrane layer. 5. The membrane-based sensor of claim 4, wherein the peripheral cavity extends laterally beyond the backside trench. 6. The membrane-based sensor of claim 5, further comprising;
a first dielectric layer portion positioned between the cap layer and the membrane layer, the first dielectric layer portion surrounding the second spacer. 7. The membrane-based sensor of claim 5, further comprising;
a second dielectric layer portion positioned directly beneath the membrane layer, the second dielectric layer portion surrounding the backside trench. 8. The membrane-based sensor of claim 7, wherein:
the central cavity is sealed at a reference pressure. 9. A method of forming a membrane-based sensor comprising:
forming a central trench through a first dielectric layer to expose a first upper surface portion of a membrane layer; forming a first spacer as an etch stop within the central trench on the first upper surface portion; forming a cap layer integrally with the first spacer; etching a central cavity through the cap layer, a lateral edge of the central cavity defined by the first spacer as an etch stop; and forming a backside trench to expose a lower surface of the membrane layer. 10. The method of claim 9, wherein:
etching the central cavity includes exposing a first area of the upper surface; forming the backside trench includes exposing a second area of the lower surface; and the first area is less than the second area. 11. The method of claim 9, further comprising:
forming a cap electrode in a portion of the cap layer located inwardly of the central trench. 12. The method of claim 9, further comprising:
forming a peripheral trench through the first dielectric layer to expose a second upper surface portion of a membrane layer; forming a second spacer integrally with the cap layer as an etch stop within the peripheral trench on the second upper surface portion; and etching a peripheral cavity through the cap layer, a first lateral edge of the peripheral cavity defined by the first spacer as an etch stop and a second lateral edge of the peripheral cavity defined by the second spacer as an etch stop. 13. The method of claim 12, wherein forming the backside trench comprises:
forming the backside trench with a lateral extent that is less than a lateral extent of the peripheral cavity. 14. The method of claim 13, wherein forming a cap layer comprises:
forming the cap layer at least partially on an upper surface of the first dielectric layer. 15. The method of claim 14, wherein forming the backside trench comprises:
forming the backside trench through a second dielectric layer positioned directly beneath the membrane layer. 16. The method of claim 15, further comprising:
establishing a desired pressure within the central cavity; and sealing the central cavity after establishing the desired pressure. | A membrane-based sensor in one embodiment includes a membrane layer including an upper surface and a lower surface, a backside trench defined on one side by the lower surface, a central cavity defined on a first side by the upper surface, a cap layer positioned above the central cavity, and a first spacer extending from the upper surface to the cap layer and integrally formed with the cap layer, the first spacer defining a second side of the central cavity and an inner membrane portion of the membrane layer.1. A membrane-based sensor comprising:
a membrane layer including an upper surface and a lower surface; a backside trench defined on one side by the lower surface; a central cavity defined on a first side by the upper surface; a cap layer positioned above the central cavity; and a first spacer extending from the upper surface to the cap layer and integrally formed with the cap layer, the first spacer defining a second side of the central cavity and an inner membrane portion of the membrane layer. 2. The membrane-based sensor of claim 1, wherein an area of the upper surface surrounded by the first spacer is smaller than an area of the lower surface that defines the one side of the backside trench. 3. The membrane-based sensor of claim 1, further comprising:
a cap electrode defined in a portion of the cap layer directly above the central cavity. 4. The membrane-based sensor of claim 1, further comprising:
a peripheral cavity defined on a third side by the upper surface and defined on a fourth side by the first spacer; and a second spacer extending from the upper surface to the cap layer and integrally formed with the cap layer, the second spacer defining a fifth side of the peripheral cavity and an outer membrane portion of the membrane layer. 5. The membrane-based sensor of claim 4, wherein the peripheral cavity extends laterally beyond the backside trench. 6. The membrane-based sensor of claim 5, further comprising;
a first dielectric layer portion positioned between the cap layer and the membrane layer, the first dielectric layer portion surrounding the second spacer. 7. The membrane-based sensor of claim 5, further comprising;
a second dielectric layer portion positioned directly beneath the membrane layer, the second dielectric layer portion surrounding the backside trench. 8. The membrane-based sensor of claim 7, wherein:
the central cavity is sealed at a reference pressure. 9. A method of forming a membrane-based sensor comprising:
forming a central trench through a first dielectric layer to expose a first upper surface portion of a membrane layer; forming a first spacer as an etch stop within the central trench on the first upper surface portion; forming a cap layer integrally with the first spacer; etching a central cavity through the cap layer, a lateral edge of the central cavity defined by the first spacer as an etch stop; and forming a backside trench to expose a lower surface of the membrane layer. 10. The method of claim 9, wherein:
etching the central cavity includes exposing a first area of the upper surface; forming the backside trench includes exposing a second area of the lower surface; and the first area is less than the second area. 11. The method of claim 9, further comprising:
forming a cap electrode in a portion of the cap layer located inwardly of the central trench. 12. The method of claim 9, further comprising:
forming a peripheral trench through the first dielectric layer to expose a second upper surface portion of a membrane layer; forming a second spacer integrally with the cap layer as an etch stop within the peripheral trench on the second upper surface portion; and etching a peripheral cavity through the cap layer, a first lateral edge of the peripheral cavity defined by the first spacer as an etch stop and a second lateral edge of the peripheral cavity defined by the second spacer as an etch stop. 13. The method of claim 12, wherein forming the backside trench comprises:
forming the backside trench with a lateral extent that is less than a lateral extent of the peripheral cavity. 14. The method of claim 13, wherein forming a cap layer comprises:
forming the cap layer at least partially on an upper surface of the first dielectric layer. 15. The method of claim 14, wherein forming the backside trench comprises:
forming the backside trench through a second dielectric layer positioned directly beneath the membrane layer. 16. The method of claim 15, further comprising:
establishing a desired pressure within the central cavity; and sealing the central cavity after establishing the desired pressure. | 2,800 |
12,146 | 12,146 | 14,194,533 | 2,846 | An induction motor controller is provided. The induction motor controller includes a first module that derives a commanded stator voltage vector, in a rotor flux reference frame, via a rotor flux regulator loop and a torque regulator loop, which process at least partially in the rotor flux reference frame. The induction motor controller includes a second module that processes the commanded stator voltage vector to produce AC (alternating current) power for an induction motor. | 1. An induction motor controller, comprising:
a first module that derives a commanded stator voltage vector, in a rotor flux reference frame, via a rotor flux regulator loop and a torque regulator loop; and a second module that processes the commanded stator voltage vector to produce AC (alternating current) power for an induction motor. 2. The induction motor controller of claim 1, wherein:
the second module transforms the commanded stator voltage vector from the rotor flux reference frame to a phase voltage reference frame, applying vector rotation according to a rotor flux angle; the second module generates pulse width modulation switching controls for a DC (direct current) to AC inverter from the commanded stator voltage vector as transformed to the phase voltage reference frame; and the second module generates three-phase AC power for the induction motor from the pulse width modulation switching controls. 3. The induction motor controller of claim 1, further comprising:
a third module that produces a torque, a rotor flux angle, a rotor flux, a stator current vector expressed in the rotor flux reference frame, and a rotor current vector expressed in the rotor flux reference frame, from a stator voltage vector expressed in a phase voltage reference frame, a stator current of at least two phases, and a rotational speed of a rotor of the induction motor. 4. The induction motor controller of claim 3, wherein:
the rotor flux is coupled from the third module to a flux regulator of the first module; the torque is coupled from the third module to a torque regulator of the first module; the rotor flux angle is coupled from the third module to the second module; the stator voltage vector expressed in the phase voltage reference frame is produced by the second module from the commanded stator voltage vector expressed in the rotor flux reference frame; and the stator current of at least two phases is provided by the second module. 5. The induction motor controller of claim 1, further comprising:
a third module that applies a rotor flux current model and a rotor flux voltage model to generate a rotor flux and a torque, wherein the rotor flux regulator loop includes the rotor flux as an input to the first module, and the torque regulator loop includes the torque as an input to the first module. 6. The induction motor controller of claim 5, further comprising:
a fourth module that generates a commanded torque and a commanded rotor flux, limiting the commanded torque to less than or equal to a maximum commanded torque and limiting the commanded rotor flux to greater than or equal to a minimum commanded rotor flux and less than or equal to a maximum commanded rotor flux, the commanded torque and the commanded rotor flux coupled as inputs to the first module. 7. The induction motor controller of claim 1, wherein:
the first module includes a torque regulator that processes a portion of the torque regulator loop and produces a projection of the commanded stator voltage vector onto a quadrature axis in the rotor flux reference frame; and the first module includes a rotor flux regulator that processes a portion of the rotor flux regulator loop and produces a projection of the commanded stator voltage vector onto a direct axis in the rotor flux reference frame. 8. An induction motor controller, comprising:
a torque regulator that processes in a rotor flux reference frame a commanded torque, a torque, a commanded rotor flux, and a rotational speed of a rotor of an induction motor, to produce a commanded stator voltage projected onto a quadrature axis in the rotor flux reference frame; a rotor flux regulator that processes in the rotor flux reference frame the commanded rotor flux and a rotor flux, to produce the commanded stator voltage projected onto a direct axis in the rotor flux reference frame; and a rotor flux reference frame to phase voltage reference frame vector rotation module that applies a rotor flux angle to transform the commanded stator voltage, as projected onto the direct axis and the quadrature axis, from a first vector expressed in the rotor flux reference frame to a second vector expressed in the phase voltage reference frame. 9. The induction motor controller of claim 8, further comprising:
a flux and torque estimator that generates the rotor flux angle, the rotor flux, the torque, a rotor current vector expressed in the rotor flux reference frame, and a stator current vector expressed in the rotor flux reference frame, from a stator voltage vector expressed in the phase voltage reference frame, a stator current of at least two phases, and the rotational speed of the rotor; and the flux and torque estimator including a phase voltage reference frame to rotor flux reference frame vector rotation module that transforms current vectors from the phase voltage reference frame to the rotor flux reference frame. 10. The induction motor controller of claim 8, further comprising a flux and torque estimator that includes:
a stator phase current reference frame to phase voltage reference frame vector rotation module that transforms a stator current of at least two phases to a stator current vector expressed in the phase voltage reference frame; a rotor flux current model that generates a first rotor flux vector expressed in the phase voltage reference frame from the stator current vector expressed in the phase voltage reference frame and the rotational speed of the rotor; a rotor flux voltage model that generates a second rotor flux vector expressed in the phase voltage reference frame from a stator voltage vector expressed in the phase voltage reference frame, the stator current vector expressed in the phase voltage reference frame, and an estimation correction factor; an estimator regulator that generates the estimation correction factor from the first rotor flux vector expressed in the phase voltage reference frame and the second rotor flux vector expressed in the phase voltage reference frame; a rotor flux magnitude calculator that generates the rotor flux from the second rotor flux vector expressed in the phase voltage reference frame; a stator flux calculator that generates a stator flux vector expressed in the phase voltage reference frame from the second rotor flux vector expressed in the phase voltage reference frame and the stator current vector expressed in the phase voltage reference frame; a rotor current calculator that generates a rotor current vector expressed in the phase voltage reference frame from the first rotor flux vector expressed in the phase voltage reference frame and the stator flux vector expressed in the phase voltage reference frame; a torque calculator that generates the torque from the stator current vector expressed in the phase voltage reference frame and the stator flux vector expressed in the phase voltage reference frame; a rotor flux angle calculator that generates the rotor flux angle from the rotor flux vector expressed in the phase voltage reference frame; and a phase voltage reference frame to rotor flux reference frame vector rotation module that generates the rotor current vector expressed in the rotor flux reference frame and the stator current vector expressed in the rotor flux reference frame, from the rotor current vector expressed in the phase voltage reference frame, the stator current vector expressed in the phase voltage reference frame, and the rotor flux angle. 11. The induction motor controller of claim 10, wherein:
the estimator regulator includes a PI (proportional-integral) controller; the stator flux calculator includes a model of inductances for windings of the induction motor; the rotor flux reference frame to phase voltage reference frame vector rotation module performs a second transformation that is an inverse of a first transformation performed by the phase voltage reference frame to rotor flux reference frame vector rotation module; and each of the rotor flux current model, the rotor flux voltage model, the rotor flux magnitude calculator, the rotor current calculator, the stator flux calculator, the torque calculator and the rotor flux angle calculator is lookup-table-based or real-time-calculation-based. 12. The induction motor controller of claim 8, further comprising:
a space vector modulation module that generates pulse width modulation (PWM) switching controls, and generates a stator voltage vector expressed in the phase voltage reference frame, from the commanded stator voltage received as the second vector and a DC (direct current) voltage of a power source; and a DC to AC (alternating current) inverter that generates three-phase AC power for the induction motor from the PWM switching controls. 13. The induction motor controller of claim 8, further comprising:
a flux and torque limiter that generates a minimum commanded rotor flux, a maximum commanded rotor flux, and a maximum commanded torque, from a stator current vector expressed in the rotor flux reference frame, a rotor current vector expressed in the rotor flux reference frame, an inverter temperature, a motor temperature, and the rotational speed of the rotor. 14. The induction motor controller of claim 8, further comprising a flux and torque limiter that includes:
a rotor current limiter that generates a maximum rotor current from the rotational speed of the rotor, a rotor current vector expressed in the rotor flux reference frame, and a motor temperature; a field weakener that generates a maximum stator flux from the rotational speed of the rotor and a DC (direct current) voltage of a power source; a stator current limiter that generates a maximum stator current from the rotational speed of the rotor, a stator current vector expressed in the rotor flux reference frame, and an inverter temperature; a low rotor flux limiter that generates a minimum commanded rotor flux from the maximum rotor current and the rotational speed of the rotor; a high rotor flux limiter that generates a maximum commanded rotor flux from the maximum stator flux and the maximum stator current; a stator-based torque limiter that generates a maximum stator-based commanded torque from the maximum stator flux and the maximum stator current; a rotor-based torque limiter that generates a maximum rotor-based commanded torque from the maximum rotor current and the maximum commanded rotor flux; and a final torque limiter that generates a maximum commanded torque from the maximum rotor-based commanded torque and the maximum stator-based commanded torque; wherein each of the rotor current limiter, the field weakener, the stator current limiter, the low rotor flux limiter, the high rotor flux limiter, the stator-based torque limiter, and the rotor-based torque limiter is lookup-table-based or real-time-calculation-based. 15. The induction motor controller of claim 8, further comprising a flux and torque limiter that includes:
a rotor current limiter that decreases a maximum rotor current in response to an increased motor temperature; a field weakener that decreases a maximum stator flux in response to the rotational speed of the rotor exceeding a base speed and further decreases the maximum stator flux in response to a decreasing DC (direct current) voltage of a power source; a stator current limiter that decreases a maximum stator current in response to an increased inverter temperature; a low rotor flux limiter that sets a minimum commanded rotor flux consistent with readiness to accelerate the rotor; a high rotor flux limiter that sets a maximum commanded rotor flux based upon the maximum stator flux and the maximum stator current; a stator-based torque limiter that sets a maximum stator-based commanded torque based upon a product of the maximum stator flux and the maximum stator current; a rotor-based torque limiter that sets a maximum rotor-based commanded torque based upon a product of the maximum rotor current and the maximum commanded rotor flux; and a final torque limiter that sets a maximum commanded torque selected as a lesser of the maximum rotor-based commanded torque and the maximum stator-based commanded torque. 16. The induction motor controller of claim 8, further comprising:
a torque command generator that generates the commanded torque from a maximum commanded torque and an initial commanded torque, the maximum commanded torque applied to the initial commanded torque as a torque limit; and a rotor flux command generator that generates the commanded rotor flux from a minimum commanded rotor flux, a maximum commanded rotor flux, and the commanded torque, the minimum commanded rotor flux and the maximum commanded rotor flux applied to the commanded rotor flux as flux limits. 17. The induction motor controller of claim 8, wherein:
the torque regulator includes a proportional-integral (PI) controller having a difference between the commanded torque and the torque as an input; and the torque regulator includes a feedforward summation having as inputs an output of the PI controller and a product of the commanded rotor flux and the rotational speed of the rotor, the feedforward summation having as an output the commanded stator voltage projected onto the quadrature axis in the rotor flux reference frame. 18. The induction motor controller of claim 8, wherein:
the rotor flux regulator includes a proportional-integral-derivative (PID) controller having as inputs the commanded rotor flux and the rotor flux, and having as an output the commanded stator voltage projected onto the direct axis in the rotor flux reference frame. 19. A method of controlling an induction motor, comprising:
generating a stator voltage vector, in a rotor flux reference frame, the generating including,
generating a quadrature axis projection of a commanded stator voltage vector expressed in the rotor flux reference frame from a commanded torque, a torque, a commanded rotor flux, and a rotational speed of a rotor of the induction motor; and
generating a direct axis projection of the commanded stator voltage vector expressed in the rotor flux reference frame from the commanded rotor flux and a rotor flux, wherein the stator voltage vector, in the rotor flux reference frame, includes the direct axis projection of the commanded stator voltage vector and the quadrature axis projection of the commanded stator voltage vector;
transforming the stator voltage vector from the rotor flux reference frame to a phase voltage reference frame; and producing alternating current (AC) power for an induction motor, from the stator voltage vector of the phase voltage reference frame, wherein at least one step of the method is performed by a processor. 20. The method of claim 19, wherein generating the quadrature axis projection of the commanded stator voltage vector expressed in the rotor flux reference frame includes:
subtracting the torque from the commanded torque to form a torque error; adding a first term proportional to the torque error and a second term proportional to an integral of the torque error to form a PI (proportional-integral) controller output; multiplying the rotational speed of the rotor by the commanded rotor flux to form a feedforward quantity; and adding the feedforward quantity to the PI controller output to form the quadrature axis projection of the commanded stator voltage vector expressed in the rotor flux reference frame. 21. The method of claim 19, wherein generating the direct axis projection of the commanded stator voltage vector expressed in the rotor flux reference frame includes:
subtracting the rotor flux from the commanded rotor flux to form a flux error; and adding a first term proportional to the flux error, a second term proportional to an integral of the flux error, and a third term proportional to a derivative of the flux error to form the direct axis projection of the commanded stator voltage vector expressed in the rotor flux reference frame. | An induction motor controller is provided. The induction motor controller includes a first module that derives a commanded stator voltage vector, in a rotor flux reference frame, via a rotor flux regulator loop and a torque regulator loop, which process at least partially in the rotor flux reference frame. The induction motor controller includes a second module that processes the commanded stator voltage vector to produce AC (alternating current) power for an induction motor.1. An induction motor controller, comprising:
a first module that derives a commanded stator voltage vector, in a rotor flux reference frame, via a rotor flux regulator loop and a torque regulator loop; and a second module that processes the commanded stator voltage vector to produce AC (alternating current) power for an induction motor. 2. The induction motor controller of claim 1, wherein:
the second module transforms the commanded stator voltage vector from the rotor flux reference frame to a phase voltage reference frame, applying vector rotation according to a rotor flux angle; the second module generates pulse width modulation switching controls for a DC (direct current) to AC inverter from the commanded stator voltage vector as transformed to the phase voltage reference frame; and the second module generates three-phase AC power for the induction motor from the pulse width modulation switching controls. 3. The induction motor controller of claim 1, further comprising:
a third module that produces a torque, a rotor flux angle, a rotor flux, a stator current vector expressed in the rotor flux reference frame, and a rotor current vector expressed in the rotor flux reference frame, from a stator voltage vector expressed in a phase voltage reference frame, a stator current of at least two phases, and a rotational speed of a rotor of the induction motor. 4. The induction motor controller of claim 3, wherein:
the rotor flux is coupled from the third module to a flux regulator of the first module; the torque is coupled from the third module to a torque regulator of the first module; the rotor flux angle is coupled from the third module to the second module; the stator voltage vector expressed in the phase voltage reference frame is produced by the second module from the commanded stator voltage vector expressed in the rotor flux reference frame; and the stator current of at least two phases is provided by the second module. 5. The induction motor controller of claim 1, further comprising:
a third module that applies a rotor flux current model and a rotor flux voltage model to generate a rotor flux and a torque, wherein the rotor flux regulator loop includes the rotor flux as an input to the first module, and the torque regulator loop includes the torque as an input to the first module. 6. The induction motor controller of claim 5, further comprising:
a fourth module that generates a commanded torque and a commanded rotor flux, limiting the commanded torque to less than or equal to a maximum commanded torque and limiting the commanded rotor flux to greater than or equal to a minimum commanded rotor flux and less than or equal to a maximum commanded rotor flux, the commanded torque and the commanded rotor flux coupled as inputs to the first module. 7. The induction motor controller of claim 1, wherein:
the first module includes a torque regulator that processes a portion of the torque regulator loop and produces a projection of the commanded stator voltage vector onto a quadrature axis in the rotor flux reference frame; and the first module includes a rotor flux regulator that processes a portion of the rotor flux regulator loop and produces a projection of the commanded stator voltage vector onto a direct axis in the rotor flux reference frame. 8. An induction motor controller, comprising:
a torque regulator that processes in a rotor flux reference frame a commanded torque, a torque, a commanded rotor flux, and a rotational speed of a rotor of an induction motor, to produce a commanded stator voltage projected onto a quadrature axis in the rotor flux reference frame; a rotor flux regulator that processes in the rotor flux reference frame the commanded rotor flux and a rotor flux, to produce the commanded stator voltage projected onto a direct axis in the rotor flux reference frame; and a rotor flux reference frame to phase voltage reference frame vector rotation module that applies a rotor flux angle to transform the commanded stator voltage, as projected onto the direct axis and the quadrature axis, from a first vector expressed in the rotor flux reference frame to a second vector expressed in the phase voltage reference frame. 9. The induction motor controller of claim 8, further comprising:
a flux and torque estimator that generates the rotor flux angle, the rotor flux, the torque, a rotor current vector expressed in the rotor flux reference frame, and a stator current vector expressed in the rotor flux reference frame, from a stator voltage vector expressed in the phase voltage reference frame, a stator current of at least two phases, and the rotational speed of the rotor; and the flux and torque estimator including a phase voltage reference frame to rotor flux reference frame vector rotation module that transforms current vectors from the phase voltage reference frame to the rotor flux reference frame. 10. The induction motor controller of claim 8, further comprising a flux and torque estimator that includes:
a stator phase current reference frame to phase voltage reference frame vector rotation module that transforms a stator current of at least two phases to a stator current vector expressed in the phase voltage reference frame; a rotor flux current model that generates a first rotor flux vector expressed in the phase voltage reference frame from the stator current vector expressed in the phase voltage reference frame and the rotational speed of the rotor; a rotor flux voltage model that generates a second rotor flux vector expressed in the phase voltage reference frame from a stator voltage vector expressed in the phase voltage reference frame, the stator current vector expressed in the phase voltage reference frame, and an estimation correction factor; an estimator regulator that generates the estimation correction factor from the first rotor flux vector expressed in the phase voltage reference frame and the second rotor flux vector expressed in the phase voltage reference frame; a rotor flux magnitude calculator that generates the rotor flux from the second rotor flux vector expressed in the phase voltage reference frame; a stator flux calculator that generates a stator flux vector expressed in the phase voltage reference frame from the second rotor flux vector expressed in the phase voltage reference frame and the stator current vector expressed in the phase voltage reference frame; a rotor current calculator that generates a rotor current vector expressed in the phase voltage reference frame from the first rotor flux vector expressed in the phase voltage reference frame and the stator flux vector expressed in the phase voltage reference frame; a torque calculator that generates the torque from the stator current vector expressed in the phase voltage reference frame and the stator flux vector expressed in the phase voltage reference frame; a rotor flux angle calculator that generates the rotor flux angle from the rotor flux vector expressed in the phase voltage reference frame; and a phase voltage reference frame to rotor flux reference frame vector rotation module that generates the rotor current vector expressed in the rotor flux reference frame and the stator current vector expressed in the rotor flux reference frame, from the rotor current vector expressed in the phase voltage reference frame, the stator current vector expressed in the phase voltage reference frame, and the rotor flux angle. 11. The induction motor controller of claim 10, wherein:
the estimator regulator includes a PI (proportional-integral) controller; the stator flux calculator includes a model of inductances for windings of the induction motor; the rotor flux reference frame to phase voltage reference frame vector rotation module performs a second transformation that is an inverse of a first transformation performed by the phase voltage reference frame to rotor flux reference frame vector rotation module; and each of the rotor flux current model, the rotor flux voltage model, the rotor flux magnitude calculator, the rotor current calculator, the stator flux calculator, the torque calculator and the rotor flux angle calculator is lookup-table-based or real-time-calculation-based. 12. The induction motor controller of claim 8, further comprising:
a space vector modulation module that generates pulse width modulation (PWM) switching controls, and generates a stator voltage vector expressed in the phase voltage reference frame, from the commanded stator voltage received as the second vector and a DC (direct current) voltage of a power source; and a DC to AC (alternating current) inverter that generates three-phase AC power for the induction motor from the PWM switching controls. 13. The induction motor controller of claim 8, further comprising:
a flux and torque limiter that generates a minimum commanded rotor flux, a maximum commanded rotor flux, and a maximum commanded torque, from a stator current vector expressed in the rotor flux reference frame, a rotor current vector expressed in the rotor flux reference frame, an inverter temperature, a motor temperature, and the rotational speed of the rotor. 14. The induction motor controller of claim 8, further comprising a flux and torque limiter that includes:
a rotor current limiter that generates a maximum rotor current from the rotational speed of the rotor, a rotor current vector expressed in the rotor flux reference frame, and a motor temperature; a field weakener that generates a maximum stator flux from the rotational speed of the rotor and a DC (direct current) voltage of a power source; a stator current limiter that generates a maximum stator current from the rotational speed of the rotor, a stator current vector expressed in the rotor flux reference frame, and an inverter temperature; a low rotor flux limiter that generates a minimum commanded rotor flux from the maximum rotor current and the rotational speed of the rotor; a high rotor flux limiter that generates a maximum commanded rotor flux from the maximum stator flux and the maximum stator current; a stator-based torque limiter that generates a maximum stator-based commanded torque from the maximum stator flux and the maximum stator current; a rotor-based torque limiter that generates a maximum rotor-based commanded torque from the maximum rotor current and the maximum commanded rotor flux; and a final torque limiter that generates a maximum commanded torque from the maximum rotor-based commanded torque and the maximum stator-based commanded torque; wherein each of the rotor current limiter, the field weakener, the stator current limiter, the low rotor flux limiter, the high rotor flux limiter, the stator-based torque limiter, and the rotor-based torque limiter is lookup-table-based or real-time-calculation-based. 15. The induction motor controller of claim 8, further comprising a flux and torque limiter that includes:
a rotor current limiter that decreases a maximum rotor current in response to an increased motor temperature; a field weakener that decreases a maximum stator flux in response to the rotational speed of the rotor exceeding a base speed and further decreases the maximum stator flux in response to a decreasing DC (direct current) voltage of a power source; a stator current limiter that decreases a maximum stator current in response to an increased inverter temperature; a low rotor flux limiter that sets a minimum commanded rotor flux consistent with readiness to accelerate the rotor; a high rotor flux limiter that sets a maximum commanded rotor flux based upon the maximum stator flux and the maximum stator current; a stator-based torque limiter that sets a maximum stator-based commanded torque based upon a product of the maximum stator flux and the maximum stator current; a rotor-based torque limiter that sets a maximum rotor-based commanded torque based upon a product of the maximum rotor current and the maximum commanded rotor flux; and a final torque limiter that sets a maximum commanded torque selected as a lesser of the maximum rotor-based commanded torque and the maximum stator-based commanded torque. 16. The induction motor controller of claim 8, further comprising:
a torque command generator that generates the commanded torque from a maximum commanded torque and an initial commanded torque, the maximum commanded torque applied to the initial commanded torque as a torque limit; and a rotor flux command generator that generates the commanded rotor flux from a minimum commanded rotor flux, a maximum commanded rotor flux, and the commanded torque, the minimum commanded rotor flux and the maximum commanded rotor flux applied to the commanded rotor flux as flux limits. 17. The induction motor controller of claim 8, wherein:
the torque regulator includes a proportional-integral (PI) controller having a difference between the commanded torque and the torque as an input; and the torque regulator includes a feedforward summation having as inputs an output of the PI controller and a product of the commanded rotor flux and the rotational speed of the rotor, the feedforward summation having as an output the commanded stator voltage projected onto the quadrature axis in the rotor flux reference frame. 18. The induction motor controller of claim 8, wherein:
the rotor flux regulator includes a proportional-integral-derivative (PID) controller having as inputs the commanded rotor flux and the rotor flux, and having as an output the commanded stator voltage projected onto the direct axis in the rotor flux reference frame. 19. A method of controlling an induction motor, comprising:
generating a stator voltage vector, in a rotor flux reference frame, the generating including,
generating a quadrature axis projection of a commanded stator voltage vector expressed in the rotor flux reference frame from a commanded torque, a torque, a commanded rotor flux, and a rotational speed of a rotor of the induction motor; and
generating a direct axis projection of the commanded stator voltage vector expressed in the rotor flux reference frame from the commanded rotor flux and a rotor flux, wherein the stator voltage vector, in the rotor flux reference frame, includes the direct axis projection of the commanded stator voltage vector and the quadrature axis projection of the commanded stator voltage vector;
transforming the stator voltage vector from the rotor flux reference frame to a phase voltage reference frame; and producing alternating current (AC) power for an induction motor, from the stator voltage vector of the phase voltage reference frame, wherein at least one step of the method is performed by a processor. 20. The method of claim 19, wherein generating the quadrature axis projection of the commanded stator voltage vector expressed in the rotor flux reference frame includes:
subtracting the torque from the commanded torque to form a torque error; adding a first term proportional to the torque error and a second term proportional to an integral of the torque error to form a PI (proportional-integral) controller output; multiplying the rotational speed of the rotor by the commanded rotor flux to form a feedforward quantity; and adding the feedforward quantity to the PI controller output to form the quadrature axis projection of the commanded stator voltage vector expressed in the rotor flux reference frame. 21. The method of claim 19, wherein generating the direct axis projection of the commanded stator voltage vector expressed in the rotor flux reference frame includes:
subtracting the rotor flux from the commanded rotor flux to form a flux error; and adding a first term proportional to the flux error, a second term proportional to an integral of the flux error, and a third term proportional to a derivative of the flux error to form the direct axis projection of the commanded stator voltage vector expressed in the rotor flux reference frame. | 2,800 |
12,147 | 12,147 | 15,841,345 | 2,828 | An optoelectronic device includes a semiconductor substrate with a first set of epitaxial layers formed on an area of the substrate defining a lower distributed Bragg-reflector (DBR) stack. A second set of epitaxial layers formed over the first set defines a quantum well structure, and a third set of epitaxial layers, formed over the second set, defines an upper DBR stack. At least the third set of epitaxial layers is contained in a mesa having sides that are perpendicular to the epitaxial layers. A dielectric coating extends over the sides of at least a part of the mesa that contains the third set of epitaxial layers. Electrodes are coupled to the epitaxial layers so as to apply an excitation current to the quantum well structure. | 1. An optoelectronic device, comprising:
a semiconductor substrate; a first set of epitaxial layers formed on an area of the substrate defining a lower distributed Bragg-reflector (DBR) stack; a second set of epitaxial layers formed over the first set, defining a quantum well structure; a third set of epitaxial layers, formed over the second set, defining an upper DBR stack, wherein at least the third set of epitaxial layers is contained in a mesa having sides that are perpendicular to the epitaxial layers; a dielectric coating extending over the sides of at least a part of the mesa that contains the third set of epitaxial layers; and electrodes coupled to the epitaxial layers so as to apply an excitation current to the quantum well structure. 2. The optoelectronic device according to claim 1, wherein the dielectric coating does not extend over an upper surface of the mesa. 3. The optoelectronic device according to claim 1, comprising a confinement layer formed within the third set of epitaxial layers, the confinement layer comprising:
a central part comprising a semiconducting material; and a peripheral part surrounding the central part and comprising a dielectric material. 4. The optoelectronic device according to claim 3, wherein the dielectric coating extends from an upper surface of the mesa down to the confinement layer. 5. The optoelectronic device according to claim 3, wherein the semiconductor material comprises AlxGa1-xAs, wherein x does not exceed 0.92. 6. The optoelectronic device according to claim 3, wherein the thickness of the confinement layer exceeds 50 nm. 7. The optoelectronic device according to claim 3, wherein the refractive index of the dielectric material does not exceed 1.6. 8. The optoelectronic device according to claim 3, wherein the dielectric material comprises silicon dioxide (SiO2). 9. The optoelectronic device according to claim 3, wherein the peripheral part comprises a sealed cavity. 10. An optoelectronic device, comprising:
a semiconductor substrate; a first set of epitaxial layers formed on an area of the substrate defining a lower distributed Bragg-reflector (DBR) stack; a second set of epitaxial layers formed over the first set, defining a quantum well structure; a third set of epitaxial layers, formed over the second set, defining an upper DBR stack; a confinement layer formed within the third set of epitaxial layers, comprising:
a central part contained under the mesa and comprising a semiconducting material; and
a peripheral part surrounding the central part and comprising a dielectric material having a refractive index that does not exceed 1.6; and
electrodes coupled to the epitaxial layers so as to apply an excitation current to the quantum well structure. 11. The optoelectronic device according to claim 10, wherein the semiconductor material comprises AlxGa1-xAs, wherein x does not exceed 0.92. 12. The optoelectronic device according to claim 10, wherein the thickness of the confinement layer exceeds 50 nm. 13. The optoelectronic device according to claim 10, wherein the dielectric material comprises silicon dioxide (SiO2). 14. The optoelectronic device according to claim 10, wherein the peripheral part comprises a sealed cavity. 15. A method for manufacturing an optoelectronic device, the method comprising:
depositing a first set of epitaxial layers on an area of a semiconductor substrate to define a lower distributed Bragg-reflector (DBR) stack; depositing a second set of epitaxial layers over the first set, defining a quantum well structure; depositing a third set of epitaxial layers over the second set, defining an upper DBR stack, and including a confinement layer, comprising a semiconductor material, within the upper DBR stack; etching the third set of epitaxial layers to define a mesa having sides that are perpendicular to the epitaxial layers and extend from an upper surface of the upper DBR stack down to the confinement layer; coating the sides of the mesa with a dielectric coating; after coating the sides of the mesa, processing the confinement layer so as to convert a peripheral part of the confinement layer to a dielectric material, while leaving the semiconductor material in a central part of the confinement layer, surrounded by the peripheral part; and coupling electrodes to the epitaxial layers so as to apply an excitation current to the quantum well structure. 16. The method according to claim 15, wherein the semiconductor material comprises AlxGa1-xAs, wherein x does not exceed 0.92. 17. The method according to claim 15, wherein the thickness of the confinement layer exceeds 50 nm. 18. The method according to claim 15, wherein converting the peripheral part comprises:
etching the peripheral part so as to form a cavity under the mesa; and applying a conformal coating of a dielectric material to the cavity. 19. The method according to claim 18, wherein the dielectric material is silicon dioxide (SiO2). 20. The method according to claim 15, wherein converting the peripheral part comprises:
etching the peripheral part so as to form a cavity under the mesa; and applying a non-conformal coating of a dielectric material to the optoelectronic device so as to seal the entrance of the cavity with the dielectric material leaving the cavity filled with the gas. | An optoelectronic device includes a semiconductor substrate with a first set of epitaxial layers formed on an area of the substrate defining a lower distributed Bragg-reflector (DBR) stack. A second set of epitaxial layers formed over the first set defines a quantum well structure, and a third set of epitaxial layers, formed over the second set, defines an upper DBR stack. At least the third set of epitaxial layers is contained in a mesa having sides that are perpendicular to the epitaxial layers. A dielectric coating extends over the sides of at least a part of the mesa that contains the third set of epitaxial layers. Electrodes are coupled to the epitaxial layers so as to apply an excitation current to the quantum well structure.1. An optoelectronic device, comprising:
a semiconductor substrate; a first set of epitaxial layers formed on an area of the substrate defining a lower distributed Bragg-reflector (DBR) stack; a second set of epitaxial layers formed over the first set, defining a quantum well structure; a third set of epitaxial layers, formed over the second set, defining an upper DBR stack, wherein at least the third set of epitaxial layers is contained in a mesa having sides that are perpendicular to the epitaxial layers; a dielectric coating extending over the sides of at least a part of the mesa that contains the third set of epitaxial layers; and electrodes coupled to the epitaxial layers so as to apply an excitation current to the quantum well structure. 2. The optoelectronic device according to claim 1, wherein the dielectric coating does not extend over an upper surface of the mesa. 3. The optoelectronic device according to claim 1, comprising a confinement layer formed within the third set of epitaxial layers, the confinement layer comprising:
a central part comprising a semiconducting material; and a peripheral part surrounding the central part and comprising a dielectric material. 4. The optoelectronic device according to claim 3, wherein the dielectric coating extends from an upper surface of the mesa down to the confinement layer. 5. The optoelectronic device according to claim 3, wherein the semiconductor material comprises AlxGa1-xAs, wherein x does not exceed 0.92. 6. The optoelectronic device according to claim 3, wherein the thickness of the confinement layer exceeds 50 nm. 7. The optoelectronic device according to claim 3, wherein the refractive index of the dielectric material does not exceed 1.6. 8. The optoelectronic device according to claim 3, wherein the dielectric material comprises silicon dioxide (SiO2). 9. The optoelectronic device according to claim 3, wherein the peripheral part comprises a sealed cavity. 10. An optoelectronic device, comprising:
a semiconductor substrate; a first set of epitaxial layers formed on an area of the substrate defining a lower distributed Bragg-reflector (DBR) stack; a second set of epitaxial layers formed over the first set, defining a quantum well structure; a third set of epitaxial layers, formed over the second set, defining an upper DBR stack; a confinement layer formed within the third set of epitaxial layers, comprising:
a central part contained under the mesa and comprising a semiconducting material; and
a peripheral part surrounding the central part and comprising a dielectric material having a refractive index that does not exceed 1.6; and
electrodes coupled to the epitaxial layers so as to apply an excitation current to the quantum well structure. 11. The optoelectronic device according to claim 10, wherein the semiconductor material comprises AlxGa1-xAs, wherein x does not exceed 0.92. 12. The optoelectronic device according to claim 10, wherein the thickness of the confinement layer exceeds 50 nm. 13. The optoelectronic device according to claim 10, wherein the dielectric material comprises silicon dioxide (SiO2). 14. The optoelectronic device according to claim 10, wherein the peripheral part comprises a sealed cavity. 15. A method for manufacturing an optoelectronic device, the method comprising:
depositing a first set of epitaxial layers on an area of a semiconductor substrate to define a lower distributed Bragg-reflector (DBR) stack; depositing a second set of epitaxial layers over the first set, defining a quantum well structure; depositing a third set of epitaxial layers over the second set, defining an upper DBR stack, and including a confinement layer, comprising a semiconductor material, within the upper DBR stack; etching the third set of epitaxial layers to define a mesa having sides that are perpendicular to the epitaxial layers and extend from an upper surface of the upper DBR stack down to the confinement layer; coating the sides of the mesa with a dielectric coating; after coating the sides of the mesa, processing the confinement layer so as to convert a peripheral part of the confinement layer to a dielectric material, while leaving the semiconductor material in a central part of the confinement layer, surrounded by the peripheral part; and coupling electrodes to the epitaxial layers so as to apply an excitation current to the quantum well structure. 16. The method according to claim 15, wherein the semiconductor material comprises AlxGa1-xAs, wherein x does not exceed 0.92. 17. The method according to claim 15, wherein the thickness of the confinement layer exceeds 50 nm. 18. The method according to claim 15, wherein converting the peripheral part comprises:
etching the peripheral part so as to form a cavity under the mesa; and applying a conformal coating of a dielectric material to the cavity. 19. The method according to claim 18, wherein the dielectric material is silicon dioxide (SiO2). 20. The method according to claim 15, wherein converting the peripheral part comprises:
etching the peripheral part so as to form a cavity under the mesa; and applying a non-conformal coating of a dielectric material to the optoelectronic device so as to seal the entrance of the cavity with the dielectric material leaving the cavity filled with the gas. | 2,800 |
12,148 | 12,148 | 15,337,922 | 2,875 | An elliptical lens comprises a lens body having a proximal section and a distal section. The proximal section has at least one input surface for receiving light from a light source and the distal section has at least one output surface through which light exits the lens body. The proximal section further comprises a substantially elliptical peripheral surface receiving at least a portion of the light entering the lens body via the at least one input surface and directing at least some of the received light via total internal reflection to the distal section such that at least a portion of the light directed to the distal section exits the lens body through said at least one output surface. Optical assemblies having said elliptical lens may be embedded in medical devices such as endoscopes to provide efficient illumination. | 1. A lens, comprising:
a lens body disposed about an optical axis and comprising a proximal section having at least one input surface for receiving light from a light source and a distal section having at least a substantially flat output surface that is substantially orthogonal to said optical axis and through which light exits the lens body, said input surface comprising a convex central portion and a peripheral portion surrounding said central portion collectively forming a cavity for at least partially receiving said light source, wherein said proximal section further comprises: a substantially elliptical peripheral surface receiving at least a portion of the light entering the lens body via said peripheral portion of said at least one input surface and directing at least some of said received light via total internal reflection to said distal section such that at least a portion of the light directed to the distal section exits the lens body through said at least one output surface. 2. The lens of claim 1, wherein said peripheral elliptical surface is characterized by a proximal focal point and a distal focal point and is shaped such that said distal focal point is positioned outside of said distal section of the lens body. 3. The lens of claim 2, wherein said distal focal point is positioned at a distance in a range of about 4 mm to about 6 mm relative to said output surface. 4. The lens of claim 1, wherein said distal focal point is positioned inside said lens body. 5. The lens of claim 4, wherein said distal focal point is positioned at a distance in a range of about 4 mm to about 6 mm below said output surface. 6. The lens of claim 2, wherein said proximal focal point of said elliptical surface is positioned at or in proximity of said light source such that the elliptical surface transfers at least a portion of light emitted by said light source from said proximal focal point to said distal focal point. 7. The lens of claim 2, wherein said proximal focal point of the elliptical surface is disposed within said cavity. 8. The lens of claim 1, wherein said peripheral portion of the input surface is shaped such that at least about 80% of the light entering the lens body via said peripheral portion propagates to said peripheral surface of the lens body. 9. The lens of claim 1, wherein said convex portion is characterized by a positive optical power in a range of about 50 D to about 300 D. 10. The lens of claim 1, wherein at least a portion of the light entering the lens body via said convex portion propagates to said output surface. 11. The lens of claim 10, wherein said convex portion is configured such that the light entering said lens body via the convex portion propagates to said output surface without striking said peripheral surface. 12. The lens of claim 1, wherein said peripheral portion of the input surface comprises a proximal concave segment and distal convex segment. 13. The lens of claim 1, wherein said input surface is configured to capture at least about 80% of the light emitted by said light source. 14. The lens of claim 1, wherein said input surface is configured to capture at least about 90% of the light emitted by said light source. 15. The lens of claim 1, wherein said proximal section and said distal section are rotationally symmetric about said optical axis of said lens body. 16. The lens of claim 1, further comprising a collar at least partially surrounding said lens body. 17. The lens of claim 16, wherein said collar is disposed at a boundary between said proximal section and said distal section. 18. The lens of claim 1, wherein said proximal and distal section form a unitary structure. 19. The lens of claim 16, wherein said proximal and distal section and said collar form a unitary structure. 20. The lens of claim 16, wherein any of said lens body and collar is formed of a polymeric material. 21. The lens of claim 20, wherein said polymeric material is any of polycarbonate, polymethylmethacrylate (PMMA), polycarbonate and high density polyethylene. 22. The lens of claim 16, wherein any of said lens body and said collar is formed of any of glass and silicone. 23. An optical assembly, comprising
a lens having a lens body comprising a proximal section having at least one input surface for receiving light from a light source and a distal section having at least one output surface through which light exits the lens body, a light guide optically coupled to said output surface of the lens body for receiving at least a portion of the light exiting the lens, wherein said proximal section further comprises: a substantially elliptical peripheral surface receiving at least a portion of the light entering the lens body via said at least one input surface and directing at least some of said received light via total internal reflection to said distal section such that at least a portion of the light directed to the distal section exits the lens body through said at least one output surface. 24. The optical assembly of claim 23, wherein said light guide is attached to said output surface of the lens. 25. The optical assembly of claim 23, wherein said peripheral elliptical surface is characterized by a proximal focal point and a distal focal point and is shaped such that said distal focal point is positioned outside of said distal section of the lens body. 26. The optical assembly of claim 25, wherein said distal focal point is positioned at a distance in a range of about 4 mm to about 6 mm relative to said output surface. 27. The optical assembly of claim 25, wherein said proximal focal point of said elliptical surface is positioned substantially at or in proximity of said light source such that the elliptical surface transfers at least a portion of light emitted by said light source from said proximal focal point to said distal focal point. 28. The optical assembly of claim 25, wherein said at least one input surface comprises a central convex portion and a peripheral portion surrounding said central convex portion. 29. The optical assembly of claim 28, wherein said peripheral portion of the input surface is shaped such that at least a portion of the light entering the lens body via said peripheral portion propagates to said peripheral elliptical surface to be reflected thereby. 30. The optical assembly of claim 28, wherein said convex portion is characterized by a positive optical power in a range of about 50 D to about 300 D. 31. The optical assembly of claim 28, wherein said peripheral portion of the input surface comprises a proximal concave segment and distal convex segment. 32. The optical assembly of claim 23, wherein said input surface is configured to capture at least about 80% of the light emitted by said light source. 33. The optical assembly of claim 23, wherein said lens further comprises a flange encircling said lens body. 34. The optical assembly of claim 33, wherein said lens body and said flange are formed as a unitary structure. 35. A lens, comprising,
a lens body comprising: an input surface for receiving light from a light source, an output surface through which light exits the lens, and an elliptical peripheral surface for receiving at least a portion for the light entering the lens body via said input surface and directing said received light via total internal reflection to said output surface; a collar at least partially encircling the lens body, wherein said input surface comprises a central convex portion and a peripheral portion surrounding the central convex portion. 36. The lens of claim 35, wherein said elliptical surface is characterized by an input focus and output focus. 37. The lens of claim 36, wherein said input focus is positioned at or in proximity of said light source. 38. The lens of claim 36, wherein said output focus is positioned outside of the lens body. 39. The lens of claim 36, wherein said output focus is positioned within the lens body. 40. The lens of claim 36, wherein said input surface comprises a convex central portion and a peripheral portion surrounding said central portion. 41. An optical assembly, comprising
a lens having a lens body comprising an input surface for receiving light from a light source, an output surface through which the light exits the lens body, and an elliptical peripheral surface for receiving at least a portion for the light entering the lens body via said input surface and directing said received light via total internal reflection to said output surface a light guide optically coupled to said output surface of the lens body for receiving at least a portion of the light exiting the lens. 42. The optical assembly of claim 41, wherein said lens further comprises a collar at least partially encircling said lens body. | An elliptical lens comprises a lens body having a proximal section and a distal section. The proximal section has at least one input surface for receiving light from a light source and the distal section has at least one output surface through which light exits the lens body. The proximal section further comprises a substantially elliptical peripheral surface receiving at least a portion of the light entering the lens body via the at least one input surface and directing at least some of the received light via total internal reflection to the distal section such that at least a portion of the light directed to the distal section exits the lens body through said at least one output surface. Optical assemblies having said elliptical lens may be embedded in medical devices such as endoscopes to provide efficient illumination.1. A lens, comprising:
a lens body disposed about an optical axis and comprising a proximal section having at least one input surface for receiving light from a light source and a distal section having at least a substantially flat output surface that is substantially orthogonal to said optical axis and through which light exits the lens body, said input surface comprising a convex central portion and a peripheral portion surrounding said central portion collectively forming a cavity for at least partially receiving said light source, wherein said proximal section further comprises: a substantially elliptical peripheral surface receiving at least a portion of the light entering the lens body via said peripheral portion of said at least one input surface and directing at least some of said received light via total internal reflection to said distal section such that at least a portion of the light directed to the distal section exits the lens body through said at least one output surface. 2. The lens of claim 1, wherein said peripheral elliptical surface is characterized by a proximal focal point and a distal focal point and is shaped such that said distal focal point is positioned outside of said distal section of the lens body. 3. The lens of claim 2, wherein said distal focal point is positioned at a distance in a range of about 4 mm to about 6 mm relative to said output surface. 4. The lens of claim 1, wherein said distal focal point is positioned inside said lens body. 5. The lens of claim 4, wherein said distal focal point is positioned at a distance in a range of about 4 mm to about 6 mm below said output surface. 6. The lens of claim 2, wherein said proximal focal point of said elliptical surface is positioned at or in proximity of said light source such that the elliptical surface transfers at least a portion of light emitted by said light source from said proximal focal point to said distal focal point. 7. The lens of claim 2, wherein said proximal focal point of the elliptical surface is disposed within said cavity. 8. The lens of claim 1, wherein said peripheral portion of the input surface is shaped such that at least about 80% of the light entering the lens body via said peripheral portion propagates to said peripheral surface of the lens body. 9. The lens of claim 1, wherein said convex portion is characterized by a positive optical power in a range of about 50 D to about 300 D. 10. The lens of claim 1, wherein at least a portion of the light entering the lens body via said convex portion propagates to said output surface. 11. The lens of claim 10, wherein said convex portion is configured such that the light entering said lens body via the convex portion propagates to said output surface without striking said peripheral surface. 12. The lens of claim 1, wherein said peripheral portion of the input surface comprises a proximal concave segment and distal convex segment. 13. The lens of claim 1, wherein said input surface is configured to capture at least about 80% of the light emitted by said light source. 14. The lens of claim 1, wherein said input surface is configured to capture at least about 90% of the light emitted by said light source. 15. The lens of claim 1, wherein said proximal section and said distal section are rotationally symmetric about said optical axis of said lens body. 16. The lens of claim 1, further comprising a collar at least partially surrounding said lens body. 17. The lens of claim 16, wherein said collar is disposed at a boundary between said proximal section and said distal section. 18. The lens of claim 1, wherein said proximal and distal section form a unitary structure. 19. The lens of claim 16, wherein said proximal and distal section and said collar form a unitary structure. 20. The lens of claim 16, wherein any of said lens body and collar is formed of a polymeric material. 21. The lens of claim 20, wherein said polymeric material is any of polycarbonate, polymethylmethacrylate (PMMA), polycarbonate and high density polyethylene. 22. The lens of claim 16, wherein any of said lens body and said collar is formed of any of glass and silicone. 23. An optical assembly, comprising
a lens having a lens body comprising a proximal section having at least one input surface for receiving light from a light source and a distal section having at least one output surface through which light exits the lens body, a light guide optically coupled to said output surface of the lens body for receiving at least a portion of the light exiting the lens, wherein said proximal section further comprises: a substantially elliptical peripheral surface receiving at least a portion of the light entering the lens body via said at least one input surface and directing at least some of said received light via total internal reflection to said distal section such that at least a portion of the light directed to the distal section exits the lens body through said at least one output surface. 24. The optical assembly of claim 23, wherein said light guide is attached to said output surface of the lens. 25. The optical assembly of claim 23, wherein said peripheral elliptical surface is characterized by a proximal focal point and a distal focal point and is shaped such that said distal focal point is positioned outside of said distal section of the lens body. 26. The optical assembly of claim 25, wherein said distal focal point is positioned at a distance in a range of about 4 mm to about 6 mm relative to said output surface. 27. The optical assembly of claim 25, wherein said proximal focal point of said elliptical surface is positioned substantially at or in proximity of said light source such that the elliptical surface transfers at least a portion of light emitted by said light source from said proximal focal point to said distal focal point. 28. The optical assembly of claim 25, wherein said at least one input surface comprises a central convex portion and a peripheral portion surrounding said central convex portion. 29. The optical assembly of claim 28, wherein said peripheral portion of the input surface is shaped such that at least a portion of the light entering the lens body via said peripheral portion propagates to said peripheral elliptical surface to be reflected thereby. 30. The optical assembly of claim 28, wherein said convex portion is characterized by a positive optical power in a range of about 50 D to about 300 D. 31. The optical assembly of claim 28, wherein said peripheral portion of the input surface comprises a proximal concave segment and distal convex segment. 32. The optical assembly of claim 23, wherein said input surface is configured to capture at least about 80% of the light emitted by said light source. 33. The optical assembly of claim 23, wherein said lens further comprises a flange encircling said lens body. 34. The optical assembly of claim 33, wherein said lens body and said flange are formed as a unitary structure. 35. A lens, comprising,
a lens body comprising: an input surface for receiving light from a light source, an output surface through which light exits the lens, and an elliptical peripheral surface for receiving at least a portion for the light entering the lens body via said input surface and directing said received light via total internal reflection to said output surface; a collar at least partially encircling the lens body, wherein said input surface comprises a central convex portion and a peripheral portion surrounding the central convex portion. 36. The lens of claim 35, wherein said elliptical surface is characterized by an input focus and output focus. 37. The lens of claim 36, wherein said input focus is positioned at or in proximity of said light source. 38. The lens of claim 36, wherein said output focus is positioned outside of the lens body. 39. The lens of claim 36, wherein said output focus is positioned within the lens body. 40. The lens of claim 36, wherein said input surface comprises a convex central portion and a peripheral portion surrounding said central portion. 41. An optical assembly, comprising
a lens having a lens body comprising an input surface for receiving light from a light source, an output surface through which the light exits the lens body, and an elliptical peripheral surface for receiving at least a portion for the light entering the lens body via said input surface and directing said received light via total internal reflection to said output surface a light guide optically coupled to said output surface of the lens body for receiving at least a portion of the light exiting the lens. 42. The optical assembly of claim 41, wherein said lens further comprises a collar at least partially encircling said lens body. | 2,800 |
12,149 | 12,149 | 15,692,741 | 2,853 | An electromagnetic flowmeter assembly is provided. The assembly includes a magnetic flowmeter configured to couple to a process pipe at a coupling point and measure a flowrate of a flow of process fluid. The assembly includes a conductive polymer reference connection configured to contact the process fluid and provide an electrical connection to magnetic flowmeter electronics. | 1. An electromagnetic flowmeter assembly comprising:
a magnetic flowmeter configured to couple to a process pipe at a coupling point and measure a flowrate of a flow of process fluid; and a conductive polymer reference connection configured to contact the process fluid and provide an electrical connection to magnetic flowmeter electronics. 2. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection is configured to provide a fluidic seal between the process pipe and the magnetic flowmeter. 3. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection comprises a conductive polymer section molded into a magnetic flowmeter liner. 4. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection comprises a conductive polymer chemically-compatible with the process fluid. 5. The electromagnetic flowmeter assembly of claim 4, wherein the conductive polymer has a higher working temperature than a temperature of the process fluid. 6. The electromagnetic flowmeter assembly of claim 5, wherein the conductive polymer reference connection is configured to provide a low impedance electrical connection to the magnetic flowmeter electronics. 7. The electromagnetic flowmeter assembly of claim 6, wherein the conductive polymer of the conductive polymer reference connection comprises carbon black and perfluoroalkoxy. 8. The electromagnetic flowmeter assembly of claim 7, wherein the conductive polymer reference connection comprises 5% by weight of carbon black. 9. The electromagnetic flowmeter assembly of claim 1, wherein the coupling point comprises an area between a process flange of the process pipe and a flowtube flange of the magnetic flowmeter. 10. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection comprises a central aperture configured to reduce a line size between the process pipe and the magnetic flowmeter. 11. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection comprises a metal ring over-molded with a conductive polymer. 12. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection comprises a press-fitted metal ring with a conductive polymer. 13. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection comprises a plurality of radial apertures. 14. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection is configured to be molded into a variety of different shapes and sizes. 15. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection is configured to serve as a self-aligning aid to avoid disrupting the flow of process fluid. 16. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection comprises an electrode over-molded with a conductive polymer. 17. An electromagnetic flowmeter assembly comprising:
a magnetic flowmeter configured to couple to a process pipe at a coupling point and measure a flowrate of a flow of process fluid; and a plurality of conductive polymer reference connections configured to contact the process fluid and provide an electrical connection to magnetic flowmeter electronics. 18. The electromagnetic flowmeter assembly of claim 17, wherein the plurality of conductive polymer reference connections comprises a first conductive polymer reference connection configured to provide a fluidic seal between the magnetic flowmeter and the process pipe and a second conductive polymer reference connection disposed within a liner of the magnetic flowmeter. 19. A method of assembling a flowmeter assembly comprising:
providing a measurement device; providing a conductive polymer reference connection; and coupling the conductive polymer reference connection to the measurement device. 20. The method of claim 19, wherein the measurement device comprises a flowmeter and the conductive polymer reference connection comprises a conductive polymer reference connection configured to provide a fluidic seal between the measurement device and a process pipe. | An electromagnetic flowmeter assembly is provided. The assembly includes a magnetic flowmeter configured to couple to a process pipe at a coupling point and measure a flowrate of a flow of process fluid. The assembly includes a conductive polymer reference connection configured to contact the process fluid and provide an electrical connection to magnetic flowmeter electronics.1. An electromagnetic flowmeter assembly comprising:
a magnetic flowmeter configured to couple to a process pipe at a coupling point and measure a flowrate of a flow of process fluid; and a conductive polymer reference connection configured to contact the process fluid and provide an electrical connection to magnetic flowmeter electronics. 2. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection is configured to provide a fluidic seal between the process pipe and the magnetic flowmeter. 3. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection comprises a conductive polymer section molded into a magnetic flowmeter liner. 4. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection comprises a conductive polymer chemically-compatible with the process fluid. 5. The electromagnetic flowmeter assembly of claim 4, wherein the conductive polymer has a higher working temperature than a temperature of the process fluid. 6. The electromagnetic flowmeter assembly of claim 5, wherein the conductive polymer reference connection is configured to provide a low impedance electrical connection to the magnetic flowmeter electronics. 7. The electromagnetic flowmeter assembly of claim 6, wherein the conductive polymer of the conductive polymer reference connection comprises carbon black and perfluoroalkoxy. 8. The electromagnetic flowmeter assembly of claim 7, wherein the conductive polymer reference connection comprises 5% by weight of carbon black. 9. The electromagnetic flowmeter assembly of claim 1, wherein the coupling point comprises an area between a process flange of the process pipe and a flowtube flange of the magnetic flowmeter. 10. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection comprises a central aperture configured to reduce a line size between the process pipe and the magnetic flowmeter. 11. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection comprises a metal ring over-molded with a conductive polymer. 12. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection comprises a press-fitted metal ring with a conductive polymer. 13. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection comprises a plurality of radial apertures. 14. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection is configured to be molded into a variety of different shapes and sizes. 15. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection is configured to serve as a self-aligning aid to avoid disrupting the flow of process fluid. 16. The electromagnetic flowmeter assembly of claim 1, wherein the conductive polymer reference connection comprises an electrode over-molded with a conductive polymer. 17. An electromagnetic flowmeter assembly comprising:
a magnetic flowmeter configured to couple to a process pipe at a coupling point and measure a flowrate of a flow of process fluid; and a plurality of conductive polymer reference connections configured to contact the process fluid and provide an electrical connection to magnetic flowmeter electronics. 18. The electromagnetic flowmeter assembly of claim 17, wherein the plurality of conductive polymer reference connections comprises a first conductive polymer reference connection configured to provide a fluidic seal between the magnetic flowmeter and the process pipe and a second conductive polymer reference connection disposed within a liner of the magnetic flowmeter. 19. A method of assembling a flowmeter assembly comprising:
providing a measurement device; providing a conductive polymer reference connection; and coupling the conductive polymer reference connection to the measurement device. 20. The method of claim 19, wherein the measurement device comprises a flowmeter and the conductive polymer reference connection comprises a conductive polymer reference connection configured to provide a fluidic seal between the measurement device and a process pipe. | 2,800 |
12,150 | 12,150 | 15,990,046 | 2,856 | A system includes an inspection robot comprising a plurality of sensor sleds; a plurality of ultra-sonic (UT) sensors; a couplant chamber mounted to each of the plurality of sleds, each couplant chamber comprising: a cone, the cone comprising a cone tip portion at an inspection surface end of the cone; a sensor mounting end opposite the cone tip portion; a couplant entry fluidly coupled to the cone at a position between the cone tip portion and the sensor mounting end; and wherein each of the UT sensors is mounted to the sensor mounting end of one of the couplant chambers. | 1. A system, comprising:
an inspection robot comprising a plurality of sensor sleds; a plurality of ultra-sonic (UT) sensors; a couplant chamber mounted to each of the plurality of sleds, each couplant chamber comprising:
a cone, the cone comprising a cone tip portion at an inspection surface end of the cone;
a sensor mounting end opposite the cone tip portion;
a couplant entry fluidly coupled to the cone at a position between the cone tip portion and the sensor mounting end; and
wherein each of the UT sensors is mounted to the sensor mounting end of one of the couplant chambers. 2. The system of claim 1, wherein the couplant entry is positioned at a vertically upper side of the cone in an intended orientation of the inspection robot on the inspection surface. 3. The system of claim 1, wherein each of the plurality of sensor sleds comprises a bottom surface having a curvature matching a curvature of the inspection surface. 4. The system of claim 3, wherein the inspection robot further comprises a plurality of arms, wherein each of the plurality of sensor sleds is mounted on one of the plurality of arms, the inspection robot further comprising a biasing member providing a down force on each of the plurality of arms. 5. The system of claim 4, wherein the plurality of sensor sleds are horizontally distributed relative to the inspection surface at selected horizontal positions. 6. The system of claim 5, wherein the selected horizontal positions comprise an inspection distance between two horizontally adjacent sensors of the plurality of UT sensors that is not greater than a selected horizontal resolution. 7. A method, comprising:
mounting a couplant chamber to each one of a plurality of sensor sleds of an inspection robot; coupling an ultra-sonic (UT) sensor to a sensor mounting end of each of the couplant chambers; providing couplant to a couplant entry of each of the couplant chambers, thereby acoustically coupling each of the UT sensors to an inspection surface; and acoustically interrogating the inspection surface with the UT sensors. 8. The method of claim 7, further comprising attaching a couplant source to each couplant entry, and providing the couplant from the couplant source. 9. The method of claim 8, further comprising replacing one of the UT sensors, wherein the replacing is performed without detaching the couplant source for the couplant entry corresponding to the replaced sensor. 10. The method of claim 9, wherein the replacing is performed without unmounting the couplant chamber corresponding to the replaced sensor. 11. The method of claim 10, further comprising moving the inspection robot over the inspection surface during the acoustically interrogating, wherein the moving the inspection robot further comprises aligning each of the plurality of sensor sleds with a feature of the inspection surface. 12. The method of claim 11, wherein the moving further comprises traversing a surface anomaly of the inspection surface, wherein the traversing comprises engaging a sled ramp of one of the sleds with the surface anomaly. 13. The method of claim 11, wherein the aligning comprises at least one operation selected from the operations consisting of: providing a curvature to a bottom surface of the sensor sleds; providing a down force on each of the sensor sleds; and providing at least one pivotal degree of freedom to each of the sensor sleds. 14. A system, comprising:
an inspection robot comprising a plurality of sensor sleds; a plurality of ultra-sonic (UT) sensors each coupled to one of the plurality of sensor sleds; a means for acoustically coupling the plurality of UT sensors to an inspection surface; and a means for acoustically interrogating a horizontal inspection lane of the inspection surface. 15. The system of claim 14, further comprising a means for self-aligning the plurality of sensor sleds during the acoustically interrogating. 16. The system of claim 15, further comprising a means for replacing one of the UT sensors without disconnecting a couplant source from the sensor sled corresponding to the replaced sensor. 17. The system of claim 14, wherein the means for acoustically interrogating further comprises a means for acoustically interrogating the horizontal inspection lane at a selected horizontal resolution. 18. The system of claim 17, wherein the means for acoustically interrogating the horizontal inspection lane at the selected horizontal resolution further comprises a means for interrogating the horizontal inspection lane at the selected horizontal resolution in a single inspection pass of the inspection robot. 19. The system of claim 14, further comprising a means for adjusting horizontal positions of the plurality of sensor sleds. 20. The system of claim 14, further comprising a means for acoustically re-coupling one of the plurality of UT sensors to the inspection surface during the acoustically interrogating. | A system includes an inspection robot comprising a plurality of sensor sleds; a plurality of ultra-sonic (UT) sensors; a couplant chamber mounted to each of the plurality of sleds, each couplant chamber comprising: a cone, the cone comprising a cone tip portion at an inspection surface end of the cone; a sensor mounting end opposite the cone tip portion; a couplant entry fluidly coupled to the cone at a position between the cone tip portion and the sensor mounting end; and wherein each of the UT sensors is mounted to the sensor mounting end of one of the couplant chambers.1. A system, comprising:
an inspection robot comprising a plurality of sensor sleds; a plurality of ultra-sonic (UT) sensors; a couplant chamber mounted to each of the plurality of sleds, each couplant chamber comprising:
a cone, the cone comprising a cone tip portion at an inspection surface end of the cone;
a sensor mounting end opposite the cone tip portion;
a couplant entry fluidly coupled to the cone at a position between the cone tip portion and the sensor mounting end; and
wherein each of the UT sensors is mounted to the sensor mounting end of one of the couplant chambers. 2. The system of claim 1, wherein the couplant entry is positioned at a vertically upper side of the cone in an intended orientation of the inspection robot on the inspection surface. 3. The system of claim 1, wherein each of the plurality of sensor sleds comprises a bottom surface having a curvature matching a curvature of the inspection surface. 4. The system of claim 3, wherein the inspection robot further comprises a plurality of arms, wherein each of the plurality of sensor sleds is mounted on one of the plurality of arms, the inspection robot further comprising a biasing member providing a down force on each of the plurality of arms. 5. The system of claim 4, wherein the plurality of sensor sleds are horizontally distributed relative to the inspection surface at selected horizontal positions. 6. The system of claim 5, wherein the selected horizontal positions comprise an inspection distance between two horizontally adjacent sensors of the plurality of UT sensors that is not greater than a selected horizontal resolution. 7. A method, comprising:
mounting a couplant chamber to each one of a plurality of sensor sleds of an inspection robot; coupling an ultra-sonic (UT) sensor to a sensor mounting end of each of the couplant chambers; providing couplant to a couplant entry of each of the couplant chambers, thereby acoustically coupling each of the UT sensors to an inspection surface; and acoustically interrogating the inspection surface with the UT sensors. 8. The method of claim 7, further comprising attaching a couplant source to each couplant entry, and providing the couplant from the couplant source. 9. The method of claim 8, further comprising replacing one of the UT sensors, wherein the replacing is performed without detaching the couplant source for the couplant entry corresponding to the replaced sensor. 10. The method of claim 9, wherein the replacing is performed without unmounting the couplant chamber corresponding to the replaced sensor. 11. The method of claim 10, further comprising moving the inspection robot over the inspection surface during the acoustically interrogating, wherein the moving the inspection robot further comprises aligning each of the plurality of sensor sleds with a feature of the inspection surface. 12. The method of claim 11, wherein the moving further comprises traversing a surface anomaly of the inspection surface, wherein the traversing comprises engaging a sled ramp of one of the sleds with the surface anomaly. 13. The method of claim 11, wherein the aligning comprises at least one operation selected from the operations consisting of: providing a curvature to a bottom surface of the sensor sleds; providing a down force on each of the sensor sleds; and providing at least one pivotal degree of freedom to each of the sensor sleds. 14. A system, comprising:
an inspection robot comprising a plurality of sensor sleds; a plurality of ultra-sonic (UT) sensors each coupled to one of the plurality of sensor sleds; a means for acoustically coupling the plurality of UT sensors to an inspection surface; and a means for acoustically interrogating a horizontal inspection lane of the inspection surface. 15. The system of claim 14, further comprising a means for self-aligning the plurality of sensor sleds during the acoustically interrogating. 16. The system of claim 15, further comprising a means for replacing one of the UT sensors without disconnecting a couplant source from the sensor sled corresponding to the replaced sensor. 17. The system of claim 14, wherein the means for acoustically interrogating further comprises a means for acoustically interrogating the horizontal inspection lane at a selected horizontal resolution. 18. The system of claim 17, wherein the means for acoustically interrogating the horizontal inspection lane at the selected horizontal resolution further comprises a means for interrogating the horizontal inspection lane at the selected horizontal resolution in a single inspection pass of the inspection robot. 19. The system of claim 14, further comprising a means for adjusting horizontal positions of the plurality of sensor sleds. 20. The system of claim 14, further comprising a means for acoustically re-coupling one of the plurality of UT sensors to the inspection surface during the acoustically interrogating. | 2,800 |
12,151 | 12,151 | 16,379,801 | 2,847 | An electromagnetic shielding material includes multiple strands of an electrically conductive yarn that are arranged as a braided, knitted, or woven mesh. Each strand of the electrically conductive yarn comprises one or more electrically conductive filaments; each electrically conductive filament comprises a core of a first electrically conductive material surrounded by a sheath of a second electrically conductive material different from the first electrically conductive material. The first electrically conductive material exceeds the second electrically conductive material with respect to electrical conductivity, while the second electrically conductive material exceeds the first electrically conductive material with respect to one or more of tensile strength, corrosion resistance, or one or more other mechanical or chemical properties or characteristics. In many examples, the first electrically conductive material includes copper and the second electrically conductive material includes stainless steel. | 1. An electromagnetic shielding material comprising multiple strands of an electrically conductive yarn that are arranged as a braided, knitted, or woven mesh, wherein:
(a) each strand of the electrically conductive yarn comprises one or more electrically conductive filaments; (b) each electrically conductive filament comprises a core of a first electrically conductive material surrounded by a sheath of a second electrically conductive material different from the first electrically conductive material; (c) the first electrically conductive material exceeds the second electrically conductive material with respect to electrical conductivity; (d) the second electrically conductive material exceeds the first electrically conductive material with respect to one or both of tensile strength or corrosion resistance; (e) the braided, woven, or knitted mesh is arranged as a flexible tube; and (f) the flexible tube exhibits screening attenuation greater than about 30 dB for electrical signal frequencies above 500 MHz. 2. The electromagnetic shielding material of claim 1 wherein (g) the electrical conductivity of the first electrically conductive material is more than about ten times greater than the electrical conductivity of the second electrically conductive material, and wherein one or both:
(h) the tensile strength of the second electrically conductive material is more than about two times greater than the tensile strength of the first electrically conductive material; or
(i) the corrosion resistance of the second electrically conductive material is more than about two times greater than the corrosion resistance of the first electrically conductive material. 3. The electromagnetic shielding material of claim 1 wherein (g) the electrical conductivity of the first electrically conductive material is more than about ten times greater than the electrical conductivity of the second electrically conductive material, and (h) the corrosion resistance of the second electrically conductive material is more than about two times greater than the corrosion resistance of the first electrically conductive material. 4. The electromagnetic shielding material of claim 1 wherein the first electrically conductive material includes one or more of copper, silver, gold, aluminum, gallium, bismuth, suitable alloys or mixtures of any two or more of those materials, or conductive or super-conductive ceramic materials and the second electrically conductive material includes one or more of stainless steel, titanium, iridium, tungsten, niobium, molybdenum, tantalum, nickel, vanadium, palladium, platinum, rhodium, ruthenium, osmium, or suitable alloys or mixtures of any two or more of those materials. 5. The electromagnetic shielding material of claim 1 wherein the first electrically conductive material includes copper and the second electrically conductive material includes stainless steel. 6. An electromagnetic shielding material comprising multiple strands of an electrically conductive yarn that are arranged as a braided, knitted, or woven mesh, wherein:
(a) each strand of the electrically conductive yarn comprises one or more electrically conductive filaments; (b) each electrically conductive filament comprises a core that includes copper surrounded by a sheath that includes stainless steel; (c) the braided, woven, or knitted mesh is arranged as a flexible tube; and (d) the flexible tube exhibits screening attenuation greater than about 30 dB for electrical signal frequencies above 500 MHz. 7. The electromagnetic shielding material of claim 6 wherein each electrically conductive filament comprises drawn core and sheath. 8. The electromagnetic shielding material of claim 7 wherein the drawn core and sheath are annealed. 9. The electromagnetic shielding material of claim 6 wherein the sheath of each electrically conductive filament comprises material electroplated or electrodeposited on the core. 10. The electromagnetic shielding material of claim 6 wherein each electrically conductive filament is less than about 100. microns in diameter. 11. The electromagnetic shielding material of claim 6 wherein each electrically conductive filament is less than about 50. microns in diameter. 12. The electromagnetic shielding material of claim 6 wherein each electrically conductive sheath is less than about 10. microns thick. 13. The electromagnetic shielding material of claim 6 wherein each electrically conductive sheath is less than about 8 microns thick. 14. The electromagnetic shielding material of claim 6 wherein each strand of the electrically conductive yarn comprises only one electrically conductive filament. 15. The electromagnetic shielding material of claim 6 wherein each strand of the electrically conductive yarn comprises multiple electrically conductive filaments bundled together without twisting. 16. The electromagnetic shielding material of claim 6 wherein each strand of the electrically conductive yarn comprises multiple electrically conductive filaments twisted together. 17. The electromagnetic shielding material of claim 6 wherein each strand of the electrically conductive yarn includes from 2 to 100 electrically conductive filaments. 18. The electromagnetic shielding material of claim 6 wherein each strand of the electrically conductive yarn includes from 10 to 25 electrically conductive filaments. 19. (canceled) 20. The electromagnetic shielding material of claim 6 wherein the flexible tube exhibits a transfer impedance less than about 100. mΩ/m for electrical signal frequencies up to 100 MHz. 21. The electromagnetic shielding material of claim 6 wherein the flexible tube exhibits screening attenuation greater than about 40 dB for electrical signal frequencies above 500 MHz. 22. The electromagnetic shielding material of claim 6 wherein the flexible tube exhibits pull strength greater than about 100. pounds. 23. The electromagnetic shielding material of claim 6 wherein, after 96 or more hours of exposure to an aqueous NaCl mist during a salt fog test administered according to DO-160G Section 14 Category T or according to ASTM B117 standard, the flexible tube exhibits electrical resistance less than about 50. mΩ/m. 24. The electromagnetic shielding material of claim 6 wherein, after 1000 or more hours of exposure to an aqueous NaCl mist during a salt fog test administered according to DO-160G Section 14 Category T or according to ASTM B117 standard, the flexible tube exhibits electrical resistance less than about 50. mΩ/m. 25. The electromagnetic shielding material of claim 6 wherein, after 10,000 or more cycles of bending from 0° to 180° and back again around a 2.5 inch diameter mandrel, the flexible tube exhibits electrical resistance less than about 50. mΩ/m. 26. The electromagnetic shielding material of claim 6 wherein the flexible tube exhibits electrical resistance less than about 50. mΩ/m after ten or more temperature cycles wherein each cycle includes 30 minutes at 200° C., cooling from 200° C. to −65° C. in less than 1 minute, 30 minutes at −65° C., and heating from −65° C. to 200° C. in less than 1 minute. 27. The electromagnetic shielding material of claim 6 wherein the flexible tube exhibits electrical resistance less than about 50. mΩ/m after 1000 or more abrasion cycles wherein each cycle includes about 0.25 inches of reciprocating movement of the flexible tube pressed with a force of about 2.5 pounds against a sacrificial wire bundle. 28. (canceled) 29. An electrical cable comprising an outer electromagnetic shield and one or more inner electrical conductors within the electromagnetic shield, wherein the outer electromagnetic shield includes the electromagnetic shielding material of claim 6. 30. A method for making the electrical cable of claim 29 comprising braiding, weaving, or knitting the multiple strands of the electrically conductive yarn around the one or more inner electrical conductors to form the flexible tube around the one or more inner electrical conductors to form the electrical cable. 31. A method for making the electrical cable of claim 29 wherein the method comprises inserting the one or more inner electrical conductors into the flexible tube to form the electrical cable. 32. A method for making the electrical cable of claim 29 wherein: (a) the braided, woven, or knitted mesh is arranged as a flexible sheet; and (b) the method comprises wrapping the flexible sheet around the inner electrical conductors to form the flexible tube around the inner electrical conductors to form the electrical cable. 33. A method for making the electromagnetic shielding material of claim 6, the method comprising braiding, weaving, or knitting the multiple strands of the electrically conductive yarn to form a braided, woven, or knitted mesh arranged as the flexible tube. | An electromagnetic shielding material includes multiple strands of an electrically conductive yarn that are arranged as a braided, knitted, or woven mesh. Each strand of the electrically conductive yarn comprises one or more electrically conductive filaments; each electrically conductive filament comprises a core of a first electrically conductive material surrounded by a sheath of a second electrically conductive material different from the first electrically conductive material. The first electrically conductive material exceeds the second electrically conductive material with respect to electrical conductivity, while the second electrically conductive material exceeds the first electrically conductive material with respect to one or more of tensile strength, corrosion resistance, or one or more other mechanical or chemical properties or characteristics. In many examples, the first electrically conductive material includes copper and the second electrically conductive material includes stainless steel.1. An electromagnetic shielding material comprising multiple strands of an electrically conductive yarn that are arranged as a braided, knitted, or woven mesh, wherein:
(a) each strand of the electrically conductive yarn comprises one or more electrically conductive filaments; (b) each electrically conductive filament comprises a core of a first electrically conductive material surrounded by a sheath of a second electrically conductive material different from the first electrically conductive material; (c) the first electrically conductive material exceeds the second electrically conductive material with respect to electrical conductivity; (d) the second electrically conductive material exceeds the first electrically conductive material with respect to one or both of tensile strength or corrosion resistance; (e) the braided, woven, or knitted mesh is arranged as a flexible tube; and (f) the flexible tube exhibits screening attenuation greater than about 30 dB for electrical signal frequencies above 500 MHz. 2. The electromagnetic shielding material of claim 1 wherein (g) the electrical conductivity of the first electrically conductive material is more than about ten times greater than the electrical conductivity of the second electrically conductive material, and wherein one or both:
(h) the tensile strength of the second electrically conductive material is more than about two times greater than the tensile strength of the first electrically conductive material; or
(i) the corrosion resistance of the second electrically conductive material is more than about two times greater than the corrosion resistance of the first electrically conductive material. 3. The electromagnetic shielding material of claim 1 wherein (g) the electrical conductivity of the first electrically conductive material is more than about ten times greater than the electrical conductivity of the second electrically conductive material, and (h) the corrosion resistance of the second electrically conductive material is more than about two times greater than the corrosion resistance of the first electrically conductive material. 4. The electromagnetic shielding material of claim 1 wherein the first electrically conductive material includes one or more of copper, silver, gold, aluminum, gallium, bismuth, suitable alloys or mixtures of any two or more of those materials, or conductive or super-conductive ceramic materials and the second electrically conductive material includes one or more of stainless steel, titanium, iridium, tungsten, niobium, molybdenum, tantalum, nickel, vanadium, palladium, platinum, rhodium, ruthenium, osmium, or suitable alloys or mixtures of any two or more of those materials. 5. The electromagnetic shielding material of claim 1 wherein the first electrically conductive material includes copper and the second electrically conductive material includes stainless steel. 6. An electromagnetic shielding material comprising multiple strands of an electrically conductive yarn that are arranged as a braided, knitted, or woven mesh, wherein:
(a) each strand of the electrically conductive yarn comprises one or more electrically conductive filaments; (b) each electrically conductive filament comprises a core that includes copper surrounded by a sheath that includes stainless steel; (c) the braided, woven, or knitted mesh is arranged as a flexible tube; and (d) the flexible tube exhibits screening attenuation greater than about 30 dB for electrical signal frequencies above 500 MHz. 7. The electromagnetic shielding material of claim 6 wherein each electrically conductive filament comprises drawn core and sheath. 8. The electromagnetic shielding material of claim 7 wherein the drawn core and sheath are annealed. 9. The electromagnetic shielding material of claim 6 wherein the sheath of each electrically conductive filament comprises material electroplated or electrodeposited on the core. 10. The electromagnetic shielding material of claim 6 wherein each electrically conductive filament is less than about 100. microns in diameter. 11. The electromagnetic shielding material of claim 6 wherein each electrically conductive filament is less than about 50. microns in diameter. 12. The electromagnetic shielding material of claim 6 wherein each electrically conductive sheath is less than about 10. microns thick. 13. The electromagnetic shielding material of claim 6 wherein each electrically conductive sheath is less than about 8 microns thick. 14. The electromagnetic shielding material of claim 6 wherein each strand of the electrically conductive yarn comprises only one electrically conductive filament. 15. The electromagnetic shielding material of claim 6 wherein each strand of the electrically conductive yarn comprises multiple electrically conductive filaments bundled together without twisting. 16. The electromagnetic shielding material of claim 6 wherein each strand of the electrically conductive yarn comprises multiple electrically conductive filaments twisted together. 17. The electromagnetic shielding material of claim 6 wherein each strand of the electrically conductive yarn includes from 2 to 100 electrically conductive filaments. 18. The electromagnetic shielding material of claim 6 wherein each strand of the electrically conductive yarn includes from 10 to 25 electrically conductive filaments. 19. (canceled) 20. The electromagnetic shielding material of claim 6 wherein the flexible tube exhibits a transfer impedance less than about 100. mΩ/m for electrical signal frequencies up to 100 MHz. 21. The electromagnetic shielding material of claim 6 wherein the flexible tube exhibits screening attenuation greater than about 40 dB for electrical signal frequencies above 500 MHz. 22. The electromagnetic shielding material of claim 6 wherein the flexible tube exhibits pull strength greater than about 100. pounds. 23. The electromagnetic shielding material of claim 6 wherein, after 96 or more hours of exposure to an aqueous NaCl mist during a salt fog test administered according to DO-160G Section 14 Category T or according to ASTM B117 standard, the flexible tube exhibits electrical resistance less than about 50. mΩ/m. 24. The electromagnetic shielding material of claim 6 wherein, after 1000 or more hours of exposure to an aqueous NaCl mist during a salt fog test administered according to DO-160G Section 14 Category T or according to ASTM B117 standard, the flexible tube exhibits electrical resistance less than about 50. mΩ/m. 25. The electromagnetic shielding material of claim 6 wherein, after 10,000 or more cycles of bending from 0° to 180° and back again around a 2.5 inch diameter mandrel, the flexible tube exhibits electrical resistance less than about 50. mΩ/m. 26. The electromagnetic shielding material of claim 6 wherein the flexible tube exhibits electrical resistance less than about 50. mΩ/m after ten or more temperature cycles wherein each cycle includes 30 minutes at 200° C., cooling from 200° C. to −65° C. in less than 1 minute, 30 minutes at −65° C., and heating from −65° C. to 200° C. in less than 1 minute. 27. The electromagnetic shielding material of claim 6 wherein the flexible tube exhibits electrical resistance less than about 50. mΩ/m after 1000 or more abrasion cycles wherein each cycle includes about 0.25 inches of reciprocating movement of the flexible tube pressed with a force of about 2.5 pounds against a sacrificial wire bundle. 28. (canceled) 29. An electrical cable comprising an outer electromagnetic shield and one or more inner electrical conductors within the electromagnetic shield, wherein the outer electromagnetic shield includes the electromagnetic shielding material of claim 6. 30. A method for making the electrical cable of claim 29 comprising braiding, weaving, or knitting the multiple strands of the electrically conductive yarn around the one or more inner electrical conductors to form the flexible tube around the one or more inner electrical conductors to form the electrical cable. 31. A method for making the electrical cable of claim 29 wherein the method comprises inserting the one or more inner electrical conductors into the flexible tube to form the electrical cable. 32. A method for making the electrical cable of claim 29 wherein: (a) the braided, woven, or knitted mesh is arranged as a flexible sheet; and (b) the method comprises wrapping the flexible sheet around the inner electrical conductors to form the flexible tube around the inner electrical conductors to form the electrical cable. 33. A method for making the electromagnetic shielding material of claim 6, the method comprising braiding, weaving, or knitting the multiple strands of the electrically conductive yarn to form a braided, woven, or knitted mesh arranged as the flexible tube. | 2,800 |
12,152 | 12,152 | 15,410,116 | 2,847 | A ceramic wiring board that includes a ceramic insulator and a via-conductor. The ceramic insulator includes a crystalline constituent and an amorphous constituent. The via-conductor includes a metal and an oxide. The crystalline constituent and the oxide include at least one metal element in common. A tubular region having a thickness of 5 μm adjoins and surrounds the via-conductor and has a higher concentration of the metal element than the ceramic insulator. | 1. A ceramic wiring board comprising:
a ceramic insulator including a crystalline constituent and an amorphous constituent; a via-conductor formed in the ceramic insulator, the via-conductor including a metal and an oxide the crystalline constituent and the oxide including a metal element in common; and a tubular region adjoining and surrounding the via-conductor, the tubular region having a concentration of the metal element higher than that of the ceramic insulator. 2. The ceramic wiring board according to claim 1, wherein the tubular region has a thickness of 5 μm. 3. The ceramic wiring board according to claim 1, wherein an absolute value of a difference in a degree of basicity between the amorphous constituent and the oxide is 0.049 or less, a degree of basicity BMi-O of the oxide is represented by (1) and (2) as follows:
B
Mi
-
O
=
B
Mi
-
O
0
-
B
Si
-
O
0
B
Ca
-
O
0
-
B
Si
-
O
0
(
1
)
when the oxide includes a plurality of cationic constituents,
B
=
∑
i
n
i
B
Mi
-
O
where ni represents a compositional proportion of a cation Mi,
B
Mi
-
O
0
=
(
r
Mi
+
1.4
)
2
2
Z
Mi
(
2
)
where BMi-O0 is the oxygen-donating ability of MiO,
MiO represents an oxide of an element,
BSi—O0 is oxygen-donating ability of SiO2,
BCa—O0 is oxygen-donating ability of CaO,
rMi is a Pauling's ionic radius (A) of the cation Mi,
ZMi is a valence of the cation Mi, and the calculated BMi-O being rounded to four decimal places. 4. The ceramic wiring board according to claim 1, wherein the tubular region includes a crystalline constituent including the metal element. 5. The ceramic wiring board according to claim 4, wherein the metal element is Ti. 6. The ceramic wiring board according to claim 5, wherein the crystalline constituent including the metal element includes a fresnoite compound including Ba, Ti, and Si. 7. The ceramic wiring board according to claim 4, wherein the metal element is Al. 8. The ceramic wiring board according to claim 7, wherein the crystalline constituent including the metal element includes a celsian compound including Ba, Al, and Si. 9. The ceramic wiring board according to claim 1, wherein the via-conductor has a diameter of 100 μm or less. 10. The ceramic wiring board according to claim 1, wherein the via-conductor is exposed at a surface of the ceramic wiring board. 11. A method for producing a ceramic wiring board, the method comprising:
preparing ceramic green sheets including a raw-material powder; forming a via-hole in at least one of the green sheets so as to penetrate the green sheet; preparing a conductive paste, the conductive paste including a metal powder, an additive, and an organic vehicle, the additive including a metal element that is also included in the raw-material powder of the ceramic green sheets; filling the via-hole with the conductive paste; stacking the green sheets including the green sheet having the via-hole filled with the conductive paste on top of one another to form an unfired ceramic wiring board having an unfired ceramic insulator and an unfired via-conductor; and firing the unfired ceramic wiring board to (1) sinter the unfired ceramic insulator into a ceramic insulator including a crystalline constituent including the metal element and an amorphous constituent, (2) sinter the unfired via-conductor into a via-conductor including a metal and an oxide, and (3) diffuse the metal element in the amorphous constituent to create a tubular region adjoining and surrounding the via-conductor, the tubular region having a concentration of the metal element higher than that of the ceramic insulator. 12. The method for producing the ceramic wiring board according to claim 11, wherein the tubular region has a thickness of 5 μm. 13. The method for producing the ceramic wiring board according to claim 11, wherein the via-conductor has a diameter of 100 μm or less. 14. The method for producing the ceramic wiring board according to claim 11, wherein the raw-material powder includes a compound containing SiO2, and at least one selected from TiO2 and Al2O3, and Ba. 15. The method for producing the ceramic wiring board according to claim 11, wherein the additive is at least one selected from a TiO2 powder and an Al2O3 powder. 16. The method for producing the ceramic wiring board according to claim 15, wherein the TiO2 powder and the Al2O3 powder have a specific surface area of 10 m2/g or more. 17. The method for producing the ceramic wiring board according to claim 11, wherein the additive is at least one selected from a Ti-containing organic compound and an Al-containing organic compound. 18. The method for producing the ceramic wiring board according to claim 11, wherein the firing of the unfired ceramic wiring board includes a first substep of holding at a first temperature of T1° C. to T1+50° C. for 1 hour or more, and a second substep of holding at a second temperature greater than T1+50° C. for 1 hour or more, where T1 is a sintering-starting temperature of the unfired ceramic insulator. 19. The method for producing the ceramic wiring board according to claim 18, further comprising stacking a shrinkage-reduction green sheet on each principal plane of the unfired ceramic wiring board, the shrinkage-reduction green sheet including a shrinkage-reducing material that does not become sintered or shrink at T1+50° C. | A ceramic wiring board that includes a ceramic insulator and a via-conductor. The ceramic insulator includes a crystalline constituent and an amorphous constituent. The via-conductor includes a metal and an oxide. The crystalline constituent and the oxide include at least one metal element in common. A tubular region having a thickness of 5 μm adjoins and surrounds the via-conductor and has a higher concentration of the metal element than the ceramic insulator.1. A ceramic wiring board comprising:
a ceramic insulator including a crystalline constituent and an amorphous constituent; a via-conductor formed in the ceramic insulator, the via-conductor including a metal and an oxide the crystalline constituent and the oxide including a metal element in common; and a tubular region adjoining and surrounding the via-conductor, the tubular region having a concentration of the metal element higher than that of the ceramic insulator. 2. The ceramic wiring board according to claim 1, wherein the tubular region has a thickness of 5 μm. 3. The ceramic wiring board according to claim 1, wherein an absolute value of a difference in a degree of basicity between the amorphous constituent and the oxide is 0.049 or less, a degree of basicity BMi-O of the oxide is represented by (1) and (2) as follows:
B
Mi
-
O
=
B
Mi
-
O
0
-
B
Si
-
O
0
B
Ca
-
O
0
-
B
Si
-
O
0
(
1
)
when the oxide includes a plurality of cationic constituents,
B
=
∑
i
n
i
B
Mi
-
O
where ni represents a compositional proportion of a cation Mi,
B
Mi
-
O
0
=
(
r
Mi
+
1.4
)
2
2
Z
Mi
(
2
)
where BMi-O0 is the oxygen-donating ability of MiO,
MiO represents an oxide of an element,
BSi—O0 is oxygen-donating ability of SiO2,
BCa—O0 is oxygen-donating ability of CaO,
rMi is a Pauling's ionic radius (A) of the cation Mi,
ZMi is a valence of the cation Mi, and the calculated BMi-O being rounded to four decimal places. 4. The ceramic wiring board according to claim 1, wherein the tubular region includes a crystalline constituent including the metal element. 5. The ceramic wiring board according to claim 4, wherein the metal element is Ti. 6. The ceramic wiring board according to claim 5, wherein the crystalline constituent including the metal element includes a fresnoite compound including Ba, Ti, and Si. 7. The ceramic wiring board according to claim 4, wherein the metal element is Al. 8. The ceramic wiring board according to claim 7, wherein the crystalline constituent including the metal element includes a celsian compound including Ba, Al, and Si. 9. The ceramic wiring board according to claim 1, wherein the via-conductor has a diameter of 100 μm or less. 10. The ceramic wiring board according to claim 1, wherein the via-conductor is exposed at a surface of the ceramic wiring board. 11. A method for producing a ceramic wiring board, the method comprising:
preparing ceramic green sheets including a raw-material powder; forming a via-hole in at least one of the green sheets so as to penetrate the green sheet; preparing a conductive paste, the conductive paste including a metal powder, an additive, and an organic vehicle, the additive including a metal element that is also included in the raw-material powder of the ceramic green sheets; filling the via-hole with the conductive paste; stacking the green sheets including the green sheet having the via-hole filled with the conductive paste on top of one another to form an unfired ceramic wiring board having an unfired ceramic insulator and an unfired via-conductor; and firing the unfired ceramic wiring board to (1) sinter the unfired ceramic insulator into a ceramic insulator including a crystalline constituent including the metal element and an amorphous constituent, (2) sinter the unfired via-conductor into a via-conductor including a metal and an oxide, and (3) diffuse the metal element in the amorphous constituent to create a tubular region adjoining and surrounding the via-conductor, the tubular region having a concentration of the metal element higher than that of the ceramic insulator. 12. The method for producing the ceramic wiring board according to claim 11, wherein the tubular region has a thickness of 5 μm. 13. The method for producing the ceramic wiring board according to claim 11, wherein the via-conductor has a diameter of 100 μm or less. 14. The method for producing the ceramic wiring board according to claim 11, wherein the raw-material powder includes a compound containing SiO2, and at least one selected from TiO2 and Al2O3, and Ba. 15. The method for producing the ceramic wiring board according to claim 11, wherein the additive is at least one selected from a TiO2 powder and an Al2O3 powder. 16. The method for producing the ceramic wiring board according to claim 15, wherein the TiO2 powder and the Al2O3 powder have a specific surface area of 10 m2/g or more. 17. The method for producing the ceramic wiring board according to claim 11, wherein the additive is at least one selected from a Ti-containing organic compound and an Al-containing organic compound. 18. The method for producing the ceramic wiring board according to claim 11, wherein the firing of the unfired ceramic wiring board includes a first substep of holding at a first temperature of T1° C. to T1+50° C. for 1 hour or more, and a second substep of holding at a second temperature greater than T1+50° C. for 1 hour or more, where T1 is a sintering-starting temperature of the unfired ceramic insulator. 19. The method for producing the ceramic wiring board according to claim 18, further comprising stacking a shrinkage-reduction green sheet on each principal plane of the unfired ceramic wiring board, the shrinkage-reduction green sheet including a shrinkage-reducing material that does not become sintered or shrink at T1+50° C. | 2,800 |
12,153 | 12,153 | 15,998,162 | 2,883 | A Diamond Nano Resonator Semiconductor, This is an Technology Light years Ahead of the 21st Century. Diamond Sensors for your mobile Devices, such as a Cell Phone, Tablet, your Car, Buses, Commercial Airplane, Jets, Rockets, Satellites, Trains, Televisions, Radio, Diamond™ Smart Watch, Power Plants, Cell Phone Tower, everything will run on Synthetic Diamonds, Because nothing can transfer Heat and Conduct Electricity like Synthetic Diamonds, these Diamonds™ Coated Semiconductor runs on tiny Synthetic Nano Resonators in any size and shape, with Encryption Software in an Pseudonymous Format. All Figures will have this ability. And some will run on Anti Matter. | 1. A Diamond Nano Resonator Semiconductor Comprising:
A Diamond Coated Synthetic Diamond, and Sensor for Cars, Trucks, Trains, Diamonds Coated Smart Watch. Power Plants, cell phones tower, mother board circuits, commercial air planes, Jet planes, And Rockets, Satellites, cell phones, Tablets, three way radio, Data Centers, the commercial planes, and jets, and rockets will run on anti matter; the servers and drives will run on synthetic diamonds, Because there is nothing that transfer heat like Synthetic Diamonds with Encryption Software in a Pseudonymous Format, the diamonds can work any electronic device. 2. As in claim 1 The Device of claim 2 further comprising capable of Cruise Ships, Helicopters, all running on Synthetic Diamonds; insulin pumps, EKG, pace makers for the heart, any medical equipment, will have Encryption Software in a pseudonymous format. 3. A Electronic Kane as in claim 1 with wireless ear plugs with a camera and sensor to see when an oncoming car is near, or the light changes, the sensor can detect cars, the wireless earplugs will tell The blind person what to do, when walk or stop this Al Kane is for the Blind, Phone ready. 4. A Smart Television as in claim 1 with better picture from synthetic diamonds resonators with USB ports in the front and back, a user can a USB drive for steaming movies, wireless standard size, for Cell phones, MP3 Players, Tablets as well. 5. A Smart Watch as in claim 1 that is capable of working with airplanes, with a camera on it for detecting infrared to know where soldiers are at all times to stop friendly fire, a pilot can talk to the Unit at all times and will know where they are and their position, the Al helmet works with the watch. 6. A Space station as in claim 1 that will stay in space for a hundred years or more that will be harness By the Solar, Hydrogen, Helium, Methane gas, that runs on anti matter, like a space hotel. 7. A three mode Jet as in claim 1 first it take off like a normal plane from the ground, vertical or The traditional runway, the second mode it go to speed of supersonic speed, the third mode is Rocket with Mach 66 Speed it can go into Space to Mars and back thirteen times within a year How, with Anti Matter, and Synthetic Diamonds Resonators, that can transfer heat, and conduct electricity like Nothing ever heard of massive, robust power light year technology, the first in history Nano Technology with microscopic power, it will take us there, the airplane will armed with laser guns, it is stealth with plasma body and synthetic diamonds it can shoot ICBM capability synthetic diamond sensors harness by hydrogen, helium, and methane gas and solar panels. 8. A data center as in claim 1 that is solar, and runs on synthetic diamond Nano Resonators made in Any size and shape that can transfer heat, and conduct electricity faster and better than anything known to man, Synthetic Diamond Panels, as an cooling system shown in FIGS. 55A and 55B to keep the data room cool at all times, the servers and drives are Synthetic Diamond as well the data center will have 10,000 processing chips and 33,000 graphics processors, the system will run on synthetic diamonds this is a Super Computer. 9. All units as in claim 1 will run on Diamond Nano Resonators that are synthetic for electronic devices all from the diamonds the size of a single strand of human hair, that can power anything in space or earth, AI meal kit order from store to pick up or home delivery, view store list on phone, or tablet. 10. The first Al Car as in claim 1 with 14 camera's and with the only realistic place to speak is the steering wheel with microphone speakers on both sides, A television in the dash board that runs on Diamond Nano resonators, and Solar light ports, because the car can transfer heat and conduct electricity so fast it will run indefinitely, it never needs fueling because it is Electric Car the best it is made to run without fuel, and is Stand alone the user don't need a phone to talk or communicate With the Car, The Smart Car will have Encryption Software in a Pseudonymous format. 11. A wireless assistant first with a camera as in claim 1 with front and back facing camera's, capable Of watching Television, video conferencing, phone as well, music, taking pictures, foreign languages, Messaging, Radio, Al voice command, streaming movies, sports, sorting pictures, mobile the user can take it anywhere, solar panels, it runs on Diamond coated Nano resonators semiconductor ten microphones, three speakers armed with protection with Encryption Software in a Pseudonymous format to stop hackers. 12. A Solar cell phone tower as in claim 1 and a water fuel cell phone tower with a generator that's runs on a semiconductor of diamonds coated synthetic, that handles traffic data for electronic devices like cell phones, and mp3 players. 13. A Augmented pair of glasses as in claim 1 that streams movies, makes movies, take pictures by Al Voice command runs on a Diamond synthetic Nano resonator with two speakers on the side to talk into and Encryption Software in a Pseudonymous format phone calls made also. 14. A Smart washer and dryer as in claim 1 that will call the user when the clothes are washing and drying as well, and they are finished washing and drying the software will call the user cell phone, or tablet any mobile device that runs on a diamond coated Nano Resonators semi conductor. 15. A All Diamond Synthetic Diamond Wafer as in claim 1 sprinkle with small grains of synthetic diamonds under low pressure mixed with Methane Gas and Hydrogen, that can produced a Wafer That will make microchips for semiconductors; and an all Black Diamond known as Carbonado Wafer As well to make microchips as well, but this is a rare element, so most will Synthetic Diamond made. 16. A all Diamond set of Dentures as in claim 1 Made of Synthetic Diamond that is twice as hard As diamond found in the earth; FIG. 51 and Synthetic Diamond Bones, for knee replacement FIG. 52 and Doctors Scalpel FIG. 52A and Dental implants as well any Bone needed for the Body. 17. Crypto Currency as in claim 1 the user can have insurance for the same amount that is in the Bank example if you have a Billion Dollars in your account than you are insured for that amount; And Government Regulation is accepted; this is new software will not be one sided, in the past ii f the user has five hundred million in the bank the user is only insured for two hundred thousand dollars, or What the Government rate is at that time, the crypto currency ATM, the user can get coins back by Al on a Cell Phone, Tablet or any mobile device. 18. A Software Application as in claim 1 to stop hacking of Government Agency; and Department stores, Banks, Health Care Data on Digital Medical Equipment, Business Medical Records, Social Security Numbers; Hospital Records, any Private Records, all filed and Protected by Encryption Software in a Pseudonymous format; the Potential Hack, cannot get in the Stack; they Will never get a chance to see any Data, because no Data will be filed in Plain Text ever, a smart cap for pills tells what pill you are taking and how many to take the sensor will call your cell phone or tablet to let user know. 19. A DVD Catalog as in claim 1 will never by Physical buy movies and music that stay in your ownership once a user pays the movie studio, and the music company it will stay on your mobile Device, cell phone, tablet, and the Television can load the Software Application; the TV will have Encryption Software in a Pseudonymous format and each Television will have its own IP Address. 20. A voting system for voters to use a machine with Encryption Software, in a Pseudonymous format in any foreign language worldwide. 21. A Encryption Software in a Pseudonymous format, Stealth Submarine, Synthetic diamond body. 22. An AI Warp Drive Rocket as in claim 1 a smart watch to control the AI Plane that will have a warp drive, that is attachable and detachable in the front hood area of Plane, four Ft long and wide, Just say Warp drive and it will up to take the air craft into Hyper Space this is Mode Four, with a Photon force Shield to defend against asteroids, debris, comets, black holes, Gas, dust, with Synthetic Diamond Sensors; and a Gravity Drive to Produce Synthetic Gravity, the Sensors will let the Star Craft know when an Object is moving towards the Star Ship, AI also as well, will quickly notify the AI unmanned Space Craft is well equipped, man cannot handle Speeds up to 71,506,481,482,063 he can override the craft but that will not be needed, the Photon Shield produces anti gravity, Cameras all through out the Star Ship inside and Outside to view the Star Ship at all times, AI is very Vital to avoid objects the entire Star Ship will work Better with AI, the warp drive will harness Solar Energy as well, will run on Anti Matter also. 23. A pair of wireless ear plugs as in claim 1 for heads of state and President worldwide in any foreign language example the President of France has a wireless earplug in a meeting with the President of America when he speaks it will come out in English to the President of America, and likewise when the President of America speaks it will come out in French; there is no need for an interpreter just speak into the wireless ear plug. 24. A Software program as in claim 1 that allows users to pay their cell phone or mobile device bill or cable bill by AI, just sign up for the program. | A Diamond Nano Resonator Semiconductor, This is an Technology Light years Ahead of the 21st Century. Diamond Sensors for your mobile Devices, such as a Cell Phone, Tablet, your Car, Buses, Commercial Airplane, Jets, Rockets, Satellites, Trains, Televisions, Radio, Diamond™ Smart Watch, Power Plants, Cell Phone Tower, everything will run on Synthetic Diamonds, Because nothing can transfer Heat and Conduct Electricity like Synthetic Diamonds, these Diamonds™ Coated Semiconductor runs on tiny Synthetic Nano Resonators in any size and shape, with Encryption Software in an Pseudonymous Format. All Figures will have this ability. And some will run on Anti Matter.1. A Diamond Nano Resonator Semiconductor Comprising:
A Diamond Coated Synthetic Diamond, and Sensor for Cars, Trucks, Trains, Diamonds Coated Smart Watch. Power Plants, cell phones tower, mother board circuits, commercial air planes, Jet planes, And Rockets, Satellites, cell phones, Tablets, three way radio, Data Centers, the commercial planes, and jets, and rockets will run on anti matter; the servers and drives will run on synthetic diamonds, Because there is nothing that transfer heat like Synthetic Diamonds with Encryption Software in a Pseudonymous Format, the diamonds can work any electronic device. 2. As in claim 1 The Device of claim 2 further comprising capable of Cruise Ships, Helicopters, all running on Synthetic Diamonds; insulin pumps, EKG, pace makers for the heart, any medical equipment, will have Encryption Software in a pseudonymous format. 3. A Electronic Kane as in claim 1 with wireless ear plugs with a camera and sensor to see when an oncoming car is near, or the light changes, the sensor can detect cars, the wireless earplugs will tell The blind person what to do, when walk or stop this Al Kane is for the Blind, Phone ready. 4. A Smart Television as in claim 1 with better picture from synthetic diamonds resonators with USB ports in the front and back, a user can a USB drive for steaming movies, wireless standard size, for Cell phones, MP3 Players, Tablets as well. 5. A Smart Watch as in claim 1 that is capable of working with airplanes, with a camera on it for detecting infrared to know where soldiers are at all times to stop friendly fire, a pilot can talk to the Unit at all times and will know where they are and their position, the Al helmet works with the watch. 6. A Space station as in claim 1 that will stay in space for a hundred years or more that will be harness By the Solar, Hydrogen, Helium, Methane gas, that runs on anti matter, like a space hotel. 7. A three mode Jet as in claim 1 first it take off like a normal plane from the ground, vertical or The traditional runway, the second mode it go to speed of supersonic speed, the third mode is Rocket with Mach 66 Speed it can go into Space to Mars and back thirteen times within a year How, with Anti Matter, and Synthetic Diamonds Resonators, that can transfer heat, and conduct electricity like Nothing ever heard of massive, robust power light year technology, the first in history Nano Technology with microscopic power, it will take us there, the airplane will armed with laser guns, it is stealth with plasma body and synthetic diamonds it can shoot ICBM capability synthetic diamond sensors harness by hydrogen, helium, and methane gas and solar panels. 8. A data center as in claim 1 that is solar, and runs on synthetic diamond Nano Resonators made in Any size and shape that can transfer heat, and conduct electricity faster and better than anything known to man, Synthetic Diamond Panels, as an cooling system shown in FIGS. 55A and 55B to keep the data room cool at all times, the servers and drives are Synthetic Diamond as well the data center will have 10,000 processing chips and 33,000 graphics processors, the system will run on synthetic diamonds this is a Super Computer. 9. All units as in claim 1 will run on Diamond Nano Resonators that are synthetic for electronic devices all from the diamonds the size of a single strand of human hair, that can power anything in space or earth, AI meal kit order from store to pick up or home delivery, view store list on phone, or tablet. 10. The first Al Car as in claim 1 with 14 camera's and with the only realistic place to speak is the steering wheel with microphone speakers on both sides, A television in the dash board that runs on Diamond Nano resonators, and Solar light ports, because the car can transfer heat and conduct electricity so fast it will run indefinitely, it never needs fueling because it is Electric Car the best it is made to run without fuel, and is Stand alone the user don't need a phone to talk or communicate With the Car, The Smart Car will have Encryption Software in a Pseudonymous format. 11. A wireless assistant first with a camera as in claim 1 with front and back facing camera's, capable Of watching Television, video conferencing, phone as well, music, taking pictures, foreign languages, Messaging, Radio, Al voice command, streaming movies, sports, sorting pictures, mobile the user can take it anywhere, solar panels, it runs on Diamond coated Nano resonators semiconductor ten microphones, three speakers armed with protection with Encryption Software in a Pseudonymous format to stop hackers. 12. A Solar cell phone tower as in claim 1 and a water fuel cell phone tower with a generator that's runs on a semiconductor of diamonds coated synthetic, that handles traffic data for electronic devices like cell phones, and mp3 players. 13. A Augmented pair of glasses as in claim 1 that streams movies, makes movies, take pictures by Al Voice command runs on a Diamond synthetic Nano resonator with two speakers on the side to talk into and Encryption Software in a Pseudonymous format phone calls made also. 14. A Smart washer and dryer as in claim 1 that will call the user when the clothes are washing and drying as well, and they are finished washing and drying the software will call the user cell phone, or tablet any mobile device that runs on a diamond coated Nano Resonators semi conductor. 15. A All Diamond Synthetic Diamond Wafer as in claim 1 sprinkle with small grains of synthetic diamonds under low pressure mixed with Methane Gas and Hydrogen, that can produced a Wafer That will make microchips for semiconductors; and an all Black Diamond known as Carbonado Wafer As well to make microchips as well, but this is a rare element, so most will Synthetic Diamond made. 16. A all Diamond set of Dentures as in claim 1 Made of Synthetic Diamond that is twice as hard As diamond found in the earth; FIG. 51 and Synthetic Diamond Bones, for knee replacement FIG. 52 and Doctors Scalpel FIG. 52A and Dental implants as well any Bone needed for the Body. 17. Crypto Currency as in claim 1 the user can have insurance for the same amount that is in the Bank example if you have a Billion Dollars in your account than you are insured for that amount; And Government Regulation is accepted; this is new software will not be one sided, in the past ii f the user has five hundred million in the bank the user is only insured for two hundred thousand dollars, or What the Government rate is at that time, the crypto currency ATM, the user can get coins back by Al on a Cell Phone, Tablet or any mobile device. 18. A Software Application as in claim 1 to stop hacking of Government Agency; and Department stores, Banks, Health Care Data on Digital Medical Equipment, Business Medical Records, Social Security Numbers; Hospital Records, any Private Records, all filed and Protected by Encryption Software in a Pseudonymous format; the Potential Hack, cannot get in the Stack; they Will never get a chance to see any Data, because no Data will be filed in Plain Text ever, a smart cap for pills tells what pill you are taking and how many to take the sensor will call your cell phone or tablet to let user know. 19. A DVD Catalog as in claim 1 will never by Physical buy movies and music that stay in your ownership once a user pays the movie studio, and the music company it will stay on your mobile Device, cell phone, tablet, and the Television can load the Software Application; the TV will have Encryption Software in a Pseudonymous format and each Television will have its own IP Address. 20. A voting system for voters to use a machine with Encryption Software, in a Pseudonymous format in any foreign language worldwide. 21. A Encryption Software in a Pseudonymous format, Stealth Submarine, Synthetic diamond body. 22. An AI Warp Drive Rocket as in claim 1 a smart watch to control the AI Plane that will have a warp drive, that is attachable and detachable in the front hood area of Plane, four Ft long and wide, Just say Warp drive and it will up to take the air craft into Hyper Space this is Mode Four, with a Photon force Shield to defend against asteroids, debris, comets, black holes, Gas, dust, with Synthetic Diamond Sensors; and a Gravity Drive to Produce Synthetic Gravity, the Sensors will let the Star Craft know when an Object is moving towards the Star Ship, AI also as well, will quickly notify the AI unmanned Space Craft is well equipped, man cannot handle Speeds up to 71,506,481,482,063 he can override the craft but that will not be needed, the Photon Shield produces anti gravity, Cameras all through out the Star Ship inside and Outside to view the Star Ship at all times, AI is very Vital to avoid objects the entire Star Ship will work Better with AI, the warp drive will harness Solar Energy as well, will run on Anti Matter also. 23. A pair of wireless ear plugs as in claim 1 for heads of state and President worldwide in any foreign language example the President of France has a wireless earplug in a meeting with the President of America when he speaks it will come out in English to the President of America, and likewise when the President of America speaks it will come out in French; there is no need for an interpreter just speak into the wireless ear plug. 24. A Software program as in claim 1 that allows users to pay their cell phone or mobile device bill or cable bill by AI, just sign up for the program. | 2,800 |
12,154 | 12,154 | 16,116,408 | 2,838 | A system for a vehicle includes a converter configured to, responsive to a first signal from a first adaptor indicating a first plug type having a first electrical parameter configuration, output power to the adaptor according to the first electrical parameter configuration, and responsive to a second signal from a second adaptor indicating a second plug type having a second electrical parameter configuration, output power to the adaptor according to the second configuration. | 1. A vehicle comprising:
an electric machine; a traction battery configured to power the electric machine; and a converter configured to
responsive to a first signal from a first adaptor indicating a first plug type having a first electrical parameter configuration, output power from the traction battery to the first adaptor according to the first electrical parameter configuration, and
responsive to a second signal from a second adaptor indicating a second plug type having a second electrical parameter configuration, output power from the traction battery to the second adaptor according to the second configuration. 2. The vehicle of claim 1, wherein the first electrical parameter configuration and the second electrical parameter configuration include one of a pole, ground, voltage, and current different from one another. 3. The vehicle of claim 2, wherein each of the first and second configurations defines an operating range of an electric load powered via the plug type. 4. The vehicle of claim 1, wherein the first electrical parameter configuration and the second electrical parameter configuration include a pole, ground, and voltage that are same and current that is different. 5. (canceled) 6. The vehicle of claim 1, wherein the converter is further configured to issue a fault notification and interrupt the outputting of power responsive to a ground fault interrupt. 7. A system for a vehicle comprising:
a converter configured to, responsive to different signals from different types of adaptors installed at different times, each adaptor defining a different corresponding plug type and a different corresponding electrical configuration from those of one another, output power from a traction battery according to both the corresponding plug type and the corresponding electrical configuration of the adaptor. 8. The system of claim 7, wherein each electrical configuration includes a combination of a number of poles, voltage, and current different from that of other electrical configurations. 9. The system of claim 8, wherein one of the combinations is a two-pole three-wire grounding 125-V and 15-A output and another combination is a four-pole five-wire grounding 208-VAC and 20-A output. 10. The system of claim 7, wherein the converter is further configured to issue a fault notification and interrupt the outputting of power responsive to a ground fault interrupt. 11. A vehicle comprising:
an electric machine; a traction battery configured to power the electric machine; and a voltage converter defining a connection interface configured to electrically couple the converter to corresponding interfaces of each of different types of smart adaptors, each of the smart adaptors defining a different corresponding electrical configuration such that, responsive to receiving different signals from different ones of the smart adaptors connected to the converter at different times, the converter outputs power from the traction buttery according to the corresponding electrical configuration of the one of the smart adaptors that is currently connected to the converter. 12. The vehicle of claim 11, wherein the electrical configuration includes one of a pole, ground, voltage, and current different from one another. 13. The vehicle of claim 12, wherein one of the configurations is a two-pole three-wire grounding 125-V and 15-A output and another configuration is a four-pole five-wire grounding 208-VAC and 20-A output. 14. The vehicle of claim 12, wherein the electrical configuration includes one of the pole, ground, voltage, and current that are same with one another. 15. The vehicle of claim 14, wherein one of the configurations is a two-pole three-wire grounding 125-V and 15-A output and another configuration is a two-pole three-wire grounding 125-V and 20-A output. | A system for a vehicle includes a converter configured to, responsive to a first signal from a first adaptor indicating a first plug type having a first electrical parameter configuration, output power to the adaptor according to the first electrical parameter configuration, and responsive to a second signal from a second adaptor indicating a second plug type having a second electrical parameter configuration, output power to the adaptor according to the second configuration.1. A vehicle comprising:
an electric machine; a traction battery configured to power the electric machine; and a converter configured to
responsive to a first signal from a first adaptor indicating a first plug type having a first electrical parameter configuration, output power from the traction battery to the first adaptor according to the first electrical parameter configuration, and
responsive to a second signal from a second adaptor indicating a second plug type having a second electrical parameter configuration, output power from the traction battery to the second adaptor according to the second configuration. 2. The vehicle of claim 1, wherein the first electrical parameter configuration and the second electrical parameter configuration include one of a pole, ground, voltage, and current different from one another. 3. The vehicle of claim 2, wherein each of the first and second configurations defines an operating range of an electric load powered via the plug type. 4. The vehicle of claim 1, wherein the first electrical parameter configuration and the second electrical parameter configuration include a pole, ground, and voltage that are same and current that is different. 5. (canceled) 6. The vehicle of claim 1, wherein the converter is further configured to issue a fault notification and interrupt the outputting of power responsive to a ground fault interrupt. 7. A system for a vehicle comprising:
a converter configured to, responsive to different signals from different types of adaptors installed at different times, each adaptor defining a different corresponding plug type and a different corresponding electrical configuration from those of one another, output power from a traction battery according to both the corresponding plug type and the corresponding electrical configuration of the adaptor. 8. The system of claim 7, wherein each electrical configuration includes a combination of a number of poles, voltage, and current different from that of other electrical configurations. 9. The system of claim 8, wherein one of the combinations is a two-pole three-wire grounding 125-V and 15-A output and another combination is a four-pole five-wire grounding 208-VAC and 20-A output. 10. The system of claim 7, wherein the converter is further configured to issue a fault notification and interrupt the outputting of power responsive to a ground fault interrupt. 11. A vehicle comprising:
an electric machine; a traction battery configured to power the electric machine; and a voltage converter defining a connection interface configured to electrically couple the converter to corresponding interfaces of each of different types of smart adaptors, each of the smart adaptors defining a different corresponding electrical configuration such that, responsive to receiving different signals from different ones of the smart adaptors connected to the converter at different times, the converter outputs power from the traction buttery according to the corresponding electrical configuration of the one of the smart adaptors that is currently connected to the converter. 12. The vehicle of claim 11, wherein the electrical configuration includes one of a pole, ground, voltage, and current different from one another. 13. The vehicle of claim 12, wherein one of the configurations is a two-pole three-wire grounding 125-V and 15-A output and another configuration is a four-pole five-wire grounding 208-VAC and 20-A output. 14. The vehicle of claim 12, wherein the electrical configuration includes one of the pole, ground, voltage, and current that are same with one another. 15. The vehicle of claim 14, wherein one of the configurations is a two-pole three-wire grounding 125-V and 15-A output and another configuration is a two-pole three-wire grounding 125-V and 20-A output. | 2,800 |
12,155 | 12,155 | 15,347,492 | 2,859 | One embodiment provides an electronic device, including: two or more ports; two or more charging circuits, wherein the two or more ports have an associated charging circuit; a battery; a processor; and a memory device that stores instructions executable by the processor to: detect, at a first port, a physically connected plug; detect, at a second port, a physically connected plug; and provide, via the two or more charging circuits, charging to the battery from both of the detected plugs. Other aspects are described and claimed. | 1. An electronic device, comprising:
two or more ports; two or more charging circuits, wherein said two or more ports have an associated charging circuit; a battery; a processor; and a memory device that stores instructions executable by the processor to: detect, at a first port, a physically connected plug; detect, at a second port, a physically connected plug; and provide, via the two or more charging circuits, charging to the battery from both of the detected plugs. 2. The electronic device of claim 1, wherein the charging comprises parallel current input via the two or more charging circuits. 3. The electronic device of claim 1, wherein the first port and the second port are different types of ports. 4. The electronic device of claim 3, wherein one type of port is a power and data port. 5. The electronic device of claim 3, wherein the processor prioritizes one of the first port and the second port. 6. The electronic device of claim 4, wherein the processor prioritizes a port that provides a greater amount of charging as compared to another port. 7. The electronic device of claim 1, wherein the first port and the second port are the same type of port. 8. The electronic device of claim 7, wherein each of the first port and the second port are power and data ports. 9. The electronic device of claim 8, wherein each of the first port and the second port are power ports. 10. The electronic device of claim 1, further comprising:
a controller associated with at least one of the two or more ports; wherein the processor is included in a system embedded controller; and wherein the processor communicates with the controller to select a type of charging from said at least one of the two or more ports. 11. A method, comprising:
detecting, using a controller, that a plug is physically connected to a first port of an electronic device; detecting, using the controller, that a plug is physically connected to a second port of the electronic device; and providing, via two or more charging circuits associated with the first port and the second port, charging from both of the detected plugs to a battery of the electronic device. 12. The method of claim 11, wherein the charging comprises parallel current input via the two or more charging circuits. 13. The method of claim 11, wherein the first port and the second port are different types of ports. 14. The method of claim 13, wherein one type of port is a power and data port. 15. The method of claim 13, further comprising prioritizing one of the first port and the second port. 16. The method of claim 14, wherein the prioritizing comprises prioritizing a port that provides a greater amount of charging as compared to another port. 17. The method of claim 11, wherein the first port and the second port are the same type of port. 18. The method of claim 17, wherein each of the first port and the second port are power and data ports. 19. The method of claim 18, wherein each of the first port and the second port are power ports. 20. A system, comprising:
a charging unit providing at least two plugs; and an electronic device, comprising: two or more ports that accept the at least two plugs; two or more charging circuits, wherein said two or more ports have an associated charging circuit; a battery; a processor; and a memory device that stores instructions executable by the processor to: detect, at a first port, a physically connected plug; detect, at a second port, a physically connected plug; and provide, via the two or more charging circuits, charging to the battery from both of the detected plugs. | One embodiment provides an electronic device, including: two or more ports; two or more charging circuits, wherein the two or more ports have an associated charging circuit; a battery; a processor; and a memory device that stores instructions executable by the processor to: detect, at a first port, a physically connected plug; detect, at a second port, a physically connected plug; and provide, via the two or more charging circuits, charging to the battery from both of the detected plugs. Other aspects are described and claimed.1. An electronic device, comprising:
two or more ports; two or more charging circuits, wherein said two or more ports have an associated charging circuit; a battery; a processor; and a memory device that stores instructions executable by the processor to: detect, at a first port, a physically connected plug; detect, at a second port, a physically connected plug; and provide, via the two or more charging circuits, charging to the battery from both of the detected plugs. 2. The electronic device of claim 1, wherein the charging comprises parallel current input via the two or more charging circuits. 3. The electronic device of claim 1, wherein the first port and the second port are different types of ports. 4. The electronic device of claim 3, wherein one type of port is a power and data port. 5. The electronic device of claim 3, wherein the processor prioritizes one of the first port and the second port. 6. The electronic device of claim 4, wherein the processor prioritizes a port that provides a greater amount of charging as compared to another port. 7. The electronic device of claim 1, wherein the first port and the second port are the same type of port. 8. The electronic device of claim 7, wherein each of the first port and the second port are power and data ports. 9. The electronic device of claim 8, wherein each of the first port and the second port are power ports. 10. The electronic device of claim 1, further comprising:
a controller associated with at least one of the two or more ports; wherein the processor is included in a system embedded controller; and wherein the processor communicates with the controller to select a type of charging from said at least one of the two or more ports. 11. A method, comprising:
detecting, using a controller, that a plug is physically connected to a first port of an electronic device; detecting, using the controller, that a plug is physically connected to a second port of the electronic device; and providing, via two or more charging circuits associated with the first port and the second port, charging from both of the detected plugs to a battery of the electronic device. 12. The method of claim 11, wherein the charging comprises parallel current input via the two or more charging circuits. 13. The method of claim 11, wherein the first port and the second port are different types of ports. 14. The method of claim 13, wherein one type of port is a power and data port. 15. The method of claim 13, further comprising prioritizing one of the first port and the second port. 16. The method of claim 14, wherein the prioritizing comprises prioritizing a port that provides a greater amount of charging as compared to another port. 17. The method of claim 11, wherein the first port and the second port are the same type of port. 18. The method of claim 17, wherein each of the first port and the second port are power and data ports. 19. The method of claim 18, wherein each of the first port and the second port are power ports. 20. A system, comprising:
a charging unit providing at least two plugs; and an electronic device, comprising: two or more ports that accept the at least two plugs; two or more charging circuits, wherein said two or more ports have an associated charging circuit; a battery; a processor; and a memory device that stores instructions executable by the processor to: detect, at a first port, a physically connected plug; detect, at a second port, a physically connected plug; and provide, via the two or more charging circuits, charging to the battery from both of the detected plugs. | 2,800 |
12,156 | 12,156 | 14,911,877 | 2,899 | A battery having a display indicating an amount of time the battery can be used before needing to be recharged and/or replaced. The amount of time can be displayed in minutes. An end of life indicator indicating whether the battery should be replaced can also be provided on the battery. The battery can determine the amount of time and an end of life indication based on environmental conditions and/or use. The battery can include sensors for measuring and/or monitoring environmental conditions, as well as a global positioning system (GPS) transponder. The battery can also include a communication link for transmitting data to a central location, a specified location and/or a pre-selected location, which data can include the amount of time the battery can be used before needing to be recharged and/or replaced. The battery can be coupled to and configured to power a device. Particular advantages can be realized with medical devices, especially defibrillators and other Advanced Life Support Devices which are typically exposed to a wide range of end user use models and environmental conditions. | 1. A battery, comprising:
a display indicating an amount of time the battery can be used before needing to be at least one of recharged or replaced. 2. The battery of claim 1, wherein the amount of time is displayed in minutes. 3. The battery of claim 1, wherein the display provides an end of life indicator including a tricolored LED. 4. The battery of claim 3, wherein the tricolored LED includes at least one of:
a green LED indicating the battery is in a good condition; a yellow LED indicating the battery is nearing an end of life; or a red LED indicating an immediate replacement of the battery. 5. The battery of claim 1 further comprising sensors for at least one of measuring or monitoring environmental conditions, wherein the battery determines the amount of time and an end of life indication based on at least one of the environmental conditions or usage. 6. The battery of claim 1 further comprising a global positioning system transponder. 7. The battery of claim 1 further comprising a communication link for transmitting data to at least one of a central location, a specified location or a pre-selected location. 8. The battery of claim 7, wherein the data includes the amount of time the battery can be used before needing to be at least one of recharged or replaced. 9. A system comprising:
a device; and a battery, coupled to the device and configured to power the device, wherein the battery comprises a display indicating an amount of time the battery can be used to power the device before needing to be at least one of recharged or replaced. 10. The system of claim 9, wherein the display is configured to display the amount of time in minutes. 11. The system of claim 9, further comprising an end of life indicator including a tricolored LED, wherein the tricolored LED includes at least one of:
a green LED indicating the battery is in a good condition; a yellow LED indicating the battery is nearing an end of life; or a red LED indicating an immediate replacement of the battery. 12. The system of claim 9, wherein the display is configured to display an end of life condition as a number of recharge cycles remaining before the battery should be replaced. 13. The system of claim 9, wherein the display is configured to display an end of life condition as an indication that the battery should be replaced. 14. The system of claim 9, wherein the battery determines the amount of time based on at least one of environmental conditions or use. 15. The system of claim 14, wherein the battery is structured and configured to at least one of measure or monitor use. 16. The system of claim 9 further comprising a communication link for transmitting data to at least one of a central location, a specified location or a pre-selected location. 17. The system of claim 16, wherein the communication link is coupled directly to the battery. 18. The system of claim 17, wherein the communication link is structured and configured to communicate at least one of wirelessly or via the cloud. 19. The system of claim 9, wherein the device is a defibrillator. 20. A method, comprising:
monitoring at least one of environmental conditions or use of a battery; determining at least one of (i) an amount of time remaining before the battery should be recharged or replaced, or (ii) an end of life condition of the battery; and displaying at least one of the amount of time remaining or the end of life condition on a display on the battery. | A battery having a display indicating an amount of time the battery can be used before needing to be recharged and/or replaced. The amount of time can be displayed in minutes. An end of life indicator indicating whether the battery should be replaced can also be provided on the battery. The battery can determine the amount of time and an end of life indication based on environmental conditions and/or use. The battery can include sensors for measuring and/or monitoring environmental conditions, as well as a global positioning system (GPS) transponder. The battery can also include a communication link for transmitting data to a central location, a specified location and/or a pre-selected location, which data can include the amount of time the battery can be used before needing to be recharged and/or replaced. The battery can be coupled to and configured to power a device. Particular advantages can be realized with medical devices, especially defibrillators and other Advanced Life Support Devices which are typically exposed to a wide range of end user use models and environmental conditions.1. A battery, comprising:
a display indicating an amount of time the battery can be used before needing to be at least one of recharged or replaced. 2. The battery of claim 1, wherein the amount of time is displayed in minutes. 3. The battery of claim 1, wherein the display provides an end of life indicator including a tricolored LED. 4. The battery of claim 3, wherein the tricolored LED includes at least one of:
a green LED indicating the battery is in a good condition; a yellow LED indicating the battery is nearing an end of life; or a red LED indicating an immediate replacement of the battery. 5. The battery of claim 1 further comprising sensors for at least one of measuring or monitoring environmental conditions, wherein the battery determines the amount of time and an end of life indication based on at least one of the environmental conditions or usage. 6. The battery of claim 1 further comprising a global positioning system transponder. 7. The battery of claim 1 further comprising a communication link for transmitting data to at least one of a central location, a specified location or a pre-selected location. 8. The battery of claim 7, wherein the data includes the amount of time the battery can be used before needing to be at least one of recharged or replaced. 9. A system comprising:
a device; and a battery, coupled to the device and configured to power the device, wherein the battery comprises a display indicating an amount of time the battery can be used to power the device before needing to be at least one of recharged or replaced. 10. The system of claim 9, wherein the display is configured to display the amount of time in minutes. 11. The system of claim 9, further comprising an end of life indicator including a tricolored LED, wherein the tricolored LED includes at least one of:
a green LED indicating the battery is in a good condition; a yellow LED indicating the battery is nearing an end of life; or a red LED indicating an immediate replacement of the battery. 12. The system of claim 9, wherein the display is configured to display an end of life condition as a number of recharge cycles remaining before the battery should be replaced. 13. The system of claim 9, wherein the display is configured to display an end of life condition as an indication that the battery should be replaced. 14. The system of claim 9, wherein the battery determines the amount of time based on at least one of environmental conditions or use. 15. The system of claim 14, wherein the battery is structured and configured to at least one of measure or monitor use. 16. The system of claim 9 further comprising a communication link for transmitting data to at least one of a central location, a specified location or a pre-selected location. 17. The system of claim 16, wherein the communication link is coupled directly to the battery. 18. The system of claim 17, wherein the communication link is structured and configured to communicate at least one of wirelessly or via the cloud. 19. The system of claim 9, wherein the device is a defibrillator. 20. A method, comprising:
monitoring at least one of environmental conditions or use of a battery; determining at least one of (i) an amount of time remaining before the battery should be recharged or replaced, or (ii) an end of life condition of the battery; and displaying at least one of the amount of time remaining or the end of life condition on a display on the battery. | 2,800 |
12,157 | 12,157 | 15,600,996 | 2,881 | Ions are injected into an orbital electrostatic trap. An ejection potential is applied to an ion storage device, to cause ions stored in the ion storage device to be ejected towards the orbital electrostatic trap. Synchronous injection potentials are applied to a central electrode of the orbital electrostatic trap and a deflector electrode associated with the orbital electrostatic trap, to cause the ions ejected from the ion storage device to be captured by the electrostatic trap such that they orbit the central electrode. Application of the ejection potential and application of the synchronous injection potentials are each started at respective different times, the difference in times being selected based on desired values of mass-to-charge ratios of ions to be captured by the orbital electrostatic trap. | 1. A method of injecting ions into an orbital electrostatic trap, comprising:
applying an ejection potential to an ion storage device, to cause ions stored in the ion storage device to be ejected towards the orbital electrostatic trap; and applying synchronous injection potentials to a central electrode of the orbital electrostatic trap and a deflector electrode associated with the orbital electrostatic trap, to cause the ions ejected from the ion storage device to be captured by the electrostatic trap such that they orbit the central electrode; wherein the steps of applying the ejection potential and applying the synchronous injection potentials are each started at respective different times, the difference in times being selected based on desired values of mass-to-charge ratios of ions to be captured by the orbital electrostatic trap. 2. The method of claim 1, wherein one or both of a magnitude and a direction of the difference between the time at which the step of applying the ejection potential is started and the time at which the step of applying the synchronous injection potentials is started is or are selected based on the desired values of mass-to-charge ratios of ions to be captured by the orbital electrostatic trap. 3. The method of claim 1, wherein the desired values of mass-to-charge ratios of ions to be captured by the orbital electrostatic trap includes values lower than a threshold mass-to-charge ratio, the difference in times being selected such that the start of the step of applying the synchronous injection potentials precedes the start of the step of applying the ejection potential. 4. The method of claim 3, wherein the threshold mass-to-charge ratio is 100 Thomsons. 5. The method of claim 1, wherein the desired values of mass-to-charge ratios of ions to be captured by the electrostatic trap includes values higher than a limit mass-to-charge ratio, the difference in times being selected such that start of the step of applying the ejection potential precedes the start of the step of applying the synchronous injection potentials. 6. The method of claim 5, wherein the limit mass-to-charge ratio is 8000 Thomsons. 7. The method of claim 1, wherein the magnitude of the difference between the time at which the step of applying the ejection potential is started and the time at which the step of applying the synchronous injection potentials is started is one of: at least 3 μs; at least 10 μs; at least 15 μs; at least 20 μs; and at least 25 μs. 8. The method of claim 1, wherein the magnitude of the difference between the time at which the step of applying the ejection potential is started and the time at which the step of applying the synchronous injection potentials is started is based on one or more of: a time period associated with the ejection potential; a time period associated with the synchronous injection potentials; and a time period associated with a flight time for ions between the ion storage device and the electrostatic trap. 9. The method of claim 8, wherein the magnitude of the difference is at least 3 times an induction period associated with the synchronous injection potentials. 10. The method of claim 8, wherein the magnitude of the difference is based on: a discharge time constant associated with the synchronous injection potentials; and/or a flight time for ions between the ion storage device and the orbital electrostatic trap. 11. The method of claim 10, wherein the magnitude of the difference is greater than the flight time for ions between the ion storage device and the orbital electrostatic trap but less than the sum of the flight time for ions between the ion storage device and the orbital electrostatic trap and the discharge time constant associated with the synchronous injection potentials. 12. The method of claim 10, wherein the discharge time constant associated with the synchronous injection potentials is dependent on at least one respective resistance and at least one respective capacitance associated with each of the central electrode and the deflector electrode to which the synchronous injection potentials are applied. 13. The method of claim 10, wherein the discharge time constant associated with the synchronous injection waveforms is programmable or adjustable using digital circuitry. 14. The method of claim 1, wherein the orbital electrostatic trap comprises the central electrode and a co-axial outer electrode and wherein the step of applying synchronous injection potentials comprises applying a trapping injection potential to the central electrode. 15. The method of claim 14, wherein the trapping injection potential is a ramping potential from a first injection potential level to a second, lower injection potential level. 16. The method of claim 1, wherein an ion deflector comprising the deflector electrode is provided between the ion storage device and the orbital electrostatic trap and wherein the step of applying synchronous injection potentials comprises applying a deflecting injection potential to the ion deflector, to cause the ions to travel towards the orbital electrostatic trap. 17. The method of claim 1, wherein the step of applying the ejection potential comprises reducing a magnitude of a potential applied to one or more electrodes of the ion storage device, such that the ions stored in the ion storage device are ejected towards the orbital electrostatic trap. 18. The method of claim 17, wherein the step of applying the ejection potential comprises switching off an RF potential applied to one or more electrodes of the ion storage device, and applying a DC extraction potential to one or more electrodes of the ion storage device, such that the ions stored in the ion storage device are ejected towards the orbital electrostatic trap. 19. The method of claim 1, wherein the ion storage device is a curved linear trap. 20. The method of claim 1, wherein the step of applying an ejection potential is started by applying an ejection trigger signal to an ejection switch controlling application of the ejection potential and/or wherein the step of applying synchronous injection potentials is started by applying one or more injection trigger signals to at least one injection switch controlling application of the synchronous injection potentials. 21. The method of claim 1, wherein an RF potential with a predetermined frequency is generated and the difference between respective start times of the steps of applying the ejection potential and applying the synchronous injection potentials is measured using the predetermined frequency of the RF potential. 22. A mass spectrometer, comprising:
an ion storage device, configured to receive ions for analysis, store the received ions and eject the stored ions; an orbital electrostatic trap, having a central electrode and an associated deflector electrode and being arranged to receive the ions ejected from the ion storage device; and a controller, configured to perform steps of:
applying an ejection potential to the ion storage device, to cause ions stored in the ion storage device to be ejected towards the orbital electrostatic trap; and
applying synchronous injection potentials to the central electrode of the orbital electrostatic trap and a deflector electrode associated with the orbital electrostatic trap, to cause the ions ejected from the ion storage device to be captured by the electrostatic trap such that they orbit the central electrode; wherein the steps of applying the ejection potential and applying the synchronous injection potentials are each started at respective different times, the difference in times being selected based on desired values of mass-to-charge ratios of ions to be captured by the orbital electrostatic trap. | Ions are injected into an orbital electrostatic trap. An ejection potential is applied to an ion storage device, to cause ions stored in the ion storage device to be ejected towards the orbital electrostatic trap. Synchronous injection potentials are applied to a central electrode of the orbital electrostatic trap and a deflector electrode associated with the orbital electrostatic trap, to cause the ions ejected from the ion storage device to be captured by the electrostatic trap such that they orbit the central electrode. Application of the ejection potential and application of the synchronous injection potentials are each started at respective different times, the difference in times being selected based on desired values of mass-to-charge ratios of ions to be captured by the orbital electrostatic trap.1. A method of injecting ions into an orbital electrostatic trap, comprising:
applying an ejection potential to an ion storage device, to cause ions stored in the ion storage device to be ejected towards the orbital electrostatic trap; and applying synchronous injection potentials to a central electrode of the orbital electrostatic trap and a deflector electrode associated with the orbital electrostatic trap, to cause the ions ejected from the ion storage device to be captured by the electrostatic trap such that they orbit the central electrode; wherein the steps of applying the ejection potential and applying the synchronous injection potentials are each started at respective different times, the difference in times being selected based on desired values of mass-to-charge ratios of ions to be captured by the orbital electrostatic trap. 2. The method of claim 1, wherein one or both of a magnitude and a direction of the difference between the time at which the step of applying the ejection potential is started and the time at which the step of applying the synchronous injection potentials is started is or are selected based on the desired values of mass-to-charge ratios of ions to be captured by the orbital electrostatic trap. 3. The method of claim 1, wherein the desired values of mass-to-charge ratios of ions to be captured by the orbital electrostatic trap includes values lower than a threshold mass-to-charge ratio, the difference in times being selected such that the start of the step of applying the synchronous injection potentials precedes the start of the step of applying the ejection potential. 4. The method of claim 3, wherein the threshold mass-to-charge ratio is 100 Thomsons. 5. The method of claim 1, wherein the desired values of mass-to-charge ratios of ions to be captured by the electrostatic trap includes values higher than a limit mass-to-charge ratio, the difference in times being selected such that start of the step of applying the ejection potential precedes the start of the step of applying the synchronous injection potentials. 6. The method of claim 5, wherein the limit mass-to-charge ratio is 8000 Thomsons. 7. The method of claim 1, wherein the magnitude of the difference between the time at which the step of applying the ejection potential is started and the time at which the step of applying the synchronous injection potentials is started is one of: at least 3 μs; at least 10 μs; at least 15 μs; at least 20 μs; and at least 25 μs. 8. The method of claim 1, wherein the magnitude of the difference between the time at which the step of applying the ejection potential is started and the time at which the step of applying the synchronous injection potentials is started is based on one or more of: a time period associated with the ejection potential; a time period associated with the synchronous injection potentials; and a time period associated with a flight time for ions between the ion storage device and the electrostatic trap. 9. The method of claim 8, wherein the magnitude of the difference is at least 3 times an induction period associated with the synchronous injection potentials. 10. The method of claim 8, wherein the magnitude of the difference is based on: a discharge time constant associated with the synchronous injection potentials; and/or a flight time for ions between the ion storage device and the orbital electrostatic trap. 11. The method of claim 10, wherein the magnitude of the difference is greater than the flight time for ions between the ion storage device and the orbital electrostatic trap but less than the sum of the flight time for ions between the ion storage device and the orbital electrostatic trap and the discharge time constant associated with the synchronous injection potentials. 12. The method of claim 10, wherein the discharge time constant associated with the synchronous injection potentials is dependent on at least one respective resistance and at least one respective capacitance associated with each of the central electrode and the deflector electrode to which the synchronous injection potentials are applied. 13. The method of claim 10, wherein the discharge time constant associated with the synchronous injection waveforms is programmable or adjustable using digital circuitry. 14. The method of claim 1, wherein the orbital electrostatic trap comprises the central electrode and a co-axial outer electrode and wherein the step of applying synchronous injection potentials comprises applying a trapping injection potential to the central electrode. 15. The method of claim 14, wherein the trapping injection potential is a ramping potential from a first injection potential level to a second, lower injection potential level. 16. The method of claim 1, wherein an ion deflector comprising the deflector electrode is provided between the ion storage device and the orbital electrostatic trap and wherein the step of applying synchronous injection potentials comprises applying a deflecting injection potential to the ion deflector, to cause the ions to travel towards the orbital electrostatic trap. 17. The method of claim 1, wherein the step of applying the ejection potential comprises reducing a magnitude of a potential applied to one or more electrodes of the ion storage device, such that the ions stored in the ion storage device are ejected towards the orbital electrostatic trap. 18. The method of claim 17, wherein the step of applying the ejection potential comprises switching off an RF potential applied to one or more electrodes of the ion storage device, and applying a DC extraction potential to one or more electrodes of the ion storage device, such that the ions stored in the ion storage device are ejected towards the orbital electrostatic trap. 19. The method of claim 1, wherein the ion storage device is a curved linear trap. 20. The method of claim 1, wherein the step of applying an ejection potential is started by applying an ejection trigger signal to an ejection switch controlling application of the ejection potential and/or wherein the step of applying synchronous injection potentials is started by applying one or more injection trigger signals to at least one injection switch controlling application of the synchronous injection potentials. 21. The method of claim 1, wherein an RF potential with a predetermined frequency is generated and the difference between respective start times of the steps of applying the ejection potential and applying the synchronous injection potentials is measured using the predetermined frequency of the RF potential. 22. A mass spectrometer, comprising:
an ion storage device, configured to receive ions for analysis, store the received ions and eject the stored ions; an orbital electrostatic trap, having a central electrode and an associated deflector electrode and being arranged to receive the ions ejected from the ion storage device; and a controller, configured to perform steps of:
applying an ejection potential to the ion storage device, to cause ions stored in the ion storage device to be ejected towards the orbital electrostatic trap; and
applying synchronous injection potentials to the central electrode of the orbital electrostatic trap and a deflector electrode associated with the orbital electrostatic trap, to cause the ions ejected from the ion storage device to be captured by the electrostatic trap such that they orbit the central electrode; wherein the steps of applying the ejection potential and applying the synchronous injection potentials are each started at respective different times, the difference in times being selected based on desired values of mass-to-charge ratios of ions to be captured by the orbital electrostatic trap. | 2,800 |
12,158 | 12,158 | 16,139,360 | 2,811 | Provided is an ultraviolet light receiving element capable of reducing visible light sensitivity. The ultraviolet light receiving element includes: a first photodiode sensitive to an ultraviolet light provided in a first region of a semiconductor substrate; and a second photodiode insensitive to the ultraviolet light provided in a second region of the semiconductor substrate. A second well implantation layer in the second photodiode has a peak concentration position deeper than a peak concentration position of a well implantation layer in the first photodiode by a depth equal to a depth from a surface of the semiconductor substrate to a peak concentration position of a surface implantation layer in the second photodiode. | 1. An ultraviolet light receiving element, comprising:
a first photodiode sensitive to an ultraviolet light provided in a first region of a semiconductor substrate, and including a first well implantation layer of a first conductivity type, a first embedded implantation layer of a second conductivity type, and a first surface implantation layer of the first conductivity type, the first embedded implantation layer being formed in the first well implantation layer, the first surface implantation layer being formed in a surface of the semiconductor substrate in the first embedded implantation layer; and a second photodiode insensitive to an ultraviolet light provided in a second region of the semiconductor substrate, and including a second well implantation layer of the first conductivity type, a second embedded implantation layer of the second conductivity type, and a second surface implantation layer of the first conductivity type, the second embedded implantation layer being formed in the second well implantation layer, the second surface implantation layer being formed in the surface of the semiconductor substrate in the second embedded implantation layer, the second well implantation layer having a peak concentration position deeper than a peak concentration position of the first well implantation layer by a depth equal to a depth from the surface of the semiconductor substrate to a peak concentration position of the second surface implantation layer. 2. An ultraviolet light receiving element, comprising:
a first photodiode sensitive to the ultraviolet light provided in a first region of a semiconductor substrate, and including a first well implantation layer of a first conductivity type, a first embedded implantation layer of a second conductivity type, and a first surface implantation layer of the first conductivity type, the first embedded implantation layer being formed in the first well implantation layer, the first surface implantation layer being formed in a surface of the semiconductor substrate in the first embedded implantation layer; and a second photodiode insensitive to the ultraviolet light provided in a second region of the semiconductor substrate, and including a second well implantation layer of the first conductivity type, a second embedded implantation layer of the second conductivity type, and a second surface implantation layer of the first conductivity type, the second embedded implantation layer being formed in the second well implantation layer, the second surface implantation layer being formed in the surface of the semiconductor substrate in the second embedded implantation layer, the second well implantation layer having a peak concentration position deeper than the peak concentration position of the first well implantation layer by a depth dp which is calculated by the following expression:
d p ≈d s exp(αx p)
where ds is a depth from the surface of the semiconductor substrate to a peak concentration position of the second surface implantation layer, xp is a depth from the surface of the semiconductor substrate to a peak concentration position of the first well implantation layer, α is a light absorption coefficient in the semiconductor substrate, and αxp is not regarded as zero. 3. A method of manufacturing an ultraviolet light receiving element, comprising:
forming, in a first region of a semiconductor substrate of a first conductivity type, a first photodiode sensitive to the ultraviolet light including a first well implantation layer of a second conductivity type, a first embedded implantation layer of the first conductivity type, and a first surface implantation layer of the second conductivity type, the first embedded implantation layer being formed in the first well implantation layer, the first surface implantation layer being formed in a surface of the semiconductor substrate in the first embedded implantation layer; and forming, in a second region of the semiconductor substrate, a second photodiode insensitive to the ultraviolet light including a second well implantation layer of the second conductivity type, a second embedded implantation layer of the first conductivity type, and a second surface implantation layer of the second conductivity type, the second embedded implantation layer being formed in the second well implantation layer, the second surface implantation layer being formed in the surface of the semiconductor substrate in the second embedded implantation layer, the second well implantation layer being formed so as to have a peak concentration position deeper than a peak concentration position of the first well implantation layer by a depth equal to a depth from the surface of the semiconductor substrate to a peak concentration position of the second surface implantation layer. 4. A method of manufacturing an ultraviolet light receiving element, comprising:
forming, in a first region of a semiconductor substrate of a first conductivity type, a first photodiode sensitive to an ultraviolet light including a first well implantation layer of a second conductivity type, a first embedded implantation layer of the first conductivity type, and a first surface implantation layer of the second conductivity type, the first embedded implantation layer being formed in the first well implantation layer, the first surface implantation layer being formed in a surface of the semiconductor substrate in the first embedded implantation layer; and forming, in a second region of the semiconductor substrate, a second photodiode insensitive to the ultraviolet light including a second well implantation layer of the second conductivity type, a second embedded implantation layer of the first conductivity type, and a second surface implantation layer of the second conductivity type, the second embedded implantation layer being formed in the second well implantation layer, the second surface implantation layer being formed in the surface of the semiconductor substrate in the second embedded implantation layer, the second well implantation layer being formed so as to have a peak concentration position deeper than the peak concentration position of the first well implantation layer by a depth dp which is calculated by the following expression:
d p ≈d s exp(αx p)
where ds is a depth from the surface of the semiconductor substrate to a peak concentration position of the second surface implantation layer, xp is a depth from the surface of the semiconductor substrate to a peak concentration position of the first well implantation layer, α is a light absorption coefficient in the semiconductor substrate, and αxp is not regarded as zero. | Provided is an ultraviolet light receiving element capable of reducing visible light sensitivity. The ultraviolet light receiving element includes: a first photodiode sensitive to an ultraviolet light provided in a first region of a semiconductor substrate; and a second photodiode insensitive to the ultraviolet light provided in a second region of the semiconductor substrate. A second well implantation layer in the second photodiode has a peak concentration position deeper than a peak concentration position of a well implantation layer in the first photodiode by a depth equal to a depth from a surface of the semiconductor substrate to a peak concentration position of a surface implantation layer in the second photodiode.1. An ultraviolet light receiving element, comprising:
a first photodiode sensitive to an ultraviolet light provided in a first region of a semiconductor substrate, and including a first well implantation layer of a first conductivity type, a first embedded implantation layer of a second conductivity type, and a first surface implantation layer of the first conductivity type, the first embedded implantation layer being formed in the first well implantation layer, the first surface implantation layer being formed in a surface of the semiconductor substrate in the first embedded implantation layer; and a second photodiode insensitive to an ultraviolet light provided in a second region of the semiconductor substrate, and including a second well implantation layer of the first conductivity type, a second embedded implantation layer of the second conductivity type, and a second surface implantation layer of the first conductivity type, the second embedded implantation layer being formed in the second well implantation layer, the second surface implantation layer being formed in the surface of the semiconductor substrate in the second embedded implantation layer, the second well implantation layer having a peak concentration position deeper than a peak concentration position of the first well implantation layer by a depth equal to a depth from the surface of the semiconductor substrate to a peak concentration position of the second surface implantation layer. 2. An ultraviolet light receiving element, comprising:
a first photodiode sensitive to the ultraviolet light provided in a first region of a semiconductor substrate, and including a first well implantation layer of a first conductivity type, a first embedded implantation layer of a second conductivity type, and a first surface implantation layer of the first conductivity type, the first embedded implantation layer being formed in the first well implantation layer, the first surface implantation layer being formed in a surface of the semiconductor substrate in the first embedded implantation layer; and a second photodiode insensitive to the ultraviolet light provided in a second region of the semiconductor substrate, and including a second well implantation layer of the first conductivity type, a second embedded implantation layer of the second conductivity type, and a second surface implantation layer of the first conductivity type, the second embedded implantation layer being formed in the second well implantation layer, the second surface implantation layer being formed in the surface of the semiconductor substrate in the second embedded implantation layer, the second well implantation layer having a peak concentration position deeper than the peak concentration position of the first well implantation layer by a depth dp which is calculated by the following expression:
d p ≈d s exp(αx p)
where ds is a depth from the surface of the semiconductor substrate to a peak concentration position of the second surface implantation layer, xp is a depth from the surface of the semiconductor substrate to a peak concentration position of the first well implantation layer, α is a light absorption coefficient in the semiconductor substrate, and αxp is not regarded as zero. 3. A method of manufacturing an ultraviolet light receiving element, comprising:
forming, in a first region of a semiconductor substrate of a first conductivity type, a first photodiode sensitive to the ultraviolet light including a first well implantation layer of a second conductivity type, a first embedded implantation layer of the first conductivity type, and a first surface implantation layer of the second conductivity type, the first embedded implantation layer being formed in the first well implantation layer, the first surface implantation layer being formed in a surface of the semiconductor substrate in the first embedded implantation layer; and forming, in a second region of the semiconductor substrate, a second photodiode insensitive to the ultraviolet light including a second well implantation layer of the second conductivity type, a second embedded implantation layer of the first conductivity type, and a second surface implantation layer of the second conductivity type, the second embedded implantation layer being formed in the second well implantation layer, the second surface implantation layer being formed in the surface of the semiconductor substrate in the second embedded implantation layer, the second well implantation layer being formed so as to have a peak concentration position deeper than a peak concentration position of the first well implantation layer by a depth equal to a depth from the surface of the semiconductor substrate to a peak concentration position of the second surface implantation layer. 4. A method of manufacturing an ultraviolet light receiving element, comprising:
forming, in a first region of a semiconductor substrate of a first conductivity type, a first photodiode sensitive to an ultraviolet light including a first well implantation layer of a second conductivity type, a first embedded implantation layer of the first conductivity type, and a first surface implantation layer of the second conductivity type, the first embedded implantation layer being formed in the first well implantation layer, the first surface implantation layer being formed in a surface of the semiconductor substrate in the first embedded implantation layer; and forming, in a second region of the semiconductor substrate, a second photodiode insensitive to the ultraviolet light including a second well implantation layer of the second conductivity type, a second embedded implantation layer of the first conductivity type, and a second surface implantation layer of the second conductivity type, the second embedded implantation layer being formed in the second well implantation layer, the second surface implantation layer being formed in the surface of the semiconductor substrate in the second embedded implantation layer, the second well implantation layer being formed so as to have a peak concentration position deeper than the peak concentration position of the first well implantation layer by a depth dp which is calculated by the following expression:
d p ≈d s exp(αx p)
where ds is a depth from the surface of the semiconductor substrate to a peak concentration position of the second surface implantation layer, xp is a depth from the surface of the semiconductor substrate to a peak concentration position of the first well implantation layer, α is a light absorption coefficient in the semiconductor substrate, and αxp is not regarded as zero. | 2,800 |
12,159 | 12,159 | 16,205,429 | 2,853 | A printer is configured to apply marking material to print media to create a printed item, and a transport belt is positioned to receive the printed item from the printer and is configured to dry the marking material on the printed item. The transport belt has a middle layer attached between outer and inner layers, and the printed item contacts the outer layer. The outer and inner layers are non-perforated entangled fiber materials that are porous and that are more flexible than the middle layer. | 1. An apparatus comprising:
a printer configured to apply marking material to print media to create a printed item; and a transport belt positioned to receive the printed item from the printer and configured to dry the marking material on the printed item, wherein the transport belt comprises a second layer between a first layer and a third layer, wherein the printed item contacts the first layer, and wherein the first layer and the third layer comprise non-perforated entangled fiber materials that are air porous. 2. The apparatus according to claim 1, wherein the second layer comprises a woven material, and wherein the fibers of the second layer include a first group of parallel linear fibers and a second group of parallel linear fibers, wherein the first group is arranged perpendicular to the second group. 3. The apparatus according to claim 2, further comprising a polymer coating on the second layer preventing the first group from moving relative to the second group. 4. The apparatus according to claim 1, wherein the first layer and the third layer are more flexible than the second layer. 5. The apparatus according to claim 1, wherein the first layer has a different flexibility from the third layer. 6. The apparatus according to claim 1, further comprising an adhesive bonding the second layer to the first layer and the third layer. 7. The apparatus according to claim 1, wherein the second layer comprises a solid material with perforations, and wherein the second layer is not air permeable and air only passes through the perforations in the second layer. 8. An apparatus comprising:
a sheet feeder configured to feed print media; a print engine positioned to receive the print media from the sheet feeder and configured to apply marking material to the print media to create a printed item; a transport belt positioned to receive the printed item from the print engine and configured to move the printed item away from the print engine; a heater positioned adjacent to the transport belt and configured to heat the printed item on the transport belt; and a vacuum plenum positioned adjacent to the transport belt and configured to draw air through the transport belt, wherein the transport belt, the vacuum plenum, and the heater are configured to dry the marking material on the printed item while the printed item is on the transport belt, wherein the transport belt comprises a second layer between a first layer and a third layer, wherein the printed item contacts the first layer, and wherein the first layer and the third layer comprise non-perforated entangled fiber materials that are air porous. 9. The apparatus according to claim 8, wherein the second layer comprises a woven material, and wherein the fibers of the second layer include a first group of parallel linear fibers and a second group of parallel linear fibers, wherein the first group is arranged perpendicular to the second group. 10. The apparatus according to claim 9, further comprising a polymer coating on the second layer preventing the first group from moving relative to the second group. 11. The apparatus according to claim 8, wherein the first layer and the third layer are more flexible than the second layer. 12. The apparatus according to claim 8, wherein the first layer has a different flexibility from the third layer. 13. The apparatus according to claim 8, further comprising an adhesive bonding the second layer to the first layer and the third layer. 14. The apparatus according to claim 8, wherein the second layer comprises a solid material with perforations, and wherein the second layer is not air permeable and air only passes through perforations in the second layer. 15. A transport belt comprising:
a second layer; a first layer attached to a first side of the second layer; and a third layer attached to a second side of the second layer, opposite the first side, wherein the second layer is between the first layer and the third layer, wherein the first layer is positioned to receive a printed item from a printer, wherein the second layer, the first layer, and the third layer are configured to dry the marking material on the printed item, and wherein the first layer and the third layer comprise non-perforated entangled fiber materials that are air porous. 16. The transport belt according to claim 15, wherein the second layer comprises a woven material, and wherein the fibers of the second layer include a first group of parallel linear fibers and a second group of parallel linear fibers, wherein the first group is arranged perpendicular to the second group. 17. The transport belt according to claim 16, further comprising a polymer coating on the second layer preventing the first group from moving relative to the second group. 18. The transport belt according to claim 15, wherein the first layer and the third layer are more flexible than the second layer. 19. The transport belt according to claim 15, wherein the first layer has a different flexibility from the third layer. 20. The transport belt according to claim 15, further comprising an adhesive bonding the second layer to the first layer and the third layer. | A printer is configured to apply marking material to print media to create a printed item, and a transport belt is positioned to receive the printed item from the printer and is configured to dry the marking material on the printed item. The transport belt has a middle layer attached between outer and inner layers, and the printed item contacts the outer layer. The outer and inner layers are non-perforated entangled fiber materials that are porous and that are more flexible than the middle layer.1. An apparatus comprising:
a printer configured to apply marking material to print media to create a printed item; and a transport belt positioned to receive the printed item from the printer and configured to dry the marking material on the printed item, wherein the transport belt comprises a second layer between a first layer and a third layer, wherein the printed item contacts the first layer, and wherein the first layer and the third layer comprise non-perforated entangled fiber materials that are air porous. 2. The apparatus according to claim 1, wherein the second layer comprises a woven material, and wherein the fibers of the second layer include a first group of parallel linear fibers and a second group of parallel linear fibers, wherein the first group is arranged perpendicular to the second group. 3. The apparatus according to claim 2, further comprising a polymer coating on the second layer preventing the first group from moving relative to the second group. 4. The apparatus according to claim 1, wherein the first layer and the third layer are more flexible than the second layer. 5. The apparatus according to claim 1, wherein the first layer has a different flexibility from the third layer. 6. The apparatus according to claim 1, further comprising an adhesive bonding the second layer to the first layer and the third layer. 7. The apparatus according to claim 1, wherein the second layer comprises a solid material with perforations, and wherein the second layer is not air permeable and air only passes through the perforations in the second layer. 8. An apparatus comprising:
a sheet feeder configured to feed print media; a print engine positioned to receive the print media from the sheet feeder and configured to apply marking material to the print media to create a printed item; a transport belt positioned to receive the printed item from the print engine and configured to move the printed item away from the print engine; a heater positioned adjacent to the transport belt and configured to heat the printed item on the transport belt; and a vacuum plenum positioned adjacent to the transport belt and configured to draw air through the transport belt, wherein the transport belt, the vacuum plenum, and the heater are configured to dry the marking material on the printed item while the printed item is on the transport belt, wherein the transport belt comprises a second layer between a first layer and a third layer, wherein the printed item contacts the first layer, and wherein the first layer and the third layer comprise non-perforated entangled fiber materials that are air porous. 9. The apparatus according to claim 8, wherein the second layer comprises a woven material, and wherein the fibers of the second layer include a first group of parallel linear fibers and a second group of parallel linear fibers, wherein the first group is arranged perpendicular to the second group. 10. The apparatus according to claim 9, further comprising a polymer coating on the second layer preventing the first group from moving relative to the second group. 11. The apparatus according to claim 8, wherein the first layer and the third layer are more flexible than the second layer. 12. The apparatus according to claim 8, wherein the first layer has a different flexibility from the third layer. 13. The apparatus according to claim 8, further comprising an adhesive bonding the second layer to the first layer and the third layer. 14. The apparatus according to claim 8, wherein the second layer comprises a solid material with perforations, and wherein the second layer is not air permeable and air only passes through perforations in the second layer. 15. A transport belt comprising:
a second layer; a first layer attached to a first side of the second layer; and a third layer attached to a second side of the second layer, opposite the first side, wherein the second layer is between the first layer and the third layer, wherein the first layer is positioned to receive a printed item from a printer, wherein the second layer, the first layer, and the third layer are configured to dry the marking material on the printed item, and wherein the first layer and the third layer comprise non-perforated entangled fiber materials that are air porous. 16. The transport belt according to claim 15, wherein the second layer comprises a woven material, and wherein the fibers of the second layer include a first group of parallel linear fibers and a second group of parallel linear fibers, wherein the first group is arranged perpendicular to the second group. 17. The transport belt according to claim 16, further comprising a polymer coating on the second layer preventing the first group from moving relative to the second group. 18. The transport belt according to claim 15, wherein the first layer and the third layer are more flexible than the second layer. 19. The transport belt according to claim 15, wherein the first layer has a different flexibility from the third layer. 20. The transport belt according to claim 15, further comprising an adhesive bonding the second layer to the first layer and the third layer. | 2,800 |
12,160 | 12,160 | 14,927,016 | 2,883 | A photonic integrated circuit may be coupled to an optical fiber and packaged. The optical fiber may be supported by a fiber holder during a solder reflow process performed to mount the packaged photonic integrated circuit to a circuit board or other substrate. The optical fiber may be decoupled from the fiber holder, and the fiber holder removed, after completion of the solder reflow process. | 1. An apparatus, comprising:
a substrate having a first surface; a photonic integrated circuit (PIC) coupled to the substrate and having a first surface proximate the first surface of the substrate and a second surface opposite the first surface of the PIC and distal the first surface of the substrate; a lid, contacting the first surface of the substrate; a fiber holder disposed on the lid; and an optical fiber coupled to the PIC and in contact with the fiber holder. 2. The apparatus according to claim 1, wherein a portion of the optical fiber is coiled around the fiber holder. 3. The apparatus according to claim 2, wherein the portion of the optical fiber is coiled around the fiber holder within a plane that is substantially parallel to the second surface of the PIC. 4. The apparatus according to claim 1, wherein the optical fiber is edge-coupled to the PIC. 5. The apparatus according to claim 1, further comprising an electronic integrated circuit disposed on the first surface of the substrate. 6. The apparatus according to claim 1, further comprising a circuit board on which the substrate in mounted. 7. The apparatus according to claim 6, wherein the substrate is electrically connected to the circuit board through a ball grid array. 8. The apparatus according to claim 1, wherein the fiber holder is made of copper. 9. The apparatus according to claim 1, further comprising an interposer having a first surface proximate the first surface of the substrate and a second surface opposite the first surface of the interposer and proximate the first surface of the PIC. 10. The apparatus according to claim 1, further comprising a fiber assembly containing a groove on which the optical fiber is disposed. 11. The apparatus according to claim 10, further comprising a thermal pad contacting the fiber assembly. 12. A method, comprising:
packaging a photonic integrated circuit (PIC) in a package comprising a substrate and a lid; mounting a fiber holder on the lid of the package such that the lid is between the PIC and the fiber holder; coupling an optical fiber to the PIC; mechanically coupling the optical fiber to the fiber holder. 13. The method according to claim 12, further comprising surface-mounting the package on a chip carrier. 14. The method according to claim 13, further comprising securing an end of the optical fiber on the fiber holder. 15. The method according to claim 12, further comprising performing reflow soldering of the package. 16. The method according to claim 15, further comprising removing the fiber holder from the package subsequent to the reflow soldering. 17. The method according to claim 12, wherein mechanically coupling the optical fiber to the fiber holder comprises coiling a portion of the optical fiber around the fiber holder. 18. The method according to claim 17, wherein the portion of the optical fiber is coiled around the fiber holder with a radius that is less than a minimum bend radius of the optical fiber. 19. The method according to claim 12, further comprising splicing the optical fiber to an optical component. 20. The method according to claim 12, wherein mounting the fiber holder on the lid of the package comprises mounting the fiber holder with at least one screw inserted on the lid. 21. An apparatus, comprising:
a substrate having a first surface; a photonic integrated circuit (PIC) coupled to the substrate and having a first surface proximate the first surface of the substrate and a second surface opposite the first surface of the PIC and distal the first surface of the substrate; a lid, contacting the first surface of the substrate and at least partially covering the PIC, exhibiting at least one retaining feature; and an optical fiber coupled to the PIC and in contact with the retaining feature of the lid. 22. The apparatus of claim 21, wherein the retaining feature comprises a groove in the lid. 23. The apparatus of claim 21, wherein the retaining feature comprises a fiber channel. 24. The apparatus of claim 21, wherein the lid is formed of a thermally conductive material. | A photonic integrated circuit may be coupled to an optical fiber and packaged. The optical fiber may be supported by a fiber holder during a solder reflow process performed to mount the packaged photonic integrated circuit to a circuit board or other substrate. The optical fiber may be decoupled from the fiber holder, and the fiber holder removed, after completion of the solder reflow process.1. An apparatus, comprising:
a substrate having a first surface; a photonic integrated circuit (PIC) coupled to the substrate and having a first surface proximate the first surface of the substrate and a second surface opposite the first surface of the PIC and distal the first surface of the substrate; a lid, contacting the first surface of the substrate; a fiber holder disposed on the lid; and an optical fiber coupled to the PIC and in contact with the fiber holder. 2. The apparatus according to claim 1, wherein a portion of the optical fiber is coiled around the fiber holder. 3. The apparatus according to claim 2, wherein the portion of the optical fiber is coiled around the fiber holder within a plane that is substantially parallel to the second surface of the PIC. 4. The apparatus according to claim 1, wherein the optical fiber is edge-coupled to the PIC. 5. The apparatus according to claim 1, further comprising an electronic integrated circuit disposed on the first surface of the substrate. 6. The apparatus according to claim 1, further comprising a circuit board on which the substrate in mounted. 7. The apparatus according to claim 6, wherein the substrate is electrically connected to the circuit board through a ball grid array. 8. The apparatus according to claim 1, wherein the fiber holder is made of copper. 9. The apparatus according to claim 1, further comprising an interposer having a first surface proximate the first surface of the substrate and a second surface opposite the first surface of the interposer and proximate the first surface of the PIC. 10. The apparatus according to claim 1, further comprising a fiber assembly containing a groove on which the optical fiber is disposed. 11. The apparatus according to claim 10, further comprising a thermal pad contacting the fiber assembly. 12. A method, comprising:
packaging a photonic integrated circuit (PIC) in a package comprising a substrate and a lid; mounting a fiber holder on the lid of the package such that the lid is between the PIC and the fiber holder; coupling an optical fiber to the PIC; mechanically coupling the optical fiber to the fiber holder. 13. The method according to claim 12, further comprising surface-mounting the package on a chip carrier. 14. The method according to claim 13, further comprising securing an end of the optical fiber on the fiber holder. 15. The method according to claim 12, further comprising performing reflow soldering of the package. 16. The method according to claim 15, further comprising removing the fiber holder from the package subsequent to the reflow soldering. 17. The method according to claim 12, wherein mechanically coupling the optical fiber to the fiber holder comprises coiling a portion of the optical fiber around the fiber holder. 18. The method according to claim 17, wherein the portion of the optical fiber is coiled around the fiber holder with a radius that is less than a minimum bend radius of the optical fiber. 19. The method according to claim 12, further comprising splicing the optical fiber to an optical component. 20. The method according to claim 12, wherein mounting the fiber holder on the lid of the package comprises mounting the fiber holder with at least one screw inserted on the lid. 21. An apparatus, comprising:
a substrate having a first surface; a photonic integrated circuit (PIC) coupled to the substrate and having a first surface proximate the first surface of the substrate and a second surface opposite the first surface of the PIC and distal the first surface of the substrate; a lid, contacting the first surface of the substrate and at least partially covering the PIC, exhibiting at least one retaining feature; and an optical fiber coupled to the PIC and in contact with the retaining feature of the lid. 22. The apparatus of claim 21, wherein the retaining feature comprises a groove in the lid. 23. The apparatus of claim 21, wherein the retaining feature comprises a fiber channel. 24. The apparatus of claim 21, wherein the lid is formed of a thermally conductive material. | 2,800 |
12,161 | 12,161 | 15,557,591 | 2,899 | The invention relates to a chip arrangement ( 10 ) and to a method for forming a contact connection ( 11 ) between a chip ( 18 ), in particular a power transistor or the like, and a conductor material track ( 14 ), the conductor material track being formed on a non-conductive substrate ( 12 ), the chip being arranged on the substrate or on a conductor material track ( 15 ), a silver paste ( 29 ) or a copper paste being applied to each of a chip contact surface ( 25 ) of the chip and the conductor material track ( 28 ), a contact conductor ( 30 ) being immersed into the silver paste or the copper paste on the chip contact surface and into the silver paste or the copper paste on the conductor material track, a solvent contained in the silver paste or the copper paste being at least partially vaporized by heating and the contact connection being formed by sintering the silver paste or the copper paste by means of laser energy. | 1. A method for forming a contact connection between a chip and a conductor material track, the conductor material track being formed on a non-conductive substrate, the chip being arranged on the substrate or on another conductor material track,
comprising the steps of applying a silver paste or a copper paste to each of a chip contact surface of the chip and the conductor material track, immersing a contact conductor into the silver paste or the copper paste on the chip contact surface and into the silver paste or the copper paste on the conductor material track, heating the silver paste or the copper paste to at least partially vaporize a solvent contained in the silver paste or the copper paste and forming the contact connection by sintering the silver paste or the copper paste with laser energy. 2. The method according to claim 1,
wherein a stranded wire is used as a contact conductor. 3. The method according to claim 2,
wherein the stranded wire is at least partially infiltrated by the silver paste or the copper paste. 4. The method according to claim 2,
wherein only one stranded wire is used per chip contact surface. 5. The method according to claim 1,
wherein the step of heating of the silver paste or the copper paste is achieved by arranging the substrate on or on top of a heating element. 6. The method according to claim 1,
further comprising the step of supporting the substrate with a clamp during heating. 7. The method according to claim 1,
further comprising the step of sintering the silver paste or the copper paste prior to complete vaporization of the solvent. 8. The method according to claim 1,
further comprising the step of pressing the contact conductor onto the chip contact surface and/or onto the conductor material track during sintering. 9. The method according to claim 1,
further comprising the step of severing the contact conductor after sintering. 10. The method according to claim 1,
wherein the chip contact surface is formed by applying a copper strip to a chip surface. 11. The method according to claim 1,
wherein a contact metallization is applied to the conductor material track and/or to the chip contact surface. 12. The method according to claim 11,
wherein the contact metallization is formed by physical vapor deposition (PVD), sputter deposition, galvanization or electroless plating. 13. The method according to claim 11,
wherein the contact metallization is made of silver, nickel, copper, gold, palladium, aluminum or an alloy of one of said metals. 14. A chip arrangement comprising a chip, a non-conductive substrate having a conductor material track formed thereon and a contact conductor, the chip being arranged on the substrate or on a conductor material track,
wherein a silver paste or a copper paste is applied to each of a chip contact surface of the chip and the conductor material track, the contact conductor being immersed into the silver paste or the copper paste on the chip contact surface and into the silver paste or the copper paste on the conductor material track, a solvent contained in the silver paste or the copper paste being vaporized by heating and a contact connection being formed by sintering of the silver paste or the copper paste with laser energy. 15. The method of claim 1, wherein the chip is a power transistor. 16. The method of claim 2, wherein the stranded wire is a flat litz wire made of copper or a copper alloy. 17. The chip arrangement of claim 14, wherein the chip comprises a power transistor. | The invention relates to a chip arrangement ( 10 ) and to a method for forming a contact connection ( 11 ) between a chip ( 18 ), in particular a power transistor or the like, and a conductor material track ( 14 ), the conductor material track being formed on a non-conductive substrate ( 12 ), the chip being arranged on the substrate or on a conductor material track ( 15 ), a silver paste ( 29 ) or a copper paste being applied to each of a chip contact surface ( 25 ) of the chip and the conductor material track ( 28 ), a contact conductor ( 30 ) being immersed into the silver paste or the copper paste on the chip contact surface and into the silver paste or the copper paste on the conductor material track, a solvent contained in the silver paste or the copper paste being at least partially vaporized by heating and the contact connection being formed by sintering the silver paste or the copper paste by means of laser energy.1. A method for forming a contact connection between a chip and a conductor material track, the conductor material track being formed on a non-conductive substrate, the chip being arranged on the substrate or on another conductor material track,
comprising the steps of applying a silver paste or a copper paste to each of a chip contact surface of the chip and the conductor material track, immersing a contact conductor into the silver paste or the copper paste on the chip contact surface and into the silver paste or the copper paste on the conductor material track, heating the silver paste or the copper paste to at least partially vaporize a solvent contained in the silver paste or the copper paste and forming the contact connection by sintering the silver paste or the copper paste with laser energy. 2. The method according to claim 1,
wherein a stranded wire is used as a contact conductor. 3. The method according to claim 2,
wherein the stranded wire is at least partially infiltrated by the silver paste or the copper paste. 4. The method according to claim 2,
wherein only one stranded wire is used per chip contact surface. 5. The method according to claim 1,
wherein the step of heating of the silver paste or the copper paste is achieved by arranging the substrate on or on top of a heating element. 6. The method according to claim 1,
further comprising the step of supporting the substrate with a clamp during heating. 7. The method according to claim 1,
further comprising the step of sintering the silver paste or the copper paste prior to complete vaporization of the solvent. 8. The method according to claim 1,
further comprising the step of pressing the contact conductor onto the chip contact surface and/or onto the conductor material track during sintering. 9. The method according to claim 1,
further comprising the step of severing the contact conductor after sintering. 10. The method according to claim 1,
wherein the chip contact surface is formed by applying a copper strip to a chip surface. 11. The method according to claim 1,
wherein a contact metallization is applied to the conductor material track and/or to the chip contact surface. 12. The method according to claim 11,
wherein the contact metallization is formed by physical vapor deposition (PVD), sputter deposition, galvanization or electroless plating. 13. The method according to claim 11,
wherein the contact metallization is made of silver, nickel, copper, gold, palladium, aluminum or an alloy of one of said metals. 14. A chip arrangement comprising a chip, a non-conductive substrate having a conductor material track formed thereon and a contact conductor, the chip being arranged on the substrate or on a conductor material track,
wherein a silver paste or a copper paste is applied to each of a chip contact surface of the chip and the conductor material track, the contact conductor being immersed into the silver paste or the copper paste on the chip contact surface and into the silver paste or the copper paste on the conductor material track, a solvent contained in the silver paste or the copper paste being vaporized by heating and a contact connection being formed by sintering of the silver paste or the copper paste with laser energy. 15. The method of claim 1, wherein the chip is a power transistor. 16. The method of claim 2, wherein the stranded wire is a flat litz wire made of copper or a copper alloy. 17. The chip arrangement of claim 14, wherein the chip comprises a power transistor. | 2,800 |
12,162 | 12,162 | 15,253,418 | 2,812 | A method of manufacturing a semiconductor device includes: forming a porous area at a surface of a semiconductor body; forming a semiconductor layer on the porous area by epitaxial growth; forming semiconductor regions including source, drain, body, emitter, base and/or collector regions in a front surface of the semiconductor layer, wherein the front surface of the semiconductor layer corresponds to a front side of the semiconductor device; introducing, after forming the semiconductor regions, hydrogen into the porous area by a thermal treatment, wherein the semiconductor layer with the semiconductor regions is separated from the semiconductor body along the porous area; and applying, after separation of the semiconductor layer, rear side processing to the semiconductor layer, wherein a rear side of the semiconductor layer corresponds to a rear side of the semiconductor device. | 1. A method of manufacturing a semiconductor device, the method comprising:
forming a porous area at a surface of a semiconductor body; forming a semiconductor layer on the porous area by epitaxial growth; forming semiconductor regions including source, drain, body, emitter, base and/or collector regions in a front surface of the semiconductor layer, wherein the front surface of the semiconductor layer corresponds to a front side of the semiconductor device; introducing, after forming the semiconductor regions, hydrogen into the porous area by a thermal treatment, wherein the semiconductor layer with the semiconductor regions is separated from the semiconductor body along the porous area; and applying, after separation of the semiconductor layer, rear side processing to the semiconductor layer, wherein a rear side of the semiconductor layer corresponds to a rear side of the semiconductor device. 2. The method of claim 1, wherein the hydrogen is introduced into the porous area by diffusion of the hydrogen through the semiconductor layer into the porous area. 3. The method of claim 1, wherein the semiconductor body is one of Si and SiC. 4. The method of claim 1, wherein forming the porous area of the semiconductor body comprises anodic dissolution of the semiconductor body. 5. The method of claim 4, wherein the anodic dissolution of the semiconductor body comprises anodic dissolution of silicon in a chemical mixture of hydrofluoric acid and ethanol or acetic acid. 6. The method of claim 4, wherein forming the porous area comprises forming a double porosity structure including a first porous area in the semiconductor body which has a first porosity and a second porous area deeper within the semiconductor body which has a second porosity, wherein the first porosity is smaller than the second porosity. 7. The method of claim 6, wherein the porosity of the first porous area is set in a range between 10% and 50% and the porosity of the second porous area is set in a range between the porosity of the first porous area and 80%. 8. The method of claim 1, wherein forming the semiconductor regions in the semiconductor layer comprises forming at least one of n-type and p-type regions in the semiconductor layer by introducing impurities into the semiconductor layer. 9. The method of claim 1, further comprising forming a trench in at least one of the semiconductor body and in the semiconductor layer. 10. The method of claim 1, wherein the semiconductor layer has a thickness in a range from 5 μm to 200 μm. 11. The method of claim 1, wherein the rear side processing comprises at least one of ion implantation and laser anneal. 12. A method of manufacturing a semiconductor device, the method comprising:
forming a porous area at a surface of a semiconductor body, wherein the porous area has a porous structure; forming a semiconductor layer on the porous area by epitaxial growth; forming, by ion implantation, semiconductor regions including source, drain, body, emitter, base and/or collector regions in a front side of the semiconductor layer, wherein the front surface of the semiconductor layer forms a front side surface of a semiconducting portion of the semiconductor device; introducing, after forming the semiconductor regions, hydrogen into the porous area by ion-implantation, wherein the semiconductor layer with the semiconductor regions is separated from the semiconductor body along the porous area; and applying, after separation of the semiconductor layer, rear side processing comprising ion_implantation to the semiconductor layer, wherein a rear side of the semiconductor layer defines a rear side surface of the semiconducting portion and a thickness of the semiconductor layer defines a thickness of the semiconductor portion. 13. The method of claim 12, wherein an implant dose of the hydrogen is in a range of 5·1014 cm−2 to 5·1015 cm−2. 14. The method of claim 12, wherein an implant energy of the ion implantation is in the range of 150 keV to 4 MeV. 15. The method of claim 12, wherein forming the porous area of the semiconductor body comprises anodic dissolution of the semiconductor body. 16. The method of claim 15, wherein the anodic dissolution of the semiconductor body comprises anodic dissolution of silicon in a chemical mixture of hydrofluoric acid and ethanol or acetic acid. 17. The method of claim 15, wherein forming the porous area comprises forming a double porosity structure including a first porous area in the semiconductor body which has a first porosity and a second porous area deeper within the semiconductor body which has a second porosity, wherein the first porosity is smaller than the second porosity. 18. The method of claim 17, wherein the porosity of the first porous area is set in a range between 10% and 50% and the porosity of the second porous area is set in a range between the porosity of the first porous area and 80%. | A method of manufacturing a semiconductor device includes: forming a porous area at a surface of a semiconductor body; forming a semiconductor layer on the porous area by epitaxial growth; forming semiconductor regions including source, drain, body, emitter, base and/or collector regions in a front surface of the semiconductor layer, wherein the front surface of the semiconductor layer corresponds to a front side of the semiconductor device; introducing, after forming the semiconductor regions, hydrogen into the porous area by a thermal treatment, wherein the semiconductor layer with the semiconductor regions is separated from the semiconductor body along the porous area; and applying, after separation of the semiconductor layer, rear side processing to the semiconductor layer, wherein a rear side of the semiconductor layer corresponds to a rear side of the semiconductor device.1. A method of manufacturing a semiconductor device, the method comprising:
forming a porous area at a surface of a semiconductor body; forming a semiconductor layer on the porous area by epitaxial growth; forming semiconductor regions including source, drain, body, emitter, base and/or collector regions in a front surface of the semiconductor layer, wherein the front surface of the semiconductor layer corresponds to a front side of the semiconductor device; introducing, after forming the semiconductor regions, hydrogen into the porous area by a thermal treatment, wherein the semiconductor layer with the semiconductor regions is separated from the semiconductor body along the porous area; and applying, after separation of the semiconductor layer, rear side processing to the semiconductor layer, wherein a rear side of the semiconductor layer corresponds to a rear side of the semiconductor device. 2. The method of claim 1, wherein the hydrogen is introduced into the porous area by diffusion of the hydrogen through the semiconductor layer into the porous area. 3. The method of claim 1, wherein the semiconductor body is one of Si and SiC. 4. The method of claim 1, wherein forming the porous area of the semiconductor body comprises anodic dissolution of the semiconductor body. 5. The method of claim 4, wherein the anodic dissolution of the semiconductor body comprises anodic dissolution of silicon in a chemical mixture of hydrofluoric acid and ethanol or acetic acid. 6. The method of claim 4, wherein forming the porous area comprises forming a double porosity structure including a first porous area in the semiconductor body which has a first porosity and a second porous area deeper within the semiconductor body which has a second porosity, wherein the first porosity is smaller than the second porosity. 7. The method of claim 6, wherein the porosity of the first porous area is set in a range between 10% and 50% and the porosity of the second porous area is set in a range between the porosity of the first porous area and 80%. 8. The method of claim 1, wherein forming the semiconductor regions in the semiconductor layer comprises forming at least one of n-type and p-type regions in the semiconductor layer by introducing impurities into the semiconductor layer. 9. The method of claim 1, further comprising forming a trench in at least one of the semiconductor body and in the semiconductor layer. 10. The method of claim 1, wherein the semiconductor layer has a thickness in a range from 5 μm to 200 μm. 11. The method of claim 1, wherein the rear side processing comprises at least one of ion implantation and laser anneal. 12. A method of manufacturing a semiconductor device, the method comprising:
forming a porous area at a surface of a semiconductor body, wherein the porous area has a porous structure; forming a semiconductor layer on the porous area by epitaxial growth; forming, by ion implantation, semiconductor regions including source, drain, body, emitter, base and/or collector regions in a front side of the semiconductor layer, wherein the front surface of the semiconductor layer forms a front side surface of a semiconducting portion of the semiconductor device; introducing, after forming the semiconductor regions, hydrogen into the porous area by ion-implantation, wherein the semiconductor layer with the semiconductor regions is separated from the semiconductor body along the porous area; and applying, after separation of the semiconductor layer, rear side processing comprising ion_implantation to the semiconductor layer, wherein a rear side of the semiconductor layer defines a rear side surface of the semiconducting portion and a thickness of the semiconductor layer defines a thickness of the semiconductor portion. 13. The method of claim 12, wherein an implant dose of the hydrogen is in a range of 5·1014 cm−2 to 5·1015 cm−2. 14. The method of claim 12, wherein an implant energy of the ion implantation is in the range of 150 keV to 4 MeV. 15. The method of claim 12, wherein forming the porous area of the semiconductor body comprises anodic dissolution of the semiconductor body. 16. The method of claim 15, wherein the anodic dissolution of the semiconductor body comprises anodic dissolution of silicon in a chemical mixture of hydrofluoric acid and ethanol or acetic acid. 17. The method of claim 15, wherein forming the porous area comprises forming a double porosity structure including a first porous area in the semiconductor body which has a first porosity and a second porous area deeper within the semiconductor body which has a second porosity, wherein the first porosity is smaller than the second porosity. 18. The method of claim 17, wherein the porosity of the first porous area is set in a range between 10% and 50% and the porosity of the second porous area is set in a range between the porosity of the first porous area and 80%. | 2,800 |
12,163 | 12,163 | 16,317,624 | 2,844 | Embodiments of the present disclosure provide a microstrip antenna and an antenna array. The microstrip antenna includes a ground plane disposed on a first surface of a substrate of the microstrip antenna; a metal patch disposed on a second surface of the substrate opposite to the first surface; a feeding point disposed on the metal patch such that the microstrip antenna has a first resonant frequency; and a shorting point disposed on the metal patch such that the microstrip antenna has a second resonant frequency different from the first resonant frequency. The microstrip antenna according to embodiments of the present disclosure has a wide bandwidth, a low profile, a high gain, a small size, and a simple structure. | 1. A microstrip antenna, comprising:
a ground plane disposed on a first surface of a substrate of the microstrip antenna; a metal patch disposed on a second surface of the substrate opposite to the first surface; a feeding point disposed on the metal patch such that the microstrip antenna has a first resonant frequency; and a shorting point disposed on the metal patch such that the microstrip antenna has a second resonant frequency different from the first resonant frequency. 2. The microstrip antenna of claim 1, wherein an angle between a line from the shorting point to a center point of the metal patch and a line from the feeding point to the center point is greater than 90 degrees and less than 180 degrees. 3. The microstrip antenna of claim 1, wherein the shorting point includes a via connected to the ground plane. 4. The microstrip antenna of claim 1, further comprising:
at least one slot disposed around the feeding point. 5. The microstrip antenna of claim 4, wherein the at least one slot includes two slots that are substantially symmetrical with respect to a line from the feeding point to a center point of the metal patch. 6. The microstrip antenna of claim 1, wherein the metal patch includes a circular metal patch. 7. The microstrip antenna of claim 1, wherein the microstrip antenna is fed via a coaxial cable. 8. The microstrip antenna of claim 1, wherein a thickness of the substrate is smaller than about one tenth of a wavelength corresponding to a center frequency of the microstrip antenna. 9. The microstrip antenna of claim 1, wherein a size of the metal patch is smaller than about a half of a wavelength corresponding to a center frequency of the microstrip antenna. 10. An antenna array, including a plurality of microstrip antennas according to claim 1. 11. The antenna array of claim 10, wherein an arrangement of the plurality of microstrip antennas and positions of the shorting points of the respective microstrip antennas on the respective metal patches are disposed cooperatively, such that propagation of a surface wave in the antenna array is reduced. 12. The antenna array of claim 10, wherein the antenna array is used in a multiple input multiple output (MIMO) system. 13. A method of manufacturing a microstrip antenna, comprising:
providing a ground plane on a first surface of a substrate of the microstrip antenna; providing a metal patch on a second surface of the substrate opposite to the first surface; providing a feeding point on the metal patch such that the microstrip antenna has a first resonant frequency; and providing a shorting point on the metal patch such that the microstrip antenna has a second resonant frequency different from the first resonant frequency. 14. The method of claim 13, wherein providing the shorting point on the metal patch comprises:
providing the shorting point such that an angle between a line from the shorting point to a center point of the metal patch and a line from the feeding point to the center point is greater than 90 degrees and less than 180 degrees. 15. (canceled) 16. The method of claim 13, further comprising:
providing at least one slot around the feeding point. 17.-21. (canceled) | Embodiments of the present disclosure provide a microstrip antenna and an antenna array. The microstrip antenna includes a ground plane disposed on a first surface of a substrate of the microstrip antenna; a metal patch disposed on a second surface of the substrate opposite to the first surface; a feeding point disposed on the metal patch such that the microstrip antenna has a first resonant frequency; and a shorting point disposed on the metal patch such that the microstrip antenna has a second resonant frequency different from the first resonant frequency. The microstrip antenna according to embodiments of the present disclosure has a wide bandwidth, a low profile, a high gain, a small size, and a simple structure.1. A microstrip antenna, comprising:
a ground plane disposed on a first surface of a substrate of the microstrip antenna; a metal patch disposed on a second surface of the substrate opposite to the first surface; a feeding point disposed on the metal patch such that the microstrip antenna has a first resonant frequency; and a shorting point disposed on the metal patch such that the microstrip antenna has a second resonant frequency different from the first resonant frequency. 2. The microstrip antenna of claim 1, wherein an angle between a line from the shorting point to a center point of the metal patch and a line from the feeding point to the center point is greater than 90 degrees and less than 180 degrees. 3. The microstrip antenna of claim 1, wherein the shorting point includes a via connected to the ground plane. 4. The microstrip antenna of claim 1, further comprising:
at least one slot disposed around the feeding point. 5. The microstrip antenna of claim 4, wherein the at least one slot includes two slots that are substantially symmetrical with respect to a line from the feeding point to a center point of the metal patch. 6. The microstrip antenna of claim 1, wherein the metal patch includes a circular metal patch. 7. The microstrip antenna of claim 1, wherein the microstrip antenna is fed via a coaxial cable. 8. The microstrip antenna of claim 1, wherein a thickness of the substrate is smaller than about one tenth of a wavelength corresponding to a center frequency of the microstrip antenna. 9. The microstrip antenna of claim 1, wherein a size of the metal patch is smaller than about a half of a wavelength corresponding to a center frequency of the microstrip antenna. 10. An antenna array, including a plurality of microstrip antennas according to claim 1. 11. The antenna array of claim 10, wherein an arrangement of the plurality of microstrip antennas and positions of the shorting points of the respective microstrip antennas on the respective metal patches are disposed cooperatively, such that propagation of a surface wave in the antenna array is reduced. 12. The antenna array of claim 10, wherein the antenna array is used in a multiple input multiple output (MIMO) system. 13. A method of manufacturing a microstrip antenna, comprising:
providing a ground plane on a first surface of a substrate of the microstrip antenna; providing a metal patch on a second surface of the substrate opposite to the first surface; providing a feeding point on the metal patch such that the microstrip antenna has a first resonant frequency; and providing a shorting point on the metal patch such that the microstrip antenna has a second resonant frequency different from the first resonant frequency. 14. The method of claim 13, wherein providing the shorting point on the metal patch comprises:
providing the shorting point such that an angle between a line from the shorting point to a center point of the metal patch and a line from the feeding point to the center point is greater than 90 degrees and less than 180 degrees. 15. (canceled) 16. The method of claim 13, further comprising:
providing at least one slot around the feeding point. 17.-21. (canceled) | 2,800 |
12,164 | 12,164 | 14,066,477 | 2,845 | An omni-directional antenna module includes a plurality of vertically and horizontally polarized antenna elements arranged to provide 360° coverage around an antenna, and to eliminate nulls below the antenna. The antenna elements are arranged in parallel with respective orthogonal axes of a three-dimensional Cartesian coordinate system, with the centers of the antenna elements being arranged collinearly along the vertical or “Z” axis so that the radiation patterns of the individual orthogonally polarized dipoles do not interfere. | 1. An omni-directional antenna module, comprising:
a plurality of vertically polarized antenna elements and a plurality of horizontally polarized antenna elements arranged to provide 360° coverage, and to eliminate nulls below an antenna, wherein: the vertically polarized antenna elements and the horizontally polarized antenna element are arranged in parallel with respective orthogonal axes of a three-dimensional Cartesian coordinate system, and centers of the antenna elements are arranged collinearly along a vertical axis of the three-dimensional Cartesian coordinate system. 2. The omni-directional antenna module as claimed in claim 1, wherein a number of the vertically polarized antenna elements is at least three, and the three vertically polarized antenna elements are arranged to coaxially extend along the vertical axis, at least three horizontally polarized antenna elements extending in parallel with a first horizontal axis of the three-dimensional Cartesian coordinate system, and at least two horizontally polarized antenna elements extending in parallel to a second horizontal axis of the three-dimensional Cartesian coordinate system. 3. The omni-directional antenna module as claimed in claim 2, wherein respective pairs consisting of one of the vertically polarized antenna elements and one of the horizontally polarized antenna elements are concentric. 4. The omni-directional antenna module as claimed in claim 2, wherein the horizontally polarized antenna elements have a half-wavelength spacing and a spacing of the vertically polarized antenna elements is approximately one-wavelength. 5. The omni-directional antenna module as claimed in claim 2, wherein the omni-directional antenna module is mounted in a single radome of a small cell base station. 6. The omni-directional antenna module as claimed in claim 1, wherein respective pairs consisting of one of the vertically polarized antenna elements and one of the horizontally polarized antenna elements are concentric. 7. The omni-directional antenna module as claimed in claim 1, wherein the horizontally polarized antenna elements have a half-wavelength spacing and a spacing of the vertically polarized antenna elements is approximately one-wavelength. 8. The omni-directional antenna module as claimed in claim 1, wherein the omni-directional antenna module is mounted in a single radome of a small cell base station. 9. An omni-directional antenna module for small cell applications comprising at least one vertically polarized antenna element, and a plurality of horizontally polarized antenna elements mounted in a single radome of a small cell base station. 10. The omni-directional antenna module for small cell applications as claimed in claim 9, wherein centers of the vertically and horizontally polarized antenna elements are vertically aligned. 11. A method for configuring an omni-directional antenna comprising:
arranging a plurality of vertically polarized antenna elements and a plurality of horizontally polarized antenna elements to provide 360° coverage, and to eliminate nulls below an antenna; arranging the vertically polarized antenna elements and the horizontally polarized antenna element are in parallel with respective orthogonal axes of a three-dimensional Cartesian coordinate system; and arranging centers of the antenna elements collinearly along a vertical axis of the three-dimensional Cartesian coordinate system. 12. The method as claimed in claim 11, wherein a number of the vertically polarized antenna elements is at least three, and the method further comprises coaxially extending the three vertically polarized antenna elements along the vertical axis, extending at least three horizontally polarized antenna elements in parallel with a first horizontal axis of the three-dimensional Cartesian coordinate system, and extending at least two horizontally polarized antenna elements in parallel to a second horizontal axis of the three-dimensional Cartesian coordinate system. 13. The method as claimed in claim 12 further comprising concentrically arranging respective pairs consisting of one of the vertically polarized antenna elements and one of the horizontally polarized antenna elements. 14. The method as claimed in claim 12, wherein the horizontally polarized antenna elements have a half-wavelength spacing and a spacing of the vertically polarized antenna elements is approximately one-wavelength. 15. The method as claimed in claim 12 further comprising mounting the omni-directional antenna module in a single radome of a small cell base station. 16. The method as claimed in claim 11 further comprising concentrically arranging respective pairs consisting of one of the vertically polarized antenna elements and one of the horizontally polarized antenna elements. 17. The method as claimed in claim 11, wherein the horizontally polarized antenna elements have a half-wavelength spacing and a spacing of the vertically polarized antenna elements is approximately one-wavelength. 18. The method as claimed in claim 11 further comprising mounting the omni-directional antenna module in a single radome of a small cell base station. | An omni-directional antenna module includes a plurality of vertically and horizontally polarized antenna elements arranged to provide 360° coverage around an antenna, and to eliminate nulls below the antenna. The antenna elements are arranged in parallel with respective orthogonal axes of a three-dimensional Cartesian coordinate system, with the centers of the antenna elements being arranged collinearly along the vertical or “Z” axis so that the radiation patterns of the individual orthogonally polarized dipoles do not interfere.1. An omni-directional antenna module, comprising:
a plurality of vertically polarized antenna elements and a plurality of horizontally polarized antenna elements arranged to provide 360° coverage, and to eliminate nulls below an antenna, wherein: the vertically polarized antenna elements and the horizontally polarized antenna element are arranged in parallel with respective orthogonal axes of a three-dimensional Cartesian coordinate system, and centers of the antenna elements are arranged collinearly along a vertical axis of the three-dimensional Cartesian coordinate system. 2. The omni-directional antenna module as claimed in claim 1, wherein a number of the vertically polarized antenna elements is at least three, and the three vertically polarized antenna elements are arranged to coaxially extend along the vertical axis, at least three horizontally polarized antenna elements extending in parallel with a first horizontal axis of the three-dimensional Cartesian coordinate system, and at least two horizontally polarized antenna elements extending in parallel to a second horizontal axis of the three-dimensional Cartesian coordinate system. 3. The omni-directional antenna module as claimed in claim 2, wherein respective pairs consisting of one of the vertically polarized antenna elements and one of the horizontally polarized antenna elements are concentric. 4. The omni-directional antenna module as claimed in claim 2, wherein the horizontally polarized antenna elements have a half-wavelength spacing and a spacing of the vertically polarized antenna elements is approximately one-wavelength. 5. The omni-directional antenna module as claimed in claim 2, wherein the omni-directional antenna module is mounted in a single radome of a small cell base station. 6. The omni-directional antenna module as claimed in claim 1, wherein respective pairs consisting of one of the vertically polarized antenna elements and one of the horizontally polarized antenna elements are concentric. 7. The omni-directional antenna module as claimed in claim 1, wherein the horizontally polarized antenna elements have a half-wavelength spacing and a spacing of the vertically polarized antenna elements is approximately one-wavelength. 8. The omni-directional antenna module as claimed in claim 1, wherein the omni-directional antenna module is mounted in a single radome of a small cell base station. 9. An omni-directional antenna module for small cell applications comprising at least one vertically polarized antenna element, and a plurality of horizontally polarized antenna elements mounted in a single radome of a small cell base station. 10. The omni-directional antenna module for small cell applications as claimed in claim 9, wherein centers of the vertically and horizontally polarized antenna elements are vertically aligned. 11. A method for configuring an omni-directional antenna comprising:
arranging a plurality of vertically polarized antenna elements and a plurality of horizontally polarized antenna elements to provide 360° coverage, and to eliminate nulls below an antenna; arranging the vertically polarized antenna elements and the horizontally polarized antenna element are in parallel with respective orthogonal axes of a three-dimensional Cartesian coordinate system; and arranging centers of the antenna elements collinearly along a vertical axis of the three-dimensional Cartesian coordinate system. 12. The method as claimed in claim 11, wherein a number of the vertically polarized antenna elements is at least three, and the method further comprises coaxially extending the three vertically polarized antenna elements along the vertical axis, extending at least three horizontally polarized antenna elements in parallel with a first horizontal axis of the three-dimensional Cartesian coordinate system, and extending at least two horizontally polarized antenna elements in parallel to a second horizontal axis of the three-dimensional Cartesian coordinate system. 13. The method as claimed in claim 12 further comprising concentrically arranging respective pairs consisting of one of the vertically polarized antenna elements and one of the horizontally polarized antenna elements. 14. The method as claimed in claim 12, wherein the horizontally polarized antenna elements have a half-wavelength spacing and a spacing of the vertically polarized antenna elements is approximately one-wavelength. 15. The method as claimed in claim 12 further comprising mounting the omni-directional antenna module in a single radome of a small cell base station. 16. The method as claimed in claim 11 further comprising concentrically arranging respective pairs consisting of one of the vertically polarized antenna elements and one of the horizontally polarized antenna elements. 17. The method as claimed in claim 11, wherein the horizontally polarized antenna elements have a half-wavelength spacing and a spacing of the vertically polarized antenna elements is approximately one-wavelength. 18. The method as claimed in claim 11 further comprising mounting the omni-directional antenna module in a single radome of a small cell base station. | 2,800 |
12,165 | 12,165 | 16,522,170 | 2,848 | A printed circuit board (PCB) including a first side and a second side; a conductive layer within the PCB between the first side and the second side; one or more first side electrical components that are physically attached to the first side and electrically connected to the conductive layer; one or more second side electrical components attached to the second side of the PCB and electrically connected to the conductive layer; and a thermally and electrically insulating dielectric layer, within the PCB between the first side electrical components and the second side electrical components, that prevents heat emitted by the first side electrical components from increasing the temperature of the second side electrical components. | 1. A printed circuit board (PCB) comprising:
a first side and a second side; a conductive layer within the PCB between the first side and the second side; one or more first side electrical components that are physically attached to the first side and electrically connected to the conductive layer; one or more second side electrical components attached to the second side of the PCB and electrically connected to the conductive layer; and a thermally and electrically insulating dielectric layer, within the PCB between the first side electrical components and the second side electrical components, that prevents heat emitted by the first side electrical components from increasing the temperature of the second side electrical components, wherein at least one of the first side electrical components vertically overlaps at least one of the second side electrical components. 2. The PCB recited in claim 1, wherein a top surface of the first side electrical component(s) is coplanar with the first side of the PCB. 3. The PCB recited in claim 2, further comprising a heat sink that directly abuts the first side and the top surface of the first side electrical components. 4. The PCB recited in claim 1, further comprising, an electrically-actuated turbocharger that receives the PCB within a PCB housing. 5. The PCB recited in claim 4, wherein the electrically-actuated turbocharger comprises a compressor and an exhaust turbine. 6. (canceled) 7. A printed circuit board (PCB) comprising:
a first side and a second side; a conductive layer within the PCB between the first side and the second side; one or more apertures in the first side for receiving one or more first side electrical components that are electrically connected to the conductive layer and positioned within the aperture(s) on the first side, wherein the top surface of the first side electrical component(s) is configured to contact a heat sink; one or more second side electrical components attached to the second side of the PCB; and a thermally and electrically insulating dielectric layer, within the PCB between the first side electrical components and the second side electrical components, that prevents heat emitted by the first side electrical components from increasing the temperature of the second side electrical components. 8. The PCB recited in claim 7, wherein a top surface of the first side electrical component(s) is coplanar with the first side of the PCB. 9. The PCB recited in claim 7, further comprising, an electrically-actuated turbocharger that receives the PCB within a PCB housing. 10. The PCB recited in claim 9, wherein the electrically-actuated turbocharger further comprises a compressor and an exhaust turbine. 11. The PCB recited in claim 7, further comprising a heat sink that directly abuts the first side and the top surface of the first side electrical components. 12. The PCB recited in claim 7, wherein at least one of the first side electrical components vertically overlaps at least one of the second side electrical components. | A printed circuit board (PCB) including a first side and a second side; a conductive layer within the PCB between the first side and the second side; one or more first side electrical components that are physically attached to the first side and electrically connected to the conductive layer; one or more second side electrical components attached to the second side of the PCB and electrically connected to the conductive layer; and a thermally and electrically insulating dielectric layer, within the PCB between the first side electrical components and the second side electrical components, that prevents heat emitted by the first side electrical components from increasing the temperature of the second side electrical components.1. A printed circuit board (PCB) comprising:
a first side and a second side; a conductive layer within the PCB between the first side and the second side; one or more first side electrical components that are physically attached to the first side and electrically connected to the conductive layer; one or more second side electrical components attached to the second side of the PCB and electrically connected to the conductive layer; and a thermally and electrically insulating dielectric layer, within the PCB between the first side electrical components and the second side electrical components, that prevents heat emitted by the first side electrical components from increasing the temperature of the second side electrical components, wherein at least one of the first side electrical components vertically overlaps at least one of the second side electrical components. 2. The PCB recited in claim 1, wherein a top surface of the first side electrical component(s) is coplanar with the first side of the PCB. 3. The PCB recited in claim 2, further comprising a heat sink that directly abuts the first side and the top surface of the first side electrical components. 4. The PCB recited in claim 1, further comprising, an electrically-actuated turbocharger that receives the PCB within a PCB housing. 5. The PCB recited in claim 4, wherein the electrically-actuated turbocharger comprises a compressor and an exhaust turbine. 6. (canceled) 7. A printed circuit board (PCB) comprising:
a first side and a second side; a conductive layer within the PCB between the first side and the second side; one or more apertures in the first side for receiving one or more first side electrical components that are electrically connected to the conductive layer and positioned within the aperture(s) on the first side, wherein the top surface of the first side electrical component(s) is configured to contact a heat sink; one or more second side electrical components attached to the second side of the PCB; and a thermally and electrically insulating dielectric layer, within the PCB between the first side electrical components and the second side electrical components, that prevents heat emitted by the first side electrical components from increasing the temperature of the second side electrical components. 8. The PCB recited in claim 7, wherein a top surface of the first side electrical component(s) is coplanar with the first side of the PCB. 9. The PCB recited in claim 7, further comprising, an electrically-actuated turbocharger that receives the PCB within a PCB housing. 10. The PCB recited in claim 9, wherein the electrically-actuated turbocharger further comprises a compressor and an exhaust turbine. 11. The PCB recited in claim 7, further comprising a heat sink that directly abuts the first side and the top surface of the first side electrical components. 12. The PCB recited in claim 7, wherein at least one of the first side electrical components vertically overlaps at least one of the second side electrical components. | 2,800 |
12,166 | 12,166 | 16,764,938 | 2,853 | An interface structure connectable to a separate liquid reservoir, to connect that liquid reservoir to a receiving station, comprising a liquid interface to fluidically connect to at least one liquid needle of the receiving station, a liquid channel, to fluidically connect the liquid interface to the reservoir, a support wall supporting an integrated circuit laterally next to the liquid channel, the integrated circuit having contact pad contact surfaces, and a front push area adjacent the liquid, the front push area terminating at a front edge that defines a profile height of the interface structure, between said front edge and an opposite distal edge. | 1. An interface structure connectable to a separate liquid reservoir, to connect that liquid reservoir to a receiving station, comprising
a first, second and third dimension at straight angles with each other, a liquid interface to fluidically connect to at least one liquid needle of the receiving station, including an interface edge and a seal, a liquid channel, along the second dimension, to fluidically connect the liquid interface to the reservoir, the liquid channel and interface defining a needle insertion direction along the second dimension,
a support wall supporting an integrated circuit laterally next to the liquid channel,
the integrated circuit including contact pad contact surfaces extending approximately in a first virtual reference plane parallel to the second and third dimensions and along a line parallel to the third dimension, the first virtual reference plane extending at a distance from a second virtual reference plane parallel the second and third interface dimensions, the second virtual reference plane intersecting the liquid channel and liquid interface, the contact surfaces facing the second virtual reference plane, and
a front push area adjacent the liquid interface at the opposite side of the liquid interface with respect to the first virtual reference plane, the front push area terminating at a front edge that defines a profile height of the interface structure, between said front edge and an opposite distal edge adjacent the first virtual reference plane. 2. The interface structure of claim 1 further comprising
a base offset from an interface front towards the needle insertion direction,
a key pen protruding from the base next to the liquid channel and parallel and opposite to the needle insertion direction, approximately up to a level of the liquid interface along the second dimension, the second virtual reference plane intersecting the key pen and liquid channel. 3-6. (canceled) 7. The interface structure of claim 1 wherein
a center virtual reference plane passes approximately through a middle of a third dimension of the interface structure, the center virtual reference plane extending parallel to the first and second dimension, and
the liquid interface is located on one side of the center virtual reference plane and the integrated circuit contact pads are provided on the other side of the center virtual reference plane. 8-12. (canceled) 13. The interface structure of claim 2, wherein there are two of said key pens at opposite sides of the liquid channel and the profile height spans opposite key pens approximately parallel to, and at opposite lateral sides of, the liquid channel, and at least one secure feature at an external lateral side of a respective key pen, the secure feature including at least one of a clearance and stop surface, wherein the key pens and the at least one secure feature are intersected by the second virtual reference plane. 14. The interface structure of claim 1 wherein the liquid channel includes a reservoir connecting portion at an opposite end of the liquid channel with respect to the liquid interface, wherein the reservoir connecting portion extends at least partially outside of the profile height, to fluidically connect to the reservoir. 15. The interface structure of claim 1 wherein a central axis of a reservoir connecting liquid channel portion extends at an angle with respect to a central axis of a needle receiving liquid channel portion adjacent the liquid interface, as viewed in a direction of the third dimension. 16-20. (canceled) 21. The interface structure of claim 1 wherein the interface structure includes:
at least one first relatively flat and elongate guide surface that is elongate in a direction along the second dimension, to guide the interface structure along a corresponding guide surface of the receiving station; and
at least one second relatively flat and elongate guide surface, at an angle with the first guide surface, elongate in a direction of the second dimension, the first and second guide surfaces to facilitate guiding in a direction of the second dimension along corresponding guide surfaces of the receiving station, while inhibiting freedom of movement in at least one direction along the first dimension and two opposite directions along the third dimension to facilitate positioning the liquid interface with respect to the needle. 22. (canceled) 23. The interface structure of claim 1 wherein the interface structure includes at least one guide feature extending along the second dimension, at at least one of a lateral side and an external side of the support wall, and wherein the at least one guide feature includes an elongate slot along the second dimension for receiving a corresponding guide rail of the receiving station. 24. (canceled) 25. The interface structure of claim 1 wherein the interface structure includes relatively straight guide surfaces to slide the interface structure along corresponding receiving station surfaces to facilitate aligning the liquid interface to the liquid needle, comprising at least one of (i) at least one lateral guide surface at a respective external lateral side of the interface structure, parallel to the second dimension, to limit a freedom of movement of the interface structure in a direction of the third dimension, and (ii) at least one intermediate guide surface at an external side of the interface structure that extends adjacent the first virtual reference plane, the at least one intermediate guide surface extending parallel to the second dimension and adapted to limit a freedom of movement of the interface structure in a direction of the first dimension. 26-28. (canceled) 29. The interface structure of claim 1 comprising adjacent first and second lateral guide surfaces at straight angles with each other. 30. The interface structure of claim 1 wherein at least one intermediate guide surface is provided in an external side of the support wall of the interface structure, the at least one intermediate guide surface adjacent the liquid interface and channel, the intermediate guide surface to limit the degree of freedom of movement of the interface structure in a direction of the third dimension. 31-33. (canceled) 34. The interface structure of claim 1 comprising a secure feature to facilitate securing the apparatus to a receiving station. 35-48. (canceled) 49. The interface structure of claim 1 comprising two fluidic interfaces, including said liquid interface, and two corresponding channels, including said liquid channel, for receiving two needles of a single receiving station at a single insertion motion. 50. The interface structure of claim 1 wherein the interface structure comprises a protruding key pen protruding along the second dimension from a base to pass through a key hole of the receiving station to actuate upon an actuator, the key pen having an actuating surface area distanced from the base, to engage the actuator. 51-65. (canceled) 66. A print liquid supply apparatus, comprising:
an interface structure according to claim 1, a container including a reservoir, connected to the interface structure, the container having a first, second and third dimension that are parallel to said first, second and third dimension of the interface structure, respectively, the dimensions defining an outer volume of the container, the interface structure projecting outwards with respect to the container over the first dimension. 67. (canceled) 68. The print liquid supply apparatus of claim 66 wherein a projecting portion of the container projects in the main liquid flow direction surpassing the liquid interface. 69. The print liquid supply apparatus of claim 66, wherein interface components of the interface structure that are to interface with the receiving station all extend within a contour defined by the second and third dimension of the container as seen in a view direction parallel to the first dimension of the container, the interface components comprising the liquid interface, the needle receiving portion of the liquid channel, the front push area adjacent the liquid interface, at least one of a key pen, the integrated circuit contact pads, at least one guide feature for guiding the supply apparatus along the second dimension, and a secure feature. 70. The print liquid supply apparatus of claim 66, wherein the container comprises a support structure to support a reservoir, the support structure including an opening in a container wall from which the interface structure projects, to facilitate fluidic connection between the reservoir and the liquid channel of the interface structure. 71-72. (canceled) 73. The print liquid supply apparatus of claim 66, wherein
a liquid reservoir including an at least partly flexible wall relatively impermeable to fluids, the container includes a support structure at least partially around the reservoir, walls of which are relatively permeable to fluids, the interface structure comprises a relatively rigid monolithic plastic structure relatively impermeable to fluids, and the reservoir, support structure and interface structure are separate components. 74. Kit of the components of for construing the interface structure or supply apparatus of claim 66, the kit including at least a fluidic structure, a key pen, a seal and an integrated circuit, the fluidic structure comprising a rigid monolithic fluidic structure that defines at least the liquid channel, to which the key pen, seal and integrated circuit are to be assembled. | An interface structure connectable to a separate liquid reservoir, to connect that liquid reservoir to a receiving station, comprising a liquid interface to fluidically connect to at least one liquid needle of the receiving station, a liquid channel, to fluidically connect the liquid interface to the reservoir, a support wall supporting an integrated circuit laterally next to the liquid channel, the integrated circuit having contact pad contact surfaces, and a front push area adjacent the liquid, the front push area terminating at a front edge that defines a profile height of the interface structure, between said front edge and an opposite distal edge.1. An interface structure connectable to a separate liquid reservoir, to connect that liquid reservoir to a receiving station, comprising
a first, second and third dimension at straight angles with each other, a liquid interface to fluidically connect to at least one liquid needle of the receiving station, including an interface edge and a seal, a liquid channel, along the second dimension, to fluidically connect the liquid interface to the reservoir, the liquid channel and interface defining a needle insertion direction along the second dimension,
a support wall supporting an integrated circuit laterally next to the liquid channel,
the integrated circuit including contact pad contact surfaces extending approximately in a first virtual reference plane parallel to the second and third dimensions and along a line parallel to the third dimension, the first virtual reference plane extending at a distance from a second virtual reference plane parallel the second and third interface dimensions, the second virtual reference plane intersecting the liquid channel and liquid interface, the contact surfaces facing the second virtual reference plane, and
a front push area adjacent the liquid interface at the opposite side of the liquid interface with respect to the first virtual reference plane, the front push area terminating at a front edge that defines a profile height of the interface structure, between said front edge and an opposite distal edge adjacent the first virtual reference plane. 2. The interface structure of claim 1 further comprising
a base offset from an interface front towards the needle insertion direction,
a key pen protruding from the base next to the liquid channel and parallel and opposite to the needle insertion direction, approximately up to a level of the liquid interface along the second dimension, the second virtual reference plane intersecting the key pen and liquid channel. 3-6. (canceled) 7. The interface structure of claim 1 wherein
a center virtual reference plane passes approximately through a middle of a third dimension of the interface structure, the center virtual reference plane extending parallel to the first and second dimension, and
the liquid interface is located on one side of the center virtual reference plane and the integrated circuit contact pads are provided on the other side of the center virtual reference plane. 8-12. (canceled) 13. The interface structure of claim 2, wherein there are two of said key pens at opposite sides of the liquid channel and the profile height spans opposite key pens approximately parallel to, and at opposite lateral sides of, the liquid channel, and at least one secure feature at an external lateral side of a respective key pen, the secure feature including at least one of a clearance and stop surface, wherein the key pens and the at least one secure feature are intersected by the second virtual reference plane. 14. The interface structure of claim 1 wherein the liquid channel includes a reservoir connecting portion at an opposite end of the liquid channel with respect to the liquid interface, wherein the reservoir connecting portion extends at least partially outside of the profile height, to fluidically connect to the reservoir. 15. The interface structure of claim 1 wherein a central axis of a reservoir connecting liquid channel portion extends at an angle with respect to a central axis of a needle receiving liquid channel portion adjacent the liquid interface, as viewed in a direction of the third dimension. 16-20. (canceled) 21. The interface structure of claim 1 wherein the interface structure includes:
at least one first relatively flat and elongate guide surface that is elongate in a direction along the second dimension, to guide the interface structure along a corresponding guide surface of the receiving station; and
at least one second relatively flat and elongate guide surface, at an angle with the first guide surface, elongate in a direction of the second dimension, the first and second guide surfaces to facilitate guiding in a direction of the second dimension along corresponding guide surfaces of the receiving station, while inhibiting freedom of movement in at least one direction along the first dimension and two opposite directions along the third dimension to facilitate positioning the liquid interface with respect to the needle. 22. (canceled) 23. The interface structure of claim 1 wherein the interface structure includes at least one guide feature extending along the second dimension, at at least one of a lateral side and an external side of the support wall, and wherein the at least one guide feature includes an elongate slot along the second dimension for receiving a corresponding guide rail of the receiving station. 24. (canceled) 25. The interface structure of claim 1 wherein the interface structure includes relatively straight guide surfaces to slide the interface structure along corresponding receiving station surfaces to facilitate aligning the liquid interface to the liquid needle, comprising at least one of (i) at least one lateral guide surface at a respective external lateral side of the interface structure, parallel to the second dimension, to limit a freedom of movement of the interface structure in a direction of the third dimension, and (ii) at least one intermediate guide surface at an external side of the interface structure that extends adjacent the first virtual reference plane, the at least one intermediate guide surface extending parallel to the second dimension and adapted to limit a freedom of movement of the interface structure in a direction of the first dimension. 26-28. (canceled) 29. The interface structure of claim 1 comprising adjacent first and second lateral guide surfaces at straight angles with each other. 30. The interface structure of claim 1 wherein at least one intermediate guide surface is provided in an external side of the support wall of the interface structure, the at least one intermediate guide surface adjacent the liquid interface and channel, the intermediate guide surface to limit the degree of freedom of movement of the interface structure in a direction of the third dimension. 31-33. (canceled) 34. The interface structure of claim 1 comprising a secure feature to facilitate securing the apparatus to a receiving station. 35-48. (canceled) 49. The interface structure of claim 1 comprising two fluidic interfaces, including said liquid interface, and two corresponding channels, including said liquid channel, for receiving two needles of a single receiving station at a single insertion motion. 50. The interface structure of claim 1 wherein the interface structure comprises a protruding key pen protruding along the second dimension from a base to pass through a key hole of the receiving station to actuate upon an actuator, the key pen having an actuating surface area distanced from the base, to engage the actuator. 51-65. (canceled) 66. A print liquid supply apparatus, comprising:
an interface structure according to claim 1, a container including a reservoir, connected to the interface structure, the container having a first, second and third dimension that are parallel to said first, second and third dimension of the interface structure, respectively, the dimensions defining an outer volume of the container, the interface structure projecting outwards with respect to the container over the first dimension. 67. (canceled) 68. The print liquid supply apparatus of claim 66 wherein a projecting portion of the container projects in the main liquid flow direction surpassing the liquid interface. 69. The print liquid supply apparatus of claim 66, wherein interface components of the interface structure that are to interface with the receiving station all extend within a contour defined by the second and third dimension of the container as seen in a view direction parallel to the first dimension of the container, the interface components comprising the liquid interface, the needle receiving portion of the liquid channel, the front push area adjacent the liquid interface, at least one of a key pen, the integrated circuit contact pads, at least one guide feature for guiding the supply apparatus along the second dimension, and a secure feature. 70. The print liquid supply apparatus of claim 66, wherein the container comprises a support structure to support a reservoir, the support structure including an opening in a container wall from which the interface structure projects, to facilitate fluidic connection between the reservoir and the liquid channel of the interface structure. 71-72. (canceled) 73. The print liquid supply apparatus of claim 66, wherein
a liquid reservoir including an at least partly flexible wall relatively impermeable to fluids, the container includes a support structure at least partially around the reservoir, walls of which are relatively permeable to fluids, the interface structure comprises a relatively rigid monolithic plastic structure relatively impermeable to fluids, and the reservoir, support structure and interface structure are separate components. 74. Kit of the components of for construing the interface structure or supply apparatus of claim 66, the kit including at least a fluidic structure, a key pen, a seal and an integrated circuit, the fluidic structure comprising a rigid monolithic fluidic structure that defines at least the liquid channel, to which the key pen, seal and integrated circuit are to be assembled. | 2,800 |
12,167 | 12,167 | 16,317,023 | 2,896 | Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a plurality of gates disposed above the quantum well stack, wherein at least two of the gates are spaced apart in a first dimension above the quantum well stack, at least two of the gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular; and an insulating material disposed above the quantum well stack, wherein the insulating material extends between at least two of the gates spaced apart in the first dimension, and the insulating material extends between at least two of the gates spaced apart in the second dimension. | 1. A quantum dot device, comprising:
a quantum well stack including a quantum well layer; a plurality of gates disposed above the quantum well stack, wherein at least two of the gates are spaced apart in a first dimension above the quantum well stack, at least two of the gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular; and an insulating material disposed above the quantum well stack, wherein the insulating material extends between at least two of the gates spaced apart in the first dimension, and the insulating material extends between at least two of the gates spaced apart in the second dimension. 2. The quantum dot device of claim 1, wherein individual gates of the plurality of gates have a substantially rectangular footprint. 3. The quantum dot device of claim 2, wherein the plurality of gates are distributed in a regular rectangular array. 4. The quantum dot device of claim 1, wherein the plurality of gates are arranged in an n×m array, n is greater than 1, and m is greater than 1. 5. The quantum dot device of claim 1, wherein the insulating material includes a perimeter portion extending around the plurality of gates. 6. The quantum dot device of claim 1, wherein the plurality of gates is a plurality of first gates, the quantum well layer is a first quantum well layer, the quantum well stack includes a second quantum well layer, and the quantum dot device further includes:
a plurality of second gates disposed below the quantum well stack, wherein the second quantum well layer is disposed between the plurality of second gates and the first quantum well layer. 7. The quantum dot device of claim 6, wherein at least two of the second gates are spaced apart in the first dimension below the quantum well stack, and at least two of the second gates are spaced apart in the second dimension below the quantum well stack. 8. The quantum dot device of claim 7, wherein the insulating material is a first insulating material, and the quantum dot device further comprises:
a second insulating material disposed below the quantum well stack, wherein the second insulating material extends between at least two of the second gates spaced apart in the first dimension, and the second insulating material extends between at least two of the second gates spaced apart in the second dimension. 9. The quantum dot device of claim 8, wherein the first insulating material and the second insulating material have a same shape. 10. The quantum dot device of claim 7, wherein an arrangement of the second gates below the quantum well stack is a same arrangement as an arrangement of the first gates above the quantum well stack. 11. The quantum dot device of claim 6, further comprising:
first and second conductive pathways that conductively contact the first quantum well layer; and third and fourth conductive pathways that conductively contact the second quantum well layer. 12. The quantum dot device of claim 1, wherein adjacent ones of the gates are spaced apart by a distance of 100 nanometers or less. 13. The quantum dot device of claim 1, wherein the plurality of gates includes:
a first gate having a first length, two second gates arranged such that the first gate is disposed between the second gates, wherein the second gates have a second length different from the first length, and two third gates arranged such that the second gates are disposed between the third gates, wherein the third gates have a third length different from the first length and different from the second length. 14-17. (canceled) 18. A method of manufacturing a quantum dot device, comprising:
providing a quantum well stack; forming a patterned insulating material above the quantum well stack, wherein the patterned insulating material includes at least two openings spaced apart in a first dimension and at least two openings spaced apart in a second dimension perpendicular to the first dimension; and forming a plurality of gates above the quantum well stack, wherein individual ones of the gates are at least partially disposed in corresponding individual ones of the openings. 19. The method of claim 18, wherein the patterned insulating material and the plurality of gates are formed above a first face of the quantum well stack, and the method further comprises:
forming another set of gates above a second face of the quantum well stack, wherein the second face of the quantum well stack is opposite to the first face of the quantum well stack. 20. The method of claim 18, wherein forming the patterned insulating material includes:
providing an unpatterned insulating material; providing a first hardmask above the unpatterned insulating material; forming a first plurality of parallel trenches oriented in a first direction in the first hardmask; providing a second hardmask above the unpatterned insulating material; forming a second plurality of parallel trenches oriented in a second direction in the first hardmask, wherein the second direction is perpendicular to the first direction; and patterning the unpatterned insulating material to form the patterned insulating material by removing the unpatterned insulating material in areas in which the first plurality of trenches and the second plurality of trenches overlap. 21. (canceled) 22. A quantum computing device, comprising:
a quantum processing device, wherein the quantum processing device includes an active quantum well layer and a read quantum well layer, a first set of gates to control formation of quantum dots in the active quantum well layer, and a second set of gates to control formation of quantum dots in the read quantum well layer, and wherein the first set of gates includes at least three first gates and an insulating material extending between at least two different pairs of first gates; a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the first set of gates and the second set of gates; and a memory device to store data generated by the read quantum well layer during operation of the quantum processing device. 23. The quantum computing device of claim 22, further comprising:
a cooling apparatus to maintain a temperature of the quantum processing device below 5 degrees Kelvin. 24. The quantum computing device of claim 22, wherein the first set of gates and the second set of gates each include a plurality of gates arranged in a two-dimensional array. 25. The quantum computing device of claim 22, wherein the insulating material has a region shaped as a grid. | Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a plurality of gates disposed above the quantum well stack, wherein at least two of the gates are spaced apart in a first dimension above the quantum well stack, at least two of the gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular; and an insulating material disposed above the quantum well stack, wherein the insulating material extends between at least two of the gates spaced apart in the first dimension, and the insulating material extends between at least two of the gates spaced apart in the second dimension.1. A quantum dot device, comprising:
a quantum well stack including a quantum well layer; a plurality of gates disposed above the quantum well stack, wherein at least two of the gates are spaced apart in a first dimension above the quantum well stack, at least two of the gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular; and an insulating material disposed above the quantum well stack, wherein the insulating material extends between at least two of the gates spaced apart in the first dimension, and the insulating material extends between at least two of the gates spaced apart in the second dimension. 2. The quantum dot device of claim 1, wherein individual gates of the plurality of gates have a substantially rectangular footprint. 3. The quantum dot device of claim 2, wherein the plurality of gates are distributed in a regular rectangular array. 4. The quantum dot device of claim 1, wherein the plurality of gates are arranged in an n×m array, n is greater than 1, and m is greater than 1. 5. The quantum dot device of claim 1, wherein the insulating material includes a perimeter portion extending around the plurality of gates. 6. The quantum dot device of claim 1, wherein the plurality of gates is a plurality of first gates, the quantum well layer is a first quantum well layer, the quantum well stack includes a second quantum well layer, and the quantum dot device further includes:
a plurality of second gates disposed below the quantum well stack, wherein the second quantum well layer is disposed between the plurality of second gates and the first quantum well layer. 7. The quantum dot device of claim 6, wherein at least two of the second gates are spaced apart in the first dimension below the quantum well stack, and at least two of the second gates are spaced apart in the second dimension below the quantum well stack. 8. The quantum dot device of claim 7, wherein the insulating material is a first insulating material, and the quantum dot device further comprises:
a second insulating material disposed below the quantum well stack, wherein the second insulating material extends between at least two of the second gates spaced apart in the first dimension, and the second insulating material extends between at least two of the second gates spaced apart in the second dimension. 9. The quantum dot device of claim 8, wherein the first insulating material and the second insulating material have a same shape. 10. The quantum dot device of claim 7, wherein an arrangement of the second gates below the quantum well stack is a same arrangement as an arrangement of the first gates above the quantum well stack. 11. The quantum dot device of claim 6, further comprising:
first and second conductive pathways that conductively contact the first quantum well layer; and third and fourth conductive pathways that conductively contact the second quantum well layer. 12. The quantum dot device of claim 1, wherein adjacent ones of the gates are spaced apart by a distance of 100 nanometers or less. 13. The quantum dot device of claim 1, wherein the plurality of gates includes:
a first gate having a first length, two second gates arranged such that the first gate is disposed between the second gates, wherein the second gates have a second length different from the first length, and two third gates arranged such that the second gates are disposed between the third gates, wherein the third gates have a third length different from the first length and different from the second length. 14-17. (canceled) 18. A method of manufacturing a quantum dot device, comprising:
providing a quantum well stack; forming a patterned insulating material above the quantum well stack, wherein the patterned insulating material includes at least two openings spaced apart in a first dimension and at least two openings spaced apart in a second dimension perpendicular to the first dimension; and forming a plurality of gates above the quantum well stack, wherein individual ones of the gates are at least partially disposed in corresponding individual ones of the openings. 19. The method of claim 18, wherein the patterned insulating material and the plurality of gates are formed above a first face of the quantum well stack, and the method further comprises:
forming another set of gates above a second face of the quantum well stack, wherein the second face of the quantum well stack is opposite to the first face of the quantum well stack. 20. The method of claim 18, wherein forming the patterned insulating material includes:
providing an unpatterned insulating material; providing a first hardmask above the unpatterned insulating material; forming a first plurality of parallel trenches oriented in a first direction in the first hardmask; providing a second hardmask above the unpatterned insulating material; forming a second plurality of parallel trenches oriented in a second direction in the first hardmask, wherein the second direction is perpendicular to the first direction; and patterning the unpatterned insulating material to form the patterned insulating material by removing the unpatterned insulating material in areas in which the first plurality of trenches and the second plurality of trenches overlap. 21. (canceled) 22. A quantum computing device, comprising:
a quantum processing device, wherein the quantum processing device includes an active quantum well layer and a read quantum well layer, a first set of gates to control formation of quantum dots in the active quantum well layer, and a second set of gates to control formation of quantum dots in the read quantum well layer, and wherein the first set of gates includes at least three first gates and an insulating material extending between at least two different pairs of first gates; a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the first set of gates and the second set of gates; and a memory device to store data generated by the read quantum well layer during operation of the quantum processing device. 23. The quantum computing device of claim 22, further comprising:
a cooling apparatus to maintain a temperature of the quantum processing device below 5 degrees Kelvin. 24. The quantum computing device of claim 22, wherein the first set of gates and the second set of gates each include a plurality of gates arranged in a two-dimensional array. 25. The quantum computing device of claim 22, wherein the insulating material has a region shaped as a grid. | 2,800 |
12,168 | 12,168 | 16,161,117 | 2,843 | A high-frequency module includes a plurality of filters, a switch that commonly connects a plurality of paths, and a low noise amplifier that amplifies a high-frequency signal input from the plurality of filters with the switch interposed therebetween, wherein paths in which first and second filters are respectively provided among the plurality of paths connect the respective filters and the switch without connecting impedance elements, and each of the first and second filters has an output impedance located in a matching region between a NF matching impedance at which an NF of the low noise amplifier is minimum and a gain matching impedance at which a gain of the low noise amplifier is maximum in its respective pass band thereof on a Smith chart. | 1. A high-frequency module comprising:
a filter; a connection circuit that connects a path in which the filter is provided; and a low noise amplifier that is connected to the connection circuit; wherein the connection circuit is connected between the filter and the low noise amplifier; in the path in which the filter is provided, the filter and the connection circuit are connected without connecting impedance elements; the filter has an output impedance located in a matching region between a noise figure matching impedance at which a noise figure of the low noise amplifier is minimum and a gain matching impedance at which a gain of the low noise amplifier is maximum in the pass band of the filter on a Smith chart. 2. The high-frequency module according to claim 1, further comprising a first impedance adjustment circuit that is connected between the connection circuit and the low noise amplifier, wherein
the first impedance adjustment circuit adjusts a first impedance when a circuit portion in which the first impedance adjustment circuit is connected to the low noise amplifier is seen from an output side of the filter in a case in which the noise figure is minimum and the gain is maximum at respective frequency bands. 3. The high-frequency module according to claim 2, wherein the first impedance adjustment circuit adjusts the first impedance to be any one of inductive or capacitive in the pass band of the filter in the case in which the noise figure is minimum and the gain is maximum. 4. The high-frequency module according to claim 3, wherein
the filter has the output impedance with a capacitive property in the pass band of the filter; and the first impedance adjustment circuit adjusts the first impedance to be inductive in the pass band of the filter in the case in which the noise figure is minimum and the gain is maximum. 5. The high-frequency module according to claim 1, wherein the connection circuit includes a switch connected to the low noise amplifier. 6. The high-frequency module according to claim 1, wherein the filter includes an elastic wave resonator using surface acoustic waves, bulk waves, or boundary acoustic waves. 7. A communication apparatus comprising:
an RF signal processing circuit that processes a high-frequency signal which is transmitted or received with an antenna element; and the high-frequency module according to claim 1 transmits or receives the high-frequency signal between the antenna element and the RF signal processing circuit. 8. The communication apparatus according to claim 7, further comprising:
a first impedance adjustment circuit that is connected between the connection circuit and the low noise amplifier; wherein the first impedance adjustment circuit adjusts a first impedance when a circuit portion in which the first impedance adjustment circuit is connected to the low noise amplifier is seen from an output side of the filter in a case in which the noise figure is minimum and the gain is maximum at a respective frequency band 9. The communication apparatus according to claim 8, wherein the first impedance adjustment circuit adjusts the first impedance to be any one of inductive or capacitive in the pass band of the filter in the case in which the noise figure is minimum and the gain is maximum. | A high-frequency module includes a plurality of filters, a switch that commonly connects a plurality of paths, and a low noise amplifier that amplifies a high-frequency signal input from the plurality of filters with the switch interposed therebetween, wherein paths in which first and second filters are respectively provided among the plurality of paths connect the respective filters and the switch without connecting impedance elements, and each of the first and second filters has an output impedance located in a matching region between a NF matching impedance at which an NF of the low noise amplifier is minimum and a gain matching impedance at which a gain of the low noise amplifier is maximum in its respective pass band thereof on a Smith chart.1. A high-frequency module comprising:
a filter; a connection circuit that connects a path in which the filter is provided; and a low noise amplifier that is connected to the connection circuit; wherein the connection circuit is connected between the filter and the low noise amplifier; in the path in which the filter is provided, the filter and the connection circuit are connected without connecting impedance elements; the filter has an output impedance located in a matching region between a noise figure matching impedance at which a noise figure of the low noise amplifier is minimum and a gain matching impedance at which a gain of the low noise amplifier is maximum in the pass band of the filter on a Smith chart. 2. The high-frequency module according to claim 1, further comprising a first impedance adjustment circuit that is connected between the connection circuit and the low noise amplifier, wherein
the first impedance adjustment circuit adjusts a first impedance when a circuit portion in which the first impedance adjustment circuit is connected to the low noise amplifier is seen from an output side of the filter in a case in which the noise figure is minimum and the gain is maximum at respective frequency bands. 3. The high-frequency module according to claim 2, wherein the first impedance adjustment circuit adjusts the first impedance to be any one of inductive or capacitive in the pass band of the filter in the case in which the noise figure is minimum and the gain is maximum. 4. The high-frequency module according to claim 3, wherein
the filter has the output impedance with a capacitive property in the pass band of the filter; and the first impedance adjustment circuit adjusts the first impedance to be inductive in the pass band of the filter in the case in which the noise figure is minimum and the gain is maximum. 5. The high-frequency module according to claim 1, wherein the connection circuit includes a switch connected to the low noise amplifier. 6. The high-frequency module according to claim 1, wherein the filter includes an elastic wave resonator using surface acoustic waves, bulk waves, or boundary acoustic waves. 7. A communication apparatus comprising:
an RF signal processing circuit that processes a high-frequency signal which is transmitted or received with an antenna element; and the high-frequency module according to claim 1 transmits or receives the high-frequency signal between the antenna element and the RF signal processing circuit. 8. The communication apparatus according to claim 7, further comprising:
a first impedance adjustment circuit that is connected between the connection circuit and the low noise amplifier; wherein the first impedance adjustment circuit adjusts a first impedance when a circuit portion in which the first impedance adjustment circuit is connected to the low noise amplifier is seen from an output side of the filter in a case in which the noise figure is minimum and the gain is maximum at a respective frequency band 9. The communication apparatus according to claim 8, wherein the first impedance adjustment circuit adjusts the first impedance to be any one of inductive or capacitive in the pass band of the filter in the case in which the noise figure is minimum and the gain is maximum. | 2,800 |
12,169 | 12,169 | 15,570,634 | 2,853 | A fluid recirculation channel for dispensing a plurality of fluid drop weights includes a number of sub-channels. The sub-channels include at least one pump channel, and a plurality of drop generator channels fluidically coupled to the at least one pump channel. The fluid recirculation channel further includes a number of pump generators incorporated into the at least one pump channel, a number of drop generators incorporated into drop generator channels, and a plurality of nozzles defined within the drop generator channels, the nozzles being at least as numerous as the number of drop generators. | 1. A fluid recirculation channel for dispensing a plurality of fluid drop weights comprising:
a number of sub-channels comprising:
at least one pump channel; and
a plurality of drop generator channels fluidically coupled to the at least one pump channel;
a number of pump generators incorporated into the at least one pump channel; a number of drop generators incorporated into drop generator channels; and a plurality of nozzles defined within the drop generator channels, the nozzles being at least as numerous as the number of drop generators; wherein the nozzles comprise at least two different nozzles that emit at least two different drop weights of fluid, the two different drop weights comprising a first drop weight and a second drop weight, the second drop weight comprising a drop weight that is relatively higher than the first drop weight. 2. The fluid recirculation channel of claim 1, wherein the fluid recirculation channel comprises an N:1 drop generator to pump ratio, wherein N is at least 1. 3. The fluid recirculation channel of claim 2, wherein N is at least 2. 4. The fluid recirculation channel of claim 1, wherein the number of pumps is defined by the number of pump channels within the fluid recirculation channel. 5. The fluid recirculation channel of claim 1, wherein the number of drop generators is defined by the number of drop generator channels within the fluid recirculation channel. 6. A fluid ejection assembly comprising:
a fluid slot; a number of fluid recirculation channels fluidically coupled to the fluid slot, each fluid recirculation channel comprising:
at least one pump channel fluidically coupled to the fluid slot; and
a plurality of drop generator channels fluidically coupled to the at least one pump channel via a number of connection channels on a first end and fluidically coupled to the fluid slot on a second end;
at least one pump disposed within the at least one pump channel, wherein the at least one pump circulates fluid from the fluid slot, and throughout the pump channel and the drop generator channels;
a number of drop generators disposed within each of the drop generator channels; and
a plurality of nozzles defined within the drop generator channels. 7. The fluid recirculation channel of claim 6, wherein the nozzles comprise at least two different nozzles that emit at least two different drop weights of fluid, the two different drop weights comprising a first drop weight and a second drop weight, the second drop weight comprising a drop weight that is relatively higher than the first drop weight. 8. The fluid recirculation channel of claim 6, wherein the nozzles comprise at least two different nozzles that emit approximately the same drop weights of fluid. 9. The fluid recirculation channel of claim 7, wherein the nozzles are aligned across the fluid slot to create an effectual nozzle density higher than the physical nozzle density within the fluid ejection assembly. 10. A fluid ejection device comprising:
a fluid ejection array comprising:
a number of fluid ejection assemblies, each fluid ejection assembly comprising:
a number of fluid recirculation channels for dispensing a fluid, each fluid recirculation channel comprising:
at least one pump channel;
a number of drop generator channels fluidically coupled to the at least one pump channel;
a number of pumps incorporated into the at least one pump channel;
a number of drop generators incorporated into drop generator channels; and
a plurality of nozzles defined within the drop generator channels, the nozzles comprising at least two different nozzles that emit at least two different drop weights of fluid, the two different drop weights comprising a first drop weight and a second drop weight, the second drop weight comprising a drop weight that is relatively higher than the first drop weight; and;
a controller to activate the pumps to generate fluid displacements within the recirculation channel to drive the fluid flow within the fluid recirculation channels. 11. The fluid ejection device of claim 10, wherein the controller activates the pumps as defined by a recirculation timing profile. 12. The fluid ejection device of claim 10, wherein the controller activates the pumps during idle time of the drop generators within a first one of the fluid recirculation channels, during active operation of the drop generators within the fluid recirculation channels, or combinations thereof. 13. The fluid ejection device of claim 10, wherein the controller activates the pumps using a number of different modes of pump pulses comprising modes of pump pulses driven based on drop generator idle times, modes of pump pulses driven based on a fixed time interval, modes of pump pulses driven based on firing of the drop generators, or combinations thereof. 14. The fluid ejection device of claim 10, wherein a plurality of fluid recirculation channels are included within each of the fluid ejection assemblies, the plurality of fluid recirculation channels being arranged on different sides of a fluid slot of the printhead such that a number of conditions are met, the conditions comprising:
a first nozzle on a first side of the slot emits the first drop weight of fluid and a second nozzle aligned with the first nozzle on a second side of the slot emits the second drop weight of fluid; the second nozzle on the first side of the slot emits the first drop weight of fluid and the first nozzle aligned with the second nozzle on the second side of the slot emits the second drop weight of fluid; the first nozzle on the first side of the slot is aligned with a pump on the second side of the slot, wherein the first nozzle emits the second drop weight; the second nozzle on the second side of the slot is aligned with a pump on the second side of the slot, wherein the second nozzle emits the second drop weight; or combinations thereof. 15. The fluid ejection device of claim 10, wherein
a plurality of the fluid ejection assemblies are included within the fluid ejection device, the plurality of printheads being aligned such that the first nozzle and the second nozzle located on a first fluid ejection assembly emit a first collective drop weight of fluid different from a second collective drop weight of fluid emitted by a third nozzle and a fourth nozzle located on a second fluid ejection assembly. | A fluid recirculation channel for dispensing a plurality of fluid drop weights includes a number of sub-channels. The sub-channels include at least one pump channel, and a plurality of drop generator channels fluidically coupled to the at least one pump channel. The fluid recirculation channel further includes a number of pump generators incorporated into the at least one pump channel, a number of drop generators incorporated into drop generator channels, and a plurality of nozzles defined within the drop generator channels, the nozzles being at least as numerous as the number of drop generators.1. A fluid recirculation channel for dispensing a plurality of fluid drop weights comprising:
a number of sub-channels comprising:
at least one pump channel; and
a plurality of drop generator channels fluidically coupled to the at least one pump channel;
a number of pump generators incorporated into the at least one pump channel; a number of drop generators incorporated into drop generator channels; and a plurality of nozzles defined within the drop generator channels, the nozzles being at least as numerous as the number of drop generators; wherein the nozzles comprise at least two different nozzles that emit at least two different drop weights of fluid, the two different drop weights comprising a first drop weight and a second drop weight, the second drop weight comprising a drop weight that is relatively higher than the first drop weight. 2. The fluid recirculation channel of claim 1, wherein the fluid recirculation channel comprises an N:1 drop generator to pump ratio, wherein N is at least 1. 3. The fluid recirculation channel of claim 2, wherein N is at least 2. 4. The fluid recirculation channel of claim 1, wherein the number of pumps is defined by the number of pump channels within the fluid recirculation channel. 5. The fluid recirculation channel of claim 1, wherein the number of drop generators is defined by the number of drop generator channels within the fluid recirculation channel. 6. A fluid ejection assembly comprising:
a fluid slot; a number of fluid recirculation channels fluidically coupled to the fluid slot, each fluid recirculation channel comprising:
at least one pump channel fluidically coupled to the fluid slot; and
a plurality of drop generator channels fluidically coupled to the at least one pump channel via a number of connection channels on a first end and fluidically coupled to the fluid slot on a second end;
at least one pump disposed within the at least one pump channel, wherein the at least one pump circulates fluid from the fluid slot, and throughout the pump channel and the drop generator channels;
a number of drop generators disposed within each of the drop generator channels; and
a plurality of nozzles defined within the drop generator channels. 7. The fluid recirculation channel of claim 6, wherein the nozzles comprise at least two different nozzles that emit at least two different drop weights of fluid, the two different drop weights comprising a first drop weight and a second drop weight, the second drop weight comprising a drop weight that is relatively higher than the first drop weight. 8. The fluid recirculation channel of claim 6, wherein the nozzles comprise at least two different nozzles that emit approximately the same drop weights of fluid. 9. The fluid recirculation channel of claim 7, wherein the nozzles are aligned across the fluid slot to create an effectual nozzle density higher than the physical nozzle density within the fluid ejection assembly. 10. A fluid ejection device comprising:
a fluid ejection array comprising:
a number of fluid ejection assemblies, each fluid ejection assembly comprising:
a number of fluid recirculation channels for dispensing a fluid, each fluid recirculation channel comprising:
at least one pump channel;
a number of drop generator channels fluidically coupled to the at least one pump channel;
a number of pumps incorporated into the at least one pump channel;
a number of drop generators incorporated into drop generator channels; and
a plurality of nozzles defined within the drop generator channels, the nozzles comprising at least two different nozzles that emit at least two different drop weights of fluid, the two different drop weights comprising a first drop weight and a second drop weight, the second drop weight comprising a drop weight that is relatively higher than the first drop weight; and;
a controller to activate the pumps to generate fluid displacements within the recirculation channel to drive the fluid flow within the fluid recirculation channels. 11. The fluid ejection device of claim 10, wherein the controller activates the pumps as defined by a recirculation timing profile. 12. The fluid ejection device of claim 10, wherein the controller activates the pumps during idle time of the drop generators within a first one of the fluid recirculation channels, during active operation of the drop generators within the fluid recirculation channels, or combinations thereof. 13. The fluid ejection device of claim 10, wherein the controller activates the pumps using a number of different modes of pump pulses comprising modes of pump pulses driven based on drop generator idle times, modes of pump pulses driven based on a fixed time interval, modes of pump pulses driven based on firing of the drop generators, or combinations thereof. 14. The fluid ejection device of claim 10, wherein a plurality of fluid recirculation channels are included within each of the fluid ejection assemblies, the plurality of fluid recirculation channels being arranged on different sides of a fluid slot of the printhead such that a number of conditions are met, the conditions comprising:
a first nozzle on a first side of the slot emits the first drop weight of fluid and a second nozzle aligned with the first nozzle on a second side of the slot emits the second drop weight of fluid; the second nozzle on the first side of the slot emits the first drop weight of fluid and the first nozzle aligned with the second nozzle on the second side of the slot emits the second drop weight of fluid; the first nozzle on the first side of the slot is aligned with a pump on the second side of the slot, wherein the first nozzle emits the second drop weight; the second nozzle on the second side of the slot is aligned with a pump on the second side of the slot, wherein the second nozzle emits the second drop weight; or combinations thereof. 15. The fluid ejection device of claim 10, wherein
a plurality of the fluid ejection assemblies are included within the fluid ejection device, the plurality of printheads being aligned such that the first nozzle and the second nozzle located on a first fluid ejection assembly emit a first collective drop weight of fluid different from a second collective drop weight of fluid emitted by a third nozzle and a fourth nozzle located on a second fluid ejection assembly. | 2,800 |
12,170 | 12,170 | 16,462,111 | 2,865 | The present invention provides a computer-implemented method for detecting at least one natural contour of a geologic object in 3D seismic data, the method comprising the steps of: (a) receiving at least one first predetermined data set from said 3D seismic data comprising a plurality of phase events; (b) selecting at least one first seed phase event having a first phase characteristic from said plurality of phase events; (c) determine a characterising score between said selected at least one first seed phase event and each one of a predetermined number of candidate phase events of said at least one first predetermined data set; (d) assign said characterising score to each one of said predetermined number of candidate phase events; (e) adjust said characterising score of at least one of said predetermined number of candidate phase events in accordance with at least one first boundary condition; (f) determine at least one natural contour between said at least one first seed phase event and at least a second phase event, utilising an optimisation algorithm; (g) generate a visual representation of said at least one natural contour within said at least one first predetermined data set. | 1. A computer-implemented method for detecting at least one natural contour of a geologic object in 3D seismic data, the method comprising the steps of:
(a) receiving at least one first predetermined data set from said 3D seismic data comprising a plurality of phase events; (b) selecting at least one first seed phase event having a first phase characteristic from said plurality of phase events; (c) determining a characterising score between said selected at least one first seed phase event and each one of a predetermined number of candidate phase events of said at least one first predetermined data set; (d) assigning said characterising score to each one of said predetermined number of candidate phase events; (e) adjusting said characterising score of at least one of said predetermined number of candidate phase events in accordance with at least one first boundary condition; (f) determining at least one natural contour between said at least one first seed phase event and at least a second phase event, utilising an optimisation algorithm; and (g) generating a visual representation of said at least one natural contour within said at least one first predetermined data set;
wherein, when said at least one first predetermined data set comprises a 3D volume data set, said optimisation algorithm is a Markov Random Field optimisation. 2. (canceled) 3. A method according to claim 1, wherein said at least one first boundary condition comprises at least one geologic constraint and/or at least one stratigraphic constraint and/or at least one algorithmic optimisation constraint in accordance with at least one variable of said at least one candidate phase event. 4. A method according to claim 3, wherein said at least one variable is any one or any combination of (i) a relative position of said at least one candidate phase event with respect to any other one of said predetermined number of candidate phase events and/or a predetermined geological object, (ii) an angular inclination of said at least one first natural contour with respect to said 3D seismic data, (iii) said characterising score of said at least one candidate event, and (iv) a characterising score projected from at least one second predetermined data set from said 3D seismic data. 5. A method according to claim 4, wherein said at least one second predetermined data set comprises any one of a 2D in-line slice data set, a 2D cross-line slice data set, or a 3D volume data set that is sequentially arranged to respective said at least one first data set within said 3D seismic data. 6. A method according to claim 3, wherein said at least one algorithmic optimisation constraint comprises at least one hard constraint and/or at least one soft constraint. 7. A method according to claim 1, wherein each one of said predetermined number of candidate phase events is eligible in accordance with at least one algorithmic condition. 8. A method according to claim 7, wherein said algorithmic condition is a Degree of Freedom (DOF) for movement from one phase event to another. 9. A method according to claim 1, wherein said first phase characteristic is any one of a peak-positive amplitude, a trough-negative amplitude or a zero-crossing. 10. A method according to claim 1, wherein said at least one natural contour in step (f) includes a first natural contour, that is an optimum solution provided by said optimisation algorithm, and at least one alternate natural contour, that is an alternate solution provided by said optimisation algorithm. 11. A method according to claim 1, wherein said at least one second phase event is a second seed phase event selected by the user. 12. A method according to claim 11, wherein said step (c) includes determining said characterising score between said selected at least one first and second seed phase event and each one of said predetermined number of candidate phase events of said at least one first predetermined data set. 13. A method according to claim 1, wherein said at least one second phase event is a candidate phase event determined in accordance with its location and/or characterising score within said at least one first predetermined data set. 14. A method according to claim 1, wherein step (c) includes utilising characteristic information from a predetermined number of phase events proximate to respective each one of said predetermined number of candidate phase events. 15. A method according to claim 1, wherein said characterising score is a similarity score. 16. A method according to claim 15, wherein said similarity score is based on at least one attribute derivable from said at least one candidate phase events. 17. (canceled) 18. (canceled) 19. A method according to claim 1, wherein said geological object is any one of at least one horizon feature and at least one fault feature. 20. A computer system for detecting at least one natural contour of a geologic object in 3D seismic data by a method according to claim 1. 21. A computer-readable storage medium having embodied thereon a computer program, when executed by a computer processor that is configured to perform the method of claim 1. | The present invention provides a computer-implemented method for detecting at least one natural contour of a geologic object in 3D seismic data, the method comprising the steps of: (a) receiving at least one first predetermined data set from said 3D seismic data comprising a plurality of phase events; (b) selecting at least one first seed phase event having a first phase characteristic from said plurality of phase events; (c) determine a characterising score between said selected at least one first seed phase event and each one of a predetermined number of candidate phase events of said at least one first predetermined data set; (d) assign said characterising score to each one of said predetermined number of candidate phase events; (e) adjust said characterising score of at least one of said predetermined number of candidate phase events in accordance with at least one first boundary condition; (f) determine at least one natural contour between said at least one first seed phase event and at least a second phase event, utilising an optimisation algorithm; (g) generate a visual representation of said at least one natural contour within said at least one first predetermined data set.1. A computer-implemented method for detecting at least one natural contour of a geologic object in 3D seismic data, the method comprising the steps of:
(a) receiving at least one first predetermined data set from said 3D seismic data comprising a plurality of phase events; (b) selecting at least one first seed phase event having a first phase characteristic from said plurality of phase events; (c) determining a characterising score between said selected at least one first seed phase event and each one of a predetermined number of candidate phase events of said at least one first predetermined data set; (d) assigning said characterising score to each one of said predetermined number of candidate phase events; (e) adjusting said characterising score of at least one of said predetermined number of candidate phase events in accordance with at least one first boundary condition; (f) determining at least one natural contour between said at least one first seed phase event and at least a second phase event, utilising an optimisation algorithm; and (g) generating a visual representation of said at least one natural contour within said at least one first predetermined data set;
wherein, when said at least one first predetermined data set comprises a 3D volume data set, said optimisation algorithm is a Markov Random Field optimisation. 2. (canceled) 3. A method according to claim 1, wherein said at least one first boundary condition comprises at least one geologic constraint and/or at least one stratigraphic constraint and/or at least one algorithmic optimisation constraint in accordance with at least one variable of said at least one candidate phase event. 4. A method according to claim 3, wherein said at least one variable is any one or any combination of (i) a relative position of said at least one candidate phase event with respect to any other one of said predetermined number of candidate phase events and/or a predetermined geological object, (ii) an angular inclination of said at least one first natural contour with respect to said 3D seismic data, (iii) said characterising score of said at least one candidate event, and (iv) a characterising score projected from at least one second predetermined data set from said 3D seismic data. 5. A method according to claim 4, wherein said at least one second predetermined data set comprises any one of a 2D in-line slice data set, a 2D cross-line slice data set, or a 3D volume data set that is sequentially arranged to respective said at least one first data set within said 3D seismic data. 6. A method according to claim 3, wherein said at least one algorithmic optimisation constraint comprises at least one hard constraint and/or at least one soft constraint. 7. A method according to claim 1, wherein each one of said predetermined number of candidate phase events is eligible in accordance with at least one algorithmic condition. 8. A method according to claim 7, wherein said algorithmic condition is a Degree of Freedom (DOF) for movement from one phase event to another. 9. A method according to claim 1, wherein said first phase characteristic is any one of a peak-positive amplitude, a trough-negative amplitude or a zero-crossing. 10. A method according to claim 1, wherein said at least one natural contour in step (f) includes a first natural contour, that is an optimum solution provided by said optimisation algorithm, and at least one alternate natural contour, that is an alternate solution provided by said optimisation algorithm. 11. A method according to claim 1, wherein said at least one second phase event is a second seed phase event selected by the user. 12. A method according to claim 11, wherein said step (c) includes determining said characterising score between said selected at least one first and second seed phase event and each one of said predetermined number of candidate phase events of said at least one first predetermined data set. 13. A method according to claim 1, wherein said at least one second phase event is a candidate phase event determined in accordance with its location and/or characterising score within said at least one first predetermined data set. 14. A method according to claim 1, wherein step (c) includes utilising characteristic information from a predetermined number of phase events proximate to respective each one of said predetermined number of candidate phase events. 15. A method according to claim 1, wherein said characterising score is a similarity score. 16. A method according to claim 15, wherein said similarity score is based on at least one attribute derivable from said at least one candidate phase events. 17. (canceled) 18. (canceled) 19. A method according to claim 1, wherein said geological object is any one of at least one horizon feature and at least one fault feature. 20. A computer system for detecting at least one natural contour of a geologic object in 3D seismic data by a method according to claim 1. 21. A computer-readable storage medium having embodied thereon a computer program, when executed by a computer processor that is configured to perform the method of claim 1. | 2,800 |
12,171 | 12,171 | 15,755,207 | 2,848 | A system includes a curved circuit board with at least one electronic component mounted on the circuit board and electrically connected to a first electrically conductive trace of the circuit board. The system includes an electrically conductive curved fence conformably attached to the circuit board and surrounding the at least one electronic component. The fence is electrically connected to a different second electrically conductive trace of the circuit board. The system further includes an electrically conductive lid conformably attached to a top side of the fence. The electrically conductive lid covers the at least one electronic component. The fence comprises a plurality of spaced apart first tabs arranged along at least a first portion of a perimeter of the fence. Each first tab has a free end and is attached to the electrically conductive lid or the circuit board. | 1-10 (canceled) 11. A system comprising:
a curved circuit board; at least one electronic component mounted on the circuit board and electrically connected to a first electrically conductive trace of the circuit board; an electrically conductive curved fence conformably attached to the circuit board and surrounding the at least one electronic component, the fence electrically connected to a different second electrically conductive trace of the circuit board; and an electrically conductive lid conformably attached to a top side of the fence and covering the at least one electronic component, wherein the fence comprises a plurality of spaced apart first tabs arranged along at least a first portion of a perimeter of the fence, each first tab having a free end and attached to the electrically conductive lid or the circuit board. 12. The system of claim 11, wherein the curved circuit board is rigid. 13. The system of claim 11, wherein the curved circuit board has a shape of a partial cylinder. 14. The system of claim 11 comprising a plurality of electronic components mounted on the circuit board, surrounded by the electrically conductive curved fence, and covered by the electrically conductive lid. 15. The system of claim 11, wherein each first tab comprises:
a horizontal portion substantially parallel to the circuit board; a vertical portion substantially perpendicular to the circuit board; and an elbow portion joining the horizontal portion to the vertical portion, the horizontal portion of the tab attached to the electrically conductive lid or the circuit board. 16. The system of claim 15, wherein the horizontal portion terminates at the free end of the tab. 17. The system of claim 15, wherein the vertical portion terminates at the free end of the tab. 18. The system of claim 15, wherein one of the horizontal and vertical portions of each tab is attached to the electrically conductive lid and the other of the horizontal and vertical portions of the tab is attached to the circuit board. 19. The system of claim 11, wherein the curved fence comprises an elongated continuous portion extending continuously along the first portion of the perimeter of the curved fence parallel to the circuit board, each first tab extending from the continuous horizontal portion of the fence, such that one of the elongated continuous portion of the fence and the plurality of first tabs is attached to the electrically conductive lid and the other of the elongated continuous portion of the fence and the plurality of first tabs is attached to the circuit board. 20. The system of claim 11, wherein each first tab comprises:
a top horizontal portion substantially parallel to the circuit board; a bottom horizontal portion substantially parallel to the circuit board; and a vertical portion joining the top and bottom horizontal portions and substantially perpendicular to the circuit board, the top horizontal portion attached to the electrically conductive lid and the bottom horizontal portion attached to the circuit board. 21. The system of claim 11, wherein the fence further comprises a plurality of spaced apart second tabs arranged along a different second portion of the perimeter of the fence, each second tab terminating at a free end, the first tabs being narrower than the second tabs. 22. The system of claim 21, wherein the perimeter of the fence is a polygon having a plurality of sides, wherein the plurality of spaced apart first tabs are arranged along one side of the perimeter, and the plurality of spaced apart second tabs are arranged along an adjacent side of the perimeter. 23. A flexible rectangular metal fence for conformably mounting on a curved circuit board and surrounding an electronic component mounted on the circuit board, the fence comprising opposing parallel first sides and opposing parallel second sides, wherein each first side comprises a plurality of spaced apart narrower first tabs and each second side comprises a plurality of spaced apart wider second tabs, each first and second tab having a free end. 24. The flexible rectangular metal fence of claim 23, wherein at least one of the first and second sides is generally L-shaped. 25. The flexible rectangular metal fence of claim 23, wherein each of the first and second sides is generally L-shaped. 26. The flexible rectangular metal fence of claim 23, wherein the first sides are generally S-shaped and the second sides are generally L-shaped. | A system includes a curved circuit board with at least one electronic component mounted on the circuit board and electrically connected to a first electrically conductive trace of the circuit board. The system includes an electrically conductive curved fence conformably attached to the circuit board and surrounding the at least one electronic component. The fence is electrically connected to a different second electrically conductive trace of the circuit board. The system further includes an electrically conductive lid conformably attached to a top side of the fence. The electrically conductive lid covers the at least one electronic component. The fence comprises a plurality of spaced apart first tabs arranged along at least a first portion of a perimeter of the fence. Each first tab has a free end and is attached to the electrically conductive lid or the circuit board.1-10 (canceled) 11. A system comprising:
a curved circuit board; at least one electronic component mounted on the circuit board and electrically connected to a first electrically conductive trace of the circuit board; an electrically conductive curved fence conformably attached to the circuit board and surrounding the at least one electronic component, the fence electrically connected to a different second electrically conductive trace of the circuit board; and an electrically conductive lid conformably attached to a top side of the fence and covering the at least one electronic component, wherein the fence comprises a plurality of spaced apart first tabs arranged along at least a first portion of a perimeter of the fence, each first tab having a free end and attached to the electrically conductive lid or the circuit board. 12. The system of claim 11, wherein the curved circuit board is rigid. 13. The system of claim 11, wherein the curved circuit board has a shape of a partial cylinder. 14. The system of claim 11 comprising a plurality of electronic components mounted on the circuit board, surrounded by the electrically conductive curved fence, and covered by the electrically conductive lid. 15. The system of claim 11, wherein each first tab comprises:
a horizontal portion substantially parallel to the circuit board; a vertical portion substantially perpendicular to the circuit board; and an elbow portion joining the horizontal portion to the vertical portion, the horizontal portion of the tab attached to the electrically conductive lid or the circuit board. 16. The system of claim 15, wherein the horizontal portion terminates at the free end of the tab. 17. The system of claim 15, wherein the vertical portion terminates at the free end of the tab. 18. The system of claim 15, wherein one of the horizontal and vertical portions of each tab is attached to the electrically conductive lid and the other of the horizontal and vertical portions of the tab is attached to the circuit board. 19. The system of claim 11, wherein the curved fence comprises an elongated continuous portion extending continuously along the first portion of the perimeter of the curved fence parallel to the circuit board, each first tab extending from the continuous horizontal portion of the fence, such that one of the elongated continuous portion of the fence and the plurality of first tabs is attached to the electrically conductive lid and the other of the elongated continuous portion of the fence and the plurality of first tabs is attached to the circuit board. 20. The system of claim 11, wherein each first tab comprises:
a top horizontal portion substantially parallel to the circuit board; a bottom horizontal portion substantially parallel to the circuit board; and a vertical portion joining the top and bottom horizontal portions and substantially perpendicular to the circuit board, the top horizontal portion attached to the electrically conductive lid and the bottom horizontal portion attached to the circuit board. 21. The system of claim 11, wherein the fence further comprises a plurality of spaced apart second tabs arranged along a different second portion of the perimeter of the fence, each second tab terminating at a free end, the first tabs being narrower than the second tabs. 22. The system of claim 21, wherein the perimeter of the fence is a polygon having a plurality of sides, wherein the plurality of spaced apart first tabs are arranged along one side of the perimeter, and the plurality of spaced apart second tabs are arranged along an adjacent side of the perimeter. 23. A flexible rectangular metal fence for conformably mounting on a curved circuit board and surrounding an electronic component mounted on the circuit board, the fence comprising opposing parallel first sides and opposing parallel second sides, wherein each first side comprises a plurality of spaced apart narrower first tabs and each second side comprises a plurality of spaced apart wider second tabs, each first and second tab having a free end. 24. The flexible rectangular metal fence of claim 23, wherein at least one of the first and second sides is generally L-shaped. 25. The flexible rectangular metal fence of claim 23, wherein each of the first and second sides is generally L-shaped. 26. The flexible rectangular metal fence of claim 23, wherein the first sides are generally S-shaped and the second sides are generally L-shaped. | 2,800 |
12,172 | 12,172 | 14,488,135 | 2,883 | An optical connector adapted to be attached to an electronics module having optical-electrical conversion electronics and a module optical window. The optical connector has a connector optical window and a port for an optical link that is optically couplable to the connector optical window. The connector optical window is constructed and arranged to optically align with the module optical window when the optical connector is attached to the electronics module. | 1. An optical connector adapted to be attached to an electronics module having optical-electrical conversion electronics and having at least one module optical window, said optical connector comprising:
at least one connector optical window; and at least one port for an optical link that is optically couplable through said connector optical window and said module optical window to said optical-electrical conversion electronics; said connector optical window being constructed and arranged to optically align with said module optical window when said optical connector is operably attached to said electronics module. 2. The optical connector of claim 1 wherein said optical connector comprises no optical-electrical conversion electronics. 3. The optical connector of claim 1 wherein said optical connector is readily removably attachable to said electronics module. 4. The optical connector of claim 3 wherein said optical connector is clippingly attachable to said electronics module. 5. The optical connector of claim 4 wherein said optical connector comprises a generally inverted U-shaped configuration comprising two leg portions connected to a body portion; wherein said at least one connector optical window is mounted on said body portion; wherein said leg portions are adapted to engage opposite lateral side portions of said electronics module; and wherein said at least one connection for an optical link is provided in said body portion. 6. The optical connector of claim 1 wherein said optical connector comprises a stud portion that is insertable into a socket portion of said electronics module. 7. The optical connector of claim 1 further comprising an electrical connector incorporated into said optical connector. 8. An optical connector assembly including:
a first optical connector having no optical-electrical conversion electronics that is adapted to be attached to a first electronics module having optical-electrical conversion electronics and at least one module optical window, said first optical connector comprising at least one connector optical window and at least one port for an optical link that is optically couplable to said connector optical window, said at least one connector optical window being constructed and arranged to optically align with said at least one first module optical window when said first optical connector is operably attached to said first electronics module; a second optical connector adapted to be attached to a second electronics module and comprising at least one port for an optical link; and at least one optical link comprising a first end portion that is operably receivable in said at least one port in said first optical connector and a second end portion that is operably receivable in said at least one port in said second optical connector. 9. The optical connector assembly of claim 8 wherein said at least one optical link has said first end portion thereof mounted in said at least one port in said first optical connector and has said second end portion thereof mounted in said at least one port in said second optical connector. 10. The optical connector assembly of claim 9 wherein said first optical connector is attached to said first electronics module and said second optical connector is attached to said second electronics module, wherein electronic signals are converted to optical signals in said first electronics module, wherein said optical signals are transmitted through said first optical connector and said second optical connector to said second electronics module, and wherein said optical signals are converted to electronic signals in said second electronics module. 11. The optical connector assembly of claim 8 wherein said first optical connector comprises a generally inverted U-shaped configuration comprising opposite leg portions and a body portion connecting said leg portions. 12. The optical connector assembly of claim 11 wherein said first optical connector comprises a generally inverted U-shaped configuration comprising opposite leg portions and a body portion connecting said leg portions, wherein said leg portions of said first optical connector are adapted to engage opposite lateral side portions of said first electronics module. 13. The optical connector assembly of claim 12 wherein said at least one optical window of said first optical connector is mounted on said body portion. 14. The optical connector assembly of claim 13 wherein said at least one port provided on said optical connector is provided in said body portion. 15. The optical connector assembly of claim 8 wherein said first and second optical connectors each comprise an electrical connector. 16. The optical connector assembly of claim 8 wherein said first optical connector comprises a stud portion and wherein said at least one connector optical window is mounted in said stud portion. 17. A method of optically connecting system components comprising:
providing a first optical connector that is attached to a first end of an optical cable; providing an electronics module with optical signal processing electronics; and readily removably attaching the first optical connector to the electronics module with a window in the optical connector aligned with a window in the electronics module. 18. The method of claim 17 comprising:
providing a second optical connector having no optical-electrical conversion electronics that is attached to the second end of the optical cable; and
readily removably attaching the second optical connector to a second electronics module with a window in the second optical connector aligned with a window in the second electronics module. 19. The method of claim 18 further comprising permanently attaching the first and second electronics modules to first and second circuits. 20. An electronic device comprising:
optical-electrical conversion electronics; at least one device optical window; physical attachment structure for attaching an optical connector, having at least one connector optical window and at least one port for an optical link that is optically couplable through said connector optical window and said device optical window, to said optical-electrical conversion electronics. 21. A method of signal processing comprising:
transmitting an optical signal through a window of an optical connector and an aligned window of an electronic device to which the optical connector is attached; and in the electronic device converting the transmitted optical signal to an electronic signal. 22. The method of claim 21 further comprising:
in the electronic device converting an electronic signal to an optical signal; and
transmitting the optical signal produced by the electronic signal conversion to the optical connector through the aligned windows of the electronic device and the optical connector. 23. The optical connector of claim 1 wherein said optical connector is operably attachable to an electronics module that comprises a crosspoint module. 24. The electronic device of claim 20 wherein said electronic device is an integrated circuit package. | An optical connector adapted to be attached to an electronics module having optical-electrical conversion electronics and a module optical window. The optical connector has a connector optical window and a port for an optical link that is optically couplable to the connector optical window. The connector optical window is constructed and arranged to optically align with the module optical window when the optical connector is attached to the electronics module.1. An optical connector adapted to be attached to an electronics module having optical-electrical conversion electronics and having at least one module optical window, said optical connector comprising:
at least one connector optical window; and at least one port for an optical link that is optically couplable through said connector optical window and said module optical window to said optical-electrical conversion electronics; said connector optical window being constructed and arranged to optically align with said module optical window when said optical connector is operably attached to said electronics module. 2. The optical connector of claim 1 wherein said optical connector comprises no optical-electrical conversion electronics. 3. The optical connector of claim 1 wherein said optical connector is readily removably attachable to said electronics module. 4. The optical connector of claim 3 wherein said optical connector is clippingly attachable to said electronics module. 5. The optical connector of claim 4 wherein said optical connector comprises a generally inverted U-shaped configuration comprising two leg portions connected to a body portion; wherein said at least one connector optical window is mounted on said body portion; wherein said leg portions are adapted to engage opposite lateral side portions of said electronics module; and wherein said at least one connection for an optical link is provided in said body portion. 6. The optical connector of claim 1 wherein said optical connector comprises a stud portion that is insertable into a socket portion of said electronics module. 7. The optical connector of claim 1 further comprising an electrical connector incorporated into said optical connector. 8. An optical connector assembly including:
a first optical connector having no optical-electrical conversion electronics that is adapted to be attached to a first electronics module having optical-electrical conversion electronics and at least one module optical window, said first optical connector comprising at least one connector optical window and at least one port for an optical link that is optically couplable to said connector optical window, said at least one connector optical window being constructed and arranged to optically align with said at least one first module optical window when said first optical connector is operably attached to said first electronics module; a second optical connector adapted to be attached to a second electronics module and comprising at least one port for an optical link; and at least one optical link comprising a first end portion that is operably receivable in said at least one port in said first optical connector and a second end portion that is operably receivable in said at least one port in said second optical connector. 9. The optical connector assembly of claim 8 wherein said at least one optical link has said first end portion thereof mounted in said at least one port in said first optical connector and has said second end portion thereof mounted in said at least one port in said second optical connector. 10. The optical connector assembly of claim 9 wherein said first optical connector is attached to said first electronics module and said second optical connector is attached to said second electronics module, wherein electronic signals are converted to optical signals in said first electronics module, wherein said optical signals are transmitted through said first optical connector and said second optical connector to said second electronics module, and wherein said optical signals are converted to electronic signals in said second electronics module. 11. The optical connector assembly of claim 8 wherein said first optical connector comprises a generally inverted U-shaped configuration comprising opposite leg portions and a body portion connecting said leg portions. 12. The optical connector assembly of claim 11 wherein said first optical connector comprises a generally inverted U-shaped configuration comprising opposite leg portions and a body portion connecting said leg portions, wherein said leg portions of said first optical connector are adapted to engage opposite lateral side portions of said first electronics module. 13. The optical connector assembly of claim 12 wherein said at least one optical window of said first optical connector is mounted on said body portion. 14. The optical connector assembly of claim 13 wherein said at least one port provided on said optical connector is provided in said body portion. 15. The optical connector assembly of claim 8 wherein said first and second optical connectors each comprise an electrical connector. 16. The optical connector assembly of claim 8 wherein said first optical connector comprises a stud portion and wherein said at least one connector optical window is mounted in said stud portion. 17. A method of optically connecting system components comprising:
providing a first optical connector that is attached to a first end of an optical cable; providing an electronics module with optical signal processing electronics; and readily removably attaching the first optical connector to the electronics module with a window in the optical connector aligned with a window in the electronics module. 18. The method of claim 17 comprising:
providing a second optical connector having no optical-electrical conversion electronics that is attached to the second end of the optical cable; and
readily removably attaching the second optical connector to a second electronics module with a window in the second optical connector aligned with a window in the second electronics module. 19. The method of claim 18 further comprising permanently attaching the first and second electronics modules to first and second circuits. 20. An electronic device comprising:
optical-electrical conversion electronics; at least one device optical window; physical attachment structure for attaching an optical connector, having at least one connector optical window and at least one port for an optical link that is optically couplable through said connector optical window and said device optical window, to said optical-electrical conversion electronics. 21. A method of signal processing comprising:
transmitting an optical signal through a window of an optical connector and an aligned window of an electronic device to which the optical connector is attached; and in the electronic device converting the transmitted optical signal to an electronic signal. 22. The method of claim 21 further comprising:
in the electronic device converting an electronic signal to an optical signal; and
transmitting the optical signal produced by the electronic signal conversion to the optical connector through the aligned windows of the electronic device and the optical connector. 23. The optical connector of claim 1 wherein said optical connector is operably attachable to an electronics module that comprises a crosspoint module. 24. The electronic device of claim 20 wherein said electronic device is an integrated circuit package. | 2,800 |
12,173 | 12,173 | 15,511,606 | 2,864 | Simultaneous inversion of multi-vintage seismic data obtains seismic data for vintages and generates an initial earth model for each vintage. A cost function includes a data norm term having for at least one pair of vintages of seismic data a difference norm between a difference in obtained seismic data for the at least one pair of vintages and a difference in modeled seismic data for the at least one pair of vintages. The cost function also includes a model norm term for each pair of vintages selected from at least three vintages of seismic data. Each model norm term includes a difference norm between earth models for a given pair of vintages. A closure relationship is imposed on all earth models. The earth models are adjusted for the vintages to drive the cost function to a minimum and to produce updated earth models. | 1. A method for inversion of multi-vintage seismic data, the method comprising:
obtaining seismic data of a subsurface structure for a plurality of vintages; generating an initial earth model of the subsurface structure for each one of the plurality of vintages; defining a cost function comprising a data norm term comprising for at least one pair of vintages of seismic data, a difference norm between a difference in obtained seismic data for the at least one pair of vintages and a difference in modeled seismic data for the at least one pair of vintages; and adjusting the earth models for the at least one pair of vintages to drive the cost function to a minimum and to produce updated earth models for the subsurface structure for the at least one pair of vintages. 2. The method of claim 1, wherein:
one vintage in the at least one pair of vintages comprises a baseline vintage; and defining the cost function further comprises defining the cost function comprising the data norm term comprising a difference norm between obtained seismic data for the baseline vintage and modeled seismic data for the baseline vintage. 3. The method of claim 1, wherein defining the cost function further comprises defining the cost function comprising the data norm term comprising for each pair of vintages selected from at least three vintages of seismic data a difference norm between the difference in obtained seismic data for a given pair of vintages and the difference in modeled seismic data for the given pair of vintages. 4. The method of claim 3, wherein adjusting the earth models further comprises adjusting the earth models for the at least three vintages to drive the cost function to a minimum and to produce updated earth models for the subsurface structure for the at least three vintages. 5. The method of claim 1, wherein the modeled seismic data for a given vintage comprises a function of the earth model for that given vintage. 6. The method of claim 1, wherein defining the cost function further comprises defining the cost function comprising a model norm term comprising for each pair of vintages selected from at least three vintages of seismic data a difference norm between earth models for a given pair of vintages. 7. The method of claim 6, wherein defining the cost function further comprises defining the cost function comprising the model norm term comprising a Lagrange multiplier for each difference norm between earth models for the given pair of vintages. 8. The method of claim 6, wherein defining the cost function further comprises defining the cost function comprising the model norm term comprising the difference norm between earth models for the given pair of vintages wherein each difference in the difference norm is acted upon by an operator. 9. The method of claim 6, further comprising imposing a closure relationship on all earth models from the at least three vintages in the plurality of vintages, the closure relationship defining consistent differences between all possible combinations of differences between earth models of subsequent vintages. 10. A method for inversion of multi-vintage seismic data, the method comprising:
obtaining seismic data of a subsurface structure for a plurality of vintages; generating an initial earth model of the subsurface structure for each one of the plurality of vintages; defining a cost function comprising a model norm term for each pair of vintages selected from at least three vintages of seismic data, each model norm term comprising a difference norm between earth models for a given pair of vintages; and adjusting the earth models for the at least three vintages to drive the cost function to a minimum and to produce updated earth models for the subsurface structure for the at least three vintages. 11. The method of claim 10, wherein defining the cost function further comprises defining the cost function comprising the model norm term comprising a Lagrange multiplier for each difference norm between earth models for the given pair of vintages. 12. The method of claim 10, wherein defining the cost function further comprises defining the cost function comprising the model norm term comprising the difference norm between earth models for the given pair of vintages wherein each difference in the difference norm is acted upon by an operator. 13. The method of claim 10, further comprising imposing a closure relationship on all earth models from the at least three vintages in the plurality of vintages, the closure relationship defining consistent differences between all possible combinations between earth models of subsequent vintages. 14. The method of claim 10, wherein defining the cost function further comprises defining the cost function comprising a data norm term. 15. The method of claim 14, wherein:
one vintage in the at least three vintages comprises a baseline vintage; and defining the cost function further comprises defining the cost function comprising the data norm term comprising a difference norm between obtained seismic data for the baseline vintage and modeled seismic data for the baseline vintage. 16. A computing system for inversion of multi-vintage seismic data, the computing system comprising:
a communication module to obtain seismic data of a subsurface structure for a plurality of vintages; and a processer in communication with the communication module and configured to:
generate an initial earth model of the subsurface structure for each one of the plurality of vintages;
define a cost function comprising a data norm term comprising for at least one pair of vintages of seismic data a difference norm between a difference in obtained seismic for the at least one pair of vintages and a difference in modeled seismic data for the at least one pair of vintages; and
adjust the earth models for the at least one pair of vintages to drive the cost function to a minimum and to produce updated earth models for the subsurface structure for the at least one pair of vintages. 17. The computing system of claim 16, wherein:
one vintage in the at least one pair of vintages comprises a baseline vintage; and the processor is further configured to define the cost function comprising the data norm term comprising a difference norm between obtained seismic data for the baseline vintage and modeled seismic data for the baseline vintage. 18. The computing system of claim 16, wherein the processor is further configured to:
define the cost function comprising a model norm term comprising for each pair of vintages selected from at least three vintages of seismic data a difference norm between earth models for a given pair of vintages; and impose a closure relationship on all earth models from the at least three vintages in the plurality of vintages, the closure relationship defining a consistent differences between all possible combinations of differences between earth models of subsequent vintages. 19. The computing system of claim 18, wherein the processor is further configured to define the cost function comprising the model norm term comprising a Lagrange multiplier for each difference norm between earth models for the given pair of vintages. 20. The computing system of claim 18, wherein the processor is further configured to define the cost function comprising the model norm term comprising the difference norm between velocity models for the given pair of vintages wherein each difference in the difference norm is acted upon by an operator. | Simultaneous inversion of multi-vintage seismic data obtains seismic data for vintages and generates an initial earth model for each vintage. A cost function includes a data norm term having for at least one pair of vintages of seismic data a difference norm between a difference in obtained seismic data for the at least one pair of vintages and a difference in modeled seismic data for the at least one pair of vintages. The cost function also includes a model norm term for each pair of vintages selected from at least three vintages of seismic data. Each model norm term includes a difference norm between earth models for a given pair of vintages. A closure relationship is imposed on all earth models. The earth models are adjusted for the vintages to drive the cost function to a minimum and to produce updated earth models.1. A method for inversion of multi-vintage seismic data, the method comprising:
obtaining seismic data of a subsurface structure for a plurality of vintages; generating an initial earth model of the subsurface structure for each one of the plurality of vintages; defining a cost function comprising a data norm term comprising for at least one pair of vintages of seismic data, a difference norm between a difference in obtained seismic data for the at least one pair of vintages and a difference in modeled seismic data for the at least one pair of vintages; and adjusting the earth models for the at least one pair of vintages to drive the cost function to a minimum and to produce updated earth models for the subsurface structure for the at least one pair of vintages. 2. The method of claim 1, wherein:
one vintage in the at least one pair of vintages comprises a baseline vintage; and defining the cost function further comprises defining the cost function comprising the data norm term comprising a difference norm between obtained seismic data for the baseline vintage and modeled seismic data for the baseline vintage. 3. The method of claim 1, wherein defining the cost function further comprises defining the cost function comprising the data norm term comprising for each pair of vintages selected from at least three vintages of seismic data a difference norm between the difference in obtained seismic data for a given pair of vintages and the difference in modeled seismic data for the given pair of vintages. 4. The method of claim 3, wherein adjusting the earth models further comprises adjusting the earth models for the at least three vintages to drive the cost function to a minimum and to produce updated earth models for the subsurface structure for the at least three vintages. 5. The method of claim 1, wherein the modeled seismic data for a given vintage comprises a function of the earth model for that given vintage. 6. The method of claim 1, wherein defining the cost function further comprises defining the cost function comprising a model norm term comprising for each pair of vintages selected from at least three vintages of seismic data a difference norm between earth models for a given pair of vintages. 7. The method of claim 6, wherein defining the cost function further comprises defining the cost function comprising the model norm term comprising a Lagrange multiplier for each difference norm between earth models for the given pair of vintages. 8. The method of claim 6, wherein defining the cost function further comprises defining the cost function comprising the model norm term comprising the difference norm between earth models for the given pair of vintages wherein each difference in the difference norm is acted upon by an operator. 9. The method of claim 6, further comprising imposing a closure relationship on all earth models from the at least three vintages in the plurality of vintages, the closure relationship defining consistent differences between all possible combinations of differences between earth models of subsequent vintages. 10. A method for inversion of multi-vintage seismic data, the method comprising:
obtaining seismic data of a subsurface structure for a plurality of vintages; generating an initial earth model of the subsurface structure for each one of the plurality of vintages; defining a cost function comprising a model norm term for each pair of vintages selected from at least three vintages of seismic data, each model norm term comprising a difference norm between earth models for a given pair of vintages; and adjusting the earth models for the at least three vintages to drive the cost function to a minimum and to produce updated earth models for the subsurface structure for the at least three vintages. 11. The method of claim 10, wherein defining the cost function further comprises defining the cost function comprising the model norm term comprising a Lagrange multiplier for each difference norm between earth models for the given pair of vintages. 12. The method of claim 10, wherein defining the cost function further comprises defining the cost function comprising the model norm term comprising the difference norm between earth models for the given pair of vintages wherein each difference in the difference norm is acted upon by an operator. 13. The method of claim 10, further comprising imposing a closure relationship on all earth models from the at least three vintages in the plurality of vintages, the closure relationship defining consistent differences between all possible combinations between earth models of subsequent vintages. 14. The method of claim 10, wherein defining the cost function further comprises defining the cost function comprising a data norm term. 15. The method of claim 14, wherein:
one vintage in the at least three vintages comprises a baseline vintage; and defining the cost function further comprises defining the cost function comprising the data norm term comprising a difference norm between obtained seismic data for the baseline vintage and modeled seismic data for the baseline vintage. 16. A computing system for inversion of multi-vintage seismic data, the computing system comprising:
a communication module to obtain seismic data of a subsurface structure for a plurality of vintages; and a processer in communication with the communication module and configured to:
generate an initial earth model of the subsurface structure for each one of the plurality of vintages;
define a cost function comprising a data norm term comprising for at least one pair of vintages of seismic data a difference norm between a difference in obtained seismic for the at least one pair of vintages and a difference in modeled seismic data for the at least one pair of vintages; and
adjust the earth models for the at least one pair of vintages to drive the cost function to a minimum and to produce updated earth models for the subsurface structure for the at least one pair of vintages. 17. The computing system of claim 16, wherein:
one vintage in the at least one pair of vintages comprises a baseline vintage; and the processor is further configured to define the cost function comprising the data norm term comprising a difference norm between obtained seismic data for the baseline vintage and modeled seismic data for the baseline vintage. 18. The computing system of claim 16, wherein the processor is further configured to:
define the cost function comprising a model norm term comprising for each pair of vintages selected from at least three vintages of seismic data a difference norm between earth models for a given pair of vintages; and impose a closure relationship on all earth models from the at least three vintages in the plurality of vintages, the closure relationship defining a consistent differences between all possible combinations of differences between earth models of subsequent vintages. 19. The computing system of claim 18, wherein the processor is further configured to define the cost function comprising the model norm term comprising a Lagrange multiplier for each difference norm between earth models for the given pair of vintages. 20. The computing system of claim 18, wherein the processor is further configured to define the cost function comprising the model norm term comprising the difference norm between velocity models for the given pair of vintages wherein each difference in the difference norm is acted upon by an operator. | 2,800 |
12,174 | 12,174 | 15,545,360 | 2,871 | An optical system including a lighting component and a switchable diffuser in optical communication with the lighting component. The optical system may further include a low absorbing optical component. At least one outer surface of the switchable diffuser and/or the low absorbing optical component includes light redirecting structures. When the switchable diffuser is in a first state and the optical system produces a light output, the light redirecting structures are configured to increase the full width at half-maximum (FWHM) of the light output of the optical system in at least one direction by at least 5 degrees relative to that of an otherwise equivalent optical system that does not include the light redirecting structures. | 1. An optical system comprising:
a lighting component; a switchable diffuser in optical communication with the lighting component, the switchable diffuser having at least a first state and a second state, the first state characterized by a first haze and the second state characterized by a second haze different from the first haze; a low absorbing optical component in optical communication with the lighting component and in optical communication with the switchable diffuser, wherein the low absorbing optical component includes opposing first and second outer surfaces, at least one of the first and second outer surfaces including light redirecting structures, wherein when the switchable diffuser is in the first state and the optical system produces a light output, the light redirecting structures are configured to increase the full width at half-maximum (FWHM) of the light output of the optical system in at least one direction by at least 5 degrees relative to that of an otherwise equivalent optical system that does not include the light redirecting structures. 2. An optical system comprising:
a lighting component; a switchable diffuser in optical communication with the lighting component, the switchable diffuser having at least a first state and a second state, the first state characterized by a first haze and the second state characterized by a second haze different from the first haze; wherein the switchable diffuser includes an active layer disposed between a first outer layer and a second outer layer, the first outer layer having a first outer surface opposite the active layer, the second outer layer having a second outer surface opposite the active layer, the second outer layer facing the lighting component, at least one of the first and second outer surfaces including light redirecting structures; wherein when the switchable diffuser is in the first state and the optical system produces a light output, the light redirecting structures are configured to increase the full width at half-maximum (FWHM) of the light output of the optical system in at least one direction by at least 5 degrees relative to that of an otherwise equivalent optical system that does not include the light redirecting structures. 3. An optical system comprising:
a lighting component; a switchable diffuser in optical communication with the lighting component, the switchable diffuser having at least a first state and a second state, the first state characterized by a first haze and the second state characterized by a second haze different from the first haze; wherein the switchable diffuser includes an active layer disposed between a first outer layer and a second outer layer, the first outer layer having a first outer surface opposite the active layer, the second outer layer having a second outer surface opposite the active layer, a low absorbing optical component in optical communication with the lighting component and in optical communication with the switchable diffuser, the low absorbing optical component including opposing third and fourth outer surfaces, wherein at least one of the first, second, third and fourth outer surfaces includes light redirecting structures, wherein when the switchable diffuser is in the first state and the optical system produces a light output, the light redirecting structures are configured to increase the full width at half-maximum (FWHM) of the light output of the optical system in at least one direction by at least 5 degrees relative to that of an otherwise equivalent optical system that does not include the light redirecting structures. 4. The optical system of claim 1, wherein an average direction of the light output of the optical system when the switchable diffuser is in the first state is the same as an average direction of a light output of the otherwise equivalent optical system when the switchable diffuser is in the first state. 5. The optical system of claim 1, wherein an average direction of the light output of the optical system when the switchable diffuser is in the first state is different from an average direction of a light output of the otherwise equivalent optical system when the switchable diffuser is in the first state. 6. The optical system of claim 1, wherein the switchable diffuser has a haze less than about 5 percent at all angles of incidence in the range of zero degrees to about 85 degrees when the switchable diffuser is in the first state. 7. The optical system of claim 2, wherein the active layer has a haze less than about 5 percent at all angles of incidence in the range of zero degrees to about 85 degrees when the switchable diffuser is in the first state. 8. The optical system of claim 1, wherein the FWHM of the light output of the optical system is increased in two orthogonal directions relative to that of the otherwise equivalent optical system. 9. The optical system of claim 1, wherein the switchable diffuser includes a plurality of independently addressable regions. 10. The optical system of claim 1, wherein the light redirecting structures include a first set of light redirecting structures in a first region of the low absorbing optical component and a second set of light redirecting structures in a second region of the low absorbing optical component different from the first region of the low absorbing optical component. 11. The optical system of claim 2, wherein the light redirecting structures include a first set of light redirecting structures in a first region of the switchable diffuser and a second set of light redirecting structures in a second region of the switchable diffuser different from the first region of the switchable diffuser. 12. The optical system of claim 10, wherein the first and second set of light redirecting structures have differing distributions of size, shape, spacing or slope. 13. The optical system of claim 1, wherein the light redirecting structures are configured to increase the full width at half-maximum (FWHM) of the light output in at least one direction by at least 10 degrees relative to that of the otherwise equivalent optical system. 14. The optical system of claim 1 further comprising an additional diffuser in optical communication with the lighting component. 15. A lighting system comprising:
one or more optical systems according to claim 1; a controller configured to provide a diffuser control signal to one or more of the switchable diffusers of the one or more optical systems; and one or more sensors, wherein the controller is configured to receive one or more signals from the one or more sensors. 16. The optical system of claim 11, wherein the first and second set of light redirecting structures have differing distributions of size, shape, spacing or slope. 17. The optical system of claim 2, wherein the switchable diffuser includes a plurality of independently addressable regions. 18. A lighting system comprising:
one or more optical systems according to claim 2; a controller configured to provide a diffuser control signal to one or more of the switchable diffusers of the one or more optical systems; and one or more sensors, wherein the controller is configured to receive one or more signals from the one or more sensors. 19. The optical system of claim 3, wherein the switchable diffuser includes a plurality of independently addressable regions. 20. A lighting system comprising:
one or more optical systems according to claim 3; a controller configured to provide a diffuser control signal to one or more of the switchable diffusers of the one or more optical systems; and one or more sensors, wherein the controller is configured to receive one or more signals from the one or more sensors. | An optical system including a lighting component and a switchable diffuser in optical communication with the lighting component. The optical system may further include a low absorbing optical component. At least one outer surface of the switchable diffuser and/or the low absorbing optical component includes light redirecting structures. When the switchable diffuser is in a first state and the optical system produces a light output, the light redirecting structures are configured to increase the full width at half-maximum (FWHM) of the light output of the optical system in at least one direction by at least 5 degrees relative to that of an otherwise equivalent optical system that does not include the light redirecting structures.1. An optical system comprising:
a lighting component; a switchable diffuser in optical communication with the lighting component, the switchable diffuser having at least a first state and a second state, the first state characterized by a first haze and the second state characterized by a second haze different from the first haze; a low absorbing optical component in optical communication with the lighting component and in optical communication with the switchable diffuser, wherein the low absorbing optical component includes opposing first and second outer surfaces, at least one of the first and second outer surfaces including light redirecting structures, wherein when the switchable diffuser is in the first state and the optical system produces a light output, the light redirecting structures are configured to increase the full width at half-maximum (FWHM) of the light output of the optical system in at least one direction by at least 5 degrees relative to that of an otherwise equivalent optical system that does not include the light redirecting structures. 2. An optical system comprising:
a lighting component; a switchable diffuser in optical communication with the lighting component, the switchable diffuser having at least a first state and a second state, the first state characterized by a first haze and the second state characterized by a second haze different from the first haze; wherein the switchable diffuser includes an active layer disposed between a first outer layer and a second outer layer, the first outer layer having a first outer surface opposite the active layer, the second outer layer having a second outer surface opposite the active layer, the second outer layer facing the lighting component, at least one of the first and second outer surfaces including light redirecting structures; wherein when the switchable diffuser is in the first state and the optical system produces a light output, the light redirecting structures are configured to increase the full width at half-maximum (FWHM) of the light output of the optical system in at least one direction by at least 5 degrees relative to that of an otherwise equivalent optical system that does not include the light redirecting structures. 3. An optical system comprising:
a lighting component; a switchable diffuser in optical communication with the lighting component, the switchable diffuser having at least a first state and a second state, the first state characterized by a first haze and the second state characterized by a second haze different from the first haze; wherein the switchable diffuser includes an active layer disposed between a first outer layer and a second outer layer, the first outer layer having a first outer surface opposite the active layer, the second outer layer having a second outer surface opposite the active layer, a low absorbing optical component in optical communication with the lighting component and in optical communication with the switchable diffuser, the low absorbing optical component including opposing third and fourth outer surfaces, wherein at least one of the first, second, third and fourth outer surfaces includes light redirecting structures, wherein when the switchable diffuser is in the first state and the optical system produces a light output, the light redirecting structures are configured to increase the full width at half-maximum (FWHM) of the light output of the optical system in at least one direction by at least 5 degrees relative to that of an otherwise equivalent optical system that does not include the light redirecting structures. 4. The optical system of claim 1, wherein an average direction of the light output of the optical system when the switchable diffuser is in the first state is the same as an average direction of a light output of the otherwise equivalent optical system when the switchable diffuser is in the first state. 5. The optical system of claim 1, wherein an average direction of the light output of the optical system when the switchable diffuser is in the first state is different from an average direction of a light output of the otherwise equivalent optical system when the switchable diffuser is in the first state. 6. The optical system of claim 1, wherein the switchable diffuser has a haze less than about 5 percent at all angles of incidence in the range of zero degrees to about 85 degrees when the switchable diffuser is in the first state. 7. The optical system of claim 2, wherein the active layer has a haze less than about 5 percent at all angles of incidence in the range of zero degrees to about 85 degrees when the switchable diffuser is in the first state. 8. The optical system of claim 1, wherein the FWHM of the light output of the optical system is increased in two orthogonal directions relative to that of the otherwise equivalent optical system. 9. The optical system of claim 1, wherein the switchable diffuser includes a plurality of independently addressable regions. 10. The optical system of claim 1, wherein the light redirecting structures include a first set of light redirecting structures in a first region of the low absorbing optical component and a second set of light redirecting structures in a second region of the low absorbing optical component different from the first region of the low absorbing optical component. 11. The optical system of claim 2, wherein the light redirecting structures include a first set of light redirecting structures in a first region of the switchable diffuser and a second set of light redirecting structures in a second region of the switchable diffuser different from the first region of the switchable diffuser. 12. The optical system of claim 10, wherein the first and second set of light redirecting structures have differing distributions of size, shape, spacing or slope. 13. The optical system of claim 1, wherein the light redirecting structures are configured to increase the full width at half-maximum (FWHM) of the light output in at least one direction by at least 10 degrees relative to that of the otherwise equivalent optical system. 14. The optical system of claim 1 further comprising an additional diffuser in optical communication with the lighting component. 15. A lighting system comprising:
one or more optical systems according to claim 1; a controller configured to provide a diffuser control signal to one or more of the switchable diffusers of the one or more optical systems; and one or more sensors, wherein the controller is configured to receive one or more signals from the one or more sensors. 16. The optical system of claim 11, wherein the first and second set of light redirecting structures have differing distributions of size, shape, spacing or slope. 17. The optical system of claim 2, wherein the switchable diffuser includes a plurality of independently addressable regions. 18. A lighting system comprising:
one or more optical systems according to claim 2; a controller configured to provide a diffuser control signal to one or more of the switchable diffusers of the one or more optical systems; and one or more sensors, wherein the controller is configured to receive one or more signals from the one or more sensors. 19. The optical system of claim 3, wherein the switchable diffuser includes a plurality of independently addressable regions. 20. A lighting system comprising:
one or more optical systems according to claim 3; a controller configured to provide a diffuser control signal to one or more of the switchable diffusers of the one or more optical systems; and one or more sensors, wherein the controller is configured to receive one or more signals from the one or more sensors. | 2,800 |
12,175 | 12,175 | 16,296,007 | 2,847 | Superconducting integrated circuit layouts are proofed against the detrimental effects of stray flux by designing and fabricating them to have one or more ground planes patterned in the x-y plane with a regular grid of low-aspect-ratio flux-trapping voids. The ground plane(s) can be globally patterned with such voids and thousands or more superconducting circuit devices and wires can thereafter be laid out so as not to intersect or come so close to the voids that the trapped flux would induce supercurrents in them, thus preventing undesirable coupling of flux into circuit elements. Sandwiching a wire layer between patterned ground planes permits wires to be laid out even closer to the voids. Voids of successively smaller maximum dimension can be concentrically stacked in pyramidal fashion in multiple ground plane layers having different superconductor transition temperatures, increasing the x-y area available for device placement and wire-up. | 1. A superconducting digital integrated circuit (IC) comprising:
a ground plane fabricated at least in part as a blanket deposition of a superconducting metal, the ground plane being patterned with a regular grid of dielectric-filled flux-trapping voids, each void in the grid being generally radially symmetrical in shape; and discrete circuit devices interconnected by superconducting wires fabricated on one or more device layers above the ground plane, the devices being placed and wires being routed between individual voids in the regular grid, such that the devices and wires do not intersect any of the voids and maintain at least a predetermined distance away from any of the voids, the devices and wires forming at least one active digital circuit; wherein the voids are configured to protect the at least one active digital circuit from parasitic flux bias by attracting and sequestering stray flux such that it cannot couple flux to the devices or wires. 2. The IC of claim 1, wherein the ground plane has a thickness of between about twenty nanometers and about one thousand nanometers. 3. The IC of claim 1, wherein a maximum dimension of each void in the grid is less than or equal to a maximum distance from a possible stray location on the ground plane to a nearest void edge. 4. The IC of claim 3, wherein a maximum dimension of each void in the grid is between about one-fifth of a micrometer and about ten micrometers, and wherein the maximum distance from a possible stray location on the ground plane to a nearest void edge is between about one-half of a micrometer and about ten micrometers. 5. The IC of claim 3, wherein the minimum center-to-center spacing between voids is between about five micrometers and about twenty micrometers. 6. The IC of claim 1, wherein the ground plane is a second ground plane, the IC further comprising a first superconducting ground plane located beneath the second ground plane, on the other side of the second ground plane from the one or more device layers. 7. The IC of claim 6, wherein at least one of the flux-trapping voids of the second ground plane is annular to provide a superconductive-metal-filled through-via that either superconductively connects at least one of the one or more device layers and the first ground plane or superconductively connects at least one of the one or more device layers and a wiring layer located between the first and second ground planes. 8. The IC of claim 6, wherein the first ground plane is patterned with dielectric-filled flux-trapping voids, and wherein at least some of the voids of the first ground plane are each concentric with a corresponding flux-trapping void of the second ground plane. 9. The IC of claim 8, having a wiring layer between the first and second ground planes. 10. The IC of claim 8, wherein for at least some of the voids of the second ground plane having a corresponding concentric void of the first ground plane, the maximum dimension of each second-ground-plane void is less than the maximum dimension of its corresponding first-ground-plane void. 11. The IC of claim 8, wherein each second-ground-plane void having a larger corresponding first-ground-plane void has a maximum dimension between about one fifth of a micrometer and about five micrometers, and wherein each first-ground-plane void having a smaller corresponding second-ground-plane void has a maximum dimension between about five micrometers and about fifteen micrometers. 12. The IC of claim 11, wherein the maximum distance from a possible stray location on the ground plane to a nearest void edge in the nearest layer is between about ten micrometers and about fourteen micrometers. 13. The IC of claim 10, wherein the first ground plane is configured to become superconducting before the second ground plane during cryogenic cooldown of the IC. 14. The IC of claim 13, wherein the first ground plane has a higher critical temperature than the second ground plane. 15. A method of fabricating a superconducting digital integrated circuit (IC) comprising:
fabricating a ground plane patterned with a regular grid of dielectric-filled flux-trapping voids, each void in the grid being generally radially symmetrical in shape, at least in part by fabricating each void in the grid as having a maximum dimension less than or equal to a maximum distance from a possible stray location on the ground plane to a nearest void edge; and fabricating one or more device layers above the ground plane to have discrete circuit devices interconnected by superconducting wires, the devices being placed and wires being routed between individual voids in the regular grid, such that the devices and wires do not intersect any of the voids and maintain at least a predetermined distance away from each of the voids, the devices and wires forming at least one active digital circuit; wherein the voids are configured to protect the at least one active digital circuit from parasitic flux bias by attracting and sequestering stray flux such that it cannot couple flux to the devices or wires. 16. The method of claim 15, wherein the ground plane is fabricated such that a maximum dimension of each void in the grid is between about one-fifth of a micrometer and about ten micrometers, and wherein the maximum distance from a possible stray location on the ground plane to a nearest void edge is between about one-half of a micrometer and about ten micrometers. 17. The method of claim 15, wherein the ground plane is a near ground plane, the method further comprising fabricating a far superconducting ground plane patterned with flux-trapping voids at least some of which are concentric with corresponding voids in the near ground plane, the far ground plane being configured to become superconducting prior to the near ground plane during cryogenic cooldown of the IC, the far ground plane being located on the other side of the near ground plane from the one or more device layers,
wherein each near-ground-plane void having a larger corresponding far-ground-plane void has a maximum dimension between about one fifth of a micrometer and about five micrometers, wherein each far-ground-plane void having a smaller corresponding near-ground-plane void has a maximum dimension between about five micrometers and about fifteen micrometers, and wherein the maximum distance from a possible stray location on the ground plane to a nearest void edge in the nearest layer is between about ten micrometers and about fourteen micrometers. 18. A superconducting digital integrated circuit (IC) comprising:
first and second ground planes each fabricated at least in part as a blanket deposition of a superconducting metal and each being patterned with a regular grid of dielectric-filled flux-trapping voids, at least some of the voids of the second ground plane each having a corresponding concentric void of the first ground plane, the maximum dimension of each second-ground-plane void being less than the maximum dimension of the corresponding first-ground-plane void; and one or more device layers above the ground planes, the one or more device layers comprising discrete circuit devices interconnected by superconducting wires, the devices being placed and wires being routed between individual voids in the regular grid, such that the devices and wires do not intersect any of the voids and maintain at least a predetermined distance away from any of the voids, the devices and wires forming at least one active digital circuit; wherein the voids are configured to protect the at least one active digital circuit from parasitic flux bias by attracting and sequestering stray flux such that it cannot couple flux to the devices or wires. 19. The IC of claim 18, further comprising a wiring layer between the ground planes, the wiring layer comprising wires routed between individual voids in the regular grids of the ground planes. 20. The IC of claim 19, wherein at least one of the flux-trapping voids of the second ground plane is annular to provide a superconductive-metal-filled through-via that either superconductively connects at least one of the one or more device layers and the first ground plane or superconductively connects at least one of the one or more device layers and the wiring layer. | Superconducting integrated circuit layouts are proofed against the detrimental effects of stray flux by designing and fabricating them to have one or more ground planes patterned in the x-y plane with a regular grid of low-aspect-ratio flux-trapping voids. The ground plane(s) can be globally patterned with such voids and thousands or more superconducting circuit devices and wires can thereafter be laid out so as not to intersect or come so close to the voids that the trapped flux would induce supercurrents in them, thus preventing undesirable coupling of flux into circuit elements. Sandwiching a wire layer between patterned ground planes permits wires to be laid out even closer to the voids. Voids of successively smaller maximum dimension can be concentrically stacked in pyramidal fashion in multiple ground plane layers having different superconductor transition temperatures, increasing the x-y area available for device placement and wire-up.1. A superconducting digital integrated circuit (IC) comprising:
a ground plane fabricated at least in part as a blanket deposition of a superconducting metal, the ground plane being patterned with a regular grid of dielectric-filled flux-trapping voids, each void in the grid being generally radially symmetrical in shape; and discrete circuit devices interconnected by superconducting wires fabricated on one or more device layers above the ground plane, the devices being placed and wires being routed between individual voids in the regular grid, such that the devices and wires do not intersect any of the voids and maintain at least a predetermined distance away from any of the voids, the devices and wires forming at least one active digital circuit; wherein the voids are configured to protect the at least one active digital circuit from parasitic flux bias by attracting and sequestering stray flux such that it cannot couple flux to the devices or wires. 2. The IC of claim 1, wherein the ground plane has a thickness of between about twenty nanometers and about one thousand nanometers. 3. The IC of claim 1, wherein a maximum dimension of each void in the grid is less than or equal to a maximum distance from a possible stray location on the ground plane to a nearest void edge. 4. The IC of claim 3, wherein a maximum dimension of each void in the grid is between about one-fifth of a micrometer and about ten micrometers, and wherein the maximum distance from a possible stray location on the ground plane to a nearest void edge is between about one-half of a micrometer and about ten micrometers. 5. The IC of claim 3, wherein the minimum center-to-center spacing between voids is between about five micrometers and about twenty micrometers. 6. The IC of claim 1, wherein the ground plane is a second ground plane, the IC further comprising a first superconducting ground plane located beneath the second ground plane, on the other side of the second ground plane from the one or more device layers. 7. The IC of claim 6, wherein at least one of the flux-trapping voids of the second ground plane is annular to provide a superconductive-metal-filled through-via that either superconductively connects at least one of the one or more device layers and the first ground plane or superconductively connects at least one of the one or more device layers and a wiring layer located between the first and second ground planes. 8. The IC of claim 6, wherein the first ground plane is patterned with dielectric-filled flux-trapping voids, and wherein at least some of the voids of the first ground plane are each concentric with a corresponding flux-trapping void of the second ground plane. 9. The IC of claim 8, having a wiring layer between the first and second ground planes. 10. The IC of claim 8, wherein for at least some of the voids of the second ground plane having a corresponding concentric void of the first ground plane, the maximum dimension of each second-ground-plane void is less than the maximum dimension of its corresponding first-ground-plane void. 11. The IC of claim 8, wherein each second-ground-plane void having a larger corresponding first-ground-plane void has a maximum dimension between about one fifth of a micrometer and about five micrometers, and wherein each first-ground-plane void having a smaller corresponding second-ground-plane void has a maximum dimension between about five micrometers and about fifteen micrometers. 12. The IC of claim 11, wherein the maximum distance from a possible stray location on the ground plane to a nearest void edge in the nearest layer is between about ten micrometers and about fourteen micrometers. 13. The IC of claim 10, wherein the first ground plane is configured to become superconducting before the second ground plane during cryogenic cooldown of the IC. 14. The IC of claim 13, wherein the first ground plane has a higher critical temperature than the second ground plane. 15. A method of fabricating a superconducting digital integrated circuit (IC) comprising:
fabricating a ground plane patterned with a regular grid of dielectric-filled flux-trapping voids, each void in the grid being generally radially symmetrical in shape, at least in part by fabricating each void in the grid as having a maximum dimension less than or equal to a maximum distance from a possible stray location on the ground plane to a nearest void edge; and fabricating one or more device layers above the ground plane to have discrete circuit devices interconnected by superconducting wires, the devices being placed and wires being routed between individual voids in the regular grid, such that the devices and wires do not intersect any of the voids and maintain at least a predetermined distance away from each of the voids, the devices and wires forming at least one active digital circuit; wherein the voids are configured to protect the at least one active digital circuit from parasitic flux bias by attracting and sequestering stray flux such that it cannot couple flux to the devices or wires. 16. The method of claim 15, wherein the ground plane is fabricated such that a maximum dimension of each void in the grid is between about one-fifth of a micrometer and about ten micrometers, and wherein the maximum distance from a possible stray location on the ground plane to a nearest void edge is between about one-half of a micrometer and about ten micrometers. 17. The method of claim 15, wherein the ground plane is a near ground plane, the method further comprising fabricating a far superconducting ground plane patterned with flux-trapping voids at least some of which are concentric with corresponding voids in the near ground plane, the far ground plane being configured to become superconducting prior to the near ground plane during cryogenic cooldown of the IC, the far ground plane being located on the other side of the near ground plane from the one or more device layers,
wherein each near-ground-plane void having a larger corresponding far-ground-plane void has a maximum dimension between about one fifth of a micrometer and about five micrometers, wherein each far-ground-plane void having a smaller corresponding near-ground-plane void has a maximum dimension between about five micrometers and about fifteen micrometers, and wherein the maximum distance from a possible stray location on the ground plane to a nearest void edge in the nearest layer is between about ten micrometers and about fourteen micrometers. 18. A superconducting digital integrated circuit (IC) comprising:
first and second ground planes each fabricated at least in part as a blanket deposition of a superconducting metal and each being patterned with a regular grid of dielectric-filled flux-trapping voids, at least some of the voids of the second ground plane each having a corresponding concentric void of the first ground plane, the maximum dimension of each second-ground-plane void being less than the maximum dimension of the corresponding first-ground-plane void; and one or more device layers above the ground planes, the one or more device layers comprising discrete circuit devices interconnected by superconducting wires, the devices being placed and wires being routed between individual voids in the regular grid, such that the devices and wires do not intersect any of the voids and maintain at least a predetermined distance away from any of the voids, the devices and wires forming at least one active digital circuit; wherein the voids are configured to protect the at least one active digital circuit from parasitic flux bias by attracting and sequestering stray flux such that it cannot couple flux to the devices or wires. 19. The IC of claim 18, further comprising a wiring layer between the ground planes, the wiring layer comprising wires routed between individual voids in the regular grids of the ground planes. 20. The IC of claim 19, wherein at least one of the flux-trapping voids of the second ground plane is annular to provide a superconductive-metal-filled through-via that either superconductively connects at least one of the one or more device layers and the first ground plane or superconductively connects at least one of the one or more device layers and the wiring layer. | 2,800 |
12,176 | 12,176 | 16,156,708 | 2,848 | A monolithic ceramic capacitor has a plurality of dielectric layers and a plurality of conductive layers sintered together to form a substantially monolithic ceramic body. The ceramic body defines at least one void between the dielectric and conductive layers. The void is at least partially enclosed within the ceramic body and bounded by at least a portion of a dielectric layer, a first conductive layer, and a second conductive layer. Within the dielectric body, the first and second conductive layers are connected in a nonconductive manner. | 1. A ceramic capacitor comprising:
a plurality of dielectric layers and a plurality of conductive layer sintered together to form a substantially monolithic ceramic body, the body defining at least one void between the dielectric and conductive layers, the void being at least partially enclosed within the ceramic body and bounded by at least a portion of a dielectric layer, a first conductive layer, and a second conductive layer, the first and second conductive layers having no conductive connection therebetween. 2. The capacitor of claim 1, wherein the first and second conductive layers each have an end bordering the void, the first and second layer ends being sufficiently close together as to form a fringe effect capacitance in the void. 3. The capacitor of claim 1, wherein the first conductive layer at least partially overlays the second conductive layer and the void is between the overlaying layers. 4. The capacitor of claim 1, wherein a capacitance is formed in the void by a fringe effect field between the first and second conductive layers. 5. The capacitor of claim 4, wherein a high frequency capacitance is formed in the void. 6. The capacitor of claim 2, further comprising a second void at least partially enclosed within the ceramic body and bounded by at least a portion of a dielectric layer, a third conductive layer and a fourth conductive layer, the third and fourth conductive layers having no conductive connection therebetween. 7. The capacitor of claim 6 wherein the third and fourth layers each have an end bordering the second void, the third and fourth layer ends being sufficiently close to form a second fringe effect capacitance in the second void. 8. The capacitor of claim 3, wherein the void is spaced between the first and second conductive layers in a vertical direction. 9. The capacitor of claim 4, wherein at least some of the plurality of dielectric layers are interleaved with at least some of the plurality of conductive layers in the ceramic body to form an additional, lower frequency capacitance. 10. The capacitor of claim 1, wherein the capacitor further comprises a low frequency, higher capacitance value section and a high frequency, lower capacitance value section, the vertical spacing between conductive layers being substantially greater in the high frequency, lower capacitance value section. 11. The capacitor of claim 3, wherein the capacitor further comprises a low frequency, higher capacitance value section and a high frequency, lower capacitance value section, the overlay between the layers being substantially greater in the low frequency, higher capacitance value section. 12. A capacitor comprising:
a substantially monolithic dielectric body; a plurality of conductive first layers disposed within the dielectric body and electrically connected to a first conductive contact on the dielectric body; a plurality of conductive second layers disposed within the dielectric body and electrically connected to a second conductive contact on the dielectric body, the plurality of second layers interleaved with the plurality of first layers to form capacitances between the layers; at least one set of conductive plates separated by a void, the void at least partially enclosed by the dielectric body and bordered by at least a portion of a dielectric layer and adjacent edges of first and second conductive plates, the first and second conductive plates being spaced apart to form a nonconductive capacitive connection through the void. 13. The capacitor of claim 12, wherein the first and second conductive plates are spaced apart to form a fringe effect capacitance within the void. 14. The capacitor of claim 13, wherein the first and second conductive plates are coplanar. 15. A method of making a monolithic ceramic capacitor containing at least one air gap capacitance, the method comprising:
providing a plurality of layers of a dielectric ceramic; providing a plurality of conductive layers; stacking the conductive and dielectric layers in an interleaving fashion; sintering the interleaved layers to form a monolithic ceramic body; forming a void in the monolithic ceramic body, the void being at least partially enclosed by the monolithic ceramic body, bounded by at least a portion of a dielectric layer and portions of a first conductive layer and a second conductive layer; and spacing the first and second conductive layers apart relative to the void to form a nonconductive capacitive connection between the layers. 16. The method of claim 15, further comprising the step of spacing the first and second conductive layers related to the void to form a capacitance in the void. 17. The method of claim 15, wherein the step of forming a void further comprises drilling an opening into at least one of the plurality of layers of a dielectric ceramic, at least one of the plurality of conductive layers, or combinations thereof. 18. The method of claim 15, wherein the step of forming a void further comprises punching an opening into at least one of the plurality of layers of a dielectric ceramic, at least one of the plurality of conductive layers, or combinations thereof. 19. The method of claim 15, wherein the step of forming a void further comprises laser cutting an opening into at least one of the plurality of layers of a dielectric ceramic, at least one of the plurality of conductive layers, or combinations thereof. 20. The method of claim 15, wherein the steps of sintering and forming a void further comprises providing a fugitive material in at least one of the plurality of layers of dielectric material and burning away the fugitive material during the sintering step to form the void. 21. The method of claim 15, wherein electro-plating is used to bridge the plurality of conductive layers bounding the void in a manner that maintains the nonconductive capacitive connection between the layers. | A monolithic ceramic capacitor has a plurality of dielectric layers and a plurality of conductive layers sintered together to form a substantially monolithic ceramic body. The ceramic body defines at least one void between the dielectric and conductive layers. The void is at least partially enclosed within the ceramic body and bounded by at least a portion of a dielectric layer, a first conductive layer, and a second conductive layer. Within the dielectric body, the first and second conductive layers are connected in a nonconductive manner.1. A ceramic capacitor comprising:
a plurality of dielectric layers and a plurality of conductive layer sintered together to form a substantially monolithic ceramic body, the body defining at least one void between the dielectric and conductive layers, the void being at least partially enclosed within the ceramic body and bounded by at least a portion of a dielectric layer, a first conductive layer, and a second conductive layer, the first and second conductive layers having no conductive connection therebetween. 2. The capacitor of claim 1, wherein the first and second conductive layers each have an end bordering the void, the first and second layer ends being sufficiently close together as to form a fringe effect capacitance in the void. 3. The capacitor of claim 1, wherein the first conductive layer at least partially overlays the second conductive layer and the void is between the overlaying layers. 4. The capacitor of claim 1, wherein a capacitance is formed in the void by a fringe effect field between the first and second conductive layers. 5. The capacitor of claim 4, wherein a high frequency capacitance is formed in the void. 6. The capacitor of claim 2, further comprising a second void at least partially enclosed within the ceramic body and bounded by at least a portion of a dielectric layer, a third conductive layer and a fourth conductive layer, the third and fourth conductive layers having no conductive connection therebetween. 7. The capacitor of claim 6 wherein the third and fourth layers each have an end bordering the second void, the third and fourth layer ends being sufficiently close to form a second fringe effect capacitance in the second void. 8. The capacitor of claim 3, wherein the void is spaced between the first and second conductive layers in a vertical direction. 9. The capacitor of claim 4, wherein at least some of the plurality of dielectric layers are interleaved with at least some of the plurality of conductive layers in the ceramic body to form an additional, lower frequency capacitance. 10. The capacitor of claim 1, wherein the capacitor further comprises a low frequency, higher capacitance value section and a high frequency, lower capacitance value section, the vertical spacing between conductive layers being substantially greater in the high frequency, lower capacitance value section. 11. The capacitor of claim 3, wherein the capacitor further comprises a low frequency, higher capacitance value section and a high frequency, lower capacitance value section, the overlay between the layers being substantially greater in the low frequency, higher capacitance value section. 12. A capacitor comprising:
a substantially monolithic dielectric body; a plurality of conductive first layers disposed within the dielectric body and electrically connected to a first conductive contact on the dielectric body; a plurality of conductive second layers disposed within the dielectric body and electrically connected to a second conductive contact on the dielectric body, the plurality of second layers interleaved with the plurality of first layers to form capacitances between the layers; at least one set of conductive plates separated by a void, the void at least partially enclosed by the dielectric body and bordered by at least a portion of a dielectric layer and adjacent edges of first and second conductive plates, the first and second conductive plates being spaced apart to form a nonconductive capacitive connection through the void. 13. The capacitor of claim 12, wherein the first and second conductive plates are spaced apart to form a fringe effect capacitance within the void. 14. The capacitor of claim 13, wherein the first and second conductive plates are coplanar. 15. A method of making a monolithic ceramic capacitor containing at least one air gap capacitance, the method comprising:
providing a plurality of layers of a dielectric ceramic; providing a plurality of conductive layers; stacking the conductive and dielectric layers in an interleaving fashion; sintering the interleaved layers to form a monolithic ceramic body; forming a void in the monolithic ceramic body, the void being at least partially enclosed by the monolithic ceramic body, bounded by at least a portion of a dielectric layer and portions of a first conductive layer and a second conductive layer; and spacing the first and second conductive layers apart relative to the void to form a nonconductive capacitive connection between the layers. 16. The method of claim 15, further comprising the step of spacing the first and second conductive layers related to the void to form a capacitance in the void. 17. The method of claim 15, wherein the step of forming a void further comprises drilling an opening into at least one of the plurality of layers of a dielectric ceramic, at least one of the plurality of conductive layers, or combinations thereof. 18. The method of claim 15, wherein the step of forming a void further comprises punching an opening into at least one of the plurality of layers of a dielectric ceramic, at least one of the plurality of conductive layers, or combinations thereof. 19. The method of claim 15, wherein the step of forming a void further comprises laser cutting an opening into at least one of the plurality of layers of a dielectric ceramic, at least one of the plurality of conductive layers, or combinations thereof. 20. The method of claim 15, wherein the steps of sintering and forming a void further comprises providing a fugitive material in at least one of the plurality of layers of dielectric material and burning away the fugitive material during the sintering step to form the void. 21. The method of claim 15, wherein electro-plating is used to bridge the plurality of conductive layers bounding the void in a manner that maintains the nonconductive capacitive connection between the layers. | 2,800 |
12,177 | 12,177 | 15,420,344 | 2,884 | A mobile X-ray system includes a movable base, a robotic arm mounted on the movable base, an X-ray source attached to the robotic arm, a radiation detector, one or more user interfaces, and a controller configured to determine a position of the X-ray source and a position of the detector and to automatically move the base and the robotic arm to align the X-ray source with the detector. | 1. A mobile X-ray system comprising:
a movable base; a robotic arm mounted on the movable base; an X-ray source attached to the robotic arm; a radiation detector; one or more user interfaces; and a controller configured to determine a position of the X-ray source and a position of the detector and to automatically move the base and the robotic arm to align the X-ray source with the detector. 2. The mobile X-ray system of claim 1, wherein the movable base comprises one or more drive wheels and a drive system configured to provide power to the one or more drive wheels. 3. The mobile X-ray system of claim 2, wherein the drive system is configured to provide steering forces in a horizontal plane and motive forces in a vertical plane to the one or more drive wheels. 4. The mobile X-ray system of claim 3, wherein the drive system is configured to provide the steering forces and motive forces to the one or more drive wheels to cause the mobile X-ray system to rotate around a vertical axis. 5. The mobile X-ray system of claim 1, wherein the robotic arm comprises a plurality of joints and arm members providing multiple degrees of freedom. 6. The mobile X-ray system of claim 1, comprising:
one or more first sensors mounted on the X-ray source and one or more second sensors mounted on the detector, wherein the first and second sensors are connected to the controller, and the controller is configured to determine the position of the X-ray source and the detector from signals produced by the first and second sensors. 7. The mobile X-ray system of claim 6, wherein the first sensors are distance sensors configured to measure a distance to the second sensors and transmit the distance information to the controller, and wherein the controller is configured to determine the position of the X-ray source and the detector from the distance information. 8. The mobile X-ray system of claim 6, wherein the first and second sensors are three dimensional position sensors configured to transmit three dimensional position information to the controller, and wherein the controller is configured to determine the position of the X-ray source and the detector from the three dimensional position information. 9. The mobile X-ray system of claim 1, wherein the one or more user interfaces comprises a first display screen and a camera mounted on opposite sides of the mobile X-ray system, wherein images collected by the camera are transmitted to the first user interface to provide a view of an area in front of the mobile X-ray system opposite the first display screen. 10. The mobile X-ray system of claim 1, wherein the one or more user interfaces comprises a second detachable display screen for controlling movement and image acquisition of the mobile X-ray system. 11. A method of operating a mobile X-ray system comprising:
using a sensor system to determine a position of an X-ray source and a position of a radiation detector of the mobile X-ray system; and using a controller to automatically move a movable base and a robotic arm of the mobile X-ray system to align the X-ray source with the detector based on signals from the sensor system. 12. The method of claim 11, further comprising using the controller to operate a drive system of the mobile X-ray system to provide power to one or more drive wheels to move the movable base. 13. The method of claim 12 comprising using the controller to operate the drive system to provide steering forces in a horizontal plane and motive forces in a vertical plane to the one or more drive wheels to move the movable base. 14. The method of claim 13, comprising using the controller to operate the drive system to provide the steering forces and motive forces to the one or more drive wheels to cause the mobile X-ray system to rotate around a vertical axis. 15. The method of claim 11, wherein the sensor system comprises one or more first sensors mounted on the X-ray source and one or more second sensors mounted on the detector, the method comprising using the controller to determine the position of the X-ray source and the detector from signals produced by the first and second sensors. 16. The method of claim 15, comprising:
using the first sensors to measure a distance to the second sensors and transmit the distance information to the controller; and using the controller to determine the position of the X-ray source and the detector from the distance information. 17. The method of claim 15, comprising:
using the first and second sensors to transmit three dimensional position information to the controller; and using the controller to determine the position of the X-ray source and the detector from the three dimensional position information. 18. The method of claim 11, comprising using a first display screen and a camera mounted on opposite sides of the mobile X-ray system to provide a view of an area in front of the mobile X-ray system opposite the first display screen. 19. The method of claim 11, comprising using a second detachable display screen for controlling movement and image acquisition of the mobile X-ray system. | A mobile X-ray system includes a movable base, a robotic arm mounted on the movable base, an X-ray source attached to the robotic arm, a radiation detector, one or more user interfaces, and a controller configured to determine a position of the X-ray source and a position of the detector and to automatically move the base and the robotic arm to align the X-ray source with the detector.1. A mobile X-ray system comprising:
a movable base; a robotic arm mounted on the movable base; an X-ray source attached to the robotic arm; a radiation detector; one or more user interfaces; and a controller configured to determine a position of the X-ray source and a position of the detector and to automatically move the base and the robotic arm to align the X-ray source with the detector. 2. The mobile X-ray system of claim 1, wherein the movable base comprises one or more drive wheels and a drive system configured to provide power to the one or more drive wheels. 3. The mobile X-ray system of claim 2, wherein the drive system is configured to provide steering forces in a horizontal plane and motive forces in a vertical plane to the one or more drive wheels. 4. The mobile X-ray system of claim 3, wherein the drive system is configured to provide the steering forces and motive forces to the one or more drive wheels to cause the mobile X-ray system to rotate around a vertical axis. 5. The mobile X-ray system of claim 1, wherein the robotic arm comprises a plurality of joints and arm members providing multiple degrees of freedom. 6. The mobile X-ray system of claim 1, comprising:
one or more first sensors mounted on the X-ray source and one or more second sensors mounted on the detector, wherein the first and second sensors are connected to the controller, and the controller is configured to determine the position of the X-ray source and the detector from signals produced by the first and second sensors. 7. The mobile X-ray system of claim 6, wherein the first sensors are distance sensors configured to measure a distance to the second sensors and transmit the distance information to the controller, and wherein the controller is configured to determine the position of the X-ray source and the detector from the distance information. 8. The mobile X-ray system of claim 6, wherein the first and second sensors are three dimensional position sensors configured to transmit three dimensional position information to the controller, and wherein the controller is configured to determine the position of the X-ray source and the detector from the three dimensional position information. 9. The mobile X-ray system of claim 1, wherein the one or more user interfaces comprises a first display screen and a camera mounted on opposite sides of the mobile X-ray system, wherein images collected by the camera are transmitted to the first user interface to provide a view of an area in front of the mobile X-ray system opposite the first display screen. 10. The mobile X-ray system of claim 1, wherein the one or more user interfaces comprises a second detachable display screen for controlling movement and image acquisition of the mobile X-ray system. 11. A method of operating a mobile X-ray system comprising:
using a sensor system to determine a position of an X-ray source and a position of a radiation detector of the mobile X-ray system; and using a controller to automatically move a movable base and a robotic arm of the mobile X-ray system to align the X-ray source with the detector based on signals from the sensor system. 12. The method of claim 11, further comprising using the controller to operate a drive system of the mobile X-ray system to provide power to one or more drive wheels to move the movable base. 13. The method of claim 12 comprising using the controller to operate the drive system to provide steering forces in a horizontal plane and motive forces in a vertical plane to the one or more drive wheels to move the movable base. 14. The method of claim 13, comprising using the controller to operate the drive system to provide the steering forces and motive forces to the one or more drive wheels to cause the mobile X-ray system to rotate around a vertical axis. 15. The method of claim 11, wherein the sensor system comprises one or more first sensors mounted on the X-ray source and one or more second sensors mounted on the detector, the method comprising using the controller to determine the position of the X-ray source and the detector from signals produced by the first and second sensors. 16. The method of claim 15, comprising:
using the first sensors to measure a distance to the second sensors and transmit the distance information to the controller; and using the controller to determine the position of the X-ray source and the detector from the distance information. 17. The method of claim 15, comprising:
using the first and second sensors to transmit three dimensional position information to the controller; and using the controller to determine the position of the X-ray source and the detector from the three dimensional position information. 18. The method of claim 11, comprising using a first display screen and a camera mounted on opposite sides of the mobile X-ray system to provide a view of an area in front of the mobile X-ray system opposite the first display screen. 19. The method of claim 11, comprising using a second detachable display screen for controlling movement and image acquisition of the mobile X-ray system. | 2,800 |
12,178 | 12,178 | 14,735,469 | 2,862 | Methods and systems for automated monitoring of sensors associated with a tool used in a manufacturing process are described. Sensor health may be evaluated based on the sensor's actual responses to set point changes. Rather than interrupt operation of the tool to determine whether one or more sensors are behaving in a predictable manner over an applicable range of operating conditions, pairs of set point values and sensor responses may be collected during the manufacturing process and stored in a time-indexed manner. A virtual model may be created for each sensor using selected ones of the indexed pairs and represented as points in an orthogonal coordinate system to identify a predictable operating region corresponding to the operating range. If a sensor response to a set point change, reflected in a stored, time indexed pair, is non-linear or offset relative to the predictable operating region, an alarm may be generated. | 1. A computer-implemented method for automated monitoring of behavior of at least one sensor having a predictable operating behavior expected over a range of operating conditions applicable to a manufacturing process, wherein the at least one sensor is associated with a tool operated during the manufacturing process and provides data sensitive to at least one of a tool state or a process state change, the method comprising:
while operating the tool during the manufacturing process,
collecting at each of a plurality of points in time, a respective set point associated with a target tool state or a target process state; and
collecting from the at least one sensor, at each of the plurality of points in time, a corresponding actual measurement value read back from the at least one sensor;
storing the collected set points and actual measurements together with an indication of an applicable time of actual measurement collection to create time indexed pairs of set points and actual measurements corresponding to operation of the tool; and evaluating health of the sensor based on actual measured response of the at least one sensor to set point changes represented by the indexed pairs. 2. The method of claim 1, wherein the evaluating includes modeling the sensor, using at least some of the time indexed pairs, as a virtual sensor to confirm predictability of behavior over an operating range encountered by the at least one sensor during the manufacturing process. 3. The method of claim 2, wherein the modeling includes representing the selected indexed pairs as points in an orthogonal coordinate system to identify a linear portion corresponding to the operating range. 4. The method of claim 3, further including
determining if a sensor response to a set point change reflected in a stored, time indexed pair is non-linear or offset relative to the identified linear portion; and generating and transmitting an alerting message if a sensor response to a set point change reflected in a time indexed pair is determined to be non-linear or offset relative to the identified linear portion. 5. The method of claim 1, wherein the at least one sensor includes a temperature sensor or a pressure sensor. 6. A computer-implemented method for automated monitoring of behavior of at least one sensor having a predictable operating behavior expected over a range of operating conditions applicable to a semiconductor manufacturing process, wherein the at least one sensor is associated with a semiconductor process tool operated during the semiconductor manufacturing process and provides data sensitive to at least one of a tool state or a process state change, the method comprising:
while operating the tool during the semiconductor manufacturing process,
collecting at each of a plurality of points in time, a respective set point associated with a target tool state or a target process state; and
collecting from the at least one sensor, at each of the plurality of points in time, a corresponding actual measurement value read back from the at least one sensor;
storing the collected set points and actual measurements together with an indication of an applicable time of actual measurement collection to create time indexed pairs of set points and actual measurements corresponding to operation of the tool; and evaluating health of the sensor based on actual measured response of the at least one sensor to set point changes represented by the indexed pairs. 7. The method of claim 6, wherein the tool employs a plurality of recipes in the fabrication of semiconductor devices, each recipe having a plurality of set points at different points in time. 8. The method of claim 7, wherein the evaluating includes modeling the sensor, using at least some of the time indexed pairs, as a virtual sensor to confirm predictability of behavior over an operating range encountered by the at least one sensor during the fabrication process. 9. The method of claim 7, wherein evaluating health of a sensor includes:
selecting a first set point and actual measured value pair corresponding to a lower limit of an operating range encountered by the tool and the sensor across at least one of a plurality of recipes employed during the fabrication process; selecting a second set point and actual measured value pair corresponding to an upper limit of an operating range encountered by the tool and the sensor across at least one of a plurality of recipes employed during the fabrication process; selecting at least one intermediate set point and actual measured value pair collected across at least one of a plurality of recipes employed during the fabrication process; and modeling the sensor, using the indexed pairs selected, as a virtual sensor to confirm predictability of behavior over the operating range. 10. The method of claim 9, wherein the modeling includes representing the selected indexed pairs as points in an orthogonal coordinate system to identify a linear portion corresponding to the operating range, and
wherein the method further includes determining if a sensor response to a set point change reflected in a stored, time indexed pair is non-linear or offset relative to the identified linear portion. 11. The method of claim 10, further including generating and transmitting an alarm message if a sensor response to a set point change reflected in a time indexed pair is determined to be one of non-linear or offset relative to the identified linear portion. 12. The method of claim 7, wherein set point and actual measured value pairs are selected and the modeling is performed after each recipe run to reduce a probability of substrate excursions. 13. A system for implementing an automatic and non-disruptive sensor health monitoring scheme during execution of a recipe on a substrate within a processing chamber of a plasma processing system as part of a device fabrication process, comprising:
at least one sensor configured to collect sensor data to facilitate monitoring set points during execution of said recipe; an interface configured to receive sensor data collected from the at least one sensor; and an analytical computer system communicably coupled with said interface and having a memory and a processor configured to execute instructions stored in memory, the processor being operative to execute instructions:
to store measurements returned by the at least one sensor in response to set point changes;
to associate each measurement returned by the at least one sensor with a corresponding set point and a time of measurement to form time indexed pairs; and
to evaluate health of the at least one sensor based on a plurality of measurements returned as a response to a corresponding set point change. 14. The system of claim 13, wherein stored instructions executable by the processor to evaluate sensor health include instructions to model the at least one sensor, using at least some of the time indexed pairs, as a virtual sensor for use in confirming predictability of behavior over an operating range encountered by the at least one sensor during execution of the recipe. 15. The system of claim 14, wherein stored instructions executable by the processor to model the sensor as a virtual sensor include instructions to represent selected indexed pairs as points in an orthogonal coordinate system and to identify a linear portion corresponding to the operating range encountered by the sensor during execution of the recipe. 16. The system of claim 15, wherein stored instructions executable by the processor to evaluate health of the sensor include instructions to determine if a sensor response, to a set point change reflected in a stored indexed pair, is non-linear or offset relative to the identified linear portion. 17. The system of claim 16, wherein stored instructions are executable by the processor to generate or transmit an alarm message if a sensor response, to a set point change reflected in an indexed pair, is determined to be linear or offset relative to the identified linear portion. 18. The system of claim 13, wherein stored instructions executable by the processor to evaluate sensor health include instructions:
to select a first set point and sensor measurement pair corresponding to a lower limit of an operating range encountered during execution of the recipe; to select a second set point and sensor measurement pair corresponding to an upper limit of an operating range encountered during execution of the recipe; to select at least one intermediate set point and sensor measurement pair collected encountered during execution of the recipe; and to model the at least one sensor, using the selected pairs, as a virtual sensor for use in confirming predictability of behavior over the operating range. 19. The system of claim 18, wherein stored instructions executable by the processor to model the sensor as a virtual sensor include instructions to represent selected indexed pairs as points in an orthogonal coordinate system and to identify a linear portion corresponding to the operating range encountered by the at least one sensor during execution of the recipe. 20. The system of claim 19, wherein stored instructions executable by the processor to evaluate health of the sensor include instructions to determine if a sensor response, to a set point change reflected in a stored indexed pair, is non-linear or offset relative to the identified linear portion, and
wherein stored instructions are executable by the processor to generate and transmit an alarm message if a sensor response, to a set point change reflected in an indexed pair, is determined to be non-linear or offset relative to the identified linear portion. | Methods and systems for automated monitoring of sensors associated with a tool used in a manufacturing process are described. Sensor health may be evaluated based on the sensor's actual responses to set point changes. Rather than interrupt operation of the tool to determine whether one or more sensors are behaving in a predictable manner over an applicable range of operating conditions, pairs of set point values and sensor responses may be collected during the manufacturing process and stored in a time-indexed manner. A virtual model may be created for each sensor using selected ones of the indexed pairs and represented as points in an orthogonal coordinate system to identify a predictable operating region corresponding to the operating range. If a sensor response to a set point change, reflected in a stored, time indexed pair, is non-linear or offset relative to the predictable operating region, an alarm may be generated.1. A computer-implemented method for automated monitoring of behavior of at least one sensor having a predictable operating behavior expected over a range of operating conditions applicable to a manufacturing process, wherein the at least one sensor is associated with a tool operated during the manufacturing process and provides data sensitive to at least one of a tool state or a process state change, the method comprising:
while operating the tool during the manufacturing process,
collecting at each of a plurality of points in time, a respective set point associated with a target tool state or a target process state; and
collecting from the at least one sensor, at each of the plurality of points in time, a corresponding actual measurement value read back from the at least one sensor;
storing the collected set points and actual measurements together with an indication of an applicable time of actual measurement collection to create time indexed pairs of set points and actual measurements corresponding to operation of the tool; and evaluating health of the sensor based on actual measured response of the at least one sensor to set point changes represented by the indexed pairs. 2. The method of claim 1, wherein the evaluating includes modeling the sensor, using at least some of the time indexed pairs, as a virtual sensor to confirm predictability of behavior over an operating range encountered by the at least one sensor during the manufacturing process. 3. The method of claim 2, wherein the modeling includes representing the selected indexed pairs as points in an orthogonal coordinate system to identify a linear portion corresponding to the operating range. 4. The method of claim 3, further including
determining if a sensor response to a set point change reflected in a stored, time indexed pair is non-linear or offset relative to the identified linear portion; and generating and transmitting an alerting message if a sensor response to a set point change reflected in a time indexed pair is determined to be non-linear or offset relative to the identified linear portion. 5. The method of claim 1, wherein the at least one sensor includes a temperature sensor or a pressure sensor. 6. A computer-implemented method for automated monitoring of behavior of at least one sensor having a predictable operating behavior expected over a range of operating conditions applicable to a semiconductor manufacturing process, wherein the at least one sensor is associated with a semiconductor process tool operated during the semiconductor manufacturing process and provides data sensitive to at least one of a tool state or a process state change, the method comprising:
while operating the tool during the semiconductor manufacturing process,
collecting at each of a plurality of points in time, a respective set point associated with a target tool state or a target process state; and
collecting from the at least one sensor, at each of the plurality of points in time, a corresponding actual measurement value read back from the at least one sensor;
storing the collected set points and actual measurements together with an indication of an applicable time of actual measurement collection to create time indexed pairs of set points and actual measurements corresponding to operation of the tool; and evaluating health of the sensor based on actual measured response of the at least one sensor to set point changes represented by the indexed pairs. 7. The method of claim 6, wherein the tool employs a plurality of recipes in the fabrication of semiconductor devices, each recipe having a plurality of set points at different points in time. 8. The method of claim 7, wherein the evaluating includes modeling the sensor, using at least some of the time indexed pairs, as a virtual sensor to confirm predictability of behavior over an operating range encountered by the at least one sensor during the fabrication process. 9. The method of claim 7, wherein evaluating health of a sensor includes:
selecting a first set point and actual measured value pair corresponding to a lower limit of an operating range encountered by the tool and the sensor across at least one of a plurality of recipes employed during the fabrication process; selecting a second set point and actual measured value pair corresponding to an upper limit of an operating range encountered by the tool and the sensor across at least one of a plurality of recipes employed during the fabrication process; selecting at least one intermediate set point and actual measured value pair collected across at least one of a plurality of recipes employed during the fabrication process; and modeling the sensor, using the indexed pairs selected, as a virtual sensor to confirm predictability of behavior over the operating range. 10. The method of claim 9, wherein the modeling includes representing the selected indexed pairs as points in an orthogonal coordinate system to identify a linear portion corresponding to the operating range, and
wherein the method further includes determining if a sensor response to a set point change reflected in a stored, time indexed pair is non-linear or offset relative to the identified linear portion. 11. The method of claim 10, further including generating and transmitting an alarm message if a sensor response to a set point change reflected in a time indexed pair is determined to be one of non-linear or offset relative to the identified linear portion. 12. The method of claim 7, wherein set point and actual measured value pairs are selected and the modeling is performed after each recipe run to reduce a probability of substrate excursions. 13. A system for implementing an automatic and non-disruptive sensor health monitoring scheme during execution of a recipe on a substrate within a processing chamber of a plasma processing system as part of a device fabrication process, comprising:
at least one sensor configured to collect sensor data to facilitate monitoring set points during execution of said recipe; an interface configured to receive sensor data collected from the at least one sensor; and an analytical computer system communicably coupled with said interface and having a memory and a processor configured to execute instructions stored in memory, the processor being operative to execute instructions:
to store measurements returned by the at least one sensor in response to set point changes;
to associate each measurement returned by the at least one sensor with a corresponding set point and a time of measurement to form time indexed pairs; and
to evaluate health of the at least one sensor based on a plurality of measurements returned as a response to a corresponding set point change. 14. The system of claim 13, wherein stored instructions executable by the processor to evaluate sensor health include instructions to model the at least one sensor, using at least some of the time indexed pairs, as a virtual sensor for use in confirming predictability of behavior over an operating range encountered by the at least one sensor during execution of the recipe. 15. The system of claim 14, wherein stored instructions executable by the processor to model the sensor as a virtual sensor include instructions to represent selected indexed pairs as points in an orthogonal coordinate system and to identify a linear portion corresponding to the operating range encountered by the sensor during execution of the recipe. 16. The system of claim 15, wherein stored instructions executable by the processor to evaluate health of the sensor include instructions to determine if a sensor response, to a set point change reflected in a stored indexed pair, is non-linear or offset relative to the identified linear portion. 17. The system of claim 16, wherein stored instructions are executable by the processor to generate or transmit an alarm message if a sensor response, to a set point change reflected in an indexed pair, is determined to be linear or offset relative to the identified linear portion. 18. The system of claim 13, wherein stored instructions executable by the processor to evaluate sensor health include instructions:
to select a first set point and sensor measurement pair corresponding to a lower limit of an operating range encountered during execution of the recipe; to select a second set point and sensor measurement pair corresponding to an upper limit of an operating range encountered during execution of the recipe; to select at least one intermediate set point and sensor measurement pair collected encountered during execution of the recipe; and to model the at least one sensor, using the selected pairs, as a virtual sensor for use in confirming predictability of behavior over the operating range. 19. The system of claim 18, wherein stored instructions executable by the processor to model the sensor as a virtual sensor include instructions to represent selected indexed pairs as points in an orthogonal coordinate system and to identify a linear portion corresponding to the operating range encountered by the at least one sensor during execution of the recipe. 20. The system of claim 19, wherein stored instructions executable by the processor to evaluate health of the sensor include instructions to determine if a sensor response, to a set point change reflected in a stored indexed pair, is non-linear or offset relative to the identified linear portion, and
wherein stored instructions are executable by the processor to generate and transmit an alarm message if a sensor response, to a set point change reflected in an indexed pair, is determined to be non-linear or offset relative to the identified linear portion. | 2,800 |
12,179 | 12,179 | 16,158,599 | 2,861 | A sensor system for a sub-surface system is disclosed, comprising a pressure sensor positioned in a first orientation; a gravity sensor arranged proximate to the pressure sensor, the gravity sensor detecting gravitational force on the pressure sensor relative to the first orientation; and a data acquisition system operatively connected to each of the pressure sensor and the gravity sensor, the data acquisition system determining a gravity compensated pressure value detected by the pressure sensor corrected for gravitational force on the pressure sensor relative to the first orientation. | 1. A sensor system for a sub-surface system comprising:
a pressure sensor positioned in a first orientation; a gravity sensor arranged proximate to the pressure sensor, the gravity sensor detecting gravitational force on the pressure sensor relative to the first orientation; and a data acquisition system operatively connected to each of the pressure sensor and the gravity sensor, the data acquisition system determining a gravity compensated pressure value detected by the pressure sensor corrected for gravitational force on the pressure sensor relative to the first orientation. 2. The sensor system according to claim 1, wherein the pressure sensor is surrounded by an isolation fluid. 3. The sensor system according to claim 1, wherein the pressure sensor comprises a strain gauge. 4. The sensor system according to claim 1, wherein the pressure sensor comprises a quartz based sensor. 5. The sensor system according to claim 1, wherein the pressure sensor and the gravity sensor are arranged in a common package. 6. The sensor system according to claim 1, wherein each of the pressure sensor and the gravity sensor are mounted to a tubular extending into a sub-surface formation. 7. The sensor system according to claim 1, wherein the gravity sensor comprises an accelerometer. 8. A sensor system comprising:
a pressure sensor positioned in a first orientation; and a data acquisition system operatively connected to the pressure sensor, the data acquisition system determining a gravity compensated pressure value detected by the pressure sensor corrected for gravitational force on the pressure sensor relative to the first orientation. 9. The sensor system according to claim 8, wherein the data acquisition system includes a non-volatile memory having stored thereon a gravity compensated pressure value for the pressure sensor. 10. The sensor system according to claim 8, wherein the pressure sensor is surrounded by an isolation fluid. 11. The sensor system according to claim 8, wherein the pressure sensor comprises a strain gauge. 12. The sensor system according to claim 8, wherein the pressure sensor comprises a quartz based sensor. 13. The sensor system according to claim 8, wherein the pressure sensor is mounted to a tubular extending into a sub-surface formation. 14. A method of calibrating a pressure sensor comprising:
positioning the pressure sensor in a calibration system in a first orientation; positioning a gravity sensor in the calibration system; sensing a gravitational force on the pressure sensor relative to the first orientation; determining a calibration coefficient of the pressure sensor; and determining a gravity based correction factor based on a the gravitational force on the pressure sensor relative to the first orientation. | A sensor system for a sub-surface system is disclosed, comprising a pressure sensor positioned in a first orientation; a gravity sensor arranged proximate to the pressure sensor, the gravity sensor detecting gravitational force on the pressure sensor relative to the first orientation; and a data acquisition system operatively connected to each of the pressure sensor and the gravity sensor, the data acquisition system determining a gravity compensated pressure value detected by the pressure sensor corrected for gravitational force on the pressure sensor relative to the first orientation.1. A sensor system for a sub-surface system comprising:
a pressure sensor positioned in a first orientation; a gravity sensor arranged proximate to the pressure sensor, the gravity sensor detecting gravitational force on the pressure sensor relative to the first orientation; and a data acquisition system operatively connected to each of the pressure sensor and the gravity sensor, the data acquisition system determining a gravity compensated pressure value detected by the pressure sensor corrected for gravitational force on the pressure sensor relative to the first orientation. 2. The sensor system according to claim 1, wherein the pressure sensor is surrounded by an isolation fluid. 3. The sensor system according to claim 1, wherein the pressure sensor comprises a strain gauge. 4. The sensor system according to claim 1, wherein the pressure sensor comprises a quartz based sensor. 5. The sensor system according to claim 1, wherein the pressure sensor and the gravity sensor are arranged in a common package. 6. The sensor system according to claim 1, wherein each of the pressure sensor and the gravity sensor are mounted to a tubular extending into a sub-surface formation. 7. The sensor system according to claim 1, wherein the gravity sensor comprises an accelerometer. 8. A sensor system comprising:
a pressure sensor positioned in a first orientation; and a data acquisition system operatively connected to the pressure sensor, the data acquisition system determining a gravity compensated pressure value detected by the pressure sensor corrected for gravitational force on the pressure sensor relative to the first orientation. 9. The sensor system according to claim 8, wherein the data acquisition system includes a non-volatile memory having stored thereon a gravity compensated pressure value for the pressure sensor. 10. The sensor system according to claim 8, wherein the pressure sensor is surrounded by an isolation fluid. 11. The sensor system according to claim 8, wherein the pressure sensor comprises a strain gauge. 12. The sensor system according to claim 8, wherein the pressure sensor comprises a quartz based sensor. 13. The sensor system according to claim 8, wherein the pressure sensor is mounted to a tubular extending into a sub-surface formation. 14. A method of calibrating a pressure sensor comprising:
positioning the pressure sensor in a calibration system in a first orientation; positioning a gravity sensor in the calibration system; sensing a gravitational force on the pressure sensor relative to the first orientation; determining a calibration coefficient of the pressure sensor; and determining a gravity based correction factor based on a the gravitational force on the pressure sensor relative to the first orientation. | 2,800 |
12,180 | 12,180 | 15,887,209 | 2,834 | A hand-held tool that includes a housing. The housing includes a handle. A tool also includes a motor assembly, a battery assembly and a circuit board. The motor assembly includes a motor, the motor including a rotatable motor output shaft, a motor positive terminal and a motor negative terminal. The motor assembly also includes a first rigid conductive electrical connector having a first end fixed to the motor positive terminal and a second end fixed to the circuit board. The battery assembly includes a battery cell with a battery cell positive terminal and a battery cell negative terminal. The battery assembly further includes a second rigid conductive electrical connector having a first end fixed to the battery cell positive terminal and a second end fixed to the circuit board. | 1. A hand-held tool, comprising:
a housing, the housing including a handle; a motor assembly; a battery assembly; and a circuit board; wherein the motor assembly includes a motor, the motor including a rotatable motor output shaft, a motor positive terminal and a motor negative terminal; wherein the motor assembly further includes a first rigid conductive electrical connector having a first end fixed to the motor positive terminal and a second end fixed to the circuit board; wherein the battery assembly includes a battery cell with a battery cell positive terminal and a battery cell negative terminal; wherein the battery assembly further includes a second rigid conductive electrical connector having a first end fixed to the battery cell positive terminal and a second end fixed to the circuit board. 2. The hand-held tool of claim 1, wherein the first rigid conductive electrical connector is soldered to the circuit board. 3. The hand-held tool of claim 2, wherein the second rigid conductive electrical connector is soldered to the circuit board. 4. The hand-held tool of claim 1, wherein the first rigid conductive electrical connector is fixed to the circuit board by a tulip connector. 5. The hand-held tool of claim 1, further comprising a switch configured to selectively turn on the motor. 6. The hand-held tool of claim 5, further comprising a socket electrically connected to the battery cell through which a charge can be provided to the battery cell. 7. The hand-held tool of claim 1, wherein the first rigid conductive electrical connector and the second rigid conductive electrical connector are a stamped metal connectors. 8. The hand-held tool of claim 1, wherein the hand-held tool is a cordless hand-held vacuum cleaner. 9. The hand-held tool of claim 1, wherein the hand-held tool is a cordless screwdriver. 10. A hand-held tool, comprising:
a housing, the housing including a handle; a motor assembly including a motor; a battery assembly; a circuit board; and a switch configured to selectively turn on the motor; wherein the battery assembly includes a battery cell with a battery cell positive terminal and a battery cell negative terminal; wherein the battery assembly further includes a first rigid conductive electrical connector having a first end fixed to the battery cell positive terminal and a second end fixed to the circuit board and a second rigid conductive electrical connector having a first end fixed to the battery cell negative terminal and a second end fixed to the circuit board. wherein the battery cell includes a longitudinal axis which is disposed at an angle with respect to the circuit board, the angle being between 10 degrees and 90 degrees. 11. The hand-held tool of claim 10, wherein at least one of the first rigid conductive electrical connector and the second rigid conductive electrical connector runs parallel to the longitudinal axis of the battery cell. 12. The hand-held tool of claim 10, wherein the first rigid conductive electrical connector and the second rigid conductive electrical connector are a stamped metal connectors. 13. The hand-held tool of claim 10, wherein the first rigid conductive electrical connector is soldered to the circuit board; and
wherein the second rigid conductive electrical connector is soldered to the circuit board. 14. The hand-held tool of claim 10, wherein the first rigid conductive electrical connector is fixed to the circuit board by a tulip connector; and
wherein the second rigid conductive electrical connector is fixed to the circuit board by a tulip connector. 15. The hand-held tool of claim 10, wherein the hand-held tool comprises one of a hand-held vacuum cleaner and a hand-held screwdriver. 16. A hand-held tool, comprising:
a housing, the housing including a handle; a motor assembly including a motor; a first battery assembly and a second battery assembly; a circuit board; and a switch configured to selectively turn on the motor; wherein the first battery assembly and the second battery assembly each include a battery cell with a battery cell positive terminal and a battery cell negative terminal; wherein each of the first battery assembly and the second battery assembly further includes a first rigid conductive electrical connector having a first end fixed to the battery cell positive terminal and a second end fixed to the circuit board and a second rigid conductive electrical connector having a first end fixed to the battery cell negative terminal and a second end fixed to the circuit board; wherein the first battery assembly is disposed in the housing at a first side of the motor; and wherein the second battery assembly is disposed in the housing at a second side of the motor, opposite the first side of the motor. 17. The hand-held tool of claim 16, wherein the motor has a longitudinal axis and the battery cells of the first battery assembly and the second battery assembly are disposed parallel to the longitudinal axis of the motor. 18. The hand-held tool of claim 17, wherein the motor longitudinal axis is at an angle of between 10 degrees and 90 degrees with respect to the circuit board. 19. The hand-held tool of claim 16, wherein the motor includes a rotatable motor output shaft, a motor positive terminal and a motor negative terminal; and
wherein the motor positive terminal and the motor negative terminal are connected to the circuit board by motor rigid conductive electrical connectors. 20. The hand-held tool of claim 16, wherein the first rigid conductive electrical connector and the second rigid conductive electrical connector are stamped metal connectors. | A hand-held tool that includes a housing. The housing includes a handle. A tool also includes a motor assembly, a battery assembly and a circuit board. The motor assembly includes a motor, the motor including a rotatable motor output shaft, a motor positive terminal and a motor negative terminal. The motor assembly also includes a first rigid conductive electrical connector having a first end fixed to the motor positive terminal and a second end fixed to the circuit board. The battery assembly includes a battery cell with a battery cell positive terminal and a battery cell negative terminal. The battery assembly further includes a second rigid conductive electrical connector having a first end fixed to the battery cell positive terminal and a second end fixed to the circuit board.1. A hand-held tool, comprising:
a housing, the housing including a handle; a motor assembly; a battery assembly; and a circuit board; wherein the motor assembly includes a motor, the motor including a rotatable motor output shaft, a motor positive terminal and a motor negative terminal; wherein the motor assembly further includes a first rigid conductive electrical connector having a first end fixed to the motor positive terminal and a second end fixed to the circuit board; wherein the battery assembly includes a battery cell with a battery cell positive terminal and a battery cell negative terminal; wherein the battery assembly further includes a second rigid conductive electrical connector having a first end fixed to the battery cell positive terminal and a second end fixed to the circuit board. 2. The hand-held tool of claim 1, wherein the first rigid conductive electrical connector is soldered to the circuit board. 3. The hand-held tool of claim 2, wherein the second rigid conductive electrical connector is soldered to the circuit board. 4. The hand-held tool of claim 1, wherein the first rigid conductive electrical connector is fixed to the circuit board by a tulip connector. 5. The hand-held tool of claim 1, further comprising a switch configured to selectively turn on the motor. 6. The hand-held tool of claim 5, further comprising a socket electrically connected to the battery cell through which a charge can be provided to the battery cell. 7. The hand-held tool of claim 1, wherein the first rigid conductive electrical connector and the second rigid conductive electrical connector are a stamped metal connectors. 8. The hand-held tool of claim 1, wherein the hand-held tool is a cordless hand-held vacuum cleaner. 9. The hand-held tool of claim 1, wherein the hand-held tool is a cordless screwdriver. 10. A hand-held tool, comprising:
a housing, the housing including a handle; a motor assembly including a motor; a battery assembly; a circuit board; and a switch configured to selectively turn on the motor; wherein the battery assembly includes a battery cell with a battery cell positive terminal and a battery cell negative terminal; wherein the battery assembly further includes a first rigid conductive electrical connector having a first end fixed to the battery cell positive terminal and a second end fixed to the circuit board and a second rigid conductive electrical connector having a first end fixed to the battery cell negative terminal and a second end fixed to the circuit board. wherein the battery cell includes a longitudinal axis which is disposed at an angle with respect to the circuit board, the angle being between 10 degrees and 90 degrees. 11. The hand-held tool of claim 10, wherein at least one of the first rigid conductive electrical connector and the second rigid conductive electrical connector runs parallel to the longitudinal axis of the battery cell. 12. The hand-held tool of claim 10, wherein the first rigid conductive electrical connector and the second rigid conductive electrical connector are a stamped metal connectors. 13. The hand-held tool of claim 10, wherein the first rigid conductive electrical connector is soldered to the circuit board; and
wherein the second rigid conductive electrical connector is soldered to the circuit board. 14. The hand-held tool of claim 10, wherein the first rigid conductive electrical connector is fixed to the circuit board by a tulip connector; and
wherein the second rigid conductive electrical connector is fixed to the circuit board by a tulip connector. 15. The hand-held tool of claim 10, wherein the hand-held tool comprises one of a hand-held vacuum cleaner and a hand-held screwdriver. 16. A hand-held tool, comprising:
a housing, the housing including a handle; a motor assembly including a motor; a first battery assembly and a second battery assembly; a circuit board; and a switch configured to selectively turn on the motor; wherein the first battery assembly and the second battery assembly each include a battery cell with a battery cell positive terminal and a battery cell negative terminal; wherein each of the first battery assembly and the second battery assembly further includes a first rigid conductive electrical connector having a first end fixed to the battery cell positive terminal and a second end fixed to the circuit board and a second rigid conductive electrical connector having a first end fixed to the battery cell negative terminal and a second end fixed to the circuit board; wherein the first battery assembly is disposed in the housing at a first side of the motor; and wherein the second battery assembly is disposed in the housing at a second side of the motor, opposite the first side of the motor. 17. The hand-held tool of claim 16, wherein the motor has a longitudinal axis and the battery cells of the first battery assembly and the second battery assembly are disposed parallel to the longitudinal axis of the motor. 18. The hand-held tool of claim 17, wherein the motor longitudinal axis is at an angle of between 10 degrees and 90 degrees with respect to the circuit board. 19. The hand-held tool of claim 16, wherein the motor includes a rotatable motor output shaft, a motor positive terminal and a motor negative terminal; and
wherein the motor positive terminal and the motor negative terminal are connected to the circuit board by motor rigid conductive electrical connectors. 20. The hand-held tool of claim 16, wherein the first rigid conductive electrical connector and the second rigid conductive electrical connector are stamped metal connectors. | 2,800 |
12,181 | 12,181 | 15,760,033 | 2,863 | A method for determining the rotational rate of a movable member using an array of inertial sensors is provided. The method includes defining a hidden Markov model (“HMM”). The HMM represents a discrete value measurement of the rotational rate of the movable member. A transition probability of the HMM accounts for a motion model (linear or non-linear) of the movable member. An observation probability of the HMM accounts for noise and bias of at least one of the inertial sensors of the array of inertial sensors. A processor receives input from the array of inertial sensors. The processor determines the rotational rate of the movable member by solving for an output of the HMM using the input received from the array of inertial sensors. The processor may use a forward algorithm, a forward-backward algorithm, or a Viterbi algorithm to solve the HMM. | 1. A method for determining rotational rate of a movable member using an array of inertial sensors, the method comprising:
defining a hidden Markov model (“HMM”), wherein hidden states of the HMM represent a discrete value measurement of the rotational rate of the movable member, and transition probability of the HHM accounts for a motion model of the movable member, and observation probability accounts for noise and bias of at least one of the inertial sensors in the array of inertial sensors; receiving, by a processor, input from the array of inertial sensors; and determining, by the processor, the rotational rate of the movable member by solving for an output of the HMM using the input received from the array of inertial sensors. 2. The method of claim 1, wherein a forward algorithm is used by the processor to solve the HMM. 3. The method of claim 1, wherein a forward-backward algorithm or a Viterbi algorithm is used by the processor to solve the HMM. 4. The method of claim 1, wherein each inertial sensor of the array of inertial sensors outputs a rotational rate and is coupled to the movable member. 5. The method of claim 1, wherein the hidden states represent a plurality of angular rates measured at a plurality of timesteps. 6. The method of claim 1, wherein an angular rate of the movable member at a first timestep is probabilistically conditioned on an angular rate of the movable member a second timestep. 7. The method of claim 1, further comprising:
applying a pre-filter to obtain an approximate of the rotational rate of the movable member; and using the approximate rotational rate to discretize a state space to achieve a reduction in computation time for the HMM. 8. The method of claim 1, wherein the motion model for the movable member is non-linear. 9. The method of claim 1, wherein the motion model has a probability peak at zero velocity and uniform probability elsewhere. 10. The method of claim 1, wherein the motion model is a learned motion model trained from a training set. 11. The method of claim 1, wherein the observation probability is non-linear. 12. The method of claim 1, further comprising:
maintaining as a constant a state space size as the number of inertial sensors of the array of inertial sensors increases. 13. The method of claim 1, wherein the observation probability further comprises:
the bias for each inertial sensor of the array of inertial sensors, wherein the bias is determined using a filtered angular rate estimate. 14. The method of claim 1, wherein the observation probability further comprises:
an angle random walk modeled as an additive Gaussian white noise process. 15. The method of claim 1, wherein bias is modeled as a random walk produced by integrating zero-mean Gaussian walk noise. 16. The method of claim 1, wherein the inertial sensors of the array of inertial sensors are non-homogenous. 17. The method of claim 1, wherein the inertial sensors of the array of inertial sensors are gyroscopes. 18. An apparatus comprising:
a platform, wherein the platform comprises
an array of inertial sensors coupled to the platform, and
a processor coupled to the platform that receives inputs from each inertial sensors of the array of inertial sensors; and
a movable member coupled to the platform, wherein
each inertial sensor of the array of sensors outputs a rotational rate of the movable member,
the processor defines a hidden Markov model (“HMM”), wherein hidden states of the HMM represent a discrete value measurement of the rotational rate of the movable member, and transition probability of the HHM accounts for a motion model of the movable member, and observation probability accounts for noise and bias of at least one of the inertial sensor in the array of inertial sensors; and
the processor determines the rotational rate of the movable member by solving for an output of the HMM using the input received from the array of inertial sensors. 19. The apparatus of claim 18, wherein the processor uses a forward algorithm to solve the HMM. 20. The apparatus of claim 18, wherein a state space size is constant as the number of inertial sensors of the array of inertial sensors increases. 21. The apparatus of claim 18, wherein the bias for each inertial sensor of the array of inertial sensors is determined using a filtered angular rate estimate. 22. The apparatus of claim 18, wherein a pre-filter is used to approximate the rotational rate of the movable member, and the approximate rotational rate is used to discretize a state space to achieve a reduction in computation time for the HMM. 23. The apparatus of claim 18, wherein the motion model for the movable member is non-linear. 24. The apparatus of claim 18, wherein the inertial sensors of the array of inertial sensors are mounted in different plans and orientations with respect to each other. 25. The apparatus of claim 18, wherein the inertial sensors of the array of inertial sensors have different sensitivities and dynamic ranges. | A method for determining the rotational rate of a movable member using an array of inertial sensors is provided. The method includes defining a hidden Markov model (“HMM”). The HMM represents a discrete value measurement of the rotational rate of the movable member. A transition probability of the HMM accounts for a motion model (linear or non-linear) of the movable member. An observation probability of the HMM accounts for noise and bias of at least one of the inertial sensors of the array of inertial sensors. A processor receives input from the array of inertial sensors. The processor determines the rotational rate of the movable member by solving for an output of the HMM using the input received from the array of inertial sensors. The processor may use a forward algorithm, a forward-backward algorithm, or a Viterbi algorithm to solve the HMM.1. A method for determining rotational rate of a movable member using an array of inertial sensors, the method comprising:
defining a hidden Markov model (“HMM”), wherein hidden states of the HMM represent a discrete value measurement of the rotational rate of the movable member, and transition probability of the HHM accounts for a motion model of the movable member, and observation probability accounts for noise and bias of at least one of the inertial sensors in the array of inertial sensors; receiving, by a processor, input from the array of inertial sensors; and determining, by the processor, the rotational rate of the movable member by solving for an output of the HMM using the input received from the array of inertial sensors. 2. The method of claim 1, wherein a forward algorithm is used by the processor to solve the HMM. 3. The method of claim 1, wherein a forward-backward algorithm or a Viterbi algorithm is used by the processor to solve the HMM. 4. The method of claim 1, wherein each inertial sensor of the array of inertial sensors outputs a rotational rate and is coupled to the movable member. 5. The method of claim 1, wherein the hidden states represent a plurality of angular rates measured at a plurality of timesteps. 6. The method of claim 1, wherein an angular rate of the movable member at a first timestep is probabilistically conditioned on an angular rate of the movable member a second timestep. 7. The method of claim 1, further comprising:
applying a pre-filter to obtain an approximate of the rotational rate of the movable member; and using the approximate rotational rate to discretize a state space to achieve a reduction in computation time for the HMM. 8. The method of claim 1, wherein the motion model for the movable member is non-linear. 9. The method of claim 1, wherein the motion model has a probability peak at zero velocity and uniform probability elsewhere. 10. The method of claim 1, wherein the motion model is a learned motion model trained from a training set. 11. The method of claim 1, wherein the observation probability is non-linear. 12. The method of claim 1, further comprising:
maintaining as a constant a state space size as the number of inertial sensors of the array of inertial sensors increases. 13. The method of claim 1, wherein the observation probability further comprises:
the bias for each inertial sensor of the array of inertial sensors, wherein the bias is determined using a filtered angular rate estimate. 14. The method of claim 1, wherein the observation probability further comprises:
an angle random walk modeled as an additive Gaussian white noise process. 15. The method of claim 1, wherein bias is modeled as a random walk produced by integrating zero-mean Gaussian walk noise. 16. The method of claim 1, wherein the inertial sensors of the array of inertial sensors are non-homogenous. 17. The method of claim 1, wherein the inertial sensors of the array of inertial sensors are gyroscopes. 18. An apparatus comprising:
a platform, wherein the platform comprises
an array of inertial sensors coupled to the platform, and
a processor coupled to the platform that receives inputs from each inertial sensors of the array of inertial sensors; and
a movable member coupled to the platform, wherein
each inertial sensor of the array of sensors outputs a rotational rate of the movable member,
the processor defines a hidden Markov model (“HMM”), wherein hidden states of the HMM represent a discrete value measurement of the rotational rate of the movable member, and transition probability of the HHM accounts for a motion model of the movable member, and observation probability accounts for noise and bias of at least one of the inertial sensor in the array of inertial sensors; and
the processor determines the rotational rate of the movable member by solving for an output of the HMM using the input received from the array of inertial sensors. 19. The apparatus of claim 18, wherein the processor uses a forward algorithm to solve the HMM. 20. The apparatus of claim 18, wherein a state space size is constant as the number of inertial sensors of the array of inertial sensors increases. 21. The apparatus of claim 18, wherein the bias for each inertial sensor of the array of inertial sensors is determined using a filtered angular rate estimate. 22. The apparatus of claim 18, wherein a pre-filter is used to approximate the rotational rate of the movable member, and the approximate rotational rate is used to discretize a state space to achieve a reduction in computation time for the HMM. 23. The apparatus of claim 18, wherein the motion model for the movable member is non-linear. 24. The apparatus of claim 18, wherein the inertial sensors of the array of inertial sensors are mounted in different plans and orientations with respect to each other. 25. The apparatus of claim 18, wherein the inertial sensors of the array of inertial sensors have different sensitivities and dynamic ranges. | 2,800 |
12,182 | 12,182 | 15,657,104 | 2,855 | A system for capacitive liquid level measurement of liquid in a container, including a level sensor with level+ and level− electrodes, driven out-of-phase to project a sensing electric field into the container, and a reference sensor with ref+ and ref− electrodes, driven out-of-phase to project a sensing electric field into the container. Sensor electronics drives the level sensor electrodes level+/− and the reference sensor electrodes ref+/− out of phase to project respective level and reference capacitance sensing fields into the container, and acquires respective level and reference capacitance measurements from the level and reference sensors. The level and reference capacitance measurement are converted into data representative of liquid level in the container. The level and reference capacitance measurements can be differentially converted according to: Liquid Level=(h L −h R ) [MEAS 1 /MEAS 1 (h L )]+h R , where MEAS 1 =Cin 1 −Cin 2. | 1. A system for capacitive liquid level measurement, comprising:
a container with liquid; a level sensor with level+ and level− electrodes, driven out-of-phase to project a sensing electric field into the container; a reference sensor with ref+ and ref− electrodes, driven out-of-phase to project a sensing electric field into the container; sensor electronics to
drive the level sensor electrodes level+/− and the reference sensor electrodes ref+/− out of phase to project respective level and reference capacitance sensing fields into the container, and
acquire respective level and reference capacitance measurements from the level and reference sensors, and
differentially convert the level and reference capacitance measurements into data representative of liquid level in the container. 2. The system of claim 1, wherein the level and reference capacitance measurements are differentially converted according to: Liquid Level=(hL−hR) [MEAS1/MEAS1(hL)]+hR, where MEAS1=Cin1−Cin2. 3. The system of claim 1, wherein the container comprises a first container, and further comprising:
a second container disposed adjacent the first container; a printed circuit board (PCB) disposed between the first and second containers; the PCB including a first PCB side adjacent the first container, and a second PCB side adjacent the second container;
the first PCB side including differential level and reference sensors for the first tank, and
the second PCB side including differential level and reference sensors for the second tank. | A system for capacitive liquid level measurement of liquid in a container, including a level sensor with level+ and level− electrodes, driven out-of-phase to project a sensing electric field into the container, and a reference sensor with ref+ and ref− electrodes, driven out-of-phase to project a sensing electric field into the container. Sensor electronics drives the level sensor electrodes level+/− and the reference sensor electrodes ref+/− out of phase to project respective level and reference capacitance sensing fields into the container, and acquires respective level and reference capacitance measurements from the level and reference sensors. The level and reference capacitance measurement are converted into data representative of liquid level in the container. The level and reference capacitance measurements can be differentially converted according to: Liquid Level=(h L −h R ) [MEAS 1 /MEAS 1 (h L )]+h R , where MEAS 1 =Cin 1 −Cin 2.1. A system for capacitive liquid level measurement, comprising:
a container with liquid; a level sensor with level+ and level− electrodes, driven out-of-phase to project a sensing electric field into the container; a reference sensor with ref+ and ref− electrodes, driven out-of-phase to project a sensing electric field into the container; sensor electronics to
drive the level sensor electrodes level+/− and the reference sensor electrodes ref+/− out of phase to project respective level and reference capacitance sensing fields into the container, and
acquire respective level and reference capacitance measurements from the level and reference sensors, and
differentially convert the level and reference capacitance measurements into data representative of liquid level in the container. 2. The system of claim 1, wherein the level and reference capacitance measurements are differentially converted according to: Liquid Level=(hL−hR) [MEAS1/MEAS1(hL)]+hR, where MEAS1=Cin1−Cin2. 3. The system of claim 1, wherein the container comprises a first container, and further comprising:
a second container disposed adjacent the first container; a printed circuit board (PCB) disposed between the first and second containers; the PCB including a first PCB side adjacent the first container, and a second PCB side adjacent the second container;
the first PCB side including differential level and reference sensors for the first tank, and
the second PCB side including differential level and reference sensors for the second tank. | 2,800 |
12,183 | 12,183 | 14,440,510 | 2,822 | An ultraviolet light detector has a pn-junction of wide-gap semiconductors layers, where a p-type semiconductor layer with a polycrystalline metal oxide contacts an n-type semiconductor layer of metal oxide nanoparticles, or the converse. The ultraviolet detector is prepared using solvent based deposition methods and where temperatures can be maintained below 300° C. | 1. An ultraviolet light detector, comprising a pn-j unction of wide-gap semiconductors layers, wherein a p-type semiconductor layer comprising a polycrystalline metal oxide contacts an n-type semiconductor layer comprising a multiplicity of metal oxide nanoparticles. 2. The ultraviolet light detector according to claim 1, wherein the polycrystalline metal oxide comprises NiO, Mn:SnO2, CuAlO2, CuGaO2, CuInO2, or SrCu2O2. 3. The ultraviolet light detector according to claim 1, wherein the metal oxide nanoparticles comprise ZnO, TiO2, MoO3, or V2O5. 4. The ultraviolet light detector according to claim 1, wherein the metal oxide nanoparticles are 2 to 100 nm in cross-section. 5. A method to prepare an ultraviolet light detector according to claim 1, comprising:
providing a substrate; depositing an electrode layer on the substrate; depositing a p-type polycrystalline metal oxide layer; depositing an n-type nanoparticulate metal oxide layer; and depositing a counter-electrode layer. 6. The method of claim 5, wherein the electrode layer is an anode. 7. The method of claim 5, wherein depositing a p-type polycrystalline metal oxide layer comprises: placing a solution of a metal oxide precursor on the electrode layer or on the n-type nanoparticulate metal oxide layer; removing the solvent of the solution to form a film of a solute, and heating the film of the solute to form the p-type polycrystalline metal oxide layer. 8. The method of claim 7, wherein heating is to a temperature less than 300° C. 9. The method of claim 5, wherein depositing an n-type nanoparticulate metal oxide layer comprises: providing a multiplicity of metal oxide nanoparticles; suspending the metal oxide nanoparticles in a fluid to form a suspension; placing the suspension on the electrode or on the p-type polycrystalline metal oxide layer; and removing the fluid to form the n-type nanoparticulate metal oxide layer. 10. An ultraviolet light detector, comprising a pn-junction of wide-gap semiconductors layers, wherein an n-type semiconductor layer comprising a polycrystalline metal oxide contacts a p-type semiconductor layer comprising a multiplicity of metal oxide nanoparticles. 11. The ultraviolet light detector according to claim 10, wherein the polycrystalline metal oxide comprises ZnO, TiO2, MoO3, or V2O5. 12. The ultraviolet light detector according to claim 10, wherein the metal oxide nanoparticles comprise NiO, Mn:SnO2, CuAlO2, CuGaO2, CuInO2, or SrCu2O2. 13. The ultraviolet light detector according to claim 10, wherein the metal oxide nanoparticles are 2 to 100 nm in cross-section. 14. A method to prepare an ultraviolet light detector according to claim 10, comprising:
providing a substrate; depositing an electrode layer on the substrate; depositing an n-type polycrystalline metal oxide layer; depositing a p-type nanoparticulate metal oxide layer; and depositing a counter-electrode layer. 15. The method of claim 14, wherein the electrode layer is a cathode. 16. The method of claim 14, wherein depositing a p-type polycrystalline metal oxide layer comprises: placing a solution of a metal oxide precursor on the electrode layer or on the n-type nanoparticulate metal oxide layer; removing the solvent of the solution to form a film of a solute, and heating the film of the solute to form the p-type polycrystalline metal oxide layer. 17. The method of claim 14, wherein depositing an n-type nanoparticulate metal oxide layer comprises: providing a multiplicity of metal oxide nanoparticles; suspending the metal oxide nanoparticles in a fluid to form a suspension; placing the suspension on the electrode or on the p-type polycrystalline metal oxide layer; and removing the fluid to form the n-type nanoparticulate metal oxide layer. | An ultraviolet light detector has a pn-junction of wide-gap semiconductors layers, where a p-type semiconductor layer with a polycrystalline metal oxide contacts an n-type semiconductor layer of metal oxide nanoparticles, or the converse. The ultraviolet detector is prepared using solvent based deposition methods and where temperatures can be maintained below 300° C.1. An ultraviolet light detector, comprising a pn-j unction of wide-gap semiconductors layers, wherein a p-type semiconductor layer comprising a polycrystalline metal oxide contacts an n-type semiconductor layer comprising a multiplicity of metal oxide nanoparticles. 2. The ultraviolet light detector according to claim 1, wherein the polycrystalline metal oxide comprises NiO, Mn:SnO2, CuAlO2, CuGaO2, CuInO2, or SrCu2O2. 3. The ultraviolet light detector according to claim 1, wherein the metal oxide nanoparticles comprise ZnO, TiO2, MoO3, or V2O5. 4. The ultraviolet light detector according to claim 1, wherein the metal oxide nanoparticles are 2 to 100 nm in cross-section. 5. A method to prepare an ultraviolet light detector according to claim 1, comprising:
providing a substrate; depositing an electrode layer on the substrate; depositing a p-type polycrystalline metal oxide layer; depositing an n-type nanoparticulate metal oxide layer; and depositing a counter-electrode layer. 6. The method of claim 5, wherein the electrode layer is an anode. 7. The method of claim 5, wherein depositing a p-type polycrystalline metal oxide layer comprises: placing a solution of a metal oxide precursor on the electrode layer or on the n-type nanoparticulate metal oxide layer; removing the solvent of the solution to form a film of a solute, and heating the film of the solute to form the p-type polycrystalline metal oxide layer. 8. The method of claim 7, wherein heating is to a temperature less than 300° C. 9. The method of claim 5, wherein depositing an n-type nanoparticulate metal oxide layer comprises: providing a multiplicity of metal oxide nanoparticles; suspending the metal oxide nanoparticles in a fluid to form a suspension; placing the suspension on the electrode or on the p-type polycrystalline metal oxide layer; and removing the fluid to form the n-type nanoparticulate metal oxide layer. 10. An ultraviolet light detector, comprising a pn-junction of wide-gap semiconductors layers, wherein an n-type semiconductor layer comprising a polycrystalline metal oxide contacts a p-type semiconductor layer comprising a multiplicity of metal oxide nanoparticles. 11. The ultraviolet light detector according to claim 10, wherein the polycrystalline metal oxide comprises ZnO, TiO2, MoO3, or V2O5. 12. The ultraviolet light detector according to claim 10, wherein the metal oxide nanoparticles comprise NiO, Mn:SnO2, CuAlO2, CuGaO2, CuInO2, or SrCu2O2. 13. The ultraviolet light detector according to claim 10, wherein the metal oxide nanoparticles are 2 to 100 nm in cross-section. 14. A method to prepare an ultraviolet light detector according to claim 10, comprising:
providing a substrate; depositing an electrode layer on the substrate; depositing an n-type polycrystalline metal oxide layer; depositing a p-type nanoparticulate metal oxide layer; and depositing a counter-electrode layer. 15. The method of claim 14, wherein the electrode layer is a cathode. 16. The method of claim 14, wherein depositing a p-type polycrystalline metal oxide layer comprises: placing a solution of a metal oxide precursor on the electrode layer or on the n-type nanoparticulate metal oxide layer; removing the solvent of the solution to form a film of a solute, and heating the film of the solute to form the p-type polycrystalline metal oxide layer. 17. The method of claim 14, wherein depositing an n-type nanoparticulate metal oxide layer comprises: providing a multiplicity of metal oxide nanoparticles; suspending the metal oxide nanoparticles in a fluid to form a suspension; placing the suspension on the electrode or on the p-type polycrystalline metal oxide layer; and removing the fluid to form the n-type nanoparticulate metal oxide layer. | 2,800 |
12,184 | 12,184 | 16,599,238 | 2,831 | According to one embodiment, a controller may include a user interface that is operable to receive input from a user to control an electronic system to which the controller may be coupled either directly or indirectly. The user interface may comprise an interface housing to which the user interface is coupled, the interface housing having a front portion and a rear portion, the front portion of which may contain the user interface. A controller housing may be coupled to the rear portion of the interface housing, the controller housing having a smaller perimeter than the interface housing. The controller housing may be comprised of at least one sidewall and a rear wall. At least one magnet may be coupled to the controller housing. The magnet(s) may be operable to hold the controller in position using magnetic force when the controller housing is inserted into a mounting receptacle. | 1. A controller system, comprising:
an electrical junction box; a mounting receptacle inserted into and coupled to the junction box; a user interface operable to receive input from a user, wherein the user interface comprises an interface housing to which the user interface is coupled, the interface housing having a front portion and a rear portion, the front portion containing the user interface; a controller housing coupled to the rear portion of the user interface housing, the controller housing comprised of at least one sidewall and a rear wall; at least one magnet coupled to the controller housing, the at least one magnet operable to hold the controller in position using magnetic force when the controller housing is inserted into the mounting receptacle. 2. The controller system of claim 1, wherein the user interface comprises an electronic display. 3. The controller system of claim 1, wherein the user interface comprises a touchscreen. 4. The controller system of claim 1, wherein the user interface comprises a keypad. 5. The controller system of claim 1, wherein the user interface comprises at least one key and an electronic display. 6. The controller system of claim 1, wherein the at least one magnet is glued to the controller housing. 7. The controller system of claim 1, wherein
the rear wall of the controller housing comprises at least one connector port configured to receive a data communication cable connector. 8. A controller system, comprising:
a mounting receptacle adapted to be coupled into a junction box; a controller, the controller including
a user interface operable to receive input from a user, wherein the user interface comprises a user interface housing to which the user interface is coupled, the user interface housing having a front portion and a rear portion, the front portion containing the user interface;
a controller housing coupled to the rear portion of the user interface housing, the controller housing comprised of at least one sidewall and a rear wall;
at least one magnet coupled to the controller, the at least one magnet operable to hold the controller in position using magnetic force when the controller is inserted into a mounting receptacle; and wherein when the controller is inserted into the mounting receptacle, there is a magnetic force between the at least one magnet and the mounting receptacle. 9. The controller system of claim 8, wherein the user interface comprises an electronic display. 10. The controller system of claim 8, wherein the user interface comprises a touchscreen. 11. The controller system of claim 8, wherein the user interface comprises a keypad. 12. The controller system of claim 8, wherein the user interface comprises at least one key and an electronic display. 13. The controller system of claim 8, wherein at least a portion of the mounting receptacle comprises a ferromagnetic material. 14. The controller system of claim 8, wherein the rear wall of the controller housing comprises at least one connector port configured to receive a data communication cable connector. 15. The controller system of claim 8, wherein the controller has a wireless interface to an external device. 16. The controller system of claim 8, wherein the at least one magnet comprises a plurality of magnets, wherein the controller housing has multiple sidewalls, and wherein the at least two of the plurality of magnets are coupled to different ones of the multiple sidewalls. 17. The controller system of claim 8, wherein the mounting receptacle comprises a metal ring made of ferromagnetic metal. 18. The controller system of claim 8, wherein the mounting receptacle comprises at least one piece of ferromagnetic metal coupled to a nonmagnetic material. 19. The controller system of claim 8, wherein the user interface is further operable to provide output to a user. 20. The controller system of claim 8, wherein the mounting receptacle comprises a metal ring made of ferromagnetic metal;
wherein the at least one magnet comprises a plurality of magnets coupled to one or more sidewalls of the controller housing; and wherein the controller housing has a closed back comprising at least one connector port configured to receive a data communication cable connector. 21. The controller system of claim 3, wherein the at least one magnet coupled to the controller has a first polarity, the controller system further comprising:
at least a second magnet coupled to the mounting receptacle, wherein the second magnet has a second polarity wherein the first and second magnet are operable to hold the controller in position using magnetic force between the first magnet and second magnet when the controller is inserted into the mounting receptacle. | According to one embodiment, a controller may include a user interface that is operable to receive input from a user to control an electronic system to which the controller may be coupled either directly or indirectly. The user interface may comprise an interface housing to which the user interface is coupled, the interface housing having a front portion and a rear portion, the front portion of which may contain the user interface. A controller housing may be coupled to the rear portion of the interface housing, the controller housing having a smaller perimeter than the interface housing. The controller housing may be comprised of at least one sidewall and a rear wall. At least one magnet may be coupled to the controller housing. The magnet(s) may be operable to hold the controller in position using magnetic force when the controller housing is inserted into a mounting receptacle.1. A controller system, comprising:
an electrical junction box; a mounting receptacle inserted into and coupled to the junction box; a user interface operable to receive input from a user, wherein the user interface comprises an interface housing to which the user interface is coupled, the interface housing having a front portion and a rear portion, the front portion containing the user interface; a controller housing coupled to the rear portion of the user interface housing, the controller housing comprised of at least one sidewall and a rear wall; at least one magnet coupled to the controller housing, the at least one magnet operable to hold the controller in position using magnetic force when the controller housing is inserted into the mounting receptacle. 2. The controller system of claim 1, wherein the user interface comprises an electronic display. 3. The controller system of claim 1, wherein the user interface comprises a touchscreen. 4. The controller system of claim 1, wherein the user interface comprises a keypad. 5. The controller system of claim 1, wherein the user interface comprises at least one key and an electronic display. 6. The controller system of claim 1, wherein the at least one magnet is glued to the controller housing. 7. The controller system of claim 1, wherein
the rear wall of the controller housing comprises at least one connector port configured to receive a data communication cable connector. 8. A controller system, comprising:
a mounting receptacle adapted to be coupled into a junction box; a controller, the controller including
a user interface operable to receive input from a user, wherein the user interface comprises a user interface housing to which the user interface is coupled, the user interface housing having a front portion and a rear portion, the front portion containing the user interface;
a controller housing coupled to the rear portion of the user interface housing, the controller housing comprised of at least one sidewall and a rear wall;
at least one magnet coupled to the controller, the at least one magnet operable to hold the controller in position using magnetic force when the controller is inserted into a mounting receptacle; and wherein when the controller is inserted into the mounting receptacle, there is a magnetic force between the at least one magnet and the mounting receptacle. 9. The controller system of claim 8, wherein the user interface comprises an electronic display. 10. The controller system of claim 8, wherein the user interface comprises a touchscreen. 11. The controller system of claim 8, wherein the user interface comprises a keypad. 12. The controller system of claim 8, wherein the user interface comprises at least one key and an electronic display. 13. The controller system of claim 8, wherein at least a portion of the mounting receptacle comprises a ferromagnetic material. 14. The controller system of claim 8, wherein the rear wall of the controller housing comprises at least one connector port configured to receive a data communication cable connector. 15. The controller system of claim 8, wherein the controller has a wireless interface to an external device. 16. The controller system of claim 8, wherein the at least one magnet comprises a plurality of magnets, wherein the controller housing has multiple sidewalls, and wherein the at least two of the plurality of magnets are coupled to different ones of the multiple sidewalls. 17. The controller system of claim 8, wherein the mounting receptacle comprises a metal ring made of ferromagnetic metal. 18. The controller system of claim 8, wherein the mounting receptacle comprises at least one piece of ferromagnetic metal coupled to a nonmagnetic material. 19. The controller system of claim 8, wherein the user interface is further operable to provide output to a user. 20. The controller system of claim 8, wherein the mounting receptacle comprises a metal ring made of ferromagnetic metal;
wherein the at least one magnet comprises a plurality of magnets coupled to one or more sidewalls of the controller housing; and wherein the controller housing has a closed back comprising at least one connector port configured to receive a data communication cable connector. 21. The controller system of claim 3, wherein the at least one magnet coupled to the controller has a first polarity, the controller system further comprising:
at least a second magnet coupled to the mounting receptacle, wherein the second magnet has a second polarity wherein the first and second magnet are operable to hold the controller in position using magnetic force between the first magnet and second magnet when the controller is inserted into the mounting receptacle. | 2,800 |
12,185 | 12,185 | 15,493,862 | 2,859 | A system of a vehicle includes a processor configured to control output current of a remote power distribution circuit (PDC) connected to the vehicle according to a temperature change of a power line or return line of the PDC. The temperature change is derived from a PDC output voltage or output current change. The PDC output voltage and output current are measured at an input to a load connected to the PDC. And, the PDC output voltage is measured between a ground line of the PDC and one of the power and return lines. | 1. A system of a vehicle comprising:
a processor configured to control output current of a remote power distribution circuit (PDC) connected to the vehicle according to a temperature change of a power line or return line of the PDC that is derived from a PDC output voltage or output current change, the PDC output voltage and output current being measured at an input to a load connected to the PDC, and the PDC output voltage being measured between a ground line of the PDC and one of the power and return lines. 2. The system of claim 1, wherein the processor is further configured to transmit messages including data related to the PDC output voltage, the PDC output voltage change, the PDC output current, or the PDC output current change. 3. The system of claim 1, wherein the processor is further configured to transmit off-board the vehicle messages including data related to the PDC output voltage, the PDC output voltage change, the PDC output current, or the PDC output current change. 4. The system of claim 1, wherein the processor is included within a battery charger. 5. The system of claim 1, wherein the return line is a neutral line. 6. A system of a vehicle comprising:
a processor configured to control output current of a remote power distribution circuit (PDC) connected to the vehicle according to a temperature change of a power or return line of the PDC derived from a PDC output voltage change that is measured at an input to a load connected to the PDC and between a ground line of the PDC and one of the power and return lines. 7. The system of claim 6, wherein the processor is further configured to transmit messages including data related to the PDC output voltage change. 8. The system of claim 6, wherein the processor is further configured to transmit off-board the vehicle messages including data related to the PDC output voltage change. 9. The system of claim 6, wherein the processor is included within a battery charger. 10. The system of claim 6, wherein the return line is a neutral line. 11. A power system of a vehicle comprising:
a processor configured to control output current of a remote power distribution circuit (PDC) connected to the vehicle according to a temperature change of a power line or return line of the PDC that is derived from a change in a PDC output voltage, a PDC output current, an input voltage to a load connected to the PDC, or an input current to the load, the PDC output voltage and output current being measured at an input to the load, and the PDC output voltage being measured between a ground line of the PDC and one of the power and return lines. 12. The system of claim 11, wherein the processor is further configured to transmit messages including data related to the PDC output voltage, the PDC output current, the input voltage to the load connected to the PDC, or the input current to the load. 13. The system of claim 11, wherein the processor is further configured to transmit off-board the vehicle messages including data related to the PDC output voltage, the PDC output current, the input voltage to the load connected to the PDC, or the input current to the load. 14. The system of claim 11, wherein the processor is included within a battery charger. 15. The system of claim 11, wherein the return line is a neutral line. | A system of a vehicle includes a processor configured to control output current of a remote power distribution circuit (PDC) connected to the vehicle according to a temperature change of a power line or return line of the PDC. The temperature change is derived from a PDC output voltage or output current change. The PDC output voltage and output current are measured at an input to a load connected to the PDC. And, the PDC output voltage is measured between a ground line of the PDC and one of the power and return lines.1. A system of a vehicle comprising:
a processor configured to control output current of a remote power distribution circuit (PDC) connected to the vehicle according to a temperature change of a power line or return line of the PDC that is derived from a PDC output voltage or output current change, the PDC output voltage and output current being measured at an input to a load connected to the PDC, and the PDC output voltage being measured between a ground line of the PDC and one of the power and return lines. 2. The system of claim 1, wherein the processor is further configured to transmit messages including data related to the PDC output voltage, the PDC output voltage change, the PDC output current, or the PDC output current change. 3. The system of claim 1, wherein the processor is further configured to transmit off-board the vehicle messages including data related to the PDC output voltage, the PDC output voltage change, the PDC output current, or the PDC output current change. 4. The system of claim 1, wherein the processor is included within a battery charger. 5. The system of claim 1, wherein the return line is a neutral line. 6. A system of a vehicle comprising:
a processor configured to control output current of a remote power distribution circuit (PDC) connected to the vehicle according to a temperature change of a power or return line of the PDC derived from a PDC output voltage change that is measured at an input to a load connected to the PDC and between a ground line of the PDC and one of the power and return lines. 7. The system of claim 6, wherein the processor is further configured to transmit messages including data related to the PDC output voltage change. 8. The system of claim 6, wherein the processor is further configured to transmit off-board the vehicle messages including data related to the PDC output voltage change. 9. The system of claim 6, wherein the processor is included within a battery charger. 10. The system of claim 6, wherein the return line is a neutral line. 11. A power system of a vehicle comprising:
a processor configured to control output current of a remote power distribution circuit (PDC) connected to the vehicle according to a temperature change of a power line or return line of the PDC that is derived from a change in a PDC output voltage, a PDC output current, an input voltage to a load connected to the PDC, or an input current to the load, the PDC output voltage and output current being measured at an input to the load, and the PDC output voltage being measured between a ground line of the PDC and one of the power and return lines. 12. The system of claim 11, wherein the processor is further configured to transmit messages including data related to the PDC output voltage, the PDC output current, the input voltage to the load connected to the PDC, or the input current to the load. 13. The system of claim 11, wherein the processor is further configured to transmit off-board the vehicle messages including data related to the PDC output voltage, the PDC output current, the input voltage to the load connected to the PDC, or the input current to the load. 14. The system of claim 11, wherein the processor is included within a battery charger. 15. The system of claim 11, wherein the return line is a neutral line. | 2,800 |
12,186 | 12,186 | 15,431,528 | 2,811 | A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used. | 1. A method of making a semiconductor device, comprising:
providing a first semiconductor die including a first protection circuit; disposing a second semiconductor die including a second protection circuit over the first semiconductor die; and forming an interconnect structure to commonly connect the first protection circuit and second protection circuit, wherein a transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. 2. The method of claim 1, further including removing a portion of the first semiconductor die and second semiconductor die to reduce die thickness. 3. The method of claim 1, wherein forming the interconnect structure includes:
forming a first conductive via through the first semiconductor die; forming a second conductive via through the second semiconductor die; and connecting the first conductive via to the second conductive via. 4. The method of claim 1, further including:
providing a substrate; disposing the first semiconductor die and second semiconductor die over the substrate; and depositing an encapsulant over the first semiconductor die, second semiconductor die, and substrate. 5. The method of claim 1, further including:
providing a first semiconductor wafer including the first semiconductor die; disposing a second semiconductor wafer including the second semiconductor die over the first semiconductor wafer; and singulating the first semiconductor wafer and second semiconductor wafer leaving the second semiconductor die disposed over the first semiconductor die. 6. The method of claim 1, further including:
providing a first semiconductor wafer including the first semiconductor die; disposing the second semiconductor die over the first semiconductor wafer after singulating the second semiconductor die from a second semiconductor wafer; and singulating the first semiconductor wafer leaving the second semiconductor die disposed over the first semiconductor die. 7. A method of making a semiconductor device, comprising:
providing a first semiconductor die including a first protection circuit; disposing a second semiconductor die including a second protection circuit over the first semiconductor die with a first conductive via of the first semiconductor die aligned to a second conductive via of the second semiconductor die; and providing an interconnect structure between the first conductive via and second conductive via. 8. The method of claim 7, wherein providing the interconnect structure includes:
forming a first contact pad on a surface of the first semiconductor die over the first conductive via; forming a second contact pad on a surface of the second semiconductor die over the second conductive via; and bonding the first contact pad to the second contact pad by thermocompression. 9. The method of claim 7, wherein providing the interconnect structure includes:
forming a contact pad on a surface of the second semiconductor die and aligned with the first conductive via; and disposing a conductive bump between the contact pad and the first conductive via. 10. The method of claim 7, further including disposing the second semiconductor die over the first semiconductor die while the first semiconductor die remains as part of a first semiconductor wafer. 11. The method of claim 10, further including disposing the second semiconductor die over the first semiconductor die while the second semiconductor die remains as part of a second semiconductor wafer. 12. The method of claim 7, further including disposing the first semiconductor die and second semiconductor die over a leadframe with the first conductive via and second conductive via directly over a first terminal of the leadframe. 13. The method of claim 12, further including depositing an encapsulant over the first semiconductor die, second semiconductor die, and leadframe, wherein the first protection circuit and second protection circuit are electrically coupled in parallel between the first terminal of the leadframe and a second terminal of the leadframe. 14. A method of making a semiconductor device, comprising:
providing a first semiconductor die including a first protection circuit; and disposing a second semiconductor die including a second protection circuit over the first semiconductor die with the first protection circuit and second protection circuit electrically coupled in parallel. 15. The method of claim 14, further including disposing the first semiconductor die and second semiconductor die over a leadframe, with the first protection circuit and second protection circuit electrically coupled in parallel between a first terminal of the leadframe and a second terminal of the leadframe. 16. The method of claim 15, further including bonding the first semiconductor die to the leadframe using a conductive bump. 17. The method of claim 14, further including bonding the first semiconductor die to the second semiconductor die using a conductive bump. 18. The method of claim 14, further including bonding the first semiconductor die to the second semiconductor die using thermocompression. 19. The method of claim 14, further including:
forming a conductive via in the first semiconductor die; backgrinding the first semiconductor die to expose the conductive via; and disposing the second semiconductor die over the first semiconductor die with a contact pad of the second semiconductor die aligned with the conductive via. 20. A semiconductor device, comprising:
a first semiconductor die including a first protection circuit; a second semiconductor die including a second protection circuit disposed over the first semiconductor die; and a leadframe, with the first protection circuit and second protection circuit electrically coupled in parallel between a first terminal of the leadframe and a second terminal of the leadframe. 21. The semiconductor device of claim 20, wherein the first protection circuit includes a first transient voltage suppression (TVS) diode and the second protection circuit includes a second TVS diode. 22. The semiconductor device of claim 20, further including a contact pad of the first semiconductor die directly bonded to a second contact pad of the second semiconductor die. 23. The semiconductor device of claim 20, further including a first conductive bump extending from the first semiconductor die to the second semiconductor die. 24. The semiconductor device of claim 23, further including a second conductive bump extending from the first semiconductor die to the leadframe. 25. The semiconductor device of claim 24, further including a conductive via formed through the first semiconductor die between the first conductive bump and second conductive bump. | A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.1. A method of making a semiconductor device, comprising:
providing a first semiconductor die including a first protection circuit; disposing a second semiconductor die including a second protection circuit over the first semiconductor die; and forming an interconnect structure to commonly connect the first protection circuit and second protection circuit, wherein a transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. 2. The method of claim 1, further including removing a portion of the first semiconductor die and second semiconductor die to reduce die thickness. 3. The method of claim 1, wherein forming the interconnect structure includes:
forming a first conductive via through the first semiconductor die; forming a second conductive via through the second semiconductor die; and connecting the first conductive via to the second conductive via. 4. The method of claim 1, further including:
providing a substrate; disposing the first semiconductor die and second semiconductor die over the substrate; and depositing an encapsulant over the first semiconductor die, second semiconductor die, and substrate. 5. The method of claim 1, further including:
providing a first semiconductor wafer including the first semiconductor die; disposing a second semiconductor wafer including the second semiconductor die over the first semiconductor wafer; and singulating the first semiconductor wafer and second semiconductor wafer leaving the second semiconductor die disposed over the first semiconductor die. 6. The method of claim 1, further including:
providing a first semiconductor wafer including the first semiconductor die; disposing the second semiconductor die over the first semiconductor wafer after singulating the second semiconductor die from a second semiconductor wafer; and singulating the first semiconductor wafer leaving the second semiconductor die disposed over the first semiconductor die. 7. A method of making a semiconductor device, comprising:
providing a first semiconductor die including a first protection circuit; disposing a second semiconductor die including a second protection circuit over the first semiconductor die with a first conductive via of the first semiconductor die aligned to a second conductive via of the second semiconductor die; and providing an interconnect structure between the first conductive via and second conductive via. 8. The method of claim 7, wherein providing the interconnect structure includes:
forming a first contact pad on a surface of the first semiconductor die over the first conductive via; forming a second contact pad on a surface of the second semiconductor die over the second conductive via; and bonding the first contact pad to the second contact pad by thermocompression. 9. The method of claim 7, wherein providing the interconnect structure includes:
forming a contact pad on a surface of the second semiconductor die and aligned with the first conductive via; and disposing a conductive bump between the contact pad and the first conductive via. 10. The method of claim 7, further including disposing the second semiconductor die over the first semiconductor die while the first semiconductor die remains as part of a first semiconductor wafer. 11. The method of claim 10, further including disposing the second semiconductor die over the first semiconductor die while the second semiconductor die remains as part of a second semiconductor wafer. 12. The method of claim 7, further including disposing the first semiconductor die and second semiconductor die over a leadframe with the first conductive via and second conductive via directly over a first terminal of the leadframe. 13. The method of claim 12, further including depositing an encapsulant over the first semiconductor die, second semiconductor die, and leadframe, wherein the first protection circuit and second protection circuit are electrically coupled in parallel between the first terminal of the leadframe and a second terminal of the leadframe. 14. A method of making a semiconductor device, comprising:
providing a first semiconductor die including a first protection circuit; and disposing a second semiconductor die including a second protection circuit over the first semiconductor die with the first protection circuit and second protection circuit electrically coupled in parallel. 15. The method of claim 14, further including disposing the first semiconductor die and second semiconductor die over a leadframe, with the first protection circuit and second protection circuit electrically coupled in parallel between a first terminal of the leadframe and a second terminal of the leadframe. 16. The method of claim 15, further including bonding the first semiconductor die to the leadframe using a conductive bump. 17. The method of claim 14, further including bonding the first semiconductor die to the second semiconductor die using a conductive bump. 18. The method of claim 14, further including bonding the first semiconductor die to the second semiconductor die using thermocompression. 19. The method of claim 14, further including:
forming a conductive via in the first semiconductor die; backgrinding the first semiconductor die to expose the conductive via; and disposing the second semiconductor die over the first semiconductor die with a contact pad of the second semiconductor die aligned with the conductive via. 20. A semiconductor device, comprising:
a first semiconductor die including a first protection circuit; a second semiconductor die including a second protection circuit disposed over the first semiconductor die; and a leadframe, with the first protection circuit and second protection circuit electrically coupled in parallel between a first terminal of the leadframe and a second terminal of the leadframe. 21. The semiconductor device of claim 20, wherein the first protection circuit includes a first transient voltage suppression (TVS) diode and the second protection circuit includes a second TVS diode. 22. The semiconductor device of claim 20, further including a contact pad of the first semiconductor die directly bonded to a second contact pad of the second semiconductor die. 23. The semiconductor device of claim 20, further including a first conductive bump extending from the first semiconductor die to the second semiconductor die. 24. The semiconductor device of claim 23, further including a second conductive bump extending from the first semiconductor die to the leadframe. 25. The semiconductor device of claim 24, further including a conductive via formed through the first semiconductor die between the first conductive bump and second conductive bump. | 2,800 |
12,187 | 12,187 | 16,240,071 | 2,881 | A system, method, and apparatus for heating a workpiece in chamber provides one or more surfaces generally enclosing a chamber volume. Vacuum and purge gas ports are in in fluid communication with the chamber volume. A heater apparatus selectively heats the workpiece on a workpiece support to a predetermined temperature and generates an outgassed material within the chamber volume. A vacuum valve provides selective fluid communication between a vacuum source and the vacuum port. A purge gas valve provides selective fluid communication between a purge gas source for a purge gas and the purge gas port. A controller controls the vacuum and purge gas valves to selectively flow the purge gas from the purge gas port to the vacuum port at a predetermined pressure while the workpiece is heated, thus removing and preventing condensation of the outgassed material on the chamber surfaces. | 1. A workpiece processing system, comprising:
a process chamber; a chamber having one or more surfaces generally enclosing a chamber volume, and wherein the chamber comprises a vacuum port and a purge gas port in fluid communication with the chamber volume, wherein the chamber generally defines a load lock chamber operably coupled to the process chamber; a workpiece support positioned within the chamber and configured to selectively support a workpiece; a heater apparatus configured to selectively heat the workpiece to a predetermined temperature, whereby heating the workpiece generates an outgassed material within the chamber volume; a vacuum source; a vacuum valve configured to provide selective fluid communication between the vacuum source and the vacuum port; a purge gas source having a purge gas associated therewith; a purge gas valve configured to provide selective fluid communication between the purge gas source and the purge gas port; and a controller configured to control the vacuum valve and purge gas valve to selectively flow the purge gas from the purge gas port to the vacuum port at a predetermined pressure concurrent with heating of the workpiece, thereby generally evacuating the outgassed material from the chamber volume and preventing a condensation of the outgassed material on the one or more surfaces. 2. The workpiece processing system of claim 1, further comprising:
a first loadlock valve operably coupled to the chamber and configured to provide selective fluid communication between the chamber volume and a first environment, and wherein the first loadlock valve is further configured to selectively pass the workpiece between the chamber volume and the first environment; and a second loadlock valve operably coupled to the chamber and configured to provide selective fluid communication between the chamber volume and a second environment associated with the process chamber, and wherein the second loadlock valve is further configured to selectively pass the workpiece between the chamber volume and second environment. 3. The workpiece processing system of claim 2, wherein the controller is further configured to selectively open and close the first loadlock valve, thereby selectively isolating the chamber volume from the first environment, and wherein the controller is further configured to selectively open and close the second loadlock valve, thereby selectively isolating the chamber volume from the second environment. 4. The workpiece processing system of claim 3, wherein the first environment comprises an atmospheric environment at atmospheric pressure, and wherein the second environment comprises a vacuum environment at a vacuum pressure, and wherein the controller is configured to flow the purge gas from the purge gas port to the vacuum port concurrent with the second loadlock valve isolating the chamber volume from the second environment. 5. The workpiece processing system of claim 4, wherein the controller is configured to flow the purge gas from the purge gas port to the vacuum port concurrent with the second loadlock valve isolating the chamber volume from the second environment and the first loadlock valve isolating the chamber volume from the first environment. 6. The workpiece processing system of claim 1, wherein the controller is configured open the purge gas valve and vacuum valve concurrent with the heating of the workpiece, thereby further concurrently flowing the purge gas from the purge gas port to the vacuum port at the predetermined pressure. 7. The workpiece processing system of claim 6, wherein the purge gas valve comprises a purge gas regulator, and wherein the vacuum valve comprises a vacuum regulator, wherein the purge gas regulator and vacuum regulator are configured to provide the predetermined pressure when the purge gas is flowed from the purge gas port to the vacuum port. 8. The workpiece processing system of claim 7, wherein the controller is further configured to control one or more of the purge gas regulator and vacuum regulator, thereby controlling the predetermined pressure. 9. The workpiece processing system of claim 7, wherein one or more of the purge gas regulator and vacuum regulator comprise manual regulators. 10. The workpiece processing system of claim 1, wherein the predetermined pressure is approximately atmospheric pressure. 11. The workpiece processing system of claim 1, further comprising a temperature measurement apparatus configured to determine a measured temperature of the workpiece, wherein the controller is further configured to control the vacuum valve and purge gas valve based, at least in part, on the measured temperature of the workpiece. 12. The workpiece processing system of claim 1, wherein the controller is further configured to control the vacuum valve and purge gas valve based, at least in part, on a predetermined time. 13. The workpiece processing system of claim 1, wherein the workpiece support comprises a heated platen having a support surface configured to contact a backside of the workpiece, wherein the heated platen generally defines the heater apparatus. 14. The workpiece processing system of claim 13, wherein the workpiece support comprise one or more pins configured to selectively raise and lower the workpiece onto a support surface associated therewith. 15. The workpiece processing system of claim 1, wherein the heater apparatus comprises one or more of a heat lamp, an infrared heater, and a resistive heater. 16. The workpiece processing system of claim 1, wherein the vacuum port and purge gas port are generally positioned opposite one another. 17. A loadlock apparatus, comprising:
a chamber having one or more chamber surfaces generally defining a chamber volume; a heated platen disposed within the chamber volume and configured to selectively support and heat a workpiece, wherein heating the workpiece generates an outgassed material; a vacuum valve; a vacuum source in selective fluid communication with the chamber volume via the vacuum valve; a purge gas valve; a purge gas source for providing a purge gas, wherein the purge gas source is in selective fluid communication with the chamber volume via the purge gas valve; a first loadlock valve operably coupled to the chamber and configured to provide selective fluid communication between the chamber volume and a first environment, and wherein the first loadlock valve is further configured to selectively pass the workpiece between the chamber volume and the first environment; and a second loadlock valve operably coupled to the chamber and configured to provide selective fluid communication between the chamber volume and a second environment associated with a process chamber, and wherein the second loadlock valve is further configured to selectively pass the workpiece between the chamber volume and second environment; and a controller configured to control the vacuum valve and purge gas valve to selectively flow the purge gas within the chamber volume at a predetermined pressure from the purge gas source to the vacuum source concurrent with the heating of the workpiece, thereby generally evacuating the outgassed material from the chamber volume and preventing a condensation of the outgassed material on the one or more chamber surfaces. 18. The loadlock apparatus of claim 17, wherein the chamber comprises a vacuum port and a purge gas port, wherein the vacuum port is in fluid communication with the chamber volume and the vacuum valve, and wherein the purge gas port is in fluid communication with chamber volume and the purge gas valve, wherein the vacuum port and purge gas port generally oppose one another, and wherein the heated platen is positioned between the vacuum port and purge gas port, wherein the selective flow of the purge gas passed across the heated platen. 19. The loadlock apparatus of claim 17, wherein the predetermined pressure is approximately atmospheric pressure. 20. A method for mitigating condensation of outgassing of a workpiece; the method comprising:
heating the workpiece in a chamber having one or more chamber surfaces generally defining a chamber volume, thereby generating an outgassed material; flowing a purge gas within the chamber volume at a predetermined pressure concurrent with the heating of the workpiece; and evacuating the purge gas from the chamber volume concurrent with the flowing of the purge gas, wherein the predetermined pressure is maintained, and wherein the outgassed material is generally evacuated from the chamber volume. | A system, method, and apparatus for heating a workpiece in chamber provides one or more surfaces generally enclosing a chamber volume. Vacuum and purge gas ports are in in fluid communication with the chamber volume. A heater apparatus selectively heats the workpiece on a workpiece support to a predetermined temperature and generates an outgassed material within the chamber volume. A vacuum valve provides selective fluid communication between a vacuum source and the vacuum port. A purge gas valve provides selective fluid communication between a purge gas source for a purge gas and the purge gas port. A controller controls the vacuum and purge gas valves to selectively flow the purge gas from the purge gas port to the vacuum port at a predetermined pressure while the workpiece is heated, thus removing and preventing condensation of the outgassed material on the chamber surfaces.1. A workpiece processing system, comprising:
a process chamber; a chamber having one or more surfaces generally enclosing a chamber volume, and wherein the chamber comprises a vacuum port and a purge gas port in fluid communication with the chamber volume, wherein the chamber generally defines a load lock chamber operably coupled to the process chamber; a workpiece support positioned within the chamber and configured to selectively support a workpiece; a heater apparatus configured to selectively heat the workpiece to a predetermined temperature, whereby heating the workpiece generates an outgassed material within the chamber volume; a vacuum source; a vacuum valve configured to provide selective fluid communication between the vacuum source and the vacuum port; a purge gas source having a purge gas associated therewith; a purge gas valve configured to provide selective fluid communication between the purge gas source and the purge gas port; and a controller configured to control the vacuum valve and purge gas valve to selectively flow the purge gas from the purge gas port to the vacuum port at a predetermined pressure concurrent with heating of the workpiece, thereby generally evacuating the outgassed material from the chamber volume and preventing a condensation of the outgassed material on the one or more surfaces. 2. The workpiece processing system of claim 1, further comprising:
a first loadlock valve operably coupled to the chamber and configured to provide selective fluid communication between the chamber volume and a first environment, and wherein the first loadlock valve is further configured to selectively pass the workpiece between the chamber volume and the first environment; and a second loadlock valve operably coupled to the chamber and configured to provide selective fluid communication between the chamber volume and a second environment associated with the process chamber, and wherein the second loadlock valve is further configured to selectively pass the workpiece between the chamber volume and second environment. 3. The workpiece processing system of claim 2, wherein the controller is further configured to selectively open and close the first loadlock valve, thereby selectively isolating the chamber volume from the first environment, and wherein the controller is further configured to selectively open and close the second loadlock valve, thereby selectively isolating the chamber volume from the second environment. 4. The workpiece processing system of claim 3, wherein the first environment comprises an atmospheric environment at atmospheric pressure, and wherein the second environment comprises a vacuum environment at a vacuum pressure, and wherein the controller is configured to flow the purge gas from the purge gas port to the vacuum port concurrent with the second loadlock valve isolating the chamber volume from the second environment. 5. The workpiece processing system of claim 4, wherein the controller is configured to flow the purge gas from the purge gas port to the vacuum port concurrent with the second loadlock valve isolating the chamber volume from the second environment and the first loadlock valve isolating the chamber volume from the first environment. 6. The workpiece processing system of claim 1, wherein the controller is configured open the purge gas valve and vacuum valve concurrent with the heating of the workpiece, thereby further concurrently flowing the purge gas from the purge gas port to the vacuum port at the predetermined pressure. 7. The workpiece processing system of claim 6, wherein the purge gas valve comprises a purge gas regulator, and wherein the vacuum valve comprises a vacuum regulator, wherein the purge gas regulator and vacuum regulator are configured to provide the predetermined pressure when the purge gas is flowed from the purge gas port to the vacuum port. 8. The workpiece processing system of claim 7, wherein the controller is further configured to control one or more of the purge gas regulator and vacuum regulator, thereby controlling the predetermined pressure. 9. The workpiece processing system of claim 7, wherein one or more of the purge gas regulator and vacuum regulator comprise manual regulators. 10. The workpiece processing system of claim 1, wherein the predetermined pressure is approximately atmospheric pressure. 11. The workpiece processing system of claim 1, further comprising a temperature measurement apparatus configured to determine a measured temperature of the workpiece, wherein the controller is further configured to control the vacuum valve and purge gas valve based, at least in part, on the measured temperature of the workpiece. 12. The workpiece processing system of claim 1, wherein the controller is further configured to control the vacuum valve and purge gas valve based, at least in part, on a predetermined time. 13. The workpiece processing system of claim 1, wherein the workpiece support comprises a heated platen having a support surface configured to contact a backside of the workpiece, wherein the heated platen generally defines the heater apparatus. 14. The workpiece processing system of claim 13, wherein the workpiece support comprise one or more pins configured to selectively raise and lower the workpiece onto a support surface associated therewith. 15. The workpiece processing system of claim 1, wherein the heater apparatus comprises one or more of a heat lamp, an infrared heater, and a resistive heater. 16. The workpiece processing system of claim 1, wherein the vacuum port and purge gas port are generally positioned opposite one another. 17. A loadlock apparatus, comprising:
a chamber having one or more chamber surfaces generally defining a chamber volume; a heated platen disposed within the chamber volume and configured to selectively support and heat a workpiece, wherein heating the workpiece generates an outgassed material; a vacuum valve; a vacuum source in selective fluid communication with the chamber volume via the vacuum valve; a purge gas valve; a purge gas source for providing a purge gas, wherein the purge gas source is in selective fluid communication with the chamber volume via the purge gas valve; a first loadlock valve operably coupled to the chamber and configured to provide selective fluid communication between the chamber volume and a first environment, and wherein the first loadlock valve is further configured to selectively pass the workpiece between the chamber volume and the first environment; and a second loadlock valve operably coupled to the chamber and configured to provide selective fluid communication between the chamber volume and a second environment associated with a process chamber, and wherein the second loadlock valve is further configured to selectively pass the workpiece between the chamber volume and second environment; and a controller configured to control the vacuum valve and purge gas valve to selectively flow the purge gas within the chamber volume at a predetermined pressure from the purge gas source to the vacuum source concurrent with the heating of the workpiece, thereby generally evacuating the outgassed material from the chamber volume and preventing a condensation of the outgassed material on the one or more chamber surfaces. 18. The loadlock apparatus of claim 17, wherein the chamber comprises a vacuum port and a purge gas port, wherein the vacuum port is in fluid communication with the chamber volume and the vacuum valve, and wherein the purge gas port is in fluid communication with chamber volume and the purge gas valve, wherein the vacuum port and purge gas port generally oppose one another, and wherein the heated platen is positioned between the vacuum port and purge gas port, wherein the selective flow of the purge gas passed across the heated platen. 19. The loadlock apparatus of claim 17, wherein the predetermined pressure is approximately atmospheric pressure. 20. A method for mitigating condensation of outgassing of a workpiece; the method comprising:
heating the workpiece in a chamber having one or more chamber surfaces generally defining a chamber volume, thereby generating an outgassed material; flowing a purge gas within the chamber volume at a predetermined pressure concurrent with the heating of the workpiece; and evacuating the purge gas from the chamber volume concurrent with the flowing of the purge gas, wherein the predetermined pressure is maintained, and wherein the outgassed material is generally evacuated from the chamber volume. | 2,800 |
12,188 | 12,188 | 15,259,241 | 2,864 | The invention relates to a method of setting a plurality of part regions of a desired protected zone, in which
a) the positions of a plurality of monitoring units are detected, with each monitoring unit detecting a detection zone;
b) a maximum size of each detection zone is determined;
c) the desired protected zone is fixed in a graphical user interface;
d) the part regions to be monitored by the respective monitoring units are fixed with reference to the positions of the monitoring units, to the maximum size of the detection zones and of the desired protected zone; and
e) the part regions are assigned to the respective monitoring units. | 1. A method of setting a plurality of part regions of a desired protected zone, in which
a) positions of a plurality of monitoring units are detected, wherein each of the plurality of monitoring units detects a detection zone; b) a maximum size of each detection zone is determined; c) the desired protected zone is fixed in a graphical user interface; d) the part regions to be monitored by the respective plurality of monitoring units are fixed with reference to the positions of the plurality of monitoring units, to the maximum size of the detection zones and to the desired protected zone; and e) the part regions are assigned to a respective one of the plurality of monitoring units. 2. The method in accordance with claim 1,
wherein, in step a), the positions of the plurality of monitoring units are detected by laser scanners. 3. The method in accordance with claim 1,
wherein an alignment of the plurality of monitoring units is also detected. 4. The method in accordance with claim 1,
wherein the part regions are at least partly fixed for overlap regions of the protected zone which can be monitored by a plurality of monitoring units such that only exactly one respective monitoring unit monitors the respective overlap region. 5. The method in accordance with claim 1,
wherein boundary regions having a predefined width are fixed for boundaries between two part regions and are each associated with the two part regions. 6. The method in accordance with claim 1,
wherein the part regions are fixed at least in part for overlap regions of the protected zone which are monitorable by a plurality of monitoring units such that only exactly that respective monitoring unit monitors the overlap region which is closest to the respective overlap region. 7. The method in accordance with claim 1,
wherein the part regions are fixed at least in part for overlap regions of the protected zone which are monitorable by a plurality of monitoring units such that only exactly that respective monitoring unit monitors the overlap region which is closest to the respective overlap region, with respect to the size of its detection zone. 8. The method in accordance with claim 1, in which
f) the plurality of monitoring units are each set only to monitor the respective associated part region. 9. The method in accordance with claim 1,
wherein the desired protected zone comprises a plurality of mutually separate protected zone sections. 10. The method in accordance with claim 1,
wherein the desired protected zone has regions not to be monitored within the protected zone. 11. The method in accordance with claim 1,
wherein an output of non-monitorable regions of the desired protected zone takes place. 12. The method in accordance with claim 1,
wherein contour regions within the desired protected zone are also determined and are taken into account in the fixing of the part regions. 13. The method in accordance with claim 1,
wherein the positions of the plurality of monitoring units are determined by means of a reference object. 14. The method in accordance with claim 1,
wherein the fixed part regions and/or the desired protected zone can be set and/or changed by means of a piece of software. 15. The method in accordance with claim 14,
wherein the software places a site plan behind the displayed part regions and/or the desired protected zone. 16. A system having a processing unit and at least two monitoring units, wherein the processing unit and the monitoring units are coupled by means of a data connection and the system is configured to carry out a method in accordance with claim 1. 17. A computer program having program code means which are adapted such that a method in accordance with claim 1 is carried out when the program is executed on a computer. | The invention relates to a method of setting a plurality of part regions of a desired protected zone, in which
a) the positions of a plurality of monitoring units are detected, with each monitoring unit detecting a detection zone;
b) a maximum size of each detection zone is determined;
c) the desired protected zone is fixed in a graphical user interface;
d) the part regions to be monitored by the respective monitoring units are fixed with reference to the positions of the monitoring units, to the maximum size of the detection zones and of the desired protected zone; and
e) the part regions are assigned to the respective monitoring units.1. A method of setting a plurality of part regions of a desired protected zone, in which
a) positions of a plurality of monitoring units are detected, wherein each of the plurality of monitoring units detects a detection zone; b) a maximum size of each detection zone is determined; c) the desired protected zone is fixed in a graphical user interface; d) the part regions to be monitored by the respective plurality of monitoring units are fixed with reference to the positions of the plurality of monitoring units, to the maximum size of the detection zones and to the desired protected zone; and e) the part regions are assigned to a respective one of the plurality of monitoring units. 2. The method in accordance with claim 1,
wherein, in step a), the positions of the plurality of monitoring units are detected by laser scanners. 3. The method in accordance with claim 1,
wherein an alignment of the plurality of monitoring units is also detected. 4. The method in accordance with claim 1,
wherein the part regions are at least partly fixed for overlap regions of the protected zone which can be monitored by a plurality of monitoring units such that only exactly one respective monitoring unit monitors the respective overlap region. 5. The method in accordance with claim 1,
wherein boundary regions having a predefined width are fixed for boundaries between two part regions and are each associated with the two part regions. 6. The method in accordance with claim 1,
wherein the part regions are fixed at least in part for overlap regions of the protected zone which are monitorable by a plurality of monitoring units such that only exactly that respective monitoring unit monitors the overlap region which is closest to the respective overlap region. 7. The method in accordance with claim 1,
wherein the part regions are fixed at least in part for overlap regions of the protected zone which are monitorable by a plurality of monitoring units such that only exactly that respective monitoring unit monitors the overlap region which is closest to the respective overlap region, with respect to the size of its detection zone. 8. The method in accordance with claim 1, in which
f) the plurality of monitoring units are each set only to monitor the respective associated part region. 9. The method in accordance with claim 1,
wherein the desired protected zone comprises a plurality of mutually separate protected zone sections. 10. The method in accordance with claim 1,
wherein the desired protected zone has regions not to be monitored within the protected zone. 11. The method in accordance with claim 1,
wherein an output of non-monitorable regions of the desired protected zone takes place. 12. The method in accordance with claim 1,
wherein contour regions within the desired protected zone are also determined and are taken into account in the fixing of the part regions. 13. The method in accordance with claim 1,
wherein the positions of the plurality of monitoring units are determined by means of a reference object. 14. The method in accordance with claim 1,
wherein the fixed part regions and/or the desired protected zone can be set and/or changed by means of a piece of software. 15. The method in accordance with claim 14,
wherein the software places a site plan behind the displayed part regions and/or the desired protected zone. 16. A system having a processing unit and at least two monitoring units, wherein the processing unit and the monitoring units are coupled by means of a data connection and the system is configured to carry out a method in accordance with claim 1. 17. A computer program having program code means which are adapted such that a method in accordance with claim 1 is carried out when the program is executed on a computer. | 2,800 |
12,189 | 12,189 | 15,909,679 | 2,814 | A method for fabricating a copper pillar. The method includes forming a layer of titanium tungsten (TiW) over a semiconductor wafer, forming a layer of zinc (Zn) over the layer of TiW, and forming a copper pillar over the via. In addition, the method includes performing an anneal to diffuse the layer of Zn into the copper pillar. A semiconductor device that includes a layer of TiW coupled to a via of a semiconductor wafer and a copper pillar coupled to the layer of TiW. The copper pillar has interdiffused Zn within its bottom portion. Another method for fabricating a copper pillar includes forming a layer of TiW over a semiconductor wafer, forming a first patterned photoresist, forming a layer of Zn, and then removing the first patterned photoresist. The method further includes forming a second patterned photoresist and forming a copper pillar. | 1. A method for fabricating a copper pillar over a semiconductor wafer, comprising:
providing said semiconductor wafer including a via; forming a layer of titanium tungsten (TiW) over said semiconductor wafer; forming a layer of zinc (Zn) over said layer of TiW; forming a patterned photoresist over said layer of Zn, said patterned photoresist being absent over said via; forming said copper pillar over said via, said copper pillar having a perimeter; removing said patterned photoresist; performing an anneal; removing said layer of Zn; and removing said layer of TiW that is located outside said perimeter of said copper pillar. 2. The method of claim 1 wherein said via includes copper. 3. The method of claim 1 wherein said anneal causes interdiffusion of said layer of Zn and said copper pillar. 4. A method for fabricating a packaged semiconductor device, comprising:
providing a semiconductor wafer including a via; forming a layer of titanium tungsten (TiW) over said semiconductor wafer; forming a layer of zinc (Zn) over said layer of TiW; forming a patterned photoresist over said layer of Zn, said patterned photoresist being absent over said via; forming a copper pillar over said via, said copper pillar having a perimeter; removing said patterned photoresist; performing an anneal; removing said layer of Zn; removing said layer of TiW that is located outside said perimeter of said copper pillar; singulating said semiconductor wafer to form a semiconductor die; attaching said copper pillar to a printed circuit board; and encapsulating said semiconductor die and portions of said printed circuit board with molding compound to form said packaged semiconductor die. 5. The method of claim 4 wherein said via includes copper. 6. The method of claim 4 wherein said anneal causes interdiffusion of said layer of Zn and said copper pillar. 7. A semiconductor device, comprising:
a semiconductor die including a via; a layer of titanium tungsten (TiW) coupled to said via; and a copper pillar coupled to said layer of Ti W, said copper pillar having a top portion and a bottom portion that is in contact with said layer of TiW, and said copper pillar having interdiffused zinc within said bottom portion. 8. The semiconductor device of claim 7 wherein said layer of TiW is also coupled to portions of said semiconductor die. 9. The semiconductor device of claim 7 wherein said via includes copper. 10. A packaged semiconductor device, comprising:
a semiconductor die including a via; a layer of titanium tungsten (TiW) coupled to said via; a copper pillar coupled to said layer of TiW, said copper pillar having a top portion and a bottom portion that is in contact with said layer of TiW, and said copper pillar having interdiffused zinc within said bottom portion; a printed circuit board coupled to the copper pillar; and molding compound encapsulating said semiconductor die and portions of said printed circuit board. 11. The packaged semiconductor device of claim 10 wherein said layer of TiW is also coupled to portions of said semiconductor die. 12. The packaged semiconductor device of claim 10 wherein said via includes copper. 13. A method for fabricating a copper pillar over a semiconductor wafer, comprising:
providing said semiconductor wafer including a via; forming a layer of titanium tungsten (TiW) over said semiconductor wafer; forming a first patterned photoresist over said via; forming a layer of zinc (Zn) over said layer of TiW and said first patterned photoresist; removing said first patterned photoresist; forming a second patterned photoresist over said layer of Zn; forming said copper pillar over said via, said copper pillar having a perimeter; removing said second patterned photoresist; removing said layer of Zn; and removing said layer of TiW that is located outside said perimeter of said copper pillar. 14. The method of claim 13 wherein said via includes copper. 15. The method of claim 13 wherein said first patterned photoresist is negative tone photoresist. 16. The method of claim 13 wherein said second patterned photoresist is positive tone photoresist. 17. A method for fabricating a packaged semiconductor device, comprising:
providing a semiconductor wafer including a via; forming a layer of titanium tungsten (TiW) over said semiconductor wafer; forming a first patterned photoresist over said via; forming a layer of zinc (Zn) over said layer of TiW and said first patterned photoresist; removing said first patterned photoresist; forming a second patterned photoresist over said layer of Zn; forming a copper pillar over said via, said copper pillar having a perimeter; removing said second patterned photoresist; removing said layer of Zn; removing said layer of TiW that is located outside said perimeter of said copper pillar; singulating said semiconductor wafer to form a semiconductor die; attaching said copper pillar to a printed circuit board; and encapsulating said semiconductor die and portions of said printed circuit board with molding compound to form said packaged semiconductor device. 18. The method of claim 17 wherein said via includes copper. 19. The method of claim 17 wherein said first patterned photoresist is negative tone photoresist. 20. The method of claim 17 wherein said second patterned photoresist is positive tone photoresist. | A method for fabricating a copper pillar. The method includes forming a layer of titanium tungsten (TiW) over a semiconductor wafer, forming a layer of zinc (Zn) over the layer of TiW, and forming a copper pillar over the via. In addition, the method includes performing an anneal to diffuse the layer of Zn into the copper pillar. A semiconductor device that includes a layer of TiW coupled to a via of a semiconductor wafer and a copper pillar coupled to the layer of TiW. The copper pillar has interdiffused Zn within its bottom portion. Another method for fabricating a copper pillar includes forming a layer of TiW over a semiconductor wafer, forming a first patterned photoresist, forming a layer of Zn, and then removing the first patterned photoresist. The method further includes forming a second patterned photoresist and forming a copper pillar.1. A method for fabricating a copper pillar over a semiconductor wafer, comprising:
providing said semiconductor wafer including a via; forming a layer of titanium tungsten (TiW) over said semiconductor wafer; forming a layer of zinc (Zn) over said layer of TiW; forming a patterned photoresist over said layer of Zn, said patterned photoresist being absent over said via; forming said copper pillar over said via, said copper pillar having a perimeter; removing said patterned photoresist; performing an anneal; removing said layer of Zn; and removing said layer of TiW that is located outside said perimeter of said copper pillar. 2. The method of claim 1 wherein said via includes copper. 3. The method of claim 1 wherein said anneal causes interdiffusion of said layer of Zn and said copper pillar. 4. A method for fabricating a packaged semiconductor device, comprising:
providing a semiconductor wafer including a via; forming a layer of titanium tungsten (TiW) over said semiconductor wafer; forming a layer of zinc (Zn) over said layer of TiW; forming a patterned photoresist over said layer of Zn, said patterned photoresist being absent over said via; forming a copper pillar over said via, said copper pillar having a perimeter; removing said patterned photoresist; performing an anneal; removing said layer of Zn; removing said layer of TiW that is located outside said perimeter of said copper pillar; singulating said semiconductor wafer to form a semiconductor die; attaching said copper pillar to a printed circuit board; and encapsulating said semiconductor die and portions of said printed circuit board with molding compound to form said packaged semiconductor die. 5. The method of claim 4 wherein said via includes copper. 6. The method of claim 4 wherein said anneal causes interdiffusion of said layer of Zn and said copper pillar. 7. A semiconductor device, comprising:
a semiconductor die including a via; a layer of titanium tungsten (TiW) coupled to said via; and a copper pillar coupled to said layer of Ti W, said copper pillar having a top portion and a bottom portion that is in contact with said layer of TiW, and said copper pillar having interdiffused zinc within said bottom portion. 8. The semiconductor device of claim 7 wherein said layer of TiW is also coupled to portions of said semiconductor die. 9. The semiconductor device of claim 7 wherein said via includes copper. 10. A packaged semiconductor device, comprising:
a semiconductor die including a via; a layer of titanium tungsten (TiW) coupled to said via; a copper pillar coupled to said layer of TiW, said copper pillar having a top portion and a bottom portion that is in contact with said layer of TiW, and said copper pillar having interdiffused zinc within said bottom portion; a printed circuit board coupled to the copper pillar; and molding compound encapsulating said semiconductor die and portions of said printed circuit board. 11. The packaged semiconductor device of claim 10 wherein said layer of TiW is also coupled to portions of said semiconductor die. 12. The packaged semiconductor device of claim 10 wherein said via includes copper. 13. A method for fabricating a copper pillar over a semiconductor wafer, comprising:
providing said semiconductor wafer including a via; forming a layer of titanium tungsten (TiW) over said semiconductor wafer; forming a first patterned photoresist over said via; forming a layer of zinc (Zn) over said layer of TiW and said first patterned photoresist; removing said first patterned photoresist; forming a second patterned photoresist over said layer of Zn; forming said copper pillar over said via, said copper pillar having a perimeter; removing said second patterned photoresist; removing said layer of Zn; and removing said layer of TiW that is located outside said perimeter of said copper pillar. 14. The method of claim 13 wherein said via includes copper. 15. The method of claim 13 wherein said first patterned photoresist is negative tone photoresist. 16. The method of claim 13 wherein said second patterned photoresist is positive tone photoresist. 17. A method for fabricating a packaged semiconductor device, comprising:
providing a semiconductor wafer including a via; forming a layer of titanium tungsten (TiW) over said semiconductor wafer; forming a first patterned photoresist over said via; forming a layer of zinc (Zn) over said layer of TiW and said first patterned photoresist; removing said first patterned photoresist; forming a second patterned photoresist over said layer of Zn; forming a copper pillar over said via, said copper pillar having a perimeter; removing said second patterned photoresist; removing said layer of Zn; removing said layer of TiW that is located outside said perimeter of said copper pillar; singulating said semiconductor wafer to form a semiconductor die; attaching said copper pillar to a printed circuit board; and encapsulating said semiconductor die and portions of said printed circuit board with molding compound to form said packaged semiconductor device. 18. The method of claim 17 wherein said via includes copper. 19. The method of claim 17 wherein said first patterned photoresist is negative tone photoresist. 20. The method of claim 17 wherein said second patterned photoresist is positive tone photoresist. | 2,800 |
12,190 | 12,190 | 16,604,476 | 2,835 | A heat exchanging arrangement for a subsea electronic system, the heat exchanging arrangement including: at least one pipe having an external surface; and at least one heat exchanging element arranged inside the at least one pipe and defining at least one internal passage for conducting a dielectric fluid through the at least one pipe; wherein the at least one heat exchanging element is arranged to press laterally outwards against an internal surface of the at least one pipe to establish a heat transfer bond between the at least one heat exchanging element and the at least one pipe. A subsea electronic system including the heat exchanging arrangement is also provided. | 1. A exchanging arrangement for a subsea electronic system, the heat exchanging arrangement comprising:
at least one pipe having an external surface; and at least one heat exchanging element, arranged inside the at least one pipe and defining at least one internal passage for conducting a dielectric fluid through the at least one pipe; wherein the at least one heat exchanging element is arranged to press laterally outwards against an internal surface of the at least one pipe to establish a heat transfer bond between the at least one heat exchanging element and the at least one pipe. 2. The heat exchanging arrangement according to claim 1, wherein the at least one heat exchanging element and the at least one pipe are shrink fitted. 3. The heat exchanging arrangements according to claim 1, further comprising at least one expansion tool substantially concentrically arranged inside the at least one pipe for pressing the at least one heat exchanging element laterally outwards against the internal surface of the at least one pipe. 4. The heat exchanging arrangement according to claim 1, wherein the at least one heat exchanging element includes at least two heat exchanging elements arranged inside the at least one pipe at substantially the same position along a longitudinal axis of the at least one pipe. 5. The heat exchanging arrangement according to claim 1, wherein the at least one heat exchanging elements is extruded. 6. The heat exchanging arrangement f according to claim 1, wherein the at least one heat exchanging element is made of a material with high thermal conductivity, such as aluminum. 7. The heat exchanging arrangement according to claim 1, wherein the at least one pipe is made of a material resistant to seawater corrosion, such as stainless steel. 8. The heat exchanging arrangement according claim 1, wherein the at least one heat exchanging element includes at least two heat exchanging elements having longitudinal recesses such that a longitudinal recess of one heat exchanging element and a longitudinal recess of another heat exchanging element together define one of the at least one internal passage when the heat exchanging elements are mated. 9. The heat exchanging arrangements according to claim 1, further comprising a thermally insulated tube arranged laterally inside the at least one heat exchanging element pipe includes a closed end; wherein the thermally insulated tube is arranged to conduct the dielectric fluid towards the closed end of the at least one pipe and wherein the at least one internal passage is arranged to conduct the dielectric fluid away from the closed endue of the at least one pipe. 10. A subsea electronic system comprising:
a watertight enclosure having at least one wall section; at least one electronic component arranged inside the enclosure; and a heat exchanging arrangement according to claim 1; wherein the at least one pipe of the heat exchanging arrangement forms a part of a cooling circuit passing by the at least one electronic component. 11. The subsea electronic system according to claim 10, wherein the at least one wall section has a wave formed profile including peaks and valleys and wherein the at least one pipe is at least partly accommodated within a valley. 12. The subsea electronic system according to claim 10, wherein one of the at least one wall section is a substantially vertically oriented wall section and wherein the heat exchanging arrangement is connected to the wall section. 13. The subsea electronic system according to claim 10, wherein one of the at least one electronic component is constituted by a power converter. 14. The subsea electronic system according to claim 10, wherein the enclosure includes an upper enclosure part and a lower enclosure part jointly defining a continuous enclosure volume for a dielectric fluid; wherein the enclosure volume includes an upper cooling circuit and a lower cooling circuit, vertically below the upper cooling circuit; and wherein the at least one pipe of the heat exchanging arrangement forms a part of the upper cooling circuit passing by the at least one electronic component. 15. The subsea electronic systems according to claim 10, wherein, when the at least one electronic component is in use, the dielectric fluid-s circulates by natural convection. | A heat exchanging arrangement for a subsea electronic system, the heat exchanging arrangement including: at least one pipe having an external surface; and at least one heat exchanging element arranged inside the at least one pipe and defining at least one internal passage for conducting a dielectric fluid through the at least one pipe; wherein the at least one heat exchanging element is arranged to press laterally outwards against an internal surface of the at least one pipe to establish a heat transfer bond between the at least one heat exchanging element and the at least one pipe. A subsea electronic system including the heat exchanging arrangement is also provided.1. A exchanging arrangement for a subsea electronic system, the heat exchanging arrangement comprising:
at least one pipe having an external surface; and at least one heat exchanging element, arranged inside the at least one pipe and defining at least one internal passage for conducting a dielectric fluid through the at least one pipe; wherein the at least one heat exchanging element is arranged to press laterally outwards against an internal surface of the at least one pipe to establish a heat transfer bond between the at least one heat exchanging element and the at least one pipe. 2. The heat exchanging arrangement according to claim 1, wherein the at least one heat exchanging element and the at least one pipe are shrink fitted. 3. The heat exchanging arrangements according to claim 1, further comprising at least one expansion tool substantially concentrically arranged inside the at least one pipe for pressing the at least one heat exchanging element laterally outwards against the internal surface of the at least one pipe. 4. The heat exchanging arrangement according to claim 1, wherein the at least one heat exchanging element includes at least two heat exchanging elements arranged inside the at least one pipe at substantially the same position along a longitudinal axis of the at least one pipe. 5. The heat exchanging arrangement according to claim 1, wherein the at least one heat exchanging elements is extruded. 6. The heat exchanging arrangement f according to claim 1, wherein the at least one heat exchanging element is made of a material with high thermal conductivity, such as aluminum. 7. The heat exchanging arrangement according to claim 1, wherein the at least one pipe is made of a material resistant to seawater corrosion, such as stainless steel. 8. The heat exchanging arrangement according claim 1, wherein the at least one heat exchanging element includes at least two heat exchanging elements having longitudinal recesses such that a longitudinal recess of one heat exchanging element and a longitudinal recess of another heat exchanging element together define one of the at least one internal passage when the heat exchanging elements are mated. 9. The heat exchanging arrangements according to claim 1, further comprising a thermally insulated tube arranged laterally inside the at least one heat exchanging element pipe includes a closed end; wherein the thermally insulated tube is arranged to conduct the dielectric fluid towards the closed end of the at least one pipe and wherein the at least one internal passage is arranged to conduct the dielectric fluid away from the closed endue of the at least one pipe. 10. A subsea electronic system comprising:
a watertight enclosure having at least one wall section; at least one electronic component arranged inside the enclosure; and a heat exchanging arrangement according to claim 1; wherein the at least one pipe of the heat exchanging arrangement forms a part of a cooling circuit passing by the at least one electronic component. 11. The subsea electronic system according to claim 10, wherein the at least one wall section has a wave formed profile including peaks and valleys and wherein the at least one pipe is at least partly accommodated within a valley. 12. The subsea electronic system according to claim 10, wherein one of the at least one wall section is a substantially vertically oriented wall section and wherein the heat exchanging arrangement is connected to the wall section. 13. The subsea electronic system according to claim 10, wherein one of the at least one electronic component is constituted by a power converter. 14. The subsea electronic system according to claim 10, wherein the enclosure includes an upper enclosure part and a lower enclosure part jointly defining a continuous enclosure volume for a dielectric fluid; wherein the enclosure volume includes an upper cooling circuit and a lower cooling circuit, vertically below the upper cooling circuit; and wherein the at least one pipe of the heat exchanging arrangement forms a part of the upper cooling circuit passing by the at least one electronic component. 15. The subsea electronic systems according to claim 10, wherein, when the at least one electronic component is in use, the dielectric fluid-s circulates by natural convection. | 2,800 |
12,191 | 12,191 | 15,223,099 | 2,829 | Provided are a composite substrate suitable for low-cost manufacture of light emitting devices having a three-dimensional shape such as a curved shape or a concave-convex shape, and a light emitting device having a three-dimensional shape manufactured with such a substrate. The composite substrate of the present invention comprises a substrate having a surface with a three-dimensional shape and a group 13 element nitride crystal layer provided on the substrate. The substrate is a substrate in which the surface with a three-dimensional shape comprises a layer composed of oriented polycrystalline alumina, or a substrate an entirety of which is composed of oriented polycrystalline alumina. The group 13 element nitride crystal layer 14 is formed on the oriented polycrystalline alumina of the substrate. Optionally, a light emitting functional layer is provided on the group 13 element nitride crystal layer. | 1. A composite substrate comprising:
a substrate having a surface with a three-dimensional shape, wherein the surface with a three-dimensional shape comprises a layer composed of oriented polycrystalline alumina, or wherein an entirety of the substrate is composed of oriented polycrystalline alumina; and a group 13 element nitride crystal layer formed on the oriented polycrystalline alumina of the substrate. 2. The composite substrate according to claim 1, wherein the three-dimensional shape includes a curved shape and/or a concave-convex shape. 3. The composite substrate according to claim 1, wherein the three-dimensional shape is a macroscopic shape having a visible, three-dimensional profile. 4. The composite substrate according to claim 1, further comprising a seed crystal layer between the group 13 element nitride crystal layer and the substrate. 5. The composite substrate according to claim 1, wherein the group 13 element nitride crystal layer has a structure in which grains are grown mostly in conformity with crystal orientation of the oriented polycrystalline alumina. 6. The composite substrate according to claim 1, wherein the substrate is a composite comprising a base substrate and a layer composed of oriented polycrystalline alumina on the base substrate, and the layer composed of oriented polycrystalline alumina is formed by laser CVD and/or lamp-heating CVD. 7. The composite substrate according to claim 1, wherein the substrate is composed of an oriented polycrystalline alumina sintered body. 8. The composite substrate according to claim 1, further comprising a light emitting functional layer on the group 13 element nitride crystal layer. 9. A method for manufacturing a light emitting device, comprising the steps of:
forming a translucent electrode layer on the light emitting functional layer of the composite substrate according to claim 8; locally removing part of the light emitting functional layer before or after forming the translucent electrode layer to locally expose a lowermost layer of the light emitting functional layer; and forming an electrode layer on the exposed lowermost layer to obtain the light emitting device. 10. A method for manufacturing a light emitting device, comprising the steps of:
forming a reflective electrode layer or a translucent electrode layer on the light emitting functional layer of the composite substrate according to claim 8; removing at least the substrate from the composite substrate before or after forming the reflective electrode layer or the translucent electrode layer to expose the light emitting functional layer, the group 13 element nitride crystal layer, or the seed crystal layer; and forming a translucent electrode layer or a reflective electrode layer on the exposed light emitting functional layer, group 13 element nitride crystal layer, or seed crystal layer to obtain the light emitting device. 11. A method for manufacturing a light emitting device, comprising the steps of:
forming a support layer that also functions as a reflective electrode on the light emitting functional layer of the composite substrate according to claim 8 to obtain a reinforced composite substrate; removing at least the substrate from the reinforced composite substrate to expose the light emitting functional layer, the group 13 element nitride crystal layer, or the seed crystal layer; and forming a translucent electrode layer on the exposed light emitting functional layer, group 13 element nitride crystal layer, or seed crystal layer to obtain the light emitting device. 12. The method according to claim 11, wherein the composite substrate has a curved shape such that the light emitting functional layer is an outer circumferential surface so that the light emitting device is configured as a curved light emitting device that emits light from an inner circumferential surface side. 13. A method for manufacturing a light emitting device, comprising the steps of:
forming a temporary support layer on the light emitting functional layer of the composite substrate according to claim 8 to obtain a reinforced composite substrate; removing at least the substrate from the reinforced composite substrate to expose the light emitting functional layer, the group 13 element nitride crystal layer, or the seed crystal layer; forming a support layer that also functions as a reflective electrode on the exposed light emitting functional layer, group 13 element nitride crystal layer, or seed crystal layer to obtain a further reinforced composite substrate; removing the temporary support layer from the further reinforced composite substrate to expose the light emitting functional layer; and forming a translucent electrode layer on the exposed light emitting functional layer to obtain the light emitting device. 14. The method according to claim 13, wherein the composite substrate has a curved shape such that the light emitting functional layer is an outer circumferential surface, so that the light emitting device is configured as a curved light emitting device that emits light from an outer circumferential surface side. 15. A light emitting device, comprising:
a support layer having a surface with a three-dimensional shape, wherein the support layer also functions as a reflective electrode; a light emitting functional layer formed on the surface with a three-dimensional shape of the support layer, wherein the light emitting functional layer comprises two or more layers composed of semiconductor single crystal grains, wherein each of the two or more layers has a single crystal structure in a direction approximately normal to the surface with a three-dimensional shape; and a translucent electrode layer provided on a side of the light emitting functional layer opposite to the support layer. 16. The light emitting device according to claim 15, wherein the three-dimensional shape is a curved shape, the light emitting functional layer is formed on an inner circumferential surface of the support layer so that the light emitting device is formed as a curved light emitting device that emits light from an inner circumferential surface side. 17. The light emitting device according to claim 15, wherein the three-dimensional shape is a curved shape, the light emitting functional layer is formed on an outer circumferential surface of the support layer so that the light emitting device is formed as a curved light emitting device that emits light from an outer circumferential surface side. | Provided are a composite substrate suitable for low-cost manufacture of light emitting devices having a three-dimensional shape such as a curved shape or a concave-convex shape, and a light emitting device having a three-dimensional shape manufactured with such a substrate. The composite substrate of the present invention comprises a substrate having a surface with a three-dimensional shape and a group 13 element nitride crystal layer provided on the substrate. The substrate is a substrate in which the surface with a three-dimensional shape comprises a layer composed of oriented polycrystalline alumina, or a substrate an entirety of which is composed of oriented polycrystalline alumina. The group 13 element nitride crystal layer 14 is formed on the oriented polycrystalline alumina of the substrate. Optionally, a light emitting functional layer is provided on the group 13 element nitride crystal layer.1. A composite substrate comprising:
a substrate having a surface with a three-dimensional shape, wherein the surface with a three-dimensional shape comprises a layer composed of oriented polycrystalline alumina, or wherein an entirety of the substrate is composed of oriented polycrystalline alumina; and a group 13 element nitride crystal layer formed on the oriented polycrystalline alumina of the substrate. 2. The composite substrate according to claim 1, wherein the three-dimensional shape includes a curved shape and/or a concave-convex shape. 3. The composite substrate according to claim 1, wherein the three-dimensional shape is a macroscopic shape having a visible, three-dimensional profile. 4. The composite substrate according to claim 1, further comprising a seed crystal layer between the group 13 element nitride crystal layer and the substrate. 5. The composite substrate according to claim 1, wherein the group 13 element nitride crystal layer has a structure in which grains are grown mostly in conformity with crystal orientation of the oriented polycrystalline alumina. 6. The composite substrate according to claim 1, wherein the substrate is a composite comprising a base substrate and a layer composed of oriented polycrystalline alumina on the base substrate, and the layer composed of oriented polycrystalline alumina is formed by laser CVD and/or lamp-heating CVD. 7. The composite substrate according to claim 1, wherein the substrate is composed of an oriented polycrystalline alumina sintered body. 8. The composite substrate according to claim 1, further comprising a light emitting functional layer on the group 13 element nitride crystal layer. 9. A method for manufacturing a light emitting device, comprising the steps of:
forming a translucent electrode layer on the light emitting functional layer of the composite substrate according to claim 8; locally removing part of the light emitting functional layer before or after forming the translucent electrode layer to locally expose a lowermost layer of the light emitting functional layer; and forming an electrode layer on the exposed lowermost layer to obtain the light emitting device. 10. A method for manufacturing a light emitting device, comprising the steps of:
forming a reflective electrode layer or a translucent electrode layer on the light emitting functional layer of the composite substrate according to claim 8; removing at least the substrate from the composite substrate before or after forming the reflective electrode layer or the translucent electrode layer to expose the light emitting functional layer, the group 13 element nitride crystal layer, or the seed crystal layer; and forming a translucent electrode layer or a reflective electrode layer on the exposed light emitting functional layer, group 13 element nitride crystal layer, or seed crystal layer to obtain the light emitting device. 11. A method for manufacturing a light emitting device, comprising the steps of:
forming a support layer that also functions as a reflective electrode on the light emitting functional layer of the composite substrate according to claim 8 to obtain a reinforced composite substrate; removing at least the substrate from the reinforced composite substrate to expose the light emitting functional layer, the group 13 element nitride crystal layer, or the seed crystal layer; and forming a translucent electrode layer on the exposed light emitting functional layer, group 13 element nitride crystal layer, or seed crystal layer to obtain the light emitting device. 12. The method according to claim 11, wherein the composite substrate has a curved shape such that the light emitting functional layer is an outer circumferential surface so that the light emitting device is configured as a curved light emitting device that emits light from an inner circumferential surface side. 13. A method for manufacturing a light emitting device, comprising the steps of:
forming a temporary support layer on the light emitting functional layer of the composite substrate according to claim 8 to obtain a reinforced composite substrate; removing at least the substrate from the reinforced composite substrate to expose the light emitting functional layer, the group 13 element nitride crystal layer, or the seed crystal layer; forming a support layer that also functions as a reflective electrode on the exposed light emitting functional layer, group 13 element nitride crystal layer, or seed crystal layer to obtain a further reinforced composite substrate; removing the temporary support layer from the further reinforced composite substrate to expose the light emitting functional layer; and forming a translucent electrode layer on the exposed light emitting functional layer to obtain the light emitting device. 14. The method according to claim 13, wherein the composite substrate has a curved shape such that the light emitting functional layer is an outer circumferential surface, so that the light emitting device is configured as a curved light emitting device that emits light from an outer circumferential surface side. 15. A light emitting device, comprising:
a support layer having a surface with a three-dimensional shape, wherein the support layer also functions as a reflective electrode; a light emitting functional layer formed on the surface with a three-dimensional shape of the support layer, wherein the light emitting functional layer comprises two or more layers composed of semiconductor single crystal grains, wherein each of the two or more layers has a single crystal structure in a direction approximately normal to the surface with a three-dimensional shape; and a translucent electrode layer provided on a side of the light emitting functional layer opposite to the support layer. 16. The light emitting device according to claim 15, wherein the three-dimensional shape is a curved shape, the light emitting functional layer is formed on an inner circumferential surface of the support layer so that the light emitting device is formed as a curved light emitting device that emits light from an inner circumferential surface side. 17. The light emitting device according to claim 15, wherein the three-dimensional shape is a curved shape, the light emitting functional layer is formed on an outer circumferential surface of the support layer so that the light emitting device is formed as a curved light emitting device that emits light from an outer circumferential surface side. | 2,800 |
12,192 | 12,192 | 14,745,825 | 2,829 | An ungrounded power line sensor system includes a housing configured for coupling about a power line, at least a first voltage sensing plate supported by the housing and exposed to rain and snow, and at least a second voltage sensing plate supported by the housing and shielded from rain and snow. Voltages sensed by the first and second voltage sensing plate are separately measured in order to mitigate variations in the two measurements due to a weather event, for example by applying a weighted average calculation to the measurements to cancel out the effects of rain on the first voltage sensing plate. | 1. An ungrounded power line sensor system comprising:
a housing configured for coupling about a power line; at least a first voltage sensing plate supported by the housing and exposed to rain and snow; at least a second voltage sensing plate supported by the housing and shielded from rain and snow; and a processing subsystem configured to:
measure a voltage sensed by the first voltage sensing plate,
separately measure a voltage sensed by the second voltage sensing plate, and
mitigate variations in said measurements due to a weather event. 2. The system of claim 1 in which the processing subsystem is configured to mitigate variations in said measurements by applying a weighted average calculation to said measurements to cancel out the effects of rain on the first voltage sensing plate. 3. The system of claim 2 in which the measured voltage sensed by the first voltage sensing plate is Vtop, the measured voltage sensed by the second voltage sensing plate is Vbottom, and the weighted average calculation is Vavg=(1−c)Vtop+c Vbot where c is a constant weighting factor. 4. The system of claim 1 further including a current sensor and wherein the processing subsystem is further configured to measure power and energy using a current measurement output by the current sensor and a measured voltage sensed only by the second voltage sensing plate. 5. The system of claim 4 in which the processing subsystem is configured to apply a scaling factor to said power and energy measurements. 6. The system of claim 5 in which said scaling factor is a function of the measured voltage sensed by the first voltage sensing plate and the measured voltage sensed by the second voltage sensing plate. 7. The system of claim 6 in which the measured voltage sensed by the first voltage sensing plate is Vtop, the measured voltage sensing by the second voltage sensing plate is Vbot and the scaling factor is (1−c)Vtop+c Vbot divided by Vbot where c is a constant weighting factor. 8. The system of claim 1 in which the processing subsystem is configured to mitigate variations in said measurements by comparing the measured voltage sensed by the first voltage sensing plate and the measured voltage sensed by the second voltage sensing plate. 9. The system of claim 8 in which the processing subsystem is further configured to report a snow event when the measured voltage sensed by the first voltage sensing plate differs from the measured voltage sensed by the second voltage sensing plate by a predetermined value. 10. The system of claim 1 in which there are two electrically connected voltage sensing plates exposed to rain and snow and two electrically connected voltage sensing plates shield from rain and snow. 11. The system of claim 10 in which the housing has an apex between opposing outwardly sloping top voltage sensing plates exposed to rain and snow and opposing inwardly sloping bottom voltage sensing plates shielded from rain and snow. 12. The system of claim 1 in which the processing subsystem includes a first processor in the housing electrically connected to the first voltage sensing plate and separately electrically connected to the second voltage sensing plate. 13. The system of claim 12 further including a collector and the processing subsystem further includes a second processor in the collector. 14. An ungrounded power line sensing method comprising:
measuring a voltage sensed by a first voltage sensing plate proximate a power line and exposed to rain and snow; separately measuring the voltage sensed by a second voltage sensing plate proximate a power line and shielded from rain and snow; and mitigating variations in said measurements due to a weather event. 15. The method of claim 14 in which mitigating variations in said measurements includes applying a weighted average calculation to said measurements to cancel out effects of rain on the first voltage sensing plate. 16. The method of claim 15 in which the measured voltage sensed by the first voltage sensing plate is Vtop, the measured voltage sensed by the second voltage sensing plate is Vbottom, and the weighted average calculation is Vavg=(1−c)Vtop+c Vbot where c is a constant weighting factor. 17. The method of claim 14 further including measuring power line current and measuring power and energy using a current measurement and a measured voltage sensed only by the second voltage sensing plate. 18. The method of claim 17 further including applying a scaling factor to said power and energy measurements. 19. The method of claim 18 in which said scaling factor is a function of the measured voltage sensed by the first voltage sensing plate and the measured voltage sensed by the second voltage sensing plate. 20. The method of claim 19 in which the measured voltage sensed by the first voltage sensing plate is Vtop, the measured voltage sensing by the second voltage sensing plate is Vbot, and the scaling factor is (1−c)Vtop+c Vbot divided by Vbot where c is a constant weighting factor. 21. The method of claim 14 in which mitigating variations in said measurements includes comparing the measured voltage sensed by the first voltage sensing plate and the measured voltage sensed by the second voltage sensing plate. 22. The method of claim 21 further including reporting a snow event when the measured voltage sensed by the first voltage sensing plate differs from the measured voltage sensed by the second voltage sensing plate by a predetermined value. 23. The method of claim 14 in which there are two electrically connected voltage sensing plates exposed to rain and snow and two electrically connected voltage sensing plates shield from rain and snow. 24. An ungrounded power line sensor system comprising:
a housing configured for disposal about a power line; a current sensor associated with the housing for measuring power line current; a first voltage sensing plate supported by the housing and exposed to rain and snow; a second voltage sensing plate supported by the housing and shielded from rain and snow; and a processing subsystem configured to:
measure a voltage sensed by the first voltage sensing plate,
measure a voltage sensed by the second voltage sensing plate,
mitigate variations in said measurements by applying a weighted average calculation to said voltage measurements to cancel out the effects of rain on the first voltage sensing plate, and
measure power and energy using the power line current measurement and only the measured voltage sensed by the second voltage sensing plate. 25. An ungrounded power line sensing method comprising:
measuring a voltage sensed by a first voltage sensing plate proximate a power line and exposed to rain and snow; measuring a voltage sensed by a second voltage sensing plate proximate a power line and shielded from rain and snow; measuring power line current; applying a weighted average calculation to said voltage measurements to cancel out the effects of rain on the first voltage sensing plate; and measuring power and energy using the measured current and only the measured voltage sensed by the second voltage sensing plate. | An ungrounded power line sensor system includes a housing configured for coupling about a power line, at least a first voltage sensing plate supported by the housing and exposed to rain and snow, and at least a second voltage sensing plate supported by the housing and shielded from rain and snow. Voltages sensed by the first and second voltage sensing plate are separately measured in order to mitigate variations in the two measurements due to a weather event, for example by applying a weighted average calculation to the measurements to cancel out the effects of rain on the first voltage sensing plate.1. An ungrounded power line sensor system comprising:
a housing configured for coupling about a power line; at least a first voltage sensing plate supported by the housing and exposed to rain and snow; at least a second voltage sensing plate supported by the housing and shielded from rain and snow; and a processing subsystem configured to:
measure a voltage sensed by the first voltage sensing plate,
separately measure a voltage sensed by the second voltage sensing plate, and
mitigate variations in said measurements due to a weather event. 2. The system of claim 1 in which the processing subsystem is configured to mitigate variations in said measurements by applying a weighted average calculation to said measurements to cancel out the effects of rain on the first voltage sensing plate. 3. The system of claim 2 in which the measured voltage sensed by the first voltage sensing plate is Vtop, the measured voltage sensed by the second voltage sensing plate is Vbottom, and the weighted average calculation is Vavg=(1−c)Vtop+c Vbot where c is a constant weighting factor. 4. The system of claim 1 further including a current sensor and wherein the processing subsystem is further configured to measure power and energy using a current measurement output by the current sensor and a measured voltage sensed only by the second voltage sensing plate. 5. The system of claim 4 in which the processing subsystem is configured to apply a scaling factor to said power and energy measurements. 6. The system of claim 5 in which said scaling factor is a function of the measured voltage sensed by the first voltage sensing plate and the measured voltage sensed by the second voltage sensing plate. 7. The system of claim 6 in which the measured voltage sensed by the first voltage sensing plate is Vtop, the measured voltage sensing by the second voltage sensing plate is Vbot and the scaling factor is (1−c)Vtop+c Vbot divided by Vbot where c is a constant weighting factor. 8. The system of claim 1 in which the processing subsystem is configured to mitigate variations in said measurements by comparing the measured voltage sensed by the first voltage sensing plate and the measured voltage sensed by the second voltage sensing plate. 9. The system of claim 8 in which the processing subsystem is further configured to report a snow event when the measured voltage sensed by the first voltage sensing plate differs from the measured voltage sensed by the second voltage sensing plate by a predetermined value. 10. The system of claim 1 in which there are two electrically connected voltage sensing plates exposed to rain and snow and two electrically connected voltage sensing plates shield from rain and snow. 11. The system of claim 10 in which the housing has an apex between opposing outwardly sloping top voltage sensing plates exposed to rain and snow and opposing inwardly sloping bottom voltage sensing plates shielded from rain and snow. 12. The system of claim 1 in which the processing subsystem includes a first processor in the housing electrically connected to the first voltage sensing plate and separately electrically connected to the second voltage sensing plate. 13. The system of claim 12 further including a collector and the processing subsystem further includes a second processor in the collector. 14. An ungrounded power line sensing method comprising:
measuring a voltage sensed by a first voltage sensing plate proximate a power line and exposed to rain and snow; separately measuring the voltage sensed by a second voltage sensing plate proximate a power line and shielded from rain and snow; and mitigating variations in said measurements due to a weather event. 15. The method of claim 14 in which mitigating variations in said measurements includes applying a weighted average calculation to said measurements to cancel out effects of rain on the first voltage sensing plate. 16. The method of claim 15 in which the measured voltage sensed by the first voltage sensing plate is Vtop, the measured voltage sensed by the second voltage sensing plate is Vbottom, and the weighted average calculation is Vavg=(1−c)Vtop+c Vbot where c is a constant weighting factor. 17. The method of claim 14 further including measuring power line current and measuring power and energy using a current measurement and a measured voltage sensed only by the second voltage sensing plate. 18. The method of claim 17 further including applying a scaling factor to said power and energy measurements. 19. The method of claim 18 in which said scaling factor is a function of the measured voltage sensed by the first voltage sensing plate and the measured voltage sensed by the second voltage sensing plate. 20. The method of claim 19 in which the measured voltage sensed by the first voltage sensing plate is Vtop, the measured voltage sensing by the second voltage sensing plate is Vbot, and the scaling factor is (1−c)Vtop+c Vbot divided by Vbot where c is a constant weighting factor. 21. The method of claim 14 in which mitigating variations in said measurements includes comparing the measured voltage sensed by the first voltage sensing plate and the measured voltage sensed by the second voltage sensing plate. 22. The method of claim 21 further including reporting a snow event when the measured voltage sensed by the first voltage sensing plate differs from the measured voltage sensed by the second voltage sensing plate by a predetermined value. 23. The method of claim 14 in which there are two electrically connected voltage sensing plates exposed to rain and snow and two electrically connected voltage sensing plates shield from rain and snow. 24. An ungrounded power line sensor system comprising:
a housing configured for disposal about a power line; a current sensor associated with the housing for measuring power line current; a first voltage sensing plate supported by the housing and exposed to rain and snow; a second voltage sensing plate supported by the housing and shielded from rain and snow; and a processing subsystem configured to:
measure a voltage sensed by the first voltage sensing plate,
measure a voltage sensed by the second voltage sensing plate,
mitigate variations in said measurements by applying a weighted average calculation to said voltage measurements to cancel out the effects of rain on the first voltage sensing plate, and
measure power and energy using the power line current measurement and only the measured voltage sensed by the second voltage sensing plate. 25. An ungrounded power line sensing method comprising:
measuring a voltage sensed by a first voltage sensing plate proximate a power line and exposed to rain and snow; measuring a voltage sensed by a second voltage sensing plate proximate a power line and shielded from rain and snow; measuring power line current; applying a weighted average calculation to said voltage measurements to cancel out the effects of rain on the first voltage sensing plate; and measuring power and energy using the measured current and only the measured voltage sensed by the second voltage sensing plate. | 2,800 |
12,193 | 12,193 | 15,910,223 | 2,834 | An electric motor assembly includes a rotor assembly configured to rotate about a central axis and a stator assembly configured to extend about the rotor assembly. The rotor assembly includes at least one of the following: a plurality of spokes and at least one neodymium iron boron magnet. The stator assembly includes an annular body including an inner surface and an outer surface. A first thickness is defined between the inner surface and the outer surface. The stator assembly also includes a plurality of stator teeth extending radially from the annular body and spaced circumferentially about the annular body. Each stator tooth has a second thickness. A ratio of the second thickness to the first thickness is in a range of about 0.5 to about 1. The stator assembly includes no more than 24 slots defined by the plurality of stator teeth. | 1. An electric motor assembly comprising:
a rotor assembly configured to rotate about a central axis, wherein said rotor assembly includes at least one of the following: a plurality of spokes and at least one neodymium iron boron magnet; and a stator assembly configured to extend about said rotor assembly, said stator assembly comprising:
an annular body extending about the central axis, said annular body including an inner surface and an outer surface, wherein said inner surface and said outer surface extend about the central axis and are spaced radially apart, said annular body having a first thickness defined between said inner surface and said outer surface;
a plurality of stator teeth extending radially from said annular body and spaced circumferentially about said annular body, each stator tooth of said plurality of stator teeth having a second thickness, wherein a ratio of said second thickness to said first thickness is in a range of about 0.5 to about 1; and
a plurality of slots defined by said plurality of stator teeth, wherein said plurality of slots comprises no more than 24 slots. 2. The electric motor assembly in accordance with claim 1, wherein the first thickness is at least about 8 millimeter (mm), and an outer diameter of said annular body is approximately 140 mm. 3. The electric motor assembly in accordance with claim 2, wherein the second thickness is less than about 9 mm. 4. The electric motor assembly in accordance with claim 1 further comprising a housing coupled to said stator assembly and configured to enclose said stator assembly, said housing including a shell and an end shield coupled to said shell, wherein said shell and said end shield are substantially solid. 5. The electric motor assembly in accordance with claim 4, wherein said shell has a thickness of at least about 1.5 mm. 6. The electric motor assembly in accordance with claim 4, wherein said end shield includes a plate extending across an end of said shell. 7. The electric motor assembly in accordance with claim 1, wherein each stator tooth of said plurality of stator teeth includes an end and a pair of side surfaces extending from said inner surface to said end, wherein said pair of side surfaces define the second thickness therebetween. 8. The electric motor assembly in accordance with claim 7, wherein each stator tooth of said plurality of stator teeth is configured to receive a conduction coil such that the conduction coil extends about said pair of side surfaces and through the plurality of slots. 9. The electric motor assembly in accordance with claim 8, wherein said rotor assembly provides a magnetic flux that interacts with said stator assembly such that said rotor assembly rotates when voltage is applied to the conduction coils. 10. The electric motor assembly in accordance with claim 1, wherein said outer surface includes at least one curved portion extending at least partially about the central axis. 11. A stator assembly for an electric motor assembly, said stator assembly comprising:
an annular body extending about a central axis, said annular body including an inner surface and an outer surface, wherein said inner surface and said outer surface extend about the central axis and are spaced radially apart, said annular body having a first thickness defined between said inner surface and said outer surface, wherein said stator assembly is configured to cause rotation of a rotor assembly about a central axis, wherein the rotor assembly includes at least one of the following: a plurality of spokes and at least one neodymium iron boron magnet; a plurality of stator teeth extending radially from said annular body and spaced circumferentially about said annular body, each stator tooth of said plurality of stator teeth having a second thickness, wherein a ratio of the second thickness to said first thickness is in a range of about 0.5 to about 1; and a plurality of slots defined by said plurality of stator teeth, wherein said plurality of slots comprises no more than 24 slots. 12. The stator assembly in accordance with claim 11, wherein the first thickness is at least about 8 millimeters (mm), and an outer diameter of said annular body is approximately 140 mm. 13. The stator assembly in accordance with claim 12, wherein the second thickness is less than about 9 mm. 14. The stator assembly in accordance with claim 11, wherein each stator tooth of said plurality of stator teeth includes an end and a pair of side surfaces extending from said inner surface to said end, wherein said pair of side surfaces define the second thickness therebetween, each stator tooth of said plurality of stator teeth configured to receive a conduction coil such that the conduction coil extends about said pair of side surfaces and through the plurality of slots. 15. A method of assembling an electric motor assembly, said method comprising:
coupling a rotor assembly to a bearing such that the rotor assembly is configured to rotate about a central axis, wherein the rotor assembly includes at least one of the following: a plurality of spokes and at least one neodymium iron boron magnet; positioning a stator assembly along the central axis, the stator assembly including a plurality of stator teeth and an annular body extending about the central axis, the annular body including an inner surface and an outer surface, wherein the inner surface and the outer surface extend about the central axis and are spaced radially apart, the annular body having a first thickness defined between the inner surface and the outer surface; positioning the stator assembly adjacent the rotor assembly such that the plurality of stator teeth are spaced about the rotor assembly, wherein the plurality of stator teeth extend radially from the annular body and are spaced circumferentially about the annular body, each stator tooth of said plurality of stator teeth having a second thickness, wherein a ratio of the second thickness to the first thickness is in a range of about 0.5 to about 1; and positioning a plurality of conduction coils about the plurality of stator teeth, wherein each conduction coil of the plurality of conduction coils is coupled to one stator tooth of the plurality of stator teeth. 16. The method in accordance with claim 15 further comprising coupling a housing to the stator assembly to enclose the stator assembly, the housing including a shell and an end shield, wherein the shell and the end shield are substantially solid. 17. The method in accordance with claim 16, further comprising positioning the shell about the stator assembly, wherein the shell has a thickness of at least about 1.5 mm. 18. The method in accordance with claim 16, further comprising coupling an end shield to the shell, wherein the end shield includes a plate configured to extend across an end of the shell. 19. The method in accordance with claim 15, wherein positioning a plurality of conduction coils about the plurality of stator teeth comprises positioning the plurality of conduction coils such that the conduction coils extend about side surfaces of each stator tooth and through a plurality of slots defined between stator teeth. 20. The method in accordance with claim 19 further comprising positioning the rotor assembly within the stator assembly, wherein the rotor assembly provides a magnetic flux that interacts with the stator assembly such that the rotor assembly rotates when voltage is applied to the conduction coils. | An electric motor assembly includes a rotor assembly configured to rotate about a central axis and a stator assembly configured to extend about the rotor assembly. The rotor assembly includes at least one of the following: a plurality of spokes and at least one neodymium iron boron magnet. The stator assembly includes an annular body including an inner surface and an outer surface. A first thickness is defined between the inner surface and the outer surface. The stator assembly also includes a plurality of stator teeth extending radially from the annular body and spaced circumferentially about the annular body. Each stator tooth has a second thickness. A ratio of the second thickness to the first thickness is in a range of about 0.5 to about 1. The stator assembly includes no more than 24 slots defined by the plurality of stator teeth.1. An electric motor assembly comprising:
a rotor assembly configured to rotate about a central axis, wherein said rotor assembly includes at least one of the following: a plurality of spokes and at least one neodymium iron boron magnet; and a stator assembly configured to extend about said rotor assembly, said stator assembly comprising:
an annular body extending about the central axis, said annular body including an inner surface and an outer surface, wherein said inner surface and said outer surface extend about the central axis and are spaced radially apart, said annular body having a first thickness defined between said inner surface and said outer surface;
a plurality of stator teeth extending radially from said annular body and spaced circumferentially about said annular body, each stator tooth of said plurality of stator teeth having a second thickness, wherein a ratio of said second thickness to said first thickness is in a range of about 0.5 to about 1; and
a plurality of slots defined by said plurality of stator teeth, wherein said plurality of slots comprises no more than 24 slots. 2. The electric motor assembly in accordance with claim 1, wherein the first thickness is at least about 8 millimeter (mm), and an outer diameter of said annular body is approximately 140 mm. 3. The electric motor assembly in accordance with claim 2, wherein the second thickness is less than about 9 mm. 4. The electric motor assembly in accordance with claim 1 further comprising a housing coupled to said stator assembly and configured to enclose said stator assembly, said housing including a shell and an end shield coupled to said shell, wherein said shell and said end shield are substantially solid. 5. The electric motor assembly in accordance with claim 4, wherein said shell has a thickness of at least about 1.5 mm. 6. The electric motor assembly in accordance with claim 4, wherein said end shield includes a plate extending across an end of said shell. 7. The electric motor assembly in accordance with claim 1, wherein each stator tooth of said plurality of stator teeth includes an end and a pair of side surfaces extending from said inner surface to said end, wherein said pair of side surfaces define the second thickness therebetween. 8. The electric motor assembly in accordance with claim 7, wherein each stator tooth of said plurality of stator teeth is configured to receive a conduction coil such that the conduction coil extends about said pair of side surfaces and through the plurality of slots. 9. The electric motor assembly in accordance with claim 8, wherein said rotor assembly provides a magnetic flux that interacts with said stator assembly such that said rotor assembly rotates when voltage is applied to the conduction coils. 10. The electric motor assembly in accordance with claim 1, wherein said outer surface includes at least one curved portion extending at least partially about the central axis. 11. A stator assembly for an electric motor assembly, said stator assembly comprising:
an annular body extending about a central axis, said annular body including an inner surface and an outer surface, wherein said inner surface and said outer surface extend about the central axis and are spaced radially apart, said annular body having a first thickness defined between said inner surface and said outer surface, wherein said stator assembly is configured to cause rotation of a rotor assembly about a central axis, wherein the rotor assembly includes at least one of the following: a plurality of spokes and at least one neodymium iron boron magnet; a plurality of stator teeth extending radially from said annular body and spaced circumferentially about said annular body, each stator tooth of said plurality of stator teeth having a second thickness, wherein a ratio of the second thickness to said first thickness is in a range of about 0.5 to about 1; and a plurality of slots defined by said plurality of stator teeth, wherein said plurality of slots comprises no more than 24 slots. 12. The stator assembly in accordance with claim 11, wherein the first thickness is at least about 8 millimeters (mm), and an outer diameter of said annular body is approximately 140 mm. 13. The stator assembly in accordance with claim 12, wherein the second thickness is less than about 9 mm. 14. The stator assembly in accordance with claim 11, wherein each stator tooth of said plurality of stator teeth includes an end and a pair of side surfaces extending from said inner surface to said end, wherein said pair of side surfaces define the second thickness therebetween, each stator tooth of said plurality of stator teeth configured to receive a conduction coil such that the conduction coil extends about said pair of side surfaces and through the plurality of slots. 15. A method of assembling an electric motor assembly, said method comprising:
coupling a rotor assembly to a bearing such that the rotor assembly is configured to rotate about a central axis, wherein the rotor assembly includes at least one of the following: a plurality of spokes and at least one neodymium iron boron magnet; positioning a stator assembly along the central axis, the stator assembly including a plurality of stator teeth and an annular body extending about the central axis, the annular body including an inner surface and an outer surface, wherein the inner surface and the outer surface extend about the central axis and are spaced radially apart, the annular body having a first thickness defined between the inner surface and the outer surface; positioning the stator assembly adjacent the rotor assembly such that the plurality of stator teeth are spaced about the rotor assembly, wherein the plurality of stator teeth extend radially from the annular body and are spaced circumferentially about the annular body, each stator tooth of said plurality of stator teeth having a second thickness, wherein a ratio of the second thickness to the first thickness is in a range of about 0.5 to about 1; and positioning a plurality of conduction coils about the plurality of stator teeth, wherein each conduction coil of the plurality of conduction coils is coupled to one stator tooth of the plurality of stator teeth. 16. The method in accordance with claim 15 further comprising coupling a housing to the stator assembly to enclose the stator assembly, the housing including a shell and an end shield, wherein the shell and the end shield are substantially solid. 17. The method in accordance with claim 16, further comprising positioning the shell about the stator assembly, wherein the shell has a thickness of at least about 1.5 mm. 18. The method in accordance with claim 16, further comprising coupling an end shield to the shell, wherein the end shield includes a plate configured to extend across an end of the shell. 19. The method in accordance with claim 15, wherein positioning a plurality of conduction coils about the plurality of stator teeth comprises positioning the plurality of conduction coils such that the conduction coils extend about side surfaces of each stator tooth and through a plurality of slots defined between stator teeth. 20. The method in accordance with claim 19 further comprising positioning the rotor assembly within the stator assembly, wherein the rotor assembly provides a magnetic flux that interacts with the stator assembly such that the rotor assembly rotates when voltage is applied to the conduction coils. | 2,800 |
12,194 | 12,194 | 16,060,545 | 2,845 | The present disclosure provides a low band dipole and a multi-band multi-port antenna arrangement, wherein the low band dipole has four dipole arms, and the four dipole arms are horizontally and mutually perpendicularly placed in a “+” shape and adjacent two mutually perpendicular dipole arms are fed therebetween. The antenna arrangement includes a main reflector, at least one column of low band dipole array disposed on the main reflector, and at least one column of high band dipole array adjacent to the at least one column of the low band dipole array, wherein at least one low band dipole in each column of the at least one column of low band dipole array satisfies the following condition: the low band dipole has four dipole arms, and the four dipole arms are horizontally and mutually perpendicularly placed in a “+” shape, and adjacent two mutually perpendicular dipole arms are fed therebetween to form a +/−45 degree polarization. The multi-band multi-port antenna arrangement solves the problem that the high and low band dipole arms shield each other and reduces the mutual coupling between the high and low band dipoles by adopting the above-mentioned structure of the low band dipole. | 1. A low band dipole, wherein the low band dipole has four dipole arms, and the four dipole arms are horizontally and mutually perpendicularly placed in a “+” shape, and adjacent two mutually perpendicular dipole arms are fed therebetween. 2. The low band dipole according to claim 1, wherein the feeding mode comprises at least any one of the following:
coupling feeding; direct feeding. 3. The low band dipole according to claim 1, wherein at least one of the four dipole arms is in a sheet shape. 4. The low band dipole according to claim 1, wherein at least one of the four dipole arms is in a columnar shape. 5. The low band dipole according to claim 1, wherein at least one of the four dipole arms is a combination of a solid columnar wire and a hollow columnar metal shell, and the cross-sectional area of the hollow columnar metal shell is different from that of the solid columnar wire. 6. The low band dipole according to claim 1, wherein a reverse current loop is provided on at least one of the four dipole arms. 7. The low band dipole according to claim 1, wherein at least one groove is provided on at least one of the four dipole arms. 8. A multi-band multi-port antenna arrangement, wherein the antenna arrangement comprises: a main reflector, at least one column of low band dipole array disposed on the main reflector, and at least one column of high band dipole array adjacent to the at least one column of low band dipole array, wherein each column of the at least one column of low band dipole array includes at least one low band dipole according to claim 1, wherein the low band dipole and the high band dipole do not shield each other. 9. The antenna arrangement according to claim 8, wherein a high band dipole is disposed on at least one corner of the four dipole arms of at least one of the low band dipoles, wherein the four dipole arms are horizontally and mutually perpendicularly arranged in the “+” shape. 10. The antenna arrangement according to claim 9, wherein the types of high band dipoles disposed on the at least one corner may be different. 11. The antenna arrangement according to claim 8, wherein the cross-sectional area of the at least one dipole arm in a columnar shape is set according to performance requirement of the antenna. 12. The antenna arrangement according to claim 8, wherein the cross-sectional area of the hollow columnar metal shell and the cross-sectional area of the solid columnar wire are respectively set according to the performance requirement of the antenna. | The present disclosure provides a low band dipole and a multi-band multi-port antenna arrangement, wherein the low band dipole has four dipole arms, and the four dipole arms are horizontally and mutually perpendicularly placed in a “+” shape and adjacent two mutually perpendicular dipole arms are fed therebetween. The antenna arrangement includes a main reflector, at least one column of low band dipole array disposed on the main reflector, and at least one column of high band dipole array adjacent to the at least one column of the low band dipole array, wherein at least one low band dipole in each column of the at least one column of low band dipole array satisfies the following condition: the low band dipole has four dipole arms, and the four dipole arms are horizontally and mutually perpendicularly placed in a “+” shape, and adjacent two mutually perpendicular dipole arms are fed therebetween to form a +/−45 degree polarization. The multi-band multi-port antenna arrangement solves the problem that the high and low band dipole arms shield each other and reduces the mutual coupling between the high and low band dipoles by adopting the above-mentioned structure of the low band dipole.1. A low band dipole, wherein the low band dipole has four dipole arms, and the four dipole arms are horizontally and mutually perpendicularly placed in a “+” shape, and adjacent two mutually perpendicular dipole arms are fed therebetween. 2. The low band dipole according to claim 1, wherein the feeding mode comprises at least any one of the following:
coupling feeding; direct feeding. 3. The low band dipole according to claim 1, wherein at least one of the four dipole arms is in a sheet shape. 4. The low band dipole according to claim 1, wherein at least one of the four dipole arms is in a columnar shape. 5. The low band dipole according to claim 1, wherein at least one of the four dipole arms is a combination of a solid columnar wire and a hollow columnar metal shell, and the cross-sectional area of the hollow columnar metal shell is different from that of the solid columnar wire. 6. The low band dipole according to claim 1, wherein a reverse current loop is provided on at least one of the four dipole arms. 7. The low band dipole according to claim 1, wherein at least one groove is provided on at least one of the four dipole arms. 8. A multi-band multi-port antenna arrangement, wherein the antenna arrangement comprises: a main reflector, at least one column of low band dipole array disposed on the main reflector, and at least one column of high band dipole array adjacent to the at least one column of low band dipole array, wherein each column of the at least one column of low band dipole array includes at least one low band dipole according to claim 1, wherein the low band dipole and the high band dipole do not shield each other. 9. The antenna arrangement according to claim 8, wherein a high band dipole is disposed on at least one corner of the four dipole arms of at least one of the low band dipoles, wherein the four dipole arms are horizontally and mutually perpendicularly arranged in the “+” shape. 10. The antenna arrangement according to claim 9, wherein the types of high band dipoles disposed on the at least one corner may be different. 11. The antenna arrangement according to claim 8, wherein the cross-sectional area of the at least one dipole arm in a columnar shape is set according to performance requirement of the antenna. 12. The antenna arrangement according to claim 8, wherein the cross-sectional area of the hollow columnar metal shell and the cross-sectional area of the solid columnar wire are respectively set according to the performance requirement of the antenna. | 2,800 |
12,195 | 12,195 | 16,142,410 | 2,871 | Provided is a display apparatus including a display panel for displaying an image, a heat source arranged at a side surface of at least one side of the display panel, a heat absorbing section for absorbing heat generated by the heat source, a back surface plate arranged at a back surface side of the display panel and made of a metal, a portion of the back surface plate being in c lose contact with the heat absorbing section, a front surface plate arranged at a front surface side of the display panel and made of a metal, and a middle chassis arranged between the front surface plate and the heat absorbing section. | 1. (canceled) 2. A display apparatus comprising:
a display panel for displaying an image; a heat source arranged at a side surface of at least one side of the display panel; a heat absorbing section for absorbing heat generated by the heat source; a back surface plate comprising a metal arranged at a back surface side of the display panel, wherein a portion of the back surface plate is in close contact with the heat absorbing section; an optical waveguide arranged at the back surface side of the display panel; a front surface plate arranged at a front surface side of the display panel; a middle chassis arranged between the front surface plate and the heat absorbing section; a back chassis arranged at a back surface side of the back surface plate; and a panel control board mounted on the back chassis, the panel control board controlling drive of the display panel and being located at a central portion of the back surface side of the back surface plate. 3. The display apparatus according to claim 2, wherein the middle chassis is made of a material having a thermal conductivity lower than a thermal conductivity of the heat absorbing section. 4. The display apparatus according to claim 2, further comprising:
a panel driver board for controlling display of an image on the display panel; and a flexible board for connecting the panel control board and the panel driver board, wherein the back surface plate has a recessed portion, having an indentation corresponding to a width, a length, and a thickness of the flexible board, to place the flexible boards therein. 5. The display apparatus according to claim 2, wherein a peripheral portion of the front surface plate has a tapered portion extending from a front surface side of the front surface plate to a back surface side of the front surface plate so as to make the back surface side of the front surface plate smaller. 6. The display apparatus according to claim 2, further comprising:
the heat source emitting a visible light; and a light radiation unit comprising the optical waveguide for diffusing the light emitted by the heat source to radiate the diffused light onto the display panel, thus displaying an image on the display panel. 7. The display apparatus according to claim 2, wherein the heat absorbing section is arranged along a side surface of the display panel. 8. The display apparatus according to claim 2, further including a thermally conductive material adhering the heat absorbing section to the back surface plate. 9. The display apparatus of claim 2,
wherein the back chassis is further mounted thereon at least one of a signal board, a power supply board, or an LED driver board. 10. The display apparatus of claim 9, wherein heat generated by at least one of the panel control board, the signal board, the power supply board, or the LED driver board is discharged from the back chassis. 11. The display apparatus of claim 2, further comprising:
a stand coupled with the back chassis. 12. The display apparatus of claim 11, wherein the back chassis is detachable from the stand. 13. The display apparatus of claim 12, wherein the back chassis includes a fastening section for fixing to a wall after the back chassis is detached from the stand. 14. The display apparatus of claim 2, wherein the central portion is substantially in a center of the back surface plate in a horizontal direction. 15. The display apparatus of claim 2, wherein the back surface side of the back surface plate is coated with a material comprising rubber. 16. The display apparatus of claim 11, further comprising:
an arm section coupled to the stand; and a cover disposed on the arm section in an openable and closable manner. 17. The display apparatus of claim 16,
wherein the arm section is configured to accommodate an electric cord. 18. The display apparatus of claim 16,
wherein the arm section is coupled to the stand and the back chassis. 19. The display apparatus of claim 16, further comprising:
a speaker incorporated with the stand. 20. The display apparatus of claim 19, further comprising:
at least one connector electrically connecting the back chassis and the stand, wherein the speaker is electrically connected with the at least one connector. 21. A display apparatus comprising:
a display panel for displaying an image; an optical sheet arranged at a back surface side of the display panel; a heat source arranged at a side surface of at least one side of the display panel; a heat absorbing section for absorbing heat generated by the heat source; a back surface plate comprising a metal arranged at the back surface side of the display panel, wherein a portion of the back surface plate is in close contact with the heat absorbing section; a front surface plate arranged at a front surface side of the display panel; and a middle chassis arranged between the front surface plate and the heat absorbing section, in which the middle chassis is made of a non-metal material having a thermal conductivity lower than a thermal conductivity of the heat absorbing section to suppress heat generated by the heat source from being discharged from the front surface plate such that when the generated heat is absorbed by the heat absorbing section an amount of heat discharged from the front surface plate is less than that discharged from the back surface plate. 22. The display apparatus according to claim 21, further comprising at least one of a panel control board, a panel driver board, or a flexible board. 23. The display apparatus according to claim 21, wherein the middle chassis is made a material comprising synthetic resin. 24. The display apparatus according to claim 21, further comprising:
a plurality of heat sources emitting visible light; an optical waveguide arranged at a back surface side of the optical sheet; and a light radiation unit comprising the optical waveguide and the optical sheet for diffusing the light emitted by the plurality of heat sources to radiate the diffused light onto the display panel, thus displaying an image on the display panel. 25. The display apparatus according to claim 24, wherein the plurality of heat sources are arranged at positions along at least one given side of the display panel. 26. The display apparatus according to claim 24, wherein the light radiation unit comprises a back surface on which diffusion material is printed. 27. The display apparatus according to claim 24, wherein the light radiation unit is made of a material comprising silicone rubber resin. 28. The display apparatus according to claim 24, wherein the light radiation unit further performs at least one of a process of decomposing display light incident to the display panel or a process of compensating a phase difference of a lightwave. 29. The display apparatus according to claim 21, wherein the display panel comprises two glass substrates and two polarization plates. 30. The display apparatus according to claim 29, further comprising a panel driver board, wherein the two glass substrates receive voltages applied by the panel driver board. 31. The display apparatus according to claim 29, wherein the two glass substrates are sealed between the two polarization plates. 32. The display apparatus according to claim 29, wherein the display panel further comprises a liquid crystal layer, the liquid crystal layer being formed between the two glass substrates. 33. The display apparatus according to claim 32, wherein orientation states of the liquid crystal layer are changed by applying voltages with a panel driver board. 34. The display apparatus according to claim 21, in which an outer or exterior surface of the back surface plate is coated with rubber. 35. The display apparatus according to claim 22, wherein the panel control board is connected to the panel driver board via the flexible board and the panel control board is positioned in back of the back surface plate. 36. The display apparatus according to claim 35, wherein the front surface plate comprises a second metal. 37. A display apparatus comprising:
a display panel for displaying an image; a heat source arranged at a side surface of at least one side of the display panel; a heat absorbing section for absorbing heat generated by the heat source; a back surface plate comprising a metal arranged at a back surface side of the display panel, wherein a portion of the back surface plate is in close contact with the heat absorbing section; a front surface plate arranged at a front surface side of the display panel; and a middle chassis comprising a non-metal arranged between the front surface plate and the heat absorbing section, wherein a width of the heat absorbing section facing the back surface plate is larger than a width of the heat absorbing section facing the heat source. 38. The display apparatus according to claim 37, wherein the front surface plate comprises a second metal. 39. The display apparatus according to claim 37, wherein the middle chassis is made of a material having a thermal conductivity lower than a thermal conductivity of the heat absorbing section. 40. The display apparatus of claim 37, further comprising:
a back chassis arranged at a back surface side of the back surface plate; and at least one of a panel control board, signal board, a power supply board, or an LED driver board mounted on the back chassis. 41. The display apparatus of claim 40, wherein heat generated by at least one of the panel control board, the signal board, the power supply board, or the LED driver board is discharged from the back chassis. 42. A display apparatus comprising:
a display panel for displaying an image; a heat source arranged at a side surface of at least one side of the display panel; a heat absorbing section for absorbing heat generated by the heat source, the heat source in close contact with the heat absorbing section on a side of the heat absorbing section; a back surface plate comprising a metal arranged at a back surface side of the display panel, the back surface plate having a portion in close contact with the heat absorbing section; a front surface plate arranged at a front surface side of the display panel; a middle chassis, arranged between the front surface plate and the heat absorbing section, for conducting the heat absorbed by the heat absorbing section to the front surface plate; and a chassis arranged at a back surface side of the back surface plate, and having thereon a panel control board for driving the display panel, wherein the chassis has a connecting unit for fixing and installing the display panel, and a width of the side of the heat absorbing section to which the heat source is in close contact is smaller than a width of another side of the heat absorbing section to which the back surface plate is in close contact. 43. The display apparatus according to claim 42, wherein the middle chassis is made of a material having a thermal conductivity lower than a thermal conductivity of the heat absorbing section. 44. The display apparatus according to claim 43, wherein the front surface plate comprises a second metal. | Provided is a display apparatus including a display panel for displaying an image, a heat source arranged at a side surface of at least one side of the display panel, a heat absorbing section for absorbing heat generated by the heat source, a back surface plate arranged at a back surface side of the display panel and made of a metal, a portion of the back surface plate being in c lose contact with the heat absorbing section, a front surface plate arranged at a front surface side of the display panel and made of a metal, and a middle chassis arranged between the front surface plate and the heat absorbing section.1. (canceled) 2. A display apparatus comprising:
a display panel for displaying an image; a heat source arranged at a side surface of at least one side of the display panel; a heat absorbing section for absorbing heat generated by the heat source; a back surface plate comprising a metal arranged at a back surface side of the display panel, wherein a portion of the back surface plate is in close contact with the heat absorbing section; an optical waveguide arranged at the back surface side of the display panel; a front surface plate arranged at a front surface side of the display panel; a middle chassis arranged between the front surface plate and the heat absorbing section; a back chassis arranged at a back surface side of the back surface plate; and a panel control board mounted on the back chassis, the panel control board controlling drive of the display panel and being located at a central portion of the back surface side of the back surface plate. 3. The display apparatus according to claim 2, wherein the middle chassis is made of a material having a thermal conductivity lower than a thermal conductivity of the heat absorbing section. 4. The display apparatus according to claim 2, further comprising:
a panel driver board for controlling display of an image on the display panel; and a flexible board for connecting the panel control board and the panel driver board, wherein the back surface plate has a recessed portion, having an indentation corresponding to a width, a length, and a thickness of the flexible board, to place the flexible boards therein. 5. The display apparatus according to claim 2, wherein a peripheral portion of the front surface plate has a tapered portion extending from a front surface side of the front surface plate to a back surface side of the front surface plate so as to make the back surface side of the front surface plate smaller. 6. The display apparatus according to claim 2, further comprising:
the heat source emitting a visible light; and a light radiation unit comprising the optical waveguide for diffusing the light emitted by the heat source to radiate the diffused light onto the display panel, thus displaying an image on the display panel. 7. The display apparatus according to claim 2, wherein the heat absorbing section is arranged along a side surface of the display panel. 8. The display apparatus according to claim 2, further including a thermally conductive material adhering the heat absorbing section to the back surface plate. 9. The display apparatus of claim 2,
wherein the back chassis is further mounted thereon at least one of a signal board, a power supply board, or an LED driver board. 10. The display apparatus of claim 9, wherein heat generated by at least one of the panel control board, the signal board, the power supply board, or the LED driver board is discharged from the back chassis. 11. The display apparatus of claim 2, further comprising:
a stand coupled with the back chassis. 12. The display apparatus of claim 11, wherein the back chassis is detachable from the stand. 13. The display apparatus of claim 12, wherein the back chassis includes a fastening section for fixing to a wall after the back chassis is detached from the stand. 14. The display apparatus of claim 2, wherein the central portion is substantially in a center of the back surface plate in a horizontal direction. 15. The display apparatus of claim 2, wherein the back surface side of the back surface plate is coated with a material comprising rubber. 16. The display apparatus of claim 11, further comprising:
an arm section coupled to the stand; and a cover disposed on the arm section in an openable and closable manner. 17. The display apparatus of claim 16,
wherein the arm section is configured to accommodate an electric cord. 18. The display apparatus of claim 16,
wherein the arm section is coupled to the stand and the back chassis. 19. The display apparatus of claim 16, further comprising:
a speaker incorporated with the stand. 20. The display apparatus of claim 19, further comprising:
at least one connector electrically connecting the back chassis and the stand, wherein the speaker is electrically connected with the at least one connector. 21. A display apparatus comprising:
a display panel for displaying an image; an optical sheet arranged at a back surface side of the display panel; a heat source arranged at a side surface of at least one side of the display panel; a heat absorbing section for absorbing heat generated by the heat source; a back surface plate comprising a metal arranged at the back surface side of the display panel, wherein a portion of the back surface plate is in close contact with the heat absorbing section; a front surface plate arranged at a front surface side of the display panel; and a middle chassis arranged between the front surface plate and the heat absorbing section, in which the middle chassis is made of a non-metal material having a thermal conductivity lower than a thermal conductivity of the heat absorbing section to suppress heat generated by the heat source from being discharged from the front surface plate such that when the generated heat is absorbed by the heat absorbing section an amount of heat discharged from the front surface plate is less than that discharged from the back surface plate. 22. The display apparatus according to claim 21, further comprising at least one of a panel control board, a panel driver board, or a flexible board. 23. The display apparatus according to claim 21, wherein the middle chassis is made a material comprising synthetic resin. 24. The display apparatus according to claim 21, further comprising:
a plurality of heat sources emitting visible light; an optical waveguide arranged at a back surface side of the optical sheet; and a light radiation unit comprising the optical waveguide and the optical sheet for diffusing the light emitted by the plurality of heat sources to radiate the diffused light onto the display panel, thus displaying an image on the display panel. 25. The display apparatus according to claim 24, wherein the plurality of heat sources are arranged at positions along at least one given side of the display panel. 26. The display apparatus according to claim 24, wherein the light radiation unit comprises a back surface on which diffusion material is printed. 27. The display apparatus according to claim 24, wherein the light radiation unit is made of a material comprising silicone rubber resin. 28. The display apparatus according to claim 24, wherein the light radiation unit further performs at least one of a process of decomposing display light incident to the display panel or a process of compensating a phase difference of a lightwave. 29. The display apparatus according to claim 21, wherein the display panel comprises two glass substrates and two polarization plates. 30. The display apparatus according to claim 29, further comprising a panel driver board, wherein the two glass substrates receive voltages applied by the panel driver board. 31. The display apparatus according to claim 29, wherein the two glass substrates are sealed between the two polarization plates. 32. The display apparatus according to claim 29, wherein the display panel further comprises a liquid crystal layer, the liquid crystal layer being formed between the two glass substrates. 33. The display apparatus according to claim 32, wherein orientation states of the liquid crystal layer are changed by applying voltages with a panel driver board. 34. The display apparatus according to claim 21, in which an outer or exterior surface of the back surface plate is coated with rubber. 35. The display apparatus according to claim 22, wherein the panel control board is connected to the panel driver board via the flexible board and the panel control board is positioned in back of the back surface plate. 36. The display apparatus according to claim 35, wherein the front surface plate comprises a second metal. 37. A display apparatus comprising:
a display panel for displaying an image; a heat source arranged at a side surface of at least one side of the display panel; a heat absorbing section for absorbing heat generated by the heat source; a back surface plate comprising a metal arranged at a back surface side of the display panel, wherein a portion of the back surface plate is in close contact with the heat absorbing section; a front surface plate arranged at a front surface side of the display panel; and a middle chassis comprising a non-metal arranged between the front surface plate and the heat absorbing section, wherein a width of the heat absorbing section facing the back surface plate is larger than a width of the heat absorbing section facing the heat source. 38. The display apparatus according to claim 37, wherein the front surface plate comprises a second metal. 39. The display apparatus according to claim 37, wherein the middle chassis is made of a material having a thermal conductivity lower than a thermal conductivity of the heat absorbing section. 40. The display apparatus of claim 37, further comprising:
a back chassis arranged at a back surface side of the back surface plate; and at least one of a panel control board, signal board, a power supply board, or an LED driver board mounted on the back chassis. 41. The display apparatus of claim 40, wherein heat generated by at least one of the panel control board, the signal board, the power supply board, or the LED driver board is discharged from the back chassis. 42. A display apparatus comprising:
a display panel for displaying an image; a heat source arranged at a side surface of at least one side of the display panel; a heat absorbing section for absorbing heat generated by the heat source, the heat source in close contact with the heat absorbing section on a side of the heat absorbing section; a back surface plate comprising a metal arranged at a back surface side of the display panel, the back surface plate having a portion in close contact with the heat absorbing section; a front surface plate arranged at a front surface side of the display panel; a middle chassis, arranged between the front surface plate and the heat absorbing section, for conducting the heat absorbed by the heat absorbing section to the front surface plate; and a chassis arranged at a back surface side of the back surface plate, and having thereon a panel control board for driving the display panel, wherein the chassis has a connecting unit for fixing and installing the display panel, and a width of the side of the heat absorbing section to which the heat source is in close contact is smaller than a width of another side of the heat absorbing section to which the back surface plate is in close contact. 43. The display apparatus according to claim 42, wherein the middle chassis is made of a material having a thermal conductivity lower than a thermal conductivity of the heat absorbing section. 44. The display apparatus according to claim 43, wherein the front surface plate comprises a second metal. | 2,800 |
12,196 | 12,196 | 16,398,277 | 2,892 | In various embodiments a semiconductor device is provided, including a semiconductor body including a drift region and a gate electrode arranged adjacent to the drift region; and a contact structure provided over the drift region of the semiconductor body and having a first metal layer, an adhesion layer over the first metal layer and a second metal layer over the adhesion layer. | 1. A semiconductor device, comprising:
a semiconductor body having a front side and a back side opposite to the front side, the semiconductor body comprising a semiconductor layer, a first drift region and a first gate electrode arranged laterally adjacent to the first drift region, wherein the first gate electrode vertically extends from the front side of the semiconductor body towards the back side of the semiconductor body, and a first contact structure provided over the semiconductor body and at least partially horizontally overlapping the first drift region of the semiconductor body, the first contact structure including a first metal layer contacting the semiconductor body at the front side, an adhesion layer disposed over the first metal layer, and a second metal layer disposed over the adhesion layer, wherein the first metal layer of the first contact structure and the first gate electrode do not horizontally overlap. 2. The semiconductor device of claim 1, further comprising:
a second contact structure provided over the semiconductor body and laterally adjacent to the first gate electrode, the second contact structure including a first metal layer contacting the semiconductor body at the front side, an adhesion layer disposed over the first metal layer, and a second metal layer disposed over the adhesion layer, wherein the first metal layer of the second contact structure and the first gate electrode do not horizontally overlap. 3. The semiconductor device of claim 2, further comprising:
a second drift region of the semiconductor body, wherein the first gate electrode is arranged laterally adjacent to the second drift region; and wherein the second contact structure at least partially horizontally overlaps the second drift region of the semiconductor body. 4. The semiconductor device of claim 2, further comprising:
a gate portion disposed at the front side of the semiconductor body, wherein the gate portion is electrically coupled to the first gate electrode and is at least partially disposed between the first and second contact structures. 5. The semiconductor device of claim 2, further comprising:
a third contact structure provided over the semiconductor body, the third contact structure including a first metal layer contacting the semiconductor body at the front side, an adhesion layer disposed over the first metal layer, and a second metal layer disposed over the adhesion layer, wherein the first metal layer of the third contact structure is physically and electrically coupled to gate portion. 6. The semiconductor device of claim 5, wherein top surfaces of the first metal layers of the first, second, and third contact structures are coplanar. 7. The semiconductor device of claim 2, wherein the first metal layers of the first and second contact structures include aluminum. 8. The semiconductor device of claim 2, wherein the adhesion layers of the first and second contact structures include titanium, tantalum, or titanium tungsten. 9. The semiconductor device of claim 2, wherein the second metal layers of the first and second contact structures include copper. 10. The semiconductor device of claim 4, further comprising: dielectric material provided between the first and second contact structures that covers the gate portion. 11. The semiconductor device of claim 10, further comprising: passivation material provided over the dielectric material between the first and second contact structures. 12. The semiconductor device of claim 11, wherein the passivation material is further provided over the first and second contact structures so as to encapsulate the contact structures. 13. The semiconductor device of claim 12, further comprising: an opening provided in the passivation material over the upper surface of each of the first contact structure exposing an upper surface of the first contact structure. 14. The semiconductor device of claim 4, further comprising: a further gate portion provided over the semiconductor body that is electrically coupled to the gate portion, the further gate portion being covered by dielectric material. 15. The semiconductor device of claim 2, wherein the second contact structure is laterally and physically separate from the first contact structure. 16. The semiconductor device of claim 2, wherein upper surfaces of the second metal layer of the first contact structure and of the second metal layer of the second contact structure are level. 17. The semiconductor device of claim 4, wherein upper surfaces of the first metal layer of the first contact structure and of the gate portion are level. 18. The semiconductor device of claim 1, further comprising:
a back side metal layer provided at the back side of the semiconductor body. 19. The semiconductor device of claim 2, wherein a thickness of the second metal layer of the first and second contact structures is the range from 5 μm to 10 μm. 20. The semiconductor device of claim 1, wherein a thickness of the semiconductor device is in the range from 60 μm to 100 μm. | In various embodiments a semiconductor device is provided, including a semiconductor body including a drift region and a gate electrode arranged adjacent to the drift region; and a contact structure provided over the drift region of the semiconductor body and having a first metal layer, an adhesion layer over the first metal layer and a second metal layer over the adhesion layer.1. A semiconductor device, comprising:
a semiconductor body having a front side and a back side opposite to the front side, the semiconductor body comprising a semiconductor layer, a first drift region and a first gate electrode arranged laterally adjacent to the first drift region, wherein the first gate electrode vertically extends from the front side of the semiconductor body towards the back side of the semiconductor body, and a first contact structure provided over the semiconductor body and at least partially horizontally overlapping the first drift region of the semiconductor body, the first contact structure including a first metal layer contacting the semiconductor body at the front side, an adhesion layer disposed over the first metal layer, and a second metal layer disposed over the adhesion layer, wherein the first metal layer of the first contact structure and the first gate electrode do not horizontally overlap. 2. The semiconductor device of claim 1, further comprising:
a second contact structure provided over the semiconductor body and laterally adjacent to the first gate electrode, the second contact structure including a first metal layer contacting the semiconductor body at the front side, an adhesion layer disposed over the first metal layer, and a second metal layer disposed over the adhesion layer, wherein the first metal layer of the second contact structure and the first gate electrode do not horizontally overlap. 3. The semiconductor device of claim 2, further comprising:
a second drift region of the semiconductor body, wherein the first gate electrode is arranged laterally adjacent to the second drift region; and wherein the second contact structure at least partially horizontally overlaps the second drift region of the semiconductor body. 4. The semiconductor device of claim 2, further comprising:
a gate portion disposed at the front side of the semiconductor body, wherein the gate portion is electrically coupled to the first gate electrode and is at least partially disposed between the first and second contact structures. 5. The semiconductor device of claim 2, further comprising:
a third contact structure provided over the semiconductor body, the third contact structure including a first metal layer contacting the semiconductor body at the front side, an adhesion layer disposed over the first metal layer, and a second metal layer disposed over the adhesion layer, wherein the first metal layer of the third contact structure is physically and electrically coupled to gate portion. 6. The semiconductor device of claim 5, wherein top surfaces of the first metal layers of the first, second, and third contact structures are coplanar. 7. The semiconductor device of claim 2, wherein the first metal layers of the first and second contact structures include aluminum. 8. The semiconductor device of claim 2, wherein the adhesion layers of the first and second contact structures include titanium, tantalum, or titanium tungsten. 9. The semiconductor device of claim 2, wherein the second metal layers of the first and second contact structures include copper. 10. The semiconductor device of claim 4, further comprising: dielectric material provided between the first and second contact structures that covers the gate portion. 11. The semiconductor device of claim 10, further comprising: passivation material provided over the dielectric material between the first and second contact structures. 12. The semiconductor device of claim 11, wherein the passivation material is further provided over the first and second contact structures so as to encapsulate the contact structures. 13. The semiconductor device of claim 12, further comprising: an opening provided in the passivation material over the upper surface of each of the first contact structure exposing an upper surface of the first contact structure. 14. The semiconductor device of claim 4, further comprising: a further gate portion provided over the semiconductor body that is electrically coupled to the gate portion, the further gate portion being covered by dielectric material. 15. The semiconductor device of claim 2, wherein the second contact structure is laterally and physically separate from the first contact structure. 16. The semiconductor device of claim 2, wherein upper surfaces of the second metal layer of the first contact structure and of the second metal layer of the second contact structure are level. 17. The semiconductor device of claim 4, wherein upper surfaces of the first metal layer of the first contact structure and of the gate portion are level. 18. The semiconductor device of claim 1, further comprising:
a back side metal layer provided at the back side of the semiconductor body. 19. The semiconductor device of claim 2, wherein a thickness of the second metal layer of the first and second contact structures is the range from 5 μm to 10 μm. 20. The semiconductor device of claim 1, wherein a thickness of the semiconductor device is in the range from 60 μm to 100 μm. | 2,800 |
12,197 | 12,197 | 16,216,169 | 2,892 | A mechanism for preparing a wafer and/or substrate is disclosed. A plurality of mandrel lines are etched via a mandrel mask. The mandrel lines are separated by spaces. Spin-on glass (SOG) is deposited to backfill the spaces between the mandrel lines. A non-mandrel mask is employed to etch spaces from the SOG in between the mandrel lines to create non-mandrel lines. The mandrel lines and the non-mandrel lines can then be replaced with a conductive material. | 1. A wafer prepared by a process comprising:
etching a plurality of mandrel lines via a mandrel mask, the mandrel lines separated by spaces; depositing spin-on glass (SOG) to backfill the spaces between the mandrel lines; etching, via a non-mandrel mask, the SOG from the spaces between the mandrel lines to create non-mandrel lines; and replacing the mandrel lines and the non-mandrel lines with a conductive material. 2. The wafer of claim 1, wherein the process further comprises depositing spacers around the mandrel lines prior to depositing the SOG, and wherein the spacers guide the deposition of the SOG to support etching the non-mandrel lines. 3. The wafer of claim 1, wherein the non-mandrel lines and the mandrel lines extend across the wafer along a first axis, and wherein lengths and positions of the non-mandrel lines along the first axis is independent of lengths and positions of mandrel lines along the first axis. 4. The wafer of claim 1, wherein etching the SOG via the non-mandrel mask creates non-mandrel lines that omit dummy traces. 5. The wafer of claim 1, wherein the process further comprises performing an etch-back on the SOG, prior to etching the SOG, to expose at least some of the mandrel lines. 6. The wafer of claim 1, wherein gaps are created in the mandrel lines by the non-mandrel mask. 7. The wafer of claim 1, wherein gaps are created in the mandrel lines by the mandrel mask prior to creating the non-mandrel lines. 8. The wafer of claim 1, wherein the mandrel lines and the non-mandrel lines include a width along a second axis of eighty nanometers or less. 9. A method comprising:
etching a plurality of mandrel lines via a mandrel mask, the mandrel lines separated by a space; depositing spin-on glass (SOG) to backfill the spaces between the mandrel lines; etching, via a non-mandrel mask, the SOG from the spaces between the mandrel lines to create non-mandrel lines; and replacing the mandrel lines and the non-mandrel lines with a conductive material. 10. The method of claim 9, further comprising depositing spacers around the mandrel lines prior to depositing the SOG, wherein the spacers guide the deposition of the SOG to support etching the non-mandrel lines. 11. The method of claim 9, wherein the non-mandrel lines and the mandrel lines extend across a wafer along a first axis, and wherein a length and position of the non-mandrel lines along the first axis is independent of a length and position of mandrel lines along the first axis. 12. The method of claim 9, wherein etching the SOG via the non-mandrel mask creates non-mandrel lines that omit dummy traces. 13. The method of claim 9, further comprising performing an etch-back on the SOG, prior to etching the SOG, to expose at least some of the mandrel lines. 14. The method of claim 9, wherein gaps are created in the mandrel lines by the non-mandrel mask. 15. The method of claim 9, wherein gaps are created in the mandrel lines by the mandrel mask prior to creating the non-mandrel lines. 16. The method of claim 9, wherein the mandrel lines and the non-mandrel lines include a width along a second axis of eighty nanometers or less. 17. A wafer comprising:
a substrate; a plurality of mandrel line channels of conductive material extending across the substrate along a first axis, the mandrel line channels separated by spaces along a second axis perpendicular to the first axis; and a plurality of non-mandrel line channels of conductive material extending across the substrate along the first axis, wherein lengths and positions of the non-mandrel line channels along the first axis is independent of lengths and positions of mandrel lines along the first axis. 18. The wafer of claim 17, wherein the mandrel line channels omit dummy traces uncoupled to operational components. 19. The wafer of claim 17, wherein the non-mandrel line channels omit dummy traces uncoupled to operational components. 20. The wafer of claim 17, wherein the mandrel line channels and the non-mandrel line channels include a width along the second axis of eighty nanometers or less. | A mechanism for preparing a wafer and/or substrate is disclosed. A plurality of mandrel lines are etched via a mandrel mask. The mandrel lines are separated by spaces. Spin-on glass (SOG) is deposited to backfill the spaces between the mandrel lines. A non-mandrel mask is employed to etch spaces from the SOG in between the mandrel lines to create non-mandrel lines. The mandrel lines and the non-mandrel lines can then be replaced with a conductive material.1. A wafer prepared by a process comprising:
etching a plurality of mandrel lines via a mandrel mask, the mandrel lines separated by spaces; depositing spin-on glass (SOG) to backfill the spaces between the mandrel lines; etching, via a non-mandrel mask, the SOG from the spaces between the mandrel lines to create non-mandrel lines; and replacing the mandrel lines and the non-mandrel lines with a conductive material. 2. The wafer of claim 1, wherein the process further comprises depositing spacers around the mandrel lines prior to depositing the SOG, and wherein the spacers guide the deposition of the SOG to support etching the non-mandrel lines. 3. The wafer of claim 1, wherein the non-mandrel lines and the mandrel lines extend across the wafer along a first axis, and wherein lengths and positions of the non-mandrel lines along the first axis is independent of lengths and positions of mandrel lines along the first axis. 4. The wafer of claim 1, wherein etching the SOG via the non-mandrel mask creates non-mandrel lines that omit dummy traces. 5. The wafer of claim 1, wherein the process further comprises performing an etch-back on the SOG, prior to etching the SOG, to expose at least some of the mandrel lines. 6. The wafer of claim 1, wherein gaps are created in the mandrel lines by the non-mandrel mask. 7. The wafer of claim 1, wherein gaps are created in the mandrel lines by the mandrel mask prior to creating the non-mandrel lines. 8. The wafer of claim 1, wherein the mandrel lines and the non-mandrel lines include a width along a second axis of eighty nanometers or less. 9. A method comprising:
etching a plurality of mandrel lines via a mandrel mask, the mandrel lines separated by a space; depositing spin-on glass (SOG) to backfill the spaces between the mandrel lines; etching, via a non-mandrel mask, the SOG from the spaces between the mandrel lines to create non-mandrel lines; and replacing the mandrel lines and the non-mandrel lines with a conductive material. 10. The method of claim 9, further comprising depositing spacers around the mandrel lines prior to depositing the SOG, wherein the spacers guide the deposition of the SOG to support etching the non-mandrel lines. 11. The method of claim 9, wherein the non-mandrel lines and the mandrel lines extend across a wafer along a first axis, and wherein a length and position of the non-mandrel lines along the first axis is independent of a length and position of mandrel lines along the first axis. 12. The method of claim 9, wherein etching the SOG via the non-mandrel mask creates non-mandrel lines that omit dummy traces. 13. The method of claim 9, further comprising performing an etch-back on the SOG, prior to etching the SOG, to expose at least some of the mandrel lines. 14. The method of claim 9, wherein gaps are created in the mandrel lines by the non-mandrel mask. 15. The method of claim 9, wherein gaps are created in the mandrel lines by the mandrel mask prior to creating the non-mandrel lines. 16. The method of claim 9, wherein the mandrel lines and the non-mandrel lines include a width along a second axis of eighty nanometers or less. 17. A wafer comprising:
a substrate; a plurality of mandrel line channels of conductive material extending across the substrate along a first axis, the mandrel line channels separated by spaces along a second axis perpendicular to the first axis; and a plurality of non-mandrel line channels of conductive material extending across the substrate along the first axis, wherein lengths and positions of the non-mandrel line channels along the first axis is independent of lengths and positions of mandrel lines along the first axis. 18. The wafer of claim 17, wherein the mandrel line channels omit dummy traces uncoupled to operational components. 19. The wafer of claim 17, wherein the non-mandrel line channels omit dummy traces uncoupled to operational components. 20. The wafer of claim 17, wherein the mandrel line channels and the non-mandrel line channels include a width along the second axis of eighty nanometers or less. | 2,800 |
12,198 | 12,198 | 16,056,827 | 2,894 | Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process. | 1. An integrated circuit, comprising:
at least one circuit element comprising a layer of a ferroelectric material, and disposed near a semiconducting surface of a body; at least one layer of insulating material disposed over the surface and overlying the at least one circuit element; at least one level of conductors disposed near the surface; a protective overcoat layer, comprising an insulating material, disposed over the ferroelectric circuit element, the at least one layer of insulating material, and the at least one level of conductors; and a passivation layer overlying the protective overcoat layer, the passivation layer having a tensile stress state, and formed by a process comprising:
heating the passivation layer to a temperature below a Curie temperature of the ferroelectric material for a duration sufficient to cure the material of the passivation layer into a tensile stress state, and of less than about twenty minutes. 2. The integrated circuit of claim 1, further comprising:
a plurality of solder halls near the surface, in contact with conductors through openings in the passivation layer. 3. The integrated circuit of claim 1, wherein the passivation layer comprises a polymer-containing soft stress release material having a low elastic modulus as compared with SiO2. 4. The integrated circuit of claim 3, wherein the polymer-containing soft stress release material is selected from the group consisting of polynnides, polybenzoxazole (PBO), benzocyclobutene-based polymers (BCB), and fluoro-polymers. 5. The integrated circuit of claim 1, wherein the at least one circuit element comprises a plurality of ferroelectric capacitors, each comprising first and second parallel conductive plates disposed on either side of the ferroelectric material. 6. The integrated circuit of claim 5, wherein the at least one circuit elements further comprise a plurality of metal-oxide-semiconductor (MOS) transistors, each associated with one of the ferroelectric capacitors in a plurality of memory cells;
and wherein each of the plurality of ferroelectric capacitors comprises first and second parallel conductive plates disposed on either side of the ferroelectric material, the first plate coupled to a plate line conductor in the integrated circuit and the second plate coupled to a source/drain region of its associated MOS transistor. 7. A method of manufacturing an integrated circuit, comprising:
forming at least one circuit element comprising a layer of a ferroelectric material near a semiconducting surface of a body; then forming at least one level of conductors overlying the element, each level comprising patterned metal conductors and a dielectric layer; forming a protective overcoat layer over the surface and overlying the at least one circuit element and the at least one level of conductors; then depositing a passivation layer of a material comprising a polymer-containing film over the protective overcoat layer; and applying electromagnetic energy to the passivation layer at a frequency corresponding to a vibrational frequency of the polymer, to heat the passivation layer to a temperature below a Curie temperature of the ferroelectric material for a duration sufficient to cure the material of the passivation layer into a tensile stress state. 8. The method of claim 7, wherein the step of applying electromagnetic energy heats the passivation layer is performed for a duration of less than about twenty minutes. | Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.1. An integrated circuit, comprising:
at least one circuit element comprising a layer of a ferroelectric material, and disposed near a semiconducting surface of a body; at least one layer of insulating material disposed over the surface and overlying the at least one circuit element; at least one level of conductors disposed near the surface; a protective overcoat layer, comprising an insulating material, disposed over the ferroelectric circuit element, the at least one layer of insulating material, and the at least one level of conductors; and a passivation layer overlying the protective overcoat layer, the passivation layer having a tensile stress state, and formed by a process comprising:
heating the passivation layer to a temperature below a Curie temperature of the ferroelectric material for a duration sufficient to cure the material of the passivation layer into a tensile stress state, and of less than about twenty minutes. 2. The integrated circuit of claim 1, further comprising:
a plurality of solder halls near the surface, in contact with conductors through openings in the passivation layer. 3. The integrated circuit of claim 1, wherein the passivation layer comprises a polymer-containing soft stress release material having a low elastic modulus as compared with SiO2. 4. The integrated circuit of claim 3, wherein the polymer-containing soft stress release material is selected from the group consisting of polynnides, polybenzoxazole (PBO), benzocyclobutene-based polymers (BCB), and fluoro-polymers. 5. The integrated circuit of claim 1, wherein the at least one circuit element comprises a plurality of ferroelectric capacitors, each comprising first and second parallel conductive plates disposed on either side of the ferroelectric material. 6. The integrated circuit of claim 5, wherein the at least one circuit elements further comprise a plurality of metal-oxide-semiconductor (MOS) transistors, each associated with one of the ferroelectric capacitors in a plurality of memory cells;
and wherein each of the plurality of ferroelectric capacitors comprises first and second parallel conductive plates disposed on either side of the ferroelectric material, the first plate coupled to a plate line conductor in the integrated circuit and the second plate coupled to a source/drain region of its associated MOS transistor. 7. A method of manufacturing an integrated circuit, comprising:
forming at least one circuit element comprising a layer of a ferroelectric material near a semiconducting surface of a body; then forming at least one level of conductors overlying the element, each level comprising patterned metal conductors and a dielectric layer; forming a protective overcoat layer over the surface and overlying the at least one circuit element and the at least one level of conductors; then depositing a passivation layer of a material comprising a polymer-containing film over the protective overcoat layer; and applying electromagnetic energy to the passivation layer at a frequency corresponding to a vibrational frequency of the polymer, to heat the passivation layer to a temperature below a Curie temperature of the ferroelectric material for a duration sufficient to cure the material of the passivation layer into a tensile stress state. 8. The method of claim 7, wherein the step of applying electromagnetic energy heats the passivation layer is performed for a duration of less than about twenty minutes. | 2,800 |
12,199 | 12,199 | 15,648,298 | 2,827 | A SRAM system having an address scheme and/or wire control layout. By preferentially accessing a defined address range mapped to SRAM array blocks located near a controller, significant power savings can be realized. In one embodiment, the address scheme determines a range physically closer to a central control location. In another embodiment, the wire control layout reduces number and length of active wires, further reducing power consumption. | 1. A SRAM circuit comprising:
arrays of SRAM bit cells, each capable of storing a bit of information, that together define an address bitmap, each array of the arrays of SRAM bit cells including a sense amplifier and a write driver; peripheral circuitry able to generate selected control, data, and address signals, connected to the arrays of SRAM bit cells and positioned at a designated location, the peripheral circuitry including at least one array decoder for each array of the arrays of SRAM bit cells located at the designated location and signal lines coupling the at least one array decoder to the sense amplifier and the write driver of the each array, the sense amplifier and the write driver of each array of the arrays of SRAM bit cells not being at the designated location and being adjacent the arrays of SRAM bit cells; and wherein a subset of arrays in the arrays of SRAM bit cells are mapped to a subset of the address bitmap, and are placed adjacent to the designated location. 2. The SRAM circuit of claim 1, wherein the designated location is lanes defined between innermost arrays of the arrays of SRAM bit cells. 3. The SRAM circuit of claim 1, wherein the designated location is at the center of the arrays of SRAM bit cells. 4. The SRAM circuit of claim 1, wherein the subset of the address bitmap defines a contiguous address range. 5. The SRAM circuit of claim 4, wherein the contiguous address range starts at address 0. 6. The SRAM circuit of claim 1, further comprising a connection to a software system arranged to direct commonly used data in and/or out of the arrays of SRAM bit cells in the subset of arrays placed adjacent to the designated location. 7. The SRAM circuit of claim 1, wherein the arrays of SRAM bit cells are in a power domain distinct from the peripheral circuitry. 8. The SRAM circuit of claim 1, wherein the peripheral circuitry includes both address path facilities and data path facilities, each in a distinct power domain. 9. The SRAM circuit of claim 1, wherein the peripheral circuitry includes both address path facilities and data path facilities, and wherein the designated location is surrounded by the arrays of SRAM bit cells and both the address path facility and the data path facility. 10. The SRAM circuit of claim 1, wherein the peripheral circuitry has a plurality of connected lines to each respective member of the arrays of SRAM bit cells, configured to allow access to a subset of arrays during an operation, wherein the lines not connected to the subset of arrays are not activated during the operation. 11. An array control circuit connected to a plurality of array blocks comprising:
peripheral circuitry connected by signal lines to the plurality of array blocks to access a subset of array blocks during an operation, the peripheral circuitry being positioned at a designated location, with an array decoder for each block of the array of blocks being located at the designated location and sense amplifiers and write drivers for each block of the array of bocks not being locate at the designated location; and wherein only those signal lines connecting the peripheral circuitry to the accessed subset of array blocks are active during the operation. 12. The array control circuit of claim 11, wherein signal lines connecting the peripheral circuitry to array blocks that are not accessed do not switch during the operation. 13. The array control circuit of claim 11, wherein the operation can be at least one of a write, a read, a standby, and retention operation of a SRAM system. 14. The array control circuit of claim 11, wherein each block in the connected plurality of array blocks has an address, and wherein the addresses of blocks located near the designated location are contiguous. 15. The array control circuit of claim 14, wherein addresses of the blocks located near the designated location start at address 0. 16. The array control circuit of claim 11, wherein at least some of the connected plurality of array blocks are SRAM bit cell array blocks. 17. The array control circuit of claim 11, wherein the designated location is surrounded by the subset of array blocks. 18. The SRAM circuit of claim 11, wherein the designated location is at a center of the subset of array blocks. 19. The SRAM circuit of claim 11, wherein at least some of the plurality of array blocks are SRAM bit cell array blocks in a power domain distinct from the peripheral circuitry. 20. A system with multiple arrays that can be selectively accessed, comprising:
first circuitry positioned adjacent to at least some of the multiple arrays, the multiple arrays accessible and controllable with one or more control signals, and with only circuitry connected to accessed arrays being enabled, wherein the first circuitry is sense amplifiers and write drivers; and second circuitry generating at least some of the one or more control signals to enable the first circuitry, the second circuitry being at a designated location at a center of the multiple arrays and including array decoders for the multiple arrays, the first circuitry not being at the designated location. 21-25. (canceled) 26. The system of claim 20, wherein the multiple arrays and the second circuitry are in different power domains. 27. The system of claim 26, wherein transistors of the multiple arrays have a higher threshold than transistors of the second circuitry. 28. The system of claim 20, wherein the designated location is lanes between the multiple arrays. 29. The array control circuit of claim 11, wherein the plurality of array blocks includes at least 16 array blocks. | A SRAM system having an address scheme and/or wire control layout. By preferentially accessing a defined address range mapped to SRAM array blocks located near a controller, significant power savings can be realized. In one embodiment, the address scheme determines a range physically closer to a central control location. In another embodiment, the wire control layout reduces number and length of active wires, further reducing power consumption.1. A SRAM circuit comprising:
arrays of SRAM bit cells, each capable of storing a bit of information, that together define an address bitmap, each array of the arrays of SRAM bit cells including a sense amplifier and a write driver; peripheral circuitry able to generate selected control, data, and address signals, connected to the arrays of SRAM bit cells and positioned at a designated location, the peripheral circuitry including at least one array decoder for each array of the arrays of SRAM bit cells located at the designated location and signal lines coupling the at least one array decoder to the sense amplifier and the write driver of the each array, the sense amplifier and the write driver of each array of the arrays of SRAM bit cells not being at the designated location and being adjacent the arrays of SRAM bit cells; and wherein a subset of arrays in the arrays of SRAM bit cells are mapped to a subset of the address bitmap, and are placed adjacent to the designated location. 2. The SRAM circuit of claim 1, wherein the designated location is lanes defined between innermost arrays of the arrays of SRAM bit cells. 3. The SRAM circuit of claim 1, wherein the designated location is at the center of the arrays of SRAM bit cells. 4. The SRAM circuit of claim 1, wherein the subset of the address bitmap defines a contiguous address range. 5. The SRAM circuit of claim 4, wherein the contiguous address range starts at address 0. 6. The SRAM circuit of claim 1, further comprising a connection to a software system arranged to direct commonly used data in and/or out of the arrays of SRAM bit cells in the subset of arrays placed adjacent to the designated location. 7. The SRAM circuit of claim 1, wherein the arrays of SRAM bit cells are in a power domain distinct from the peripheral circuitry. 8. The SRAM circuit of claim 1, wherein the peripheral circuitry includes both address path facilities and data path facilities, each in a distinct power domain. 9. The SRAM circuit of claim 1, wherein the peripheral circuitry includes both address path facilities and data path facilities, and wherein the designated location is surrounded by the arrays of SRAM bit cells and both the address path facility and the data path facility. 10. The SRAM circuit of claim 1, wherein the peripheral circuitry has a plurality of connected lines to each respective member of the arrays of SRAM bit cells, configured to allow access to a subset of arrays during an operation, wherein the lines not connected to the subset of arrays are not activated during the operation. 11. An array control circuit connected to a plurality of array blocks comprising:
peripheral circuitry connected by signal lines to the plurality of array blocks to access a subset of array blocks during an operation, the peripheral circuitry being positioned at a designated location, with an array decoder for each block of the array of blocks being located at the designated location and sense amplifiers and write drivers for each block of the array of bocks not being locate at the designated location; and wherein only those signal lines connecting the peripheral circuitry to the accessed subset of array blocks are active during the operation. 12. The array control circuit of claim 11, wherein signal lines connecting the peripheral circuitry to array blocks that are not accessed do not switch during the operation. 13. The array control circuit of claim 11, wherein the operation can be at least one of a write, a read, a standby, and retention operation of a SRAM system. 14. The array control circuit of claim 11, wherein each block in the connected plurality of array blocks has an address, and wherein the addresses of blocks located near the designated location are contiguous. 15. The array control circuit of claim 14, wherein addresses of the blocks located near the designated location start at address 0. 16. The array control circuit of claim 11, wherein at least some of the connected plurality of array blocks are SRAM bit cell array blocks. 17. The array control circuit of claim 11, wherein the designated location is surrounded by the subset of array blocks. 18. The SRAM circuit of claim 11, wherein the designated location is at a center of the subset of array blocks. 19. The SRAM circuit of claim 11, wherein at least some of the plurality of array blocks are SRAM bit cell array blocks in a power domain distinct from the peripheral circuitry. 20. A system with multiple arrays that can be selectively accessed, comprising:
first circuitry positioned adjacent to at least some of the multiple arrays, the multiple arrays accessible and controllable with one or more control signals, and with only circuitry connected to accessed arrays being enabled, wherein the first circuitry is sense amplifiers and write drivers; and second circuitry generating at least some of the one or more control signals to enable the first circuitry, the second circuitry being at a designated location at a center of the multiple arrays and including array decoders for the multiple arrays, the first circuitry not being at the designated location. 21-25. (canceled) 26. The system of claim 20, wherein the multiple arrays and the second circuitry are in different power domains. 27. The system of claim 26, wherein transistors of the multiple arrays have a higher threshold than transistors of the second circuitry. 28. The system of claim 20, wherein the designated location is lanes between the multiple arrays. 29. The array control circuit of claim 11, wherein the plurality of array blocks includes at least 16 array blocks. | 2,800 |
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