system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8hadamardPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ ISETP.GE.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8hadamardPfS_S_ii
.globl _Z8hadamardPfS_S_ii
.p2align 8
.type _Z8hadamardPfS_S_ii,@function
_Z8hadamardPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8hadamardPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8hadamardPfS_S_ii, .Lfunc_end0-_Z8hadamardPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8hadamardPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8hadamardPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001525a2_00000000-6_hadamard_product.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.2f "
.LC1:
.string "\n"
.text
.globl _Z12print_matrixPfii
.type _Z12print_matrixPfii, @function
_Z12print_matrixPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L3
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r12
jmp .L5
.L7:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L3
.L5:
testl %r15d, %r15d
jg .L7
jmp .L8
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12print_matrixPfii, .-_Z12print_matrixPfii
.globl _Z33__device_stub__Z8hadamardPfS_S_iiPfS_S_ii
.type _Z33__device_stub__Z8hadamardPfS_S_iiPfS_S_ii, @function
_Z33__device_stub__Z8hadamardPfS_S_iiPfS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8hadamardPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z8hadamardPfS_S_iiPfS_S_ii, .-_Z33__device_stub__Z8hadamardPfS_S_iiPfS_S_ii
.globl _Z8hadamardPfS_S_ii
.type _Z8hadamardPfS_S_ii, @function
_Z8hadamardPfS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z8hadamardPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8hadamardPfS_S_ii, .-_Z8hadamardPfS_S_ii
.section .rodata.str1.1
.LC2:
.string "%d"
.LC3:
.string "%d %d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Failed to allocate host vectors!\n"
.section .rodata.str1.1
.LC5:
.string "%f"
.section .rodata.str1.8
.align 8
.LC6:
.string "Failed to launch vectorAdd kernel (error code %s)!\n"
.align 8
.LC9:
.string "Result verification failed at element %d!\n"
.align 8
.LC10:
.string "Failed to deinitialize the device! error=%s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rsi
leaq .LC2(%rip), %rdi
call __isoc23_scanf@PLT
movl 28(%rsp), %eax
leal -1(%rax), %edx
movl %edx, 28(%rsp)
testl %eax, %eax
jne .L32
.L20:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L42
movl $2, %ecx
movq (%rsp), %rdx
movq 56(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %edx
imull 32(%rsp), %edx
testl %edx, %edx
jle .L27
movslq %edx, %rdx
movl $0, %eax
.L30:
movss (%r14,%rax,4), %xmm0
mulss (%r15,%rax,4), %xmm0
subss 0(%r13,%rax,4), %xmm0
andps .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC8(%rip), %xmm0
ja .L43
addq $1, %rax
cmpq %rdx, %rax
jne .L30
.L27:
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L44
movl 36(%rsp), %edx
movl 32(%rsp), %esi
movq %r13, %rdi
call _Z12print_matrixPfii
movl 28(%rsp), %eax
leal -1(%rax), %edx
movl %edx, 28(%rsp)
testl %eax, %eax
je .L20
.L32:
leaq 36(%rsp), %rdx
leaq 32(%rsp), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 32(%rsp), %eax
imull 36(%rsp), %eax
movl %eax, 12(%rsp)
cltq
leaq 0(,%rax,4), %rbx
movq %rbx, (%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
testq %r14, %r14
sete %al
testq %r15, %r15
sete %dl
orb %dl, %al
jne .L21
testq %r13, %r13
je .L21
movq %r14, %r12
movq %r15, %rbp
movl $0, %ebx
cmpl $0, 12(%rsp)
jle .L23
.L24:
movq %r12, %rsi
leaq .LC5(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %rbp, %rsi
leaq .LC5(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %r12
addq $4, %rbp
movl 36(%rsp), %eax
imull 32(%rsp), %eax
cmpl %ebx, %eax
jg .L24
.L23:
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
leaq 40(%rsp), %rdi
movq (%rsp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %eax
imull 36(%rsp), %eax
leal 510(%rax), %edx
addl $255, %eax
cmovs %edx, %eax
sarl $8, %eax
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L25
movl 36(%rsp), %r8d
movl 32(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z33__device_stub__Z8hadamardPfS_S_iiPfS_S_ii
jmp .L25
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movl %eax, %ecx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z8hadamardPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z8hadamardPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC7:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hadamard_product.hip"
.globl _Z23__device_stub__hadamardPfS_S_ii # -- Begin function _Z23__device_stub__hadamardPfS_S_ii
.p2align 4, 0x90
.type _Z23__device_stub__hadamardPfS_S_ii,@function
_Z23__device_stub__hadamardPfS_S_ii: # @_Z23__device_stub__hadamardPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8hadamardPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__hadamardPfS_S_ii, .Lfunc_end0-_Z23__device_stub__hadamardPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z12print_matrixPfii # -- Begin function _Z12print_matrixPfii
.p2align 4, 0x90
.type _Z12print_matrixPfii,@function
_Z12print_matrixPfii: # @_Z12print_matrixPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ebx, %ebx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12print_matrixPfii, .Lfunc_end1-_Z12print_matrixPfii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 20(%rsp), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
subl $1, 20(%rsp)
jae .LBB2_1
.LBB2_26: # %._crit_edge69
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1: # %.lr.ph68
.cfi_def_cfa_offset 240
movabsq $4294967296, %rax # imm = 0x100000000
addq $256, %rax # imm = 0x100
movq %rax, 64(%rsp) # 8-byte Spill
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_25: # %_Z12print_matrixPfii.exit
# in Loop: Header=BB2_2 Depth=1
subl $1, 20(%rsp)
jb .LBB2_26
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_7 Depth 2
# Child Loop BB2_15 Depth 2
# Child Loop BB2_21 Depth 2
# Child Loop BB2_23 Depth 3
movl $.L.str.3, %edi
leaq 16(%rsp), %rsi
leaq 12(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_scanf
movslq 16(%rsp), %rax
movslq 12(%rsp), %r12
imulq %rax, %r12
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %rbp
movq %r12, %rdi
callq malloc
movq %r14, 24(%rsp) # 8-byte Spill
testq %r14, %r14
je .LBB2_28
# %bb.3: # in Loop: Header=BB2_2 Depth=1
testq %rbp, %rbp
je .LBB2_28
# %bb.4: # in Loop: Header=BB2_2 Depth=1
movq %rax, %rbx
testq %rax, %rax
je .LBB2_28
# %bb.5: # %.preheader
# in Loop: Header=BB2_2 Depth=1
movl 16(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .LBB2_8
# %bb.6: # %.lr.ph.preheader
# in Loop: Header=BB2_2 Depth=1
movq 24(%rsp), %r14 # 8-byte Reload
movq %rbp, %r15
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_7: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.5, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.5, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r13
movslq 12(%rsp), %rax
movslq 16(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r15
addq $4, %r14
cmpq %rcx, %r13
jl .LBB2_7
.LBB2_8: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq $0, 48(%rsp)
movq $0, 40(%rsp)
movq $0, 32(%rsp)
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 24(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %rbp, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edi
imull 16(%rsp), %edi
leal 255(%rdi), %eax
addl $510, %edi # imm = 0x1FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $8, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq 64(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9: # in Loop: Header=BB2_2 Depth=1
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movl 16(%rsp), %esi
movl 12(%rsp), %edi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %esi, 60(%rsp)
movl %edi, 56(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 60(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z8hadamardPfS_S_ii, %edi
leaq 144(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10: # in Loop: Header=BB2_2 Depth=1
callq hipGetLastError
testl %eax, %eax
jne .LBB2_11
# %bb.13: # in Loop: Header=BB2_2 Depth=1
movq 32(%rsp), %rsi
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl 16(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
movaps .LCPI2_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movsd .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero
jle .LBB2_17
# %bb.14: # %.lr.ph64.preheader
# in Loop: Header=BB2_2 Depth=1
movl %eax, %eax
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_15: # %.lr.ph64
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%rbp,%rdx,4), %xmm0
subss (%rbx,%rdx,4), %xmm0
andps %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm2, %xmm0
ja .LBB2_27
# %bb.16: # in Loop: Header=BB2_15 Depth=2
incq %rdx
cmpq %rdx, %rax
jne .LBB2_15
.LBB2_17: # %._crit_edge65
# in Loop: Header=BB2_2 Depth=1
movq %rbx, 24(%rsp) # 8-byte Spill
callq hipDeviceReset
testl %eax, %eax
jne .LBB2_18
# %bb.19: # in Loop: Header=BB2_2 Depth=1
movl 16(%rsp), %r14d
testl %r14d, %r14d
jle .LBB2_25
# %bb.20: # %.preheader.lr.ph.i
# in Loop: Header=BB2_2 Depth=1
movl 12(%rsp), %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
jmp .LBB2_21
.p2align 4, 0x90
.LBB2_24: # %._crit_edge.i
# in Loop: Header=BB2_21 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r13
addl %r15d, %r12d
cmpq %r14, %r13
je .LBB2_25
.LBB2_21: # %.preheader.i
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_23 Depth 3
testl %r15d, %r15d
jle .LBB2_24
# %bb.22: # %.lr.ph.i
# in Loop: Header=BB2_21 Depth=2
movl %r12d, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_23: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_21 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rbp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r15
jne .LBB2_23
jmp .LBB2_24
.LBB2_27:
movq stderr(%rip), %rdi
movl $.L.str.7, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB2_28:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $33, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB2_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
jmp .LBB2_12
.LBB2_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
.LBB2_12:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8hadamardPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8hadamardPfS_S_ii,@object # @_Z8hadamardPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z8hadamardPfS_S_ii
.p2align 3, 0x0
_Z8hadamardPfS_S_ii:
.quad _Z23__device_stub__hadamardPfS_S_ii
.size _Z8hadamardPfS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.2f "
.size .L.str, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d %d"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to allocate host vectors!\n"
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to launch vectorAdd kernel (error code %s)!\n"
.size .L.str.6, 52
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Result verification failed at element %d!\n"
.size .L.str.7, 43
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to deinitialize the device! error=%s\n"
.size .L.str.8, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8hadamardPfS_S_ii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__hadamardPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8hadamardPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
#include <sys/time.h>
using namespace std;
const int threadsPerBlock = 512;
const int N = (1 <<20)-3;
const int blocksPerGrid = (N + threadsPerBlock - 1)/threadsPerBlock;
const int iters = 100;
__global__ void kernel1(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = 1; s < blockDim.x; s*=2){
if(tid % (2*s) == 0 && i + s <N){
s_data[tid] += s_data[tid + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
__global__ void kernel2(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = 1; s < blockDim.x; s*=2){
int index = tid * 2 * s; // 原来是每个线程对应一个位置，第一轮循环，只有0、2、4、6这些线程在执行，1、3、5线程闲置，同一个warp内有一半线程没有用上
if((index + s) < blockDim.x && (blockIdx.x * blockDim.x + index + s) < N){ // 现在是tid号线程处理处理tid*2*s位置的任务，第一轮循环0123456线程都在线，warp利用率高
s_data[index] += s_data[index + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
__global__ void kernel3(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = blockDim.x/2; s > 0; s>>=1){ // 2的访问share memory的方式，存在share memory bank conflit
if(tid < s && i + s < N){
s_data[tid] += s_data[tid + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
void varifyOutput(float* predict, float* arr, int N){
float pred = 0.0;
for(int i=0;i<blocksPerGrid;i++){
pred += predict[i];
}
float result = 0.0;
struct timeval s;
struct timeval e;
gettimeofday(&s,NULL);
for(int t=0;t<iters;t++){
result = 0.0;
for(int i=0;i<N;i++){
result += arr[i];
}
}
gettimeofday(&e,NULL);
cout << "CPU Elapse time: " << ((e.tv_sec-s.tv_sec)*1000000+(e.tv_usec-s.tv_usec)) / iters / 1000.0 << " ms" << endl;
cout << "predict: " << pred << endl << "result: " << result << endl;
}
int main(){
float* a_host, *r_host;
float* a_device, *r_device;
cudaMallocHost(&a_host, N * sizeof(float));
cudaMallocHost(&r_host, blocksPerGrid * sizeof(float));
cudaMalloc(&a_device, N * sizeof(float));
cudaMalloc(&r_device, blocksPerGrid * sizeof(float));
for(int i=0;i<N;i++){
a_host[i] = 1;
}
for(int i=0;i<blocksPerGrid;i++){
r_host[i] = 0.0;
}
cudaStream_t stream;
cudaStreamCreate(&stream);
cudaMemcpyAsync(a_device, a_host, N * sizeof(float), cudaMemcpyHostToDevice, stream);
cudaMemcpyAsync(r_device, r_host, blocksPerGrid * sizeof(float), cudaMemcpyHostToDevice, stream);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
for(int i=0;i<iters;i++){
kernel3<<<blocksPerGrid, threadsPerBlock, 0, stream>>>(a_device, r_device, N);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "GPU Elapse time: " << elapsedTime / iters << " ms" << endl;
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(r_host, r_device, blocksPerGrid * sizeof(float), cudaMemcpyDeviceToHost);
varifyOutput(r_host, a_host, N);
cudaFree(r_device);
cudaFree(a_device);
cudaFreeHost(r_host);
cudaFreeHost(a_host);
return 0;
} | code for sm_80
Function : _Z7kernel3PfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R6, c[0x0][0x0], R7 ; /* 0x0000000006007a24 */
/* 0x001fca00078e0207 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0060*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff038424 */
/* 0x000fc800078e00ff */
/*0070*/ @!P0 IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000028625 */
/* 0x000fcc00078e0003 */
/*0080*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000602028981 */
/* 0x000ea2000c1e1900 */
/*0090*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00a0*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f25270 */
/*00b0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00c0*/ ISETP.NE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf45270 */
/*00d0*/ @!P0 STS [R7.X4], R2 ; /* 0x0000000207008388 */
/* 0x0041e80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00f0*/ @!P2 BRA 0x1e0 ; /* 0x000000e00000a947 */
/* 0x000fea0003800000 */
/*0100*/ SHF.L.U32 R2, R7, 0x2, RZ ; /* 0x0000000207027819 */
/* 0x001fe200000006ff */
/*0110*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*0120*/ IADD3 R4, R0, R3, RZ ; /* 0x0000000300047210 */
/* 0x000fc80007ffe0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fc80003f06070 */
/*0140*/ ISETP.GE.U32.OR P0, PT, R7, R3, P0 ; /* 0x000000030700720c */
/* 0x000fda0000706470 */
/*0150*/ @!P0 IMAD R4, R3, 0x4, R2 ; /* 0x0000000403048824 */
/* 0x000fe200078e0202 */
/*0160*/ @!P0 LDS R5, [R7.X4] ; /* 0x0000000007058984 */
/* 0x000fe20000004800 */
/*0170*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc80000011603 */
/*0180*/ @!P0 LDS R4, [R4] ; /* 0x0000000004048984 */
/* 0x000e240000000800 */
/*0190*/ @!P0 FADD R5, R5, R4 ; /* 0x0000000405058221 */
/* 0x001fca0000000000 */
/*01a0*/ @!P0 STS [R7.X4], R5 ; /* 0x0000000507008388 */
/* 0x0001e80000004800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*01d0*/ @P0 BRA 0x120 ; /* 0xffffff4000000947 */
/* 0x001fea000383ffff */
/*01e0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x001fea0003800000 */
/*01f0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0200*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0210*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0220*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7kernel2PfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x100 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GE.U32.AND P2, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f46070 */
/*0070*/ IMAD R2, R4, c[0x0][0x0], R5 ; /* 0x0000000004027a24 */
/* 0x001fe200078e0205 */
/*0080*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f25270 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06070 */
/*00a0*/ @P0 BRA 0xf0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00c0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0041e40000004800 */
/*00f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ @!P2 BRA 0x210 ; /* 0x000000f00000a947 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.SHL.U32 R0, R5, 0x2, RZ ; /* 0x0000000205007824 */
/* 0x000fe200078e00ff */
/*0130*/ MOV R3, 0x1 ; /* 0x0000000100037802 */
/* 0x000fca0000000f00 */
/*0140*/ IMAD R6, R0, R3, RZ ; /* 0x0000000300067224 */
/* 0x000fc800078e02ff */
/*0150*/ IMAD.IADD R5, R6, 0x1, R3 ; /* 0x0000000106057824 */
/* 0x001fe200078e0203 */
/*0160*/ SHF.L.U32 R3, R3, 0x1, RZ ; /* 0x0000000103037819 */
/* 0x000fc600000006ff */
/*0170*/ IMAD R2, R4, c[0x0][0x0], R5 ; /* 0x0000000004027a24 */
/* 0x000fca00078e0205 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fc80003f06070 */
/*0190*/ ISETP.GE.U32.OR P0, PT, R5, c[0x0][0x0], P0 ; /* 0x0000000005007a0c */
/* 0x000fda0000706470 */
/*01a0*/ @!P0 LDS R5, [R5.X4] ; /* 0x0000000005058984 */
/* 0x000fe80000004800 */
/*01b0*/ @!P0 LDS R2, [R6.X4] ; /* 0x0000000006028984 */
/* 0x000e240000004800 */
/*01c0*/ @!P0 FADD R2, R2, R5 ; /* 0x0000000502028221 */
/* 0x001fca0000000000 */
/*01d0*/ @!P0 STS [R6.X4], R2 ; /* 0x0000000206008388 */
/* 0x0001e80000004800 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x0], PT ; /* 0x0000000003007a0c */
/* 0x000fda0003f06070 */
/*0200*/ @!P0 BRA 0x140 ; /* 0xffffff3000008947 */
/* 0x001fea000383ffff */
/*0210*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0220*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*0230*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0240*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0003 */
/*0250*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7kernel1PfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x110 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GE.U32.AND P2, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f46070 */
/*0070*/ IMAD R4, R0, c[0x0][0x0], R8 ; /* 0x0000000000047a24 */
/* 0x001fe200078e0208 */
/*0080*/ ISETP.NE.AND P1, PT, R8.reuse, RZ, PT ; /* 0x000000ff0800720c */
/* 0x040fe40003f25270 */
/*0090*/ SHF.L.U32 R5, R8, 0x2, RZ ; /* 0x0000000208057819 */
/* 0x000fc400000006ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06070 */
/*00b0*/ @P0 BRA 0x100 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0003 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ STS [R8.X4], R2 ; /* 0x0000000208007388 */
/* 0x0041e40000004800 */
/*0100*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0120*/ @!P2 BRA 0x320 ; /* 0x000001f00000a947 */
/* 0x000fea0003800000 */
/*0130*/ HFMA2.MMA R6, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff067435 */
/* 0x000fd400000001ff */
/*0140*/ IMAD.SHL.U32 R10, R6, 0x2, RZ ; /* 0x00000002060a7824 */
/* 0x000fc800078e00ff */
/*0150*/ I2F.U32.RP R7, R10 ; /* 0x0000000a00077306 */
/* 0x000e620000209000 */
/*0160*/ IADD3 R9, RZ, -R10, RZ ; /* 0x8000000aff097210 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.NE.U32.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fca0003f45070 */
/*0180*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x002e640000001000 */
/*0190*/ IADD3 R2, R7, 0xffffffe, RZ ; /* 0x0ffffffe07027810 */
/* 0x003fcc0007ffe0ff */
/*01a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*01b0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*01c0*/ IMAD R9, R9, R3, RZ ; /* 0x0000000309097224 */
/* 0x002fc800078e02ff */
/*01d0*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fc800078e0002 */
/*01e0*/ IMAD.IADD R2, R4, 0x1, R6 ; /* 0x0000000104027824 */
/* 0x000fe400078e0206 */
/*01f0*/ IMAD.HI.U32 R3, R3, R8, RZ ; /* 0x0000000803037227 */
/* 0x000fca00078e00ff */
/*0200*/ IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03037210 */
/* 0x000fca0007ffe1ff */
/*0210*/ IMAD R3, R10, R3, R8 ; /* 0x000000030a037224 */
/* 0x000fca00078e0208 */
/*0220*/ ISETP.GE.U32.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f06070 */
/*0230*/ @P0 IMAD.IADD R3, R3, 0x1, -R10 ; /* 0x0000000103030824 */
/* 0x000fca00078e0a0a */
/*0240*/ ISETP.GE.U32.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f06070 */
/*0250*/ @P0 IADD3 R3, -R10, R3, RZ ; /* 0x000000030a030210 */
/* 0x000fe40007ffe1ff */
/*0260*/ @!P2 LOP3.LUT R3, RZ, R10, RZ, 0x33, !PT ; /* 0x0000000aff03a212 */
/* 0x000fc800078e33ff */
/*0270*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc80003f05270 */
/*0280*/ ISETP.GE.U32.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */
/* 0x000fda0000706470 */
/*0290*/ @!P0 LEA R2, R6, R5, 0x2 ; /* 0x0000000506028211 */
/* 0x000fe200078e10ff */
/*02a0*/ @!P0 LDS R3, [R8.X4] ; /* 0x0000000008038984 */
/* 0x000fe20000004800 */
/*02b0*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fc800078e000a */
/*02c0*/ @!P0 LDS R2, [R2] ; /* 0x0000000002028984 */
/* 0x000e240000000800 */
/*02d0*/ @!P0 FADD R3, R3, R2 ; /* 0x0000000203038221 */
/* 0x001fca0000000000 */
/*02e0*/ @!P0 STS [R8.X4], R3 ; /* 0x0000000308008388 */
/* 0x0001e80000004800 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x0], PT ; /* 0x000000000a007a0c */
/* 0x000fda0003f06070 */
/*0310*/ @!P0 BRA 0x140 ; /* 0xfffffe2000008947 */
/* 0x001fea000383ffff */
/*0320*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0330*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*0340*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0350*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x001fca00078e0003 */
/*0360*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include <sys/time.h>
using namespace std;
const int threadsPerBlock = 512;
const int N = (1 <<20)-3;
const int blocksPerGrid = (N + threadsPerBlock - 1)/threadsPerBlock;
const int iters = 100;
__global__ void kernel1(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = 1; s < blockDim.x; s*=2){
if(tid % (2*s) == 0 && i + s <N){
s_data[tid] += s_data[tid + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
__global__ void kernel2(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = 1; s < blockDim.x; s*=2){
int index = tid * 2 * s; // 原来是每个线程对应一个位置，第一轮循环，只有0、2、4、6这些线程在执行，1、3、5线程闲置，同一个warp内有一半线程没有用上
if((index + s) < blockDim.x && (blockIdx.x * blockDim.x + index + s) < N){ // 现在是tid号线程处理处理tid*2*s位置的任务，第一轮循环0123456线程都在线，warp利用率高
s_data[index] += s_data[index + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
__global__ void kernel3(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = blockDim.x/2; s > 0; s>>=1){ // 2的访问share memory的方式，存在share memory bank conflit
if(tid < s && i + s < N){
s_data[tid] += s_data[tid + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
void varifyOutput(float* predict, float* arr, int N){
float pred = 0.0;
for(int i=0;i<blocksPerGrid;i++){
pred += predict[i];
}
float result = 0.0;
struct timeval s;
struct timeval e;
gettimeofday(&s,NULL);
for(int t=0;t<iters;t++){
result = 0.0;
for(int i=0;i<N;i++){
result += arr[i];
}
}
gettimeofday(&e,NULL);
cout << "CPU Elapse time: " << ((e.tv_sec-s.tv_sec)*1000000+(e.tv_usec-s.tv_usec)) / iters / 1000.0 << " ms" << endl;
cout << "predict: " << pred << endl << "result: " << result << endl;
}
int main(){
float* a_host, *r_host;
float* a_device, *r_device;
cudaMallocHost(&a_host, N * sizeof(float));
cudaMallocHost(&r_host, blocksPerGrid * sizeof(float));
cudaMalloc(&a_device, N * sizeof(float));
cudaMalloc(&r_device, blocksPerGrid * sizeof(float));
for(int i=0;i<N;i++){
a_host[i] = 1;
}
for(int i=0;i<blocksPerGrid;i++){
r_host[i] = 0.0;
}
cudaStream_t stream;
cudaStreamCreate(&stream);
cudaMemcpyAsync(a_device, a_host, N * sizeof(float), cudaMemcpyHostToDevice, stream);
cudaMemcpyAsync(r_device, r_host, blocksPerGrid * sizeof(float), cudaMemcpyHostToDevice, stream);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
for(int i=0;i<iters;i++){
kernel3<<<blocksPerGrid, threadsPerBlock, 0, stream>>>(a_device, r_device, N);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "GPU Elapse time: " << elapsedTime / iters << " ms" << endl;
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(r_host, r_device, blocksPerGrid * sizeof(float), cudaMemcpyDeviceToHost);
varifyOutput(r_host, a_host, N);
cudaFree(r_device);
cudaFree(a_device);
cudaFreeHost(r_host);
cudaFreeHost(a_host);
return 0;
} | .file "tmpxft_00019b03_00000000-6_reduction.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CPU Elapse time: "
.LC3:
.string " ms"
.LC4:
.string "predict: "
.LC5:
.string "result: "
.text
.globl _Z12varifyOutputPfS_i
.type _Z12varifyOutputPfS_i, @function
_Z12varifyOutputPfS_i:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %rsi, %rbp
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq %rdi, %rax
leaq 8192(%rdi), %rdx
movl $0x00000000, 12(%rsp)
.L4:
movss 12(%rsp), %xmm2
addss (%rax), %xmm2
movss %xmm2, 12(%rsp)
addq $4, %rax
cmpq %rax, %rdx
jne .L4
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movslq %r12d, %rax
leaq 0(%rbp,%rax,4), %rdx
movl $100, %ecx
jmp .L5
.L6:
movd %ebx, %xmm1
addss (%rax), %xmm1
movd %xmm1, %ebx
addq $4, %rax
cmpq %rax, %rdx
jne .L6
.L8:
subl $1, %ecx
je .L7
.L5:
movq %rbp, %rax
movl $0x00000000, %ebx
testl %r12d, %r12d
jg .L6
jmp .L8
.L7:
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $17, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 32(%rsp), %rcx
subq 16(%rsp), %rcx
imulq $1000000, %rcx, %rcx
addq 40(%rsp), %rcx
subq 24(%rsp), %rcx
movabsq $-6640827866535438581, %rdx
movq %rcx, %rax
imulq %rdx
leaq (%rdx,%rcx), %rax
sarq $6, %rax
sarq $63, %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L27
cmpb $0, 56(%r12)
je .L11
movzbl 67(%r12), %eax
.L12:
movsbl %al, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $9, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbp
testq %rbp, %rbp
je .L28
cmpb $0, 56(%rbp)
je .L15
movzbl 67(%rbp), %eax
.L16:
movsbl %al, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %rax, %rbp
movl $8, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movd %ebx, %xmm3
pxor %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L29
cmpb $0, 56(%rbx)
je .L19
movzbl 67(%rbx), %eax
.L20:
movsbl %al, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
call _ZSt16__throw_bad_castv@PLT
.L31:
call __stack_chk_fail@PLT
.L11:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
jmp .L12
.L28:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
call _ZSt16__throw_bad_castv@PLT
.L32:
call __stack_chk_fail@PLT
.L15:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L16
.L29:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
call _ZSt16__throw_bad_castv@PLT
.L33:
call __stack_chk_fail@PLT
.L19:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L20
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z12varifyOutputPfS_i, .-_Z12varifyOutputPfS_i
.globl _Z29__device_stub__Z7kernel1PfS_iPfS_i
.type _Z29__device_stub__Z7kernel1PfS_iPfS_i, @function
_Z29__device_stub__Z7kernel1PfS_iPfS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kernel1PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z29__device_stub__Z7kernel1PfS_iPfS_i, .-_Z29__device_stub__Z7kernel1PfS_iPfS_i
.globl _Z7kernel1PfS_i
.type _Z7kernel1PfS_i, @function
_Z7kernel1PfS_i:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7kernel1PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7kernel1PfS_i, .-_Z7kernel1PfS_i
.globl _Z29__device_stub__Z7kernel2PfS_iPfS_i
.type _Z29__device_stub__Z7kernel2PfS_iPfS_i, @function
_Z29__device_stub__Z7kernel2PfS_iPfS_i:
.LFB3697:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kernel2PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z29__device_stub__Z7kernel2PfS_iPfS_i, .-_Z29__device_stub__Z7kernel2PfS_iPfS_i
.globl _Z7kernel2PfS_i
.type _Z7kernel2PfS_i, @function
_Z7kernel2PfS_i:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7kernel2PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z7kernel2PfS_i, .-_Z7kernel2PfS_i
.globl _Z29__device_stub__Z7kernel3PfS_iPfS_i
.type _Z29__device_stub__Z7kernel3PfS_iPfS_i, @function
_Z29__device_stub__Z7kernel3PfS_iPfS_i:
.LFB3699:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L54
.L50:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kernel3PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L50
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z29__device_stub__Z7kernel3PfS_iPfS_i, .-_Z29__device_stub__Z7kernel3PfS_iPfS_i
.globl _Z7kernel3PfS_i
.type _Z7kernel3PfS_i, @function
_Z7kernel3PfS_i:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7kernel3PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z7kernel3PfS_i, .-_Z7kernel3PfS_i
.section .rodata.str1.1
.LC7:
.string "GPU Elapse time: "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $96, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $0, %edx
movl $4194292, %esi
call cudaHostAlloc@PLT
leaq 16(%rsp), %rdi
movl $0, %edx
movl $8192, %esi
call cudaHostAlloc@PLT
leaq 24(%rsp), %rdi
movl $4194292, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC6(%rip), %xmm0
.L59:
movq 8(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194292, %rax
jne .L59
movl $0, %eax
.L60:
movq 16(%rsp), %rdx
movl $0x00000000, (%rdx,%rax)
addq $4, %rax
cmpq $8192, %rax
jne .L60
leaq 40(%rsp), %rdi
call cudaStreamCreate@PLT
movq 40(%rsp), %r8
movl $1, %ecx
movl $4194292, %edx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq 40(%rsp), %r8
movl $1, %ecx
movl $8192, %edx
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpyAsync@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, %ebx
jmp .L62
.L61:
subl $1, %ebx
je .L68
.L62:
movl $512, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $2048, 64(%rsp)
movl $1, 68(%rsp)
movq 40(%rsp), %r9
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L61
movl $1048573, %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z7kernel3PfS_iPfS_i
jmp .L61
.L68:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movss 76(%rsp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $8192, %edx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1048573, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z12varifyOutputPfS_i
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L69
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z7kernel3PfS_i"
.LC10:
.string "_Z7kernel2PfS_i"
.LC11:
.string "_Z7kernel1PfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3702:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel3PfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel2PfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1PfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1083129856
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1065353216
.align 4
.LC8:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include <sys/time.h>
using namespace std;
const int threadsPerBlock = 512;
const int N = (1 <<20)-3;
const int blocksPerGrid = (N + threadsPerBlock - 1)/threadsPerBlock;
const int iters = 100;
__global__ void kernel1(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = 1; s < blockDim.x; s*=2){
if(tid % (2*s) == 0 && i + s <N){
s_data[tid] += s_data[tid + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
__global__ void kernel2(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = 1; s < blockDim.x; s*=2){
int index = tid * 2 * s; // 原来是每个线程对应一个位置，第一轮循环，只有0、2、4、6这些线程在执行，1、3、5线程闲置，同一个warp内有一半线程没有用上
if((index + s) < blockDim.x && (blockIdx.x * blockDim.x + index + s) < N){ // 现在是tid号线程处理处理tid*2*s位置的任务，第一轮循环0123456线程都在线，warp利用率高
s_data[index] += s_data[index + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
__global__ void kernel3(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = blockDim.x/2; s > 0; s>>=1){ // 2的访问share memory的方式，存在share memory bank conflit
if(tid < s && i + s < N){
s_data[tid] += s_data[tid + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
void varifyOutput(float* predict, float* arr, int N){
float pred = 0.0;
for(int i=0;i<blocksPerGrid;i++){
pred += predict[i];
}
float result = 0.0;
struct timeval s;
struct timeval e;
gettimeofday(&s,NULL);
for(int t=0;t<iters;t++){
result = 0.0;
for(int i=0;i<N;i++){
result += arr[i];
}
}
gettimeofday(&e,NULL);
cout << "CPU Elapse time: " << ((e.tv_sec-s.tv_sec)*1000000+(e.tv_usec-s.tv_usec)) / iters / 1000.0 << " ms" << endl;
cout << "predict: " << pred << endl << "result: " << result << endl;
}
int main(){
float* a_host, *r_host;
float* a_device, *r_device;
cudaMallocHost(&a_host, N * sizeof(float));
cudaMallocHost(&r_host, blocksPerGrid * sizeof(float));
cudaMalloc(&a_device, N * sizeof(float));
cudaMalloc(&r_device, blocksPerGrid * sizeof(float));
for(int i=0;i<N;i++){
a_host[i] = 1;
}
for(int i=0;i<blocksPerGrid;i++){
r_host[i] = 0.0;
}
cudaStream_t stream;
cudaStreamCreate(&stream);
cudaMemcpyAsync(a_device, a_host, N * sizeof(float), cudaMemcpyHostToDevice, stream);
cudaMemcpyAsync(r_device, r_host, blocksPerGrid * sizeof(float), cudaMemcpyHostToDevice, stream);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
for(int i=0;i<iters;i++){
kernel3<<<blocksPerGrid, threadsPerBlock, 0, stream>>>(a_device, r_device, N);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "GPU Elapse time: " << elapsedTime / iters << " ms" << endl;
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(r_host, r_device, blocksPerGrid * sizeof(float), cudaMemcpyDeviceToHost);
varifyOutput(r_host, a_host, N);
cudaFree(r_device);
cudaFree(a_device);
cudaFreeHost(r_host);
cudaFreeHost(a_host);
return 0;
} | #include <hip/hip_runtime.h>
#include<iostream>
#include <sys/time.h>
using namespace std;
const int threadsPerBlock = 512;
const int N = (1 <<20)-3;
const int blocksPerGrid = (N + threadsPerBlock - 1)/threadsPerBlock;
const int iters = 100;
__global__ void kernel1(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = 1; s < blockDim.x; s*=2){
if(tid % (2*s) == 0 && i + s <N){
s_data[tid] += s_data[tid + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
__global__ void kernel2(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = 1; s < blockDim.x; s*=2){
int index = tid * 2 * s; // 原来是每个线程对应一个位置，第一轮循环，只有0、2、4、6这些线程在执行，1、3、5线程闲置，同一个warp内有一半线程没有用上
if((index + s) < blockDim.x && (blockIdx.x * blockDim.x + index + s) < N){ // 现在是tid号线程处理处理tid*2*s位置的任务，第一轮循环0123456线程都在线，warp利用率高
s_data[index] += s_data[index + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
__global__ void kernel3(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = blockDim.x/2; s > 0; s>>=1){ // 2的访问share memory的方式，存在share memory bank conflit
if(tid < s && i + s < N){
s_data[tid] += s_data[tid + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
void varifyOutput(float* predict, float* arr, int N){
float pred = 0.0;
for(int i=0;i<blocksPerGrid;i++){
pred += predict[i];
}
float result = 0.0;
struct timeval s;
struct timeval e;
gettimeofday(&s,NULL);
for(int t=0;t<iters;t++){
result = 0.0;
for(int i=0;i<N;i++){
result += arr[i];
}
}
gettimeofday(&e,NULL);
cout << "CPU Elapse time: " << ((e.tv_sec-s.tv_sec)*1000000+(e.tv_usec-s.tv_usec)) / iters / 1000.0 << " ms" << endl;
cout << "predict: " << pred << endl << "result: " << result << endl;
}
int main(){
float* a_host, *r_host;
float* a_device, *r_device;
hipHostMalloc(&a_host, N * sizeof(float), hipHostMallocDefault);
hipHostMalloc(&r_host, blocksPerGrid * sizeof(float), hipHostMallocDefault);
hipMalloc(&a_device, N * sizeof(float));
hipMalloc(&r_device, blocksPerGrid * sizeof(float));
for(int i=0;i<N;i++){
a_host[i] = 1;
}
for(int i=0;i<blocksPerGrid;i++){
r_host[i] = 0.0;
}
hipStream_t stream;
hipStreamCreate(&stream);
hipMemcpyAsync(a_device, a_host, N * sizeof(float), hipMemcpyHostToDevice, stream);
hipMemcpyAsync(r_device, r_host, blocksPerGrid * sizeof(float), hipMemcpyHostToDevice, stream);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
for(int i=0;i<iters;i++){
kernel3<<<blocksPerGrid, threadsPerBlock, 0, stream>>>(a_device, r_device, N);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "GPU Elapse time: " << elapsedTime / iters << " ms" << endl;
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(r_host, r_device, blocksPerGrid * sizeof(float), hipMemcpyDeviceToHost);
varifyOutput(r_host, a_host, N);
hipFree(r_device);
hipFree(a_device);
hipHostFree(r_host);
hipHostFree(a_host);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include <sys/time.h>
using namespace std;
const int threadsPerBlock = 512;
const int N = (1 <<20)-3;
const int blocksPerGrid = (N + threadsPerBlock - 1)/threadsPerBlock;
const int iters = 100;
__global__ void kernel1(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = 1; s < blockDim.x; s*=2){
if(tid % (2*s) == 0 && i + s <N){
s_data[tid] += s_data[tid + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
__global__ void kernel2(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = 1; s < blockDim.x; s*=2){
int index = tid * 2 * s; // 原来是每个线程对应一个位置，第一轮循环，只有0、2、4、6这些线程在执行，1、3、5线程闲置，同一个warp内有一半线程没有用上
if((index + s) < blockDim.x && (blockIdx.x * blockDim.x + index + s) < N){ // 现在是tid号线程处理处理tid*2*s位置的任务，第一轮循环0123456线程都在线，warp利用率高
s_data[index] += s_data[index + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
__global__ void kernel3(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = blockDim.x/2; s > 0; s>>=1){ // 2的访问share memory的方式，存在share memory bank conflit
if(tid < s && i + s < N){
s_data[tid] += s_data[tid + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
void varifyOutput(float* predict, float* arr, int N){
float pred = 0.0;
for(int i=0;i<blocksPerGrid;i++){
pred += predict[i];
}
float result = 0.0;
struct timeval s;
struct timeval e;
gettimeofday(&s,NULL);
for(int t=0;t<iters;t++){
result = 0.0;
for(int i=0;i<N;i++){
result += arr[i];
}
}
gettimeofday(&e,NULL);
cout << "CPU Elapse time: " << ((e.tv_sec-s.tv_sec)*1000000+(e.tv_usec-s.tv_usec)) / iters / 1000.0 << " ms" << endl;
cout << "predict: " << pred << endl << "result: " << result << endl;
}
int main(){
float* a_host, *r_host;
float* a_device, *r_device;
hipHostMalloc(&a_host, N * sizeof(float), hipHostMallocDefault);
hipHostMalloc(&r_host, blocksPerGrid * sizeof(float), hipHostMallocDefault);
hipMalloc(&a_device, N * sizeof(float));
hipMalloc(&r_device, blocksPerGrid * sizeof(float));
for(int i=0;i<N;i++){
a_host[i] = 1;
}
for(int i=0;i<blocksPerGrid;i++){
r_host[i] = 0.0;
}
hipStream_t stream;
hipStreamCreate(&stream);
hipMemcpyAsync(a_device, a_host, N * sizeof(float), hipMemcpyHostToDevice, stream);
hipMemcpyAsync(r_device, r_host, blocksPerGrid * sizeof(float), hipMemcpyHostToDevice, stream);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
for(int i=0;i<iters;i++){
kernel3<<<blocksPerGrid, threadsPerBlock, 0, stream>>>(a_device, r_device, N);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "GPU Elapse time: " << elapsedTime / iters << " ms" << endl;
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(r_host, r_device, blocksPerGrid * sizeof(float), hipMemcpyDeviceToHost);
varifyOutput(r_host, a_host, N);
hipFree(r_device);
hipFree(a_device);
hipHostFree(r_host);
hipHostFree(a_host);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel1PfS_i
.globl _Z7kernel1PfS_i
.p2align 8
.type _Z7kernel1PfS_i,@function
_Z7kernel1PfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_lt_u32 s5, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
v_lshlrev_b32_e32 v2, 2, v0
s_mov_b32 s7, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_ge_u32 s6, s5
s_mov_b32 s7, s6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_5:
s_lshl_b32 s6, s7, 1
v_add_nc_u32_e32 v4, s7, v1
s_add_i32 s2, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v3, s2, v0
v_cmp_gt_u32_e64 s2, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, 0, v3
s_and_b32 s8, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s8
s_cbranch_execz .LBB0_4
v_add_lshl_u32 v3, s7, v0, 2
ds_load_b32 v3, v3
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
ds_store_b32 v2, v3
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel1PfS_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel1PfS_i, .Lfunc_end0-_Z7kernel1PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7kernel2PfS_i
.globl _Z7kernel2PfS_i
.p2align 8
.type _Z7kernel2PfS_i,@function
_Z7kernel2PfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_mov_b32 s2, exec_lo
s_mul_i32 s6, s15, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s6, v0
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b64 s[8:9], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_b32 v1, v[1:2], off
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_lt_u32 s5, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_7
v_lshlrev_b32_e32 v1, 1, v0
s_mov_b32 s7, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_5
.p2align 6
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s2
s_lshl_b32 s7, s7, 1
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s7, s5
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_7
.LBB1_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s7, v1
v_add_nc_u32_e32 v3, s7, v2
v_add3_u32 v4, s7, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s5, v3
v_cmp_gt_u32_e64 s2, s3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, vcc_lo, s2
s_and_saveexec_b32 s2, s8
s_cbranch_execz .LBB1_4
v_lshlrev_b32_e32 v3, 2, v3
v_lshlrev_b32_e32 v2, 2, v2
ds_load_b32 v3, v3
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
ds_store_b32 v2, v3
s_branch .LBB1_4
.LBB1_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_9
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel2PfS_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7kernel2PfS_i, .Lfunc_end1-_Z7kernel2PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7kernel3PfS_i
.globl _Z7kernel3PfS_i
.p2align 8
.type _Z7kernel3PfS_i,@function
_Z7kernel3PfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB2_2
s_load_b64 s[6:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_lt_u32 s5, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_7
v_lshlrev_b32_e32 v2, 2, v0
s_branch .LBB2_5
.p2align 6
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_lt_u32 s5, 4
s_mov_b32 s5, s6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_7
.LBB2_5:
s_lshr_b32 s6, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, s6, v1
v_cmp_gt_u32_e32 vcc_lo, s6, v0
v_cmp_gt_u32_e64 s2, s3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s7, vcc_lo, s2
s_and_saveexec_b32 s2, s7
s_cbranch_execz .LBB2_4
v_add_lshl_u32 v3, s6, v0, 2
ds_load_b32 v3, v3
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
ds_store_b32 v2, v3
s_branch .LBB2_4
.LBB2_7:
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_9
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB2_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel3PfS_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7kernel3PfS_i, .Lfunc_end2-_Z7kernel3PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel1PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel1PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel2PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel2PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel3PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel3PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include <sys/time.h>
using namespace std;
const int threadsPerBlock = 512;
const int N = (1 <<20)-3;
const int blocksPerGrid = (N + threadsPerBlock - 1)/threadsPerBlock;
const int iters = 100;
__global__ void kernel1(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = 1; s < blockDim.x; s*=2){
if(tid % (2*s) == 0 && i + s <N){
s_data[tid] += s_data[tid + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
__global__ void kernel2(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = 1; s < blockDim.x; s*=2){
int index = tid * 2 * s; // 原来是每个线程对应一个位置，第一轮循环，只有0、2、4、6这些线程在执行，1、3、5线程闲置，同一个warp内有一半线程没有用上
if((index + s) < blockDim.x && (blockIdx.x * blockDim.x + index + s) < N){ // 现在是tid号线程处理处理tid*2*s位置的任务，第一轮循环0123456线程都在线，warp利用率高
s_data[index] += s_data[index + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
__global__ void kernel3(float* arr, float* out, int N){
__shared__ float s_data[threadsPerBlock];
unsigned int tid = threadIdx.x;
unsigned int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i < N){
s_data[tid] = arr[i];
}
__syncthreads();
for(int s = blockDim.x/2; s > 0; s>>=1){ // 2的访问share memory的方式，存在share memory bank conflit
if(tid < s && i + s < N){
s_data[tid] += s_data[tid + s];
}
__syncthreads();
}
if(tid == 0){
out[blockIdx.x] = s_data[0];
}
}
void varifyOutput(float* predict, float* arr, int N){
float pred = 0.0;
for(int i=0;i<blocksPerGrid;i++){
pred += predict[i];
}
float result = 0.0;
struct timeval s;
struct timeval e;
gettimeofday(&s,NULL);
for(int t=0;t<iters;t++){
result = 0.0;
for(int i=0;i<N;i++){
result += arr[i];
}
}
gettimeofday(&e,NULL);
cout << "CPU Elapse time: " << ((e.tv_sec-s.tv_sec)*1000000+(e.tv_usec-s.tv_usec)) / iters / 1000.0 << " ms" << endl;
cout << "predict: " << pred << endl << "result: " << result << endl;
}
int main(){
float* a_host, *r_host;
float* a_device, *r_device;
hipHostMalloc(&a_host, N * sizeof(float), hipHostMallocDefault);
hipHostMalloc(&r_host, blocksPerGrid * sizeof(float), hipHostMallocDefault);
hipMalloc(&a_device, N * sizeof(float));
hipMalloc(&r_device, blocksPerGrid * sizeof(float));
for(int i=0;i<N;i++){
a_host[i] = 1;
}
for(int i=0;i<blocksPerGrid;i++){
r_host[i] = 0.0;
}
hipStream_t stream;
hipStreamCreate(&stream);
hipMemcpyAsync(a_device, a_host, N * sizeof(float), hipMemcpyHostToDevice, stream);
hipMemcpyAsync(r_device, r_host, blocksPerGrid * sizeof(float), hipMemcpyHostToDevice, stream);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
for(int i=0;i<iters;i++){
kernel3<<<blocksPerGrid, threadsPerBlock, 0, stream>>>(a_device, r_device, N);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "GPU Elapse time: " << elapsedTime / iters << " ms" << endl;
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(r_host, r_device, blocksPerGrid * sizeof(float), hipMemcpyDeviceToHost);
varifyOutput(r_host, a_host, N);
hipFree(r_device);
hipFree(a_device);
hipHostFree(r_host);
hipHostFree(a_host);
return 0;
} | .text
.file "reduction.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__kernel1PfS_i # -- Begin function _Z22__device_stub__kernel1PfS_i
.p2align 4, 0x90
.type _Z22__device_stub__kernel1PfS_i,@function
_Z22__device_stub__kernel1PfS_i: # @_Z22__device_stub__kernel1PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kernel1PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel1PfS_i, .Lfunc_end0-_Z22__device_stub__kernel1PfS_i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel2PfS_i # -- Begin function _Z22__device_stub__kernel2PfS_i
.p2align 4, 0x90
.type _Z22__device_stub__kernel2PfS_i,@function
_Z22__device_stub__kernel2PfS_i: # @_Z22__device_stub__kernel2PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kernel2PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__kernel2PfS_i, .Lfunc_end1-_Z22__device_stub__kernel2PfS_i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel3PfS_i # -- Begin function _Z22__device_stub__kernel3PfS_i
.p2align 4, 0x90
.type _Z22__device_stub__kernel3PfS_i,@function
_Z22__device_stub__kernel3PfS_i: # @_Z22__device_stub__kernel3PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kernel3PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z22__device_stub__kernel3PfS_i, .Lfunc_end2-_Z22__device_stub__kernel3PfS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12varifyOutputPfS_i
.LCPI3_0:
.quad 0x408f400000000000 # double 1000
.text
.globl _Z12varifyOutputPfS_i
.p2align 4, 0x90
.type _Z12varifyOutputPfS_i,@function
_Z12varifyOutputPfS_i: # @_Z12varifyOutputPfS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $48, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r14
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
addss (%rdi,%rax,4), %xmm0
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB3_1
# %bb.2:
movss %xmm0, 12(%rsp) # 4-byte Spill
xorl %r15d, %r15d
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl %ebx, %eax
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_6: # %._crit_edge
# in Loop: Header=BB3_3 Depth=1
incl %r15d
cmpl $100, %r15d
je .LBB3_7
.LBB3_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
xorps %xmm0, %xmm0
testl %ebx, %ebx
jle .LBB3_6
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB3_3 Depth=1
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_5: # %.lr.ph
# Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
addss (%r14,%rcx,4), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB3_5
jmp .LBB3_6
.LBB3_7:
movss %xmm0, 8(%rsp) # 4-byte Spill
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq 32(%rsp), %rax
subq 40(%rsp), %rcx
imulq $1000000, %rax, %rax # imm = 0xF4240
addq %rax, %rcx
movabsq $-6640827866535438581, %rdx # imm = 0xA3D70A3D70A3D70B
movq %rcx, %rax
imulq %rdx
addq %rcx, %rdx
movq %rdx, %rax
shrq $63, %rax
sarq $6, %rdx
addq %rax, %rdx
xorps %xmm0, %xmm0
cvtsi2sd %rdx, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_20
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB3_10
# %bb.9:
movzbl 67(%r14), %eax
jmp .LBB3_11
.LBB3_10:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_20
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i19
cmpb $0, 56(%rbx)
je .LBB3_14
# %bb.13:
movzbl 67(%rbx), %ecx
jmp .LBB3_15
.LBB3_14:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit22
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rax, %rbx
movl $.L.str.3, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_20
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i24
cmpb $0, 56(%rbx)
je .LBB3_18
# %bb.17:
movzbl 67(%rbx), %ecx
jmp .LBB3_19
.LBB3_18:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit27
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
addq $48, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB3_20:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z12varifyOutputPfS_i, .Lfunc_end3-_Z12varifyOutputPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x42c80000 # float 100
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
xorl %ebx, %ebx
movl $4194292, %esi # imm = 0x3FFFF4
xorl %edx, %edx
callq hipHostMalloc
movq %rsp, %rdi
movl $8192, %esi # imm = 0x2000
xorl %edx, %edx
callq hipHostMalloc
leaq 48(%rsp), %rdi
movl $4194292, %esi # imm = 0x3FFFF4
callq hipMalloc
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movq 24(%rsp), %rax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rbx,4) # imm = 0x3F800000
incq %rbx
cmpq $1048573, %rbx # imm = 0xFFFFD
jne .LBB4_1
# %bb.2: # %.preheader
movabsq $4294967808, %rbx # imm = 0x100000200
movq (%rsp), %rdi
movl $8192, %edx # imm = 0x2000
xorl %esi, %esi
callq memset@PLT
leaq 40(%rsp), %rdi
callq hipStreamCreate
movq 48(%rsp), %rdi
movq 24(%rsp), %rsi
movq 40(%rsp), %r8
movl $4194292, %edx # imm = 0x3FFFF4
movl $1, %ecx
callq hipMemcpyAsync
movq 16(%rsp), %rdi
movq (%rsp), %rsi
movq 40(%rsp), %r8
movl $8192, %edx # imm = 0x2000
movl $1, %ecx
callq hipMemcpyAsync
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100, %r12d
leaq 1536(%rbx), %r14
leaq 96(%rsp), %r13
leaq 88(%rsp), %rbp
leaq 64(%rsp), %r15
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_5: # in Loop: Header=BB4_3 Depth=1
decl %r12d
je .LBB4_6
.LBB4_3: # =>This Inner Loop Header: Depth=1
movq 40(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_5
# %bb.4: # in Loop: Header=BB4_3 Depth=1
movq 48(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl $1048573, 60(%rsp) # imm = 0xFFFFD
leaq 144(%rsp), %rax
movq %rax, 64(%rsp)
leaq 136(%rsp), %rax
movq %rax, 72(%rsp)
leaq 60(%rsp), %rax
movq %rax, 80(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z7kernel3PfS_i, %edi
movq %r15, %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_5
.LBB4_6:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB4_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB4_9
# %bb.8:
movzbl 67(%r14), %eax
jmp .LBB4_10
.LBB4_9:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
movq 16(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movq 24(%rsp), %rsi
movl $1048573, %edx # imm = 0xFFFFD
callq _Z12varifyOutputPfS_i
movq 16(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipHostFree
movq 24(%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_11:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1PfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel2PfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel3PfS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernel1PfS_i,@object # @_Z7kernel1PfS_i
.section .rodata,"a",@progbits
.globl _Z7kernel1PfS_i
.p2align 3, 0x0
_Z7kernel1PfS_i:
.quad _Z22__device_stub__kernel1PfS_i
.size _Z7kernel1PfS_i, 8
.type _Z7kernel2PfS_i,@object # @_Z7kernel2PfS_i
.globl _Z7kernel2PfS_i
.p2align 3, 0x0
_Z7kernel2PfS_i:
.quad _Z22__device_stub__kernel2PfS_i
.size _Z7kernel2PfS_i, 8
.type _Z7kernel3PfS_i,@object # @_Z7kernel3PfS_i
.globl _Z7kernel3PfS_i
.p2align 3, 0x0
_Z7kernel3PfS_i:
.quad _Z22__device_stub__kernel3PfS_i
.size _Z7kernel3PfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU Elapse time: "
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ms"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "predict: "
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "result: "
.size .L.str.3, 9
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU Elapse time: "
.size .L.str.4, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7kernel1PfS_i"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7kernel2PfS_i"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7kernel3PfS_i"
.size .L__unnamed_3, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel1PfS_i
.addrsig_sym _Z22__device_stub__kernel2PfS_i
.addrsig_sym _Z22__device_stub__kernel3PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernel1PfS_i
.addrsig_sym _Z7kernel2PfS_i
.addrsig_sym _Z7kernel3PfS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7kernel3PfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R6, c[0x0][0x0], R7 ; /* 0x0000000006007a24 */
/* 0x001fca00078e0207 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0060*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff038424 */
/* 0x000fc800078e00ff */
/*0070*/ @!P0 IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000028625 */
/* 0x000fcc00078e0003 */
/*0080*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000602028981 */
/* 0x000ea2000c1e1900 */
/*0090*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00a0*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f25270 */
/*00b0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00c0*/ ISETP.NE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf45270 */
/*00d0*/ @!P0 STS [R7.X4], R2 ; /* 0x0000000207008388 */
/* 0x0041e80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00f0*/ @!P2 BRA 0x1e0 ; /* 0x000000e00000a947 */
/* 0x000fea0003800000 */
/*0100*/ SHF.L.U32 R2, R7, 0x2, RZ ; /* 0x0000000207027819 */
/* 0x001fe200000006ff */
/*0110*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*0120*/ IADD3 R4, R0, R3, RZ ; /* 0x0000000300047210 */
/* 0x000fc80007ffe0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fc80003f06070 */
/*0140*/ ISETP.GE.U32.OR P0, PT, R7, R3, P0 ; /* 0x000000030700720c */
/* 0x000fda0000706470 */
/*0150*/ @!P0 IMAD R4, R3, 0x4, R2 ; /* 0x0000000403048824 */
/* 0x000fe200078e0202 */
/*0160*/ @!P0 LDS R5, [R7.X4] ; /* 0x0000000007058984 */
/* 0x000fe20000004800 */
/*0170*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc80000011603 */
/*0180*/ @!P0 LDS R4, [R4] ; /* 0x0000000004048984 */
/* 0x000e240000000800 */
/*0190*/ @!P0 FADD R5, R5, R4 ; /* 0x0000000405058221 */
/* 0x001fca0000000000 */
/*01a0*/ @!P0 STS [R7.X4], R5 ; /* 0x0000000507008388 */
/* 0x0001e80000004800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*01d0*/ @P0 BRA 0x120 ; /* 0xffffff4000000947 */
/* 0x001fea000383ffff */
/*01e0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x001fea0003800000 */
/*01f0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0200*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0210*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0220*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7kernel2PfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x100 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GE.U32.AND P2, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f46070 */
/*0070*/ IMAD R2, R4, c[0x0][0x0], R5 ; /* 0x0000000004027a24 */
/* 0x001fe200078e0205 */
/*0080*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f25270 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06070 */
/*00a0*/ @P0 BRA 0xf0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00c0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0041e40000004800 */
/*00f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ @!P2 BRA 0x210 ; /* 0x000000f00000a947 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.SHL.U32 R0, R5, 0x2, RZ ; /* 0x0000000205007824 */
/* 0x000fe200078e00ff */
/*0130*/ MOV R3, 0x1 ; /* 0x0000000100037802 */
/* 0x000fca0000000f00 */
/*0140*/ IMAD R6, R0, R3, RZ ; /* 0x0000000300067224 */
/* 0x000fc800078e02ff */
/*0150*/ IMAD.IADD R5, R6, 0x1, R3 ; /* 0x0000000106057824 */
/* 0x001fe200078e0203 */
/*0160*/ SHF.L.U32 R3, R3, 0x1, RZ ; /* 0x0000000103037819 */
/* 0x000fc600000006ff */
/*0170*/ IMAD R2, R4, c[0x0][0x0], R5 ; /* 0x0000000004027a24 */
/* 0x000fca00078e0205 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fc80003f06070 */
/*0190*/ ISETP.GE.U32.OR P0, PT, R5, c[0x0][0x0], P0 ; /* 0x0000000005007a0c */
/* 0x000fda0000706470 */
/*01a0*/ @!P0 LDS R5, [R5.X4] ; /* 0x0000000005058984 */
/* 0x000fe80000004800 */
/*01b0*/ @!P0 LDS R2, [R6.X4] ; /* 0x0000000006028984 */
/* 0x000e240000004800 */
/*01c0*/ @!P0 FADD R2, R2, R5 ; /* 0x0000000502028221 */
/* 0x001fca0000000000 */
/*01d0*/ @!P0 STS [R6.X4], R2 ; /* 0x0000000206008388 */
/* 0x0001e80000004800 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x0], PT ; /* 0x0000000003007a0c */
/* 0x000fda0003f06070 */
/*0200*/ @!P0 BRA 0x140 ; /* 0xffffff3000008947 */
/* 0x001fea000383ffff */
/*0210*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0220*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*0230*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0240*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0003 */
/*0250*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7kernel1PfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x110 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GE.U32.AND P2, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f46070 */
/*0070*/ IMAD R4, R0, c[0x0][0x0], R8 ; /* 0x0000000000047a24 */
/* 0x001fe200078e0208 */
/*0080*/ ISETP.NE.AND P1, PT, R8.reuse, RZ, PT ; /* 0x000000ff0800720c */
/* 0x040fe40003f25270 */
/*0090*/ SHF.L.U32 R5, R8, 0x2, RZ ; /* 0x0000000208057819 */
/* 0x000fc400000006ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06070 */
/*00b0*/ @P0 BRA 0x100 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0003 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ STS [R8.X4], R2 ; /* 0x0000000208007388 */
/* 0x0041e40000004800 */
/*0100*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0120*/ @!P2 BRA 0x320 ; /* 0x000001f00000a947 */
/* 0x000fea0003800000 */
/*0130*/ HFMA2.MMA R6, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff067435 */
/* 0x000fd400000001ff */
/*0140*/ IMAD.SHL.U32 R10, R6, 0x2, RZ ; /* 0x00000002060a7824 */
/* 0x000fc800078e00ff */
/*0150*/ I2F.U32.RP R7, R10 ; /* 0x0000000a00077306 */
/* 0x000e620000209000 */
/*0160*/ IADD3 R9, RZ, -R10, RZ ; /* 0x8000000aff097210 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.NE.U32.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fca0003f45070 */
/*0180*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x002e640000001000 */
/*0190*/ IADD3 R2, R7, 0xffffffe, RZ ; /* 0x0ffffffe07027810 */
/* 0x003fcc0007ffe0ff */
/*01a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*01b0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*01c0*/ IMAD R9, R9, R3, RZ ; /* 0x0000000309097224 */
/* 0x002fc800078e02ff */
/*01d0*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fc800078e0002 */
/*01e0*/ IMAD.IADD R2, R4, 0x1, R6 ; /* 0x0000000104027824 */
/* 0x000fe400078e0206 */
/*01f0*/ IMAD.HI.U32 R3, R3, R8, RZ ; /* 0x0000000803037227 */
/* 0x000fca00078e00ff */
/*0200*/ IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03037210 */
/* 0x000fca0007ffe1ff */
/*0210*/ IMAD R3, R10, R3, R8 ; /* 0x000000030a037224 */
/* 0x000fca00078e0208 */
/*0220*/ ISETP.GE.U32.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f06070 */
/*0230*/ @P0 IMAD.IADD R3, R3, 0x1, -R10 ; /* 0x0000000103030824 */
/* 0x000fca00078e0a0a */
/*0240*/ ISETP.GE.U32.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f06070 */
/*0250*/ @P0 IADD3 R3, -R10, R3, RZ ; /* 0x000000030a030210 */
/* 0x000fe40007ffe1ff */
/*0260*/ @!P2 LOP3.LUT R3, RZ, R10, RZ, 0x33, !PT ; /* 0x0000000aff03a212 */
/* 0x000fc800078e33ff */
/*0270*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc80003f05270 */
/*0280*/ ISETP.GE.U32.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */
/* 0x000fda0000706470 */
/*0290*/ @!P0 LEA R2, R6, R5, 0x2 ; /* 0x0000000506028211 */
/* 0x000fe200078e10ff */
/*02a0*/ @!P0 LDS R3, [R8.X4] ; /* 0x0000000008038984 */
/* 0x000fe20000004800 */
/*02b0*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fc800078e000a */
/*02c0*/ @!P0 LDS R2, [R2] ; /* 0x0000000002028984 */
/* 0x000e240000000800 */
/*02d0*/ @!P0 FADD R3, R3, R2 ; /* 0x0000000203038221 */
/* 0x001fca0000000000 */
/*02e0*/ @!P0 STS [R8.X4], R3 ; /* 0x0000000308008388 */
/* 0x0001e80000004800 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x0], PT ; /* 0x000000000a007a0c */
/* 0x000fda0003f06070 */
/*0310*/ @!P0 BRA 0x140 ; /* 0xfffffe2000008947 */
/* 0x001fea000383ffff */
/*0320*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0330*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*0340*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0350*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x001fca00078e0003 */
/*0360*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel1PfS_i
.globl _Z7kernel1PfS_i
.p2align 8
.type _Z7kernel1PfS_i,@function
_Z7kernel1PfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_lt_u32 s5, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
v_lshlrev_b32_e32 v2, 2, v0
s_mov_b32 s7, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_ge_u32 s6, s5
s_mov_b32 s7, s6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_5:
s_lshl_b32 s6, s7, 1
v_add_nc_u32_e32 v4, s7, v1
s_add_i32 s2, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v3, s2, v0
v_cmp_gt_u32_e64 s2, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, 0, v3
s_and_b32 s8, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s8
s_cbranch_execz .LBB0_4
v_add_lshl_u32 v3, s7, v0, 2
ds_load_b32 v3, v3
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
ds_store_b32 v2, v3
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel1PfS_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel1PfS_i, .Lfunc_end0-_Z7kernel1PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7kernel2PfS_i
.globl _Z7kernel2PfS_i
.p2align 8
.type _Z7kernel2PfS_i,@function
_Z7kernel2PfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_mov_b32 s2, exec_lo
s_mul_i32 s6, s15, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s6, v0
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b64 s[8:9], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_b32 v1, v[1:2], off
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_lt_u32 s5, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_7
v_lshlrev_b32_e32 v1, 1, v0
s_mov_b32 s7, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_5
.p2align 6
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s2
s_lshl_b32 s7, s7, 1
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s7, s5
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_7
.LBB1_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s7, v1
v_add_nc_u32_e32 v3, s7, v2
v_add3_u32 v4, s7, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s5, v3
v_cmp_gt_u32_e64 s2, s3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, vcc_lo, s2
s_and_saveexec_b32 s2, s8
s_cbranch_execz .LBB1_4
v_lshlrev_b32_e32 v3, 2, v3
v_lshlrev_b32_e32 v2, 2, v2
ds_load_b32 v3, v3
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
ds_store_b32 v2, v3
s_branch .LBB1_4
.LBB1_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_9
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel2PfS_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7kernel2PfS_i, .Lfunc_end1-_Z7kernel2PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7kernel3PfS_i
.globl _Z7kernel3PfS_i
.p2align 8
.type _Z7kernel3PfS_i,@function
_Z7kernel3PfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB2_2
s_load_b64 s[6:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_lt_u32 s5, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_7
v_lshlrev_b32_e32 v2, 2, v0
s_branch .LBB2_5
.p2align 6
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_lt_u32 s5, 4
s_mov_b32 s5, s6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_7
.LBB2_5:
s_lshr_b32 s6, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, s6, v1
v_cmp_gt_u32_e32 vcc_lo, s6, v0
v_cmp_gt_u32_e64 s2, s3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s7, vcc_lo, s2
s_and_saveexec_b32 s2, s7
s_cbranch_execz .LBB2_4
v_add_lshl_u32 v3, s6, v0, 2
ds_load_b32 v3, v3
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
ds_store_b32 v2, v3
s_branch .LBB2_4
.LBB2_7:
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_9
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB2_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel3PfS_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7kernel3PfS_i, .Lfunc_end2-_Z7kernel3PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel1PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel1PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel2PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel2PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel3PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel3PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00019b03_00000000-6_reduction.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CPU Elapse time: "
.LC3:
.string " ms"
.LC4:
.string "predict: "
.LC5:
.string "result: "
.text
.globl _Z12varifyOutputPfS_i
.type _Z12varifyOutputPfS_i, @function
_Z12varifyOutputPfS_i:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %rsi, %rbp
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq %rdi, %rax
leaq 8192(%rdi), %rdx
movl $0x00000000, 12(%rsp)
.L4:
movss 12(%rsp), %xmm2
addss (%rax), %xmm2
movss %xmm2, 12(%rsp)
addq $4, %rax
cmpq %rax, %rdx
jne .L4
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movslq %r12d, %rax
leaq 0(%rbp,%rax,4), %rdx
movl $100, %ecx
jmp .L5
.L6:
movd %ebx, %xmm1
addss (%rax), %xmm1
movd %xmm1, %ebx
addq $4, %rax
cmpq %rax, %rdx
jne .L6
.L8:
subl $1, %ecx
je .L7
.L5:
movq %rbp, %rax
movl $0x00000000, %ebx
testl %r12d, %r12d
jg .L6
jmp .L8
.L7:
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $17, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 32(%rsp), %rcx
subq 16(%rsp), %rcx
imulq $1000000, %rcx, %rcx
addq 40(%rsp), %rcx
subq 24(%rsp), %rcx
movabsq $-6640827866535438581, %rdx
movq %rcx, %rax
imulq %rdx
leaq (%rdx,%rcx), %rax
sarq $6, %rax
sarq $63, %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L27
cmpb $0, 56(%r12)
je .L11
movzbl 67(%r12), %eax
.L12:
movsbl %al, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $9, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbp
testq %rbp, %rbp
je .L28
cmpb $0, 56(%rbp)
je .L15
movzbl 67(%rbp), %eax
.L16:
movsbl %al, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %rax, %rbp
movl $8, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movd %ebx, %xmm3
pxor %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L29
cmpb $0, 56(%rbx)
je .L19
movzbl 67(%rbx), %eax
.L20:
movsbl %al, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
call _ZSt16__throw_bad_castv@PLT
.L31:
call __stack_chk_fail@PLT
.L11:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
jmp .L12
.L28:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
call _ZSt16__throw_bad_castv@PLT
.L32:
call __stack_chk_fail@PLT
.L15:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L16
.L29:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
call _ZSt16__throw_bad_castv@PLT
.L33:
call __stack_chk_fail@PLT
.L19:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L20
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z12varifyOutputPfS_i, .-_Z12varifyOutputPfS_i
.globl _Z29__device_stub__Z7kernel1PfS_iPfS_i
.type _Z29__device_stub__Z7kernel1PfS_iPfS_i, @function
_Z29__device_stub__Z7kernel1PfS_iPfS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kernel1PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z29__device_stub__Z7kernel1PfS_iPfS_i, .-_Z29__device_stub__Z7kernel1PfS_iPfS_i
.globl _Z7kernel1PfS_i
.type _Z7kernel1PfS_i, @function
_Z7kernel1PfS_i:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7kernel1PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7kernel1PfS_i, .-_Z7kernel1PfS_i
.globl _Z29__device_stub__Z7kernel2PfS_iPfS_i
.type _Z29__device_stub__Z7kernel2PfS_iPfS_i, @function
_Z29__device_stub__Z7kernel2PfS_iPfS_i:
.LFB3697:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kernel2PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z29__device_stub__Z7kernel2PfS_iPfS_i, .-_Z29__device_stub__Z7kernel2PfS_iPfS_i
.globl _Z7kernel2PfS_i
.type _Z7kernel2PfS_i, @function
_Z7kernel2PfS_i:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7kernel2PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z7kernel2PfS_i, .-_Z7kernel2PfS_i
.globl _Z29__device_stub__Z7kernel3PfS_iPfS_i
.type _Z29__device_stub__Z7kernel3PfS_iPfS_i, @function
_Z29__device_stub__Z7kernel3PfS_iPfS_i:
.LFB3699:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L54
.L50:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kernel3PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L50
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z29__device_stub__Z7kernel3PfS_iPfS_i, .-_Z29__device_stub__Z7kernel3PfS_iPfS_i
.globl _Z7kernel3PfS_i
.type _Z7kernel3PfS_i, @function
_Z7kernel3PfS_i:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7kernel3PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z7kernel3PfS_i, .-_Z7kernel3PfS_i
.section .rodata.str1.1
.LC7:
.string "GPU Elapse time: "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $96, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $0, %edx
movl $4194292, %esi
call cudaHostAlloc@PLT
leaq 16(%rsp), %rdi
movl $0, %edx
movl $8192, %esi
call cudaHostAlloc@PLT
leaq 24(%rsp), %rdi
movl $4194292, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC6(%rip), %xmm0
.L59:
movq 8(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194292, %rax
jne .L59
movl $0, %eax
.L60:
movq 16(%rsp), %rdx
movl $0x00000000, (%rdx,%rax)
addq $4, %rax
cmpq $8192, %rax
jne .L60
leaq 40(%rsp), %rdi
call cudaStreamCreate@PLT
movq 40(%rsp), %r8
movl $1, %ecx
movl $4194292, %edx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq 40(%rsp), %r8
movl $1, %ecx
movl $8192, %edx
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpyAsync@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, %ebx
jmp .L62
.L61:
subl $1, %ebx
je .L68
.L62:
movl $512, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $2048, 64(%rsp)
movl $1, 68(%rsp)
movq 40(%rsp), %r9
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L61
movl $1048573, %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z7kernel3PfS_iPfS_i
jmp .L61
.L68:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movss 76(%rsp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $8192, %edx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1048573, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z12varifyOutputPfS_i
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L69
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z7kernel3PfS_i"
.LC10:
.string "_Z7kernel2PfS_i"
.LC11:
.string "_Z7kernel1PfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3702:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel3PfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel2PfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1PfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1083129856
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1065353216
.align 4
.LC8:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduction.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__kernel1PfS_i # -- Begin function _Z22__device_stub__kernel1PfS_i
.p2align 4, 0x90
.type _Z22__device_stub__kernel1PfS_i,@function
_Z22__device_stub__kernel1PfS_i: # @_Z22__device_stub__kernel1PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kernel1PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel1PfS_i, .Lfunc_end0-_Z22__device_stub__kernel1PfS_i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel2PfS_i # -- Begin function _Z22__device_stub__kernel2PfS_i
.p2align 4, 0x90
.type _Z22__device_stub__kernel2PfS_i,@function
_Z22__device_stub__kernel2PfS_i: # @_Z22__device_stub__kernel2PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kernel2PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__kernel2PfS_i, .Lfunc_end1-_Z22__device_stub__kernel2PfS_i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel3PfS_i # -- Begin function _Z22__device_stub__kernel3PfS_i
.p2align 4, 0x90
.type _Z22__device_stub__kernel3PfS_i,@function
_Z22__device_stub__kernel3PfS_i: # @_Z22__device_stub__kernel3PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kernel3PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z22__device_stub__kernel3PfS_i, .Lfunc_end2-_Z22__device_stub__kernel3PfS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12varifyOutputPfS_i
.LCPI3_0:
.quad 0x408f400000000000 # double 1000
.text
.globl _Z12varifyOutputPfS_i
.p2align 4, 0x90
.type _Z12varifyOutputPfS_i,@function
_Z12varifyOutputPfS_i: # @_Z12varifyOutputPfS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $48, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r14
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
addss (%rdi,%rax,4), %xmm0
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB3_1
# %bb.2:
movss %xmm0, 12(%rsp) # 4-byte Spill
xorl %r15d, %r15d
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl %ebx, %eax
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_6: # %._crit_edge
# in Loop: Header=BB3_3 Depth=1
incl %r15d
cmpl $100, %r15d
je .LBB3_7
.LBB3_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
xorps %xmm0, %xmm0
testl %ebx, %ebx
jle .LBB3_6
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB3_3 Depth=1
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_5: # %.lr.ph
# Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
addss (%r14,%rcx,4), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB3_5
jmp .LBB3_6
.LBB3_7:
movss %xmm0, 8(%rsp) # 4-byte Spill
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq 32(%rsp), %rax
subq 40(%rsp), %rcx
imulq $1000000, %rax, %rax # imm = 0xF4240
addq %rax, %rcx
movabsq $-6640827866535438581, %rdx # imm = 0xA3D70A3D70A3D70B
movq %rcx, %rax
imulq %rdx
addq %rcx, %rdx
movq %rdx, %rax
shrq $63, %rax
sarq $6, %rdx
addq %rax, %rdx
xorps %xmm0, %xmm0
cvtsi2sd %rdx, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_20
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB3_10
# %bb.9:
movzbl 67(%r14), %eax
jmp .LBB3_11
.LBB3_10:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_20
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i19
cmpb $0, 56(%rbx)
je .LBB3_14
# %bb.13:
movzbl 67(%rbx), %ecx
jmp .LBB3_15
.LBB3_14:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit22
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rax, %rbx
movl $.L.str.3, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_20
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i24
cmpb $0, 56(%rbx)
je .LBB3_18
# %bb.17:
movzbl 67(%rbx), %ecx
jmp .LBB3_19
.LBB3_18:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit27
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
addq $48, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB3_20:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z12varifyOutputPfS_i, .Lfunc_end3-_Z12varifyOutputPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x42c80000 # float 100
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
xorl %ebx, %ebx
movl $4194292, %esi # imm = 0x3FFFF4
xorl %edx, %edx
callq hipHostMalloc
movq %rsp, %rdi
movl $8192, %esi # imm = 0x2000
xorl %edx, %edx
callq hipHostMalloc
leaq 48(%rsp), %rdi
movl $4194292, %esi # imm = 0x3FFFF4
callq hipMalloc
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movq 24(%rsp), %rax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rbx,4) # imm = 0x3F800000
incq %rbx
cmpq $1048573, %rbx # imm = 0xFFFFD
jne .LBB4_1
# %bb.2: # %.preheader
movabsq $4294967808, %rbx # imm = 0x100000200
movq (%rsp), %rdi
movl $8192, %edx # imm = 0x2000
xorl %esi, %esi
callq memset@PLT
leaq 40(%rsp), %rdi
callq hipStreamCreate
movq 48(%rsp), %rdi
movq 24(%rsp), %rsi
movq 40(%rsp), %r8
movl $4194292, %edx # imm = 0x3FFFF4
movl $1, %ecx
callq hipMemcpyAsync
movq 16(%rsp), %rdi
movq (%rsp), %rsi
movq 40(%rsp), %r8
movl $8192, %edx # imm = 0x2000
movl $1, %ecx
callq hipMemcpyAsync
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100, %r12d
leaq 1536(%rbx), %r14
leaq 96(%rsp), %r13
leaq 88(%rsp), %rbp
leaq 64(%rsp), %r15
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_5: # in Loop: Header=BB4_3 Depth=1
decl %r12d
je .LBB4_6
.LBB4_3: # =>This Inner Loop Header: Depth=1
movq 40(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_5
# %bb.4: # in Loop: Header=BB4_3 Depth=1
movq 48(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl $1048573, 60(%rsp) # imm = 0xFFFFD
leaq 144(%rsp), %rax
movq %rax, 64(%rsp)
leaq 136(%rsp), %rax
movq %rax, 72(%rsp)
leaq 60(%rsp), %rax
movq %rax, 80(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z7kernel3PfS_i, %edi
movq %r15, %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_5
.LBB4_6:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB4_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB4_9
# %bb.8:
movzbl 67(%r14), %eax
jmp .LBB4_10
.LBB4_9:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
movq 16(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movq 24(%rsp), %rsi
movl $1048573, %edx # imm = 0xFFFFD
callq _Z12varifyOutputPfS_i
movq 16(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipHostFree
movq 24(%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_11:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1PfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel2PfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel3PfS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernel1PfS_i,@object # @_Z7kernel1PfS_i
.section .rodata,"a",@progbits
.globl _Z7kernel1PfS_i
.p2align 3, 0x0
_Z7kernel1PfS_i:
.quad _Z22__device_stub__kernel1PfS_i
.size _Z7kernel1PfS_i, 8
.type _Z7kernel2PfS_i,@object # @_Z7kernel2PfS_i
.globl _Z7kernel2PfS_i
.p2align 3, 0x0
_Z7kernel2PfS_i:
.quad _Z22__device_stub__kernel2PfS_i
.size _Z7kernel2PfS_i, 8
.type _Z7kernel3PfS_i,@object # @_Z7kernel3PfS_i
.globl _Z7kernel3PfS_i
.p2align 3, 0x0
_Z7kernel3PfS_i:
.quad _Z22__device_stub__kernel3PfS_i
.size _Z7kernel3PfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU Elapse time: "
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ms"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "predict: "
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "result: "
.size .L.str.3, 9
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU Elapse time: "
.size .L.str.4, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7kernel1PfS_i"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7kernel2PfS_i"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7kernel3PfS_i"
.size .L__unnamed_3, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel1PfS_i
.addrsig_sym _Z22__device_stub__kernel2PfS_i
.addrsig_sym _Z22__device_stub__kernel3PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernel1PfS_i
.addrsig_sym _Z7kernel2PfS_i
.addrsig_sym _Z7kernel3PfS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <device_functions.h>
#include <stdio.h>
#include <cstdlib>
#include <math.h>
#include<time.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#define Number 1000
#define Delta_t 0.01
__global__
void Simulate(double* Vortex_p, double* Omega_v_p, double* VortexN_p, double* Omega_vN_p, double *Sigma_p)
{
double radiika_p, t1_p, t2_p;
double t3_p, Om22P_p, ssss_p, vxx_p, vyy_p, vzz_p;
double dvxdxmov, dvxdymov, dvxdzmov;
double dvydxmov, dvydymov, dvydzmov;
double dvzdxmov, dvzdymov, dvzdzmov;
double Vxc, Vyc, Vzc, dssss_dr;
int j = 3*(threadIdx.x + blockIdx.x*blockDim.x);
if (true) {
Vxc = 1.0;
Vyc = 0;
Vzc = 0;
dvxdxmov = 0.0;
dvxdymov = 0;
dvxdzmov = 0;
dvydxmov = 0;
dvydymov = 0;
dvydzmov = 0;
dvzdxmov = 0;
dvzdymov = 0;
dvzdzmov = 0;
}
for (int i=0; i < Number; i++) {
vxx_p = Vortex_p[j] - Vortex_p[i * 3];
vyy_p = Vortex_p[j + 1] - Vortex_p[(i * 3) + 1];
vzz_p = Vortex_p[j + 2] - Vortex_p[(i * 3) + 2];
radiika_p = vxx_p*vxx_p + vyy_p*vyy_p + vzz_p*vzz_p;
t1_p = vyy_p*Omega_v_p[(i * 3) + 2] - vzz_p*Omega_v_p[(i * 3) + 1];
t2_p = vzz_p*Omega_v_p[i * 3] - vxx_p*Omega_v_p[(i * 3) + 2];
t3_p = vxx_p*Omega_v_p[(i * 3) + 1] - vyy_p*Omega_v_p[i * 3];
Om22P_p = 3.1416 / Sigma_p[i] / Sigma_p[i] / 2.0;
ssss_p = exp(-radiika_p*Om22P_p);
Vxc = Vxc + ssss_p*t1_p;
Vyc = Vyc + ssss_p*t2_p;
Vzc = Vzc + ssss_p*t3_p;
dssss_dr = (-Om22P_p)*ssss_p;
dvxdxmov = dssss_dr*vxx_p*t1_p + dvxdxmov;
dvxdymov = dssss_dr*vyy_p*t1_p + Omega_v_p[(i * 3) + 2] * ssss_p + dvxdymov;
dvxdzmov = dssss_dr*vzz_p*t1_p - Omega_v_p[(i * 3) + 1] * ssss_p + dvxdzmov;
dvydxmov = dssss_dr*vxx_p*t2_p - Omega_v_p[(i * 3) + 2] * ssss_p + dvydxmov;
dvydymov = dssss_dr*vyy_p*t2_p + dvydymov;
dvydzmov = dssss_dr*vzz_p*t2_p + Omega_v_p[i * 3] * ssss_p + dvydzmov;
dvzdxmov = dssss_dr*vxx_p*t3_p + Omega_v_p[(i * 3) + 1] * ssss_p + dvzdxmov;
dvzdymov = dssss_dr*vyy_p*t3_p - Omega_v_p[i * 3] * ssss_p + dvzdymov;
dvzdzmov = dssss_dr*vzz_p*t3_p + dvzdzmov;
}
if ( true) {
VortexN_p[j] = Vortex_p[j] + Delta_t*Vxc;
VortexN_p[j + 1] = Vortex_p[j + 1] + Delta_t*Vyc;
VortexN_p[j + 2] = Vortex_p[j + 2] + Delta_t*Vzc;
double domxdt, domydt, domzdt;
domxdt = dvxdxmov*Omega_v_p[j] + dvxdymov*Omega_v_p[j + 1] + dvxdzmov*Omega_v_p[j + 2];
domydt = dvydxmov*Omega_v_p[j] + dvydymov*Omega_v_p[j + 1] + dvydzmov*Omega_v_p[j + 2];
domzdt = dvzdxmov*Omega_v_p[j] + dvzdymov*Omega_v_p[j + 1] + dvzdzmov*Omega_v_p[j + 2];
Omega_vN_p[j] = Omega_v_p[j] + domxdt*Delta_t;
Omega_vN_p[j + 1] = Omega_v_p[j + 1] + domydt*Delta_t;
Omega_vN_p[j + 2] = Omega_v_p[j + 2] + domzdt*Delta_t;
Vxc = 0, Vyc = 0, Vzc = 0;
dvxdxmov = 0, dvxdymov = 0, dvxdzmov = 0;
dvydxmov = 0, dvydymov = 0, dvydzmov = 0;
dvzdxmov = 0, dvzdymov = 0, dvzdzmov = 0;
}
}
int main()
{
const int Ntime = 10000;
//const double Delta_t = 0.01;
const double Radius = 0.1;
//const int Number = 10;
//const double V_mean = 1.0;
double Vortex[Number][3];
double Omega_v[Number][3];
double VortexN[Number][3];
double Omega_vN[Number][3];
double *Vortex_p=new double[Number*3];
double *Omega_v_p = new double[Number * 3];
double *VortexN_p = new double[Number * 3];
double *Omega_vN_p = new double[Number * 3];
double Sigma[Number];
double *Sigma_p;
double StatisticalMoments[4] = {0.000};
double Amagni=0.0,Amagnit_old,Amagnit_new,Speed_max,Sigmas;
double Energy=0;
int Ncout=0;
FILE *fp1,*fp2;
fp1 = fopen("D:\\cudaa\\Velocities1.txt","w+");
fp2 = fopen("D:\\cudaa\\MaxValue1.txt","w+");
double Vx;
double vxx, vyy, vzz;
double *vxx_p, *vyy_p, *vzz_p;
clock_t time0,time1;
for (int ivorton = 0; ivorton < Number; ivorton++) {
Vortex[ivorton][0] = (double)rand() / (double)RAND_MAX;
Vortex[ivorton][1] = (double)rand() / (double)RAND_MAX;
Vortex[ivorton][2] = (double)rand() / (double)RAND_MAX;
Omega_v[ivorton][0] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_v[ivorton][1] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_v[ivorton][2] = (((double)rand() / (double)RAND_MAX) - 0.5);
Sigma[ivorton] = Radius;
//printf("%f",Vortex[ivorton][1]);
}
int counter = 0;
for (int h = 0; h < Number; h++) {
for (int w = 0; w < 3; w++) {
Vortex_p[counter] = Vortex[h][w];
Omega_v_p[counter] = Omega_v[h][w];
VortexN_p[counter] = VortexN[h][w];
Omega_vN_p[counter] = Omega_vN[h][w];
counter++;
}
}
time0 = clock();
double radiika;
double t1, t2, t3;
double Om22P;
double ssss,dssss_dr;
double domxdt, domydt, domzdt,Replace=0;
double Vxc, Vyc , Vzc ;
double dvxdxmov , dvxdymov , dvxdzmov ;
double dvydxmov , dvydymov , dvydzmov ;
double dvzdxmov , dvzdymov , dvzdzmov ;
double *radiika_p;
double *t1_p, *t2_p, *t3_p;
double *Om22P_p;
double *ssss_p, *dssss_dr_p;
double *domxdt_p, *domydt_p, *domzdt_p, *Replace_p ;
double *Vxc_p, *Vyc_p, *Vzc_p;
double *dvxdxmov_p, *dvxdymov_p, *dvxdzmov_p;
double *dvydxmov_p, *dvydymov_p, *dvydzmov_p;
double *dvzdxmov_p, *dvzdymov_p, *dvzdzmov_p;
vxx_p = &vxx;
cudaMalloc((void**)&Vortex_p, (Number * 3) * sizeof(double));
cudaMalloc((void**)&Omega_v_p, (Number * 3) * sizeof(double));
cudaMalloc((void**)&VortexN_p, (Number * 3) * sizeof(double));
cudaMalloc((void**)&Omega_vN_p, (Number * 3) * sizeof(double));
cudaMalloc((void**)&Sigma_p, (Number) * sizeof(double));
for (int itime = 0; itime < Ntime; itime++) {
printf("%*d %f %e %d \n ",4,itime,Amagni,Energy,Ncout);
//cudaMalloc((void**)&domzdt_p, sizeof(double));
cudaMemcpy(Vortex_p, Vortex, (Number * 3) * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(Omega_v_p, Omega_v, (Number * 3) * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(VortexN_p, VortexN, (Number * 3) * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(Omega_vN_p, Omega_vN, (Number * 3) * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(Sigma_p, Sigma, (Number) * sizeof(double), cudaMemcpyHostToDevice);
dim3 dimBlock(Number, 1);
dim3 dimGrid(Number, 1);
Simulate <<<Number/32, 32 >>> (Vortex_p,Omega_v_p, VortexN_p, Omega_vN_p,Sigma_p);
cudaMemcpy(Vortex, Vortex_p, (Number * 3) * sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(Omega_v,Omega_v_p, (Number * 3) * sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(VortexN, VortexN_p, (Number * 3) * sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(Omega_vN, Omega_vN_p, (Number * 3) * sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(Sigma, Sigma_p, (Number) * sizeof(double), cudaMemcpyDeviceToHost);
/*
for (int ivorton = 0; ivorton < Number;ivorton++) {
double Vxc=V_mean, Vyc=0.0, Vzc=0.0;
double dvxdxmov = 0.0, dvxdymov = 0.0, dvxdzmov = 0.0;
double dvydxmov = 0.0, dvydymov = 0.0, dvydzmov = 0.0;
double dvzdxmov = 0.0, dvzdymov = 0.0, dvzdzmov = 0.0;
for (int induced = 0; induced < Number; induced++) {
vxx = Vortex[ivorton][0] - Vortex[induced][0];
vyy = Vortex[ivorton][1] - Vortex[induced][1];
vzz = Vortex[ivorton][2] - Vortex[induced][2];
radiika = vxx*vxx + vyy*vyy + vzz*vzz;
t1 = vyy*Omega_v[induced][2] - vzz*Omega_v[induced][1];
t2 = vzz*Omega_v[induced][0] - vzz*Omega_v[induced][2];
t3 = vxx*Omega_v[induced][1] - vzz*Omega_v[induced][0];
Om22P = 3.1416 / Sigma[induced] / Sigma[induced] / 2.0;
ssss = exp(-radiika* Om22P);
Vxc = Vxc + ssss*t1;
Vyc = Vyc + ssss*t2;
Vzc = Vzc + ssss*t3;
dssss_dr = (-Om22P)*ssss;
dvxdxmov = dssss_dr*vxx*t1 + dvxdxmov;
dvxdymov = dssss_dr*vyy*t1 + Omega_v[induced][2]*ssss + dvxdymov;
dvxdzmov = dssss_dr*vzz*t1 - Omega_v[induced][1]*ssss + dvxdzmov;
dvydxmov = dssss_dr*vxx*t2 - Omega_v[induced][2]*ssss + dvydxmov;
dvydymov = dssss_dr*vyy*t2 + dvydymov;
dvydzmov = dssss_dr*vzz*t2 + Omega_v[induced][0]*ssss + dvydzmov;
dvzdxmov = dssss_dr*vxx*t3 + Omega_v[induced][1]*ssss + dvzdxmov;
dvzdymov = dssss_dr*vyy*t3 - Omega_v[induced][0]*ssss + dvzdymov;
dvzdzmov = dssss_dr*vzz*t3 + dvzdzmov;
}
VortexN[ivorton][0] = Vortex[ivorton][0] + Delta_t*Vxc;
VortexN[ivorton][1] = Vortex[ivorton][1] + Delta_t*Vyc;
VortexN[ivorton][2] = Vortex[ivorton][2] + Delta_t*Vzc;
// domxdt=dvxdxmov*Omega_v[ivorton][0]+dvxdymov*Omega_v[][]
domxdt = dvxdxmov*Omega_v[ivorton][0] + dvxdymov*Omega_v[ivorton][1] + dvxdzmov*Omega_v[ivorton][2];
domydt = dvydxmov*Omega_v[ivorton][0] + dvydymov*Omega_v[ivorton][1] + dvydzmov*Omega_v[ivorton][2];
domzdt = dvzdxmov*Omega_v[ivorton][0] + dvzdymov*Omega_v[ivorton][1] + dvzdzmov*Omega_v[ivorton][2];
Omega_vN[ivorton][0] = Omega_v[ivorton][0] + domxdt*Delta_t;
Omega_vN[ivorton][1]= Omega_v[ivorton][1] + domydt*Delta_t;
Omega_vN[ivorton][2] = Omega_v[ivorton][2] + domzdt*Delta_t;
}
*/
Ncout = 0;
for (int ivorton = 0; ivorton < Number; ivorton++) {
Replace = 0.0;
for (int kkk = 0; kkk < 3; kkk++) {
if (VortexN[ivorton][kkk] < 0.0) {
Replace = 1.0;
}
if (VortexN[ivorton][kkk] > 1.0) {
Replace = 1.0;
}
}
if (Replace == 1.0) {
Ncout = Ncout + 1;
VortexN[ivorton][0] = (double)rand() / (double)RAND_MAX;
VortexN[ivorton][1] = (double)rand() / (double)RAND_MAX;
VortexN[ivorton][2] = (double)rand() / (double)RAND_MAX;
Omega_vN[ivorton][0] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_vN[ivorton][1] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_vN[ivorton][2] = (((double)rand() / (double)RAND_MAX) - 0.5);
Sigma[ivorton] = Radius;
}
}
Amagni = 0.0;
for (int ivorton = 0; ivorton < Number; ivorton++) {
Vortex[ivorton][0] = VortexN[ivorton][0];
Vortex[ivorton][1] = VortexN[ivorton][1];
Vortex[ivorton][2] = VortexN[ivorton][2];
Amagnit_old = sqrt((Omega_v[ivorton][0] * Omega_v[ivorton][0]) +( Omega_v[ivorton][1] * Omega_v[ivorton][1]) +( Omega_v[ivorton][2] * Omega_v[ivorton][2]));
Omega_v[ivorton][0] = Omega_vN[ivorton][0];
Omega_v[ivorton][1] = Omega_vN[ivorton][1];
Omega_v[ivorton][2] = Omega_vN[ivorton][2];
Amagnit_new= sqrt((Omega_v[ivorton][0] * Omega_v[ivorton][0]) + (Omega_v[ivorton][1] * Omega_v[ivorton][1]) + (Omega_v[ivorton][2] * Omega_v[ivorton][2]));
Sigma[ivorton] = Sigma[ivorton] * sqrt(Amagnit_old / Amagnit_new);
if (Amagnit_new >= Amagni) {
Amagni = Amagnit_new;
Energy = (Amagnit_new*Amagnit_new)*(pow(Sigma[ivorton], 5));
Speed_max = Amagnit_new*Sigma[ivorton];
Sigmas = Sigma[ivorton];
}
}
//file write
fprintf(fp1, "%f %f %f %f %f \n", itime*Delta_t, Amagni, Energy, Speed_max, Sigmas);
Vx = 0.0;
for (int induced = 0; induced < Number; induced++) {
vxx = 0.5 - Vortex[induced][0];
vyy = 0.5 - Vortex[induced][1];
vzz = 0.5 - Vortex[induced][2];
radiika = vxx*vxx + vyy*vyy + vzz*vzz;
t1 = vyy* Omega_v[induced][2] - vzz*Omega_v[induced][1];
Om22P = 3.1416 / Sigma[induced] / Sigma[induced] / 2.0;
ssss = exp(-radiika*Om22P);
Vx = Vx + ssss*t1;
}
fprintf(fp2, "%f %f \n", itime*Delta_t, Vx);
for (int ier = 0; ier < 4; ier++) {
StatisticalMoments[ier] = StatisticalMoments[ier] +pow(Vx, ier);
}
}
cudaFree(Vortex_p);
cudaFree(Omega_v_p);
cudaFree(VortexN_p);
cudaFree(Omega_vN_p);
cudaFree(Sigma_p);
fclose(fp1);
fclose(fp2);
time1 = clock();
printf("Time taken for execution with GPU acceleration (~31blocks & 32 threads)= %f sec(s)", (double)(time1 - time0) / CLOCKS_PER_SEC);
} | .file "tmpxft_0002b42f_00000000-6_GPU_Acceleration.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z8SimulatePdS_S_S_S_PdS_S_S_S_
.type _Z35__device_stub__Z8SimulatePdS_S_S_S_PdS_S_S_S_, @function
_Z35__device_stub__Z8SimulatePdS_S_S_S_PdS_S_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8SimulatePdS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z8SimulatePdS_S_S_S_PdS_S_S_S_, .-_Z35__device_stub__Z8SimulatePdS_S_S_S_PdS_S_S_S_
.globl _Z8SimulatePdS_S_S_S_
.type _Z8SimulatePdS_S_S_S_, @function
_Z8SimulatePdS_S_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8SimulatePdS_S_S_S_PdS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8SimulatePdS_S_S_S_, .-_Z8SimulatePdS_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "w+"
.LC3:
.string "D:\\cudaa\\Velocities1.txt"
.LC4:
.string "D:\\cudaa\\MaxValue1.txt"
.LC8:
.string "%*d %f %e %d \n "
.LC11:
.string "%f %f %f %f %f \n"
.LC14:
.string "%f %f \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC18:
.string "Time taken for execution with GPU acceleration (~31blocks & 32 threads)= %f sec(s)"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -102400(%rsp), %r11
.cfi_def_cfa 11, 102456
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1800, %rsp
.cfi_def_cfa_offset 104256
movq %fs:40, %rax
movq %rax, 104184(%rsp)
xorl %eax, %eax
movl $24000, %edi
call _Znam@PLT
movq %rax, 112(%rsp)
movl $24000, %edi
call _Znam@PLT
movq %rax, 120(%rsp)
movl $24000, %edi
call _Znam@PLT
movq %rax, 128(%rsp)
movl $24000, %edi
call _Znam@PLT
movq %rax, 136(%rsp)
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, 72(%rsp)
movq %rbx, %rsi
leaq .LC4(%rip), %rdi
call fopen@PLT
movq %rax, 80(%rsp)
leaq 8176(%rsp), %rbx
movq %rbx, 88(%rsp)
leaq 32176(%rsp), %rbp
movq %rbp, 96(%rsp)
leaq 176(%rsp), %rax
movq %rax, 56(%rsp)
movq %rbp, %r13
movq %rax, %r12
movq .LC7(%rip), %r14
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
movsd %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
movsd %xmm0, 8(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
movsd %xmm0, 16(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
subsd .LC6(%rip), %xmm0
movsd %xmm0, 0(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
subsd .LC6(%rip), %xmm0
movsd %xmm0, 8(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
subsd .LC6(%rip), %xmm0
movsd %xmm0, 16(%rbp)
movq %r14, (%r12)
addq $24, %rbx
addq $24, %rbp
addq $8, %r12
cmpq %r13, %rbx
jne .L12
movl $24, %esi
movl $0, %edi
movl $0, %r8d
jmp .L13
.L45:
addl $3, %r8d
addq $24, %rdi
addq $24, %rsi
cmpl $3000, %r8d
je .L15
.L13:
movq %rdi, %rdx
movq %rdi, %rax
.L14:
movsd 8176(%rsp,%rdx), %xmm0
movq 112(%rsp), %rcx
movsd %xmm0, (%rcx,%rax)
movsd 32176(%rsp,%rdx), %xmm0
movq 120(%rsp), %rcx
movsd %xmm0, (%rcx,%rax)
movsd 56176(%rsp,%rdx), %xmm0
movq 128(%rsp), %rcx
movsd %xmm0, (%rcx,%rax)
movsd 80176(%rsp,%rdx), %xmm0
movq 136(%rsp), %rcx
movsd %xmm0, (%rcx,%rax)
addq $8, %rax
addq $8, %rdx
cmpq %rsi, %rax
jne .L14
jmp .L45
.L15:
call clock@PLT
movq %rax, %rbx
leaq 112(%rsp), %rdi
movl $24000, %esi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movl $24000, %esi
call cudaMalloc@PLT
leaq 128(%rsp), %rdi
movl $24000, %esi
call cudaMalloc@PLT
leaq 136(%rsp), %rdi
movl $24000, %esi
call cudaMalloc@PLT
leaq 144(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
movl $0, 64(%rsp)
movl $0, 68(%rsp)
movq $0x000000000, 32(%rsp)
movq $0x000000000, 16(%rsp)
leaq 80176(%rsp), %r15
movq %rbx, 104(%rsp)
jmp .L29
.L50:
movq 144(%rsp), %r8
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
movq 120(%rsp), %rsi
movq 112(%rsp), %rdi
call _Z35__device_stub__Z8SimulatePdS_S_S_S_PdS_S_S_S_
jmp .L16
.L31:
movsd .LC1(%rip), %xmm0
.L18:
addq $1, %rax
cmpq $3, %rax
je .L46
.L19:
movsd (%rbx,%rax,8), %xmm1
pxor %xmm5, %xmm5
comisd %xmm1, %xmm5
ja .L31
movsd .LC1(%rip), %xmm2
cmpnltsd %xmm1, %xmm2
andpd %xmm2, %xmm0
movsd .LC1(%rip), %xmm6
andnpd %xmm6, %xmm2
orpd %xmm2, %xmm0
jmp .L18
.L46:
ucomisd .LC1(%rip), %xmm0
jp .L20
je .L47
.L20:
addq $24, %rbx
addq $24, %r12
addq $8, %r14
cmpq %rbx, %r15
je .L33
.L17:
movl $0, %eax
pxor %xmm0, %xmm0
movq %rbx, %rbp
jmp .L19
.L47:
addl $1, %r13d
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
movsd %xmm0, 0(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
movsd %xmm0, 8(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
movsd %xmm0, 16(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
subsd .LC6(%rip), %xmm0
movsd %xmm0, (%r12)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
subsd .LC6(%rip), %xmm0
movsd %xmm0, 8(%r12)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
subsd .LC6(%rip), %xmm0
movsd %xmm0, 16(%r12)
movq .LC7(%rip), %rax
movq %rax, (%r14)
jmp .L20
.L33:
movl %r13d, 68(%rsp)
movq 8(%rsp), %r13
movq 56(%rsp), %r14
movq 96(%rsp), %rbx
movq 88(%rsp), %r12
movq $0x000000000, 16(%rsp)
movq (%rsp), %rbp
movq %r15, 24(%rsp)
movq %r14, %r15
jmp .L22
.L43:
call sqrt@PLT
jmp .L25
.L26:
addq $24, %rbp
addq $24, %r12
addq $24, %rbx
addq $24, %r13
addq $8, %r15
movq 24(%rsp), %rax
cmpq %rax, %rbp
je .L48
.L22:
movsd 0(%rbp), %xmm0
movsd %xmm0, (%r12)
movsd 8(%rbp), %xmm0
movsd %xmm0, 8(%r12)
movsd 16(%rbp), %xmm0
movsd %xmm0, 16(%r12)
movsd (%rbx), %xmm1
movsd 8(%rbx), %xmm2
movsd 16(%rbx), %xmm0
mulsd %xmm1, %xmm1
mulsd %xmm2, %xmm2
addsd %xmm2, %xmm1
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
sqrtsd %xmm0, %xmm0
movsd 0(%r13), %xmm1
movsd %xmm1, (%rbx)
movsd 8(%r13), %xmm3
movsd %xmm3, 8(%rbx)
movsd 16(%r13), %xmm2
movsd %xmm2, 16(%rbx)
mulsd %xmm1, %xmm1
mulsd %xmm3, %xmm3
addsd %xmm3, %xmm1
mulsd %xmm2, %xmm2
addsd %xmm2, %xmm1
sqrtsd %xmm1, %xmm1
movsd %xmm1, (%rsp)
movq %r15, 8(%rsp)
movq (%r15), %r14
divsd %xmm1, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L43
sqrtsd %xmm0, %xmm0
.L25:
movq %r14, %xmm7
mulsd %xmm0, %xmm7
movq %xmm7, %r14
movq 8(%rsp), %rax
movsd %xmm7, (%rax)
movsd (%rsp), %xmm7
comisd 16(%rsp), %xmm7
jb .L26
movsd .LC9(%rip), %xmm1
movq %r14, %xmm0
call pow@PLT
movsd (%rsp), %xmm6
movapd %xmm6, %xmm1
mulsd %xmm6, %xmm1
mulsd %xmm0, %xmm1
movsd %xmm1, 32(%rsp)
movq %r14, %xmm5
mulsd %xmm6, %xmm5
movsd %xmm5, 40(%rsp)
movq %r14, 48(%rsp)
movsd %xmm6, 16(%rsp)
jmp .L26
.L48:
movq %rax, %r15
pxor %xmm0, %xmm0
cvtsi2sdl 64(%rsp), %xmm0
mulsd .LC10(%rip), %xmm0
movq %xmm0, %r13
movsd 48(%rsp), %xmm4
movsd 40(%rsp), %xmm3
movsd 32(%rsp), %xmm2
movsd 16(%rsp), %xmm1
leaq .LC11(%rip), %rdx
movl $2, %esi
movq 72(%rsp), %rdi
movl $5, %eax
call __fprintf_chk@PLT
movq 56(%rsp), %rbp
movl $0, %ebx
movq $0x000000000, (%rsp)
leaq 8176(%rsp), %r12
.L28:
movsd .LC6(%rip), %xmm0
subsd (%rbx,%r12), %xmm0
movsd .LC6(%rip), %xmm2
subsd 8184(%rsp,%rbx), %xmm2
movsd .LC6(%rip), %xmm1
subsd 8192(%rsp,%rbx), %xmm1
movapd %xmm2, %xmm4
mulsd 32192(%rsp,%rbx), %xmm4
movapd %xmm1, %xmm3
mulsd 32184(%rsp,%rbx), %xmm3
subsd %xmm3, %xmm4
movsd %xmm4, 8(%rsp)
movsd 0(%rbp), %xmm3
mulsd %xmm0, %xmm0
mulsd %xmm2, %xmm2
addsd %xmm2, %xmm0
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
xorpd .LC12(%rip), %xmm0
movsd .LC13(%rip), %xmm1
divsd %xmm3, %xmm1
divsd %xmm3, %xmm1
mulsd .LC6(%rip), %xmm1
mulsd %xmm1, %xmm0
call exp@PLT
mulsd 8(%rsp), %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
addq $8, %rbp
addq $24, %rbx
cmpq $24000, %rbx
jne .L28
movapd %xmm0, %xmm1
movq %r13, %xmm0
leaq .LC14(%rip), %rdx
movl $2, %esi
movq 80(%rsp), %rdi
movl $2, %eax
call __fprintf_chk@PLT
pxor %xmm1, %xmm1
movsd (%rsp), %xmm0
call pow@PLT
movsd .LC1(%rip), %xmm1
movsd (%rsp), %xmm0
call pow@PLT
movsd .LC15(%rip), %xmm1
movsd (%rsp), %xmm0
call pow@PLT
movsd .LC16(%rip), %xmm1
movsd (%rsp), %xmm0
call pow@PLT
addl $1, 64(%rsp)
movl 64(%rsp), %eax
cmpl $10000, %eax
je .L49
.L29:
movl 68(%rsp), %r8d
movsd 32(%rsp), %xmm1
movsd 16(%rsp), %xmm0
movl 64(%rsp), %ecx
movl $4, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq 8176(%rsp), %rsi
movl $1, %ecx
movl $24000, %edx
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32176(%rsp), %rsi
movl $1, %ecx
movl $24000, %edx
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
leaq 56176(%rsp), %rsi
movl $1, %ecx
movl $24000, %edx
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $24000, %edx
movq %r15, %rsi
movq 136(%rsp), %rdi
call cudaMemcpy@PLT
leaq 176(%rsp), %rsi
movl $1, %ecx
movl $8000, %edx
movq 144(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $31, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L16:
leaq 8176(%rsp), %rdi
movl $2, %ecx
movl $24000, %edx
movq 112(%rsp), %rsi
call cudaMemcpy@PLT
leaq 32176(%rsp), %rdi
movl $2, %ecx
movl $24000, %edx
movq 120(%rsp), %rsi
call cudaMemcpy@PLT
leaq 56176(%rsp), %rbx
movl $2, %ecx
movl $24000, %edx
movq 128(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $24000, %edx
movq 136(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq 176(%rsp), %rdi
movl $2, %ecx
movl $8000, %edx
movq 144(%rsp), %rsi
call cudaMemcpy@PLT
movq %rbx, (%rsp)
movq 56(%rsp), %r14
movq %r15, %r12
movl $0, %eax
movq %r15, 8(%rsp)
movl %eax, %r13d
jmp .L17
.L49:
movq 104(%rsp), %rbx
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 144(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call fclose@PLT
movq 80(%rsp), %rdi
call fclose@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC17(%rip), %xmm0
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 104184(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $104200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z8SimulatePdS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z8SimulatePdS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC5:
.long -4194304
.long 1105199103
.align 8
.LC6:
.long 0
.long 1071644672
.align 8
.LC7:
.long -1717986918
.long 1069128089
.align 8
.LC9:
.long 0
.long 1075052544
.align 8
.LC10:
.long 1202590843
.long 1065646817
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC12:
.long 0
.long -2147483648
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC13:
.long 776530087
.long 1074340351
.align 8
.LC15:
.long 0
.long 1073741824
.align 8
.LC16:
.long 0
.long 1074266112
.align 8
.LC17:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <device_functions.h>
#include <stdio.h>
#include <cstdlib>
#include <math.h>
#include<time.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#define Number 1000
#define Delta_t 0.01
__global__
void Simulate(double* Vortex_p, double* Omega_v_p, double* VortexN_p, double* Omega_vN_p, double *Sigma_p)
{
double radiika_p, t1_p, t2_p;
double t3_p, Om22P_p, ssss_p, vxx_p, vyy_p, vzz_p;
double dvxdxmov, dvxdymov, dvxdzmov;
double dvydxmov, dvydymov, dvydzmov;
double dvzdxmov, dvzdymov, dvzdzmov;
double Vxc, Vyc, Vzc, dssss_dr;
int j = 3*(threadIdx.x + blockIdx.x*blockDim.x);
if (true) {
Vxc = 1.0;
Vyc = 0;
Vzc = 0;
dvxdxmov = 0.0;
dvxdymov = 0;
dvxdzmov = 0;
dvydxmov = 0;
dvydymov = 0;
dvydzmov = 0;
dvzdxmov = 0;
dvzdymov = 0;
dvzdzmov = 0;
}
for (int i=0; i < Number; i++) {
vxx_p = Vortex_p[j] - Vortex_p[i * 3];
vyy_p = Vortex_p[j + 1] - Vortex_p[(i * 3) + 1];
vzz_p = Vortex_p[j + 2] - Vortex_p[(i * 3) + 2];
radiika_p = vxx_p*vxx_p + vyy_p*vyy_p + vzz_p*vzz_p;
t1_p = vyy_p*Omega_v_p[(i * 3) + 2] - vzz_p*Omega_v_p[(i * 3) + 1];
t2_p = vzz_p*Omega_v_p[i * 3] - vxx_p*Omega_v_p[(i * 3) + 2];
t3_p = vxx_p*Omega_v_p[(i * 3) + 1] - vyy_p*Omega_v_p[i * 3];
Om22P_p = 3.1416 / Sigma_p[i] / Sigma_p[i] / 2.0;
ssss_p = exp(-radiika_p*Om22P_p);
Vxc = Vxc + ssss_p*t1_p;
Vyc = Vyc + ssss_p*t2_p;
Vzc = Vzc + ssss_p*t3_p;
dssss_dr = (-Om22P_p)*ssss_p;
dvxdxmov = dssss_dr*vxx_p*t1_p + dvxdxmov;
dvxdymov = dssss_dr*vyy_p*t1_p + Omega_v_p[(i * 3) + 2] * ssss_p + dvxdymov;
dvxdzmov = dssss_dr*vzz_p*t1_p - Omega_v_p[(i * 3) + 1] * ssss_p + dvxdzmov;
dvydxmov = dssss_dr*vxx_p*t2_p - Omega_v_p[(i * 3) + 2] * ssss_p + dvydxmov;
dvydymov = dssss_dr*vyy_p*t2_p + dvydymov;
dvydzmov = dssss_dr*vzz_p*t2_p + Omega_v_p[i * 3] * ssss_p + dvydzmov;
dvzdxmov = dssss_dr*vxx_p*t3_p + Omega_v_p[(i * 3) + 1] * ssss_p + dvzdxmov;
dvzdymov = dssss_dr*vyy_p*t3_p - Omega_v_p[i * 3] * ssss_p + dvzdymov;
dvzdzmov = dssss_dr*vzz_p*t3_p + dvzdzmov;
}
if ( true) {
VortexN_p[j] = Vortex_p[j] + Delta_t*Vxc;
VortexN_p[j + 1] = Vortex_p[j + 1] + Delta_t*Vyc;
VortexN_p[j + 2] = Vortex_p[j + 2] + Delta_t*Vzc;
double domxdt, domydt, domzdt;
domxdt = dvxdxmov*Omega_v_p[j] + dvxdymov*Omega_v_p[j + 1] + dvxdzmov*Omega_v_p[j + 2];
domydt = dvydxmov*Omega_v_p[j] + dvydymov*Omega_v_p[j + 1] + dvydzmov*Omega_v_p[j + 2];
domzdt = dvzdxmov*Omega_v_p[j] + dvzdymov*Omega_v_p[j + 1] + dvzdzmov*Omega_v_p[j + 2];
Omega_vN_p[j] = Omega_v_p[j] + domxdt*Delta_t;
Omega_vN_p[j + 1] = Omega_v_p[j + 1] + domydt*Delta_t;
Omega_vN_p[j + 2] = Omega_v_p[j + 2] + domzdt*Delta_t;
Vxc = 0, Vyc = 0, Vzc = 0;
dvxdxmov = 0, dvxdymov = 0, dvxdzmov = 0;
dvydxmov = 0, dvydymov = 0, dvydzmov = 0;
dvzdxmov = 0, dvzdymov = 0, dvzdzmov = 0;
}
}
int main()
{
const int Ntime = 10000;
//const double Delta_t = 0.01;
const double Radius = 0.1;
//const int Number = 10;
//const double V_mean = 1.0;
double Vortex[Number][3];
double Omega_v[Number][3];
double VortexN[Number][3];
double Omega_vN[Number][3];
double *Vortex_p=new double[Number*3];
double *Omega_v_p = new double[Number * 3];
double *VortexN_p = new double[Number * 3];
double *Omega_vN_p = new double[Number * 3];
double Sigma[Number];
double *Sigma_p;
double StatisticalMoments[4] = {0.000};
double Amagni=0.0,Amagnit_old,Amagnit_new,Speed_max,Sigmas;
double Energy=0;
int Ncout=0;
FILE *fp1,*fp2;
fp1 = fopen("D:\\cudaa\\Velocities1.txt","w+");
fp2 = fopen("D:\\cudaa\\MaxValue1.txt","w+");
double Vx;
double vxx, vyy, vzz;
double *vxx_p, *vyy_p, *vzz_p;
clock_t time0,time1;
for (int ivorton = 0; ivorton < Number; ivorton++) {
Vortex[ivorton][0] = (double)rand() / (double)RAND_MAX;
Vortex[ivorton][1] = (double)rand() / (double)RAND_MAX;
Vortex[ivorton][2] = (double)rand() / (double)RAND_MAX;
Omega_v[ivorton][0] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_v[ivorton][1] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_v[ivorton][2] = (((double)rand() / (double)RAND_MAX) - 0.5);
Sigma[ivorton] = Radius;
//printf("%f",Vortex[ivorton][1]);
}
int counter = 0;
for (int h = 0; h < Number; h++) {
for (int w = 0; w < 3; w++) {
Vortex_p[counter] = Vortex[h][w];
Omega_v_p[counter] = Omega_v[h][w];
VortexN_p[counter] = VortexN[h][w];
Omega_vN_p[counter] = Omega_vN[h][w];
counter++;
}
}
time0 = clock();
double radiika;
double t1, t2, t3;
double Om22P;
double ssss,dssss_dr;
double domxdt, domydt, domzdt,Replace=0;
double Vxc, Vyc , Vzc ;
double dvxdxmov , dvxdymov , dvxdzmov ;
double dvydxmov , dvydymov , dvydzmov ;
double dvzdxmov , dvzdymov , dvzdzmov ;
double *radiika_p;
double *t1_p, *t2_p, *t3_p;
double *Om22P_p;
double *ssss_p, *dssss_dr_p;
double *domxdt_p, *domydt_p, *domzdt_p, *Replace_p ;
double *Vxc_p, *Vyc_p, *Vzc_p;
double *dvxdxmov_p, *dvxdymov_p, *dvxdzmov_p;
double *dvydxmov_p, *dvydymov_p, *dvydzmov_p;
double *dvzdxmov_p, *dvzdymov_p, *dvzdzmov_p;
vxx_p = &vxx;
cudaMalloc((void**)&Vortex_p, (Number * 3) * sizeof(double));
cudaMalloc((void**)&Omega_v_p, (Number * 3) * sizeof(double));
cudaMalloc((void**)&VortexN_p, (Number * 3) * sizeof(double));
cudaMalloc((void**)&Omega_vN_p, (Number * 3) * sizeof(double));
cudaMalloc((void**)&Sigma_p, (Number) * sizeof(double));
for (int itime = 0; itime < Ntime; itime++) {
printf("%*d %f %e %d \n ",4,itime,Amagni,Energy,Ncout);
//cudaMalloc((void**)&domzdt_p, sizeof(double));
cudaMemcpy(Vortex_p, Vortex, (Number * 3) * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(Omega_v_p, Omega_v, (Number * 3) * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(VortexN_p, VortexN, (Number * 3) * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(Omega_vN_p, Omega_vN, (Number * 3) * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(Sigma_p, Sigma, (Number) * sizeof(double), cudaMemcpyHostToDevice);
dim3 dimBlock(Number, 1);
dim3 dimGrid(Number, 1);
Simulate <<<Number/32, 32 >>> (Vortex_p,Omega_v_p, VortexN_p, Omega_vN_p,Sigma_p);
cudaMemcpy(Vortex, Vortex_p, (Number * 3) * sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(Omega_v,Omega_v_p, (Number * 3) * sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(VortexN, VortexN_p, (Number * 3) * sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(Omega_vN, Omega_vN_p, (Number * 3) * sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(Sigma, Sigma_p, (Number) * sizeof(double), cudaMemcpyDeviceToHost);
/*
for (int ivorton = 0; ivorton < Number;ivorton++) {
double Vxc=V_mean, Vyc=0.0, Vzc=0.0;
double dvxdxmov = 0.0, dvxdymov = 0.0, dvxdzmov = 0.0;
double dvydxmov = 0.0, dvydymov = 0.0, dvydzmov = 0.0;
double dvzdxmov = 0.0, dvzdymov = 0.0, dvzdzmov = 0.0;
for (int induced = 0; induced < Number; induced++) {
vxx = Vortex[ivorton][0] - Vortex[induced][0];
vyy = Vortex[ivorton][1] - Vortex[induced][1];
vzz = Vortex[ivorton][2] - Vortex[induced][2];
radiika = vxx*vxx + vyy*vyy + vzz*vzz;
t1 = vyy*Omega_v[induced][2] - vzz*Omega_v[induced][1];
t2 = vzz*Omega_v[induced][0] - vzz*Omega_v[induced][2];
t3 = vxx*Omega_v[induced][1] - vzz*Omega_v[induced][0];
Om22P = 3.1416 / Sigma[induced] / Sigma[induced] / 2.0;
ssss = exp(-radiika* Om22P);
Vxc = Vxc + ssss*t1;
Vyc = Vyc + ssss*t2;
Vzc = Vzc + ssss*t3;
dssss_dr = (-Om22P)*ssss;
dvxdxmov = dssss_dr*vxx*t1 + dvxdxmov;
dvxdymov = dssss_dr*vyy*t1 + Omega_v[induced][2]*ssss + dvxdymov;
dvxdzmov = dssss_dr*vzz*t1 - Omega_v[induced][1]*ssss + dvxdzmov;
dvydxmov = dssss_dr*vxx*t2 - Omega_v[induced][2]*ssss + dvydxmov;
dvydymov = dssss_dr*vyy*t2 + dvydymov;
dvydzmov = dssss_dr*vzz*t2 + Omega_v[induced][0]*ssss + dvydzmov;
dvzdxmov = dssss_dr*vxx*t3 + Omega_v[induced][1]*ssss + dvzdxmov;
dvzdymov = dssss_dr*vyy*t3 - Omega_v[induced][0]*ssss + dvzdymov;
dvzdzmov = dssss_dr*vzz*t3 + dvzdzmov;
}
VortexN[ivorton][0] = Vortex[ivorton][0] + Delta_t*Vxc;
VortexN[ivorton][1] = Vortex[ivorton][1] + Delta_t*Vyc;
VortexN[ivorton][2] = Vortex[ivorton][2] + Delta_t*Vzc;
// domxdt=dvxdxmov*Omega_v[ivorton][0]+dvxdymov*Omega_v[][]
domxdt = dvxdxmov*Omega_v[ivorton][0] + dvxdymov*Omega_v[ivorton][1] + dvxdzmov*Omega_v[ivorton][2];
domydt = dvydxmov*Omega_v[ivorton][0] + dvydymov*Omega_v[ivorton][1] + dvydzmov*Omega_v[ivorton][2];
domzdt = dvzdxmov*Omega_v[ivorton][0] + dvzdymov*Omega_v[ivorton][1] + dvzdzmov*Omega_v[ivorton][2];
Omega_vN[ivorton][0] = Omega_v[ivorton][0] + domxdt*Delta_t;
Omega_vN[ivorton][1]= Omega_v[ivorton][1] + domydt*Delta_t;
Omega_vN[ivorton][2] = Omega_v[ivorton][2] + domzdt*Delta_t;
}
*/
Ncout = 0;
for (int ivorton = 0; ivorton < Number; ivorton++) {
Replace = 0.0;
for (int kkk = 0; kkk < 3; kkk++) {
if (VortexN[ivorton][kkk] < 0.0) {
Replace = 1.0;
}
if (VortexN[ivorton][kkk] > 1.0) {
Replace = 1.0;
}
}
if (Replace == 1.0) {
Ncout = Ncout + 1;
VortexN[ivorton][0] = (double)rand() / (double)RAND_MAX;
VortexN[ivorton][1] = (double)rand() / (double)RAND_MAX;
VortexN[ivorton][2] = (double)rand() / (double)RAND_MAX;
Omega_vN[ivorton][0] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_vN[ivorton][1] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_vN[ivorton][2] = (((double)rand() / (double)RAND_MAX) - 0.5);
Sigma[ivorton] = Radius;
}
}
Amagni = 0.0;
for (int ivorton = 0; ivorton < Number; ivorton++) {
Vortex[ivorton][0] = VortexN[ivorton][0];
Vortex[ivorton][1] = VortexN[ivorton][1];
Vortex[ivorton][2] = VortexN[ivorton][2];
Amagnit_old = sqrt((Omega_v[ivorton][0] * Omega_v[ivorton][0]) +( Omega_v[ivorton][1] * Omega_v[ivorton][1]) +( Omega_v[ivorton][2] * Omega_v[ivorton][2]));
Omega_v[ivorton][0] = Omega_vN[ivorton][0];
Omega_v[ivorton][1] = Omega_vN[ivorton][1];
Omega_v[ivorton][2] = Omega_vN[ivorton][2];
Amagnit_new= sqrt((Omega_v[ivorton][0] * Omega_v[ivorton][0]) + (Omega_v[ivorton][1] * Omega_v[ivorton][1]) + (Omega_v[ivorton][2] * Omega_v[ivorton][2]));
Sigma[ivorton] = Sigma[ivorton] * sqrt(Amagnit_old / Amagnit_new);
if (Amagnit_new >= Amagni) {
Amagni = Amagnit_new;
Energy = (Amagnit_new*Amagnit_new)*(pow(Sigma[ivorton], 5));
Speed_max = Amagnit_new*Sigma[ivorton];
Sigmas = Sigma[ivorton];
}
}
//file write
fprintf(fp1, "%f %f %f %f %f \n", itime*Delta_t, Amagni, Energy, Speed_max, Sigmas);
Vx = 0.0;
for (int induced = 0; induced < Number; induced++) {
vxx = 0.5 - Vortex[induced][0];
vyy = 0.5 - Vortex[induced][1];
vzz = 0.5 - Vortex[induced][2];
radiika = vxx*vxx + vyy*vyy + vzz*vzz;
t1 = vyy* Omega_v[induced][2] - vzz*Omega_v[induced][1];
Om22P = 3.1416 / Sigma[induced] / Sigma[induced] / 2.0;
ssss = exp(-radiika*Om22P);
Vx = Vx + ssss*t1;
}
fprintf(fp2, "%f %f \n", itime*Delta_t, Vx);
for (int ier = 0; ier < 4; ier++) {
StatisticalMoments[ier] = StatisticalMoments[ier] +pow(Vx, ier);
}
}
cudaFree(Vortex_p);
cudaFree(Omega_v_p);
cudaFree(VortexN_p);
cudaFree(Omega_vN_p);
cudaFree(Sigma_p);
fclose(fp1);
fclose(fp2);
time1 = clock();
printf("Time taken for execution with GPU acceleration (~31blocks & 32 threads)= %f sec(s)", (double)(time1 - time0) / CLOCKS_PER_SEC);
} | #include "hip/hip_runtime.h"
#include <hip/device_functions.h>
#include <stdio.h>
#include <cstdlib>
#include <math.h>
#include<time.h>
#include <hip/hip_runtime_api.h>
#define Number 1000
#define Delta_t 0.01
__global__
void Simulate(double* Vortex_p, double* Omega_v_p, double* VortexN_p, double* Omega_vN_p, double *Sigma_p)
{
double radiika_p, t1_p, t2_p;
double t3_p, Om22P_p, ssss_p, vxx_p, vyy_p, vzz_p;
double dvxdxmov, dvxdymov, dvxdzmov;
double dvydxmov, dvydymov, dvydzmov;
double dvzdxmov, dvzdymov, dvzdzmov;
double Vxc, Vyc, Vzc, dssss_dr;
int j = 3*(threadIdx.x + blockIdx.x*blockDim.x);
if (true) {
Vxc = 1.0;
Vyc = 0;
Vzc = 0;
dvxdxmov = 0.0;
dvxdymov = 0;
dvxdzmov = 0;
dvydxmov = 0;
dvydymov = 0;
dvydzmov = 0;
dvzdxmov = 0;
dvzdymov = 0;
dvzdzmov = 0;
}
for (int i=0; i < Number; i++) {
vxx_p = Vortex_p[j] - Vortex_p[i * 3];
vyy_p = Vortex_p[j + 1] - Vortex_p[(i * 3) + 1];
vzz_p = Vortex_p[j + 2] - Vortex_p[(i * 3) + 2];
radiika_p = vxx_p*vxx_p + vyy_p*vyy_p + vzz_p*vzz_p;
t1_p = vyy_p*Omega_v_p[(i * 3) + 2] - vzz_p*Omega_v_p[(i * 3) + 1];
t2_p = vzz_p*Omega_v_p[i * 3] - vxx_p*Omega_v_p[(i * 3) + 2];
t3_p = vxx_p*Omega_v_p[(i * 3) + 1] - vyy_p*Omega_v_p[i * 3];
Om22P_p = 3.1416 / Sigma_p[i] / Sigma_p[i] / 2.0;
ssss_p = exp(-radiika_p*Om22P_p);
Vxc = Vxc + ssss_p*t1_p;
Vyc = Vyc + ssss_p*t2_p;
Vzc = Vzc + ssss_p*t3_p;
dssss_dr = (-Om22P_p)*ssss_p;
dvxdxmov = dssss_dr*vxx_p*t1_p + dvxdxmov;
dvxdymov = dssss_dr*vyy_p*t1_p + Omega_v_p[(i * 3) + 2] * ssss_p + dvxdymov;
dvxdzmov = dssss_dr*vzz_p*t1_p - Omega_v_p[(i * 3) + 1] * ssss_p + dvxdzmov;
dvydxmov = dssss_dr*vxx_p*t2_p - Omega_v_p[(i * 3) + 2] * ssss_p + dvydxmov;
dvydymov = dssss_dr*vyy_p*t2_p + dvydymov;
dvydzmov = dssss_dr*vzz_p*t2_p + Omega_v_p[i * 3] * ssss_p + dvydzmov;
dvzdxmov = dssss_dr*vxx_p*t3_p + Omega_v_p[(i * 3) + 1] * ssss_p + dvzdxmov;
dvzdymov = dssss_dr*vyy_p*t3_p - Omega_v_p[i * 3] * ssss_p + dvzdymov;
dvzdzmov = dssss_dr*vzz_p*t3_p + dvzdzmov;
}
if ( true) {
VortexN_p[j] = Vortex_p[j] + Delta_t*Vxc;
VortexN_p[j + 1] = Vortex_p[j + 1] + Delta_t*Vyc;
VortexN_p[j + 2] = Vortex_p[j + 2] + Delta_t*Vzc;
double domxdt, domydt, domzdt;
domxdt = dvxdxmov*Omega_v_p[j] + dvxdymov*Omega_v_p[j + 1] + dvxdzmov*Omega_v_p[j + 2];
domydt = dvydxmov*Omega_v_p[j] + dvydymov*Omega_v_p[j + 1] + dvydzmov*Omega_v_p[j + 2];
domzdt = dvzdxmov*Omega_v_p[j] + dvzdymov*Omega_v_p[j + 1] + dvzdzmov*Omega_v_p[j + 2];
Omega_vN_p[j] = Omega_v_p[j] + domxdt*Delta_t;
Omega_vN_p[j + 1] = Omega_v_p[j + 1] + domydt*Delta_t;
Omega_vN_p[j + 2] = Omega_v_p[j + 2] + domzdt*Delta_t;
Vxc = 0, Vyc = 0, Vzc = 0;
dvxdxmov = 0, dvxdymov = 0, dvxdzmov = 0;
dvydxmov = 0, dvydymov = 0, dvydzmov = 0;
dvzdxmov = 0, dvzdymov = 0, dvzdzmov = 0;
}
}
int main()
{
const int Ntime = 10000;
//const double Delta_t = 0.01;
const double Radius = 0.1;
//const int Number = 10;
//const double V_mean = 1.0;
double Vortex[Number][3];
double Omega_v[Number][3];
double VortexN[Number][3];
double Omega_vN[Number][3];
double *Vortex_p=new double[Number*3];
double *Omega_v_p = new double[Number * 3];
double *VortexN_p = new double[Number * 3];
double *Omega_vN_p = new double[Number * 3];
double Sigma[Number];
double *Sigma_p;
double StatisticalMoments[4] = {0.000};
double Amagni=0.0,Amagnit_old,Amagnit_new,Speed_max,Sigmas;
double Energy=0;
int Ncout=0;
FILE *fp1,*fp2;
fp1 = fopen("D:\\cudaa\\Velocities1.txt","w+");
fp2 = fopen("D:\\cudaa\\MaxValue1.txt","w+");
double Vx;
double vxx, vyy, vzz;
double *vxx_p, *vyy_p, *vzz_p;
clock_t time0,time1;
for (int ivorton = 0; ivorton < Number; ivorton++) {
Vortex[ivorton][0] = (double)rand() / (double)RAND_MAX;
Vortex[ivorton][1] = (double)rand() / (double)RAND_MAX;
Vortex[ivorton][2] = (double)rand() / (double)RAND_MAX;
Omega_v[ivorton][0] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_v[ivorton][1] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_v[ivorton][2] = (((double)rand() / (double)RAND_MAX) - 0.5);
Sigma[ivorton] = Radius;
//printf("%f",Vortex[ivorton][1]);
}
int counter = 0;
for (int h = 0; h < Number; h++) {
for (int w = 0; w < 3; w++) {
Vortex_p[counter] = Vortex[h][w];
Omega_v_p[counter] = Omega_v[h][w];
VortexN_p[counter] = VortexN[h][w];
Omega_vN_p[counter] = Omega_vN[h][w];
counter++;
}
}
time0 = clock();
double radiika;
double t1, t2, t3;
double Om22P;
double ssss,dssss_dr;
double domxdt, domydt, domzdt,Replace=0;
double Vxc, Vyc , Vzc ;
double dvxdxmov , dvxdymov , dvxdzmov ;
double dvydxmov , dvydymov , dvydzmov ;
double dvzdxmov , dvzdymov , dvzdzmov ;
double *radiika_p;
double *t1_p, *t2_p, *t3_p;
double *Om22P_p;
double *ssss_p, *dssss_dr_p;
double *domxdt_p, *domydt_p, *domzdt_p, *Replace_p ;
double *Vxc_p, *Vyc_p, *Vzc_p;
double *dvxdxmov_p, *dvxdymov_p, *dvxdzmov_p;
double *dvydxmov_p, *dvydymov_p, *dvydzmov_p;
double *dvzdxmov_p, *dvzdymov_p, *dvzdzmov_p;
vxx_p = &vxx;
hipMalloc((void**)&Vortex_p, (Number * 3) * sizeof(double));
hipMalloc((void**)&Omega_v_p, (Number * 3) * sizeof(double));
hipMalloc((void**)&VortexN_p, (Number * 3) * sizeof(double));
hipMalloc((void**)&Omega_vN_p, (Number * 3) * sizeof(double));
hipMalloc((void**)&Sigma_p, (Number) * sizeof(double));
for (int itime = 0; itime < Ntime; itime++) {
printf("%*d %f %e %d \n ",4,itime,Amagni,Energy,Ncout);
//cudaMalloc((void**)&domzdt_p, sizeof(double));
hipMemcpy(Vortex_p, Vortex, (Number * 3) * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(Omega_v_p, Omega_v, (Number * 3) * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(VortexN_p, VortexN, (Number * 3) * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(Omega_vN_p, Omega_vN, (Number * 3) * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(Sigma_p, Sigma, (Number) * sizeof(double), hipMemcpyHostToDevice);
dim3 dimBlock(Number, 1);
dim3 dimGrid(Number, 1);
Simulate <<<Number/32, 32 >>> (Vortex_p,Omega_v_p, VortexN_p, Omega_vN_p,Sigma_p);
hipMemcpy(Vortex, Vortex_p, (Number * 3) * sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(Omega_v,Omega_v_p, (Number * 3) * sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(VortexN, VortexN_p, (Number * 3) * sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(Omega_vN, Omega_vN_p, (Number * 3) * sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(Sigma, Sigma_p, (Number) * sizeof(double), hipMemcpyDeviceToHost);
/*
for (int ivorton = 0; ivorton < Number;ivorton++) {
double Vxc=V_mean, Vyc=0.0, Vzc=0.0;
double dvxdxmov = 0.0, dvxdymov = 0.0, dvxdzmov = 0.0;
double dvydxmov = 0.0, dvydymov = 0.0, dvydzmov = 0.0;
double dvzdxmov = 0.0, dvzdymov = 0.0, dvzdzmov = 0.0;
for (int induced = 0; induced < Number; induced++) {
vxx = Vortex[ivorton][0] - Vortex[induced][0];
vyy = Vortex[ivorton][1] - Vortex[induced][1];
vzz = Vortex[ivorton][2] - Vortex[induced][2];
radiika = vxx*vxx + vyy*vyy + vzz*vzz;
t1 = vyy*Omega_v[induced][2] - vzz*Omega_v[induced][1];
t2 = vzz*Omega_v[induced][0] - vzz*Omega_v[induced][2];
t3 = vxx*Omega_v[induced][1] - vzz*Omega_v[induced][0];
Om22P = 3.1416 / Sigma[induced] / Sigma[induced] / 2.0;
ssss = exp(-radiika* Om22P);
Vxc = Vxc + ssss*t1;
Vyc = Vyc + ssss*t2;
Vzc = Vzc + ssss*t3;
dssss_dr = (-Om22P)*ssss;
dvxdxmov = dssss_dr*vxx*t1 + dvxdxmov;
dvxdymov = dssss_dr*vyy*t1 + Omega_v[induced][2]*ssss + dvxdymov;
dvxdzmov = dssss_dr*vzz*t1 - Omega_v[induced][1]*ssss + dvxdzmov;
dvydxmov = dssss_dr*vxx*t2 - Omega_v[induced][2]*ssss + dvydxmov;
dvydymov = dssss_dr*vyy*t2 + dvydymov;
dvydzmov = dssss_dr*vzz*t2 + Omega_v[induced][0]*ssss + dvydzmov;
dvzdxmov = dssss_dr*vxx*t3 + Omega_v[induced][1]*ssss + dvzdxmov;
dvzdymov = dssss_dr*vyy*t3 - Omega_v[induced][0]*ssss + dvzdymov;
dvzdzmov = dssss_dr*vzz*t3 + dvzdzmov;
}
VortexN[ivorton][0] = Vortex[ivorton][0] + Delta_t*Vxc;
VortexN[ivorton][1] = Vortex[ivorton][1] + Delta_t*Vyc;
VortexN[ivorton][2] = Vortex[ivorton][2] + Delta_t*Vzc;
// domxdt=dvxdxmov*Omega_v[ivorton][0]+dvxdymov*Omega_v[][]
domxdt = dvxdxmov*Omega_v[ivorton][0] + dvxdymov*Omega_v[ivorton][1] + dvxdzmov*Omega_v[ivorton][2];
domydt = dvydxmov*Omega_v[ivorton][0] + dvydymov*Omega_v[ivorton][1] + dvydzmov*Omega_v[ivorton][2];
domzdt = dvzdxmov*Omega_v[ivorton][0] + dvzdymov*Omega_v[ivorton][1] + dvzdzmov*Omega_v[ivorton][2];
Omega_vN[ivorton][0] = Omega_v[ivorton][0] + domxdt*Delta_t;
Omega_vN[ivorton][1]= Omega_v[ivorton][1] + domydt*Delta_t;
Omega_vN[ivorton][2] = Omega_v[ivorton][2] + domzdt*Delta_t;
}
*/
Ncout = 0;
for (int ivorton = 0; ivorton < Number; ivorton++) {
Replace = 0.0;
for (int kkk = 0; kkk < 3; kkk++) {
if (VortexN[ivorton][kkk] < 0.0) {
Replace = 1.0;
}
if (VortexN[ivorton][kkk] > 1.0) {
Replace = 1.0;
}
}
if (Replace == 1.0) {
Ncout = Ncout + 1;
VortexN[ivorton][0] = (double)rand() / (double)RAND_MAX;
VortexN[ivorton][1] = (double)rand() / (double)RAND_MAX;
VortexN[ivorton][2] = (double)rand() / (double)RAND_MAX;
Omega_vN[ivorton][0] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_vN[ivorton][1] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_vN[ivorton][2] = (((double)rand() / (double)RAND_MAX) - 0.5);
Sigma[ivorton] = Radius;
}
}
Amagni = 0.0;
for (int ivorton = 0; ivorton < Number; ivorton++) {
Vortex[ivorton][0] = VortexN[ivorton][0];
Vortex[ivorton][1] = VortexN[ivorton][1];
Vortex[ivorton][2] = VortexN[ivorton][2];
Amagnit_old = sqrt((Omega_v[ivorton][0] * Omega_v[ivorton][0]) +( Omega_v[ivorton][1] * Omega_v[ivorton][1]) +( Omega_v[ivorton][2] * Omega_v[ivorton][2]));
Omega_v[ivorton][0] = Omega_vN[ivorton][0];
Omega_v[ivorton][1] = Omega_vN[ivorton][1];
Omega_v[ivorton][2] = Omega_vN[ivorton][2];
Amagnit_new= sqrt((Omega_v[ivorton][0] * Omega_v[ivorton][0]) + (Omega_v[ivorton][1] * Omega_v[ivorton][1]) + (Omega_v[ivorton][2] * Omega_v[ivorton][2]));
Sigma[ivorton] = Sigma[ivorton] * sqrt(Amagnit_old / Amagnit_new);
if (Amagnit_new >= Amagni) {
Amagni = Amagnit_new;
Energy = (Amagnit_new*Amagnit_new)*(pow(Sigma[ivorton], 5));
Speed_max = Amagnit_new*Sigma[ivorton];
Sigmas = Sigma[ivorton];
}
}
//file write
fprintf(fp1, "%f %f %f %f %f \n", itime*Delta_t, Amagni, Energy, Speed_max, Sigmas);
Vx = 0.0;
for (int induced = 0; induced < Number; induced++) {
vxx = 0.5 - Vortex[induced][0];
vyy = 0.5 - Vortex[induced][1];
vzz = 0.5 - Vortex[induced][2];
radiika = vxx*vxx + vyy*vyy + vzz*vzz;
t1 = vyy* Omega_v[induced][2] - vzz*Omega_v[induced][1];
Om22P = 3.1416 / Sigma[induced] / Sigma[induced] / 2.0;
ssss = exp(-radiika*Om22P);
Vx = Vx + ssss*t1;
}
fprintf(fp2, "%f %f \n", itime*Delta_t, Vx);
for (int ier = 0; ier < 4; ier++) {
StatisticalMoments[ier] = StatisticalMoments[ier] +pow(Vx, ier);
}
}
hipFree(Vortex_p);
hipFree(Omega_v_p);
hipFree(VortexN_p);
hipFree(Omega_vN_p);
hipFree(Sigma_p);
fclose(fp1);
fclose(fp2);
time1 = clock();
printf("Time taken for execution with GPU acceleration (~31blocks & 32 threads)= %f sec(s)", (double)(time1 - time0) / CLOCKS_PER_SEC);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <hip/device_functions.h>
#include <stdio.h>
#include <cstdlib>
#include <math.h>
#include<time.h>
#include <hip/hip_runtime_api.h>
#define Number 1000
#define Delta_t 0.01
__global__
void Simulate(double* Vortex_p, double* Omega_v_p, double* VortexN_p, double* Omega_vN_p, double *Sigma_p)
{
double radiika_p, t1_p, t2_p;
double t3_p, Om22P_p, ssss_p, vxx_p, vyy_p, vzz_p;
double dvxdxmov, dvxdymov, dvxdzmov;
double dvydxmov, dvydymov, dvydzmov;
double dvzdxmov, dvzdymov, dvzdzmov;
double Vxc, Vyc, Vzc, dssss_dr;
int j = 3*(threadIdx.x + blockIdx.x*blockDim.x);
if (true) {
Vxc = 1.0;
Vyc = 0;
Vzc = 0;
dvxdxmov = 0.0;
dvxdymov = 0;
dvxdzmov = 0;
dvydxmov = 0;
dvydymov = 0;
dvydzmov = 0;
dvzdxmov = 0;
dvzdymov = 0;
dvzdzmov = 0;
}
for (int i=0; i < Number; i++) {
vxx_p = Vortex_p[j] - Vortex_p[i * 3];
vyy_p = Vortex_p[j + 1] - Vortex_p[(i * 3) + 1];
vzz_p = Vortex_p[j + 2] - Vortex_p[(i * 3) + 2];
radiika_p = vxx_p*vxx_p + vyy_p*vyy_p + vzz_p*vzz_p;
t1_p = vyy_p*Omega_v_p[(i * 3) + 2] - vzz_p*Omega_v_p[(i * 3) + 1];
t2_p = vzz_p*Omega_v_p[i * 3] - vxx_p*Omega_v_p[(i * 3) + 2];
t3_p = vxx_p*Omega_v_p[(i * 3) + 1] - vyy_p*Omega_v_p[i * 3];
Om22P_p = 3.1416 / Sigma_p[i] / Sigma_p[i] / 2.0;
ssss_p = exp(-radiika_p*Om22P_p);
Vxc = Vxc + ssss_p*t1_p;
Vyc = Vyc + ssss_p*t2_p;
Vzc = Vzc + ssss_p*t3_p;
dssss_dr = (-Om22P_p)*ssss_p;
dvxdxmov = dssss_dr*vxx_p*t1_p + dvxdxmov;
dvxdymov = dssss_dr*vyy_p*t1_p + Omega_v_p[(i * 3) + 2] * ssss_p + dvxdymov;
dvxdzmov = dssss_dr*vzz_p*t1_p - Omega_v_p[(i * 3) + 1] * ssss_p + dvxdzmov;
dvydxmov = dssss_dr*vxx_p*t2_p - Omega_v_p[(i * 3) + 2] * ssss_p + dvydxmov;
dvydymov = dssss_dr*vyy_p*t2_p + dvydymov;
dvydzmov = dssss_dr*vzz_p*t2_p + Omega_v_p[i * 3] * ssss_p + dvydzmov;
dvzdxmov = dssss_dr*vxx_p*t3_p + Omega_v_p[(i * 3) + 1] * ssss_p + dvzdxmov;
dvzdymov = dssss_dr*vyy_p*t3_p - Omega_v_p[i * 3] * ssss_p + dvzdymov;
dvzdzmov = dssss_dr*vzz_p*t3_p + dvzdzmov;
}
if ( true) {
VortexN_p[j] = Vortex_p[j] + Delta_t*Vxc;
VortexN_p[j + 1] = Vortex_p[j + 1] + Delta_t*Vyc;
VortexN_p[j + 2] = Vortex_p[j + 2] + Delta_t*Vzc;
double domxdt, domydt, domzdt;
domxdt = dvxdxmov*Omega_v_p[j] + dvxdymov*Omega_v_p[j + 1] + dvxdzmov*Omega_v_p[j + 2];
domydt = dvydxmov*Omega_v_p[j] + dvydymov*Omega_v_p[j + 1] + dvydzmov*Omega_v_p[j + 2];
domzdt = dvzdxmov*Omega_v_p[j] + dvzdymov*Omega_v_p[j + 1] + dvzdzmov*Omega_v_p[j + 2];
Omega_vN_p[j] = Omega_v_p[j] + domxdt*Delta_t;
Omega_vN_p[j + 1] = Omega_v_p[j + 1] + domydt*Delta_t;
Omega_vN_p[j + 2] = Omega_v_p[j + 2] + domzdt*Delta_t;
Vxc = 0, Vyc = 0, Vzc = 0;
dvxdxmov = 0, dvxdymov = 0, dvxdzmov = 0;
dvydxmov = 0, dvydymov = 0, dvydzmov = 0;
dvzdxmov = 0, dvzdymov = 0, dvzdzmov = 0;
}
}
int main()
{
const int Ntime = 10000;
//const double Delta_t = 0.01;
const double Radius = 0.1;
//const int Number = 10;
//const double V_mean = 1.0;
double Vortex[Number][3];
double Omega_v[Number][3];
double VortexN[Number][3];
double Omega_vN[Number][3];
double *Vortex_p=new double[Number*3];
double *Omega_v_p = new double[Number * 3];
double *VortexN_p = new double[Number * 3];
double *Omega_vN_p = new double[Number * 3];
double Sigma[Number];
double *Sigma_p;
double StatisticalMoments[4] = {0.000};
double Amagni=0.0,Amagnit_old,Amagnit_new,Speed_max,Sigmas;
double Energy=0;
int Ncout=0;
FILE *fp1,*fp2;
fp1 = fopen("D:\\cudaa\\Velocities1.txt","w+");
fp2 = fopen("D:\\cudaa\\MaxValue1.txt","w+");
double Vx;
double vxx, vyy, vzz;
double *vxx_p, *vyy_p, *vzz_p;
clock_t time0,time1;
for (int ivorton = 0; ivorton < Number; ivorton++) {
Vortex[ivorton][0] = (double)rand() / (double)RAND_MAX;
Vortex[ivorton][1] = (double)rand() / (double)RAND_MAX;
Vortex[ivorton][2] = (double)rand() / (double)RAND_MAX;
Omega_v[ivorton][0] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_v[ivorton][1] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_v[ivorton][2] = (((double)rand() / (double)RAND_MAX) - 0.5);
Sigma[ivorton] = Radius;
//printf("%f",Vortex[ivorton][1]);
}
int counter = 0;
for (int h = 0; h < Number; h++) {
for (int w = 0; w < 3; w++) {
Vortex_p[counter] = Vortex[h][w];
Omega_v_p[counter] = Omega_v[h][w];
VortexN_p[counter] = VortexN[h][w];
Omega_vN_p[counter] = Omega_vN[h][w];
counter++;
}
}
time0 = clock();
double radiika;
double t1, t2, t3;
double Om22P;
double ssss,dssss_dr;
double domxdt, domydt, domzdt,Replace=0;
double Vxc, Vyc , Vzc ;
double dvxdxmov , dvxdymov , dvxdzmov ;
double dvydxmov , dvydymov , dvydzmov ;
double dvzdxmov , dvzdymov , dvzdzmov ;
double *radiika_p;
double *t1_p, *t2_p, *t3_p;
double *Om22P_p;
double *ssss_p, *dssss_dr_p;
double *domxdt_p, *domydt_p, *domzdt_p, *Replace_p ;
double *Vxc_p, *Vyc_p, *Vzc_p;
double *dvxdxmov_p, *dvxdymov_p, *dvxdzmov_p;
double *dvydxmov_p, *dvydymov_p, *dvydzmov_p;
double *dvzdxmov_p, *dvzdymov_p, *dvzdzmov_p;
vxx_p = &vxx;
hipMalloc((void**)&Vortex_p, (Number * 3) * sizeof(double));
hipMalloc((void**)&Omega_v_p, (Number * 3) * sizeof(double));
hipMalloc((void**)&VortexN_p, (Number * 3) * sizeof(double));
hipMalloc((void**)&Omega_vN_p, (Number * 3) * sizeof(double));
hipMalloc((void**)&Sigma_p, (Number) * sizeof(double));
for (int itime = 0; itime < Ntime; itime++) {
printf("%*d %f %e %d \n ",4,itime,Amagni,Energy,Ncout);
//cudaMalloc((void**)&domzdt_p, sizeof(double));
hipMemcpy(Vortex_p, Vortex, (Number * 3) * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(Omega_v_p, Omega_v, (Number * 3) * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(VortexN_p, VortexN, (Number * 3) * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(Omega_vN_p, Omega_vN, (Number * 3) * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(Sigma_p, Sigma, (Number) * sizeof(double), hipMemcpyHostToDevice);
dim3 dimBlock(Number, 1);
dim3 dimGrid(Number, 1);
Simulate <<<Number/32, 32 >>> (Vortex_p,Omega_v_p, VortexN_p, Omega_vN_p,Sigma_p);
hipMemcpy(Vortex, Vortex_p, (Number * 3) * sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(Omega_v,Omega_v_p, (Number * 3) * sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(VortexN, VortexN_p, (Number * 3) * sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(Omega_vN, Omega_vN_p, (Number * 3) * sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(Sigma, Sigma_p, (Number) * sizeof(double), hipMemcpyDeviceToHost);
/*
for (int ivorton = 0; ivorton < Number;ivorton++) {
double Vxc=V_mean, Vyc=0.0, Vzc=0.0;
double dvxdxmov = 0.0, dvxdymov = 0.0, dvxdzmov = 0.0;
double dvydxmov = 0.0, dvydymov = 0.0, dvydzmov = 0.0;
double dvzdxmov = 0.0, dvzdymov = 0.0, dvzdzmov = 0.0;
for (int induced = 0; induced < Number; induced++) {
vxx = Vortex[ivorton][0] - Vortex[induced][0];
vyy = Vortex[ivorton][1] - Vortex[induced][1];
vzz = Vortex[ivorton][2] - Vortex[induced][2];
radiika = vxx*vxx + vyy*vyy + vzz*vzz;
t1 = vyy*Omega_v[induced][2] - vzz*Omega_v[induced][1];
t2 = vzz*Omega_v[induced][0] - vzz*Omega_v[induced][2];
t3 = vxx*Omega_v[induced][1] - vzz*Omega_v[induced][0];
Om22P = 3.1416 / Sigma[induced] / Sigma[induced] / 2.0;
ssss = exp(-radiika* Om22P);
Vxc = Vxc + ssss*t1;
Vyc = Vyc + ssss*t2;
Vzc = Vzc + ssss*t3;
dssss_dr = (-Om22P)*ssss;
dvxdxmov = dssss_dr*vxx*t1 + dvxdxmov;
dvxdymov = dssss_dr*vyy*t1 + Omega_v[induced][2]*ssss + dvxdymov;
dvxdzmov = dssss_dr*vzz*t1 - Omega_v[induced][1]*ssss + dvxdzmov;
dvydxmov = dssss_dr*vxx*t2 - Omega_v[induced][2]*ssss + dvydxmov;
dvydymov = dssss_dr*vyy*t2 + dvydymov;
dvydzmov = dssss_dr*vzz*t2 + Omega_v[induced][0]*ssss + dvydzmov;
dvzdxmov = dssss_dr*vxx*t3 + Omega_v[induced][1]*ssss + dvzdxmov;
dvzdymov = dssss_dr*vyy*t3 - Omega_v[induced][0]*ssss + dvzdymov;
dvzdzmov = dssss_dr*vzz*t3 + dvzdzmov;
}
VortexN[ivorton][0] = Vortex[ivorton][0] + Delta_t*Vxc;
VortexN[ivorton][1] = Vortex[ivorton][1] + Delta_t*Vyc;
VortexN[ivorton][2] = Vortex[ivorton][2] + Delta_t*Vzc;
// domxdt=dvxdxmov*Omega_v[ivorton][0]+dvxdymov*Omega_v[][]
domxdt = dvxdxmov*Omega_v[ivorton][0] + dvxdymov*Omega_v[ivorton][1] + dvxdzmov*Omega_v[ivorton][2];
domydt = dvydxmov*Omega_v[ivorton][0] + dvydymov*Omega_v[ivorton][1] + dvydzmov*Omega_v[ivorton][2];
domzdt = dvzdxmov*Omega_v[ivorton][0] + dvzdymov*Omega_v[ivorton][1] + dvzdzmov*Omega_v[ivorton][2];
Omega_vN[ivorton][0] = Omega_v[ivorton][0] + domxdt*Delta_t;
Omega_vN[ivorton][1]= Omega_v[ivorton][1] + domydt*Delta_t;
Omega_vN[ivorton][2] = Omega_v[ivorton][2] + domzdt*Delta_t;
}
*/
Ncout = 0;
for (int ivorton = 0; ivorton < Number; ivorton++) {
Replace = 0.0;
for (int kkk = 0; kkk < 3; kkk++) {
if (VortexN[ivorton][kkk] < 0.0) {
Replace = 1.0;
}
if (VortexN[ivorton][kkk] > 1.0) {
Replace = 1.0;
}
}
if (Replace == 1.0) {
Ncout = Ncout + 1;
VortexN[ivorton][0] = (double)rand() / (double)RAND_MAX;
VortexN[ivorton][1] = (double)rand() / (double)RAND_MAX;
VortexN[ivorton][2] = (double)rand() / (double)RAND_MAX;
Omega_vN[ivorton][0] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_vN[ivorton][1] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_vN[ivorton][2] = (((double)rand() / (double)RAND_MAX) - 0.5);
Sigma[ivorton] = Radius;
}
}
Amagni = 0.0;
for (int ivorton = 0; ivorton < Number; ivorton++) {
Vortex[ivorton][0] = VortexN[ivorton][0];
Vortex[ivorton][1] = VortexN[ivorton][1];
Vortex[ivorton][2] = VortexN[ivorton][2];
Amagnit_old = sqrt((Omega_v[ivorton][0] * Omega_v[ivorton][0]) +( Omega_v[ivorton][1] * Omega_v[ivorton][1]) +( Omega_v[ivorton][2] * Omega_v[ivorton][2]));
Omega_v[ivorton][0] = Omega_vN[ivorton][0];
Omega_v[ivorton][1] = Omega_vN[ivorton][1];
Omega_v[ivorton][2] = Omega_vN[ivorton][2];
Amagnit_new= sqrt((Omega_v[ivorton][0] * Omega_v[ivorton][0]) + (Omega_v[ivorton][1] * Omega_v[ivorton][1]) + (Omega_v[ivorton][2] * Omega_v[ivorton][2]));
Sigma[ivorton] = Sigma[ivorton] * sqrt(Amagnit_old / Amagnit_new);
if (Amagnit_new >= Amagni) {
Amagni = Amagnit_new;
Energy = (Amagnit_new*Amagnit_new)*(pow(Sigma[ivorton], 5));
Speed_max = Amagnit_new*Sigma[ivorton];
Sigmas = Sigma[ivorton];
}
}
//file write
fprintf(fp1, "%f %f %f %f %f \n", itime*Delta_t, Amagni, Energy, Speed_max, Sigmas);
Vx = 0.0;
for (int induced = 0; induced < Number; induced++) {
vxx = 0.5 - Vortex[induced][0];
vyy = 0.5 - Vortex[induced][1];
vzz = 0.5 - Vortex[induced][2];
radiika = vxx*vxx + vyy*vyy + vzz*vzz;
t1 = vyy* Omega_v[induced][2] - vzz*Omega_v[induced][1];
Om22P = 3.1416 / Sigma[induced] / Sigma[induced] / 2.0;
ssss = exp(-radiika*Om22P);
Vx = Vx + ssss*t1;
}
fprintf(fp2, "%f %f \n", itime*Delta_t, Vx);
for (int ier = 0; ier < 4; ier++) {
StatisticalMoments[ier] = StatisticalMoments[ier] +pow(Vx, ier);
}
}
hipFree(Vortex_p);
hipFree(Omega_v_p);
hipFree(VortexN_p);
hipFree(Omega_vN_p);
hipFree(Sigma_p);
fclose(fp1);
fclose(fp2);
time1 = clock();
printf("Time taken for execution with GPU acceleration (~31blocks & 32 threads)= %f sec(s)", (double)(time1 - time0) / CLOCKS_PER_SEC);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8SimulatePdS_S_S_S_
.globl _Z8SimulatePdS_S_S_S_
.p2align 8
.type _Z8SimulatePdS_S_S_S_,@function
_Z8SimulatePdS_S_S_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x20
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v6, 0
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v21, 0
v_dual_mov_b32 v18, 0 :: v_dual_mov_b32 v13, 0
v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v27, 0
v_dual_mov_b32 v30, 0 :: v_dual_mov_b32 v7, 0
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v11, 0
v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v19, 0
v_mov_b32_e32 v15, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
v_mov_b32_e32 v31, 0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v17, 0
s_mov_b64 s[10:11], 0
s_mov_b32 s13, 0x400921ff
s_mov_b32 s12, 0x2e48e8a7
s_mov_b32 s15, 0x3ff71547
s_delay_alu instid0(VALU_DEP_3)
v_lshl_add_u32 v22, v1, 1, v1
s_mov_b32 s14, 0x652b82fe
s_mov_b32 s17, 0xbfe62e42
s_mov_b32 s16, 0xfefa39ef
s_mov_b32 s19, 0xbc7abc9e
v_ashrrev_i32_e32 v23, 31, v22
s_mov_b32 s18, 0x3b39803f
s_mov_b32 s21, 0x3e928af3
s_mov_b32 s20, 0xfca7ab0c
s_mov_b32 s23, 0x3e5ade15
v_lshlrev_b64 v[0:1], 3, v[22:23]
s_mov_b32 s22, 0x6a5dcb37
s_mov_b32 s25, 0x3ec71dee
s_mov_b32 s24, 0x623fde64
s_mov_b32 s27, 0x3efa0199
s_mov_b32 s26, 0x7c89e6b0
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
s_mov_b32 s29, 0x3f2a01a0
s_mov_b32 s28, 0x14761f6e
s_mov_b32 s31, 0x3f56c16c
s_clause 0x1
global_load_b128 v[0:3], v[4:5], off
global_load_b64 v[28:29], v[4:5], off offset:16
v_mov_b32_e32 v4, 0
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v24, 0
v_mov_b32_e32 v25, 0x3ff00000
s_mov_b32 s30, 0x1852b7b0
s_mov_b32 s35, 0x3f811111
s_mov_b32 s34, 0x11122322
s_mov_b32 s37, 0x3fa55555
s_mov_b32 s36, 0x555502a1
s_mov_b32 s39, 0x3fc55555
s_mov_b32 s38, 0x55555511
s_mov_b32 s41, 0x3fe00000
s_mov_b32 s40, 11
.LBB0_1:
s_load_b64 s[2:3], s[8:9], 0x0
s_add_u32 s42, s4, s10
s_addc_u32 s43, s5, s11
s_clause 0x1
s_load_b128 s[44:47], s[42:43], 0x0
s_load_b64 s[42:43], s[42:43], 0x10
s_waitcnt lgkmcnt(0)
v_div_scale_f64 v[32:33], null, s[2:3], s[2:3], s[12:13]
v_div_scale_f64 v[38:39], vcc_lo, s[12:13], s[2:3], s[12:13]
s_waitcnt vmcnt(1)
v_add_f64 v[42:43], v[2:3], -s[46:47]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[34:35], v[32:33]
v_mul_f64 v[44:45], v[42:43], v[42:43]
s_waitcnt_depctr 0xfff
v_fma_f64 v[36:37], -v[32:33], v[34:35], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[34:35], v[34:35], v[36:37], v[34:35]
v_fma_f64 v[36:37], -v[32:33], v[34:35], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[34:35], v[34:35], v[36:37], v[34:35]
v_mul_f64 v[36:37], v[38:39], v[34:35]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[32:33], -v[32:33], v[36:37], v[38:39]
v_div_fmas_f64 v[32:33], v[32:33], v[34:35], v[36:37]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[32:33], v[32:33], s[2:3], s[12:13]
v_div_scale_f64 v[34:35], null, s[2:3], s[2:3], v[32:33]
v_div_scale_f64 v[40:41], vcc_lo, v[32:33], s[2:3], v[32:33]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[36:37], v[34:35]
s_waitcnt_depctr 0xfff
v_fma_f64 v[38:39], -v[34:35], v[36:37], 1.0
v_fma_f64 v[36:37], v[36:37], v[38:39], v[36:37]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[38:39], -v[34:35], v[36:37], 1.0
v_fma_f64 v[36:37], v[36:37], v[38:39], v[36:37]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[38:39], v[40:41], v[36:37]
v_fma_f64 v[34:35], -v[34:35], v[38:39], v[40:41]
v_add_f64 v[40:41], v[0:1], -s[44:45]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[34:35], v[34:35], v[36:37], v[38:39]
s_waitcnt vmcnt(0)
v_add_f64 v[36:37], v[28:29], -s[42:43]
v_fma_f64 v[38:39], v[40:41], v[40:41], v[44:45]
s_add_u32 s42, s6, s10
s_addc_u32 s43, s7, s11
s_clause 0x1
s_load_b128 s[44:47], s[42:43], 0x0
s_load_b64 s[42:43], s[42:43], 0x10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[32:33], v[34:35], s[2:3], v[32:33]
v_fma_f64 v[34:35], v[36:37], v[36:37], v[38:39]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[32:33], v[32:33], 0.5
v_mul_f64 v[34:35], v[32:33], -v[34:35]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_f64 v[38:39], v[34:35], s[14:15]
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[34:35]
v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[34:35]
v_rndne_f64_e32 v[38:39], v[38:39]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_fma_f64 v[44:45], v[38:39], s[16:17], v[34:35]
v_cvt_i32_f64_e32 v48, v[38:39]
s_waitcnt lgkmcnt(0)
v_mul_f64 v[34:35], v[36:37], s[46:47]
v_fma_f64 v[44:45], v[38:39], s[18:19], v[44:45]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[34:35], v[42:43], s[42:43], -v[34:35]
v_fma_f64 v[46:47], v[44:45], s[22:23], s[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[46:47], v[44:45], v[46:47], s[24:25]
v_fma_f64 v[46:47], v[44:45], v[46:47], s[26:27]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[46:47], v[44:45], v[46:47], s[28:29]
v_fma_f64 v[46:47], v[44:45], v[46:47], s[30:31]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[46:47], v[44:45], v[46:47], s[34:35]
v_fma_f64 v[46:47], v[44:45], v[46:47], s[36:37]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[46:47], v[44:45], v[46:47], s[38:39]
v_fma_f64 v[46:47], v[44:45], v[46:47], s[40:41]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[46:47], v[44:45], v[46:47], 1.0
v_fma_f64 v[38:39], v[44:45], v[46:47], 1.0
v_mul_f64 v[44:45], v[40:41], s[42:43]
v_mul_f64 v[46:47], v[42:43], s[44:45]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f64 v[38:39], v[38:39], v48
v_fma_f64 v[44:45], v[36:37], s[44:45], -v[44:45]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[46:47], v[40:41], s[46:47], -v[46:47]
v_cndmask_b32_e32 v39, 0x7ff00000, v39, vcc_lo
s_and_b32 vcc_lo, s2, vcc_lo
s_add_u32 s10, s10, 24
s_delay_alu instid0(VALU_DEP_4)
v_cndmask_b32_e32 v38, 0, v38, vcc_lo
s_addc_u32 s11, s11, 0
v_cndmask_b32_e64 v39, 0, v39, s2
s_add_u32 s8, s8, 8
s_addc_u32 s9, s9, 0
s_cmpk_eq_i32 s10, 0x5dc0
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[32:33], v[38:39], -v[32:33]
v_mul_f64 v[48:49], s[42:43], v[38:39]
v_mul_f64 v[50:51], s[46:47], v[38:39]
v_mul_f64 v[52:53], s[44:45], v[38:39]
v_fma_f64 v[24:25], v[34:35], v[38:39], v[24:25]
v_fma_f64 v[30:31], v[44:45], v[38:39], v[30:31]
v_fma_f64 v[26:27], v[46:47], v[38:39], v[26:27]
v_mul_f64 v[42:43], v[42:43], v[32:33]
v_mul_f64 v[36:37], v[36:37], v[32:33]
v_mul_f64 v[32:33], v[40:41], v[32:33]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[40:41], v[34:35], v[42:43], v[48:49]
v_fma_f64 v[54:55], v[34:35], v[36:37], -v[50:51]
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[48:49], v[44:45], v[32:33], -v[48:49]
v_fma_f64 v[56:57], v[44:45], v[36:37], v[52:53]
v_fma_f64 v[50:51], v[46:47], v[32:33], v[50:51]
v_fma_f64 v[52:53], v[46:47], v[42:43], -v[52:53]
v_fma_f64 v[4:5], v[34:35], v[32:33], v[4:5]
v_fma_f64 v[14:15], v[44:45], v[42:43], v[14:15]
v_fma_f64 v[6:7], v[46:47], v[36:37], v[6:7]
v_add_f64 v[20:21], v[20:21], v[40:41]
v_add_f64 v[18:19], v[18:19], v[54:55]
v_add_f64 v[12:13], v[12:13], v[48:49]
v_add_f64 v[16:17], v[16:17], v[56:57]
v_add_f64 v[10:11], v[10:11], v[50:51]
v_add_f64 v[8:9], v[8:9], v[52:53]
s_cbranch_scc0 .LBB0_1
v_lshlrev_b64 v[0:1], 3, v[22:23]
s_mov_b32 s9, 0x3f847ae1
s_mov_b32 s8, 0x47ae147b
s_load_b128 s[0:3], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v32, vcc_lo, v0, 8
v_add_co_ci_u32_e32 v33, vcc_lo, 0, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v22, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v23, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[24:25], s[8:9], v[2:3]
v_add_co_u32 v24, vcc_lo, s4, v32
v_add_co_ci_u32_e32 v25, vcc_lo, s5, v33, vcc_lo
global_store_b64 v[22:23], v[2:3], off
global_load_b64 v[2:3], v[24:25], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[30:31], s[8:9], v[2:3]
v_add_co_u32 v30, vcc_lo, v0, 16
v_add_co_ci_u32_e32 v31, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v22, vcc_lo, s0, v32
v_add_co_ci_u32_e32 v23, vcc_lo, s1, v33, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v24, vcc_lo, s4, v30
v_add_co_ci_u32_e32 v25, vcc_lo, s5, v31, vcc_lo
global_store_b64 v[22:23], v[2:3], off
global_load_b64 v[2:3], v[24:25], off
v_add_co_u32 v22, vcc_lo, s0, v30
v_add_co_ci_u32_e32 v23, vcc_lo, s1, v31, vcc_lo
v_add_co_u32 v24, vcc_lo, s6, v32
v_add_co_ci_u32_e32 v25, vcc_lo, s7, v33, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[26:27], s[8:9], v[2:3]
global_store_b64 v[22:23], v[2:3], off
global_load_b64 v[2:3], v[24:25], off
v_add_co_u32 v22, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v23, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v26, vcc_lo, s6, v30
v_add_co_ci_u32_e32 v27, vcc_lo, s7, v31, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b64 v[28:29], v[26:27], off
global_load_b64 v[22:23], v[22:23], off
s_waitcnt vmcnt(2)
v_mul_f64 v[20:21], v[20:21], v[2:3]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[4:5], v[22:23], v[20:21]
v_fma_f64 v[4:5], v[18:19], v[28:29], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_fma_f64 v[4:5], v[4:5], s[8:9], v[22:23]
global_store_b64 v[0:1], v[4:5], off
global_load_b64 v[0:1], v[24:25], off
v_mul_f64 v[4:5], v[14:15], v[2:3]
v_mul_f64 v[2:3], v[8:9], v[2:3]
v_fma_f64 v[4:5], v[12:13], v[22:23], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], v[10:11], v[22:23], v[2:3]
v_fma_f64 v[4:5], v[16:17], v[28:29], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], v[6:7], v[28:29], v[2:3]
s_waitcnt vmcnt(0)
v_fma_f64 v[0:1], v[4:5], s[8:9], v[0:1]
v_add_co_u32 v4, vcc_lo, s2, v32
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v33, vcc_lo
global_store_b64 v[4:5], v[0:1], off
global_load_b64 v[0:1], v[26:27], off
s_waitcnt vmcnt(0)
v_fma_f64 v[0:1], v[2:3], s[8:9], v[0:1]
v_add_co_u32 v2, vcc_lo, s2, v30
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v31, vcc_lo
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8SimulatePdS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 58
.amdhsa_next_free_sgpr 48
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8SimulatePdS_S_S_S_, .Lfunc_end0-_Z8SimulatePdS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8SimulatePdS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 50
.sgpr_spill_count: 0
.symbol: _Z8SimulatePdS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 58
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <hip/device_functions.h>
#include <stdio.h>
#include <cstdlib>
#include <math.h>
#include<time.h>
#include <hip/hip_runtime_api.h>
#define Number 1000
#define Delta_t 0.01
__global__
void Simulate(double* Vortex_p, double* Omega_v_p, double* VortexN_p, double* Omega_vN_p, double *Sigma_p)
{
double radiika_p, t1_p, t2_p;
double t3_p, Om22P_p, ssss_p, vxx_p, vyy_p, vzz_p;
double dvxdxmov, dvxdymov, dvxdzmov;
double dvydxmov, dvydymov, dvydzmov;
double dvzdxmov, dvzdymov, dvzdzmov;
double Vxc, Vyc, Vzc, dssss_dr;
int j = 3*(threadIdx.x + blockIdx.x*blockDim.x);
if (true) {
Vxc = 1.0;
Vyc = 0;
Vzc = 0;
dvxdxmov = 0.0;
dvxdymov = 0;
dvxdzmov = 0;
dvydxmov = 0;
dvydymov = 0;
dvydzmov = 0;
dvzdxmov = 0;
dvzdymov = 0;
dvzdzmov = 0;
}
for (int i=0; i < Number; i++) {
vxx_p = Vortex_p[j] - Vortex_p[i * 3];
vyy_p = Vortex_p[j + 1] - Vortex_p[(i * 3) + 1];
vzz_p = Vortex_p[j + 2] - Vortex_p[(i * 3) + 2];
radiika_p = vxx_p*vxx_p + vyy_p*vyy_p + vzz_p*vzz_p;
t1_p = vyy_p*Omega_v_p[(i * 3) + 2] - vzz_p*Omega_v_p[(i * 3) + 1];
t2_p = vzz_p*Omega_v_p[i * 3] - vxx_p*Omega_v_p[(i * 3) + 2];
t3_p = vxx_p*Omega_v_p[(i * 3) + 1] - vyy_p*Omega_v_p[i * 3];
Om22P_p = 3.1416 / Sigma_p[i] / Sigma_p[i] / 2.0;
ssss_p = exp(-radiika_p*Om22P_p);
Vxc = Vxc + ssss_p*t1_p;
Vyc = Vyc + ssss_p*t2_p;
Vzc = Vzc + ssss_p*t3_p;
dssss_dr = (-Om22P_p)*ssss_p;
dvxdxmov = dssss_dr*vxx_p*t1_p + dvxdxmov;
dvxdymov = dssss_dr*vyy_p*t1_p + Omega_v_p[(i * 3) + 2] * ssss_p + dvxdymov;
dvxdzmov = dssss_dr*vzz_p*t1_p - Omega_v_p[(i * 3) + 1] * ssss_p + dvxdzmov;
dvydxmov = dssss_dr*vxx_p*t2_p - Omega_v_p[(i * 3) + 2] * ssss_p + dvydxmov;
dvydymov = dssss_dr*vyy_p*t2_p + dvydymov;
dvydzmov = dssss_dr*vzz_p*t2_p + Omega_v_p[i * 3] * ssss_p + dvydzmov;
dvzdxmov = dssss_dr*vxx_p*t3_p + Omega_v_p[(i * 3) + 1] * ssss_p + dvzdxmov;
dvzdymov = dssss_dr*vyy_p*t3_p - Omega_v_p[i * 3] * ssss_p + dvzdymov;
dvzdzmov = dssss_dr*vzz_p*t3_p + dvzdzmov;
}
if ( true) {
VortexN_p[j] = Vortex_p[j] + Delta_t*Vxc;
VortexN_p[j + 1] = Vortex_p[j + 1] + Delta_t*Vyc;
VortexN_p[j + 2] = Vortex_p[j + 2] + Delta_t*Vzc;
double domxdt, domydt, domzdt;
domxdt = dvxdxmov*Omega_v_p[j] + dvxdymov*Omega_v_p[j + 1] + dvxdzmov*Omega_v_p[j + 2];
domydt = dvydxmov*Omega_v_p[j] + dvydymov*Omega_v_p[j + 1] + dvydzmov*Omega_v_p[j + 2];
domzdt = dvzdxmov*Omega_v_p[j] + dvzdymov*Omega_v_p[j + 1] + dvzdzmov*Omega_v_p[j + 2];
Omega_vN_p[j] = Omega_v_p[j] + domxdt*Delta_t;
Omega_vN_p[j + 1] = Omega_v_p[j + 1] + domydt*Delta_t;
Omega_vN_p[j + 2] = Omega_v_p[j + 2] + domzdt*Delta_t;
Vxc = 0, Vyc = 0, Vzc = 0;
dvxdxmov = 0, dvxdymov = 0, dvxdzmov = 0;
dvydxmov = 0, dvydymov = 0, dvydzmov = 0;
dvzdxmov = 0, dvzdymov = 0, dvzdzmov = 0;
}
}
int main()
{
const int Ntime = 10000;
//const double Delta_t = 0.01;
const double Radius = 0.1;
//const int Number = 10;
//const double V_mean = 1.0;
double Vortex[Number][3];
double Omega_v[Number][3];
double VortexN[Number][3];
double Omega_vN[Number][3];
double *Vortex_p=new double[Number*3];
double *Omega_v_p = new double[Number * 3];
double *VortexN_p = new double[Number * 3];
double *Omega_vN_p = new double[Number * 3];
double Sigma[Number];
double *Sigma_p;
double StatisticalMoments[4] = {0.000};
double Amagni=0.0,Amagnit_old,Amagnit_new,Speed_max,Sigmas;
double Energy=0;
int Ncout=0;
FILE *fp1,*fp2;
fp1 = fopen("D:\\cudaa\\Velocities1.txt","w+");
fp2 = fopen("D:\\cudaa\\MaxValue1.txt","w+");
double Vx;
double vxx, vyy, vzz;
double *vxx_p, *vyy_p, *vzz_p;
clock_t time0,time1;
for (int ivorton = 0; ivorton < Number; ivorton++) {
Vortex[ivorton][0] = (double)rand() / (double)RAND_MAX;
Vortex[ivorton][1] = (double)rand() / (double)RAND_MAX;
Vortex[ivorton][2] = (double)rand() / (double)RAND_MAX;
Omega_v[ivorton][0] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_v[ivorton][1] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_v[ivorton][2] = (((double)rand() / (double)RAND_MAX) - 0.5);
Sigma[ivorton] = Radius;
//printf("%f",Vortex[ivorton][1]);
}
int counter = 0;
for (int h = 0; h < Number; h++) {
for (int w = 0; w < 3; w++) {
Vortex_p[counter] = Vortex[h][w];
Omega_v_p[counter] = Omega_v[h][w];
VortexN_p[counter] = VortexN[h][w];
Omega_vN_p[counter] = Omega_vN[h][w];
counter++;
}
}
time0 = clock();
double radiika;
double t1, t2, t3;
double Om22P;
double ssss,dssss_dr;
double domxdt, domydt, domzdt,Replace=0;
double Vxc, Vyc , Vzc ;
double dvxdxmov , dvxdymov , dvxdzmov ;
double dvydxmov , dvydymov , dvydzmov ;
double dvzdxmov , dvzdymov , dvzdzmov ;
double *radiika_p;
double *t1_p, *t2_p, *t3_p;
double *Om22P_p;
double *ssss_p, *dssss_dr_p;
double *domxdt_p, *domydt_p, *domzdt_p, *Replace_p ;
double *Vxc_p, *Vyc_p, *Vzc_p;
double *dvxdxmov_p, *dvxdymov_p, *dvxdzmov_p;
double *dvydxmov_p, *dvydymov_p, *dvydzmov_p;
double *dvzdxmov_p, *dvzdymov_p, *dvzdzmov_p;
vxx_p = &vxx;
hipMalloc((void**)&Vortex_p, (Number * 3) * sizeof(double));
hipMalloc((void**)&Omega_v_p, (Number * 3) * sizeof(double));
hipMalloc((void**)&VortexN_p, (Number * 3) * sizeof(double));
hipMalloc((void**)&Omega_vN_p, (Number * 3) * sizeof(double));
hipMalloc((void**)&Sigma_p, (Number) * sizeof(double));
for (int itime = 0; itime < Ntime; itime++) {
printf("%*d %f %e %d \n ",4,itime,Amagni,Energy,Ncout);
//cudaMalloc((void**)&domzdt_p, sizeof(double));
hipMemcpy(Vortex_p, Vortex, (Number * 3) * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(Omega_v_p, Omega_v, (Number * 3) * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(VortexN_p, VortexN, (Number * 3) * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(Omega_vN_p, Omega_vN, (Number * 3) * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(Sigma_p, Sigma, (Number) * sizeof(double), hipMemcpyHostToDevice);
dim3 dimBlock(Number, 1);
dim3 dimGrid(Number, 1);
Simulate <<<Number/32, 32 >>> (Vortex_p,Omega_v_p, VortexN_p, Omega_vN_p,Sigma_p);
hipMemcpy(Vortex, Vortex_p, (Number * 3) * sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(Omega_v,Omega_v_p, (Number * 3) * sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(VortexN, VortexN_p, (Number * 3) * sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(Omega_vN, Omega_vN_p, (Number * 3) * sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(Sigma, Sigma_p, (Number) * sizeof(double), hipMemcpyDeviceToHost);
/*
for (int ivorton = 0; ivorton < Number;ivorton++) {
double Vxc=V_mean, Vyc=0.0, Vzc=0.0;
double dvxdxmov = 0.0, dvxdymov = 0.0, dvxdzmov = 0.0;
double dvydxmov = 0.0, dvydymov = 0.0, dvydzmov = 0.0;
double dvzdxmov = 0.0, dvzdymov = 0.0, dvzdzmov = 0.0;
for (int induced = 0; induced < Number; induced++) {
vxx = Vortex[ivorton][0] - Vortex[induced][0];
vyy = Vortex[ivorton][1] - Vortex[induced][1];
vzz = Vortex[ivorton][2] - Vortex[induced][2];
radiika = vxx*vxx + vyy*vyy + vzz*vzz;
t1 = vyy*Omega_v[induced][2] - vzz*Omega_v[induced][1];
t2 = vzz*Omega_v[induced][0] - vzz*Omega_v[induced][2];
t3 = vxx*Omega_v[induced][1] - vzz*Omega_v[induced][0];
Om22P = 3.1416 / Sigma[induced] / Sigma[induced] / 2.0;
ssss = exp(-radiika* Om22P);
Vxc = Vxc + ssss*t1;
Vyc = Vyc + ssss*t2;
Vzc = Vzc + ssss*t3;
dssss_dr = (-Om22P)*ssss;
dvxdxmov = dssss_dr*vxx*t1 + dvxdxmov;
dvxdymov = dssss_dr*vyy*t1 + Omega_v[induced][2]*ssss + dvxdymov;
dvxdzmov = dssss_dr*vzz*t1 - Omega_v[induced][1]*ssss + dvxdzmov;
dvydxmov = dssss_dr*vxx*t2 - Omega_v[induced][2]*ssss + dvydxmov;
dvydymov = dssss_dr*vyy*t2 + dvydymov;
dvydzmov = dssss_dr*vzz*t2 + Omega_v[induced][0]*ssss + dvydzmov;
dvzdxmov = dssss_dr*vxx*t3 + Omega_v[induced][1]*ssss + dvzdxmov;
dvzdymov = dssss_dr*vyy*t3 - Omega_v[induced][0]*ssss + dvzdymov;
dvzdzmov = dssss_dr*vzz*t3 + dvzdzmov;
}
VortexN[ivorton][0] = Vortex[ivorton][0] + Delta_t*Vxc;
VortexN[ivorton][1] = Vortex[ivorton][1] + Delta_t*Vyc;
VortexN[ivorton][2] = Vortex[ivorton][2] + Delta_t*Vzc;
// domxdt=dvxdxmov*Omega_v[ivorton][0]+dvxdymov*Omega_v[][]
domxdt = dvxdxmov*Omega_v[ivorton][0] + dvxdymov*Omega_v[ivorton][1] + dvxdzmov*Omega_v[ivorton][2];
domydt = dvydxmov*Omega_v[ivorton][0] + dvydymov*Omega_v[ivorton][1] + dvydzmov*Omega_v[ivorton][2];
domzdt = dvzdxmov*Omega_v[ivorton][0] + dvzdymov*Omega_v[ivorton][1] + dvzdzmov*Omega_v[ivorton][2];
Omega_vN[ivorton][0] = Omega_v[ivorton][0] + domxdt*Delta_t;
Omega_vN[ivorton][1]= Omega_v[ivorton][1] + domydt*Delta_t;
Omega_vN[ivorton][2] = Omega_v[ivorton][2] + domzdt*Delta_t;
}
*/
Ncout = 0;
for (int ivorton = 0; ivorton < Number; ivorton++) {
Replace = 0.0;
for (int kkk = 0; kkk < 3; kkk++) {
if (VortexN[ivorton][kkk] < 0.0) {
Replace = 1.0;
}
if (VortexN[ivorton][kkk] > 1.0) {
Replace = 1.0;
}
}
if (Replace == 1.0) {
Ncout = Ncout + 1;
VortexN[ivorton][0] = (double)rand() / (double)RAND_MAX;
VortexN[ivorton][1] = (double)rand() / (double)RAND_MAX;
VortexN[ivorton][2] = (double)rand() / (double)RAND_MAX;
Omega_vN[ivorton][0] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_vN[ivorton][1] = (((double)rand() / (double)RAND_MAX) - 0.5);
Omega_vN[ivorton][2] = (((double)rand() / (double)RAND_MAX) - 0.5);
Sigma[ivorton] = Radius;
}
}
Amagni = 0.0;
for (int ivorton = 0; ivorton < Number; ivorton++) {
Vortex[ivorton][0] = VortexN[ivorton][0];
Vortex[ivorton][1] = VortexN[ivorton][1];
Vortex[ivorton][2] = VortexN[ivorton][2];
Amagnit_old = sqrt((Omega_v[ivorton][0] * Omega_v[ivorton][0]) +( Omega_v[ivorton][1] * Omega_v[ivorton][1]) +( Omega_v[ivorton][2] * Omega_v[ivorton][2]));
Omega_v[ivorton][0] = Omega_vN[ivorton][0];
Omega_v[ivorton][1] = Omega_vN[ivorton][1];
Omega_v[ivorton][2] = Omega_vN[ivorton][2];
Amagnit_new= sqrt((Omega_v[ivorton][0] * Omega_v[ivorton][0]) + (Omega_v[ivorton][1] * Omega_v[ivorton][1]) + (Omega_v[ivorton][2] * Omega_v[ivorton][2]));
Sigma[ivorton] = Sigma[ivorton] * sqrt(Amagnit_old / Amagnit_new);
if (Amagnit_new >= Amagni) {
Amagni = Amagnit_new;
Energy = (Amagnit_new*Amagnit_new)*(pow(Sigma[ivorton], 5));
Speed_max = Amagnit_new*Sigma[ivorton];
Sigmas = Sigma[ivorton];
}
}
//file write
fprintf(fp1, "%f %f %f %f %f \n", itime*Delta_t, Amagni, Energy, Speed_max, Sigmas);
Vx = 0.0;
for (int induced = 0; induced < Number; induced++) {
vxx = 0.5 - Vortex[induced][0];
vyy = 0.5 - Vortex[induced][1];
vzz = 0.5 - Vortex[induced][2];
radiika = vxx*vxx + vyy*vyy + vzz*vzz;
t1 = vyy* Omega_v[induced][2] - vzz*Omega_v[induced][1];
Om22P = 3.1416 / Sigma[induced] / Sigma[induced] / 2.0;
ssss = exp(-radiika*Om22P);
Vx = Vx + ssss*t1;
}
fprintf(fp2, "%f %f \n", itime*Delta_t, Vx);
for (int ier = 0; ier < 4; ier++) {
StatisticalMoments[ier] = StatisticalMoments[ier] +pow(Vx, ier);
}
}
hipFree(Vortex_p);
hipFree(Omega_v_p);
hipFree(VortexN_p);
hipFree(Omega_vN_p);
hipFree(Sigma_p);
fclose(fp1);
fclose(fp2);
time1 = clock();
printf("Time taken for execution with GPU acceleration (~31blocks & 32 threads)= %f sec(s)", (double)(time1 - time0) / CLOCKS_PER_SEC);
} | .text
.file "GPU_Acceleration.hip"
.globl _Z23__device_stub__SimulatePdS_S_S_S_ # -- Begin function _Z23__device_stub__SimulatePdS_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__SimulatePdS_S_S_S_,@function
_Z23__device_stub__SimulatePdS_S_S_S_: # @_Z23__device_stub__SimulatePdS_S_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8SimulatePdS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z23__device_stub__SimulatePdS_S_S_S_, .Lfunc_end0-_Z23__device_stub__SimulatePdS_S_S_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI1_1:
.quad 0xbfe0000000000000 # double -0.5
.LCPI1_2:
.quad 0x3ff0000000000000 # double 1
.LCPI1_3:
.quad 0x4014000000000000 # double 5
.LCPI1_4:
.quad 0x3f847ae147ae147b # double 0.01
.LCPI1_5:
.quad 0x3fe0000000000000 # double 0.5
.LCPI1_6:
.quad 0xc00921ff2e48e8a7 # double -3.1415999999999999
.LCPI1_7:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104328, %rsp # imm = 0x19788
.cfi_def_cfa_offset 104384
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $24000, %edi # imm = 0x5DC0
callq _Znam
movq %rax, 48(%rsp)
movl $24000, %edi # imm = 0x5DC0
callq _Znam
movq %rax, 40(%rsp)
movl $24000, %edi # imm = 0x5DC0
callq _Znam
movq %rax, 32(%rsp)
movl $24000, %edi # imm = 0x5DC0
callq _Znam
movq %rax, 24(%rsp)
xorpd %xmm0, %xmm0
movapd %xmm0, 304(%rsp)
movapd %xmm0, 288(%rsp)
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 96(%rsp) # 8-byte Spill
movl $.L.str.2, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 88(%rsp) # 8-byte Spill
leaq 48320(%rsp), %r14
movl $2, %r15d
movabsq $4591870180066957722, %rbx # imm = 0x3FB999999999999A
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 24304(%rsp,%r15,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 24312(%rsp,%r15,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 24320(%rsp,%r15,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd .LCPI1_1(%rip), %xmm0
movsd %xmm0, 304(%rsp,%r15,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd .LCPI1_1(%rip), %xmm0
movsd %xmm0, 312(%rsp,%r15,8)
callq rand
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, 320(%rsp,%r15,8)
movq %rbx, (%r14)
addq $8, %r14
addq $3, %r15
cmpq $3002, %r15 # imm = 0xBBA
jne .LBB1_1
# %bb.2: # %.preheader168
movq 48(%rsp), %rbx
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
leaq 24320(%rsp), %rsi
leaq 320(%rsp), %rdi
leaq 80320(%rsp), %r8
leaq 56320(%rsp), %r9
movq 24(%rsp), %r10
xorl %r11d, %r11d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # %.preheader167
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movslq %r14d, %r14
leaq (%rbx,%r14,8), %r12
leaq (%rcx,%r14,8), %r13
leaq (%rdx,%r14,8), %rbp
leaq (%r10,%r14,8), %rax
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rsi,%r15,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r12,%r15,8)
movsd (%rdi,%r15,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r13,%r15,8)
movsd (%r8,%r15,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rbp,%r15,8)
movsd (%r9,%r15,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rax,%r15,8)
incq %r15
cmpq $3, %r15
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
incq %r11
addq $24, %rsi
addq $24, %rdi
addq $24, %r8
addq $24, %r9
addq %r15, %r14
cmpq $1000, %r11 # imm = 0x3E8
jne .LBB1_3
# %bb.6:
movabsq $4294967327, %r14 # imm = 0x10000001F
callq clock
movq %rax, 104(%rsp) # 8-byte Spill
leaq 48(%rsp), %rdi
movl $24000, %esi # imm = 0x5DC0
callq hipMalloc
leaq 40(%rsp), %rdi
movl $24000, %esi # imm = 0x5DC0
callq hipMalloc
leaq 32(%rsp), %rdi
movl $24000, %esi # imm = 0x5DC0
callq hipMalloc
leaq 24(%rsp), %rdi
movl $24000, %esi # imm = 0x5DC0
callq hipMalloc
leaq 64(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
xorl %edx, %edx
leaq 24320(%rsp), %r12
leaq 320(%rsp), %rbp
leaq 48320(%rsp), %r13
leaq 1(%r14), %rax
movq %rax, 112(%rsp) # 8-byte Spill
xorpd %xmm0, %xmm0
movsd %xmm0, 56(%rsp) # 8-byte Spill
# implicit-def: $xmm0
# kill: killed $xmm0
# implicit-def: $xmm0
# kill: killed $xmm0
xorpd %xmm0, %xmm0
movsd %xmm0, 80(%rsp) # 8-byte Spill
movsd %xmm0, 72(%rsp) # 8-byte Spill
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # =>This Loop Header: Depth=1
# Child Loop BB1_10 Depth 2
# Child Loop BB1_11 Depth 3
# Child Loop BB1_16 Depth 2
# Child Loop BB1_29 Depth 2
# Child Loop BB1_31 Depth 2
movl $.L.str.3, %edi
movl $4, %esi
movq %rdx, 128(%rsp) # 8-byte Spill
# kill: def $edx killed $edx killed $rdx
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd 80(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movl %r15d, %ecx
movb $2, %al
callq printf
movq 48(%rsp), %rdi
movl $24000, %edx # imm = 0x5DC0
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movl $24000, %edx # imm = 0x5DC0
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $24000, %edx # imm = 0x5DC0
leaq 80320(%rsp), %r15
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $24000, %edx # imm = 0x5DC0
leaq 56320(%rsp), %r14
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq %r13, %rbx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967327, %rdi # imm = 0x10000001F
movl $1, %esi
movq 112(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 64(%rsp), %rdi
movq %rax, 232(%rsp)
movq %rcx, 224(%rsp)
movq %rdx, 216(%rsp)
movq %rsi, 208(%rsp)
movq %rdi, 200(%rsp)
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 224(%rsp), %rax
movq %rax, 248(%rsp)
leaq 216(%rsp), %rax
movq %rax, 256(%rsp)
leaq 208(%rsp), %rax
movq %rax, 264(%rsp)
leaq 200(%rsp), %rax
movq %rax, 272(%rsp)
leaq 184(%rsp), %rdi
leaq 168(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 184(%rsp), %rsi
movl 192(%rsp), %edx
movq 168(%rsp), %rcx
movl 176(%rsp), %r8d
movl $_Z8SimulatePdS_S_S_S_, %edi
leaq 240(%rsp), %r9
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
movq 48(%rsp), %rsi
movl $24000, %edx # imm = 0x5DC0
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rsi
movl $24000, %edx # imm = 0x5DC0
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rsi
movl $24000, %edx # imm = 0x5DC0
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movl $24000, %edx # imm = 0x5DC0
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 64(%rsp), %rsi
movl $8000, %edx # imm = 0x1F40
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
movq %r15, %rbp
xorl %r15d, %r15d
xorpd %xmm4, %xmm4
movsd .LCPI1_2(%rip), %xmm5 # xmm5 = mem[0],zero
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_10 Depth=2
incq %r14
addq $24, %rbp
cmpq $1000, %r14 # imm = 0x3E8
je .LBB1_15
.LBB1_10: # %.preheader
# Parent Loop BB1_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_11 Depth 3
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_7 Depth=1
# Parent Loop BB1_10 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rbp,%rax,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm1, %xmm2
cmpltsd %xmm4, %xmm2
movapd %xmm2, %xmm3
andpd %xmm5, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm3, %xmm2
movapd %xmm5, %xmm0
cmpltsd %xmm1, %xmm0
movapd %xmm0, %xmm1
andnpd %xmm2, %xmm1
andpd %xmm5, %xmm0
orpd %xmm1, %xmm0
incq %rax
cmpq $3, %rax
jne .LBB1_11
# %bb.12: # in Loop: Header=BB1_10 Depth=2
ucomisd %xmm5, %xmm0
jne .LBB1_14
jp .LBB1_14
# %bb.13: # in Loop: Header=BB1_10 Depth=2
incl %r15d
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
leaq (,%r14,8), %rax
leaq (%rax,%rax,2), %r12
movsd %xmm0, 80320(%rsp,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 80328(%rsp,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 80336(%rsp,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, 56320(%rsp,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd .LCPI1_1(%rip), %xmm0
movsd %xmm0, 56328(%rsp,%r12)
callq rand
movsd .LCPI1_2(%rip), %xmm5 # xmm5 = mem[0],zero
xorpd %xmm4, %xmm4
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd .LCPI1_1(%rip), %xmm0
movsd %xmm0, 56336(%rsp,%r12)
movq %r13, %rbx
movabsq $4591870180066957722, %rax # imm = 0x3FB999999999999A
movq %rax, 48320(%rsp,%r14,8)
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_15: # %.preheader166.preheader
# in Loop: Header=BB1_7 Depth=1
xorpd %xmm0, %xmm0
movsd %xmm0, 56(%rsp) # 8-byte Spill
xorl %ebp, %ebp
movq %rbx, %r14
jmp .LBB1_16
.p2align 4, 0x90
.LBB1_27: # in Loop: Header=BB1_16 Depth=2
addq $8, %r14
addq $24, %rbp
cmpq $24000, %rbp # imm = 0x5DC0
je .LBB1_28
.LBB1_16: # %.preheader166
# Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movsd 80320(%rsp,%rbp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 24320(%rsp,%rbp)
movups 80328(%rsp,%rbp), %xmm0
movups %xmm0, 24328(%rsp,%rbp)
movsd 320(%rsp,%rbp), %xmm0 # xmm0 = mem[0],zero
movsd 328(%rsp,%rbp), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm0
mulsd %xmm1, %xmm1
addsd %xmm0, %xmm1
movsd 336(%rsp,%rbp), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
ucomisd %xmm4, %xmm0
jb .LBB1_18
# %bb.17: # in Loop: Header=BB1_16 Depth=2
xorps %xmm3, %xmm3
sqrtsd %xmm0, %xmm3
jmp .LBB1_19
.p2align 4, 0x90
.LBB1_18: # %call.sqrt
# in Loop: Header=BB1_16 Depth=2
callq sqrt
xorpd %xmm4, %xmm4
movapd %xmm0, %xmm3
.LBB1_19: # %.preheader166.split
# in Loop: Header=BB1_16 Depth=2
movsd 56320(%rsp,%rbp), %xmm1 # xmm1 = mem[0],zero
movsd 56328(%rsp,%rbp), %xmm2 # xmm2 = mem[0],zero
movsd %xmm1, 320(%rsp,%rbp)
movsd %xmm2, 328(%rsp,%rbp)
movsd 56336(%rsp,%rbp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 336(%rsp,%rbp)
mulsd %xmm1, %xmm1
mulsd %xmm2, %xmm2
addsd %xmm1, %xmm2
mulsd %xmm0, %xmm0
addsd %xmm2, %xmm0
ucomisd %xmm4, %xmm0
jb .LBB1_21
# %bb.20: # in Loop: Header=BB1_16 Depth=2
xorps %xmm1, %xmm1
sqrtsd %xmm0, %xmm1
jmp .LBB1_22
.p2align 4, 0x90
.LBB1_21: # %call.sqrt307
# in Loop: Header=BB1_16 Depth=2
movsd %xmm3, 8(%rsp) # 8-byte Spill
callq sqrt
movsd 8(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
xorpd %xmm4, %xmm4
movapd %xmm0, %xmm1
.LBB1_22: # %.preheader166.split.split
# in Loop: Header=BB1_16 Depth=2
movsd (%r14), %xmm2 # xmm2 = mem[0],zero
divsd %xmm1, %xmm3
ucomisd %xmm4, %xmm3
movsd %xmm1, 8(%rsp) # 8-byte Spill
jb .LBB1_24
# %bb.23: # in Loop: Header=BB1_16 Depth=2
xorps %xmm0, %xmm0
sqrtsd %xmm3, %xmm0
jmp .LBB1_25
.p2align 4, 0x90
.LBB1_24: # %call.sqrt308
# in Loop: Header=BB1_16 Depth=2
movapd %xmm3, %xmm0
movsd %xmm2, 16(%rsp) # 8-byte Spill
callq sqrt
movsd 16(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
xorpd %xmm4, %xmm4
.LBB1_25: # %.preheader166.split.split.split
# in Loop: Header=BB1_16 Depth=2
mulsd %xmm0, %xmm2
movsd %xmm2, (%r14)
ucomisd 56(%rsp), %xmm1 # 8-byte Folded Reload
jb .LBB1_27
# %bb.26: # in Loop: Header=BB1_16 Depth=2
movapd %xmm1, %xmm0
mulsd %xmm1, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movapd %xmm2, %xmm0
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
xorpd %xmm4, %xmm4
mulsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 80(%rsp) # 8-byte Spill
movsd (%r14), %xmm0 # xmm0 = mem[0],zero
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movapd %xmm2, %xmm1
movsd %xmm0, 144(%rsp) # 8-byte Spill
mulsd %xmm0, %xmm1
movsd %xmm1, 136(%rsp) # 8-byte Spill
movsd %xmm2, 56(%rsp) # 8-byte Spill
jmp .LBB1_27
.p2align 4, 0x90
.LBB1_28: # in Loop: Header=BB1_7 Depth=1
movsd 72(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI1_4(%rip), %xmm0
movl $.L.str.4, %esi
movq 96(%rsp), %rdi # 8-byte Reload
movsd %xmm0, 120(%rsp) # 8-byte Spill
movsd 56(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movsd 80(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movsd 136(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movsd 144(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
movb $5, %al
callq fprintf
xorpd %xmm0, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $2, %r14d
.p2align 4, 0x90
.LBB1_29: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movsd .LCPI1_5(%rip), %xmm4 # xmm4 = mem[0],zero
movapd %xmm4, %xmm0
subsd 24304(%rsp,%r14,8), %xmm0
movapd %xmm4, %xmm5
subsd 24312(%rsp,%r14,8), %xmm5
movapd %xmm4, %xmm1
subsd 24320(%rsp,%r14,8), %xmm1
mulsd %xmm0, %xmm0
movapd %xmm5, %xmm2
mulsd %xmm5, %xmm2
addsd %xmm0, %xmm2
movapd %xmm1, %xmm3
mulsd %xmm1, %xmm3
mulsd 320(%rsp,%r14,8), %xmm5
mulsd 312(%rsp,%r14,8), %xmm1
addsd %xmm2, %xmm3
subsd %xmm1, %xmm5
movsd %xmm5, 16(%rsp) # 8-byte Spill
movsd (%rbx), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI1_6(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
divsd %xmm1, %xmm0
mulsd %xmm4, %xmm0
mulsd %xmm3, %xmm0
callq exp
mulsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
addq $8, %rbx
addq $3, %r14
cmpq $3002, %r14 # imm = 0xBBA
jne .LBB1_29
# %bb.30: # in Loop: Header=BB1_7 Depth=1
movl $.L.str.5, %esi
movq 88(%rsp), %rdi # 8-byte Reload
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movb $2, %al
callq fprintf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_31: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movsd 288(%rsp,%r14,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 16(%rsp) # 8-byte Spill
xorps %xmm1, %xmm1
cvtsi2sd %r14d, %xmm1
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq pow
addsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 288(%rsp,%r14,8)
incq %r14
cmpq $4, %r14
jne .LBB1_31
# %bb.32: # in Loop: Header=BB1_7 Depth=1
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
movsd 72(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 72(%rsp) # 8-byte Spill
movq 128(%rsp), %rdx # 8-byte Reload
incl %edx
cmpl $10000, %edx # imm = 0x2710
leaq 24320(%rsp), %r12
leaq 320(%rsp), %rbp
jne .LBB1_7
# %bb.33:
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 96(%rsp), %rdi # 8-byte Reload
callq fclose
movq 88(%rsp), %rdi # 8-byte Reload
callq fclose
callq clock
subq 104(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_7(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $104328, %rsp # imm = 0x19788
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8SimulatePdS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8SimulatePdS_S_S_S_,@object # @_Z8SimulatePdS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z8SimulatePdS_S_S_S_
.p2align 3, 0x0
_Z8SimulatePdS_S_S_S_:
.quad _Z23__device_stub__SimulatePdS_S_S_S_
.size _Z8SimulatePdS_S_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "D:\\cudaa\\Velocities1.txt"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w+"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "D:\\cudaa\\MaxValue1.txt"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%*d %f %e %d \n "
.size .L.str.3, 16
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%f %f %f %f %f \n"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f %f \n"
.size .L.str.5, 8
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time taken for execution with GPU acceleration (~31blocks & 32 threads)= %f sec(s)"
.size .L.str.6, 83
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8SimulatePdS_S_S_S_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__SimulatePdS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8SimulatePdS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002b42f_00000000-6_GPU_Acceleration.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z8SimulatePdS_S_S_S_PdS_S_S_S_
.type _Z35__device_stub__Z8SimulatePdS_S_S_S_PdS_S_S_S_, @function
_Z35__device_stub__Z8SimulatePdS_S_S_S_PdS_S_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8SimulatePdS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z8SimulatePdS_S_S_S_PdS_S_S_S_, .-_Z35__device_stub__Z8SimulatePdS_S_S_S_PdS_S_S_S_
.globl _Z8SimulatePdS_S_S_S_
.type _Z8SimulatePdS_S_S_S_, @function
_Z8SimulatePdS_S_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8SimulatePdS_S_S_S_PdS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8SimulatePdS_S_S_S_, .-_Z8SimulatePdS_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "w+"
.LC3:
.string "D:\\cudaa\\Velocities1.txt"
.LC4:
.string "D:\\cudaa\\MaxValue1.txt"
.LC8:
.string "%*d %f %e %d \n "
.LC11:
.string "%f %f %f %f %f \n"
.LC14:
.string "%f %f \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC18:
.string "Time taken for execution with GPU acceleration (~31blocks & 32 threads)= %f sec(s)"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -102400(%rsp), %r11
.cfi_def_cfa 11, 102456
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1800, %rsp
.cfi_def_cfa_offset 104256
movq %fs:40, %rax
movq %rax, 104184(%rsp)
xorl %eax, %eax
movl $24000, %edi
call _Znam@PLT
movq %rax, 112(%rsp)
movl $24000, %edi
call _Znam@PLT
movq %rax, 120(%rsp)
movl $24000, %edi
call _Znam@PLT
movq %rax, 128(%rsp)
movl $24000, %edi
call _Znam@PLT
movq %rax, 136(%rsp)
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, 72(%rsp)
movq %rbx, %rsi
leaq .LC4(%rip), %rdi
call fopen@PLT
movq %rax, 80(%rsp)
leaq 8176(%rsp), %rbx
movq %rbx, 88(%rsp)
leaq 32176(%rsp), %rbp
movq %rbp, 96(%rsp)
leaq 176(%rsp), %rax
movq %rax, 56(%rsp)
movq %rbp, %r13
movq %rax, %r12
movq .LC7(%rip), %r14
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
movsd %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
movsd %xmm0, 8(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
movsd %xmm0, 16(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
subsd .LC6(%rip), %xmm0
movsd %xmm0, 0(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
subsd .LC6(%rip), %xmm0
movsd %xmm0, 8(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
subsd .LC6(%rip), %xmm0
movsd %xmm0, 16(%rbp)
movq %r14, (%r12)
addq $24, %rbx
addq $24, %rbp
addq $8, %r12
cmpq %r13, %rbx
jne .L12
movl $24, %esi
movl $0, %edi
movl $0, %r8d
jmp .L13
.L45:
addl $3, %r8d
addq $24, %rdi
addq $24, %rsi
cmpl $3000, %r8d
je .L15
.L13:
movq %rdi, %rdx
movq %rdi, %rax
.L14:
movsd 8176(%rsp,%rdx), %xmm0
movq 112(%rsp), %rcx
movsd %xmm0, (%rcx,%rax)
movsd 32176(%rsp,%rdx), %xmm0
movq 120(%rsp), %rcx
movsd %xmm0, (%rcx,%rax)
movsd 56176(%rsp,%rdx), %xmm0
movq 128(%rsp), %rcx
movsd %xmm0, (%rcx,%rax)
movsd 80176(%rsp,%rdx), %xmm0
movq 136(%rsp), %rcx
movsd %xmm0, (%rcx,%rax)
addq $8, %rax
addq $8, %rdx
cmpq %rsi, %rax
jne .L14
jmp .L45
.L15:
call clock@PLT
movq %rax, %rbx
leaq 112(%rsp), %rdi
movl $24000, %esi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movl $24000, %esi
call cudaMalloc@PLT
leaq 128(%rsp), %rdi
movl $24000, %esi
call cudaMalloc@PLT
leaq 136(%rsp), %rdi
movl $24000, %esi
call cudaMalloc@PLT
leaq 144(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
movl $0, 64(%rsp)
movl $0, 68(%rsp)
movq $0x000000000, 32(%rsp)
movq $0x000000000, 16(%rsp)
leaq 80176(%rsp), %r15
movq %rbx, 104(%rsp)
jmp .L29
.L50:
movq 144(%rsp), %r8
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
movq 120(%rsp), %rsi
movq 112(%rsp), %rdi
call _Z35__device_stub__Z8SimulatePdS_S_S_S_PdS_S_S_S_
jmp .L16
.L31:
movsd .LC1(%rip), %xmm0
.L18:
addq $1, %rax
cmpq $3, %rax
je .L46
.L19:
movsd (%rbx,%rax,8), %xmm1
pxor %xmm5, %xmm5
comisd %xmm1, %xmm5
ja .L31
movsd .LC1(%rip), %xmm2
cmpnltsd %xmm1, %xmm2
andpd %xmm2, %xmm0
movsd .LC1(%rip), %xmm6
andnpd %xmm6, %xmm2
orpd %xmm2, %xmm0
jmp .L18
.L46:
ucomisd .LC1(%rip), %xmm0
jp .L20
je .L47
.L20:
addq $24, %rbx
addq $24, %r12
addq $8, %r14
cmpq %rbx, %r15
je .L33
.L17:
movl $0, %eax
pxor %xmm0, %xmm0
movq %rbx, %rbp
jmp .L19
.L47:
addl $1, %r13d
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
movsd %xmm0, 0(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
movsd %xmm0, 8(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
movsd %xmm0, 16(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
subsd .LC6(%rip), %xmm0
movsd %xmm0, (%r12)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
subsd .LC6(%rip), %xmm0
movsd %xmm0, 8(%r12)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
subsd .LC6(%rip), %xmm0
movsd %xmm0, 16(%r12)
movq .LC7(%rip), %rax
movq %rax, (%r14)
jmp .L20
.L33:
movl %r13d, 68(%rsp)
movq 8(%rsp), %r13
movq 56(%rsp), %r14
movq 96(%rsp), %rbx
movq 88(%rsp), %r12
movq $0x000000000, 16(%rsp)
movq (%rsp), %rbp
movq %r15, 24(%rsp)
movq %r14, %r15
jmp .L22
.L43:
call sqrt@PLT
jmp .L25
.L26:
addq $24, %rbp
addq $24, %r12
addq $24, %rbx
addq $24, %r13
addq $8, %r15
movq 24(%rsp), %rax
cmpq %rax, %rbp
je .L48
.L22:
movsd 0(%rbp), %xmm0
movsd %xmm0, (%r12)
movsd 8(%rbp), %xmm0
movsd %xmm0, 8(%r12)
movsd 16(%rbp), %xmm0
movsd %xmm0, 16(%r12)
movsd (%rbx), %xmm1
movsd 8(%rbx), %xmm2
movsd 16(%rbx), %xmm0
mulsd %xmm1, %xmm1
mulsd %xmm2, %xmm2
addsd %xmm2, %xmm1
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
sqrtsd %xmm0, %xmm0
movsd 0(%r13), %xmm1
movsd %xmm1, (%rbx)
movsd 8(%r13), %xmm3
movsd %xmm3, 8(%rbx)
movsd 16(%r13), %xmm2
movsd %xmm2, 16(%rbx)
mulsd %xmm1, %xmm1
mulsd %xmm3, %xmm3
addsd %xmm3, %xmm1
mulsd %xmm2, %xmm2
addsd %xmm2, %xmm1
sqrtsd %xmm1, %xmm1
movsd %xmm1, (%rsp)
movq %r15, 8(%rsp)
movq (%r15), %r14
divsd %xmm1, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L43
sqrtsd %xmm0, %xmm0
.L25:
movq %r14, %xmm7
mulsd %xmm0, %xmm7
movq %xmm7, %r14
movq 8(%rsp), %rax
movsd %xmm7, (%rax)
movsd (%rsp), %xmm7
comisd 16(%rsp), %xmm7
jb .L26
movsd .LC9(%rip), %xmm1
movq %r14, %xmm0
call pow@PLT
movsd (%rsp), %xmm6
movapd %xmm6, %xmm1
mulsd %xmm6, %xmm1
mulsd %xmm0, %xmm1
movsd %xmm1, 32(%rsp)
movq %r14, %xmm5
mulsd %xmm6, %xmm5
movsd %xmm5, 40(%rsp)
movq %r14, 48(%rsp)
movsd %xmm6, 16(%rsp)
jmp .L26
.L48:
movq %rax, %r15
pxor %xmm0, %xmm0
cvtsi2sdl 64(%rsp), %xmm0
mulsd .LC10(%rip), %xmm0
movq %xmm0, %r13
movsd 48(%rsp), %xmm4
movsd 40(%rsp), %xmm3
movsd 32(%rsp), %xmm2
movsd 16(%rsp), %xmm1
leaq .LC11(%rip), %rdx
movl $2, %esi
movq 72(%rsp), %rdi
movl $5, %eax
call __fprintf_chk@PLT
movq 56(%rsp), %rbp
movl $0, %ebx
movq $0x000000000, (%rsp)
leaq 8176(%rsp), %r12
.L28:
movsd .LC6(%rip), %xmm0
subsd (%rbx,%r12), %xmm0
movsd .LC6(%rip), %xmm2
subsd 8184(%rsp,%rbx), %xmm2
movsd .LC6(%rip), %xmm1
subsd 8192(%rsp,%rbx), %xmm1
movapd %xmm2, %xmm4
mulsd 32192(%rsp,%rbx), %xmm4
movapd %xmm1, %xmm3
mulsd 32184(%rsp,%rbx), %xmm3
subsd %xmm3, %xmm4
movsd %xmm4, 8(%rsp)
movsd 0(%rbp), %xmm3
mulsd %xmm0, %xmm0
mulsd %xmm2, %xmm2
addsd %xmm2, %xmm0
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
xorpd .LC12(%rip), %xmm0
movsd .LC13(%rip), %xmm1
divsd %xmm3, %xmm1
divsd %xmm3, %xmm1
mulsd .LC6(%rip), %xmm1
mulsd %xmm1, %xmm0
call exp@PLT
mulsd 8(%rsp), %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
addq $8, %rbp
addq $24, %rbx
cmpq $24000, %rbx
jne .L28
movapd %xmm0, %xmm1
movq %r13, %xmm0
leaq .LC14(%rip), %rdx
movl $2, %esi
movq 80(%rsp), %rdi
movl $2, %eax
call __fprintf_chk@PLT
pxor %xmm1, %xmm1
movsd (%rsp), %xmm0
call pow@PLT
movsd .LC1(%rip), %xmm1
movsd (%rsp), %xmm0
call pow@PLT
movsd .LC15(%rip), %xmm1
movsd (%rsp), %xmm0
call pow@PLT
movsd .LC16(%rip), %xmm1
movsd (%rsp), %xmm0
call pow@PLT
addl $1, 64(%rsp)
movl 64(%rsp), %eax
cmpl $10000, %eax
je .L49
.L29:
movl 68(%rsp), %r8d
movsd 32(%rsp), %xmm1
movsd 16(%rsp), %xmm0
movl 64(%rsp), %ecx
movl $4, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq 8176(%rsp), %rsi
movl $1, %ecx
movl $24000, %edx
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32176(%rsp), %rsi
movl $1, %ecx
movl $24000, %edx
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
leaq 56176(%rsp), %rsi
movl $1, %ecx
movl $24000, %edx
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $24000, %edx
movq %r15, %rsi
movq 136(%rsp), %rdi
call cudaMemcpy@PLT
leaq 176(%rsp), %rsi
movl $1, %ecx
movl $8000, %edx
movq 144(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $31, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L16:
leaq 8176(%rsp), %rdi
movl $2, %ecx
movl $24000, %edx
movq 112(%rsp), %rsi
call cudaMemcpy@PLT
leaq 32176(%rsp), %rdi
movl $2, %ecx
movl $24000, %edx
movq 120(%rsp), %rsi
call cudaMemcpy@PLT
leaq 56176(%rsp), %rbx
movl $2, %ecx
movl $24000, %edx
movq 128(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $24000, %edx
movq 136(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq 176(%rsp), %rdi
movl $2, %ecx
movl $8000, %edx
movq 144(%rsp), %rsi
call cudaMemcpy@PLT
movq %rbx, (%rsp)
movq 56(%rsp), %r14
movq %r15, %r12
movl $0, %eax
movq %r15, 8(%rsp)
movl %eax, %r13d
jmp .L17
.L49:
movq 104(%rsp), %rbx
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 144(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call fclose@PLT
movq 80(%rsp), %rdi
call fclose@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC17(%rip), %xmm0
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 104184(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $104200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z8SimulatePdS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z8SimulatePdS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC5:
.long -4194304
.long 1105199103
.align 8
.LC6:
.long 0
.long 1071644672
.align 8
.LC7:
.long -1717986918
.long 1069128089
.align 8
.LC9:
.long 0
.long 1075052544
.align 8
.LC10:
.long 1202590843
.long 1065646817
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC12:
.long 0
.long -2147483648
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC13:
.long 776530087
.long 1074340351
.align 8
.LC15:
.long 0
.long 1073741824
.align 8
.LC16:
.long 0
.long 1074266112
.align 8
.LC17:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "GPU_Acceleration.hip"
.globl _Z23__device_stub__SimulatePdS_S_S_S_ # -- Begin function _Z23__device_stub__SimulatePdS_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__SimulatePdS_S_S_S_,@function
_Z23__device_stub__SimulatePdS_S_S_S_: # @_Z23__device_stub__SimulatePdS_S_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8SimulatePdS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z23__device_stub__SimulatePdS_S_S_S_, .Lfunc_end0-_Z23__device_stub__SimulatePdS_S_S_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI1_1:
.quad 0xbfe0000000000000 # double -0.5
.LCPI1_2:
.quad 0x3ff0000000000000 # double 1
.LCPI1_3:
.quad 0x4014000000000000 # double 5
.LCPI1_4:
.quad 0x3f847ae147ae147b # double 0.01
.LCPI1_5:
.quad 0x3fe0000000000000 # double 0.5
.LCPI1_6:
.quad 0xc00921ff2e48e8a7 # double -3.1415999999999999
.LCPI1_7:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104328, %rsp # imm = 0x19788
.cfi_def_cfa_offset 104384
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $24000, %edi # imm = 0x5DC0
callq _Znam
movq %rax, 48(%rsp)
movl $24000, %edi # imm = 0x5DC0
callq _Znam
movq %rax, 40(%rsp)
movl $24000, %edi # imm = 0x5DC0
callq _Znam
movq %rax, 32(%rsp)
movl $24000, %edi # imm = 0x5DC0
callq _Znam
movq %rax, 24(%rsp)
xorpd %xmm0, %xmm0
movapd %xmm0, 304(%rsp)
movapd %xmm0, 288(%rsp)
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 96(%rsp) # 8-byte Spill
movl $.L.str.2, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 88(%rsp) # 8-byte Spill
leaq 48320(%rsp), %r14
movl $2, %r15d
movabsq $4591870180066957722, %rbx # imm = 0x3FB999999999999A
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 24304(%rsp,%r15,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 24312(%rsp,%r15,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 24320(%rsp,%r15,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd .LCPI1_1(%rip), %xmm0
movsd %xmm0, 304(%rsp,%r15,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd .LCPI1_1(%rip), %xmm0
movsd %xmm0, 312(%rsp,%r15,8)
callq rand
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, 320(%rsp,%r15,8)
movq %rbx, (%r14)
addq $8, %r14
addq $3, %r15
cmpq $3002, %r15 # imm = 0xBBA
jne .LBB1_1
# %bb.2: # %.preheader168
movq 48(%rsp), %rbx
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
leaq 24320(%rsp), %rsi
leaq 320(%rsp), %rdi
leaq 80320(%rsp), %r8
leaq 56320(%rsp), %r9
movq 24(%rsp), %r10
xorl %r11d, %r11d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # %.preheader167
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movslq %r14d, %r14
leaq (%rbx,%r14,8), %r12
leaq (%rcx,%r14,8), %r13
leaq (%rdx,%r14,8), %rbp
leaq (%r10,%r14,8), %rax
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rsi,%r15,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r12,%r15,8)
movsd (%rdi,%r15,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r13,%r15,8)
movsd (%r8,%r15,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rbp,%r15,8)
movsd (%r9,%r15,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rax,%r15,8)
incq %r15
cmpq $3, %r15
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
incq %r11
addq $24, %rsi
addq $24, %rdi
addq $24, %r8
addq $24, %r9
addq %r15, %r14
cmpq $1000, %r11 # imm = 0x3E8
jne .LBB1_3
# %bb.6:
movabsq $4294967327, %r14 # imm = 0x10000001F
callq clock
movq %rax, 104(%rsp) # 8-byte Spill
leaq 48(%rsp), %rdi
movl $24000, %esi # imm = 0x5DC0
callq hipMalloc
leaq 40(%rsp), %rdi
movl $24000, %esi # imm = 0x5DC0
callq hipMalloc
leaq 32(%rsp), %rdi
movl $24000, %esi # imm = 0x5DC0
callq hipMalloc
leaq 24(%rsp), %rdi
movl $24000, %esi # imm = 0x5DC0
callq hipMalloc
leaq 64(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
xorl %edx, %edx
leaq 24320(%rsp), %r12
leaq 320(%rsp), %rbp
leaq 48320(%rsp), %r13
leaq 1(%r14), %rax
movq %rax, 112(%rsp) # 8-byte Spill
xorpd %xmm0, %xmm0
movsd %xmm0, 56(%rsp) # 8-byte Spill
# implicit-def: $xmm0
# kill: killed $xmm0
# implicit-def: $xmm0
# kill: killed $xmm0
xorpd %xmm0, %xmm0
movsd %xmm0, 80(%rsp) # 8-byte Spill
movsd %xmm0, 72(%rsp) # 8-byte Spill
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # =>This Loop Header: Depth=1
# Child Loop BB1_10 Depth 2
# Child Loop BB1_11 Depth 3
# Child Loop BB1_16 Depth 2
# Child Loop BB1_29 Depth 2
# Child Loop BB1_31 Depth 2
movl $.L.str.3, %edi
movl $4, %esi
movq %rdx, 128(%rsp) # 8-byte Spill
# kill: def $edx killed $edx killed $rdx
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd 80(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movl %r15d, %ecx
movb $2, %al
callq printf
movq 48(%rsp), %rdi
movl $24000, %edx # imm = 0x5DC0
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movl $24000, %edx # imm = 0x5DC0
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $24000, %edx # imm = 0x5DC0
leaq 80320(%rsp), %r15
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $24000, %edx # imm = 0x5DC0
leaq 56320(%rsp), %r14
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq %r13, %rbx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967327, %rdi # imm = 0x10000001F
movl $1, %esi
movq 112(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 64(%rsp), %rdi
movq %rax, 232(%rsp)
movq %rcx, 224(%rsp)
movq %rdx, 216(%rsp)
movq %rsi, 208(%rsp)
movq %rdi, 200(%rsp)
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 224(%rsp), %rax
movq %rax, 248(%rsp)
leaq 216(%rsp), %rax
movq %rax, 256(%rsp)
leaq 208(%rsp), %rax
movq %rax, 264(%rsp)
leaq 200(%rsp), %rax
movq %rax, 272(%rsp)
leaq 184(%rsp), %rdi
leaq 168(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 184(%rsp), %rsi
movl 192(%rsp), %edx
movq 168(%rsp), %rcx
movl 176(%rsp), %r8d
movl $_Z8SimulatePdS_S_S_S_, %edi
leaq 240(%rsp), %r9
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
movq 48(%rsp), %rsi
movl $24000, %edx # imm = 0x5DC0
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rsi
movl $24000, %edx # imm = 0x5DC0
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rsi
movl $24000, %edx # imm = 0x5DC0
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movl $24000, %edx # imm = 0x5DC0
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 64(%rsp), %rsi
movl $8000, %edx # imm = 0x1F40
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
movq %r15, %rbp
xorl %r15d, %r15d
xorpd %xmm4, %xmm4
movsd .LCPI1_2(%rip), %xmm5 # xmm5 = mem[0],zero
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_10 Depth=2
incq %r14
addq $24, %rbp
cmpq $1000, %r14 # imm = 0x3E8
je .LBB1_15
.LBB1_10: # %.preheader
# Parent Loop BB1_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_11 Depth 3
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_7 Depth=1
# Parent Loop BB1_10 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rbp,%rax,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm1, %xmm2
cmpltsd %xmm4, %xmm2
movapd %xmm2, %xmm3
andpd %xmm5, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm3, %xmm2
movapd %xmm5, %xmm0
cmpltsd %xmm1, %xmm0
movapd %xmm0, %xmm1
andnpd %xmm2, %xmm1
andpd %xmm5, %xmm0
orpd %xmm1, %xmm0
incq %rax
cmpq $3, %rax
jne .LBB1_11
# %bb.12: # in Loop: Header=BB1_10 Depth=2
ucomisd %xmm5, %xmm0
jne .LBB1_14
jp .LBB1_14
# %bb.13: # in Loop: Header=BB1_10 Depth=2
incl %r15d
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
leaq (,%r14,8), %rax
leaq (%rax,%rax,2), %r12
movsd %xmm0, 80320(%rsp,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 80328(%rsp,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 80336(%rsp,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, 56320(%rsp,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd .LCPI1_1(%rip), %xmm0
movsd %xmm0, 56328(%rsp,%r12)
callq rand
movsd .LCPI1_2(%rip), %xmm5 # xmm5 = mem[0],zero
xorpd %xmm4, %xmm4
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd .LCPI1_1(%rip), %xmm0
movsd %xmm0, 56336(%rsp,%r12)
movq %r13, %rbx
movabsq $4591870180066957722, %rax # imm = 0x3FB999999999999A
movq %rax, 48320(%rsp,%r14,8)
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_15: # %.preheader166.preheader
# in Loop: Header=BB1_7 Depth=1
xorpd %xmm0, %xmm0
movsd %xmm0, 56(%rsp) # 8-byte Spill
xorl %ebp, %ebp
movq %rbx, %r14
jmp .LBB1_16
.p2align 4, 0x90
.LBB1_27: # in Loop: Header=BB1_16 Depth=2
addq $8, %r14
addq $24, %rbp
cmpq $24000, %rbp # imm = 0x5DC0
je .LBB1_28
.LBB1_16: # %.preheader166
# Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movsd 80320(%rsp,%rbp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 24320(%rsp,%rbp)
movups 80328(%rsp,%rbp), %xmm0
movups %xmm0, 24328(%rsp,%rbp)
movsd 320(%rsp,%rbp), %xmm0 # xmm0 = mem[0],zero
movsd 328(%rsp,%rbp), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm0
mulsd %xmm1, %xmm1
addsd %xmm0, %xmm1
movsd 336(%rsp,%rbp), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
ucomisd %xmm4, %xmm0
jb .LBB1_18
# %bb.17: # in Loop: Header=BB1_16 Depth=2
xorps %xmm3, %xmm3
sqrtsd %xmm0, %xmm3
jmp .LBB1_19
.p2align 4, 0x90
.LBB1_18: # %call.sqrt
# in Loop: Header=BB1_16 Depth=2
callq sqrt
xorpd %xmm4, %xmm4
movapd %xmm0, %xmm3
.LBB1_19: # %.preheader166.split
# in Loop: Header=BB1_16 Depth=2
movsd 56320(%rsp,%rbp), %xmm1 # xmm1 = mem[0],zero
movsd 56328(%rsp,%rbp), %xmm2 # xmm2 = mem[0],zero
movsd %xmm1, 320(%rsp,%rbp)
movsd %xmm2, 328(%rsp,%rbp)
movsd 56336(%rsp,%rbp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 336(%rsp,%rbp)
mulsd %xmm1, %xmm1
mulsd %xmm2, %xmm2
addsd %xmm1, %xmm2
mulsd %xmm0, %xmm0
addsd %xmm2, %xmm0
ucomisd %xmm4, %xmm0
jb .LBB1_21
# %bb.20: # in Loop: Header=BB1_16 Depth=2
xorps %xmm1, %xmm1
sqrtsd %xmm0, %xmm1
jmp .LBB1_22
.p2align 4, 0x90
.LBB1_21: # %call.sqrt307
# in Loop: Header=BB1_16 Depth=2
movsd %xmm3, 8(%rsp) # 8-byte Spill
callq sqrt
movsd 8(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
xorpd %xmm4, %xmm4
movapd %xmm0, %xmm1
.LBB1_22: # %.preheader166.split.split
# in Loop: Header=BB1_16 Depth=2
movsd (%r14), %xmm2 # xmm2 = mem[0],zero
divsd %xmm1, %xmm3
ucomisd %xmm4, %xmm3
movsd %xmm1, 8(%rsp) # 8-byte Spill
jb .LBB1_24
# %bb.23: # in Loop: Header=BB1_16 Depth=2
xorps %xmm0, %xmm0
sqrtsd %xmm3, %xmm0
jmp .LBB1_25
.p2align 4, 0x90
.LBB1_24: # %call.sqrt308
# in Loop: Header=BB1_16 Depth=2
movapd %xmm3, %xmm0
movsd %xmm2, 16(%rsp) # 8-byte Spill
callq sqrt
movsd 16(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
xorpd %xmm4, %xmm4
.LBB1_25: # %.preheader166.split.split.split
# in Loop: Header=BB1_16 Depth=2
mulsd %xmm0, %xmm2
movsd %xmm2, (%r14)
ucomisd 56(%rsp), %xmm1 # 8-byte Folded Reload
jb .LBB1_27
# %bb.26: # in Loop: Header=BB1_16 Depth=2
movapd %xmm1, %xmm0
mulsd %xmm1, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movapd %xmm2, %xmm0
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
xorpd %xmm4, %xmm4
mulsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 80(%rsp) # 8-byte Spill
movsd (%r14), %xmm0 # xmm0 = mem[0],zero
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movapd %xmm2, %xmm1
movsd %xmm0, 144(%rsp) # 8-byte Spill
mulsd %xmm0, %xmm1
movsd %xmm1, 136(%rsp) # 8-byte Spill
movsd %xmm2, 56(%rsp) # 8-byte Spill
jmp .LBB1_27
.p2align 4, 0x90
.LBB1_28: # in Loop: Header=BB1_7 Depth=1
movsd 72(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI1_4(%rip), %xmm0
movl $.L.str.4, %esi
movq 96(%rsp), %rdi # 8-byte Reload
movsd %xmm0, 120(%rsp) # 8-byte Spill
movsd 56(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movsd 80(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movsd 136(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movsd 144(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
movb $5, %al
callq fprintf
xorpd %xmm0, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $2, %r14d
.p2align 4, 0x90
.LBB1_29: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movsd .LCPI1_5(%rip), %xmm4 # xmm4 = mem[0],zero
movapd %xmm4, %xmm0
subsd 24304(%rsp,%r14,8), %xmm0
movapd %xmm4, %xmm5
subsd 24312(%rsp,%r14,8), %xmm5
movapd %xmm4, %xmm1
subsd 24320(%rsp,%r14,8), %xmm1
mulsd %xmm0, %xmm0
movapd %xmm5, %xmm2
mulsd %xmm5, %xmm2
addsd %xmm0, %xmm2
movapd %xmm1, %xmm3
mulsd %xmm1, %xmm3
mulsd 320(%rsp,%r14,8), %xmm5
mulsd 312(%rsp,%r14,8), %xmm1
addsd %xmm2, %xmm3
subsd %xmm1, %xmm5
movsd %xmm5, 16(%rsp) # 8-byte Spill
movsd (%rbx), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI1_6(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
divsd %xmm1, %xmm0
mulsd %xmm4, %xmm0
mulsd %xmm3, %xmm0
callq exp
mulsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
addq $8, %rbx
addq $3, %r14
cmpq $3002, %r14 # imm = 0xBBA
jne .LBB1_29
# %bb.30: # in Loop: Header=BB1_7 Depth=1
movl $.L.str.5, %esi
movq 88(%rsp), %rdi # 8-byte Reload
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movb $2, %al
callq fprintf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_31: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movsd 288(%rsp,%r14,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 16(%rsp) # 8-byte Spill
xorps %xmm1, %xmm1
cvtsi2sd %r14d, %xmm1
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq pow
addsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 288(%rsp,%r14,8)
incq %r14
cmpq $4, %r14
jne .LBB1_31
# %bb.32: # in Loop: Header=BB1_7 Depth=1
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
movsd 72(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 72(%rsp) # 8-byte Spill
movq 128(%rsp), %rdx # 8-byte Reload
incl %edx
cmpl $10000, %edx # imm = 0x2710
leaq 24320(%rsp), %r12
leaq 320(%rsp), %rbp
jne .LBB1_7
# %bb.33:
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 96(%rsp), %rdi # 8-byte Reload
callq fclose
movq 88(%rsp), %rdi # 8-byte Reload
callq fclose
callq clock
subq 104(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_7(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $104328, %rsp # imm = 0x19788
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8SimulatePdS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8SimulatePdS_S_S_S_,@object # @_Z8SimulatePdS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z8SimulatePdS_S_S_S_
.p2align 3, 0x0
_Z8SimulatePdS_S_S_S_:
.quad _Z23__device_stub__SimulatePdS_S_S_S_
.size _Z8SimulatePdS_S_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "D:\\cudaa\\Velocities1.txt"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w+"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "D:\\cudaa\\MaxValue1.txt"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%*d %f %e %d \n "
.size .L.str.3, 16
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%f %f %f %f %f \n"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f %f \n"
.size .L.str.5, 8
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time taken for execution with GPU acceleration (~31blocks & 32 threads)= %f sec(s)"
.size .L.str.6, 83
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8SimulatePdS_S_S_S_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__SimulatePdS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8SimulatePdS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void cal(int *a, int *b, int x1)
{
int i = blockIdx.x;
b[i] = x1 * a[i] + b[i];
}
int main()
{
int a[20], b[20];
int n, i;
printf("Enter size");
scanf("%d",&n);
printf("\nEnter set 1 \n");
for(i = 0; i < n; i++)
scanf("%d", &a[i]);
printf("Enter set 2 \n");
for(i = 0; i < n; i++)
scanf("%d", &b[i]);
int alpha;
printf("Enter AA ");
scanf("%d", &alpha);
int *d_a, *d_b, *d_c, *d_d, *d_e;
int size = sizeof(int) * 20;
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
cudaMalloc((void**)&d_d, size);
cudaMalloc((void**)&d_e, size);
cudaMemcpy(d_a, &a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &b, size, cudaMemcpyHostToDevice);
cal<<<n, 1>>>(d_a, d_b, alpha);
cudaMemcpy(&b, d_b, size, cudaMemcpyDeviceToHost);
printf("\nExpansion res \n");
for(i = 0; i < n; i++)
printf("%d ", b[i]);
printf("\n");
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | code for sm_80
Function : _Z3calPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fc800078e0205 */
/*0050*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe400078e0205 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IMAD R7, R2, c[0x0][0x170], R7 ; /* 0x00005c0002077a24 */
/* 0x004fca00078e0207 */
/*0090*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void cal(int *a, int *b, int x1)
{
int i = blockIdx.x;
b[i] = x1 * a[i] + b[i];
}
int main()
{
int a[20], b[20];
int n, i;
printf("Enter size");
scanf("%d",&n);
printf("\nEnter set 1 \n");
for(i = 0; i < n; i++)
scanf("%d", &a[i]);
printf("Enter set 2 \n");
for(i = 0; i < n; i++)
scanf("%d", &b[i]);
int alpha;
printf("Enter AA ");
scanf("%d", &alpha);
int *d_a, *d_b, *d_c, *d_d, *d_e;
int size = sizeof(int) * 20;
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
cudaMalloc((void**)&d_d, size);
cudaMalloc((void**)&d_e, size);
cudaMemcpy(d_a, &a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &b, size, cudaMemcpyHostToDevice);
cal<<<n, 1>>>(d_a, d_b, alpha);
cudaMemcpy(&b, d_b, size, cudaMemcpyDeviceToHost);
printf("\nExpansion res \n");
for(i = 0; i < n; i++)
printf("%d ", b[i]);
printf("\n");
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | .file "tmpxft_000a48c2_00000000-6_q3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3calPiS_iPiS_i
.type _Z25__device_stub__Z3calPiS_iPiS_i, @function
_Z25__device_stub__Z3calPiS_iPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3calPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z3calPiS_iPiS_i, .-_Z25__device_stub__Z3calPiS_iPiS_i
.globl _Z3calPiS_i
.type _Z3calPiS_i, @function
_Z3calPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3calPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3calPiS_i, .-_Z3calPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter size"
.LC1:
.string "%d"
.LC2:
.string "\nEnter set 1 \n"
.LC3:
.string "Enter set 2 \n"
.LC4:
.string "Enter AA "
.LC5:
.string "\nExpansion res \n"
.LC6:
.string "%d "
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $256, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 8(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 8(%rsp)
jle .L12
leaq 80(%rsp), %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
.L13:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 8(%rsp)
jg .L13
.L12:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 8(%rsp)
jle .L14
leaq 160(%rsp), %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
.L15:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 8(%rsp)
jg .L15
.L14:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq 16(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $80, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 160(%rsp), %rsi
movl $1, %ecx
movl $80, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl 8(%rsp), %eax
movl %eax, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L16:
leaq 160(%rsp), %rdi
movl $2, %ecx
movl $80, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 8(%rsp)
jle .L17
movl $0, %ebx
leaq .LC6(%rip), %rbp
.L18:
movl 160(%rsp,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 8(%rsp)
jg .L18
.L17:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $256, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl 12(%rsp), %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z25__device_stub__Z3calPiS_iPiS_i
jmp .L16
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z3calPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3calPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void cal(int *a, int *b, int x1)
{
int i = blockIdx.x;
b[i] = x1 * a[i] + b[i];
}
int main()
{
int a[20], b[20];
int n, i;
printf("Enter size");
scanf("%d",&n);
printf("\nEnter set 1 \n");
for(i = 0; i < n; i++)
scanf("%d", &a[i]);
printf("Enter set 2 \n");
for(i = 0; i < n; i++)
scanf("%d", &b[i]);
int alpha;
printf("Enter AA ");
scanf("%d", &alpha);
int *d_a, *d_b, *d_c, *d_d, *d_e;
int size = sizeof(int) * 20;
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
cudaMalloc((void**)&d_d, size);
cudaMalloc((void**)&d_e, size);
cudaMemcpy(d_a, &a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &b, size, cudaMemcpyHostToDevice);
cal<<<n, 1>>>(d_a, d_b, alpha);
cudaMemcpy(&b, d_b, size, cudaMemcpyDeviceToHost);
printf("\nExpansion res \n");
for(i = 0; i < n; i++)
printf("%d ", b[i]);
printf("\n");
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void cal(int *a, int *b, int x1)
{
int i = blockIdx.x;
b[i] = x1 * a[i] + b[i];
}
int main()
{
int a[20], b[20];
int n, i;
printf("Enter size");
scanf("%d",&n);
printf("\nEnter set 1 \n");
for(i = 0; i < n; i++)
scanf("%d", &a[i]);
printf("Enter set 2 \n");
for(i = 0; i < n; i++)
scanf("%d", &b[i]);
int alpha;
printf("Enter AA ");
scanf("%d", &alpha);
int *d_a, *d_b, *d_c, *d_d, *d_e;
int size = sizeof(int) * 20;
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
hipMalloc((void**)&d_d, size);
hipMalloc((void**)&d_e, size);
hipMemcpy(d_a, &a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &b, size, hipMemcpyHostToDevice);
cal<<<n, 1>>>(d_a, d_b, alpha);
hipMemcpy(&b, d_b, size, hipMemcpyDeviceToHost);
printf("\nExpansion res \n");
for(i = 0; i < n; i++)
printf("%d ", b[i]);
printf("\n");
hipFree(d_a);
hipFree(d_b);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void cal(int *a, int *b, int x1)
{
int i = blockIdx.x;
b[i] = x1 * a[i] + b[i];
}
int main()
{
int a[20], b[20];
int n, i;
printf("Enter size");
scanf("%d",&n);
printf("\nEnter set 1 \n");
for(i = 0; i < n; i++)
scanf("%d", &a[i]);
printf("Enter set 2 \n");
for(i = 0; i < n; i++)
scanf("%d", &b[i]);
int alpha;
printf("Enter AA ");
scanf("%d", &alpha);
int *d_a, *d_b, *d_c, *d_d, *d_e;
int size = sizeof(int) * 20;
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
hipMalloc((void**)&d_d, size);
hipMalloc((void**)&d_e, size);
hipMemcpy(d_a, &a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &b, size, hipMemcpyHostToDevice);
cal<<<n, 1>>>(d_a, d_b, alpha);
hipMemcpy(&b, d_b, size, hipMemcpyDeviceToHost);
printf("\nExpansion res \n");
for(i = 0; i < n; i++)
printf("%d ", b[i]);
printf("\n");
hipFree(d_a);
hipFree(d_b);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3calPiS_i
.globl _Z3calPiS_i
.p2align 8
.type _Z3calPiS_i,@function
_Z3calPiS_i:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x10
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s2
s_addc_u32 s1, s5, s3
s_add_u32 s2, s6, s2
s_load_b32 s0, s[0:1], 0x0
s_addc_u32 s3, s7, s3
s_load_b32 s1, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s0, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s1
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3calPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3calPiS_i, .Lfunc_end0-_Z3calPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3calPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3calPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void cal(int *a, int *b, int x1)
{
int i = blockIdx.x;
b[i] = x1 * a[i] + b[i];
}
int main()
{
int a[20], b[20];
int n, i;
printf("Enter size");
scanf("%d",&n);
printf("\nEnter set 1 \n");
for(i = 0; i < n; i++)
scanf("%d", &a[i]);
printf("Enter set 2 \n");
for(i = 0; i < n; i++)
scanf("%d", &b[i]);
int alpha;
printf("Enter AA ");
scanf("%d", &alpha);
int *d_a, *d_b, *d_c, *d_d, *d_e;
int size = sizeof(int) * 20;
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
hipMalloc((void**)&d_d, size);
hipMalloc((void**)&d_e, size);
hipMemcpy(d_a, &a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &b, size, hipMemcpyHostToDevice);
cal<<<n, 1>>>(d_a, d_b, alpha);
hipMemcpy(&b, d_b, size, hipMemcpyDeviceToHost);
printf("\nExpansion res \n");
for(i = 0; i < n; i++)
printf("%d ", b[i]);
printf("\n");
hipFree(d_a);
hipFree(d_b);
return 0;
} | .text
.file "q3.hip"
.globl _Z18__device_stub__calPiS_i # -- Begin function _Z18__device_stub__calPiS_i
.p2align 4, 0x90
.type _Z18__device_stub__calPiS_i,@function
_Z18__device_stub__calPiS_i: # @_Z18__device_stub__calPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3calPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__calPiS_i, .Lfunc_end0-_Z18__device_stub__calPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, 4(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 224(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 4(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
movl $.Lstr.1, %edi
callq puts@PLT
cmpl $0, 4(%rsp)
jle .LBB1_6
# %bb.4: # %.lr.ph27.preheader
leaq 144(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph27
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 4(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_5
.LBB1_6: # %._crit_edge28
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
leaq 16(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 136(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 128(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 120(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $80, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $80, %edx
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl 24(%rsp), %edx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3calPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 8(%rsp), %rsi
leaq 144(%rsp), %rdi
movl $80, %edx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
cmpl $0, 4(%rsp)
jle .LBB1_11
# %bb.9: # %.lr.ph31.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_10: # %.lr.ph31
# =>This Inner Loop Header: Depth=1
movl 144(%rsp,%rbx,4), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %rbx
movslq 4(%rsp), %rax
cmpq %rax, %rbx
jl .LBB1_10
.LBB1_11: # %._crit_edge32
movl $10, %edi
callq putchar@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3calPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3calPiS_i,@object # @_Z3calPiS_i
.section .rodata,"a",@progbits
.globl _Z3calPiS_i
.p2align 3, 0x0
_Z3calPiS_i:
.quad _Z18__device_stub__calPiS_i
.size _Z3calPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter size"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Enter AA "
.size .L.str.4, 10
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d "
.size .L.str.6, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3calPiS_i"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nEnter set 1 "
.size .Lstr, 14
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Enter set 2 "
.size .Lstr.1, 13
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nExpansion res "
.size .Lstr.2, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__calPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3calPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3calPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fc800078e0205 */
/*0050*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe400078e0205 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IMAD R7, R2, c[0x0][0x170], R7 ; /* 0x00005c0002077a24 */
/* 0x004fca00078e0207 */
/*0090*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3calPiS_i
.globl _Z3calPiS_i
.p2align 8
.type _Z3calPiS_i,@function
_Z3calPiS_i:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x10
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s2
s_addc_u32 s1, s5, s3
s_add_u32 s2, s6, s2
s_load_b32 s0, s[0:1], 0x0
s_addc_u32 s3, s7, s3
s_load_b32 s1, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s0, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s1
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3calPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3calPiS_i, .Lfunc_end0-_Z3calPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3calPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3calPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a48c2_00000000-6_q3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3calPiS_iPiS_i
.type _Z25__device_stub__Z3calPiS_iPiS_i, @function
_Z25__device_stub__Z3calPiS_iPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3calPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z3calPiS_iPiS_i, .-_Z25__device_stub__Z3calPiS_iPiS_i
.globl _Z3calPiS_i
.type _Z3calPiS_i, @function
_Z3calPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3calPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3calPiS_i, .-_Z3calPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter size"
.LC1:
.string "%d"
.LC2:
.string "\nEnter set 1 \n"
.LC3:
.string "Enter set 2 \n"
.LC4:
.string "Enter AA "
.LC5:
.string "\nExpansion res \n"
.LC6:
.string "%d "
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $256, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 8(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 8(%rsp)
jle .L12
leaq 80(%rsp), %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
.L13:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 8(%rsp)
jg .L13
.L12:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 8(%rsp)
jle .L14
leaq 160(%rsp), %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
.L15:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 8(%rsp)
jg .L15
.L14:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq 16(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $80, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 160(%rsp), %rsi
movl $1, %ecx
movl $80, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl 8(%rsp), %eax
movl %eax, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L16:
leaq 160(%rsp), %rdi
movl $2, %ecx
movl $80, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 8(%rsp)
jle .L17
movl $0, %ebx
leaq .LC6(%rip), %rbp
.L18:
movl 160(%rsp,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 8(%rsp)
jg .L18
.L17:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $256, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl 12(%rsp), %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z25__device_stub__Z3calPiS_iPiS_i
jmp .L16
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z3calPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3calPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "q3.hip"
.globl _Z18__device_stub__calPiS_i # -- Begin function _Z18__device_stub__calPiS_i
.p2align 4, 0x90
.type _Z18__device_stub__calPiS_i,@function
_Z18__device_stub__calPiS_i: # @_Z18__device_stub__calPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3calPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__calPiS_i, .Lfunc_end0-_Z18__device_stub__calPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, 4(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 224(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 4(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
movl $.Lstr.1, %edi
callq puts@PLT
cmpl $0, 4(%rsp)
jle .LBB1_6
# %bb.4: # %.lr.ph27.preheader
leaq 144(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph27
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 4(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_5
.LBB1_6: # %._crit_edge28
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
leaq 16(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 136(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 128(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 120(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $80, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $80, %edx
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl 24(%rsp), %edx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3calPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 8(%rsp), %rsi
leaq 144(%rsp), %rdi
movl $80, %edx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
cmpl $0, 4(%rsp)
jle .LBB1_11
# %bb.9: # %.lr.ph31.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_10: # %.lr.ph31
# =>This Inner Loop Header: Depth=1
movl 144(%rsp,%rbx,4), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %rbx
movslq 4(%rsp), %rax
cmpq %rax, %rbx
jl .LBB1_10
.LBB1_11: # %._crit_edge32
movl $10, %edi
callq putchar@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3calPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3calPiS_i,@object # @_Z3calPiS_i
.section .rodata,"a",@progbits
.globl _Z3calPiS_i
.p2align 3, 0x0
_Z3calPiS_i:
.quad _Z18__device_stub__calPiS_i
.size _Z3calPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter size"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Enter AA "
.size .L.str.4, 10
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d "
.size .L.str.6, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3calPiS_i"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nEnter set 1 "
.size .Lstr, 14
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Enter set 2 "
.size .Lstr.1, 13
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nExpansion res "
.size .Lstr.2, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__calPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3calPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sga_right_data_backward (const int n, const float *filters, float *top_diff, const int height, const int width, const int depth, const int wsize, float *bottom_diff){
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= n)
{
return;
}
int step = height * width;
int base = index / height * step * depth + (index % height) * width; //up->down
int fbase = index / height * step * wsize + (index % height) * width;
for (int col = width - 1; col >= 0; col--)
{
int shift = fbase + col;
for (int d = 0; d < depth; d++)
{
int location = base + d * step + col;
float temp = top_diff[location];
if (col + 1 < width)
temp += top_diff[location + 1] * filters[shift + 1 + step];
if (col + 2 < width)
temp += top_diff[location + 2] * filters[shift + 2 + 2 * step];
if (col + 1 < width && d + 1 < depth)
temp +=
top_diff[location + 1 + step] * filters[shift + 1 + 3 * step];
if (col + 1 < width && d - 1 >= 0)
temp +=
top_diff[location + 1 - step] * filters[shift + 1 + 4 * step];
top_diff[location] = temp;
bottom_diff[location] += (temp * filters[shift]);
}
}
/*
for(int d = 0; d < depth; d ++){
int shift = fbase;// + width*(height-1);
int location = base;// + width*(height-1) + d * step;
bottom_diff[location] += top_diff[location] * (filters[shift + step] + filters[shift + 2*step] + filters[shift + 3*step] + filters[shift + 4*step]);
// bottom_diff[location] += top_diff[location];
shift += 1;
location += 1;
bottom_diff[location] += top_diff[location] * filters[shift + 2*step];
}
for(int col=1;col<width;col++){
int shift = fbase + col;
int location = base + col;
bottom_diff[location] += top_diff[location] * filters[shift + 3*step];
location += (depth - 1)*step;
bottom_diff[location] += top_diff[location] * filters[shift + 4*step];
}*/
for (int col = 0; col < width; col++)
{
int shift = fbase + col;
int location = base + col;
bottom_diff[location] += top_diff[location] * filters[shift + 3 * step];
location += (depth - 1) * step;
bottom_diff[location] += top_diff[location] * filters[shift + 4 * step];
}
} | code for sm_80
Function : _Z23sga_right_data_backwardiPKfPfiiiiS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R25, SR_CTAID.X ; /* 0x0000000000197919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R25, R25, c[0x0][0x0], R0 ; /* 0x0000000019197a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R25, c[0x0][0x160], PT ; /* 0x0000580019007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IABS R5, c[0x0][0x178] ; /* 0x00005e0000057a13 */
/* 0x000fe20000000000 */
/*0070*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ MOV R21, 0x1 ; /* 0x0000000100157802 */
/* 0x000fe20000000f00 */
/*0090*/ UIMAD UR5, UR4, UR5, URZ ; /* 0x00000005040572a4 */
/* 0x000fe2000f8e023f */
/*00a0*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e300000209400 */
/*00b0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00c0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00f0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*0100*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*0110*/ IABS R4, R25 ; /* 0x0000001900047213 */
/* 0x000fc80000000000 */
/*0120*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0130*/ IMAD.HI.U32 R26, R3, R4, RZ ; /* 0x00000004031a7227 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.MOV R0, RZ, RZ, -R26 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a1a */
/*0150*/ IMAD R0, R5, R0, R4 ; /* 0x0000000005007224 */
/* 0x000fca00078e0204 */
/*0160*/ ISETP.GT.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f24070 */
/*0170*/ @!P1 IADD3 R0, R0, -R5.reuse, RZ ; /* 0x8000000500009210 */
/* 0x080fe40007ffe0ff */
/*0180*/ @!P1 IADD3 R26, R26, 0x1, RZ ; /* 0x000000011a1a9810 */
/* 0x000fe40007ffe0ff */
/*0190*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*01a0*/ LOP3.LUT R0, R25, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0019007a12 */
/* 0x000fe400078e3cff */
/*01b0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f25270 */
/*01c0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f46270 */
/*01d0*/ @P0 IADD3 R26, R26, 0x1, RZ ; /* 0x000000011a1a0810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.LE.AND P0, PT, R21, c[0x0][0x17c], PT ; /* 0x00005f0015007a0c */
/* 0x000fc80003f03270 */
/*01f0*/ @!P2 IMAD.MOV R26, RZ, RZ, -R26 ; /* 0x000000ffff1aa224 */
/* 0x000fe200078e0a1a */
/*0200*/ @!P1 LOP3.LUT R26, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff1a9a12 */
/* 0x000fca00078e33ff */
/*0210*/ IMAD.MOV R0, RZ, RZ, -R26 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0a1a */
/*0220*/ IMAD R23, R26, UR5, RZ ; /* 0x000000051a177c24 */
/* 0x000fe4000f8e02ff */
/*0230*/ IMAD R25, R0, c[0x0][0x178], R25 ; /* 0x00005e0000197a24 */
/* 0x000fc800078e0219 */
/*0240*/ IMAD R0, R25, c[0x0][0x17c], RZ ; /* 0x00005f0019007a24 */
/* 0x000fc800078e02ff */
/*0250*/ IMAD R31, R23, c[0x0][0x184], R0 ; /* 0x00006100171f7a24 */
/* 0x000fe200078e0200 */
/*0260*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fec0003800000 */
/*0270*/ ISETP.LE.AND P0, PT, R21, c[0x0][0x180], PT ; /* 0x0000600015007a0c */
/* 0x000fe20003f03270 */
/*0280*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0290*/ IADD3 R24, R31, UR5, RZ ; /* 0x000000051f187c10 */
/* 0x000fe2000fffe0ff */
/*02a0*/ IMAD R23, R23, c[0x0][0x180], R0 ; /* 0x0000600017177a24 */
/* 0x000fe200078e0200 */
/*02b0*/ MOV R3, UR5 ; /* 0x0000000500037c02 */
/* 0x000fc80008000f00 */
/*02c0*/ LEA R22, R3, R24, 0x1 ; /* 0x0000001803167211 */
/* 0x000fca00078e08ff */
/*02d0*/ @!P0 BRA 0xbd0 ; /* 0x000008f000008947 */
/* 0x000fea0003800000 */
/*02e0*/ LOP3.LUT R21, R21, c[0x0][0x180], RZ, 0xc0, !PT ; /* 0x0000600015157a12 */
/* 0x000fe200078ec0ff */
/*02f0*/ ULEA UR8, UR5, 0x2, 0x1 ; /* 0x0000000205087891 */
/* 0x000fe4000f8e083f */
/*0300*/ ULDC UR6, c[0x0][0x17c] ; /* 0x00005f0000067ab9 */
/* 0x000fe20000000800 */
/*0310*/ IADD3 R20, -R21, c[0x0][0x180], RZ ; /* 0x0000600015147a10 */
/* 0x000fe40007ffe1ff */
/*0320*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0330*/ UIADD3 UR7, UR6, -0x1, URZ ; /* 0xffffffff06077890 */
/* 0x000fe2000fffe03f */
/*0340*/ IADD3 R9, R22, UR6, RZ ; /* 0x0000000616097c10 */
/* 0x000fe2000fffe0ff */
/*0350*/ UIADD3 UR12, UR6, 0x1, URZ ; /* 0x00000001060c7890 */
/* 0x000fe2000fffe03f */
/*0360*/ IADD3 R11, R24, UR6, RZ ; /* 0x00000006180b7c10 */
/* 0x000fe2000fffe0ff */
/*0370*/ UIADD3 UR13, UR5, UR6, URZ ; /* 0x00000006050d7290 */
/* 0x000fe2000fffe03f */
/*0380*/ ISETP.NE.AND P1, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f25270 */
/*0390*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*03a0*/ IADD3 R5, R31, UR7, RZ ; /* 0x000000071f057c10 */
/* 0x000fe2000fffe0ff */
/*03b0*/ UIADD3 UR14, -UR5, UR6, URZ ; /* 0x00000006050e7290 */
/* 0x000fe2000fffe13f */
/*03c0*/ IADD3 R7, R9, UR5, RZ ; /* 0x0000000509077c10 */
/* 0x001fe2000fffe0ff */
/*03d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*03e0*/ IADD3 R3, R5, UR8, RZ ; /* 0x0000000805037c10 */
/* 0x000fc4000fffe0ff */
/*03f0*/ ISETP.NE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fc60003f05270 */
/*0400*/ IMAD.WIDE R10, R11, R0, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fc800078e0200 */
/*0410*/ IMAD.WIDE R8, R9, R0, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x000fc800078e0200 */
/*0420*/ IMAD.WIDE R6, R7, R0, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fc800078e0200 */
/*0430*/ IMAD.WIDE R4, R5, R0, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fc800078e0200 */
/*0440*/ IMAD.WIDE R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0200 */
/*0450*/ @!P1 BRA 0x8e0 ; /* 0x0000048000009947 */
/* 0x000fea0003800000 */
/*0460*/ ULDC UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fe20000000800 */
/*0470*/ MOV R27, R20 ; /* 0x00000014001b7202 */
/* 0x000fe20000000f00 */
/*0480*/ UISETP.GE.AND UP0, UPT, UR6, UR4, UPT ; /* 0x000000040600728c */
/* 0x000fc6000bf06270 */
/*0490*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*04a0*/ IMAD.U32 R18, RZ, RZ, UR5 ; /* 0x00000005ff127e24 */
/* 0x001fe2000f8e00ff */
/*04b0*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*04c0*/ PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f2f008 */
/*04d0*/ IMAD R18, R18, UR4, R23 ; /* 0x0000000412127c24 */
/* 0x000fca000f8e0217 */
/*04e0*/ IADD3 R13, R18, UR6, RZ ; /* 0x00000006120d7c10 */
/* 0x000fca000fffe0ff */
/*04f0*/ IMAD.WIDE R12, R13, R0, c[0x0][0x170] ; /* 0x00005c000d0c7625 */
/* 0x000fe200078e0200 */
/*0500*/ @!P1 LDG.E R17, [R10.64] ; /* 0x0000000a0a119981 */
/* 0x000ea8000c1e1900 */
/*0510*/ LDG.E R29, [R12.64+-0x4] ; /* 0xfffffc0a0c1d7981 */
/* 0x000ea8000c1e1900 */
/*0520*/ @!P1 LDG.E R16, [R12.64] ; /* 0x0000000a0c109981 */
/* 0x000ea2000c1e1900 */
/*0530*/ UISETP.EQ.OR UP2, UPT, UR4, URZ, UP0 ; /* 0x0000003f0400728c */
/* 0x000fe20008742670 */
/*0540*/ IADD3 R28, R18, UR5, RZ ; /* 0x00000005121c7c10 */
/* 0x000fe2000fffe0ff */
/*0550*/ ULDC UR15, c[0x0][0x17c] ; /* 0x00005f00000f7ab9 */
/* 0x000fc40000000800 */
/*0560*/ UIADD3 UR9, UR4, 0x1, URZ ; /* 0x0000000104097890 */
/* 0x000fe2000fffe03f */
/*0570*/ IADD3 R15, R28, UR6, RZ ; /* 0x000000061c0f7c10 */
/* 0x000fe2000fffe0ff */
/*0580*/ UISETP.GE.AND UP3, UPT, UR12, UR15, UPT ; /* 0x0000000f0c00728c */
/* 0x000fe2000bf66270 */
/*0590*/ PLOP3.LUT P4, PT, PT, PT, UP2, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f8f028 */
/*05a0*/ ULDC UR15, c[0x0][0x180] ; /* 0x00006000000f7ab9 */
/* 0x000fe40000000800 */
/*05b0*/ UISETP.GE.OR UP1, UPT, UR9, UR15, UP0 ; /* 0x0000000f0900728c */
/* 0x000fe20008726670 */
/*05c0*/ PLOP3.LUT P2, PT, PT, PT, UP3, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fca0003f4f038 */
/*05d0*/ PLOP3.LUT P3, PT, PT, PT, UP1, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f6f018 */
/*05e0*/ IMAD.WIDE R14, R15, R0, c[0x0][0x170] ; /* 0x00005c000f0e7625 */
/* 0x000fe400078e0200 */
/*05f0*/ @!P4 IADD3 R33, R18, UR14, RZ ; /* 0x0000000e1221cc10 */
/* 0x000fe2000fffe0ff */
/*0600*/ @!P4 LDG.E R34, [R6.64] ; /* 0x0000000a0622c981 */
/* 0x000ee8000c1e1900 */
/*0610*/ @!P2 LDG.E R30, [R2.64] ; /* 0x0000000a021ea981 */
/* 0x000f28000c1e1900 */
/*0620*/ @!P2 LDG.E R19, [R12.64+0x4] ; /* 0x0000040a0c13a981 */
/* 0x000f28000c1e1900 */
/*0630*/ @!P3 LDG.E R32, [R14.64] ; /* 0x0000000a0e20b981 */
/* 0x000f62000c1e1900 */
/*0640*/ @!P1 FFMA R29, R16, R17, R29 ; /* 0x00000011101d9223 */
/* 0x004fc4000000001d */
/*0650*/ @!P4 IMAD.WIDE R16, R33, R0, c[0x0][0x170] ; /* 0x00005c002110c625 */
/* 0x000fe400078e0200 */
/*0660*/ @!P3 LDG.E R33, [R8.64] ; /* 0x0000000a0821b981 */
/* 0x000f68000c1e1900 */
/*0670*/ @!P4 LDG.E R16, [R16.64] ; /* 0x0000000a1010c981 */
/* 0x000ee2000c1e1900 */
/*0680*/ @!P2 FFMA R29, R30, R19, R29 ; /* 0x000000131e1da223 */
/* 0x010fe2000000001d */
/*0690*/ IADD3 R19, R18, UR7, RZ ; /* 0x0000000712137c10 */
/* 0x000fca000fffe0ff */
/*06a0*/ IMAD.WIDE R18, R19, R0, c[0x0][0x188] ; /* 0x0000620013127625 */
/* 0x000fc800078e0200 */
/*06b0*/ @!P3 FFMA R29, R32, R33, R29 ; /* 0x00000021201db223 */
/* 0x020fc8000000001d */
/*06c0*/ @!P4 FFMA R29, R34, R16, R29 ; /* 0x00000010221dc223 */
/* 0x008fca000000001d */
/*06d0*/ STG.E [R12.64+-0x4], R29 ; /* 0xfffffc1d0c007986 */
/* 0x0001e8000c10190a */
/*06e0*/ LDG.E R30, [R4.64] ; /* 0x0000000a041e7981 */
/* 0x000ea8000c1e1900 */
/*06f0*/ LDG.E R32, [R18.64] ; /* 0x0000000a12207981 */
/* 0x000ea2000c1e1900 */
/*0700*/ UIADD3 UR4, UR4, 0x2, URZ ; /* 0x0000000204047890 */
/* 0x000fc8000fffe03f */
/*0710*/ UISETP.GE.OR UP1, UPT, UR4, UR15, UP0 ; /* 0x0000000f0400728c */
/* 0x000fcc0008726670 */
/*0720*/ PLOP3.LUT P3, PT, PT, PT, UP1, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f6f018 */
/*0730*/ @!P3 IADD3 R17, R28, UR13, RZ ; /* 0x0000000d1c11bc10 */
/* 0x000fca000fffe0ff */
/*0740*/ @!P3 IMAD.WIDE R16, R17, R0, c[0x0][0x170] ; /* 0x00005c001110b625 */
/* 0x000fc800078e0200 */
/*0750*/ FFMA R35, R30, R29, R32 ; /* 0x0000001d1e237223 */
/* 0x004fca0000000020 */
/*0760*/ STG.E [R18.64], R35 ; /* 0x0000002312007986 */
/* 0x0003e8000c10190a */
/*0770*/ LDG.E R33, [R14.64+-0x4] ; /* 0xfffffc0a0e217981 */
/* 0x000ea8000c1e1900 */
/*0780*/ @!P1 LDG.E R30, [R14.64] ; /* 0x0000000a0e1e9981 */
/* 0x000ea8000c1e1900 */
/*0790*/ @!P1 LDG.E R29, [R10.64] ; /* 0x0000000a0a1d9981 */
/* 0x001ea8000c1e1900 */
/*07a0*/ @!P2 LDG.E R32, [R2.64] ; /* 0x0000000a0220a981 */
/* 0x000ee8000c1e1900 */
/*07b0*/ @!P2 LDG.E R34, [R14.64+0x4] ; /* 0x0000040a0e22a981 */
/* 0x000ee8000c1e1900 */
/*07c0*/ @!P3 LDG.E R16, [R16.64] ; /* 0x0000000a1010b981 */
/* 0x000f28000c1e1900 */
/*07d0*/ @!P3 LDG.E R36, [R8.64] ; /* 0x0000000a0824b981 */
/* 0x000f28000c1e1900 */
/*07e0*/ @!P1 LDG.E R12, [R12.64] ; /* 0x0000000a0c0c9981 */
/* 0x000f68000c1e1900 */
/*07f0*/ @!P1 LDG.E R37, [R6.64] ; /* 0x0000000a06259981 */
/* 0x000f62000c1e1900 */
/*0800*/ IADD3 R19, R28, UR7, RZ ; /* 0x000000071c137c10 */
/* 0x002fca000fffe0ff */
/*0810*/ IMAD.WIDE R18, R19, R0, c[0x0][0x188] ; /* 0x0000620013127625 */
/* 0x000fc800078e0200 */
/*0820*/ @!P1 FFMA R33, R30, R29, R33 ; /* 0x0000001d1e219223 */
/* 0x004fc80000000021 */
/*0830*/ @!P2 FFMA R33, R32, R34, R33 ; /* 0x000000222021a223 */
/* 0x008fc80000000021 */
/*0840*/ @!P3 FFMA R33, R36, R16, R33 ; /* 0x000000102421b223 */
/* 0x010fc80000000021 */
/*0850*/ @!P1 FFMA R33, R12, R37, R33 ; /* 0x000000250c219223 */
/* 0x020fca0000000021 */
/*0860*/ STG.E [R14.64+-0x4], R33 ; /* 0xfffffc210e007986 */
/* 0x0001e8000c10190a */
/*0870*/ LDG.E R16, [R4.64] ; /* 0x0000000a04107981 */
/* 0x000ea8000c1e1900 */
/*0880*/ LDG.E R17, [R18.64] ; /* 0x0000000a12117981 */
/* 0x000ea2000c1e1900 */
/*0890*/ IADD3 R27, R27, -0x2, RZ ; /* 0xfffffffe1b1b7810 */
/* 0x000fc80007ffe0ff */
/*08a0*/ ISETP.NE.AND P1, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fe20003f25270 */
/*08b0*/ FFMA R17, R16, R33, R17 ; /* 0x0000002110117223 */
/* 0x004fca0000000011 */
/*08c0*/ STG.E [R18.64], R17 ; /* 0x0000001112007986 */
/* 0x0001ee000c10190a */
/*08d0*/ @P1 BRA 0x4a0 ; /* 0xfffffbc000001947 */
/* 0x000fea000383ffff */
/*08e0*/ @!P0 BRA 0xb90 ; /* 0x000002a000008947 */
/* 0x000fea0003800000 */
/*08f0*/ ULDC UR15, c[0x0][0x17c] ; /* 0x00005f00000f7ab9 */
/* 0x000fe20000000800 */
/*0900*/ MOV R12, UR5 ; /* 0x00000005000c7c02 */
/* 0x000fe20008000f00 */
/*0910*/ UISETP.GE.AND UP0, UPT, UR6, UR15, UPT ; /* 0x0000000f0600728c */
/* 0x000fe4000bf06270 */
/*0920*/ UIADD3 UR9, UR4, 0x1, URZ ; /* 0x0000000104097890 */
/* 0x000fc4000fffe03f */
/*0930*/ ULDC UR16, c[0x0][0x180] ; /* 0x0000600000107ab9 */
/* 0x000fe20000000800 */
/*0940*/ IMAD R17, R12, UR4, R23 ; /* 0x000000040c117c24 */
/* 0x001fe2000f8e0217 */
/*0950*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f008 */
/*0960*/ UISETP.GE.OR UP1, UPT, UR9, UR16, UP0 ; /* 0x000000100900728c */
/* 0x000fe40008726670 */
/*0970*/ UISETP.EQ.OR UP0, UPT, UR4, URZ, UP0 ; /* 0x0000003f0400728c */
/* 0x000fe20008702670 */
/*0980*/ IADD3 R27, R17, UR7, RZ ; /* 0x00000007111b7c10 */
/* 0x000fe2000fffe0ff */
/*0990*/ UISETP.GE.AND UP2, UPT, UR12, UR15, UPT ; /* 0x0000000f0c00728c */
/* 0x000fe4000bf46270 */
/*09a0*/ PLOP3.LUT P2, PT, PT, PT, UP1, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f4f018 */
/*09b0*/ PLOP3.LUT P3, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f6f008 */
/*09c0*/ IMAD.WIDE R12, R27, R0, c[0x0][0x170] ; /* 0x00005c001b0c7625 */
/* 0x000fe200078e0200 */
/*09d0*/ PLOP3.LUT P1, PT, PT, PT, UP2, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f2f028 */
/*09e0*/ @!P0 IADD3 R19, R17, UR6, RZ ; /* 0x0000000611138c10 */
/* 0x000fe2000fffe0ff */
/*09f0*/ @!P0 LDG.E R10, [R10.64] ; /* 0x0000000a0a0a8981 */
/* 0x000ea8000c1e1900 */
/*0a00*/ @!P0 IMAD.WIDE R18, R19, R0.reuse, c[0x0][0x170] ; /* 0x00005c0013128625 */
/* 0x080fe200078e0200 */
/*0a10*/ LDG.E R29, [R12.64] ; /* 0x0000000a0c1d7981 */
/* 0x000ea2000c1e1900 */
/*0a20*/ @!P2 IADD3 R15, R17.reuse, UR13, RZ ; /* 0x0000000d110fac10 */
/* 0x040fe4000fffe0ff */
/*0a30*/ @!P3 IADD3 R17, R17, UR14, RZ ; /* 0x0000000e1111bc10 */
/* 0x000fe2000fffe0ff */
/*0a40*/ @!P2 LDG.E R8, [R8.64] ; /* 0x0000000a0808a981 */
/* 0x000ee4000c1e1900 */
/*0a50*/ @!P2 IMAD.WIDE R14, R15, R0, c[0x0][0x170] ; /* 0x00005c000f0ea625 */
/* 0x000fc400078e0200 */
/*0a60*/ @!P0 LDG.E R18, [R18.64] ; /* 0x0000000a12128981 */
/* 0x000ea4000c1e1900 */
/*0a70*/ @!P3 IMAD.WIDE R16, R17, R0, c[0x0][0x170] ; /* 0x00005c001110b625 */
/* 0x000fe400078e0200 */
/*0a80*/ @!P1 LDG.E R2, [R2.64] ; /* 0x0000000a02029981 */
/* 0x000f28000c1e1900 */
/*0a90*/ @!P1 LDG.E R28, [R12.64+0x8] ; /* 0x0000080a0c1c9981 */
/* 0x000f28000c1e1900 */
/*0aa0*/ @!P2 LDG.E R14, [R14.64] ; /* 0x0000000a0e0ea981 */
/* 0x000ee8000c1e1900 */
/*0ab0*/ @!P3 LDG.E R6, [R6.64] ; /* 0x0000000a0606b981 */
/* 0x000f68000c1e1900 */
/*0ac0*/ @!P3 LDG.E R16, [R16.64] ; /* 0x0000000a1010b981 */
/* 0x000f62000c1e1900 */
/*0ad0*/ SHF.R.S32.HI R0, RZ, 0x1f, R27 ; /* 0x0000001fff007819 */
/* 0x000fe2000001141b */
/*0ae0*/ @!P0 FFMA R29, R10, R18, R29 ; /* 0x000000120a1d8223 */
/* 0x004fc8000000001d */
/*0af0*/ @!P1 FFMA R29, R2, R28, R29 ; /* 0x0000001c021d9223 */
/* 0x010fe2000000001d */
/*0b00*/ LEA R2, P0, R27, c[0x0][0x188], 0x2 ; /* 0x000062001b027a11 */
/* 0x000fc600078010ff */
/*0b10*/ @!P2 FFMA R29, R8, R14, R29 ; /* 0x0000000e081da223 */
/* 0x008fe2000000001d */
/*0b20*/ LEA.HI.X R3, R27, c[0x0][0x18c], R0, 0x2, P0 ; /* 0x000063001b037a11 */
/* 0x000fc600000f1400 */
/*0b30*/ @!P3 FFMA R29, R6, R16, R29 ; /* 0x00000010061db223 */
/* 0x020fca000000001d */
/*0b40*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x0001e8000c10190a */
/*0b50*/ LDG.E R4, [R4.64] ; /* 0x0000000a04047981 */
/* 0x000ea8000c1e1900 */
/*0b60*/ LDG.E R0, [R2.64] ; /* 0x0000000a02007981 */
/* 0x000ea4000c1e1900 */
/*0b70*/ FFMA R7, R4, R29, R0 ; /* 0x0000001d04077223 */
/* 0x004fca0000000000 */
/*0b80*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c10190a */
/*0b90*/ UISETP.GT.AND UP0, UPT, UR6, 0x1, UPT ; /* 0x000000010600788c */
/* 0x000fc6000bf04270 */
/*0ba0*/ UMOV UR6, UR7 ; /* 0x0000000700067c82 */
/* 0x000fc60008000000 */
/*0bb0*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f0f008 */
/*0bc0*/ @P0 BRA 0x320 ; /* 0xfffff75000000947 */
/* 0x000fea000383ffff */
/*0bd0*/ ULDC UR6, c[0x0][0x17c] ; /* 0x00005f0000067ab9 */
/* 0x000fe20000000800 */
/*0be0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0bf0*/ UIADD3 UR4, UR6, -0x1, URZ ; /* 0xffffffff06047890 */
/* 0x000fe4000fffe03f */
/*0c00*/ ULOP3.LUT UR6, UR6, 0x3, URZ, 0xc0, !UPT ; /* 0x0000000306067892 */
/* 0x000fe4000f8ec03f */
/*0c10*/ UISETP.GE.U32.AND UP0, UPT, UR4, 0x3, UPT ; /* 0x000000030400788c */
/* 0x000fe4000bf06070 */
/*0c20*/ ULDC UR7, c[0x0][0x180] ; /* 0x0000600000077ab9 */
/* 0x000fe40000000800 */
/*0c30*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*0c40*/ ISETP.NE.AND P1, PT, RZ, UR6, PT ; /* 0x00000006ff007c0c */
/* 0x000fe2000bf25270 */
/*0c50*/ UIADD3 UR4, -UR4, UR7, URZ ; /* 0x0000000704047290 */
/* 0x000fe2000fffe13f */
/*0c60*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0f008 */
/*0c70*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fd4000f8e023f */
/*0c80*/ @!P0 BRA 0x1040 ; /* 0x000003b000008947 */
/* 0x000fea0003800000 */
/*0c90*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0ca0*/ ULDC UR7, c[0x0][0x17c] ; /* 0x00005f0000077ab9 */
/* 0x000fe40000000800 */
/*0cb0*/ UIADD3 UR7, -UR6, UR7, URZ ; /* 0x0000000706077290 */
/* 0x000fce000fffe13f */
/*0cc0*/ IADD3 R4, R23, R0.reuse, RZ ; /* 0x0000000017047210 */
/* 0x084fe20007ffe0ff */
/*0cd0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x001fe200078e00ff */
/*0ce0*/ IADD3 R8, R22, R0, RZ ; /* 0x0000000016087210 */
/* 0x000fc60007ffe0ff */
/*0cf0*/ IMAD.WIDE R2, R4, R13, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fc800078e020d */
/*0d00*/ IMAD.WIDE R4, R4, R13.reuse, c[0x0][0x188] ; /* 0x0000620004047625 */
/* 0x080fe200078e020d */
/*0d10*/ LDG.E R10, [R2.64] ; /* 0x0000000a020a7981 */
/* 0x000ea6000c1e1900 */
/*0d20*/ IMAD.WIDE R6, R8.reuse, R13, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x040fe200078e020d */
/*0d30*/ LDG.E R11, [R4.64] ; /* 0x0000000a040b7981 */
/* 0x000ea8000c1e1900 */
/*0d40*/ LDG.E R9, [R6.64] ; /* 0x0000000a06097981 */
/* 0x000ea2000c1e1900 */
/*0d50*/ IADD3 R12, R8, UR5, RZ ; /* 0x00000005080c7c10 */
/* 0x000fe2000fffe0ff */
/*0d60*/ IMAD.U32 R19, RZ, RZ, UR4 ; /* 0x00000004ff137e24 */
/* 0x000fe2000f8e00ff */
/*0d70*/ MOV R17, UR4 ; /* 0x0000000400117c02 */
/* 0x000fc60008000f00 */
/*0d80*/ IMAD.WIDE R12, R12, R13, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fc800078e020d */
/*0d90*/ FFMA R15, R9, R10, R11 ; /* 0x0000000a090f7223 */
/* 0x004fe4000000000b */
/*0da0*/ IMAD.WIDE R10, R17, 0x4, R2 ; /* 0x00000004110a7825 */
/* 0x000fc800078e0202 */
/*0db0*/ IMAD.WIDE R8, R19, 0x4, R4 ; /* 0x0000000413087825 */
/* 0x000fe200078e0204 */
/*0dc0*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0001e8000c10190a */
/*0dd0*/ LDG.E R14, [R12.64] ; /* 0x0000000a0c0e7981 */
/* 0x000ea8000c1e1900 */
/*0de0*/ LDG.E R17, [R10.64] ; /* 0x0000000a0a117981 */
/* 0x000ea8000c1e1900 */
/*0df0*/ LDG.E R16, [R8.64] ; /* 0x0000000a08107981 */
/* 0x000ea4000c1e1900 */
/*0e00*/ FFMA R17, R14, R17, R16 ; /* 0x000000110e117223 */
/* 0x004fca0000000010 */
/*0e10*/ STG.E [R8.64], R17 ; /* 0x0000001108007986 */
/* 0x0003e8000c10190a */
/*0e20*/ LDG.E R14, [R6.64+0x4] ; /* 0x0000040a060e7981 */
/* 0x000ea8000c1e1900 */
/*0e30*/ LDG.E R19, [R2.64+0x4] ; /* 0x0000040a02137981 */
/* 0x000ea8000c1e1900 */
/*0e40*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040a04107981 */
/* 0x000ea4000c1e1900 */
/*0e50*/ FFMA R19, R14, R19, R16 ; /* 0x000000130e137223 */
/* 0x004fca0000000010 */
/*0e60*/ STG.E [R4.64+0x4], R19 ; /* 0x0000041304007986 */
/* 0x0005e8000c10190a */
/*0e70*/ LDG.E R14, [R12.64+0x4] ; /* 0x0000040a0c0e7981 */
/* 0x000ee8000c1e1900 */
/*0e80*/ LDG.E R15, [R10.64+0x4] ; /* 0x0000040a0a0f7981 */
/* 0x001ee8000c1e1900 */
/*0e90*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040a08107981 */
/* 0x000ee4000c1e1900 */
/*0ea0*/ FFMA R15, R14, R15, R16 ; /* 0x0000000f0e0f7223 */
/* 0x008fca0000000010 */
/*0eb0*/ STG.E [R8.64+0x4], R15 ; /* 0x0000040f08007986 */
/* 0x0001e8000c10190a */
/*0ec0*/ LDG.E R14, [R6.64+0x8] ; /* 0x0000080a060e7981 */
/* 0x000ee8000c1e1900 */
/*0ed0*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080a02117981 */
/* 0x002ee8000c1e1900 */
/*0ee0*/ LDG.E R16, [R4.64+0x8] ; /* 0x0000080a04107981 */
/* 0x000ee4000c1e1900 */
/*0ef0*/ FFMA R17, R14, R17, R16 ; /* 0x000000110e117223 */
/* 0x008fca0000000010 */
/*0f00*/ STG.E [R4.64+0x8], R17 ; /* 0x0000081104007986 */
/* 0x0003e8000c10190a */
/*0f10*/ LDG.E R14, [R12.64+0x8] ; /* 0x0000080a0c0e7981 */
/* 0x000ee8000c1e1900 */
/*0f20*/ LDG.E R19, [R10.64+0x8] ; /* 0x0000080a0a137981 */
/* 0x004ee8000c1e1900 */
/*0f30*/ LDG.E R16, [R8.64+0x8] ; /* 0x0000080a08107981 */
/* 0x000ee4000c1e1900 */
/*0f40*/ FFMA R19, R14, R19, R16 ; /* 0x000000130e137223 */
/* 0x008fca0000000010 */
/*0f50*/ STG.E [R8.64+0x8], R19 ; /* 0x0000081308007986 */
/* 0x0005e8000c10190a */
/*0f60*/ LDG.E R14, [R6.64+0xc] ; /* 0x00000c0a060e7981 */
/* 0x000ee8000c1e1900 */
/*0f70*/ LDG.E R15, [R2.64+0xc] ; /* 0x00000c0a020f7981 */
/* 0x001ee8000c1e1900 */
/*0f80*/ LDG.E R16, [R4.64+0xc] ; /* 0x00000c0a04107981 */
/* 0x000ee2000c1e1900 */
/*0f90*/ UIADD3 UR7, UR7, -0x4, URZ ; /* 0xfffffffc07077890 */
/* 0x000fe2000fffe03f */
/*0fa0*/ FFMA R15, R14, R15, R16 ; /* 0x0000000f0e0f7223 */
/* 0x008fca0000000010 */
/*0fb0*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0005e8000c10190a */
/*0fc0*/ LDG.E R14, [R12.64+0xc] ; /* 0x00000c0a0c0e7981 */
/* 0x000ee8000c1e1900 */
/*0fd0*/ LDG.E R17, [R10.64+0xc] ; /* 0x00000c0a0a117981 */
/* 0x002ee8000c1e1900 */
/*0fe0*/ LDG.E R16, [R8.64+0xc] ; /* 0x00000c0a08107981 */
/* 0x000ee2000c1e1900 */
/*0ff0*/ ISETP.NE.AND P0, PT, RZ, UR7, PT ; /* 0x00000007ff007c0c */
/* 0x000fc4000bf05270 */
/*1000*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe20007ffe0ff */
/*1010*/ FFMA R17, R14, R17, R16 ; /* 0x000000110e117223 */
/* 0x008fca0000000010 */
/*1020*/ STG.E [R8.64+0xc], R17 ; /* 0x00000c1108007986 */
/* 0x0005ea000c10190a */
/*1030*/ @P0 BRA 0xcc0 ; /* 0xfffffc8000000947 */
/* 0x000fea000383ffff */
/*1040*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*1050*/ MOV R3, c[0x0][0x184] ; /* 0x0000610000037a02 */
/* 0x001fe20000000f00 */
/*1060*/ IMAD R4, R26, c[0x0][0x180], RZ ; /* 0x000060001a047a24 */
/* 0x004fe200078e02ff */
/*1070*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fc600000001ff */
/*1080*/ IMAD R5, R4, c[0x0][0x178], R25.reuse ; /* 0x00005e0004057a24 */
/* 0x100fe400078e0219 */
/*1090*/ IMAD R2, R26.reuse, R3.reuse, 0x3 ; /* 0x000000031a027424 */
/* 0x0c0fe400078e0203 */
/*10a0*/ IMAD R26, R26, R3, 0x4 ; /* 0x000000041a1a7424 */
/* 0x000fe400078e0203 */
/*10b0*/ IMAD R6, R5, c[0x0][0x17c], R0 ; /* 0x00005f0005067a24 */
/* 0x000fe400078e0200 */
/*10c0*/ IMAD R3, R2, c[0x0][0x178], R25.reuse ; /* 0x00005e0002037a24 */
/* 0x100fe400078e0219 */
/*10d0*/ IMAD R25, R26, c[0x0][0x178], R25 ; /* 0x00005e001a197a24 */
/* 0x000fc400078e0219 */
/*10e0*/ IMAD.WIDE R4, R6, R8, c[0x0][0x188] ; /* 0x0000620006047625 */
/* 0x000fc800078e0208 */
/*10f0*/ IMAD R3, R3, c[0x0][0x17c], R0.reuse ; /* 0x00005f0003037a24 */
/* 0x100fe200078e0200 */
/*1100*/ MOV R13, R5 ; /* 0x00000005000d7202 */
/* 0x000fe20000000f00 */
/*1110*/ IMAD R25, R25, c[0x0][0x17c], R0 ; /* 0x00005f0019197a24 */
/* 0x000fe400078e0200 */
/*1120*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0004 */
/*1130*/ IMAD.WIDE R6, R6, R8, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0208 */
/*1140*/ IMAD.WIDE R2, R3, R8, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0208 */
/*1150*/ MOV R0, R6 ; /* 0x0000000600007202 */
/* 0x000fc60000000f00 */
/*1160*/ IMAD.WIDE R4, R25, R8, c[0x0][0x168] ; /* 0x00005a0019047625 */
/* 0x000fe200078e0208 */
/*1170*/ MOV R19, R3 ; /* 0x0000000300137202 */
/* 0x000fc60000000f00 */
/*1180*/ IMAD.MOV.U32 R16, RZ, RZ, R2 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0002 */
/*1190*/ MOV R14, R4 ; /* 0x00000004000e7202 */
/* 0x000fe20000000f00 */
/*11a0*/ IMAD.MOV.U32 R17, RZ, RZ, R5 ; /* 0x000000ffff117224 */
/* 0x000fe400078e0005 */
/*11b0*/ MOV R2, R12 ; /* 0x0000000c00027202 */
/* 0x000fe20000000f00 */
/*11c0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0000 */
/*11d0*/ MOV R3, R13 ; /* 0x0000000d00037202 */
/* 0x000fe20000000f00 */
/*11e0*/ IMAD.MOV.U32 R11, RZ, RZ, R19 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0013 */
/*11f0*/ MOV R5, R7 ; /* 0x0000000700057202 */
/* 0x000fe40000000f00 */
/*1200*/ MOV R10, R16 ; /* 0x00000010000a7202 */
/* 0x000fe20000000f00 */
/*1210*/ LDG.E R6, [R2.64] ; /* 0x0000000a02067981 */
/* 0x000ea8000c1e1900 */
/*1220*/ LDG.E R0, [R10.64] ; /* 0x0000000a0a007981 */
/* 0x0000a8000c1e1900 */
/*1230*/ LDG.E R7, [R4.64] ; /* 0x0000000a04077981 */
/* 0x000ea2000c1e1900 */
/*1240*/ MOV R9, UR4 ; /* 0x0000000400097c02 */
/* 0x002fc40008000f00 */
/*1250*/ MOV R15, UR4 ; /* 0x00000004000f7c02 */
/* 0x000fe20008000f00 */
/*1260*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x001fe200078e000e */
/*1270*/ MOV R11, R17 ; /* 0x00000011000b7202 */
/* 0x000fe20000000f00 */
/*1280*/ FFMA R13, R0, R7, R6 ; /* 0x00000007000d7223 */
/* 0x004fe40000000006 */
/*1290*/ IMAD.WIDE R6, R9, 0x4, R4 ; /* 0x0000000409067825 */
/* 0x000fc800078e0204 */
/*12a0*/ IMAD.WIDE R8, R15, 0x4, R2 ; /* 0x000000040f087825 */
/* 0x000fe200078e0202 */
/*12b0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c10190a */
/*12c0*/ LDG.E R7, [R6.64] ; /* 0x0000000a06077981 */
/* 0x000ea8000c1e1900 */
/*12d0*/ LDG.E R0, [R10.64] ; /* 0x0000000a0a007981 */
/* 0x000ea8000c1e1900 */
/*12e0*/ LDG.E R12, [R8.64] ; /* 0x0000000a080c7981 */
/* 0x000ea2000c1e1900 */
/*12f0*/ UIADD3 UR6, UR6, -0x1, URZ ; /* 0xffffffff06067890 */
/* 0x000fcc000fffe03f */
/*1300*/ ISETP.NE.AND P0, PT, RZ, UR6, PT ; /* 0x00000006ff007c0c */
/* 0x000fe4000bf05270 */
/*1310*/ IADD3 R16, P1, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x000fe40007f3e0ff */
/*1320*/ IADD3 R14, P2, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe40007f5e0ff */
/*1330*/ IADD3.X R19, RZ, R19, RZ, P1, !PT ; /* 0x00000013ff137210 */
/* 0x000fe40000ffe4ff */
/*1340*/ IADD3.X R17, RZ, R17, RZ, P2, !PT ; /* 0x00000011ff117210 */
/* 0x000fe200017fe4ff */
/*1350*/ FFMA R15, R0, R7, R12 ; /* 0x00000007000f7223 */
/* 0x004fe2000000000c */
/*1360*/ IADD3 R0, P4, R4, 0x4, RZ ; /* 0x0000000404007810 */
/* 0x000fc40007f9e0ff */
/*1370*/ IADD3 R12, P3, R2, 0x4, RZ ; /* 0x00000004020c7810 */
/* 0x000fe40007f7e0ff */
/*1380*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0003e2000c10190a */
/*1390*/ IMAD.X R7, RZ, RZ, R5, P4 ; /* 0x000000ffff077224 */
/* 0x000fe200020e0605 */
/*13a0*/ IADD3.X R13, RZ, R3, RZ, P3, !PT ; /* 0x00000003ff0d7210 */
/* 0x001fe20001ffe4ff */
/*13b0*/ @P0 BRA 0x11b0 ; /* 0xfffffdf000000947 */
/* 0x000fea000383ffff */
/*13c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*13d0*/ BRA 0x13d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*13e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sga_right_data_backward (const int n, const float *filters, float *top_diff, const int height, const int width, const int depth, const int wsize, float *bottom_diff){
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= n)
{
return;
}
int step = height * width;
int base = index / height * step * depth + (index % height) * width; //up->down
int fbase = index / height * step * wsize + (index % height) * width;
for (int col = width - 1; col >= 0; col--)
{
int shift = fbase + col;
for (int d = 0; d < depth; d++)
{
int location = base + d * step + col;
float temp = top_diff[location];
if (col + 1 < width)
temp += top_diff[location + 1] * filters[shift + 1 + step];
if (col + 2 < width)
temp += top_diff[location + 2] * filters[shift + 2 + 2 * step];
if (col + 1 < width && d + 1 < depth)
temp +=
top_diff[location + 1 + step] * filters[shift + 1 + 3 * step];
if (col + 1 < width && d - 1 >= 0)
temp +=
top_diff[location + 1 - step] * filters[shift + 1 + 4 * step];
top_diff[location] = temp;
bottom_diff[location] += (temp * filters[shift]);
}
}
/*
for(int d = 0; d < depth; d ++){
int shift = fbase;// + width*(height-1);
int location = base;// + width*(height-1) + d * step;
bottom_diff[location] += top_diff[location] * (filters[shift + step] + filters[shift + 2*step] + filters[shift + 3*step] + filters[shift + 4*step]);
// bottom_diff[location] += top_diff[location];
shift += 1;
location += 1;
bottom_diff[location] += top_diff[location] * filters[shift + 2*step];
}
for(int col=1;col<width;col++){
int shift = fbase + col;
int location = base + col;
bottom_diff[location] += top_diff[location] * filters[shift + 3*step];
location += (depth - 1)*step;
bottom_diff[location] += top_diff[location] * filters[shift + 4*step];
}*/
for (int col = 0; col < width; col++)
{
int shift = fbase + col;
int location = base + col;
bottom_diff[location] += top_diff[location] * filters[shift + 3 * step];
location += (depth - 1) * step;
bottom_diff[location] += top_diff[location] * filters[shift + 4 * step];
}
} | .file "tmpxft_000be6e7_00000000-6_sga_right_data_backward.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z23sga_right_data_backwardiPKfPfiiiiS1_iPKfPfiiiiS1_
.type _Z54__device_stub__Z23sga_right_data_backwardiPKfPfiiiiS1_iPKfPfiiiiS1_, @function
_Z54__device_stub__Z23sga_right_data_backwardiPKfPfiiiiS1_iPKfPfiiiiS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 216(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z23sga_right_data_backwardiPKfPfiiiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z23sga_right_data_backwardiPKfPfiiiiS1_iPKfPfiiiiS1_, .-_Z54__device_stub__Z23sga_right_data_backwardiPKfPfiiiiS1_iPKfPfiiiiS1_
.globl _Z23sga_right_data_backwardiPKfPfiiiiS1_
.type _Z23sga_right_data_backwardiPKfPfiiiiS1_, @function
_Z23sga_right_data_backwardiPKfPfiiiiS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z54__device_stub__Z23sga_right_data_backwardiPKfPfiiiiS1_iPKfPfiiiiS1_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23sga_right_data_backwardiPKfPfiiiiS1_, .-_Z23sga_right_data_backwardiPKfPfiiiiS1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23sga_right_data_backwardiPKfPfiiiiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23sga_right_data_backwardiPKfPfiiiiS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sga_right_data_backward (const int n, const float *filters, float *top_diff, const int height, const int width, const int depth, const int wsize, float *bottom_diff){
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= n)
{
return;
}
int step = height * width;
int base = index / height * step * depth + (index % height) * width; //up->down
int fbase = index / height * step * wsize + (index % height) * width;
for (int col = width - 1; col >= 0; col--)
{
int shift = fbase + col;
for (int d = 0; d < depth; d++)
{
int location = base + d * step + col;
float temp = top_diff[location];
if (col + 1 < width)
temp += top_diff[location + 1] * filters[shift + 1 + step];
if (col + 2 < width)
temp += top_diff[location + 2] * filters[shift + 2 + 2 * step];
if (col + 1 < width && d + 1 < depth)
temp +=
top_diff[location + 1 + step] * filters[shift + 1 + 3 * step];
if (col + 1 < width && d - 1 >= 0)
temp +=
top_diff[location + 1 - step] * filters[shift + 1 + 4 * step];
top_diff[location] = temp;
bottom_diff[location] += (temp * filters[shift]);
}
}
/*
for(int d = 0; d < depth; d ++){
int shift = fbase;// + width*(height-1);
int location = base;// + width*(height-1) + d * step;
bottom_diff[location] += top_diff[location] * (filters[shift + step] + filters[shift + 2*step] + filters[shift + 3*step] + filters[shift + 4*step]);
// bottom_diff[location] += top_diff[location];
shift += 1;
location += 1;
bottom_diff[location] += top_diff[location] * filters[shift + 2*step];
}
for(int col=1;col<width;col++){
int shift = fbase + col;
int location = base + col;
bottom_diff[location] += top_diff[location] * filters[shift + 3*step];
location += (depth - 1)*step;
bottom_diff[location] += top_diff[location] * filters[shift + 4*step];
}*/
for (int col = 0; col < width; col++)
{
int shift = fbase + col;
int location = base + col;
bottom_diff[location] += top_diff[location] * filters[shift + 3 * step];
location += (depth - 1) * step;
bottom_diff[location] += top_diff[location] * filters[shift + 4 * step];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sga_right_data_backward (const int n, const float *filters, float *top_diff, const int height, const int width, const int depth, const int wsize, float *bottom_diff){
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= n)
{
return;
}
int step = height * width;
int base = index / height * step * depth + (index % height) * width; //up->down
int fbase = index / height * step * wsize + (index % height) * width;
for (int col = width - 1; col >= 0; col--)
{
int shift = fbase + col;
for (int d = 0; d < depth; d++)
{
int location = base + d * step + col;
float temp = top_diff[location];
if (col + 1 < width)
temp += top_diff[location + 1] * filters[shift + 1 + step];
if (col + 2 < width)
temp += top_diff[location + 2] * filters[shift + 2 + 2 * step];
if (col + 1 < width && d + 1 < depth)
temp +=
top_diff[location + 1 + step] * filters[shift + 1 + 3 * step];
if (col + 1 < width && d - 1 >= 0)
temp +=
top_diff[location + 1 - step] * filters[shift + 1 + 4 * step];
top_diff[location] = temp;
bottom_diff[location] += (temp * filters[shift]);
}
}
/*
for(int d = 0; d < depth; d ++){
int shift = fbase;// + width*(height-1);
int location = base;// + width*(height-1) + d * step;
bottom_diff[location] += top_diff[location] * (filters[shift + step] + filters[shift + 2*step] + filters[shift + 3*step] + filters[shift + 4*step]);
// bottom_diff[location] += top_diff[location];
shift += 1;
location += 1;
bottom_diff[location] += top_diff[location] * filters[shift + 2*step];
}
for(int col=1;col<width;col++){
int shift = fbase + col;
int location = base + col;
bottom_diff[location] += top_diff[location] * filters[shift + 3*step];
location += (depth - 1)*step;
bottom_diff[location] += top_diff[location] * filters[shift + 4*step];
}*/
for (int col = 0; col < width; col++)
{
int shift = fbase + col;
int location = base + col;
bottom_diff[location] += top_diff[location] * filters[shift + 3 * step];
location += (depth - 1) * step;
bottom_diff[location] += top_diff[location] * filters[shift + 4 * step];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sga_right_data_backward (const int n, const float *filters, float *top_diff, const int height, const int width, const int depth, const int wsize, float *bottom_diff){
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= n)
{
return;
}
int step = height * width;
int base = index / height * step * depth + (index % height) * width; //up->down
int fbase = index / height * step * wsize + (index % height) * width;
for (int col = width - 1; col >= 0; col--)
{
int shift = fbase + col;
for (int d = 0; d < depth; d++)
{
int location = base + d * step + col;
float temp = top_diff[location];
if (col + 1 < width)
temp += top_diff[location + 1] * filters[shift + 1 + step];
if (col + 2 < width)
temp += top_diff[location + 2] * filters[shift + 2 + 2 * step];
if (col + 1 < width && d + 1 < depth)
temp +=
top_diff[location + 1 + step] * filters[shift + 1 + 3 * step];
if (col + 1 < width && d - 1 >= 0)
temp +=
top_diff[location + 1 - step] * filters[shift + 1 + 4 * step];
top_diff[location] = temp;
bottom_diff[location] += (temp * filters[shift]);
}
}
/*
for(int d = 0; d < depth; d ++){
int shift = fbase;// + width*(height-1);
int location = base;// + width*(height-1) + d * step;
bottom_diff[location] += top_diff[location] * (filters[shift + step] + filters[shift + 2*step] + filters[shift + 3*step] + filters[shift + 4*step]);
// bottom_diff[location] += top_diff[location];
shift += 1;
location += 1;
bottom_diff[location] += top_diff[location] * filters[shift + 2*step];
}
for(int col=1;col<width;col++){
int shift = fbase + col;
int location = base + col;
bottom_diff[location] += top_diff[location] * filters[shift + 3*step];
location += (depth - 1)*step;
bottom_diff[location] += top_diff[location] * filters[shift + 4*step];
}*/
for (int col = 0; col < width; col++)
{
int shift = fbase + col;
int location = base + col;
bottom_diff[location] += top_diff[location] * filters[shift + 3 * step];
location += (depth - 1) * step;
bottom_diff[location] += top_diff[location] * filters[shift + 4 * step];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23sga_right_data_backwardiPKfPfiiiiS1_
.globl _Z23sga_right_data_backwardiPKfPfiiiiS1_
.p2align 8
.type _Z23sga_right_data_backwardiPKfPfiiiiS1_,@function
_Z23sga_right_data_backwardiPKfPfiiiiS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_18
s_load_b64 s[8:9], s[0:1], 0x18
v_ashrrev_i32_e32 v3, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v3
v_xor_b32_e32 v4, v4, v3
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s8, 31
s_mul_i32 s10, s9, s8
s_add_i32 s3, s8, s2
v_xor_b32_e32 v3, s2, v3
s_xor_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s4, 0, s3
s_cmp_lt_i32 s9, 1
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s4, v0
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_load_b128 s[0:3], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v22, v0, v3
v_mul_lo_u32 v0, v22, s8
v_mul_lo_u32 v21, v22, s10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v1, v0
v_mul_lo_u32 v0, v0, s9
s_cbranch_scc1 .LBB0_15
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, v21, s1, v[0:1]
s_cselect_b32 s11, -1, 0
s_add_i32 s12, s0, -1
v_mul_lo_u32 v4, v22, s12
s_mov_b32 s12, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v23, s10, v2
v_lshl_add_u32 v24, s10, 2, v2
v_add_nc_u32_e32 v3, -1, v4
v_mul_lo_u32 v5, v4, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[6:7], null, s8, v3, v[1:2]
v_mad_u64_u32 v[3:4], null, s10, 3, v[2:3]
v_add3_u32 v7, v5, s8, v1
v_add_nc_u32_e32 v8, v1, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[4:5], null, s9, v6, s[12:13]
v_mad_u64_u32 v[5:6], null, s9, v7, s[12:13]
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[6:7], null, s9, v8, s[12:13]
s_lshl_b32 s12, s10, 1
s_mov_b32 s13, s9
s_add_i32 s12, s12, 2
s_branch .LBB0_4
.LBB0_3:
v_add_nc_u32_e32 v4, -1, v4
v_add_nc_u32_e32 v5, -1, v5
v_add_nc_u32_e32 v6, -1, v6
s_cmp_gt_i32 s14, 1
s_cbranch_scc0 .LBB0_15
.LBB0_4:
s_mov_b32 s14, s13
s_and_not1_b32 vcc_lo, exec_lo, s11
s_add_i32 s13, s13, -1
s_cbranch_vccnz .LBB0_3
v_add_nc_u32_e32 v13, s13, v2
v_add_nc_u32_e32 v7, s14, v23
v_add_nc_u32_e32 v9, s14, v3
v_add_nc_u32_e32 v11, s14, v24
s_cmp_lt_i32 s14, s9
v_add_nc_u32_e32 v14, s12, v13
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
s_cselect_b32 s15, -1, 0
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_lshlrev_b64 v[16:17], 2, v[9:10]
v_lshlrev_b64 v[18:19], 2, v[11:12]
s_add_i32 s16, s14, 1
v_lshlrev_b64 v[9:10], 2, v[14:15]
v_ashrrev_i32_e32 v14, 31, v13
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v16
v_lshlrev_b64 v[15:16], 2, v[13:14]
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v17, vcc_lo
v_add_co_u32 v13, vcc_lo, s4, v18
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v19, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v15, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
s_cmp_lt_i32 s16, s9
s_mov_b32 s17, 0
s_cselect_b32 s16, -1, 0
s_xor_b32 s18, s15, -1
s_mov_b32 s19, 0
s_branch .LBB0_7
.LBB0_6:
v_add_co_u32 v19, vcc_lo, s2, v19
v_add_co_ci_u32_e32 v20, vcc_lo, s3, v20, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[17:18], v25, off
s_add_i32 s17, s17, s10
global_load_b32 v17, v[15:16], off
global_load_b32 v18, v[19:20], off
s_cmp_eq_u32 s0, s20
s_mov_b32 s19, s20
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v18, v25, v17
global_store_b32 v[19:20], v18, off
s_cbranch_scc1 .LBB0_3
.LBB0_7:
v_add3_u32 v17, v6, s17, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v18, 31, v17
v_lshlrev_b64 v[19:20], 2, v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v17, vcc_lo, s6, v19
v_add_co_ci_u32_e32 v18, vcc_lo, s7, v20, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s15
global_load_b32 v25, v[17:18], off
s_cbranch_vccnz .LBB0_9
v_add_nc_u32_e32 v26, s17, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v27, 31, v26
v_lshlrev_b64 v[26:27], 2, v[26:27]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v26, vcc_lo, s6, v26
v_add_co_ci_u32_e32 v27, vcc_lo, s7, v27, vcc_lo
global_load_b32 v26, v[26:27], off
global_load_b32 v27, v[7:8], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v25, v26, v27
.LBB0_9:
s_and_not1_b32 vcc_lo, exec_lo, s16
s_cbranch_vccnz .LBB0_11
global_load_b32 v26, v[17:18], off offset:8
global_load_b32 v27, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v25, v26, v27
.LBB0_11:
s_add_i32 s20, s19, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_cmp_lt_i32 s20, s0
s_cselect_b32 s21, -1, 0
s_and_b32 s21, s15, s21
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s21
s_cbranch_vccnz .LBB0_13
v_add_nc_u32_e32 v26, s17, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v27, 31, v26
v_lshlrev_b64 v[26:27], 2, v[26:27]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v26, vcc_lo, s6, v26
v_add_co_ci_u32_e32 v27, vcc_lo, s7, v27, vcc_lo
global_load_b32 v26, v[26:27], off
global_load_b32 v27, v[11:12], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v25, v26, v27
.LBB0_13:
s_cmp_eq_u32 s19, 0
s_cselect_b32 s19, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s19, s18, s19
s_and_b32 vcc_lo, exec_lo, s19
s_cbranch_vccnz .LBB0_6
v_add_nc_u32_e32 v26, s17, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v27, 31, v26
v_lshlrev_b64 v[26:27], 2, v[26:27]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v26, vcc_lo, s6, v26
v_add_co_ci_u32_e32 v27, vcc_lo, s7, v27, vcc_lo
global_load_b32 v26, v[26:27], off
global_load_b32 v27, v[13:14], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v25, v26, v27
s_branch .LBB0_6
.LBB0_15:
s_cmp_lt_i32 s9, 1
s_cbranch_scc1 .LBB0_18
s_waitcnt lgkmcnt(0)
s_add_i32 s1, s1, -1
v_mad_u64_u32 v[2:3], null, s8, v22, s[8:9]
v_mul_lo_u32 v4, v22, s1
s_add_i32 s1, s0, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, 3, v4
v_add_nc_u32_e32 v7, 4, v4
v_mad_u64_u32 v[3:4], null, s8, v5, v[1:2]
v_mad_u64_u32 v[4:5], null, v2, s1, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[5:6], null, s8, v7, v[1:2]
v_mul_lo_u32 v1, s9, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v3, s9, v4
v_mul_lo_u32 v8, s9, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[6:7], null, v21, s0, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[10:11], 2, v[1:2]
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_u32 v4, vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[6:7]
v_lshlrev_b64 v[6:7], 2, v[8:9]
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v11, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_17:
v_add_co_u32 v8, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v10, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v1, vcc_lo
global_load_b32 v13, v[4:5], off
global_load_b32 v14, v[8:9], off
global_load_b32 v15, v[10:11], off
v_add_co_u32 v8, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v12, vcc_lo, s2, v2
s_add_i32 s9, s9, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s9, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v15, v14, v13
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, 4
global_store_b32 v[10:11], v15, off
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[6:7], off
global_load_b32 v10, v[12:13], off
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v10, v8, v9
global_store_b32 v[12:13], v10, off
s_cbranch_scc1 .LBB0_17
.LBB0_18:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23sga_right_data_backwardiPKfPfiiiiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 28
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23sga_right_data_backwardiPKfPfiiiiS1_, .Lfunc_end0-_Z23sga_right_data_backwardiPKfPfiiiiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23sga_right_data_backwardiPKfPfiiiiS1_
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z23sga_right_data_backwardiPKfPfiiiiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 28
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sga_right_data_backward (const int n, const float *filters, float *top_diff, const int height, const int width, const int depth, const int wsize, float *bottom_diff){
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= n)
{
return;
}
int step = height * width;
int base = index / height * step * depth + (index % height) * width; //up->down
int fbase = index / height * step * wsize + (index % height) * width;
for (int col = width - 1; col >= 0; col--)
{
int shift = fbase + col;
for (int d = 0; d < depth; d++)
{
int location = base + d * step + col;
float temp = top_diff[location];
if (col + 1 < width)
temp += top_diff[location + 1] * filters[shift + 1 + step];
if (col + 2 < width)
temp += top_diff[location + 2] * filters[shift + 2 + 2 * step];
if (col + 1 < width && d + 1 < depth)
temp +=
top_diff[location + 1 + step] * filters[shift + 1 + 3 * step];
if (col + 1 < width && d - 1 >= 0)
temp +=
top_diff[location + 1 - step] * filters[shift + 1 + 4 * step];
top_diff[location] = temp;
bottom_diff[location] += (temp * filters[shift]);
}
}
/*
for(int d = 0; d < depth; d ++){
int shift = fbase;// + width*(height-1);
int location = base;// + width*(height-1) + d * step;
bottom_diff[location] += top_diff[location] * (filters[shift + step] + filters[shift + 2*step] + filters[shift + 3*step] + filters[shift + 4*step]);
// bottom_diff[location] += top_diff[location];
shift += 1;
location += 1;
bottom_diff[location] += top_diff[location] * filters[shift + 2*step];
}
for(int col=1;col<width;col++){
int shift = fbase + col;
int location = base + col;
bottom_diff[location] += top_diff[location] * filters[shift + 3*step];
location += (depth - 1)*step;
bottom_diff[location] += top_diff[location] * filters[shift + 4*step];
}*/
for (int col = 0; col < width; col++)
{
int shift = fbase + col;
int location = base + col;
bottom_diff[location] += top_diff[location] * filters[shift + 3 * step];
location += (depth - 1) * step;
bottom_diff[location] += top_diff[location] * filters[shift + 4 * step];
}
} | .text
.file "sga_right_data_backward.hip"
.globl _Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_ # -- Begin function _Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_
.p2align 4, 0x90
.type _Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_,@function
_Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_: # @_Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23sga_right_data_backwardiPKfPfiiiiS1_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_, .Lfunc_end0-_Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23sga_right_data_backwardiPKfPfiiiiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23sga_right_data_backwardiPKfPfiiiiS1_,@object # @_Z23sga_right_data_backwardiPKfPfiiiiS1_
.section .rodata,"a",@progbits
.globl _Z23sga_right_data_backwardiPKfPfiiiiS1_
.p2align 3, 0x0
_Z23sga_right_data_backwardiPKfPfiiiiS1_:
.quad _Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_
.size _Z23sga_right_data_backwardiPKfPfiiiiS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23sga_right_data_backwardiPKfPfiiiiS1_"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23sga_right_data_backwardiPKfPfiiiiS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000be6e7_00000000-6_sga_right_data_backward.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z23sga_right_data_backwardiPKfPfiiiiS1_iPKfPfiiiiS1_
.type _Z54__device_stub__Z23sga_right_data_backwardiPKfPfiiiiS1_iPKfPfiiiiS1_, @function
_Z54__device_stub__Z23sga_right_data_backwardiPKfPfiiiiS1_iPKfPfiiiiS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 216(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z23sga_right_data_backwardiPKfPfiiiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z23sga_right_data_backwardiPKfPfiiiiS1_iPKfPfiiiiS1_, .-_Z54__device_stub__Z23sga_right_data_backwardiPKfPfiiiiS1_iPKfPfiiiiS1_
.globl _Z23sga_right_data_backwardiPKfPfiiiiS1_
.type _Z23sga_right_data_backwardiPKfPfiiiiS1_, @function
_Z23sga_right_data_backwardiPKfPfiiiiS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z54__device_stub__Z23sga_right_data_backwardiPKfPfiiiiS1_iPKfPfiiiiS1_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23sga_right_data_backwardiPKfPfiiiiS1_, .-_Z23sga_right_data_backwardiPKfPfiiiiS1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23sga_right_data_backwardiPKfPfiiiiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23sga_right_data_backwardiPKfPfiiiiS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sga_right_data_backward.hip"
.globl _Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_ # -- Begin function _Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_
.p2align 4, 0x90
.type _Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_,@function
_Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_: # @_Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23sga_right_data_backwardiPKfPfiiiiS1_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_, .Lfunc_end0-_Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23sga_right_data_backwardiPKfPfiiiiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23sga_right_data_backwardiPKfPfiiiiS1_,@object # @_Z23sga_right_data_backwardiPKfPfiiiiS1_
.section .rodata,"a",@progbits
.globl _Z23sga_right_data_backwardiPKfPfiiiiS1_
.p2align 3, 0x0
_Z23sga_right_data_backwardiPKfPfiiiiS1_:
.quad _Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_
.size _Z23sga_right_data_backwardiPKfPfiiiiS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23sga_right_data_backwardiPKfPfiiiiS1_"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__sga_right_data_backwardiPKfPfiiiiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23sga_right_data_backwardiPKfPfiiiiS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <math.h>
#include <ctime>
#include <iostream>
using namespace std;
int performanceMeasure1();
int performanceMeasure2();
int performanceMeasure3();
int performanceMeasure4();
int performanceMeasure5();
int countSortSerial1();
int countSortSerial2();
int countSortSerial3();
int countSortSerial4();
int countSortSerial5();
//calculate the countArray or histogram of number of times a key appears
__global__ void histogram(int * c, int * a, int K, int n)
{
//for inputArray of size n
int entry = (blockIdx.x + blockIdx.y * gridDim.x ) * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
c[entry] = 0;
//if out of range then return
if (entry < 0 || entry >= n) return;
//Get the value at the index
int value = a[entry];
//update the counterArray at the value index by 1
int *valueCount = &c[value];
atomicAdd(valueCount, 1);
}
//calculate the prefix sum using a naive stride method
__global__ void naivePrefixSum(int *b, int *c, int k)
{
int entry = threadIdx.x;
if (entry < 0 || entry >= k) return;
b[entry] = c[entry];
//printf("c %d\n", b[entry]);
__syncthreads();
//naive parallel stride prefix sum
for(int i = 1; i < k; i *= 2)
{
if(entry > i-1)
{
b[entry] = b[entry] + b[entry - i];
}
__syncthreads();
}
//printf("\nb %d", b[entry]);
}
//from the prefix sum, place the numbers in the correct postion in the array
__global__ void copyToArray(int * c, int * a, int * b, int Kp, int n)
{
extern __shared__ int temp[];
int entry = (blockIdx.x + blockIdx.y * gridDim.x ) * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
if (entry < 0 || entry >= n) return;
//get value at the inputArray at an index
int value = a[entry];
//get the index for the value
int index = atomicAdd(&c[value], -1);
b[index-1] = value;
}
int main() {
//Start Debug Test
printf("\nDebug Start\n");
///Test n elements with certain number of keys
const int n = 1024;
const int keys = 257;
//Setup Array on host and device
int i_h[n] = {0};
printf("\nInput:\n ");
//An input array i_h (input array on host) with n elements with in the range of 0 to 256 and is a power of 2.
for(int i = 0; i < n; i++){
i_h[i] = pow(2,(std::rand() % 9));
printf("%d ", i_h[i]);
}
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
cudaMalloc((void **)&i_d, sizeof(int)*n);
cudaMalloc((void **)&o_d, sizeof(int)*n);
cudaMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
cudaMemcpy(i_d, i_h, sizeof(int)*n, cudaMemcpyHostToDevice);
cudaMemcpy(o_d, o_d, sizeof(int)*n, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, sizeof(int)*keys, cudaMemcpyHostToDevice);
//CountSortFunction
//Get histogram
histogram <<<6, n>>>(c_d,i_d,keys,n);
cudaMemcpy(c_h, c_d, sizeof(int)*keys, cudaMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,n>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,n>>>(c_d,i_d,o_d,keys,n);
//Get answer
cudaMemcpy(o_h, o_d, sizeof(int)*n, cudaMemcpyDeviceToHost);
//print answer
printf("\nOutput:\n ");
for (int i = 0; i < n; ++i) printf("%d ", o_h[i]);
//free memory
cudaFree(i_d);
cudaFree(o_d);
cudaFree(c_d);
//Finish Debug Test
printf("\nFinish debug\n");
//Performance test
printf("Parallel function doesn't work on 2^21 and larger\n");
printf("tried using clock but doesn't seem to work on serial function\n");
printf("Debug test works");
countSortSerial1();
countSortSerial2();
countSortSerial3();
countSortSerial4();
countSortSerial5();
performanceMeasure1();
//performanceMeasure2();
//performanceMeasure3();
//performanceMeasure4();
//performanceMeasure5();
return 0;
}
///////////////////////////////////////////////////////////Performance Function/////////////////////////////////////////////////////////////////
int countSortSerial1()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^20 : " << duration << endl;
}
int countSortSerial2()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576*2;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^21 : " << duration << endl;
}
int countSortSerial3()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576*2;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^22 : " << duration << endl;
}
int countSortSerial4()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576*2;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^23 : " << duration << endl;
}
int countSortSerial5()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576*2;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^24 : " << duration << endl;
}
//Same function, but had trouble initalizing array from function parameter.
//so made copies of different performanceMeasure function 1 to 5 with different number of elements 2^20 to 2^24
int performanceMeasure1()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 1048576;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
cudaMalloc((void **)&i_d, sizeof(int)*elements);
cudaMalloc((void **)&o_d, sizeof(int)*elements);
cudaMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
cudaMemcpy(i_d, i_h, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(o_d, o_d, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, sizeof(int)*keys, cudaMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
cudaMemcpy(c_h, c_d, sizeof(int)*keys, cudaMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
cudaMemcpy(o_h, o_d, sizeof(int)*elements, cudaMemcpyDeviceToHost);
//free memory
cudaFree(i_d);
cudaFree(o_d);
cudaFree(c_d);
duration = ( std::clock() - start ) / (double) CLOCKS_PER_SEC;
cout << "parallel counting 2^20 : " << duration << endl;
return 0;
}
int performanceMeasure2()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 2097152;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
cudaMalloc((void **)&i_d, sizeof(int)*elements);
cudaMalloc((void **)&o_d, sizeof(int)*elements);
cudaMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
cudaMemcpy(i_d, i_h, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(o_d, o_d, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, sizeof(int)*keys, cudaMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
cudaMemcpy(c_h, c_d, sizeof(int)*keys, cudaMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
cudaMemcpy(o_h, o_d, sizeof(int)*elements, cudaMemcpyDeviceToHost);
//free memory
cudaFree(i_d);
cudaFree(o_d);
cudaFree(c_d);
cout << "parallel counting 2^21 : " << duration << endl;
return 0;
}
int performanceMeasure3()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 4194304;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
cudaMalloc((void **)&i_d, sizeof(int)*elements);
cudaMalloc((void **)&o_d, sizeof(int)*elements);
cudaMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
cudaMemcpy(i_d, i_h, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(o_d, o_d, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, sizeof(int)*keys, cudaMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
cudaMemcpy(c_h, c_d, sizeof(int)*keys, cudaMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
cudaMemcpy(o_h, o_d, sizeof(int)*elements, cudaMemcpyDeviceToHost);
//free memory
cudaFree(i_d);
cudaFree(o_d);
cudaFree(c_d);
cout << "parallel counting 2^22 : " << duration << endl;
return 0;
}
int performanceMeasure4()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 8388608;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
cudaMalloc((void **)&i_d, sizeof(int)*elements);
cudaMalloc((void **)&o_d, sizeof(int)*elements);
cudaMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
cudaMemcpy(i_d, i_h, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(o_d, o_d, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, sizeof(int)*keys, cudaMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
cudaMemcpy(c_h, c_d, sizeof(int)*keys, cudaMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
cudaMemcpy(o_h, o_d, sizeof(int)*elements, cudaMemcpyDeviceToHost);
//free memory
cudaFree(i_d);
cudaFree(o_d);
cudaFree(c_d);
cout << "parallel counting 2^23 : " << duration << endl;
return 0;
}
int performanceMeasure5()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 16777216;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
cudaMalloc((void **)&i_d, sizeof(int)*elements);
cudaMalloc((void **)&o_d, sizeof(int)*elements);
cudaMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
cudaMemcpy(i_d, i_h, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(o_d, o_d, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, sizeof(int)*keys, cudaMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
cudaMemcpy(c_h, c_d, sizeof(int)*keys, cudaMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
cudaMemcpy(o_h, o_d, sizeof(int)*elements, cudaMemcpyDeviceToHost);
//free memory
cudaFree(i_d);
cudaFree(o_d);
cudaFree(c_d);
cout << "parallel counting 2^24 : " << duration << endl;
return 0;
} | code for sm_80
Function : _Z11copyToArrayPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x001fc800078e0200 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fc80003f06270 */
/*0090*/ ISETP.LT.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000701670 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0207 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ MOV R9, 0xffffffff ; /* 0xffffffff00097802 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD.WIDE R4, R3, R7, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x004fcc00078e0207 */
/*0110*/ ATOMG.E.ADD.STRONG.GPU PT, R4, [R4.64], R9 ; /* 0x00000009040479a8 */
/* 0x000ea400081ee1c4 */
/*0120*/ IADD3 R6, R4, -0x1, RZ ; /* 0xffffffff04067810 */
/* 0x004fca0007ffe0ff */
/*0130*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fca00078e0207 */
/*0140*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14naivePrefixSumPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x170], PT ; /* 0x00005c0009007a0c */
/* 0x001fc80003f06270 */
/*0030*/ ISETP.LT.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000701670 */
/*0040*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0050*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0070*/ IMAD.WIDE R2, R9, R4, c[0x0][0x168] ; /* 0x00005a0009027625 */
/* 0x000fcc00078e0204 */
/*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.WIDE R4, R9, R4, c[0x0][0x160] ; /* 0x0000580009047625 */
/* 0x000fe200078e0204 */
/*00a0*/ MOV R0, c[0x0][0x170] ; /* 0x00005c0000007a02 */
/* 0x000fc80000000f00 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f06270 */
/*00c0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041e8000c101904 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x001fca00078e00ff */
/*0100*/ ISETP.GE.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe20003f06270 */
/*0110*/ BSSY B0, 0x1b0 ; /* 0x0000009000007945 */
/* 0x000fd80003800000 */
/*0120*/ @!P0 BRA 0x1a0 ; /* 0x0000007000008947 */
/* 0x001fea0003800000 */
/*0130*/ IADD3 R2, R9, -R0, RZ ; /* 0x8000000009027210 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0150*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea6000c1e1900 */
/*0160*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0170*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0180*/ IADD3 R7, R6, R3, RZ ; /* 0x0000000306077210 */
/* 0x004fca0007ffe0ff */
/*0190*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e4000c101904 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fe200078e00ff */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*01d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*01e0*/ @!P0 BRA 0x100 ; /* 0xffffff1000008947 */
/* 0x000fea000383ffff */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9histogramPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fe200078e0207 */
/*0090*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fc800000001ff */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fc80003f06270 */
/*00b0*/ ISETP.LT.OR P0, PT, R0.reuse, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x040fe40000701670 */
/*00c0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*00d0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001ec000c101904 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x001fe40000011400 */
/*0100*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fc800078010ff */
/*0110*/ LEA.HI.X R5, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fca00000f1403 */
/*0120*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1900 */
/*0130*/ MOV R9, 0x1 ; /* 0x0000000100097802 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x004fca00078e0207 */
/*0150*/ RED.E.ADD.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x000fe2000c10e184 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <math.h>
#include <ctime>
#include <iostream>
using namespace std;
int performanceMeasure1();
int performanceMeasure2();
int performanceMeasure3();
int performanceMeasure4();
int performanceMeasure5();
int countSortSerial1();
int countSortSerial2();
int countSortSerial3();
int countSortSerial4();
int countSortSerial5();
//calculate the countArray or histogram of number of times a key appears
__global__ void histogram(int * c, int * a, int K, int n)
{
//for inputArray of size n
int entry = (blockIdx.x + blockIdx.y * gridDim.x ) * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
c[entry] = 0;
//if out of range then return
if (entry < 0 || entry >= n) return;
//Get the value at the index
int value = a[entry];
//update the counterArray at the value index by 1
int *valueCount = &c[value];
atomicAdd(valueCount, 1);
}
//calculate the prefix sum using a naive stride method
__global__ void naivePrefixSum(int *b, int *c, int k)
{
int entry = threadIdx.x;
if (entry < 0 || entry >= k) return;
b[entry] = c[entry];
//printf("c %d\n", b[entry]);
__syncthreads();
//naive parallel stride prefix sum
for(int i = 1; i < k; i *= 2)
{
if(entry > i-1)
{
b[entry] = b[entry] + b[entry - i];
}
__syncthreads();
}
//printf("\nb %d", b[entry]);
}
//from the prefix sum, place the numbers in the correct postion in the array
__global__ void copyToArray(int * c, int * a, int * b, int Kp, int n)
{
extern __shared__ int temp[];
int entry = (blockIdx.x + blockIdx.y * gridDim.x ) * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
if (entry < 0 || entry >= n) return;
//get value at the inputArray at an index
int value = a[entry];
//get the index for the value
int index = atomicAdd(&c[value], -1);
b[index-1] = value;
}
int main() {
//Start Debug Test
printf("\nDebug Start\n");
///Test n elements with certain number of keys
const int n = 1024;
const int keys = 257;
//Setup Array on host and device
int i_h[n] = {0};
printf("\nInput:\n ");
//An input array i_h (input array on host) with n elements with in the range of 0 to 256 and is a power of 2.
for(int i = 0; i < n; i++){
i_h[i] = pow(2,(std::rand() % 9));
printf("%d ", i_h[i]);
}
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
cudaMalloc((void **)&i_d, sizeof(int)*n);
cudaMalloc((void **)&o_d, sizeof(int)*n);
cudaMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
cudaMemcpy(i_d, i_h, sizeof(int)*n, cudaMemcpyHostToDevice);
cudaMemcpy(o_d, o_d, sizeof(int)*n, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, sizeof(int)*keys, cudaMemcpyHostToDevice);
//CountSortFunction
//Get histogram
histogram <<<6, n>>>(c_d,i_d,keys,n);
cudaMemcpy(c_h, c_d, sizeof(int)*keys, cudaMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,n>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,n>>>(c_d,i_d,o_d,keys,n);
//Get answer
cudaMemcpy(o_h, o_d, sizeof(int)*n, cudaMemcpyDeviceToHost);
//print answer
printf("\nOutput:\n ");
for (int i = 0; i < n; ++i) printf("%d ", o_h[i]);
//free memory
cudaFree(i_d);
cudaFree(o_d);
cudaFree(c_d);
//Finish Debug Test
printf("\nFinish debug\n");
//Performance test
printf("Parallel function doesn't work on 2^21 and larger\n");
printf("tried using clock but doesn't seem to work on serial function\n");
printf("Debug test works");
countSortSerial1();
countSortSerial2();
countSortSerial3();
countSortSerial4();
countSortSerial5();
performanceMeasure1();
//performanceMeasure2();
//performanceMeasure3();
//performanceMeasure4();
//performanceMeasure5();
return 0;
}
///////////////////////////////////////////////////////////Performance Function/////////////////////////////////////////////////////////////////
int countSortSerial1()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^20 : " << duration << endl;
}
int countSortSerial2()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576*2;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^21 : " << duration << endl;
}
int countSortSerial3()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576*2;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^22 : " << duration << endl;
}
int countSortSerial4()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576*2;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^23 : " << duration << endl;
}
int countSortSerial5()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576*2;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^24 : " << duration << endl;
}
//Same function, but had trouble initalizing array from function parameter.
//so made copies of different performanceMeasure function 1 to 5 with different number of elements 2^20 to 2^24
int performanceMeasure1()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 1048576;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
cudaMalloc((void **)&i_d, sizeof(int)*elements);
cudaMalloc((void **)&o_d, sizeof(int)*elements);
cudaMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
cudaMemcpy(i_d, i_h, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(o_d, o_d, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, sizeof(int)*keys, cudaMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
cudaMemcpy(c_h, c_d, sizeof(int)*keys, cudaMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
cudaMemcpy(o_h, o_d, sizeof(int)*elements, cudaMemcpyDeviceToHost);
//free memory
cudaFree(i_d);
cudaFree(o_d);
cudaFree(c_d);
duration = ( std::clock() - start ) / (double) CLOCKS_PER_SEC;
cout << "parallel counting 2^20 : " << duration << endl;
return 0;
}
int performanceMeasure2()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 2097152;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
cudaMalloc((void **)&i_d, sizeof(int)*elements);
cudaMalloc((void **)&o_d, sizeof(int)*elements);
cudaMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
cudaMemcpy(i_d, i_h, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(o_d, o_d, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, sizeof(int)*keys, cudaMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
cudaMemcpy(c_h, c_d, sizeof(int)*keys, cudaMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
cudaMemcpy(o_h, o_d, sizeof(int)*elements, cudaMemcpyDeviceToHost);
//free memory
cudaFree(i_d);
cudaFree(o_d);
cudaFree(c_d);
cout << "parallel counting 2^21 : " << duration << endl;
return 0;
}
int performanceMeasure3()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 4194304;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
cudaMalloc((void **)&i_d, sizeof(int)*elements);
cudaMalloc((void **)&o_d, sizeof(int)*elements);
cudaMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
cudaMemcpy(i_d, i_h, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(o_d, o_d, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, sizeof(int)*keys, cudaMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
cudaMemcpy(c_h, c_d, sizeof(int)*keys, cudaMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
cudaMemcpy(o_h, o_d, sizeof(int)*elements, cudaMemcpyDeviceToHost);
//free memory
cudaFree(i_d);
cudaFree(o_d);
cudaFree(c_d);
cout << "parallel counting 2^22 : " << duration << endl;
return 0;
}
int performanceMeasure4()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 8388608;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
cudaMalloc((void **)&i_d, sizeof(int)*elements);
cudaMalloc((void **)&o_d, sizeof(int)*elements);
cudaMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
cudaMemcpy(i_d, i_h, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(o_d, o_d, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, sizeof(int)*keys, cudaMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
cudaMemcpy(c_h, c_d, sizeof(int)*keys, cudaMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
cudaMemcpy(o_h, o_d, sizeof(int)*elements, cudaMemcpyDeviceToHost);
//free memory
cudaFree(i_d);
cudaFree(o_d);
cudaFree(c_d);
cout << "parallel counting 2^23 : " << duration << endl;
return 0;
}
int performanceMeasure5()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 16777216;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
cudaMalloc((void **)&i_d, sizeof(int)*elements);
cudaMalloc((void **)&o_d, sizeof(int)*elements);
cudaMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
cudaMemcpy(i_d, i_h, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(o_d, o_d, sizeof(int)*elements, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, sizeof(int)*keys, cudaMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
cudaMemcpy(c_h, c_d, sizeof(int)*keys, cudaMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
cudaMemcpy(o_h, o_d, sizeof(int)*elements, cudaMemcpyDeviceToHost);
//free memory
cudaFree(i_d);
cudaFree(o_d);
cudaFree(c_d);
cout << "parallel counting 2^24 : " << duration << endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <math.h>
#include <ctime>
#include <iostream>
using namespace std;
int performanceMeasure1();
int performanceMeasure2();
int performanceMeasure3();
int performanceMeasure4();
int performanceMeasure5();
int countSortSerial1();
int countSortSerial2();
int countSortSerial3();
int countSortSerial4();
int countSortSerial5();
//calculate the countArray or histogram of number of times a key appears
__global__ void histogram(int * c, int * a, int K, int n)
{
//for inputArray of size n
int entry = (blockIdx.x + blockIdx.y * gridDim.x ) * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
c[entry] = 0;
//if out of range then return
if (entry < 0 || entry >= n) return;
//Get the value at the index
int value = a[entry];
//update the counterArray at the value index by 1
int *valueCount = &c[value];
atomicAdd(valueCount, 1);
}
//calculate the prefix sum using a naive stride method
__global__ void naivePrefixSum(int *b, int *c, int k)
{
int entry = threadIdx.x;
if (entry < 0 || entry >= k) return;
b[entry] = c[entry];
//printf("c %d\n", b[entry]);
__syncthreads();
//naive parallel stride prefix sum
for(int i = 1; i < k; i *= 2)
{
if(entry > i-1)
{
b[entry] = b[entry] + b[entry - i];
}
__syncthreads();
}
//printf("\nb %d", b[entry]);
}
//from the prefix sum, place the numbers in the correct postion in the array
__global__ void copyToArray(int * c, int * a, int * b, int Kp, int n)
{
extern __shared__ int temp[];
int entry = (blockIdx.x + blockIdx.y * gridDim.x ) * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
if (entry < 0 || entry >= n) return;
//get value at the inputArray at an index
int value = a[entry];
//get the index for the value
int index = atomicAdd(&c[value], -1);
b[index-1] = value;
}
int main() {
//Start Debug Test
printf("\nDebug Start\n");
///Test n elements with certain number of keys
const int n = 1024;
const int keys = 257;
//Setup Array on host and device
int i_h[n] = {0};
printf("\nInput:\n ");
//An input array i_h (input array on host) with n elements with in the range of 0 to 256 and is a power of 2.
for(int i = 0; i < n; i++){
i_h[i] = pow(2,(std::rand() % 9));
printf("%d ", i_h[i]);
}
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
hipMalloc((void **)&i_d, sizeof(int)*n);
hipMalloc((void **)&o_d, sizeof(int)*n);
hipMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
hipMemcpy(i_d, i_h, sizeof(int)*n, hipMemcpyHostToDevice);
hipMemcpy(o_d, o_d, sizeof(int)*n, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, sizeof(int)*keys, hipMemcpyHostToDevice);
//CountSortFunction
//Get histogram
histogram <<<6, n>>>(c_d,i_d,keys,n);
hipMemcpy(c_h, c_d, sizeof(int)*keys, hipMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,n>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,n>>>(c_d,i_d,o_d,keys,n);
//Get answer
hipMemcpy(o_h, o_d, sizeof(int)*n, hipMemcpyDeviceToHost);
//print answer
printf("\nOutput:\n ");
for (int i = 0; i < n; ++i) printf("%d ", o_h[i]);
//free memory
hipFree(i_d);
hipFree(o_d);
hipFree(c_d);
//Finish Debug Test
printf("\nFinish debug\n");
//Performance test
printf("Parallel function doesn't work on 2^21 and larger\n");
printf("tried using clock but doesn't seem to work on serial function\n");
printf("Debug test works");
countSortSerial1();
countSortSerial2();
countSortSerial3();
countSortSerial4();
countSortSerial5();
performanceMeasure1();
//performanceMeasure2();
//performanceMeasure3();
//performanceMeasure4();
//performanceMeasure5();
return 0;
}
///////////////////////////////////////////////////////////Performance Function/////////////////////////////////////////////////////////////////
int countSortSerial1()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^20 : " << duration << endl;
}
int countSortSerial2()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576*2;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^21 : " << duration << endl;
}
int countSortSerial3()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576*2;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^22 : " << duration << endl;
}
int countSortSerial4()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576*2;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^23 : " << duration << endl;
}
int countSortSerial5()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576*2;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^24 : " << duration << endl;
}
//Same function, but had trouble initalizing array from function parameter.
//so made copies of different performanceMeasure function 1 to 5 with different number of elements 2^20 to 2^24
int performanceMeasure1()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 1048576;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
hipMalloc((void **)&i_d, sizeof(int)*elements);
hipMalloc((void **)&o_d, sizeof(int)*elements);
hipMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
hipMemcpy(i_d, i_h, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(o_d, o_d, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, sizeof(int)*keys, hipMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
hipMemcpy(c_h, c_d, sizeof(int)*keys, hipMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
hipMemcpy(o_h, o_d, sizeof(int)*elements, hipMemcpyDeviceToHost);
//free memory
hipFree(i_d);
hipFree(o_d);
hipFree(c_d);
duration = ( std::clock() - start ) / (double) CLOCKS_PER_SEC;
cout << "parallel counting 2^20 : " << duration << endl;
return 0;
}
int performanceMeasure2()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 2097152;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
hipMalloc((void **)&i_d, sizeof(int)*elements);
hipMalloc((void **)&o_d, sizeof(int)*elements);
hipMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
hipMemcpy(i_d, i_h, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(o_d, o_d, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, sizeof(int)*keys, hipMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
hipMemcpy(c_h, c_d, sizeof(int)*keys, hipMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
hipMemcpy(o_h, o_d, sizeof(int)*elements, hipMemcpyDeviceToHost);
//free memory
hipFree(i_d);
hipFree(o_d);
hipFree(c_d);
cout << "parallel counting 2^21 : " << duration << endl;
return 0;
}
int performanceMeasure3()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 4194304;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
hipMalloc((void **)&i_d, sizeof(int)*elements);
hipMalloc((void **)&o_d, sizeof(int)*elements);
hipMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
hipMemcpy(i_d, i_h, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(o_d, o_d, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, sizeof(int)*keys, hipMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
hipMemcpy(c_h, c_d, sizeof(int)*keys, hipMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
hipMemcpy(o_h, o_d, sizeof(int)*elements, hipMemcpyDeviceToHost);
//free memory
hipFree(i_d);
hipFree(o_d);
hipFree(c_d);
cout << "parallel counting 2^22 : " << duration << endl;
return 0;
}
int performanceMeasure4()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 8388608;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
hipMalloc((void **)&i_d, sizeof(int)*elements);
hipMalloc((void **)&o_d, sizeof(int)*elements);
hipMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
hipMemcpy(i_d, i_h, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(o_d, o_d, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, sizeof(int)*keys, hipMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
hipMemcpy(c_h, c_d, sizeof(int)*keys, hipMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
hipMemcpy(o_h, o_d, sizeof(int)*elements, hipMemcpyDeviceToHost);
//free memory
hipFree(i_d);
hipFree(o_d);
hipFree(c_d);
cout << "parallel counting 2^23 : " << duration << endl;
return 0;
}
int performanceMeasure5()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 16777216;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
hipMalloc((void **)&i_d, sizeof(int)*elements);
hipMalloc((void **)&o_d, sizeof(int)*elements);
hipMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
hipMemcpy(i_d, i_h, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(o_d, o_d, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, sizeof(int)*keys, hipMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
hipMemcpy(c_h, c_d, sizeof(int)*keys, hipMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
hipMemcpy(o_h, o_d, sizeof(int)*elements, hipMemcpyDeviceToHost);
//free memory
hipFree(i_d);
hipFree(o_d);
hipFree(c_d);
cout << "parallel counting 2^24 : " << duration << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <math.h>
#include <ctime>
#include <iostream>
using namespace std;
int performanceMeasure1();
int performanceMeasure2();
int performanceMeasure3();
int performanceMeasure4();
int performanceMeasure5();
int countSortSerial1();
int countSortSerial2();
int countSortSerial3();
int countSortSerial4();
int countSortSerial5();
//calculate the countArray or histogram of number of times a key appears
__global__ void histogram(int * c, int * a, int K, int n)
{
//for inputArray of size n
int entry = (blockIdx.x + blockIdx.y * gridDim.x ) * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
c[entry] = 0;
//if out of range then return
if (entry < 0 || entry >= n) return;
//Get the value at the index
int value = a[entry];
//update the counterArray at the value index by 1
int *valueCount = &c[value];
atomicAdd(valueCount, 1);
}
//calculate the prefix sum using a naive stride method
__global__ void naivePrefixSum(int *b, int *c, int k)
{
int entry = threadIdx.x;
if (entry < 0 || entry >= k) return;
b[entry] = c[entry];
//printf("c %d\n", b[entry]);
__syncthreads();
//naive parallel stride prefix sum
for(int i = 1; i < k; i *= 2)
{
if(entry > i-1)
{
b[entry] = b[entry] + b[entry - i];
}
__syncthreads();
}
//printf("\nb %d", b[entry]);
}
//from the prefix sum, place the numbers in the correct postion in the array
__global__ void copyToArray(int * c, int * a, int * b, int Kp, int n)
{
extern __shared__ int temp[];
int entry = (blockIdx.x + blockIdx.y * gridDim.x ) * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x;
if (entry < 0 || entry >= n) return;
//get value at the inputArray at an index
int value = a[entry];
//get the index for the value
int index = atomicAdd(&c[value], -1);
b[index-1] = value;
}
int main() {
//Start Debug Test
printf("\nDebug Start\n");
///Test n elements with certain number of keys
const int n = 1024;
const int keys = 257;
//Setup Array on host and device
int i_h[n] = {0};
printf("\nInput:\n ");
//An input array i_h (input array on host) with n elements with in the range of 0 to 256 and is a power of 2.
for(int i = 0; i < n; i++){
i_h[i] = pow(2,(std::rand() % 9));
printf("%d ", i_h[i]);
}
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
hipMalloc((void **)&i_d, sizeof(int)*n);
hipMalloc((void **)&o_d, sizeof(int)*n);
hipMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
hipMemcpy(i_d, i_h, sizeof(int)*n, hipMemcpyHostToDevice);
hipMemcpy(o_d, o_d, sizeof(int)*n, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, sizeof(int)*keys, hipMemcpyHostToDevice);
//CountSortFunction
//Get histogram
histogram <<<6, n>>>(c_d,i_d,keys,n);
hipMemcpy(c_h, c_d, sizeof(int)*keys, hipMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,n>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,n>>>(c_d,i_d,o_d,keys,n);
//Get answer
hipMemcpy(o_h, o_d, sizeof(int)*n, hipMemcpyDeviceToHost);
//print answer
printf("\nOutput:\n ");
for (int i = 0; i < n; ++i) printf("%d ", o_h[i]);
//free memory
hipFree(i_d);
hipFree(o_d);
hipFree(c_d);
//Finish Debug Test
printf("\nFinish debug\n");
//Performance test
printf("Parallel function doesn't work on 2^21 and larger\n");
printf("tried using clock but doesn't seem to work on serial function\n");
printf("Debug test works");
countSortSerial1();
countSortSerial2();
countSortSerial3();
countSortSerial4();
countSortSerial5();
performanceMeasure1();
//performanceMeasure2();
//performanceMeasure3();
//performanceMeasure4();
//performanceMeasure5();
return 0;
}
///////////////////////////////////////////////////////////Performance Function/////////////////////////////////////////////////////////////////
int countSortSerial1()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^20 : " << duration << endl;
}
int countSortSerial2()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576*2;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^21 : " << duration << endl;
}
int countSortSerial3()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576*2;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^22 : " << duration << endl;
}
int countSortSerial4()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576*2;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^23 : " << duration << endl;
}
int countSortSerial5()
{
std::clock_t start;
double duration;
start = std::clock();
const int elements = 1048576*2;
const int keys = 257;
int inputArray[elements] = {0};
int output[elements] = {0};
for(int i = 0; i < elements; i++)
inputArray[i] = pow(2,(std::rand() % 9));
int count[elements + 1] = {0};
//Initalize the count array and count the number of keys
for(int i = 0; inputArray[i]; ++i)
++count[inputArray[i]];
//calculate the starting index for each key
int total = 0;
int oldCount;
for (int i = 0; i <= keys; ++i)
{
oldCount = count[i];
count[i] = total;
total += oldCount;
}
// Build the output character array
for (int i = 0; inputArray[i]; ++i)
{
output[count[inputArray[i]]-1] = inputArray[i];
--count[inputArray[i]];
}
cout << "serial counting 2^24 : " << duration << endl;
}
//Same function, but had trouble initalizing array from function parameter.
//so made copies of different performanceMeasure function 1 to 5 with different number of elements 2^20 to 2^24
int performanceMeasure1()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 1048576;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
hipMalloc((void **)&i_d, sizeof(int)*elements);
hipMalloc((void **)&o_d, sizeof(int)*elements);
hipMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
hipMemcpy(i_d, i_h, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(o_d, o_d, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, sizeof(int)*keys, hipMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
hipMemcpy(c_h, c_d, sizeof(int)*keys, hipMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
hipMemcpy(o_h, o_d, sizeof(int)*elements, hipMemcpyDeviceToHost);
//free memory
hipFree(i_d);
hipFree(o_d);
hipFree(c_d);
duration = ( std::clock() - start ) / (double) CLOCKS_PER_SEC;
cout << "parallel counting 2^20 : " << duration << endl;
return 0;
}
int performanceMeasure2()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 2097152;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
hipMalloc((void **)&i_d, sizeof(int)*elements);
hipMalloc((void **)&o_d, sizeof(int)*elements);
hipMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
hipMemcpy(i_d, i_h, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(o_d, o_d, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, sizeof(int)*keys, hipMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
hipMemcpy(c_h, c_d, sizeof(int)*keys, hipMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
hipMemcpy(o_h, o_d, sizeof(int)*elements, hipMemcpyDeviceToHost);
//free memory
hipFree(i_d);
hipFree(o_d);
hipFree(c_d);
cout << "parallel counting 2^21 : " << duration << endl;
return 0;
}
int performanceMeasure3()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 4194304;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
hipMalloc((void **)&i_d, sizeof(int)*elements);
hipMalloc((void **)&o_d, sizeof(int)*elements);
hipMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
hipMemcpy(i_d, i_h, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(o_d, o_d, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, sizeof(int)*keys, hipMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
hipMemcpy(c_h, c_d, sizeof(int)*keys, hipMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
hipMemcpy(o_h, o_d, sizeof(int)*elements, hipMemcpyDeviceToHost);
//free memory
hipFree(i_d);
hipFree(o_d);
hipFree(c_d);
cout << "parallel counting 2^22 : " << duration << endl;
return 0;
}
int performanceMeasure4()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 8388608;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
hipMalloc((void **)&i_d, sizeof(int)*elements);
hipMalloc((void **)&o_d, sizeof(int)*elements);
hipMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
hipMemcpy(i_d, i_h, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(o_d, o_d, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, sizeof(int)*keys, hipMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
hipMemcpy(c_h, c_d, sizeof(int)*keys, hipMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
hipMemcpy(o_h, o_d, sizeof(int)*elements, hipMemcpyDeviceToHost);
//free memory
hipFree(i_d);
hipFree(o_d);
hipFree(c_d);
cout << "parallel counting 2^23 : " << duration << endl;
return 0;
}
int performanceMeasure5()
{
std::clock_t start;
double duration;
start = std::clock();
//number of elements and number of keys
const int elements = 16777216;
const int keys = 257;
//setup device and host array variables
int i_h[elements] = {0};
for(int i = 0; i < elements; i++)
i_h[i] = pow(2,(std::rand() % 9));
int o_h[keys] = {0};
int c_h[keys] = {0};
int *i_d, *o_d, *c_d;
//setup array on gpu
hipMalloc((void **)&i_d, sizeof(int)*elements);
hipMalloc((void **)&o_d, sizeof(int)*elements);
hipMalloc((void **)&c_d, sizeof(int)*keys);
//copy values from input,etc..
hipMemcpy(i_d, i_h, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(o_d, o_d, sizeof(int)*elements, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, sizeof(int)*keys, hipMemcpyHostToDevice);
//countsort
//Get histogram
histogram <<<6, elements>>>(c_d,i_d,keys,elements);
hipMemcpy(c_h, c_d, sizeof(int)*keys, hipMemcpyDeviceToHost);
//Calculate Prefix sum
naivePrefixSum<<<1,elements>>>(c_d,c_d,keys);
//Fill in array
copyToArray<<<6,elements>>>(c_d,i_d,o_d,keys,elements);
//Get answer
hipMemcpy(o_h, o_d, sizeof(int)*elements, hipMemcpyDeviceToHost);
//free memory
hipFree(i_d);
hipFree(o_d);
hipFree(c_d);
cout << "parallel counting 2^24 : " << duration << endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9histogramPiS_ii
.globl _Z9histogramPiS_ii
.p2align 8
.type _Z9histogramPiS_ii,@function
_Z9histogramPiS_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x14
s_load_b32 s6, s[0:1], 0x24
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_lshr_b32 s4, s6, 16
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s3, s4, v[1:2]
s_and_b32 s3, s6, 0xffff
s_load_b64 s[4:5], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v2, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_cmp_lt_i32_e32 vcc_lo, -1, v3
v_cmp_gt_i32_e64 s2, s2, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s3, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s3, s5, v1, s3
global_store_b32 v[2:3], v4, off
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9histogramPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9histogramPiS_ii, .Lfunc_end0-_Z9histogramPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14naivePrefixSumPiS_i
.globl _Z14naivePrefixSumPiS_i
.p2align 8
.type _Z14naivePrefixSumPiS_i,@function
_Z14naivePrefixSumPiS_i:
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB1_6
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_i32 s4, 2
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[2:3]
s_waitcnt vmcnt(0)
global_store_b32 v1, v2, s[0:1]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_6
v_add_co_u32 v1, s2, s0, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s1, 0, s2
s_mov_b32 s2, 1
s_branch .LBB1_4
.p2align 6
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s3
s_lshl_b32 s2, s2, 1
s_waitcnt_vscnt null, 0x0
s_cmp_lt_i32 s2, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_6
.LBB1_4:
s_mov_b32 s3, exec_lo
v_cmpx_le_u32_e64 s2, v0
s_cbranch_execz .LBB1_3
v_subrev_nc_u32_e32 v3, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_clause 0x1
global_load_b32 v5, v[1:2], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v3, v5
global_store_b32 v[1:2], v3, off
s_branch .LBB1_3
.LBB1_6:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14naivePrefixSumPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14naivePrefixSumPiS_i, .Lfunc_end1-_Z14naivePrefixSumPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11copyToArrayPiS_S_ii
.globl _Z11copyToArrayPiS_S_ii
.p2align 8
.type _Z11copyToArrayPiS_S_ii,@function
_Z11copyToArrayPiS_S_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x2c
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_lshr_b32 s5, s4, 16
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s3, s5, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v2, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v0
v_cmp_gt_i32_e64 s2, s2, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v3, -1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_atomic_add_u32 v1, v[1:2], v3, off glc
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off offset:-4
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11copyToArrayPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z11copyToArrayPiS_S_ii, .Lfunc_end2-_Z11copyToArrayPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9histogramPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9histogramPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14naivePrefixSumPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z14naivePrefixSumPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11copyToArrayPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11copyToArrayPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11copyToArrayPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x001fc800078e0200 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fc80003f06270 */
/*0090*/ ISETP.LT.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000701670 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0207 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ MOV R9, 0xffffffff ; /* 0xffffffff00097802 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD.WIDE R4, R3, R7, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x004fcc00078e0207 */
/*0110*/ ATOMG.E.ADD.STRONG.GPU PT, R4, [R4.64], R9 ; /* 0x00000009040479a8 */
/* 0x000ea400081ee1c4 */
/*0120*/ IADD3 R6, R4, -0x1, RZ ; /* 0xffffffff04067810 */
/* 0x004fca0007ffe0ff */
/*0130*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fca00078e0207 */
/*0140*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14naivePrefixSumPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x170], PT ; /* 0x00005c0009007a0c */
/* 0x001fc80003f06270 */
/*0030*/ ISETP.LT.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000701670 */
/*0040*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0050*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0070*/ IMAD.WIDE R2, R9, R4, c[0x0][0x168] ; /* 0x00005a0009027625 */
/* 0x000fcc00078e0204 */
/*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.WIDE R4, R9, R4, c[0x0][0x160] ; /* 0x0000580009047625 */
/* 0x000fe200078e0204 */
/*00a0*/ MOV R0, c[0x0][0x170] ; /* 0x00005c0000007a02 */
/* 0x000fc80000000f00 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f06270 */
/*00c0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041e8000c101904 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x001fca00078e00ff */
/*0100*/ ISETP.GE.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe20003f06270 */
/*0110*/ BSSY B0, 0x1b0 ; /* 0x0000009000007945 */
/* 0x000fd80003800000 */
/*0120*/ @!P0 BRA 0x1a0 ; /* 0x0000007000008947 */
/* 0x001fea0003800000 */
/*0130*/ IADD3 R2, R9, -R0, RZ ; /* 0x8000000009027210 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0150*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea6000c1e1900 */
/*0160*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0170*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0180*/ IADD3 R7, R6, R3, RZ ; /* 0x0000000306077210 */
/* 0x004fca0007ffe0ff */
/*0190*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e4000c101904 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fe200078e00ff */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*01d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*01e0*/ @!P0 BRA 0x100 ; /* 0xffffff1000008947 */
/* 0x000fea000383ffff */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9histogramPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fe200078e0207 */
/*0090*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fc800000001ff */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fc80003f06270 */
/*00b0*/ ISETP.LT.OR P0, PT, R0.reuse, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x040fe40000701670 */
/*00c0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*00d0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001ec000c101904 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x001fe40000011400 */
/*0100*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fc800078010ff */
/*0110*/ LEA.HI.X R5, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fca00000f1403 */
/*0120*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1900 */
/*0130*/ MOV R9, 0x1 ; /* 0x0000000100097802 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x004fca00078e0207 */
/*0150*/ RED.E.ADD.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x000fe2000c10e184 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9histogramPiS_ii
.globl _Z9histogramPiS_ii
.p2align 8
.type _Z9histogramPiS_ii,@function
_Z9histogramPiS_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x14
s_load_b32 s6, s[0:1], 0x24
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_lshr_b32 s4, s6, 16
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s3, s4, v[1:2]
s_and_b32 s3, s6, 0xffff
s_load_b64 s[4:5], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v2, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_cmp_lt_i32_e32 vcc_lo, -1, v3
v_cmp_gt_i32_e64 s2, s2, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s3, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s3, s5, v1, s3
global_store_b32 v[2:3], v4, off
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9histogramPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9histogramPiS_ii, .Lfunc_end0-_Z9histogramPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14naivePrefixSumPiS_i
.globl _Z14naivePrefixSumPiS_i
.p2align 8
.type _Z14naivePrefixSumPiS_i,@function
_Z14naivePrefixSumPiS_i:
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB1_6
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_i32 s4, 2
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[2:3]
s_waitcnt vmcnt(0)
global_store_b32 v1, v2, s[0:1]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_6
v_add_co_u32 v1, s2, s0, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s1, 0, s2
s_mov_b32 s2, 1
s_branch .LBB1_4
.p2align 6
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s3
s_lshl_b32 s2, s2, 1
s_waitcnt_vscnt null, 0x0
s_cmp_lt_i32 s2, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_6
.LBB1_4:
s_mov_b32 s3, exec_lo
v_cmpx_le_u32_e64 s2, v0
s_cbranch_execz .LBB1_3
v_subrev_nc_u32_e32 v3, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_clause 0x1
global_load_b32 v5, v[1:2], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v3, v5
global_store_b32 v[1:2], v3, off
s_branch .LBB1_3
.LBB1_6:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14naivePrefixSumPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14naivePrefixSumPiS_i, .Lfunc_end1-_Z14naivePrefixSumPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11copyToArrayPiS_S_ii
.globl _Z11copyToArrayPiS_S_ii
.p2align 8
.type _Z11copyToArrayPiS_S_ii,@function
_Z11copyToArrayPiS_S_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x2c
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_lshr_b32 s5, s4, 16
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s3, s5, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v2, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v0
v_cmp_gt_i32_e64 s2, s2, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v3, -1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_atomic_add_u32 v1, v[1:2], v3, off glc
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off offset:-4
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11copyToArrayPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z11copyToArrayPiS_S_ii, .Lfunc_end2-_Z11copyToArrayPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9histogramPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9histogramPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14naivePrefixSumPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z14naivePrefixSumPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11copyToArrayPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11copyToArrayPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //Required for printf()
#include <stdio.h>
//Required for pow(), sqrt()
#include <math.h>
//Represents a point on a
//Euclidean Grid
typedef struct {
int x;
int y;
char zone;
} Point;
// Thread block size
#define BLOCK_SIZE 16
//Prototype for the createVoronoi function.
__global__ void createVoronoi(Point *l_points, int gridWidth, int gridHeight,
char *l_result, int numPoints);
/*
* Copies the result array from the GPU after the zone points are calculated.
* Copies points to the GPU. The kernel finds the Zones in parallel.
*/
void getVoronoiArray(char *result, int gridHeight, int gridWidth, Point *points,
int numPoints) {
//Create pointer to char array to hold Zone results
//Allocate pointer in GPU shared memory
char *l_result;
size_t size = (gridWidth * gridHeight) * pow(BLOCK_SIZE, 2) * sizeof(char);
cudaError_t err = cudaMalloc(&l_result, size);
printf("CUDA malloc result array: %s\n", cudaGetErrorString(err));
//Create Point pointer to pass points to GPU shared memory
Point *l_points;
err = cudaMalloc((void**) &l_points, sizeof(Point) * numPoints);
printf("CUDA malloc Points: %s\n", cudaGetErrorString(err));
err = cudaMemcpy(l_points, points, sizeof(Point) * numPoints,
cudaMemcpyHostToDevice);
printf("Copy Points to GPU: %s\n", cudaGetErrorString(err));
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(gridWidth, gridHeight);
createVoronoi<<<dimGrid, dimBlock>>>(l_points, gridWidth, gridHeight, l_result, numPoints);
err = cudaThreadSynchronize();
printf("Run kernel: %s\n", cudaGetErrorString(err));
// Read the diagram from GPU into host memory
err = cudaMemcpy(result, l_result, size, cudaMemcpyDeviceToHost);
printf("Copy result from device: %s\n", cudaGetErrorString(err));
// Free device memory
cudaFree(l_result);
cudaFree(l_points);
}
/*
* Finds the Zone for each thread run. The coordinate generated is based
* on the (x,y) of the Block, and (x,y) for each thread.
*/
__device__ char getZone(Point *l_points, int x, int y, int numPoints) {
//Find the first point
double smallest = sqrt(
pow((double) l_points[0].x - x, 2)
+ pow((double) l_points[0].y - y, 2));
char zone = l_points[0].zone;
double dist_temp = 0;
//For each point
for (int i = 1; i < numPoints; i++) {
//Find distance to current point
dist_temp = sqrt(
pow((double) l_points[i].x - x, 2)
+ pow((double) l_points[i].y - y, 2));
//If Point distance is closer,
//Change the Zone value.
if (dist_temp < smallest) {
smallest = dist_temp;
zone = l_points[i].zone;
}
}
return zone;
}
/*
*Determines the coordinate of each point in the plane.
*Sets the result array equal to the appropriate Zone id.
*Runs in parallel.
*/
__global__ void createVoronoi(Point *l_points, int gridWidth, int gridHeight,
char *l_result, int numPoints) {
// X,Y Coordinate of the Block in the defined grid
int blockCol = blockIdx.x;
int blockrow = blockIdx.y;
//X,Y Coordinate of threads in each block
int row = threadIdx.y;
int col = threadIdx.x;
//Find the (x,y) point of the current value
int x = (blockCol * BLOCK_SIZE) + col;
int y = (blockrow * BLOCK_SIZE) + row;
__syncthreads();
//Set the result array to the proper zone
l_result[(y * (BLOCK_SIZE * gridWidth)) + x] = getZone(l_points, x, y, numPoints);
}
/*
* The main method of the program.
* The program takes the following parameters:
*
* int-height int-width int-x1 int-y1 char-y2 xn...
*
* Height and width define the result array
* properties, and (x1,y1) define a Euclidean
* point, and z1 defines a Zone, which in this
* case is a single char.
*
*/
int main(int argc, char* argv[]) {
//If less than 6, Not enough params to run
if (argc < 6) {
printf(
"Voronoi height, width, x1,y1,z1,x2,y2,z2 ...\nWhere height, width, x, and y are ints\nand z is a single char.");
return 1;
}
//If point params mod 3 does not equal 1
//There is an unfinished point
if ((argc - 3) % 3 != 0) {
printf(
"Voronoi height, width, x1,y1,z1,x2,y2,z2 ...\nWhere height, width, x, and y are ints\nand z is a single char.");
return 1;
}
//Read height/width of result
int height = atoi(argv[1]);
int width = atoi(argv[2]);
//The total number of points
int numPoints = (argc - 3) / 3;
//Create memory allocation for points
Point * points;
points = (Point*) malloc(numPoints * sizeof(Point));
//Read in the point values
int start = 3;
for (int i = 0; i < numPoints; i++) {
points[i].x = atoi(argv[start++]);
points[i].y = atoi(argv[start++]);
points[i].zone = argv[start++][0];
}
//Grid width - how long the cuda grid must be to obtain result
int gridWidth = (width / BLOCK_SIZE) + 1;
//Grid Width - how high the cuda grid must be to obtain result
int gridHeight = (height / BLOCK_SIZE) + 1;
//Allocate memory to hold result ( char array )
char *result;
result = (char*) malloc(
(gridWidth * gridHeight) * pow(BLOCK_SIZE, 2) * sizeof(char));
//Writes the array of zones to the result array
getVoronoiArray(result, gridHeight, gridWidth, points, numPoints);
//Shows success!
printf("Success\n\n");
//Some information for the user
printf("Height:%d, Width:%d\n\n", height, width);
//Prints the values. The lower left is the origin at (0,0).
int print_width = (BLOCK_SIZE * gridWidth) - width;
for (int i = height; i > 0; i--) {
for (int j = gridWidth * BLOCK_SIZE; j > print_width; j--)
printf("%c ", result[i * (gridWidth * BLOCK_SIZE) - j]);
printf("\n");
}
//Success
return 1;
} | .file "tmpxft_00183eaa_00000000-6_voronoi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7getZoneP5Pointiii
.type _Z7getZoneP5Pointiii, @function
_Z7getZoneP5Pointiii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z7getZoneP5Pointiii, .-_Z7getZoneP5Pointiii
.globl _Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci
.type _Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci, @function
_Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13createVoronoiP5PointiiPci(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci, .-_Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci
.globl _Z13createVoronoiP5PointiiPci
.type _Z13createVoronoiP5PointiiPci, @function
_Z13createVoronoiP5PointiiPci:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13createVoronoiP5PointiiPci, .-_Z13createVoronoiP5PointiiPci
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "CUDA malloc result array: %s\n"
.LC3:
.string "CUDA malloc Points: %s\n"
.LC4:
.string "Copy Points to GPU: %s\n"
.LC5:
.string "Run kernel: %s\n"
.LC6:
.string "Copy result from device: %s\n"
.text
.globl _Z15getVoronoiArrayPciiP5Pointi
.type _Z15getVoronoiArrayPciiP5Pointi, @function
_Z15getVoronoiArrayPciiP5Pointi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, %ebp
movl %edx, %ebx
movq %rcx, %r15
movl %r8d, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %edx, %eax
imull %esi, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC0(%rip), %xmm0
comisd .LC1(%rip), %xmm0
jnb .L14
cvttsd2siq %xmm0, %r14
.L15:
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r13d, %rax
leaq (%rax,%rax,2), %r12
salq $2, %r12
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, 32(%rsp)
movl $16, 36(%rsp)
movl %ebx, 44(%rsp)
movl %ebp, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
call cudaThreadSynchronize@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r14, %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
subsd .LC1(%rip), %xmm0
cvttsd2siq %xmm0, %r14
btcq $63, %r14
jmp .L15
.L19:
movl %r13d, %r8d
movq 16(%rsp), %rcx
movl %ebp, %edx
movl %ebx, %esi
movq 24(%rsp), %rdi
call _Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z15getVoronoiArrayPciiP5Pointi, .-_Z15getVoronoiArrayPciiP5Pointi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Voronoi height, width, x1,y1,z1,x2,y2,z2 ...\nWhere height, width, x, and y are ints\nand z is a single char."
.section .rodata.str1.1
.LC8:
.string "Success\n\n"
.LC9:
.string "Height:%d, Width:%d\n\n"
.LC10:
.string "%c "
.LC11:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
cmpl $5, %edi
jle .L35
movq %rsi, %rbx
leal -3(%rdi), %ebp
movslq %ebp, %rax
imulq $1431655766, %rax, %rax
shrq $32, %rax
movl %ebp, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,2), %eax
cmpl %eax, %ebp
jne .L36
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, %r14d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 16(%rsp)
movl %eax, 4(%rsp)
movl $3, %ecx
movl %ebp, %eax
cltd
idivl %ecx
movl %eax, %ebp
movslq %eax, %r15
imulq $12, %r15, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
addq $24, %rbx
movq %rax, %r12
imulq $24, %r15, %r15
addq %rbx, %r15
.L25:
movq (%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, (%r12)
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 4(%r12)
movq 16(%rbx), %rax
movzbl (%rax), %eax
movb %al, 8(%r12)
addq $24, %rbx
addq $12, %r12
cmpq %r15, %rbx
jne .L25
movl $16, %ecx
movl 4(%rsp), %eax
cltd
idivl %ecx
movl %eax, %ebx
leal 1(%rax), %esi
movl %esi, (%rsp)
movl %r14d, %eax
cltd
idivl %ecx
leal 1(%rax), %r12d
movl %esi, %eax
imull %r12d, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC0(%rip), %xmm0
comisd .LC1(%rip), %xmm0
jnb .L26
cvttsd2siq %xmm0, %rdi
.L27:
call malloc@PLT
movq %rax, 24(%rsp)
movl %ebp, %r8d
movq 8(%rsp), %rcx
movl (%rsp), %r15d
movl %r15d, %edx
movl %r12d, %esi
movq %rax, %rbp
movq %rax, %rdi
call _Z15getVoronoiArrayPciiP5Pointi
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %ecx
movl %r14d, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %eax
sall $4, %eax
movl %eax, %ecx
movl 16(%rsp), %edi
subl %edi, %ecx
testl %r13d, %r13d
jle .L23
imull $-16, %r15d, %edi
movl %edi, 4(%rsp)
imull %r15d, %r13d
movl %r13d, %r15d
sall $4, %r15d
leal 1(%rbx), %edx
sall $4, %edx
movslq %edx, %rsi
movq %rsi, 32(%rsp)
movslq %ebx, %rbx
salq $4, %rbx
subl $1, %edx
subl %ecx, %edx
subq %rbx, %rdx
leaq -15(%rbp,%rdx), %rsi
movq %rsi, 40(%rsp)
movl %eax, 8(%rsp)
movl %ecx, 16(%rsp)
jmp .L28
.L35:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L23
.L36:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L23:
movl $1, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
subsd .LC1(%rip), %xmm0
cvttsd2siq %xmm0, %rdi
btcq $63, %rdi
jmp .L27
.L30:
movslq %r15d, %rbx
movq 32(%rsp), %rax
subq %rax, %rbx
movq 24(%rsp), %rax
addq %rax, %rbx
movslq %r13d, %rbp
salq $4, %rbp
movq 40(%rsp), %rax
addq %rax, %rbp
leaq .LC10(%rip), %r12
.L29:
movsbl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L29
.L31:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %eax
addl %eax, %r15d
movl (%rsp), %eax
subl %eax, %r13d
subl $1, %r14d
je .L23
.L28:
movl 16(%rsp), %ecx
cmpl %ecx, 8(%rsp)
jg .L30
jmp .L31
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z13createVoronoiP5PointiiPci"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z13createVoronoiP5PointiiPci(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1081081856
.align 8
.LC1:
.long 0
.long 1138753536
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //Required for printf()
#include <stdio.h>
//Required for pow(), sqrt()
#include <math.h>
//Represents a point on a
//Euclidean Grid
typedef struct {
int x;
int y;
char zone;
} Point;
// Thread block size
#define BLOCK_SIZE 16
//Prototype for the createVoronoi function.
__global__ void createVoronoi(Point *l_points, int gridWidth, int gridHeight,
char *l_result, int numPoints);
/*
* Copies the result array from the GPU after the zone points are calculated.
* Copies points to the GPU. The kernel finds the Zones in parallel.
*/
void getVoronoiArray(char *result, int gridHeight, int gridWidth, Point *points,
int numPoints) {
//Create pointer to char array to hold Zone results
//Allocate pointer in GPU shared memory
char *l_result;
size_t size = (gridWidth * gridHeight) * pow(BLOCK_SIZE, 2) * sizeof(char);
cudaError_t err = cudaMalloc(&l_result, size);
printf("CUDA malloc result array: %s\n", cudaGetErrorString(err));
//Create Point pointer to pass points to GPU shared memory
Point *l_points;
err = cudaMalloc((void**) &l_points, sizeof(Point) * numPoints);
printf("CUDA malloc Points: %s\n", cudaGetErrorString(err));
err = cudaMemcpy(l_points, points, sizeof(Point) * numPoints,
cudaMemcpyHostToDevice);
printf("Copy Points to GPU: %s\n", cudaGetErrorString(err));
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(gridWidth, gridHeight);
createVoronoi<<<dimGrid, dimBlock>>>(l_points, gridWidth, gridHeight, l_result, numPoints);
err = cudaThreadSynchronize();
printf("Run kernel: %s\n", cudaGetErrorString(err));
// Read the diagram from GPU into host memory
err = cudaMemcpy(result, l_result, size, cudaMemcpyDeviceToHost);
printf("Copy result from device: %s\n", cudaGetErrorString(err));
// Free device memory
cudaFree(l_result);
cudaFree(l_points);
}
/*
* Finds the Zone for each thread run. The coordinate generated is based
* on the (x,y) of the Block, and (x,y) for each thread.
*/
__device__ char getZone(Point *l_points, int x, int y, int numPoints) {
//Find the first point
double smallest = sqrt(
pow((double) l_points[0].x - x, 2)
+ pow((double) l_points[0].y - y, 2));
char zone = l_points[0].zone;
double dist_temp = 0;
//For each point
for (int i = 1; i < numPoints; i++) {
//Find distance to current point
dist_temp = sqrt(
pow((double) l_points[i].x - x, 2)
+ pow((double) l_points[i].y - y, 2));
//If Point distance is closer,
//Change the Zone value.
if (dist_temp < smallest) {
smallest = dist_temp;
zone = l_points[i].zone;
}
}
return zone;
}
/*
*Determines the coordinate of each point in the plane.
*Sets the result array equal to the appropriate Zone id.
*Runs in parallel.
*/
__global__ void createVoronoi(Point *l_points, int gridWidth, int gridHeight,
char *l_result, int numPoints) {
// X,Y Coordinate of the Block in the defined grid
int blockCol = blockIdx.x;
int blockrow = blockIdx.y;
//X,Y Coordinate of threads in each block
int row = threadIdx.y;
int col = threadIdx.x;
//Find the (x,y) point of the current value
int x = (blockCol * BLOCK_SIZE) + col;
int y = (blockrow * BLOCK_SIZE) + row;
__syncthreads();
//Set the result array to the proper zone
l_result[(y * (BLOCK_SIZE * gridWidth)) + x] = getZone(l_points, x, y, numPoints);
}
/*
* The main method of the program.
* The program takes the following parameters:
*
* int-height int-width int-x1 int-y1 char-y2 xn...
*
* Height and width define the result array
* properties, and (x1,y1) define a Euclidean
* point, and z1 defines a Zone, which in this
* case is a single char.
*
*/
int main(int argc, char* argv[]) {
//If less than 6, Not enough params to run
if (argc < 6) {
printf(
"Voronoi height, width, x1,y1,z1,x2,y2,z2 ...\nWhere height, width, x, and y are ints\nand z is a single char.");
return 1;
}
//If point params mod 3 does not equal 1
//There is an unfinished point
if ((argc - 3) % 3 != 0) {
printf(
"Voronoi height, width, x1,y1,z1,x2,y2,z2 ...\nWhere height, width, x, and y are ints\nand z is a single char.");
return 1;
}
//Read height/width of result
int height = atoi(argv[1]);
int width = atoi(argv[2]);
//The total number of points
int numPoints = (argc - 3) / 3;
//Create memory allocation for points
Point * points;
points = (Point*) malloc(numPoints * sizeof(Point));
//Read in the point values
int start = 3;
for (int i = 0; i < numPoints; i++) {
points[i].x = atoi(argv[start++]);
points[i].y = atoi(argv[start++]);
points[i].zone = argv[start++][0];
}
//Grid width - how long the cuda grid must be to obtain result
int gridWidth = (width / BLOCK_SIZE) + 1;
//Grid Width - how high the cuda grid must be to obtain result
int gridHeight = (height / BLOCK_SIZE) + 1;
//Allocate memory to hold result ( char array )
char *result;
result = (char*) malloc(
(gridWidth * gridHeight) * pow(BLOCK_SIZE, 2) * sizeof(char));
//Writes the array of zones to the result array
getVoronoiArray(result, gridHeight, gridWidth, points, numPoints);
//Shows success!
printf("Success\n\n");
//Some information for the user
printf("Height:%d, Width:%d\n\n", height, width);
//Prints the values. The lower left is the origin at (0,0).
int print_width = (BLOCK_SIZE * gridWidth) - width;
for (int i = height; i > 0; i--) {
for (int j = gridWidth * BLOCK_SIZE; j > print_width; j--)
printf("%c ", result[i * (gridWidth * BLOCK_SIZE) - j]);
printf("\n");
}
//Success
return 1;
} | //Required for printf()
#include <hip/hip_runtime.h>
#include <stdio.h>
//Required for pow(), sqrt()
#include <math.h>
//Represents a point on a
//Euclidean Grid
typedef struct {
int x;
int y;
char zone;
} Point;
// Thread block size
#define BLOCK_SIZE 16
//Prototype for the createVoronoi function.
__global__ void createVoronoi(Point *l_points, int gridWidth, int gridHeight,
char *l_result, int numPoints);
/*
* Copies the result array from the GPU after the zone points are calculated.
* Copies points to the GPU. The kernel finds the Zones in parallel.
*/
void getVoronoiArray(char *result, int gridHeight, int gridWidth, Point *points,
int numPoints) {
//Create pointer to char array to hold Zone results
//Allocate pointer in GPU shared memory
char *l_result;
size_t size = (gridWidth * gridHeight) * pow(BLOCK_SIZE, 2) * sizeof(char);
hipError_t err = hipMalloc(&l_result, size);
printf("CUDA malloc result array: %s\n", hipGetErrorString(err));
//Create Point pointer to pass points to GPU shared memory
Point *l_points;
err = hipMalloc((void**) &l_points, sizeof(Point) * numPoints);
printf("CUDA malloc Points: %s\n", hipGetErrorString(err));
err = hipMemcpy(l_points, points, sizeof(Point) * numPoints,
hipMemcpyHostToDevice);
printf("Copy Points to GPU: %s\n", hipGetErrorString(err));
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(gridWidth, gridHeight);
createVoronoi<<<dimGrid, dimBlock>>>(l_points, gridWidth, gridHeight, l_result, numPoints);
err = hipDeviceSynchronize();
printf("Run kernel: %s\n", hipGetErrorString(err));
// Read the diagram from GPU into host memory
err = hipMemcpy(result, l_result, size, hipMemcpyDeviceToHost);
printf("Copy result from device: %s\n", hipGetErrorString(err));
// Free device memory
hipFree(l_result);
hipFree(l_points);
}
/*
* Finds the Zone for each thread run. The coordinate generated is based
* on the (x,y) of the Block, and (x,y) for each thread.
*/
__device__ char getZone(Point *l_points, int x, int y, int numPoints) {
//Find the first point
double smallest = sqrt(
pow((double) l_points[0].x - x, 2)
+ pow((double) l_points[0].y - y, 2));
char zone = l_points[0].zone;
double dist_temp = 0;
//For each point
for (int i = 1; i < numPoints; i++) {
//Find distance to current point
dist_temp = sqrt(
pow((double) l_points[i].x - x, 2)
+ pow((double) l_points[i].y - y, 2));
//If Point distance is closer,
//Change the Zone value.
if (dist_temp < smallest) {
smallest = dist_temp;
zone = l_points[i].zone;
}
}
return zone;
}
/*
*Determines the coordinate of each point in the plane.
*Sets the result array equal to the appropriate Zone id.
*Runs in parallel.
*/
__global__ void createVoronoi(Point *l_points, int gridWidth, int gridHeight,
char *l_result, int numPoints) {
// X,Y Coordinate of the Block in the defined grid
int blockCol = blockIdx.x;
int blockrow = blockIdx.y;
//X,Y Coordinate of threads in each block
int row = threadIdx.y;
int col = threadIdx.x;
//Find the (x,y) point of the current value
int x = (blockCol * BLOCK_SIZE) + col;
int y = (blockrow * BLOCK_SIZE) + row;
__syncthreads();
//Set the result array to the proper zone
l_result[(y * (BLOCK_SIZE * gridWidth)) + x] = getZone(l_points, x, y, numPoints);
}
/*
* The main method of the program.
* The program takes the following parameters:
*
* int-height int-width int-x1 int-y1 char-y2 xn...
*
* Height and width define the result array
* properties, and (x1,y1) define a Euclidean
* point, and z1 defines a Zone, which in this
* case is a single char.
*
*/
int main(int argc, char* argv[]) {
//If less than 6, Not enough params to run
if (argc < 6) {
printf(
"Voronoi height, width, x1,y1,z1,x2,y2,z2 ...\nWhere height, width, x, and y are ints\nand z is a single char.");
return 1;
}
//If point params mod 3 does not equal 1
//There is an unfinished point
if ((argc - 3) % 3 != 0) {
printf(
"Voronoi height, width, x1,y1,z1,x2,y2,z2 ...\nWhere height, width, x, and y are ints\nand z is a single char.");
return 1;
}
//Read height/width of result
int height = atoi(argv[1]);
int width = atoi(argv[2]);
//The total number of points
int numPoints = (argc - 3) / 3;
//Create memory allocation for points
Point * points;
points = (Point*) malloc(numPoints * sizeof(Point));
//Read in the point values
int start = 3;
for (int i = 0; i < numPoints; i++) {
points[i].x = atoi(argv[start++]);
points[i].y = atoi(argv[start++]);
points[i].zone = argv[start++][0];
}
//Grid width - how long the cuda grid must be to obtain result
int gridWidth = (width / BLOCK_SIZE) + 1;
//Grid Width - how high the cuda grid must be to obtain result
int gridHeight = (height / BLOCK_SIZE) + 1;
//Allocate memory to hold result ( char array )
char *result;
result = (char*) malloc(
(gridWidth * gridHeight) * pow(BLOCK_SIZE, 2) * sizeof(char));
//Writes the array of zones to the result array
getVoronoiArray(result, gridHeight, gridWidth, points, numPoints);
//Shows success!
printf("Success\n\n");
//Some information for the user
printf("Height:%d, Width:%d\n\n", height, width);
//Prints the values. The lower left is the origin at (0,0).
int print_width = (BLOCK_SIZE * gridWidth) - width;
for (int i = height; i > 0; i--) {
for (int j = gridWidth * BLOCK_SIZE; j > print_width; j--)
printf("%c ", result[i * (gridWidth * BLOCK_SIZE) - j]);
printf("\n");
}
//Success
return 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //Required for printf()
#include <hip/hip_runtime.h>
#include <stdio.h>
//Required for pow(), sqrt()
#include <math.h>
//Represents a point on a
//Euclidean Grid
typedef struct {
int x;
int y;
char zone;
} Point;
// Thread block size
#define BLOCK_SIZE 16
//Prototype for the createVoronoi function.
__global__ void createVoronoi(Point *l_points, int gridWidth, int gridHeight,
char *l_result, int numPoints);
/*
* Copies the result array from the GPU after the zone points are calculated.
* Copies points to the GPU. The kernel finds the Zones in parallel.
*/
void getVoronoiArray(char *result, int gridHeight, int gridWidth, Point *points,
int numPoints) {
//Create pointer to char array to hold Zone results
//Allocate pointer in GPU shared memory
char *l_result;
size_t size = (gridWidth * gridHeight) * pow(BLOCK_SIZE, 2) * sizeof(char);
hipError_t err = hipMalloc(&l_result, size);
printf("CUDA malloc result array: %s\n", hipGetErrorString(err));
//Create Point pointer to pass points to GPU shared memory
Point *l_points;
err = hipMalloc((void**) &l_points, sizeof(Point) * numPoints);
printf("CUDA malloc Points: %s\n", hipGetErrorString(err));
err = hipMemcpy(l_points, points, sizeof(Point) * numPoints,
hipMemcpyHostToDevice);
printf("Copy Points to GPU: %s\n", hipGetErrorString(err));
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(gridWidth, gridHeight);
createVoronoi<<<dimGrid, dimBlock>>>(l_points, gridWidth, gridHeight, l_result, numPoints);
err = hipDeviceSynchronize();
printf("Run kernel: %s\n", hipGetErrorString(err));
// Read the diagram from GPU into host memory
err = hipMemcpy(result, l_result, size, hipMemcpyDeviceToHost);
printf("Copy result from device: %s\n", hipGetErrorString(err));
// Free device memory
hipFree(l_result);
hipFree(l_points);
}
/*
* Finds the Zone for each thread run. The coordinate generated is based
* on the (x,y) of the Block, and (x,y) for each thread.
*/
__device__ char getZone(Point *l_points, int x, int y, int numPoints) {
//Find the first point
double smallest = sqrt(
pow((double) l_points[0].x - x, 2)
+ pow((double) l_points[0].y - y, 2));
char zone = l_points[0].zone;
double dist_temp = 0;
//For each point
for (int i = 1; i < numPoints; i++) {
//Find distance to current point
dist_temp = sqrt(
pow((double) l_points[i].x - x, 2)
+ pow((double) l_points[i].y - y, 2));
//If Point distance is closer,
//Change the Zone value.
if (dist_temp < smallest) {
smallest = dist_temp;
zone = l_points[i].zone;
}
}
return zone;
}
/*
*Determines the coordinate of each point in the plane.
*Sets the result array equal to the appropriate Zone id.
*Runs in parallel.
*/
__global__ void createVoronoi(Point *l_points, int gridWidth, int gridHeight,
char *l_result, int numPoints) {
// X,Y Coordinate of the Block in the defined grid
int blockCol = blockIdx.x;
int blockrow = blockIdx.y;
//X,Y Coordinate of threads in each block
int row = threadIdx.y;
int col = threadIdx.x;
//Find the (x,y) point of the current value
int x = (blockCol * BLOCK_SIZE) + col;
int y = (blockrow * BLOCK_SIZE) + row;
__syncthreads();
//Set the result array to the proper zone
l_result[(y * (BLOCK_SIZE * gridWidth)) + x] = getZone(l_points, x, y, numPoints);
}
/*
* The main method of the program.
* The program takes the following parameters:
*
* int-height int-width int-x1 int-y1 char-y2 xn...
*
* Height and width define the result array
* properties, and (x1,y1) define a Euclidean
* point, and z1 defines a Zone, which in this
* case is a single char.
*
*/
int main(int argc, char* argv[]) {
//If less than 6, Not enough params to run
if (argc < 6) {
printf(
"Voronoi height, width, x1,y1,z1,x2,y2,z2 ...\nWhere height, width, x, and y are ints\nand z is a single char.");
return 1;
}
//If point params mod 3 does not equal 1
//There is an unfinished point
if ((argc - 3) % 3 != 0) {
printf(
"Voronoi height, width, x1,y1,z1,x2,y2,z2 ...\nWhere height, width, x, and y are ints\nand z is a single char.");
return 1;
}
//Read height/width of result
int height = atoi(argv[1]);
int width = atoi(argv[2]);
//The total number of points
int numPoints = (argc - 3) / 3;
//Create memory allocation for points
Point * points;
points = (Point*) malloc(numPoints * sizeof(Point));
//Read in the point values
int start = 3;
for (int i = 0; i < numPoints; i++) {
points[i].x = atoi(argv[start++]);
points[i].y = atoi(argv[start++]);
points[i].zone = argv[start++][0];
}
//Grid width - how long the cuda grid must be to obtain result
int gridWidth = (width / BLOCK_SIZE) + 1;
//Grid Width - how high the cuda grid must be to obtain result
int gridHeight = (height / BLOCK_SIZE) + 1;
//Allocate memory to hold result ( char array )
char *result;
result = (char*) malloc(
(gridWidth * gridHeight) * pow(BLOCK_SIZE, 2) * sizeof(char));
//Writes the array of zones to the result array
getVoronoiArray(result, gridHeight, gridWidth, points, numPoints);
//Shows success!
printf("Success\n\n");
//Some information for the user
printf("Height:%d, Width:%d\n\n", height, width);
//Prints the values. The lower left is the origin at (0,0).
int print_width = (BLOCK_SIZE * gridWidth) - width;
for (int i = height; i > 0; i--) {
for (int j = gridWidth * BLOCK_SIZE; j > print_width; j--)
printf("%c ", result[i * (gridWidth * BLOCK_SIZE) - j]);
printf("\n");
}
//Success
return 1;
} | .text
.file "voronoi.hip"
.globl _Z15getVoronoiArrayPciiP5Pointi # -- Begin function _Z15getVoronoiArrayPciiP5Pointi
.p2align 4, 0x90
.type _Z15getVoronoiArrayPciiP5Pointi,@function
_Z15getVoronoiArrayPciiP5Pointi: # @_Z15getVoronoiArrayPciiP5Pointi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
movq %rcx, %r13
movl %edx, %r15d
movl %esi, %r12d
movq %rdi, 40(%rsp) # 8-byte Spill
movl %edx, %eax
imull %esi, %eax
movslq %eax, %r14
shlq $8, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movslq %ebp, %rax
shlq $2, %rax
leaq (%rax,%rax,2), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl %r15d, %eax
movq %r12, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movl %r15d, 36(%rsp)
movl %r12d, 32(%rsp)
movq %rcx, 96(%rsp)
movl %ebp, 28(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13createVoronoiP5PointiiPci, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
callq hipDeviceSynchronize
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rsi
movq 40(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z15getVoronoiArrayPciiP5Pointi, .Lfunc_end0-_Z15getVoronoiArrayPciiP5Pointi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__createVoronoiP5PointiiPci # -- Begin function _Z28__device_stub__createVoronoiP5PointiiPci
.p2align 4, 0x90
.type _Z28__device_stub__createVoronoiP5PointiiPci,@function
_Z28__device_stub__createVoronoiP5PointiiPci: # @_Z28__device_stub__createVoronoiP5PointiiPci
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13createVoronoiP5PointiiPci, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__createVoronoiP5PointiiPci, .Lfunc_end1-_Z28__device_stub__createVoronoiP5PointiiPci
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $6, %edi
jl .LBB2_10
# %bb.1:
movl %edi, %ebp
addl $-3, %ebp
imull $-1431655765, %ebp, %eax # imm = 0xAAAAAAAB
cmpl $1431655765, %eax # imm = 0x55555555
jbe .LBB2_2
.LBB2_10: # %.loopexit.sink.split
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
.LBB2_11: # %.loopexit
movl $1, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 80
movq %rsi, %r12
movl $2863311531, %ebx # imm = 0xAAAAAAAB
imulq %rbp, %rbx
shrq $33, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, (%rsp) # 8-byte Spill
movq 16(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 8(%rsp) # 8-byte Spill
movq %rbx, 16(%rsp) # 8-byte Spill
movl %ebx, %ebx
leaq (,%rbx,4), %rax
leaq (%rax,%rax,2), %rdi
callq malloc
movq %rax, %r13
cmpl $3, %ebp
jb .LBB2_5
# %bb.3: # %.lr.ph.preheader
shlq $2, %rbx
leaq (%rbx,%rbx,2), %r14
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 24(%r12,%rbp,2), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, (%r13,%rbp)
movq 32(%r12,%rbp,2), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, 4(%r13,%rbp)
movq 40(%r12,%rbp,2), %rax
movzbl (%rax), %eax
movb %al, 8(%r13,%rbp)
addq $12, %rbp
cmpq %rbp, %r14
jne .LBB2_4
.LBB2_5: # %._crit_edge
movq 8(%rsp), %r12 # 8-byte Reload
leal 15(%r12), %ebp
testl %r12d, %r12d
cmovnsl %r12d, %ebp
sarl $4, %ebp
incl %ebp
movq (%rsp), %r15 # 8-byte Reload
leal 15(%r15), %r14d
testl %r15d, %r15d
cmovnsl %r15d, %r14d
sarl $4, %r14d
incl %r14d
movl %ebp, %eax
imull %r14d, %eax
movslq %eax, %rdi
shlq $8, %rdi
callq malloc
movq %rax, %rbx
movq %rax, %rdi
movl %r14d, %esi
movl %ebp, %edx
movq %r13, %rcx
movq 16(%rsp), %r8 # 8-byte Reload
# kill: def $r8d killed $r8d killed $r8
callq _Z15getVoronoiArrayPciiP5Pointi
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.7, %edi
movl %r15d, %esi
movl %r12d, %edx
movq %r15, %r14
xorl %eax, %eax
callq printf
testl %r14d, %r14d
jle .LBB2_11
# %bb.6: # %.preheader.lr.ph
shll $4, %ebp
movslq %ebp, %rcx
subl 8(%rsp), %ebp # 4-byte Folded Reload
movslq %ebp, %r15
movl %r14d, %r13d
leaq -1(%r13), %rax
imulq %rcx, %rax
addq %rax, %rbx
movq %rcx, (%rsp) # 8-byte Spill
movq %rcx, %rbp
negq %rbp
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_8: # %._crit_edge55
# in Loop: Header=BB2_7 Depth=1
movl $10, %edi
callq putchar@PLT
leaq -1(%r13), %rax
addq %rbp, %rbx
cmpq $1, %r13
movq %rax, %r13
jle .LBB2_11
.LBB2_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_9 Depth 2
movq %rbx, %r12
movq (%rsp), %r14 # 8-byte Reload
cmpl $0, 8(%rsp) # 4-byte Folded Reload
jle .LBB2_8
.p2align 4, 0x90
.LBB2_9: # Parent Loop BB2_7 Depth=1
# => This Inner Loop Header: Depth=2
movsbl (%r12), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
decq %r14
incq %r12
cmpq %r15, %r14
jg .LBB2_9
jmp .LBB2_8
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13createVoronoiP5PointiiPci, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA malloc result array: %s\n"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA malloc Points: %s\n"
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Copy Points to GPU: %s\n"
.size .L.str.2, 24
.type _Z13createVoronoiP5PointiiPci,@object # @_Z13createVoronoiP5PointiiPci
.section .rodata,"a",@progbits
.globl _Z13createVoronoiP5PointiiPci
.p2align 3, 0x0
_Z13createVoronoiP5PointiiPci:
.quad _Z28__device_stub__createVoronoiP5PointiiPci
.size _Z13createVoronoiP5PointiiPci, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Run kernel: %s\n"
.size .L.str.3, 16
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Copy result from device: %s\n"
.size .L.str.4, 29
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Voronoi height, width, x1,y1,z1,x2,y2,z2 ...\nWhere height, width, x, and y are ints\nand z is a single char."
.size .L.str.5, 108
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Height:%d, Width:%d\n\n"
.size .L.str.7, 22
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%c "
.size .L.str.8, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13createVoronoiP5PointiiPci"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Success\n"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__createVoronoiP5PointiiPci
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13createVoronoiP5PointiiPci
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00183eaa_00000000-6_voronoi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7getZoneP5Pointiii
.type _Z7getZoneP5Pointiii, @function
_Z7getZoneP5Pointiii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z7getZoneP5Pointiii, .-_Z7getZoneP5Pointiii
.globl _Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci
.type _Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci, @function
_Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13createVoronoiP5PointiiPci(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci, .-_Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci
.globl _Z13createVoronoiP5PointiiPci
.type _Z13createVoronoiP5PointiiPci, @function
_Z13createVoronoiP5PointiiPci:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13createVoronoiP5PointiiPci, .-_Z13createVoronoiP5PointiiPci
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "CUDA malloc result array: %s\n"
.LC3:
.string "CUDA malloc Points: %s\n"
.LC4:
.string "Copy Points to GPU: %s\n"
.LC5:
.string "Run kernel: %s\n"
.LC6:
.string "Copy result from device: %s\n"
.text
.globl _Z15getVoronoiArrayPciiP5Pointi
.type _Z15getVoronoiArrayPciiP5Pointi, @function
_Z15getVoronoiArrayPciiP5Pointi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, %ebp
movl %edx, %ebx
movq %rcx, %r15
movl %r8d, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %edx, %eax
imull %esi, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC0(%rip), %xmm0
comisd .LC1(%rip), %xmm0
jnb .L14
cvttsd2siq %xmm0, %r14
.L15:
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r13d, %rax
leaq (%rax,%rax,2), %r12
salq $2, %r12
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, 32(%rsp)
movl $16, 36(%rsp)
movl %ebx, 44(%rsp)
movl %ebp, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
call cudaThreadSynchronize@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r14, %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
subsd .LC1(%rip), %xmm0
cvttsd2siq %xmm0, %r14
btcq $63, %r14
jmp .L15
.L19:
movl %r13d, %r8d
movq 16(%rsp), %rcx
movl %ebp, %edx
movl %ebx, %esi
movq 24(%rsp), %rdi
call _Z43__device_stub__Z13createVoronoiP5PointiiPciP5PointiiPci
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z15getVoronoiArrayPciiP5Pointi, .-_Z15getVoronoiArrayPciiP5Pointi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Voronoi height, width, x1,y1,z1,x2,y2,z2 ...\nWhere height, width, x, and y are ints\nand z is a single char."
.section .rodata.str1.1
.LC8:
.string "Success\n\n"
.LC9:
.string "Height:%d, Width:%d\n\n"
.LC10:
.string "%c "
.LC11:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
cmpl $5, %edi
jle .L35
movq %rsi, %rbx
leal -3(%rdi), %ebp
movslq %ebp, %rax
imulq $1431655766, %rax, %rax
shrq $32, %rax
movl %ebp, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,2), %eax
cmpl %eax, %ebp
jne .L36
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, %r14d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 16(%rsp)
movl %eax, 4(%rsp)
movl $3, %ecx
movl %ebp, %eax
cltd
idivl %ecx
movl %eax, %ebp
movslq %eax, %r15
imulq $12, %r15, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
addq $24, %rbx
movq %rax, %r12
imulq $24, %r15, %r15
addq %rbx, %r15
.L25:
movq (%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, (%r12)
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 4(%r12)
movq 16(%rbx), %rax
movzbl (%rax), %eax
movb %al, 8(%r12)
addq $24, %rbx
addq $12, %r12
cmpq %r15, %rbx
jne .L25
movl $16, %ecx
movl 4(%rsp), %eax
cltd
idivl %ecx
movl %eax, %ebx
leal 1(%rax), %esi
movl %esi, (%rsp)
movl %r14d, %eax
cltd
idivl %ecx
leal 1(%rax), %r12d
movl %esi, %eax
imull %r12d, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC0(%rip), %xmm0
comisd .LC1(%rip), %xmm0
jnb .L26
cvttsd2siq %xmm0, %rdi
.L27:
call malloc@PLT
movq %rax, 24(%rsp)
movl %ebp, %r8d
movq 8(%rsp), %rcx
movl (%rsp), %r15d
movl %r15d, %edx
movl %r12d, %esi
movq %rax, %rbp
movq %rax, %rdi
call _Z15getVoronoiArrayPciiP5Pointi
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %ecx
movl %r14d, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %eax
sall $4, %eax
movl %eax, %ecx
movl 16(%rsp), %edi
subl %edi, %ecx
testl %r13d, %r13d
jle .L23
imull $-16, %r15d, %edi
movl %edi, 4(%rsp)
imull %r15d, %r13d
movl %r13d, %r15d
sall $4, %r15d
leal 1(%rbx), %edx
sall $4, %edx
movslq %edx, %rsi
movq %rsi, 32(%rsp)
movslq %ebx, %rbx
salq $4, %rbx
subl $1, %edx
subl %ecx, %edx
subq %rbx, %rdx
leaq -15(%rbp,%rdx), %rsi
movq %rsi, 40(%rsp)
movl %eax, 8(%rsp)
movl %ecx, 16(%rsp)
jmp .L28
.L35:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L23
.L36:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L23:
movl $1, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
subsd .LC1(%rip), %xmm0
cvttsd2siq %xmm0, %rdi
btcq $63, %rdi
jmp .L27
.L30:
movslq %r15d, %rbx
movq 32(%rsp), %rax
subq %rax, %rbx
movq 24(%rsp), %rax
addq %rax, %rbx
movslq %r13d, %rbp
salq $4, %rbp
movq 40(%rsp), %rax
addq %rax, %rbp
leaq .LC10(%rip), %r12
.L29:
movsbl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L29
.L31:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %eax
addl %eax, %r15d
movl (%rsp), %eax
subl %eax, %r13d
subl $1, %r14d
je .L23
.L28:
movl 16(%rsp), %ecx
cmpl %ecx, 8(%rsp)
jg .L30
jmp .L31
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z13createVoronoiP5PointiiPci"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z13createVoronoiP5PointiiPci(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1081081856
.align 8
.LC1:
.long 0
.long 1138753536
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "voronoi.hip"
.globl _Z15getVoronoiArrayPciiP5Pointi # -- Begin function _Z15getVoronoiArrayPciiP5Pointi
.p2align 4, 0x90
.type _Z15getVoronoiArrayPciiP5Pointi,@function
_Z15getVoronoiArrayPciiP5Pointi: # @_Z15getVoronoiArrayPciiP5Pointi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
movq %rcx, %r13
movl %edx, %r15d
movl %esi, %r12d
movq %rdi, 40(%rsp) # 8-byte Spill
movl %edx, %eax
imull %esi, %eax
movslq %eax, %r14
shlq $8, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movslq %ebp, %rax
shlq $2, %rax
leaq (%rax,%rax,2), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl %r15d, %eax
movq %r12, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movl %r15d, 36(%rsp)
movl %r12d, 32(%rsp)
movq %rcx, 96(%rsp)
movl %ebp, 28(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13createVoronoiP5PointiiPci, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
callq hipDeviceSynchronize
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rsi
movq 40(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z15getVoronoiArrayPciiP5Pointi, .Lfunc_end0-_Z15getVoronoiArrayPciiP5Pointi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__createVoronoiP5PointiiPci # -- Begin function _Z28__device_stub__createVoronoiP5PointiiPci
.p2align 4, 0x90
.type _Z28__device_stub__createVoronoiP5PointiiPci,@function
_Z28__device_stub__createVoronoiP5PointiiPci: # @_Z28__device_stub__createVoronoiP5PointiiPci
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13createVoronoiP5PointiiPci, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__createVoronoiP5PointiiPci, .Lfunc_end1-_Z28__device_stub__createVoronoiP5PointiiPci
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $6, %edi
jl .LBB2_10
# %bb.1:
movl %edi, %ebp
addl $-3, %ebp
imull $-1431655765, %ebp, %eax # imm = 0xAAAAAAAB
cmpl $1431655765, %eax # imm = 0x55555555
jbe .LBB2_2
.LBB2_10: # %.loopexit.sink.split
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
.LBB2_11: # %.loopexit
movl $1, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 80
movq %rsi, %r12
movl $2863311531, %ebx # imm = 0xAAAAAAAB
imulq %rbp, %rbx
shrq $33, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, (%rsp) # 8-byte Spill
movq 16(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 8(%rsp) # 8-byte Spill
movq %rbx, 16(%rsp) # 8-byte Spill
movl %ebx, %ebx
leaq (,%rbx,4), %rax
leaq (%rax,%rax,2), %rdi
callq malloc
movq %rax, %r13
cmpl $3, %ebp
jb .LBB2_5
# %bb.3: # %.lr.ph.preheader
shlq $2, %rbx
leaq (%rbx,%rbx,2), %r14
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 24(%r12,%rbp,2), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, (%r13,%rbp)
movq 32(%r12,%rbp,2), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, 4(%r13,%rbp)
movq 40(%r12,%rbp,2), %rax
movzbl (%rax), %eax
movb %al, 8(%r13,%rbp)
addq $12, %rbp
cmpq %rbp, %r14
jne .LBB2_4
.LBB2_5: # %._crit_edge
movq 8(%rsp), %r12 # 8-byte Reload
leal 15(%r12), %ebp
testl %r12d, %r12d
cmovnsl %r12d, %ebp
sarl $4, %ebp
incl %ebp
movq (%rsp), %r15 # 8-byte Reload
leal 15(%r15), %r14d
testl %r15d, %r15d
cmovnsl %r15d, %r14d
sarl $4, %r14d
incl %r14d
movl %ebp, %eax
imull %r14d, %eax
movslq %eax, %rdi
shlq $8, %rdi
callq malloc
movq %rax, %rbx
movq %rax, %rdi
movl %r14d, %esi
movl %ebp, %edx
movq %r13, %rcx
movq 16(%rsp), %r8 # 8-byte Reload
# kill: def $r8d killed $r8d killed $r8
callq _Z15getVoronoiArrayPciiP5Pointi
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.7, %edi
movl %r15d, %esi
movl %r12d, %edx
movq %r15, %r14
xorl %eax, %eax
callq printf
testl %r14d, %r14d
jle .LBB2_11
# %bb.6: # %.preheader.lr.ph
shll $4, %ebp
movslq %ebp, %rcx
subl 8(%rsp), %ebp # 4-byte Folded Reload
movslq %ebp, %r15
movl %r14d, %r13d
leaq -1(%r13), %rax
imulq %rcx, %rax
addq %rax, %rbx
movq %rcx, (%rsp) # 8-byte Spill
movq %rcx, %rbp
negq %rbp
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_8: # %._crit_edge55
# in Loop: Header=BB2_7 Depth=1
movl $10, %edi
callq putchar@PLT
leaq -1(%r13), %rax
addq %rbp, %rbx
cmpq $1, %r13
movq %rax, %r13
jle .LBB2_11
.LBB2_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_9 Depth 2
movq %rbx, %r12
movq (%rsp), %r14 # 8-byte Reload
cmpl $0, 8(%rsp) # 4-byte Folded Reload
jle .LBB2_8
.p2align 4, 0x90
.LBB2_9: # Parent Loop BB2_7 Depth=1
# => This Inner Loop Header: Depth=2
movsbl (%r12), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
decq %r14
incq %r12
cmpq %r15, %r14
jg .LBB2_9
jmp .LBB2_8
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13createVoronoiP5PointiiPci, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA malloc result array: %s\n"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA malloc Points: %s\n"
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Copy Points to GPU: %s\n"
.size .L.str.2, 24
.type _Z13createVoronoiP5PointiiPci,@object # @_Z13createVoronoiP5PointiiPci
.section .rodata,"a",@progbits
.globl _Z13createVoronoiP5PointiiPci
.p2align 3, 0x0
_Z13createVoronoiP5PointiiPci:
.quad _Z28__device_stub__createVoronoiP5PointiiPci
.size _Z13createVoronoiP5PointiiPci, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Run kernel: %s\n"
.size .L.str.3, 16
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Copy result from device: %s\n"
.size .L.str.4, 29
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Voronoi height, width, x1,y1,z1,x2,y2,z2 ...\nWhere height, width, x, and y are ints\nand z is a single char."
.size .L.str.5, 108
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Height:%d, Width:%d\n\n"
.size .L.str.7, 22
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%c "
.size .L.str.8, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13createVoronoiP5PointiiPci"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Success\n"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__createVoronoiP5PointiiPci
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13createVoronoiP5PointiiPci
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
#define THREADS_PER_BLOCK 256
#define BLOCKS 128
#define N (1 << 16)
using namespace std;
__global__ void add_array(float A[], float blocks[])
{
__shared__ int array_per_block[THREADS_PER_BLOCK];
int global_thread_ID = blockIdx.x * THREADS_PER_BLOCK + threadIdx.x, step = gridDim.x * THREADS_PER_BLOCK, my_sum = 0, num_threads = THREADS_PER_BLOCK;
for(int i = global_thread_ID; i < N; i += step)
my_sum += A[i];
array_per_block[threadIdx.x] = my_sum;
__syncthreads();
while(threadIdx.x < num_threads && num_threads > 1)
{
if(threadIdx.x < num_threads / 2)
array_per_block[threadIdx.x] += array_per_block[threadIdx.x + num_threads / 2];
num_threads = num_threads >> 1;
__syncthreads();
}
if(threadIdx.x == 0)
blocks[blockIdx.x] = array_per_block[0];
}
void init_array(float A[])
{
for(int i = 0; i < N; i++)
A[i] = 1;
}
int main()
{
float *host_A = new float[N], *host_blocks = new float[BLOCKS], *cuda_A, *cuda_blocks, final_sum = 0;
init_array(host_A);
cudaMalloc(&cuda_A, sizeof(float) * N);
cudaMemcpy(cuda_A, host_A, sizeof(float) * N, cudaMemcpyHostToDevice);
cudaMalloc(&cuda_blocks, sizeof(float) * BLOCKS);
add_array<<<BLOCKS, THREADS_PER_BLOCK>>>(cuda_A, cuda_blocks);
cudaMemcpy(host_blocks, cuda_blocks, sizeof(float) * BLOCKS, cudaMemcpyDeviceToHost);
for(int i = 0; i < BLOCKS; i++)
final_sum += host_blocks[i];
cout << "Final Sum : " << final_sum << endl;
free(host_A); free(host_blocks);
cudaFree(cuda_A); cudaFree(cuda_blocks);
return 0;
} | code for sm_80
Function : _Z9add_arrayPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B2, 0xeb0 ; /* 0x00000e7000027945 */
/* 0x000fe20003800000 */
/*0040*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0060*/ LEA R4, R0, R9, 0x8 ; /* 0x0000000900047211 */
/* 0x001fc800078e40ff */
/*0070*/ ISETP.GT.AND P0, PT, R4, 0xffff, PT ; /* 0x0000ffff0400780c */
/* 0x000fda0003f04270 */
/*0080*/ @P0 BRA 0xea0 ; /* 0x00000e1000000947 */
/* 0x000fea0003800000 */
/*0090*/ MOV R11, c[0x0][0xc] ; /* 0x00000300000b7a02 */
/* 0x000fe20000000f00 */
/*00a0*/ BSSY B1, 0xde0 ; /* 0x00000d3000017945 */
/* 0x000fe20003800000 */
/*00b0*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fe40000000f00 */
/*00c0*/ SHF.L.U32 R11, R11, 0x8, RZ ; /* 0x000000080b0b7819 */
/* 0x000fe400000006ff */
/*00d0*/ IADD3 R5, -R9, 0xffff, RZ ; /* 0x0000ffff09057810 */
/* 0x000fe40007ffe1ff */
/*00e0*/ I2F.U32.RP R6, R11 ; /* 0x0000000b00067306 */
/* 0x000e220000209000 */
/*00f0*/ IADD3 R7, RZ, -R11, RZ ; /* 0x8000000bff077210 */
/* 0x000fe40007ffe0ff */
/*0100*/ ISETP.NE.U32.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fc40003f45070 */
/*0110*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fc60000000f00 */
/*0120*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0130*/ IADD3 R3, R6, 0xffffffe, RZ ; /* 0x0ffffffe06037810 */
/* 0x001fcc0007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*0150*/ IMAD R7, R7, R3, RZ ; /* 0x0000000307077224 */
/* 0x001fc800078e02ff */
/*0160*/ IMAD.HI.U32 R7, R3, R7, R2 ; /* 0x0000000703077227 */
/* 0x000fc800078e0002 */
/*0170*/ IMAD R2, R0, -0x100, R5 ; /* 0xffffff0000027824 */
/* 0x000fc800078e0205 */
/*0180*/ IMAD.HI.U32 R7, R7, R2, RZ ; /* 0x0000000207077227 */
/* 0x000fca00078e00ff */
/*0190*/ IADD3 R5, -R7, RZ, RZ ; /* 0x000000ff07057210 */
/* 0x000fca0007ffe1ff */
/*01a0*/ IMAD R2, R11, R5, R2 ; /* 0x000000050b027224 */
/* 0x000fca00078e0202 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R2, R11, PT ; /* 0x0000000b0200720c */
/* 0x000fda0003f06070 */
/*01c0*/ @P0 IADD3 R2, -R11, R2, RZ ; /* 0x000000020b020210 */
/* 0x000fe40007ffe1ff */
/*01d0*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R2, R11, PT ; /* 0x0000000b0200720c */
/* 0x000fda0003f26070 */
/*01f0*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fe40007ffe0ff */
/*0200*/ @!P2 LOP3.LUT R7, RZ, R11, RZ, 0x33, !PT ; /* 0x0000000bff07a212 */
/* 0x000fc800078e33ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R7.reuse, 0x3, PT ; /* 0x000000030700780c */
/* 0x040fe40003f06070 */
/*0220*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*0230*/ LOP3.LUT R10, R7, 0x3, RZ, 0xc0, !PT ; /* 0x00000003070a7812 */
/* 0x000fce00078ec0ff */
/*0240*/ @!P0 BRA 0xdd0 ; /* 0x00000b8000008947 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.IADD R8, R7, 0x1, -R10 ; /* 0x0000000107087824 */
/* 0x000fe200078e0a0a */
/*0260*/ BSSY B0, 0xc30 ; /* 0x000009c000007945 */
/* 0x000fe20003800000 */
/*0270*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fc600000001ff */
/*0280*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f04270 */
/*0290*/ @!P0 BRA 0xc20 ; /* 0x0000098000008947 */
/* 0x000fea0003800000 */
/*02a0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*02b0*/ BSSY B3, 0x8c0 ; /* 0x0000060000037945 */
/* 0x000fe20003800000 */
/*02c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*02d0*/ @!P1 BRA 0x8b0 ; /* 0x000005d000009947 */
/* 0x000fea0003800000 */
/*02e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02f0*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x000fd400000001ff */
/*0300*/ IMAD.WIDE R6, R4, R17, c[0x0][0x160] ; /* 0x0000580004067625 */
/* 0x000fca00078e0211 */
/*0310*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0010a2000c1e1900 */
/*0320*/ IMAD.WIDE R20, R11, 0x4, R6 ; /* 0x000000040b147825 */
/* 0x000fca00078e0206 */
/*0330*/ LDG.E R23, [R20.64] ; /* 0x0000000414177981 */
/* 0x0022e2000c1e1900 */
/*0340*/ IMAD.WIDE R26, R11, 0x4, R20 ; /* 0x000000040b1a7825 */
/* 0x000fca00078e0214 */
/*0350*/ LDG.E R22, [R26.64] ; /* 0x000000041a167981 */
/* 0x000962000c1e1900 */
/*0360*/ IMAD.WIDE R18, R11, 0x4, R26 ; /* 0x000000040b127825 */
/* 0x000fcc00078e021a */
/*0370*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000e2000c1e1900 */
/*0380*/ IADD3 R4, R11, R4, R11 ; /* 0x000000040b047210 */
/* 0x000fc80007ffe00b */
/*0390*/ IADD3 R16, R11, R4, R11 ; /* 0x000000040b107210 */
/* 0x000fca0007ffe00b */
/*03a0*/ IMAD.WIDE R28, R16, R17, c[0x0][0x160] ; /* 0x00005800101c7625 */
/* 0x000fca00078e0211 */
/*03b0*/ LDG.E R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x0000e4000c1e1900 */
/*03c0*/ IMAD.WIDE R28, R11, 0x4, R28 ; /* 0x000000040b1c7825 */
/* 0x001fca00078e021c */
/*03d0*/ LDG.E R13, [R28.64] ; /* 0x000000041c0d7981 */
/* 0x000f62000c1e1900 */
/*03e0*/ IMAD.WIDE R4, R11, 0x4, R28 ; /* 0x000000040b047825 */
/* 0x000fca00078e021c */
/*03f0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000162000c1e1900 */
/*0400*/ IMAD.WIDE R20, R11, 0x4, R4 ; /* 0x000000040b147825 */
/* 0x002fca00078e0204 */
/*0410*/ LDG.E R15, [R20.64] ; /* 0x00000004140f7981 */
/* 0x000362000c1e1900 */
/*0420*/ I2F R3, R24 ; /* 0x0000001800037306 */
/* 0x000ea20000201400 */
/*0430*/ IADD3 R26, R11, R16, R11 ; /* 0x000000100b1a7210 */
/* 0x010fc80007ffe00b */
/*0440*/ IADD3 R26, R11, R26, R11 ; /* 0x0000001a0b1a7210 */
/* 0x000fca0007ffe00b */
/*0450*/ IMAD.WIDE R6, R26, R17, c[0x0][0x160] ; /* 0x000058001a067625 */
/* 0x000fca00078e0211 */
/*0460*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000922000c1e1900 */
/*0470*/ FADD R25, R3, R2 ; /* 0x0000000203197221 */
/* 0x004fe40000000000 */
/*0480*/ IMAD.WIDE R2, R11, 0x4, R6 ; /* 0x000000040b027825 */
/* 0x000fc800078e0206 */
/*0490*/ F2I.TRUNC.NTZ R25, R25 ; /* 0x0000001900197305 */
/* 0x000e22000020f100 */
/*04a0*/ LDG.E R19, [R2.64] ; /* 0x0000000402137981 */
/* 0x0006ae000c1e1900 */
/*04b0*/ I2F R4, R25 ; /* 0x0000001900047306 */
/* 0x001ee40000201400 */
/*04c0*/ FADD R23, R4, R23 ; /* 0x0000001704177221 */
/* 0x008fcc0000000000 */
/*04d0*/ F2I.TRUNC.NTZ R23, R23 ; /* 0x0000001700177305 */
/* 0x000e22000020f100 */
/*04e0*/ IMAD.WIDE R4, R11, 0x4, R2 ; /* 0x000000040b047825 */
/* 0x000fca00078e0202 */
/*04f0*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x0022e4000c1e1900 */
/*0500*/ I2F R21, R23 ; /* 0x0000001700157306 */
/* 0x001f640000201400 */
/*0510*/ FADD R22, R21, R22 ; /* 0x0000001615167221 */
/* 0x020fcc0000000000 */
/*0520*/ F2I.TRUNC.NTZ R22, R22 ; /* 0x0000001600167305 */
/* 0x000e22000020f100 */
/*0530*/ IMAD.WIDE R6, R11, 0x4, R4 ; /* 0x000000040b067825 */
/* 0x010fca00078e0204 */
/*0540*/ LDG.E R21, [R6.64] ; /* 0x0000000406157981 */
/* 0x000964000c1e1900 */
/*0550*/ I2F R27, R22 ; /* 0x00000016001b7306 */
/* 0x001e240000201400 */
/*0560*/ FADD R27, R27, R18 ; /* 0x000000121b1b7221 */
/* 0x001fcc0000000000 */
/*0570*/ F2I.TRUNC.NTZ R27, R27 ; /* 0x0000001b001b7305 */
/* 0x000e62000020f100 */
/*0580*/ IADD3 R18, R11, R26, R11 ; /* 0x0000001a0b127210 */
/* 0x000fc80007ffe00b */
/*0590*/ IADD3 R18, R11, R18, R11 ; /* 0x000000120b127210 */
/* 0x000fc60007ffe00b */
/*05a0*/ I2F R5, R27 ; /* 0x0000001b00057306 */
/* 0x002e240000201400 */
/*05b0*/ IMAD.WIDE R2, R18, R17, c[0x0][0x160] ; /* 0x0000580012027625 */
/* 0x000fca00078e0211 */
/*05c0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000362000c1e1900 */
/*05d0*/ FADD R23, R5, R14 ; /* 0x0000000e05177221 */
/* 0x001fcc0000000000 */
/*05e0*/ F2I.TRUNC.NTZ R23, R23 ; /* 0x0000001700177305 */
/* 0x000f22000020f100 */
/*05f0*/ IMAD.WIDE R4, R11, 0x4, R2 ; /* 0x000000040b047825 */
/* 0x000fca00078e0202 */
/*0600*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000164000c1e1900 */
/*0610*/ I2F R6, R23 ; /* 0x0000001700067306 */
/* 0x010f240000201400 */
/*0620*/ FADD R22, R6, R13 ; /* 0x0000000d06167221 */
/* 0x010fcc0000000000 */
/*0630*/ F2I.TRUNC.NTZ R22, R22 ; /* 0x0000001600167305 */
/* 0x000f22000020f100 */
/*0640*/ IMAD.WIDE R6, R11, 0x4, R4 ; /* 0x000000040b067825 */
/* 0x000fca00078e0204 */
/*0650*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000164000c1e1900 */
/*0660*/ I2F R25, R22 ; /* 0x0000001600197306 */
/* 0x010f240000201400 */
/*0670*/ FADD R12, R25, R12 ; /* 0x0000000c190c7221 */
/* 0x010fcc0000000000 */
/*0680*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000f22000020f100 */
/*0690*/ IMAD.WIDE R2, R11, 0x4, R6 ; /* 0x000000040b027825 */
/* 0x002fcc00078e0206 */
/*06a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000362000c1e1900 */
/*06b0*/ I2F R24, R12 ; /* 0x0000000c00187306 */
/* 0x010f240000201400 */
/*06c0*/ FADD R15, R24, R15 ; /* 0x0000000f180f7221 */
/* 0x010fcc0000000000 */
/*06d0*/ F2I.TRUNC.NTZ R15, R15 ; /* 0x0000000f000f7305 */
/* 0x000e30000020f100 */
/*06e0*/ I2F R5, R15 ; /* 0x0000000f00057306 */
/* 0x001e240000201400 */
/*06f0*/ FADD R5, R5, R16 ; /* 0x0000001005057221 */
/* 0x001fcc0000000000 */
/*0700*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e30000020f100 */
/*0710*/ I2F R4, R5 ; /* 0x0000000500047306 */
/* 0x001ea40000201400 */
/*0720*/ FADD R4, R4, R19 ; /* 0x0000001304047221 */
/* 0x004fcc0000000000 */
/*0730*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e30000020f100 */
/*0740*/ I2F R7, R4 ; /* 0x0000000400077306 */
/* 0x001ee40000201400 */
/*0750*/ FADD R7, R7, R20 ; /* 0x0000001407077221 */
/* 0x008fcc0000000000 */
/*0760*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*0770*/ I2F R6, R7 ; /* 0x0000000700067306 */
/* 0x001f640000201400 */
/*0780*/ FADD R6, R6, R21 ; /* 0x0000001506067221 */
/* 0x020fcc0000000000 */
/*0790*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e30000020f100 */
/*07a0*/ I2F R12, R6 ; /* 0x00000006000c7306 */
/* 0x001e240000201400 */
/*07b0*/ FADD R12, R12, R17 ; /* 0x000000110c0c7221 */
/* 0x001fcc0000000000 */
/*07c0*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e70000020f100 */
/*07d0*/ I2F R3, R12 ; /* 0x0000000c00037306 */
/* 0x002e240000201400 */
/*07e0*/ FADD R3, R3, R14 ; /* 0x0000000e03037221 */
/* 0x001fcc0000000000 */
/*07f0*/ F2I.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e30000020f100 */
/*0800*/ I2F R4, R3 ; /* 0x0000000300047306 */
/* 0x001e240000201400 */
/*0810*/ FADD R13, R4, R13 ; /* 0x0000000d040d7221 */
/* 0x001fcc0000000000 */
/*0820*/ F2I.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e22000020f100 */
/*0830*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fce0007ffe0ff */
/*0840*/ I2F R5, R13 ; /* 0x0000000d00057306 */
/* 0x001e220000201400 */
/*0850*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0860*/ IADD3 R4, R11, R18, R11 ; /* 0x000000120b047210 */
/* 0x000fe20007ffe00b */
/*0870*/ FADD R2, R5, R2 ; /* 0x0000000205027221 */
/* 0x001fc80000000000 */
/*0880*/ F2I.TRUNC.NTZ R24, R2 ; /* 0x0000000200187305 */
/* 0x000062000020f100 */
/*0890*/ IADD3 R4, R11, R4, R11 ; /* 0x000000040b047210 */
/* 0x000fca0007ffe00b */
/*08a0*/ @P1 BRA 0x2f0 ; /* 0xfffffa4000001947 */
/* 0x000fea000383ffff */
/*08b0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*08c0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fe20003f24270 */
/*08d0*/ BSSY B3, 0xbf0 ; /* 0x0000031000037945 */
/* 0x000fd80003800000 */
/*08e0*/ @!P1 BRA 0xbe0 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*08f0*/ MOV R27, 0x4 ; /* 0x00000004001b7802 */
/* 0x000fca0000000f00 */
/*0900*/ IMAD.WIDE R2, R4, R27, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fca00078e021b */
/*0910*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x0000a2000c1e1900 */
/*0920*/ IMAD.WIDE R18, R11, 0x4, R2 ; /* 0x000000040b127825 */
/* 0x000fca00078e0202 */
/*0930*/ LDG.E R7, [R18.64] ; /* 0x0000000412077981 */
/* 0x000722000c1e1900 */
/*0940*/ IMAD.WIDE R20, R11, 0x4, R18 ; /* 0x000000040b147825 */
/* 0x000fca00078e0212 */
/*0950*/ LDG.E R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x000f62000c1e1900 */
/*0960*/ IMAD.WIDE R22, R11, 0x4, R20 ; /* 0x000000040b167825 */
/* 0x000fca00078e0214 */
/*0970*/ LDG.E R13, [R22.64] ; /* 0x00000004160d7981 */
/* 0x000f22000c1e1900 */
/*0980*/ IADD3 R14, R11, R4, R11 ; /* 0x000000040b0e7210 */
/* 0x000fc80007ffe00b */
/*0990*/ IADD3 R14, R11, R14, R11 ; /* 0x0000000e0b0e7210 */
/* 0x000fca0007ffe00b */
/*09a0*/ IMAD.WIDE R26, R14, R27, c[0x0][0x160] ; /* 0x000058000e1a7625 */
/* 0x000fca00078e021b */
/*09b0*/ LDG.E R15, [R26.64] ; /* 0x000000041a0f7981 */
/* 0x000f22000c1e1900 */
/*09c0*/ IMAD.WIDE R28, R11, 0x4, R26 ; /* 0x000000040b1c7825 */
/* 0x000fca00078e021a */
/*09d0*/ LDG.E R16, [R28.64] ; /* 0x000000041c107981 */
/* 0x000f62000c1e1900 */
/*09e0*/ IMAD.WIDE R2, R11, 0x4, R28 ; /* 0x000000040b027825 */
/* 0x001fca00078e021c */
/*09f0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000162000c1e1900 */
/*0a00*/ IMAD.WIDE R4, R11, 0x4, R2 ; /* 0x000000040b047825 */
/* 0x000fcc00078e0202 */
/*0a10*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000364000c1e1900 */
/*0a20*/ I2F R19, R24 ; /* 0x0000001800137306 */
/* 0x00aea20000201400 */
/*0a30*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0a40*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ FADD R6, R19, R6 ; /* 0x0000000613067221 */
/* 0x004fcc0000000000 */
/*0a60*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e70000020f100 */
/*0a70*/ I2F R18, R6 ; /* 0x0000000600127306 */
/* 0x002f240000201400 */
/*0a80*/ FADD R7, R18, R7 ; /* 0x0000000712077221 */
/* 0x010fcc0000000000 */
/*0a90*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e70000020f100 */
/*0aa0*/ I2F R19, R7 ; /* 0x0000000700137306 */
/* 0x002f640000201400 */
/*0ab0*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x020fcc0000000000 */
/*0ac0*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*0ad0*/ I2F R2, R12 ; /* 0x0000000c00027306 */
/* 0x001e240000201400 */
/*0ae0*/ FADD R2, R2, R13 ; /* 0x0000000d02027221 */
/* 0x001fcc0000000000 */
/*0af0*/ F2I.TRUNC.NTZ R2, R2 ; /* 0x0000000200027305 */
/* 0x000e30000020f100 */
/*0b00*/ I2F R18, R2 ; /* 0x0000000200127306 */
/* 0x001e240000201400 */
/*0b10*/ FADD R15, R18, R15 ; /* 0x0000000f120f7221 */
/* 0x001fcc0000000000 */
/*0b20*/ F2I.TRUNC.NTZ R15, R15 ; /* 0x0000000f000f7305 */
/* 0x000e30000020f100 */
/*0b30*/ I2F R3, R15 ; /* 0x0000000f00037306 */
/* 0x001e240000201400 */
/*0b40*/ FADD R3, R3, R16 ; /* 0x0000001003037221 */
/* 0x001fcc0000000000 */
/*0b50*/ F2I.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e30000020f100 */
/*0b60*/ I2F R6, R3 ; /* 0x0000000300067306 */
/* 0x001e240000201400 */
/*0b70*/ FADD R6, R6, R17 ; /* 0x0000001106067221 */
/* 0x001fcc0000000000 */
/*0b80*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e30000020f100 */
/*0b90*/ I2F R5, R6 ; /* 0x0000000600057306 */
/* 0x001e240000201400 */
/*0ba0*/ FADD R5, R5, R4 ; /* 0x0000000405057221 */
/* 0x001fe20000000000 */
/*0bb0*/ IADD3 R4, R11, R14, R11 ; /* 0x0000000e0b047210 */
/* 0x000fca0007ffe00b */
/*0bc0*/ F2I.TRUNC.NTZ R24, R5 ; /* 0x0000000500187305 */
/* 0x000062000020f100 */
/*0bd0*/ IADD3 R4, R11, R4, R11 ; /* 0x000000040b047210 */
/* 0x000fce0007ffe00b */
/*0be0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0bf0*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0c00*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*0c10*/ @!P0 BRA 0xdd0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0c20*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0c30*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*0c40*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fca00078e0203 */
/*0c50*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0c60*/ IMAD.WIDE R6, R11, 0x4, R2 ; /* 0x000000040b067825 */
/* 0x000fca00078e0202 */
/*0c70*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ee2000c1e1900 */
/*0c80*/ IMAD.WIDE R12, R11, 0x4, R6 ; /* 0x000000040b0c7825 */
/* 0x000fca00078e0206 */
/*0c90*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000f22000c1e1900 */
/*0ca0*/ IMAD.WIDE R14, R11, 0x4, R12 ; /* 0x000000040b0e7825 */
/* 0x000fcc00078e020c */
/*0cb0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f62000c1e1900 */
/*0cc0*/ I2F R24, R24 ; /* 0x0000001800187306 */
/* 0x002ea20000201400 */
/*0cd0*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe40007ffe0ff */
/*0ce0*/ IADD3 R4, R11.reuse, R4, R11.reuse ; /* 0x000000040b047210 */
/* 0x140fe40007ffe00b */
/*0cf0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0d00*/ IADD3 R4, R11, R4, R11 ; /* 0x000000040b047210 */
/* 0x000fe20007ffe00b */
/*0d10*/ FADD R5, R5, R24 ; /* 0x0000001805057221 */
/* 0x004fcc0000000000 */
/*0d20*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e30000020f100 */
/*0d30*/ I2F R16, R5 ; /* 0x0000000500107306 */
/* 0x001ee40000201400 */
/*0d40*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x008fcc0000000000 */
/*0d50*/ F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000107305 */
/* 0x000e30000020f100 */
/*0d60*/ I2F R2, R16 ; /* 0x0000001000027306 */
/* 0x001f240000201400 */
/*0d70*/ FADD R2, R2, R19 ; /* 0x0000001302027221 */
/* 0x010fcc0000000000 */
/*0d80*/ F2I.TRUNC.NTZ R2, R2 ; /* 0x0000000200027305 */
/* 0x000e30000020f100 */
/*0d90*/ I2F R3, R2 ; /* 0x0000000200037306 */
/* 0x001f640000201400 */
/*0da0*/ FADD R3, R3, R14 ; /* 0x0000000e03037221 */
/* 0x020fcc0000000000 */
/*0db0*/ F2I.TRUNC.NTZ R24, R3 ; /* 0x0000000300187305 */
/* 0x000062000020f100 */
/*0dc0*/ @P0 BRA 0xc30 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0dd0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0de0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*0df0*/ @!P0 BRA 0xea0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0e00*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x001fca0000000f00 */
/*0e10*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0e20*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x0010a2000c1e1900 */
/*0e30*/ I2F R3, R24 ; /* 0x0000001800037306 */
/* 0x002ea20000201400 */
/*0e40*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fc80007ffe0ff */
/*0e50*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0e60*/ IMAD.WIDE R4, R11, 0x4, R4 ; /* 0x000000040b047825 */
/* 0x001fc800078e0204 */
/*0e70*/ FADD R2, R2, R3 ; /* 0x0000000302027221 */
/* 0x004fc80000000000 */
/*0e80*/ F2I.TRUNC.NTZ R24, R2 ; /* 0x0000000200187305 */
/* 0x000068000020f100 */
/*0e90*/ @P0 BRA 0xe20 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0ea0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0eb0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0ec0*/ ISETP.GT.U32.AND P1, PT, R9.reuse, 0xff, PT ; /* 0x000000ff0900780c */
/* 0x040fe20003f24070 */
/*0ed0*/ STS [R9.X4], R24 ; /* 0x0000001809007388 */
/* 0x0023e80000004800 */
/*0ee0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0ef0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fce0003f05270 */
/*0f00*/ @P1 BRA 0x1000 ; /* 0x000000f000001947 */
/* 0x000fec0003800000 */
/*0f10*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.52587890625e-05 ; /* 0x00000100ff037435 */
/* 0x003fe200000001ff */
/*0f20*/ IMAD.SHL.U32 R2, R9, 0x4, RZ ; /* 0x0000000409027824 */
/* 0x000fd200078e00ff */
/*0f30*/ SHF.R.U32.HI R8, RZ, 0x1, R3 ; /* 0x00000001ff087819 */
/* 0x000fe20000011603 */
/*0f40*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*0f50*/ ISETP.GE.U32.AND P1, PT, R9.reuse, R8.reuse, PT ; /* 0x000000080900720c */
/* 0x0c0fe40003f26070 */
/*0f60*/ ISETP.LT.U32.AND P2, PT, R9, R8, PT ; /* 0x000000080900720c */
/* 0x000fd60003f41070 */
/*0f70*/ @!P1 LEA R4, R8, R2, 0x2 ; /* 0x0000000208049211 */
/* 0x000fe200078e10ff */
/*0f80*/ @!P1 LDS R5, [R9.X4] ; /* 0x0000000009059984 */
/* 0x000fea0000004800 */
/*0f90*/ @!P1 LDS R4, [R4] ; /* 0x0000000004049984 */
/* 0x000e240000000800 */
/*0fa0*/ @!P1 IADD3 R6, R5, R4, RZ ; /* 0x0000000405069210 */
/* 0x001fca0007ffe0ff */
/*0fb0*/ @!P1 STS [R9.X4], R6 ; /* 0x0000000609009388 */
/* 0x0001e80000004800 */
/*0fc0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0fd0*/ ISETP.GT.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f24070 */
/*0fe0*/ MOV R3, R8 ; /* 0x0000000800037202 */
/* 0x000fd60000000f00 */
/*0ff0*/ @P1 BRA P2, 0xf30 ; /* 0xffffff3000001947 */
/* 0x001fea000103ffff */
/*1000*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x002fea0003800000 */
/*1010*/ LDS R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e620000000800 */
/*1020*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x001fca0000000f00 */
/*1030*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe200078e0003 */
/*1040*/ I2F R5, R4 ; /* 0x0000000400057306 */
/* 0x002e280000201400 */
/*1050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*1060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1070*/ BRA 0x1070; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#define THREADS_PER_BLOCK 256
#define BLOCKS 128
#define N (1 << 16)
using namespace std;
__global__ void add_array(float A[], float blocks[])
{
__shared__ int array_per_block[THREADS_PER_BLOCK];
int global_thread_ID = blockIdx.x * THREADS_PER_BLOCK + threadIdx.x, step = gridDim.x * THREADS_PER_BLOCK, my_sum = 0, num_threads = THREADS_PER_BLOCK;
for(int i = global_thread_ID; i < N; i += step)
my_sum += A[i];
array_per_block[threadIdx.x] = my_sum;
__syncthreads();
while(threadIdx.x < num_threads && num_threads > 1)
{
if(threadIdx.x < num_threads / 2)
array_per_block[threadIdx.x] += array_per_block[threadIdx.x + num_threads / 2];
num_threads = num_threads >> 1;
__syncthreads();
}
if(threadIdx.x == 0)
blocks[blockIdx.x] = array_per_block[0];
}
void init_array(float A[])
{
for(int i = 0; i < N; i++)
A[i] = 1;
}
int main()
{
float *host_A = new float[N], *host_blocks = new float[BLOCKS], *cuda_A, *cuda_blocks, final_sum = 0;
init_array(host_A);
cudaMalloc(&cuda_A, sizeof(float) * N);
cudaMemcpy(cuda_A, host_A, sizeof(float) * N, cudaMemcpyHostToDevice);
cudaMalloc(&cuda_blocks, sizeof(float) * BLOCKS);
add_array<<<BLOCKS, THREADS_PER_BLOCK>>>(cuda_A, cuda_blocks);
cudaMemcpy(host_blocks, cuda_blocks, sizeof(float) * BLOCKS, cudaMemcpyDeviceToHost);
for(int i = 0; i < BLOCKS; i++)
final_sum += host_blocks[i];
cout << "Final Sum : " << final_sum << endl;
free(host_A); free(host_blocks);
cudaFree(cuda_A); cudaFree(cuda_blocks);
return 0;
} | .file "tmpxft_000867b2_00000000-6_p2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10init_arrayPf
.type _Z10init_arrayPf, @function
_Z10init_arrayPf:
.LFB3669:
.cfi_startproc
endbr64
leaq 262144(%rdi), %rax
movss .LC0(%rip), %xmm0
.L4:
movss %xmm0, (%rdi)
addq $4, %rdi
cmpq %rax, %rdi
jne .L4
ret
.cfi_endproc
.LFE3669:
.size _Z10init_arrayPf, .-_Z10init_arrayPf
.globl _Z30__device_stub__Z9add_arrayPfS_PfS_
.type _Z30__device_stub__Z9add_arrayPfS_PfS_, @function
_Z30__device_stub__Z9add_arrayPfS_PfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9add_arrayPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z30__device_stub__Z9add_arrayPfS_PfS_, .-_Z30__device_stub__Z9add_arrayPfS_PfS_
.globl _Z9add_arrayPfS_
.type _Z9add_arrayPfS_, @function
_Z9add_arrayPfS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9add_arrayPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9add_arrayPfS_, .-_Z9add_arrayPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Final Sum : "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $262144, %edi
call _Znam@PLT
movq %rax, %rbp
movl $512, %edi
call _Znam@PLT
movq %rax, %rbx
movq %rbp, %rdi
call _Z10init_arrayPf
leaq 16(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $262144, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $128, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L15:
movl $2, %ecx
movl $512, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 512(%rbx), %rdx
movl $0x00000000, 12(%rsp)
.L16:
movss 12(%rsp), %xmm1
addss (%rax), %xmm1
movss %xmm1, 12(%rsp)
addq $4, %rax
cmpq %rdx, %rax
jne .L16
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z9add_arrayPfS_PfS_
jmp .L15
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9add_arrayPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9add_arrayPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#define THREADS_PER_BLOCK 256
#define BLOCKS 128
#define N (1 << 16)
using namespace std;
__global__ void add_array(float A[], float blocks[])
{
__shared__ int array_per_block[THREADS_PER_BLOCK];
int global_thread_ID = blockIdx.x * THREADS_PER_BLOCK + threadIdx.x, step = gridDim.x * THREADS_PER_BLOCK, my_sum = 0, num_threads = THREADS_PER_BLOCK;
for(int i = global_thread_ID; i < N; i += step)
my_sum += A[i];
array_per_block[threadIdx.x] = my_sum;
__syncthreads();
while(threadIdx.x < num_threads && num_threads > 1)
{
if(threadIdx.x < num_threads / 2)
array_per_block[threadIdx.x] += array_per_block[threadIdx.x + num_threads / 2];
num_threads = num_threads >> 1;
__syncthreads();
}
if(threadIdx.x == 0)
blocks[blockIdx.x] = array_per_block[0];
}
void init_array(float A[])
{
for(int i = 0; i < N; i++)
A[i] = 1;
}
int main()
{
float *host_A = new float[N], *host_blocks = new float[BLOCKS], *cuda_A, *cuda_blocks, final_sum = 0;
init_array(host_A);
cudaMalloc(&cuda_A, sizeof(float) * N);
cudaMemcpy(cuda_A, host_A, sizeof(float) * N, cudaMemcpyHostToDevice);
cudaMalloc(&cuda_blocks, sizeof(float) * BLOCKS);
add_array<<<BLOCKS, THREADS_PER_BLOCK>>>(cuda_A, cuda_blocks);
cudaMemcpy(host_blocks, cuda_blocks, sizeof(float) * BLOCKS, cudaMemcpyDeviceToHost);
for(int i = 0; i < BLOCKS; i++)
final_sum += host_blocks[i];
cout << "Final Sum : " << final_sum << endl;
free(host_A); free(host_blocks);
cudaFree(cuda_A); cudaFree(cuda_blocks);
return 0;
} | #include <hip/hip_runtime.h>
#include<iostream>
#define THREADS_PER_BLOCK 256
#define BLOCKS 128
#define N (1 << 16)
using namespace std;
__global__ void add_array(float A[], float blocks[])
{
__shared__ int array_per_block[THREADS_PER_BLOCK];
int global_thread_ID = blockIdx.x * THREADS_PER_BLOCK + threadIdx.x, step = gridDim.x * THREADS_PER_BLOCK, my_sum = 0, num_threads = THREADS_PER_BLOCK;
for(int i = global_thread_ID; i < N; i += step)
my_sum += A[i];
array_per_block[threadIdx.x] = my_sum;
__syncthreads();
while(threadIdx.x < num_threads && num_threads > 1)
{
if(threadIdx.x < num_threads / 2)
array_per_block[threadIdx.x] += array_per_block[threadIdx.x + num_threads / 2];
num_threads = num_threads >> 1;
__syncthreads();
}
if(threadIdx.x == 0)
blocks[blockIdx.x] = array_per_block[0];
}
void init_array(float A[])
{
for(int i = 0; i < N; i++)
A[i] = 1;
}
int main()
{
float *host_A = new float[N], *host_blocks = new float[BLOCKS], *cuda_A, *cuda_blocks, final_sum = 0;
init_array(host_A);
hipMalloc(&cuda_A, sizeof(float) * N);
hipMemcpy(cuda_A, host_A, sizeof(float) * N, hipMemcpyHostToDevice);
hipMalloc(&cuda_blocks, sizeof(float) * BLOCKS);
add_array<<<BLOCKS, THREADS_PER_BLOCK>>>(cuda_A, cuda_blocks);
hipMemcpy(host_blocks, cuda_blocks, sizeof(float) * BLOCKS, hipMemcpyDeviceToHost);
for(int i = 0; i < BLOCKS; i++)
final_sum += host_blocks[i];
cout << "Final Sum : " << final_sum << endl;
free(host_A); free(host_blocks);
hipFree(cuda_A); hipFree(cuda_blocks);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#define THREADS_PER_BLOCK 256
#define BLOCKS 128
#define N (1 << 16)
using namespace std;
__global__ void add_array(float A[], float blocks[])
{
__shared__ int array_per_block[THREADS_PER_BLOCK];
int global_thread_ID = blockIdx.x * THREADS_PER_BLOCK + threadIdx.x, step = gridDim.x * THREADS_PER_BLOCK, my_sum = 0, num_threads = THREADS_PER_BLOCK;
for(int i = global_thread_ID; i < N; i += step)
my_sum += A[i];
array_per_block[threadIdx.x] = my_sum;
__syncthreads();
while(threadIdx.x < num_threads && num_threads > 1)
{
if(threadIdx.x < num_threads / 2)
array_per_block[threadIdx.x] += array_per_block[threadIdx.x + num_threads / 2];
num_threads = num_threads >> 1;
__syncthreads();
}
if(threadIdx.x == 0)
blocks[blockIdx.x] = array_per_block[0];
}
void init_array(float A[])
{
for(int i = 0; i < N; i++)
A[i] = 1;
}
int main()
{
float *host_A = new float[N], *host_blocks = new float[BLOCKS], *cuda_A, *cuda_blocks, final_sum = 0;
init_array(host_A);
hipMalloc(&cuda_A, sizeof(float) * N);
hipMemcpy(cuda_A, host_A, sizeof(float) * N, hipMemcpyHostToDevice);
hipMalloc(&cuda_blocks, sizeof(float) * BLOCKS);
add_array<<<BLOCKS, THREADS_PER_BLOCK>>>(cuda_A, cuda_blocks);
hipMemcpy(host_blocks, cuda_blocks, sizeof(float) * BLOCKS, hipMemcpyDeviceToHost);
for(int i = 0; i < BLOCKS; i++)
final_sum += host_blocks[i];
cout << "Final Sum : " << final_sum << endl;
free(host_A); free(host_blocks);
hipFree(cuda_A); hipFree(cuda_blocks);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9add_arrayPfS_
.globl _Z9add_arrayPfS_
.p2align 8
.type _Z9add_arrayPfS_,@function
_Z9add_arrayPfS_:
s_mov_b32 s4, s15
v_mov_b32_e32 v4, 0
v_lshl_add_u32 v1, s4, 8, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x10000, v1
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b32 s2, s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 0
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_lshl_b32 s6, s2, 8
v_add_co_u32 v2, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[8:9], s[6:7], 2
.LBB0_2:
global_load_b32 v5, v[2:3], off
v_cvt_f32_i32_e32 v4, v4
v_add_nc_u32_e32 v1, s6, v1
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v5, v4
v_cmp_lt_i32_e64 s2, 0xffff, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e32 v4, v4
s_or_b32 s5, s2, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_lshlrev_b32_e32 v1, 2, v0
s_movk_i32 s2, 0x100
s_mov_b32 s3, exec_lo
ds_store_b32 v1, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB0_9
v_max_u32_e32 v2, 1, v0
s_mov_b32 s5, 0
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s6
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_9
.LBB0_7:
s_lshr_b32 s2, s2, 1
s_mov_b32 s6, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v3, s2, v0, 2
ds_load_b32 v3, v3
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
ds_store_b32 v1, v3
s_branch .LBB0_6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_cvt_f32_i32_e32 v1, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9add_arrayPfS_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9add_arrayPfS_, .Lfunc_end0-_Z9add_arrayPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9add_arrayPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9add_arrayPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#define THREADS_PER_BLOCK 256
#define BLOCKS 128
#define N (1 << 16)
using namespace std;
__global__ void add_array(float A[], float blocks[])
{
__shared__ int array_per_block[THREADS_PER_BLOCK];
int global_thread_ID = blockIdx.x * THREADS_PER_BLOCK + threadIdx.x, step = gridDim.x * THREADS_PER_BLOCK, my_sum = 0, num_threads = THREADS_PER_BLOCK;
for(int i = global_thread_ID; i < N; i += step)
my_sum += A[i];
array_per_block[threadIdx.x] = my_sum;
__syncthreads();
while(threadIdx.x < num_threads && num_threads > 1)
{
if(threadIdx.x < num_threads / 2)
array_per_block[threadIdx.x] += array_per_block[threadIdx.x + num_threads / 2];
num_threads = num_threads >> 1;
__syncthreads();
}
if(threadIdx.x == 0)
blocks[blockIdx.x] = array_per_block[0];
}
void init_array(float A[])
{
for(int i = 0; i < N; i++)
A[i] = 1;
}
int main()
{
float *host_A = new float[N], *host_blocks = new float[BLOCKS], *cuda_A, *cuda_blocks, final_sum = 0;
init_array(host_A);
hipMalloc(&cuda_A, sizeof(float) * N);
hipMemcpy(cuda_A, host_A, sizeof(float) * N, hipMemcpyHostToDevice);
hipMalloc(&cuda_blocks, sizeof(float) * BLOCKS);
add_array<<<BLOCKS, THREADS_PER_BLOCK>>>(cuda_A, cuda_blocks);
hipMemcpy(host_blocks, cuda_blocks, sizeof(float) * BLOCKS, hipMemcpyDeviceToHost);
for(int i = 0; i < BLOCKS; i++)
final_sum += host_blocks[i];
cout << "Final Sum : " << final_sum << endl;
free(host_A); free(host_blocks);
hipFree(cuda_A); hipFree(cuda_blocks);
return 0;
} | .text
.file "p2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__add_arrayPfS_ # -- Begin function _Z24__device_stub__add_arrayPfS_
.p2align 4, 0x90
.type _Z24__device_stub__add_arrayPfS_,@function
_Z24__device_stub__add_arrayPfS_: # @_Z24__device_stub__add_arrayPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9add_arrayPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__add_arrayPfS_, .Lfunc_end0-_Z24__device_stub__add_arrayPfS_
.cfi_endproc
# -- End function
.globl _Z10init_arrayPf # -- Begin function _Z10init_arrayPf
.p2align 4, 0x90
.type _Z10init_arrayPf,@function
_Z10init_arrayPf: # @_Z10init_arrayPf
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rdi,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z10init_arrayPf, .Lfunc_end1-_Z10init_arrayPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $262144, %edi # imm = 0x40000
callq _Znam
movq %rax, %rbx
movl $512, %edi # imm = 0x200
callq _Znam
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB2_1
# %bb.2: # %_Z10init_arrayPf.exit
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
movq 16(%rsp), %rdi
movl $262144, %edx # imm = 0x40000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movabsq $4294967424, %rdi # imm = 0x100000080
leaq 128(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9add_arrayPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
addss (%r14,%rax,4), %xmm0
incq %rax
cmpq $128, %rax
jne .LBB2_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $12, %edx
movss %xmm0, 28(%rsp) # 4-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 28(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB2_9
# %bb.8:
movzbl 67(%r15), %ecx
jmp .LBB2_10
.LBB2_9:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9add_arrayPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9add_arrayPfS_,@object # @_Z9add_arrayPfS_
.section .rodata,"a",@progbits
.globl _Z9add_arrayPfS_
.p2align 3, 0x0
_Z9add_arrayPfS_:
.quad _Z24__device_stub__add_arrayPfS_
.size _Z9add_arrayPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Final Sum : "
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9add_arrayPfS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__add_arrayPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9add_arrayPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9add_arrayPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B2, 0xeb0 ; /* 0x00000e7000027945 */
/* 0x000fe20003800000 */
/*0040*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0060*/ LEA R4, R0, R9, 0x8 ; /* 0x0000000900047211 */
/* 0x001fc800078e40ff */
/*0070*/ ISETP.GT.AND P0, PT, R4, 0xffff, PT ; /* 0x0000ffff0400780c */
/* 0x000fda0003f04270 */
/*0080*/ @P0 BRA 0xea0 ; /* 0x00000e1000000947 */
/* 0x000fea0003800000 */
/*0090*/ MOV R11, c[0x0][0xc] ; /* 0x00000300000b7a02 */
/* 0x000fe20000000f00 */
/*00a0*/ BSSY B1, 0xde0 ; /* 0x00000d3000017945 */
/* 0x000fe20003800000 */
/*00b0*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fe40000000f00 */
/*00c0*/ SHF.L.U32 R11, R11, 0x8, RZ ; /* 0x000000080b0b7819 */
/* 0x000fe400000006ff */
/*00d0*/ IADD3 R5, -R9, 0xffff, RZ ; /* 0x0000ffff09057810 */
/* 0x000fe40007ffe1ff */
/*00e0*/ I2F.U32.RP R6, R11 ; /* 0x0000000b00067306 */
/* 0x000e220000209000 */
/*00f0*/ IADD3 R7, RZ, -R11, RZ ; /* 0x8000000bff077210 */
/* 0x000fe40007ffe0ff */
/*0100*/ ISETP.NE.U32.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fc40003f45070 */
/*0110*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fc60000000f00 */
/*0120*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0130*/ IADD3 R3, R6, 0xffffffe, RZ ; /* 0x0ffffffe06037810 */
/* 0x001fcc0007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*0150*/ IMAD R7, R7, R3, RZ ; /* 0x0000000307077224 */
/* 0x001fc800078e02ff */
/*0160*/ IMAD.HI.U32 R7, R3, R7, R2 ; /* 0x0000000703077227 */
/* 0x000fc800078e0002 */
/*0170*/ IMAD R2, R0, -0x100, R5 ; /* 0xffffff0000027824 */
/* 0x000fc800078e0205 */
/*0180*/ IMAD.HI.U32 R7, R7, R2, RZ ; /* 0x0000000207077227 */
/* 0x000fca00078e00ff */
/*0190*/ IADD3 R5, -R7, RZ, RZ ; /* 0x000000ff07057210 */
/* 0x000fca0007ffe1ff */
/*01a0*/ IMAD R2, R11, R5, R2 ; /* 0x000000050b027224 */
/* 0x000fca00078e0202 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R2, R11, PT ; /* 0x0000000b0200720c */
/* 0x000fda0003f06070 */
/*01c0*/ @P0 IADD3 R2, -R11, R2, RZ ; /* 0x000000020b020210 */
/* 0x000fe40007ffe1ff */
/*01d0*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R2, R11, PT ; /* 0x0000000b0200720c */
/* 0x000fda0003f26070 */
/*01f0*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fe40007ffe0ff */
/*0200*/ @!P2 LOP3.LUT R7, RZ, R11, RZ, 0x33, !PT ; /* 0x0000000bff07a212 */
/* 0x000fc800078e33ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R7.reuse, 0x3, PT ; /* 0x000000030700780c */
/* 0x040fe40003f06070 */
/*0220*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*0230*/ LOP3.LUT R10, R7, 0x3, RZ, 0xc0, !PT ; /* 0x00000003070a7812 */
/* 0x000fce00078ec0ff */
/*0240*/ @!P0 BRA 0xdd0 ; /* 0x00000b8000008947 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.IADD R8, R7, 0x1, -R10 ; /* 0x0000000107087824 */
/* 0x000fe200078e0a0a */
/*0260*/ BSSY B0, 0xc30 ; /* 0x000009c000007945 */
/* 0x000fe20003800000 */
/*0270*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fc600000001ff */
/*0280*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f04270 */
/*0290*/ @!P0 BRA 0xc20 ; /* 0x0000098000008947 */
/* 0x000fea0003800000 */
/*02a0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*02b0*/ BSSY B3, 0x8c0 ; /* 0x0000060000037945 */
/* 0x000fe20003800000 */
/*02c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*02d0*/ @!P1 BRA 0x8b0 ; /* 0x000005d000009947 */
/* 0x000fea0003800000 */
/*02e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02f0*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x000fd400000001ff */
/*0300*/ IMAD.WIDE R6, R4, R17, c[0x0][0x160] ; /* 0x0000580004067625 */
/* 0x000fca00078e0211 */
/*0310*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0010a2000c1e1900 */
/*0320*/ IMAD.WIDE R20, R11, 0x4, R6 ; /* 0x000000040b147825 */
/* 0x000fca00078e0206 */
/*0330*/ LDG.E R23, [R20.64] ; /* 0x0000000414177981 */
/* 0x0022e2000c1e1900 */
/*0340*/ IMAD.WIDE R26, R11, 0x4, R20 ; /* 0x000000040b1a7825 */
/* 0x000fca00078e0214 */
/*0350*/ LDG.E R22, [R26.64] ; /* 0x000000041a167981 */
/* 0x000962000c1e1900 */
/*0360*/ IMAD.WIDE R18, R11, 0x4, R26 ; /* 0x000000040b127825 */
/* 0x000fcc00078e021a */
/*0370*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000e2000c1e1900 */
/*0380*/ IADD3 R4, R11, R4, R11 ; /* 0x000000040b047210 */
/* 0x000fc80007ffe00b */
/*0390*/ IADD3 R16, R11, R4, R11 ; /* 0x000000040b107210 */
/* 0x000fca0007ffe00b */
/*03a0*/ IMAD.WIDE R28, R16, R17, c[0x0][0x160] ; /* 0x00005800101c7625 */
/* 0x000fca00078e0211 */
/*03b0*/ LDG.E R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x0000e4000c1e1900 */
/*03c0*/ IMAD.WIDE R28, R11, 0x4, R28 ; /* 0x000000040b1c7825 */
/* 0x001fca00078e021c */
/*03d0*/ LDG.E R13, [R28.64] ; /* 0x000000041c0d7981 */
/* 0x000f62000c1e1900 */
/*03e0*/ IMAD.WIDE R4, R11, 0x4, R28 ; /* 0x000000040b047825 */
/* 0x000fca00078e021c */
/*03f0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000162000c1e1900 */
/*0400*/ IMAD.WIDE R20, R11, 0x4, R4 ; /* 0x000000040b147825 */
/* 0x002fca00078e0204 */
/*0410*/ LDG.E R15, [R20.64] ; /* 0x00000004140f7981 */
/* 0x000362000c1e1900 */
/*0420*/ I2F R3, R24 ; /* 0x0000001800037306 */
/* 0x000ea20000201400 */
/*0430*/ IADD3 R26, R11, R16, R11 ; /* 0x000000100b1a7210 */
/* 0x010fc80007ffe00b */
/*0440*/ IADD3 R26, R11, R26, R11 ; /* 0x0000001a0b1a7210 */
/* 0x000fca0007ffe00b */
/*0450*/ IMAD.WIDE R6, R26, R17, c[0x0][0x160] ; /* 0x000058001a067625 */
/* 0x000fca00078e0211 */
/*0460*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000922000c1e1900 */
/*0470*/ FADD R25, R3, R2 ; /* 0x0000000203197221 */
/* 0x004fe40000000000 */
/*0480*/ IMAD.WIDE R2, R11, 0x4, R6 ; /* 0x000000040b027825 */
/* 0x000fc800078e0206 */
/*0490*/ F2I.TRUNC.NTZ R25, R25 ; /* 0x0000001900197305 */
/* 0x000e22000020f100 */
/*04a0*/ LDG.E R19, [R2.64] ; /* 0x0000000402137981 */
/* 0x0006ae000c1e1900 */
/*04b0*/ I2F R4, R25 ; /* 0x0000001900047306 */
/* 0x001ee40000201400 */
/*04c0*/ FADD R23, R4, R23 ; /* 0x0000001704177221 */
/* 0x008fcc0000000000 */
/*04d0*/ F2I.TRUNC.NTZ R23, R23 ; /* 0x0000001700177305 */
/* 0x000e22000020f100 */
/*04e0*/ IMAD.WIDE R4, R11, 0x4, R2 ; /* 0x000000040b047825 */
/* 0x000fca00078e0202 */
/*04f0*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x0022e4000c1e1900 */
/*0500*/ I2F R21, R23 ; /* 0x0000001700157306 */
/* 0x001f640000201400 */
/*0510*/ FADD R22, R21, R22 ; /* 0x0000001615167221 */
/* 0x020fcc0000000000 */
/*0520*/ F2I.TRUNC.NTZ R22, R22 ; /* 0x0000001600167305 */
/* 0x000e22000020f100 */
/*0530*/ IMAD.WIDE R6, R11, 0x4, R4 ; /* 0x000000040b067825 */
/* 0x010fca00078e0204 */
/*0540*/ LDG.E R21, [R6.64] ; /* 0x0000000406157981 */
/* 0x000964000c1e1900 */
/*0550*/ I2F R27, R22 ; /* 0x00000016001b7306 */
/* 0x001e240000201400 */
/*0560*/ FADD R27, R27, R18 ; /* 0x000000121b1b7221 */
/* 0x001fcc0000000000 */
/*0570*/ F2I.TRUNC.NTZ R27, R27 ; /* 0x0000001b001b7305 */
/* 0x000e62000020f100 */
/*0580*/ IADD3 R18, R11, R26, R11 ; /* 0x0000001a0b127210 */
/* 0x000fc80007ffe00b */
/*0590*/ IADD3 R18, R11, R18, R11 ; /* 0x000000120b127210 */
/* 0x000fc60007ffe00b */
/*05a0*/ I2F R5, R27 ; /* 0x0000001b00057306 */
/* 0x002e240000201400 */
/*05b0*/ IMAD.WIDE R2, R18, R17, c[0x0][0x160] ; /* 0x0000580012027625 */
/* 0x000fca00078e0211 */
/*05c0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000362000c1e1900 */
/*05d0*/ FADD R23, R5, R14 ; /* 0x0000000e05177221 */
/* 0x001fcc0000000000 */
/*05e0*/ F2I.TRUNC.NTZ R23, R23 ; /* 0x0000001700177305 */
/* 0x000f22000020f100 */
/*05f0*/ IMAD.WIDE R4, R11, 0x4, R2 ; /* 0x000000040b047825 */
/* 0x000fca00078e0202 */
/*0600*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000164000c1e1900 */
/*0610*/ I2F R6, R23 ; /* 0x0000001700067306 */
/* 0x010f240000201400 */
/*0620*/ FADD R22, R6, R13 ; /* 0x0000000d06167221 */
/* 0x010fcc0000000000 */
/*0630*/ F2I.TRUNC.NTZ R22, R22 ; /* 0x0000001600167305 */
/* 0x000f22000020f100 */
/*0640*/ IMAD.WIDE R6, R11, 0x4, R4 ; /* 0x000000040b067825 */
/* 0x000fca00078e0204 */
/*0650*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000164000c1e1900 */
/*0660*/ I2F R25, R22 ; /* 0x0000001600197306 */
/* 0x010f240000201400 */
/*0670*/ FADD R12, R25, R12 ; /* 0x0000000c190c7221 */
/* 0x010fcc0000000000 */
/*0680*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000f22000020f100 */
/*0690*/ IMAD.WIDE R2, R11, 0x4, R6 ; /* 0x000000040b027825 */
/* 0x002fcc00078e0206 */
/*06a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000362000c1e1900 */
/*06b0*/ I2F R24, R12 ; /* 0x0000000c00187306 */
/* 0x010f240000201400 */
/*06c0*/ FADD R15, R24, R15 ; /* 0x0000000f180f7221 */
/* 0x010fcc0000000000 */
/*06d0*/ F2I.TRUNC.NTZ R15, R15 ; /* 0x0000000f000f7305 */
/* 0x000e30000020f100 */
/*06e0*/ I2F R5, R15 ; /* 0x0000000f00057306 */
/* 0x001e240000201400 */
/*06f0*/ FADD R5, R5, R16 ; /* 0x0000001005057221 */
/* 0x001fcc0000000000 */
/*0700*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e30000020f100 */
/*0710*/ I2F R4, R5 ; /* 0x0000000500047306 */
/* 0x001ea40000201400 */
/*0720*/ FADD R4, R4, R19 ; /* 0x0000001304047221 */
/* 0x004fcc0000000000 */
/*0730*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e30000020f100 */
/*0740*/ I2F R7, R4 ; /* 0x0000000400077306 */
/* 0x001ee40000201400 */
/*0750*/ FADD R7, R7, R20 ; /* 0x0000001407077221 */
/* 0x008fcc0000000000 */
/*0760*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*0770*/ I2F R6, R7 ; /* 0x0000000700067306 */
/* 0x001f640000201400 */
/*0780*/ FADD R6, R6, R21 ; /* 0x0000001506067221 */
/* 0x020fcc0000000000 */
/*0790*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e30000020f100 */
/*07a0*/ I2F R12, R6 ; /* 0x00000006000c7306 */
/* 0x001e240000201400 */
/*07b0*/ FADD R12, R12, R17 ; /* 0x000000110c0c7221 */
/* 0x001fcc0000000000 */
/*07c0*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e70000020f100 */
/*07d0*/ I2F R3, R12 ; /* 0x0000000c00037306 */
/* 0x002e240000201400 */
/*07e0*/ FADD R3, R3, R14 ; /* 0x0000000e03037221 */
/* 0x001fcc0000000000 */
/*07f0*/ F2I.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e30000020f100 */
/*0800*/ I2F R4, R3 ; /* 0x0000000300047306 */
/* 0x001e240000201400 */
/*0810*/ FADD R13, R4, R13 ; /* 0x0000000d040d7221 */
/* 0x001fcc0000000000 */
/*0820*/ F2I.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e22000020f100 */
/*0830*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fce0007ffe0ff */
/*0840*/ I2F R5, R13 ; /* 0x0000000d00057306 */
/* 0x001e220000201400 */
/*0850*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0860*/ IADD3 R4, R11, R18, R11 ; /* 0x000000120b047210 */
/* 0x000fe20007ffe00b */
/*0870*/ FADD R2, R5, R2 ; /* 0x0000000205027221 */
/* 0x001fc80000000000 */
/*0880*/ F2I.TRUNC.NTZ R24, R2 ; /* 0x0000000200187305 */
/* 0x000062000020f100 */
/*0890*/ IADD3 R4, R11, R4, R11 ; /* 0x000000040b047210 */
/* 0x000fca0007ffe00b */
/*08a0*/ @P1 BRA 0x2f0 ; /* 0xfffffa4000001947 */
/* 0x000fea000383ffff */
/*08b0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*08c0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fe20003f24270 */
/*08d0*/ BSSY B3, 0xbf0 ; /* 0x0000031000037945 */
/* 0x000fd80003800000 */
/*08e0*/ @!P1 BRA 0xbe0 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*08f0*/ MOV R27, 0x4 ; /* 0x00000004001b7802 */
/* 0x000fca0000000f00 */
/*0900*/ IMAD.WIDE R2, R4, R27, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fca00078e021b */
/*0910*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x0000a2000c1e1900 */
/*0920*/ IMAD.WIDE R18, R11, 0x4, R2 ; /* 0x000000040b127825 */
/* 0x000fca00078e0202 */
/*0930*/ LDG.E R7, [R18.64] ; /* 0x0000000412077981 */
/* 0x000722000c1e1900 */
/*0940*/ IMAD.WIDE R20, R11, 0x4, R18 ; /* 0x000000040b147825 */
/* 0x000fca00078e0212 */
/*0950*/ LDG.E R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x000f62000c1e1900 */
/*0960*/ IMAD.WIDE R22, R11, 0x4, R20 ; /* 0x000000040b167825 */
/* 0x000fca00078e0214 */
/*0970*/ LDG.E R13, [R22.64] ; /* 0x00000004160d7981 */
/* 0x000f22000c1e1900 */
/*0980*/ IADD3 R14, R11, R4, R11 ; /* 0x000000040b0e7210 */
/* 0x000fc80007ffe00b */
/*0990*/ IADD3 R14, R11, R14, R11 ; /* 0x0000000e0b0e7210 */
/* 0x000fca0007ffe00b */
/*09a0*/ IMAD.WIDE R26, R14, R27, c[0x0][0x160] ; /* 0x000058000e1a7625 */
/* 0x000fca00078e021b */
/*09b0*/ LDG.E R15, [R26.64] ; /* 0x000000041a0f7981 */
/* 0x000f22000c1e1900 */
/*09c0*/ IMAD.WIDE R28, R11, 0x4, R26 ; /* 0x000000040b1c7825 */
/* 0x000fca00078e021a */
/*09d0*/ LDG.E R16, [R28.64] ; /* 0x000000041c107981 */
/* 0x000f62000c1e1900 */
/*09e0*/ IMAD.WIDE R2, R11, 0x4, R28 ; /* 0x000000040b027825 */
/* 0x001fca00078e021c */
/*09f0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000162000c1e1900 */
/*0a00*/ IMAD.WIDE R4, R11, 0x4, R2 ; /* 0x000000040b047825 */
/* 0x000fcc00078e0202 */
/*0a10*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000364000c1e1900 */
/*0a20*/ I2F R19, R24 ; /* 0x0000001800137306 */
/* 0x00aea20000201400 */
/*0a30*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0a40*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ FADD R6, R19, R6 ; /* 0x0000000613067221 */
/* 0x004fcc0000000000 */
/*0a60*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e70000020f100 */
/*0a70*/ I2F R18, R6 ; /* 0x0000000600127306 */
/* 0x002f240000201400 */
/*0a80*/ FADD R7, R18, R7 ; /* 0x0000000712077221 */
/* 0x010fcc0000000000 */
/*0a90*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e70000020f100 */
/*0aa0*/ I2F R19, R7 ; /* 0x0000000700137306 */
/* 0x002f640000201400 */
/*0ab0*/ FADD R12, R19, R12 ; /* 0x0000000c130c7221 */
/* 0x020fcc0000000000 */
/*0ac0*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*0ad0*/ I2F R2, R12 ; /* 0x0000000c00027306 */
/* 0x001e240000201400 */
/*0ae0*/ FADD R2, R2, R13 ; /* 0x0000000d02027221 */
/* 0x001fcc0000000000 */
/*0af0*/ F2I.TRUNC.NTZ R2, R2 ; /* 0x0000000200027305 */
/* 0x000e30000020f100 */
/*0b00*/ I2F R18, R2 ; /* 0x0000000200127306 */
/* 0x001e240000201400 */
/*0b10*/ FADD R15, R18, R15 ; /* 0x0000000f120f7221 */
/* 0x001fcc0000000000 */
/*0b20*/ F2I.TRUNC.NTZ R15, R15 ; /* 0x0000000f000f7305 */
/* 0x000e30000020f100 */
/*0b30*/ I2F R3, R15 ; /* 0x0000000f00037306 */
/* 0x001e240000201400 */
/*0b40*/ FADD R3, R3, R16 ; /* 0x0000001003037221 */
/* 0x001fcc0000000000 */
/*0b50*/ F2I.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e30000020f100 */
/*0b60*/ I2F R6, R3 ; /* 0x0000000300067306 */
/* 0x001e240000201400 */
/*0b70*/ FADD R6, R6, R17 ; /* 0x0000001106067221 */
/* 0x001fcc0000000000 */
/*0b80*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e30000020f100 */
/*0b90*/ I2F R5, R6 ; /* 0x0000000600057306 */
/* 0x001e240000201400 */
/*0ba0*/ FADD R5, R5, R4 ; /* 0x0000000405057221 */
/* 0x001fe20000000000 */
/*0bb0*/ IADD3 R4, R11, R14, R11 ; /* 0x0000000e0b047210 */
/* 0x000fca0007ffe00b */
/*0bc0*/ F2I.TRUNC.NTZ R24, R5 ; /* 0x0000000500187305 */
/* 0x000062000020f100 */
/*0bd0*/ IADD3 R4, R11, R4, R11 ; /* 0x000000040b047210 */
/* 0x000fce0007ffe00b */
/*0be0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0bf0*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0c00*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*0c10*/ @!P0 BRA 0xdd0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0c20*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0c30*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*0c40*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fca00078e0203 */
/*0c50*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0c60*/ IMAD.WIDE R6, R11, 0x4, R2 ; /* 0x000000040b067825 */
/* 0x000fca00078e0202 */
/*0c70*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ee2000c1e1900 */
/*0c80*/ IMAD.WIDE R12, R11, 0x4, R6 ; /* 0x000000040b0c7825 */
/* 0x000fca00078e0206 */
/*0c90*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000f22000c1e1900 */
/*0ca0*/ IMAD.WIDE R14, R11, 0x4, R12 ; /* 0x000000040b0e7825 */
/* 0x000fcc00078e020c */
/*0cb0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f62000c1e1900 */
/*0cc0*/ I2F R24, R24 ; /* 0x0000001800187306 */
/* 0x002ea20000201400 */
/*0cd0*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe40007ffe0ff */
/*0ce0*/ IADD3 R4, R11.reuse, R4, R11.reuse ; /* 0x000000040b047210 */
/* 0x140fe40007ffe00b */
/*0cf0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0d00*/ IADD3 R4, R11, R4, R11 ; /* 0x000000040b047210 */
/* 0x000fe20007ffe00b */
/*0d10*/ FADD R5, R5, R24 ; /* 0x0000001805057221 */
/* 0x004fcc0000000000 */
/*0d20*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e30000020f100 */
/*0d30*/ I2F R16, R5 ; /* 0x0000000500107306 */
/* 0x001ee40000201400 */
/*0d40*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x008fcc0000000000 */
/*0d50*/ F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000107305 */
/* 0x000e30000020f100 */
/*0d60*/ I2F R2, R16 ; /* 0x0000001000027306 */
/* 0x001f240000201400 */
/*0d70*/ FADD R2, R2, R19 ; /* 0x0000001302027221 */
/* 0x010fcc0000000000 */
/*0d80*/ F2I.TRUNC.NTZ R2, R2 ; /* 0x0000000200027305 */
/* 0x000e30000020f100 */
/*0d90*/ I2F R3, R2 ; /* 0x0000000200037306 */
/* 0x001f640000201400 */
/*0da0*/ FADD R3, R3, R14 ; /* 0x0000000e03037221 */
/* 0x020fcc0000000000 */
/*0db0*/ F2I.TRUNC.NTZ R24, R3 ; /* 0x0000000300187305 */
/* 0x000062000020f100 */
/*0dc0*/ @P0 BRA 0xc30 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0dd0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0de0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*0df0*/ @!P0 BRA 0xea0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0e00*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x001fca0000000f00 */
/*0e10*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0e20*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x0010a2000c1e1900 */
/*0e30*/ I2F R3, R24 ; /* 0x0000001800037306 */
/* 0x002ea20000201400 */
/*0e40*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fc80007ffe0ff */
/*0e50*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0e60*/ IMAD.WIDE R4, R11, 0x4, R4 ; /* 0x000000040b047825 */
/* 0x001fc800078e0204 */
/*0e70*/ FADD R2, R2, R3 ; /* 0x0000000302027221 */
/* 0x004fc80000000000 */
/*0e80*/ F2I.TRUNC.NTZ R24, R2 ; /* 0x0000000200187305 */
/* 0x000068000020f100 */
/*0e90*/ @P0 BRA 0xe20 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0ea0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0eb0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0ec0*/ ISETP.GT.U32.AND P1, PT, R9.reuse, 0xff, PT ; /* 0x000000ff0900780c */
/* 0x040fe20003f24070 */
/*0ed0*/ STS [R9.X4], R24 ; /* 0x0000001809007388 */
/* 0x0023e80000004800 */
/*0ee0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0ef0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fce0003f05270 */
/*0f00*/ @P1 BRA 0x1000 ; /* 0x000000f000001947 */
/* 0x000fec0003800000 */
/*0f10*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.52587890625e-05 ; /* 0x00000100ff037435 */
/* 0x003fe200000001ff */
/*0f20*/ IMAD.SHL.U32 R2, R9, 0x4, RZ ; /* 0x0000000409027824 */
/* 0x000fd200078e00ff */
/*0f30*/ SHF.R.U32.HI R8, RZ, 0x1, R3 ; /* 0x00000001ff087819 */
/* 0x000fe20000011603 */
/*0f40*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*0f50*/ ISETP.GE.U32.AND P1, PT, R9.reuse, R8.reuse, PT ; /* 0x000000080900720c */
/* 0x0c0fe40003f26070 */
/*0f60*/ ISETP.LT.U32.AND P2, PT, R9, R8, PT ; /* 0x000000080900720c */
/* 0x000fd60003f41070 */
/*0f70*/ @!P1 LEA R4, R8, R2, 0x2 ; /* 0x0000000208049211 */
/* 0x000fe200078e10ff */
/*0f80*/ @!P1 LDS R5, [R9.X4] ; /* 0x0000000009059984 */
/* 0x000fea0000004800 */
/*0f90*/ @!P1 LDS R4, [R4] ; /* 0x0000000004049984 */
/* 0x000e240000000800 */
/*0fa0*/ @!P1 IADD3 R6, R5, R4, RZ ; /* 0x0000000405069210 */
/* 0x001fca0007ffe0ff */
/*0fb0*/ @!P1 STS [R9.X4], R6 ; /* 0x0000000609009388 */
/* 0x0001e80000004800 */
/*0fc0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0fd0*/ ISETP.GT.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f24070 */
/*0fe0*/ MOV R3, R8 ; /* 0x0000000800037202 */
/* 0x000fd60000000f00 */
/*0ff0*/ @P1 BRA P2, 0xf30 ; /* 0xffffff3000001947 */
/* 0x001fea000103ffff */
/*1000*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x002fea0003800000 */
/*1010*/ LDS R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e620000000800 */
/*1020*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x001fca0000000f00 */
/*1030*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe200078e0003 */
/*1040*/ I2F R5, R4 ; /* 0x0000000400057306 */
/* 0x002e280000201400 */
/*1050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*1060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1070*/ BRA 0x1070; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9add_arrayPfS_
.globl _Z9add_arrayPfS_
.p2align 8
.type _Z9add_arrayPfS_,@function
_Z9add_arrayPfS_:
s_mov_b32 s4, s15
v_mov_b32_e32 v4, 0
v_lshl_add_u32 v1, s4, 8, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x10000, v1
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b32 s2, s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 0
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_lshl_b32 s6, s2, 8
v_add_co_u32 v2, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[8:9], s[6:7], 2
.LBB0_2:
global_load_b32 v5, v[2:3], off
v_cvt_f32_i32_e32 v4, v4
v_add_nc_u32_e32 v1, s6, v1
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v5, v4
v_cmp_lt_i32_e64 s2, 0xffff, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e32 v4, v4
s_or_b32 s5, s2, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_lshlrev_b32_e32 v1, 2, v0
s_movk_i32 s2, 0x100
s_mov_b32 s3, exec_lo
ds_store_b32 v1, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB0_9
v_max_u32_e32 v2, 1, v0
s_mov_b32 s5, 0
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s6
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_9
.LBB0_7:
s_lshr_b32 s2, s2, 1
s_mov_b32 s6, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v3, s2, v0, 2
ds_load_b32 v3, v3
ds_load_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
ds_store_b32 v1, v3
s_branch .LBB0_6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_cvt_f32_i32_e32 v1, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9add_arrayPfS_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9add_arrayPfS_, .Lfunc_end0-_Z9add_arrayPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9add_arrayPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9add_arrayPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000867b2_00000000-6_p2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10init_arrayPf
.type _Z10init_arrayPf, @function
_Z10init_arrayPf:
.LFB3669:
.cfi_startproc
endbr64
leaq 262144(%rdi), %rax
movss .LC0(%rip), %xmm0
.L4:
movss %xmm0, (%rdi)
addq $4, %rdi
cmpq %rax, %rdi
jne .L4
ret
.cfi_endproc
.LFE3669:
.size _Z10init_arrayPf, .-_Z10init_arrayPf
.globl _Z30__device_stub__Z9add_arrayPfS_PfS_
.type _Z30__device_stub__Z9add_arrayPfS_PfS_, @function
_Z30__device_stub__Z9add_arrayPfS_PfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9add_arrayPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z30__device_stub__Z9add_arrayPfS_PfS_, .-_Z30__device_stub__Z9add_arrayPfS_PfS_
.globl _Z9add_arrayPfS_
.type _Z9add_arrayPfS_, @function
_Z9add_arrayPfS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9add_arrayPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9add_arrayPfS_, .-_Z9add_arrayPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Final Sum : "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $262144, %edi
call _Znam@PLT
movq %rax, %rbp
movl $512, %edi
call _Znam@PLT
movq %rax, %rbx
movq %rbp, %rdi
call _Z10init_arrayPf
leaq 16(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $262144, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $128, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L15:
movl $2, %ecx
movl $512, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 512(%rbx), %rdx
movl $0x00000000, 12(%rsp)
.L16:
movss 12(%rsp), %xmm1
addss (%rax), %xmm1
movss %xmm1, 12(%rsp)
addq $4, %rax
cmpq %rdx, %rax
jne .L16
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z9add_arrayPfS_PfS_
jmp .L15
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9add_arrayPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9add_arrayPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "p2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__add_arrayPfS_ # -- Begin function _Z24__device_stub__add_arrayPfS_
.p2align 4, 0x90
.type _Z24__device_stub__add_arrayPfS_,@function
_Z24__device_stub__add_arrayPfS_: # @_Z24__device_stub__add_arrayPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9add_arrayPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__add_arrayPfS_, .Lfunc_end0-_Z24__device_stub__add_arrayPfS_
.cfi_endproc
# -- End function
.globl _Z10init_arrayPf # -- Begin function _Z10init_arrayPf
.p2align 4, 0x90
.type _Z10init_arrayPf,@function
_Z10init_arrayPf: # @_Z10init_arrayPf
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rdi,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z10init_arrayPf, .Lfunc_end1-_Z10init_arrayPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $262144, %edi # imm = 0x40000
callq _Znam
movq %rax, %rbx
movl $512, %edi # imm = 0x200
callq _Znam
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB2_1
# %bb.2: # %_Z10init_arrayPf.exit
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
movq 16(%rsp), %rdi
movl $262144, %edx # imm = 0x40000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movabsq $4294967424, %rdi # imm = 0x100000080
leaq 128(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9add_arrayPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
addss (%r14,%rax,4), %xmm0
incq %rax
cmpq $128, %rax
jne .LBB2_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $12, %edx
movss %xmm0, 28(%rsp) # 4-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 28(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB2_9
# %bb.8:
movzbl 67(%r15), %ecx
jmp .LBB2_10
.LBB2_9:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9add_arrayPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9add_arrayPfS_,@object # @_Z9add_arrayPfS_
.section .rodata,"a",@progbits
.globl _Z9add_arrayPfS_
.p2align 3, 0x0
_Z9add_arrayPfS_:
.quad _Z24__device_stub__add_arrayPfS_
.size _Z9add_arrayPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Final Sum : "
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9add_arrayPfS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__add_arrayPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9add_arrayPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/* File: wtime.c */
/* Description: a timer that reports the current wall time */
/* */
/* Author: Wei-keng Liao */
/* ECE Department Northwestern University */
/* email: wkliao@ece.northwestern.edu */
/* Copyright, 2005, Wei-keng Liao */
/* */
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
#include <sys/time.h>
#include <stdio.h>
#include <stdlib.h>
double wtime(void)
{
double now_time;
struct timeval etstart;
struct timezone tzp;
if (gettimeofday(&etstart, &tzp) == -1)
perror("Error: calling gettimeofday() not successful.\n");
now_time = ((double)etstart.tv_sec) + /* in seconds */
((double)etstart.tv_usec) / 1000000.0; /* in microseconds */
return now_time;
}
#ifdef _TESTING_
int main(int argc, char **argv) {
double time;
time = wtime();
printf("time of day = %10.4f\n", time);
return 0;
}
#endif | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/* File: wtime.c */
/* Description: a timer that reports the current wall time */
/* */
/* Author: Wei-keng Liao */
/* ECE Department Northwestern University */
/* email: wkliao@ece.northwestern.edu */
/* Copyright, 2005, Wei-keng Liao */
/* */
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
#include <sys/time.h>
#include <stdio.h>
#include <stdlib.h>
double wtime(void)
{
double now_time;
struct timeval etstart;
struct timezone tzp;
if (gettimeofday(&etstart, &tzp) == -1)
perror("Error: calling gettimeofday() not successful.\n");
now_time = ((double)etstart.tv_sec) + /* in seconds */
((double)etstart.tv_usec) / 1000000.0; /* in microseconds */
return now_time;
}
#ifdef _TESTING_
int main(int argc, char **argv) {
double time;
time = wtime();
printf("time of day = %10.4f\n", time);
return 0;
}
#endif | .file "tmpxft_0002dd63_00000000-6_cuda_wtime.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error: calling gettimeofday() not successful.\n"
.text
.globl _Z5wtimev
.type _Z5wtimev, @function
_Z5wtimev:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
cmpl $-1, %eax
je .L7
.L4:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
divsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
leaq .LC0(%rip), %rdi
call perror@PLT
jmp .L4
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z5wtimev, .-_Z5wtimev
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/* File: wtime.c */
/* Description: a timer that reports the current wall time */
/* */
/* Author: Wei-keng Liao */
/* ECE Department Northwestern University */
/* email: wkliao@ece.northwestern.edu */
/* Copyright, 2005, Wei-keng Liao */
/* */
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
#include <sys/time.h>
#include <stdio.h>
#include <stdlib.h>
double wtime(void)
{
double now_time;
struct timeval etstart;
struct timezone tzp;
if (gettimeofday(&etstart, &tzp) == -1)
perror("Error: calling gettimeofday() not successful.\n");
now_time = ((double)etstart.tv_sec) + /* in seconds */
((double)etstart.tv_usec) / 1000000.0; /* in microseconds */
return now_time;
}
#ifdef _TESTING_
int main(int argc, char **argv) {
double time;
time = wtime();
printf("time of day = %10.4f\n", time);
return 0;
}
#endif | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/* File: wtime.c */
/* Description: a timer that reports the current wall time */
/* */
/* Author: Wei-keng Liao */
/* ECE Department Northwestern University */
/* email: wkliao@ece.northwestern.edu */
/* Copyright, 2005, Wei-keng Liao */
/* */
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <stdio.h>
#include <stdlib.h>
double wtime(void)
{
double now_time;
struct timeval etstart;
struct timezone tzp;
if (gettimeofday(&etstart, &tzp) == -1)
perror("Error: calling gettimeofday() not successful.\n");
now_time = ((double)etstart.tv_sec) + /* in seconds */
((double)etstart.tv_usec) / 1000000.0; /* in microseconds */
return now_time;
}
#ifdef _TESTING_
int main(int argc, char **argv) {
double time;
time = wtime();
printf("time of day = %10.4f\n", time);
return 0;
}
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/* File: wtime.c */
/* Description: a timer that reports the current wall time */
/* */
/* Author: Wei-keng Liao */
/* ECE Department Northwestern University */
/* email: wkliao@ece.northwestern.edu */
/* Copyright, 2005, Wei-keng Liao */
/* */
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <stdio.h>
#include <stdlib.h>
double wtime(void)
{
double now_time;
struct timeval etstart;
struct timezone tzp;
if (gettimeofday(&etstart, &tzp) == -1)
perror("Error: calling gettimeofday() not successful.\n");
now_time = ((double)etstart.tv_sec) + /* in seconds */
((double)etstart.tv_usec) / 1000000.0; /* in microseconds */
return now_time;
}
#ifdef _TESTING_
int main(int argc, char **argv) {
double time;
time = wtime();
printf("time of day = %10.4f\n", time);
return 0;
}
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/* File: wtime.c */
/* Description: a timer that reports the current wall time */
/* */
/* Author: Wei-keng Liao */
/* ECE Department Northwestern University */
/* email: wkliao@ece.northwestern.edu */
/* Copyright, 2005, Wei-keng Liao */
/* */
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <stdio.h>
#include <stdlib.h>
double wtime(void)
{
double now_time;
struct timeval etstart;
struct timezone tzp;
if (gettimeofday(&etstart, &tzp) == -1)
perror("Error: calling gettimeofday() not successful.\n");
now_time = ((double)etstart.tv_sec) + /* in seconds */
((double)etstart.tv_usec) / 1000000.0; /* in microseconds */
return now_time;
}
#ifdef _TESTING_
int main(int argc, char **argv) {
double time;
time = wtime();
printf("time of day = %10.4f\n", time);
return 0;
}
#endif | .text
.file "cuda_wtime.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5wtimev
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z5wtimev
.p2align 4, 0x90
.type _Z5wtimev,@function
_Z5wtimev: # @_Z5wtimev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
cmpl $-1, %eax
je .LBB0_1
.LBB0_2:
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 32
movl $.L.str, %edi
callq perror
jmp .LBB0_2
.Lfunc_end0:
.size _Z5wtimev, .Lfunc_end0-_Z5wtimev
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: calling gettimeofday() not successful.\n"
.size .L.str, 47
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002dd63_00000000-6_cuda_wtime.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error: calling gettimeofday() not successful.\n"
.text
.globl _Z5wtimev
.type _Z5wtimev, @function
_Z5wtimev:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
cmpl $-1, %eax
je .L7
.L4:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
divsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
leaq .LC0(%rip), %rdi
call perror@PLT
jmp .L4
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z5wtimev, .-_Z5wtimev
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_wtime.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5wtimev
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z5wtimev
.p2align 4, 0x90
.type _Z5wtimev,@function
_Z5wtimev: # @_Z5wtimev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
cmpl $-1, %eax
je .LBB0_1
.LBB0_2:
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 32
movl $.L.str, %edi
callq perror
jmp .LBB0_2
.Lfunc_end0:
.size _Z5wtimev, .Lfunc_end0-_Z5wtimev
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: calling gettimeofday() not successful.\n"
.size .L.str, 47
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void add_kernel(int *x, int a, int b) {
x[0] = a + b;
}
void add(int *x, int a, int b) {
add_kernel<<<1, 1>>>(x, a, b);
} | code for sm_80
Function : _Z10add_kernelPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x168], RZ ; /* 0x00005a0005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void add_kernel(int *x, int a, int b) {
x[0] = a + b;
}
void add(int *x, int a, int b) {
add_kernel<<<1, 1>>>(x, a, b);
} | .file "tmpxft_000b6baa_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10add_kernelPiiiPiii
.type _Z32__device_stub__Z10add_kernelPiiiPiii, @function
_Z32__device_stub__Z10add_kernelPiiiPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10add_kernelPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z32__device_stub__Z10add_kernelPiiiPiii, .-_Z32__device_stub__Z10add_kernelPiiiPiii
.globl _Z10add_kernelPiii
.type _Z10add_kernelPiii, @function
_Z10add_kernelPiii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10add_kernelPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10add_kernelPiii, .-_Z10add_kernelPiii
.globl _Z3addPiii
.type _Z3addPiii, @function
_Z3addPiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movl %esi, %ebp
movl %edx, %r12d
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %r12d, %edx
movl %ebp, %esi
movq %rbx, %rdi
call _Z32__device_stub__Z10add_kernelPiiiPiii
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z3addPiii, .-_Z3addPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10add_kernelPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_kernelPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void add_kernel(int *x, int a, int b) {
x[0] = a + b;
}
void add(int *x, int a, int b) {
add_kernel<<<1, 1>>>(x, a, b);
} | #include <hip/hip_runtime.h>
__global__ void add_kernel(int *x, int a, int b) {
x[0] = a + b;
}
void add(int *x, int a, int b) {
add_kernel<<<1, 1>>>(x, a, b);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void add_kernel(int *x, int a, int b) {
x[0] = a + b;
}
void add(int *x, int a, int b) {
add_kernel<<<1, 1>>>(x, a, b);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_kernelPiii
.globl _Z10add_kernelPiii
.p2align 8
.type _Z10add_kernelPiii,@function
_Z10add_kernelPiii:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_kernelPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_kernelPiii, .Lfunc_end0-_Z10add_kernelPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_kernelPiii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z10add_kernelPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void add_kernel(int *x, int a, int b) {
x[0] = a + b;
}
void add(int *x, int a, int b) {
add_kernel<<<1, 1>>>(x, a, b);
} | .text
.file "add.hip"
.globl _Z25__device_stub__add_kernelPiii # -- Begin function _Z25__device_stub__add_kernelPiii
.p2align 4, 0x90
.type _Z25__device_stub__add_kernelPiii,@function
_Z25__device_stub__add_kernelPiii: # @_Z25__device_stub__add_kernelPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10add_kernelPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__add_kernelPiii, .Lfunc_end0-_Z25__device_stub__add_kernelPiii
.cfi_endproc
# -- End function
.globl _Z3addPiii # -- Begin function _Z3addPiii
.p2align 4, 0x90
.type _Z3addPiii,@function
_Z3addPiii: # @_Z3addPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r14, 56(%rsp)
movl %ebp, 4(%rsp)
movl %ebx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10add_kernelPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z3addPiii, .Lfunc_end1-_Z3addPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_kernelPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10add_kernelPiii,@object # @_Z10add_kernelPiii
.section .rodata,"a",@progbits
.globl _Z10add_kernelPiii
.p2align 3, 0x0
_Z10add_kernelPiii:
.quad _Z25__device_stub__add_kernelPiii
.size _Z10add_kernelPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10add_kernelPiii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add_kernelPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10add_kernelPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10add_kernelPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x168], RZ ; /* 0x00005a0005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_kernelPiii
.globl _Z10add_kernelPiii
.p2align 8
.type _Z10add_kernelPiii,@function
_Z10add_kernelPiii:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_kernelPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_kernelPiii, .Lfunc_end0-_Z10add_kernelPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_kernelPiii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z10add_kernelPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b6baa_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10add_kernelPiiiPiii
.type _Z32__device_stub__Z10add_kernelPiiiPiii, @function
_Z32__device_stub__Z10add_kernelPiiiPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10add_kernelPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z32__device_stub__Z10add_kernelPiiiPiii, .-_Z32__device_stub__Z10add_kernelPiiiPiii
.globl _Z10add_kernelPiii
.type _Z10add_kernelPiii, @function
_Z10add_kernelPiii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10add_kernelPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10add_kernelPiii, .-_Z10add_kernelPiii
.globl _Z3addPiii
.type _Z3addPiii, @function
_Z3addPiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movl %esi, %ebp
movl %edx, %r12d
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %r12d, %edx
movl %ebp, %esi
movq %rbx, %rdi
call _Z32__device_stub__Z10add_kernelPiiiPiii
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z3addPiii, .-_Z3addPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10add_kernelPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_kernelPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z25__device_stub__add_kernelPiii # -- Begin function _Z25__device_stub__add_kernelPiii
.p2align 4, 0x90
.type _Z25__device_stub__add_kernelPiii,@function
_Z25__device_stub__add_kernelPiii: # @_Z25__device_stub__add_kernelPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10add_kernelPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__add_kernelPiii, .Lfunc_end0-_Z25__device_stub__add_kernelPiii
.cfi_endproc
# -- End function
.globl _Z3addPiii # -- Begin function _Z3addPiii
.p2align 4, 0x90
.type _Z3addPiii,@function
_Z3addPiii: # @_Z3addPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r14, 56(%rsp)
movl %ebp, 4(%rsp)
movl %ebx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10add_kernelPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z3addPiii, .Lfunc_end1-_Z3addPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_kernelPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10add_kernelPiii,@object # @_Z10add_kernelPiii
.section .rodata,"a",@progbits
.globl _Z10add_kernelPiii
.p2align 3, 0x0
_Z10add_kernelPiii:
.quad _Z25__device_stub__add_kernelPiii
.size _Z10add_kernelPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10add_kernelPiii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add_kernelPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10add_kernelPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cufft.h>
#include <stdio.h>
void cufft_check_error(const char* file_name, const int line_number, cufftResult result)
{
if (result == CUFFT_SUCCESS) return;
printf("CUFFT error at line %i of file %s: ", line_number, file_name);
switch (result)
{
case CUFFT_INVALID_PLAN:
{
printf("CUFFT_INVALID_PLAN\n");
break;
}
case CUFFT_ALLOC_FAILED:
{
printf("CUFFT_ALLOC_FAILED\n");
break;
}
case CUFFT_INVALID_VALUE:
{
printf("CUFFT_INVALID_VALUE\n");
break;
}
case CUFFT_INTERNAL_ERROR:
{
printf("CUFFT_INTERNAL_ERROR\n");
break;
}
case CUFFT_SETUP_FAILED:
{
printf("CUFFT_SETUP_FAILED\n");
break;
}
case CUFFT_INVALID_SIZE:
{
printf("CUFFT_INVALID_SIZE\n");
break;
}
default:
{
printf("unknown error code %i\n", result);
break;
}
}
}
int main(int argn, char** argv)
{
cuInit(0);
cufftHandle plan;
cufftResult result = cufftCreate(&plan);
cufft_check_error(__FILE__, __LINE__, result);
int nfft = 4;
int n[] = {100, 100, 100};
int fft_size = n[0] * n[1] * n[2];
size_t work_size;
//result = cufftGetSizeMany(plan, 3, n, n, 1, fft_size, n, 1, fft_size, CUFFT_Z2Z, nfft, &work_size);
//result = cufftGetSizeMany(plan, 3, n, NULL, 1, fft_size, NULL, 1, fft_size, CUFFT_Z2Z, nfft, &work_size);
result = cufftEstimateMany(3, n, NULL, 1, fft_size, NULL, 1, fft_size, CUFFT_Z2Z, nfft, &work_size);
cufft_check_error(__FILE__, __LINE__, result);
printf("FFT size: %i\n", fft_size);
printf("number of FFTs: %i\n", nfft);
printf("estimated work size: %li\n", work_size);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cufft.h>
#include <stdio.h>
void cufft_check_error(const char* file_name, const int line_number, cufftResult result)
{
if (result == CUFFT_SUCCESS) return;
printf("CUFFT error at line %i of file %s: ", line_number, file_name);
switch (result)
{
case CUFFT_INVALID_PLAN:
{
printf("CUFFT_INVALID_PLAN\n");
break;
}
case CUFFT_ALLOC_FAILED:
{
printf("CUFFT_ALLOC_FAILED\n");
break;
}
case CUFFT_INVALID_VALUE:
{
printf("CUFFT_INVALID_VALUE\n");
break;
}
case CUFFT_INTERNAL_ERROR:
{
printf("CUFFT_INTERNAL_ERROR\n");
break;
}
case CUFFT_SETUP_FAILED:
{
printf("CUFFT_SETUP_FAILED\n");
break;
}
case CUFFT_INVALID_SIZE:
{
printf("CUFFT_INVALID_SIZE\n");
break;
}
default:
{
printf("unknown error code %i\n", result);
break;
}
}
}
int main(int argn, char** argv)
{
cuInit(0);
cufftHandle plan;
cufftResult result = cufftCreate(&plan);
cufft_check_error(__FILE__, __LINE__, result);
int nfft = 4;
int n[] = {100, 100, 100};
int fft_size = n[0] * n[1] * n[2];
size_t work_size;
//result = cufftGetSizeMany(plan, 3, n, n, 1, fft_size, n, 1, fft_size, CUFFT_Z2Z, nfft, &work_size);
//result = cufftGetSizeMany(plan, 3, n, NULL, 1, fft_size, NULL, 1, fft_size, CUFFT_Z2Z, nfft, &work_size);
result = cufftEstimateMany(3, n, NULL, 1, fft_size, NULL, 1, fft_size, CUFFT_Z2Z, nfft, &work_size);
cufft_check_error(__FILE__, __LINE__, result);
printf("FFT size: %i\n", fft_size);
printf("number of FFTs: %i\n", nfft);
printf("estimated work size: %li\n", work_size);
} | .file "tmpxft_000479c3_00000000-6_test_cufftGetSizeMany.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "CUFFT error at line %i of file %s: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CUFFT_INVALID_PLAN\n"
.LC2:
.string "CUFFT_ALLOC_FAILED\n"
.LC3:
.string "CUFFT_INVALID_VALUE\n"
.LC4:
.string "CUFFT_INTERNAL_ERROR\n"
.LC5:
.string "CUFFT_SETUP_FAILED\n"
.LC6:
.string "CUFFT_INVALID_SIZE\n"
.LC7:
.string "unknown error code %i\n"
.text
.globl _Z17cufft_check_errorPKci13cufftResult_t
.type _Z17cufft_check_errorPKci13cufftResult_t, @function
_Z17cufft_check_errorPKci13cufftResult_t:
.LFB2080:
.cfi_startproc
endbr64
testl %edx, %edx
jne .L17
ret
.L17:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edx, %ebx
movq %rdi, %rcx
movl %esi, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $8, %ebx
ja .L5
movl %ebx, %eax
leaq .L7(%rip), %rdx
movslq (%rdx,%rax,4), %rax
addq %rdx, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L7:
.long .L5-.L7
.long .L12-.L7
.long .L11-.L7
.long .L5-.L7
.long .L10-.L7
.long .L9-.L7
.long .L5-.L7
.long .L8-.L7
.long .L6-.L7
.text
.L12:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L10:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L9:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L8:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L6:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L5:
movl %ebx, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.cfi_endproc
.LFE2080:
.size _Z17cufft_check_errorPKci13cufftResult_t, .-_Z17cufft_check_errorPKci13cufftResult_t
.section .rodata.str1.8
.align 8
.LC8:
.string "/home/ubuntu/Datasets/stackv2/train-structured/toxa81/testing/master/cufftGetSizeMany/test_cufftGetSizeMany.cu"
.section .rodata.str1.1
.LC9:
.string "FFT size: %i\n"
.LC10:
.string "number of FFTs: %i\n"
.LC11:
.string "estimated work size: %li\n"
.text
.globl main
.type main, @function
main:
.LFB2081:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call cuInit@PLT
leaq 12(%rsp), %rdi
call cufftCreate@PLT
movl %eax, %edx
movl $57, %esi
leaq .LC8(%rip), %rbx
movq %rbx, %rdi
call _Z17cufft_check_errorPKci13cufftResult_t
movl $100, 28(%rsp)
movl $100, 32(%rsp)
movl $100, 36(%rsp)
leaq 28(%rsp), %rsi
subq $8, %rsp
.cfi_def_cfa_offset 72
leaq 24(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 80
pushq $4
.cfi_def_cfa_offset 88
pushq $105
.cfi_def_cfa_offset 96
pushq $1000000
.cfi_def_cfa_offset 104
pushq $1
.cfi_def_cfa_offset 112
movl $0, %r9d
movl $1000000, %r8d
movl $1, %ecx
movl $0, %edx
movl $3, %edi
call cufftEstimateMany@PLT
movl %eax, %edx
addq $48, %rsp
.cfi_def_cfa_offset 64
movl $66, %esi
movq %rbx, %rdi
call _Z17cufft_check_errorPKci13cufftResult_t
movl $1000000, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cufft.h>
#include <stdio.h>
void cufft_check_error(const char* file_name, const int line_number, cufftResult result)
{
if (result == CUFFT_SUCCESS) return;
printf("CUFFT error at line %i of file %s: ", line_number, file_name);
switch (result)
{
case CUFFT_INVALID_PLAN:
{
printf("CUFFT_INVALID_PLAN\n");
break;
}
case CUFFT_ALLOC_FAILED:
{
printf("CUFFT_ALLOC_FAILED\n");
break;
}
case CUFFT_INVALID_VALUE:
{
printf("CUFFT_INVALID_VALUE\n");
break;
}
case CUFFT_INTERNAL_ERROR:
{
printf("CUFFT_INTERNAL_ERROR\n");
break;
}
case CUFFT_SETUP_FAILED:
{
printf("CUFFT_SETUP_FAILED\n");
break;
}
case CUFFT_INVALID_SIZE:
{
printf("CUFFT_INVALID_SIZE\n");
break;
}
default:
{
printf("unknown error code %i\n", result);
break;
}
}
}
int main(int argn, char** argv)
{
cuInit(0);
cufftHandle plan;
cufftResult result = cufftCreate(&plan);
cufft_check_error(__FILE__, __LINE__, result);
int nfft = 4;
int n[] = {100, 100, 100};
int fft_size = n[0] * n[1] * n[2];
size_t work_size;
//result = cufftGetSizeMany(plan, 3, n, n, 1, fft_size, n, 1, fft_size, CUFFT_Z2Z, nfft, &work_size);
//result = cufftGetSizeMany(plan, 3, n, NULL, 1, fft_size, NULL, 1, fft_size, CUFFT_Z2Z, nfft, &work_size);
result = cufftEstimateMany(3, n, NULL, 1, fft_size, NULL, 1, fft_size, CUFFT_Z2Z, nfft, &work_size);
cufft_check_error(__FILE__, __LINE__, result);
printf("FFT size: %i\n", fft_size);
printf("number of FFTs: %i\n", nfft);
printf("estimated work size: %li\n", work_size);
} | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <stdio.h>
void cufft_check_error(const char* file_name, const int line_number, hipfftResult result)
{
if (result == HIPFFT_SUCCESS) return;
printf("CUFFT error at line %i of file %s: ", line_number, file_name);
switch (result)
{
case HIPFFT_INVALID_PLAN:
{
printf("CUFFT_INVALID_PLAN\n");
break;
}
case HIPFFT_ALLOC_FAILED:
{
printf("CUFFT_ALLOC_FAILED\n");
break;
}
case HIPFFT_INVALID_VALUE:
{
printf("CUFFT_INVALID_VALUE\n");
break;
}
case HIPFFT_INTERNAL_ERROR:
{
printf("CUFFT_INTERNAL_ERROR\n");
break;
}
case HIPFFT_SETUP_FAILED:
{
printf("CUFFT_SETUP_FAILED\n");
break;
}
case HIPFFT_INVALID_SIZE:
{
printf("CUFFT_INVALID_SIZE\n");
break;
}
default:
{
printf("unknown error code %i\n", result);
break;
}
}
}
int main(int argn, char** argv)
{
hipInit(0);
hipfftHandle plan;
hipfftResult result = hipfftCreate(&plan);
cufft_check_error(__FILE__, __LINE__, result);
int nfft = 4;
int n[] = {100, 100, 100};
int fft_size = n[0] * n[1] * n[2];
size_t work_size;
//result = cufftGetSizeMany(plan, 3, n, n, 1, fft_size, n, 1, fft_size, CUFFT_Z2Z, nfft, &work_size);
//result = cufftGetSizeMany(plan, 3, n, NULL, 1, fft_size, NULL, 1, fft_size, CUFFT_Z2Z, nfft, &work_size);
result = hipfftEstimateMany(3, n, NULL, 1, fft_size, NULL, 1, fft_size, HIPFFT_Z2Z, nfft, &work_size);
cufft_check_error(__FILE__, __LINE__, result);
printf("FFT size: %i\n", fft_size);
printf("number of FFTs: %i\n", nfft);
printf("estimated work size: %li\n", work_size);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <stdio.h>
void cufft_check_error(const char* file_name, const int line_number, hipfftResult result)
{
if (result == HIPFFT_SUCCESS) return;
printf("CUFFT error at line %i of file %s: ", line_number, file_name);
switch (result)
{
case HIPFFT_INVALID_PLAN:
{
printf("CUFFT_INVALID_PLAN\n");
break;
}
case HIPFFT_ALLOC_FAILED:
{
printf("CUFFT_ALLOC_FAILED\n");
break;
}
case HIPFFT_INVALID_VALUE:
{
printf("CUFFT_INVALID_VALUE\n");
break;
}
case HIPFFT_INTERNAL_ERROR:
{
printf("CUFFT_INTERNAL_ERROR\n");
break;
}
case HIPFFT_SETUP_FAILED:
{
printf("CUFFT_SETUP_FAILED\n");
break;
}
case HIPFFT_INVALID_SIZE:
{
printf("CUFFT_INVALID_SIZE\n");
break;
}
default:
{
printf("unknown error code %i\n", result);
break;
}
}
}
int main(int argn, char** argv)
{
hipInit(0);
hipfftHandle plan;
hipfftResult result = hipfftCreate(&plan);
cufft_check_error(__FILE__, __LINE__, result);
int nfft = 4;
int n[] = {100, 100, 100};
int fft_size = n[0] * n[1] * n[2];
size_t work_size;
//result = cufftGetSizeMany(plan, 3, n, n, 1, fft_size, n, 1, fft_size, CUFFT_Z2Z, nfft, &work_size);
//result = cufftGetSizeMany(plan, 3, n, NULL, 1, fft_size, NULL, 1, fft_size, CUFFT_Z2Z, nfft, &work_size);
result = hipfftEstimateMany(3, n, NULL, 1, fft_size, NULL, 1, fft_size, HIPFFT_Z2Z, nfft, &work_size);
cufft_check_error(__FILE__, __LINE__, result);
printf("FFT size: %i\n", fft_size);
printf("number of FFTs: %i\n", nfft);
printf("estimated work size: %li\n", work_size);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <stdio.h>
void cufft_check_error(const char* file_name, const int line_number, hipfftResult result)
{
if (result == HIPFFT_SUCCESS) return;
printf("CUFFT error at line %i of file %s: ", line_number, file_name);
switch (result)
{
case HIPFFT_INVALID_PLAN:
{
printf("CUFFT_INVALID_PLAN\n");
break;
}
case HIPFFT_ALLOC_FAILED:
{
printf("CUFFT_ALLOC_FAILED\n");
break;
}
case HIPFFT_INVALID_VALUE:
{
printf("CUFFT_INVALID_VALUE\n");
break;
}
case HIPFFT_INTERNAL_ERROR:
{
printf("CUFFT_INTERNAL_ERROR\n");
break;
}
case HIPFFT_SETUP_FAILED:
{
printf("CUFFT_SETUP_FAILED\n");
break;
}
case HIPFFT_INVALID_SIZE:
{
printf("CUFFT_INVALID_SIZE\n");
break;
}
default:
{
printf("unknown error code %i\n", result);
break;
}
}
}
int main(int argn, char** argv)
{
hipInit(0);
hipfftHandle plan;
hipfftResult result = hipfftCreate(&plan);
cufft_check_error(__FILE__, __LINE__, result);
int nfft = 4;
int n[] = {100, 100, 100};
int fft_size = n[0] * n[1] * n[2];
size_t work_size;
//result = cufftGetSizeMany(plan, 3, n, n, 1, fft_size, n, 1, fft_size, CUFFT_Z2Z, nfft, &work_size);
//result = cufftGetSizeMany(plan, 3, n, NULL, 1, fft_size, NULL, 1, fft_size, CUFFT_Z2Z, nfft, &work_size);
result = hipfftEstimateMany(3, n, NULL, 1, fft_size, NULL, 1, fft_size, HIPFFT_Z2Z, nfft, &work_size);
cufft_check_error(__FILE__, __LINE__, result);
printf("FFT size: %i\n", fft_size);
printf("number of FFTs: %i\n", nfft);
printf("estimated work size: %li\n", work_size);
} | .text
.file "test_cufftGetSizeMany.hip"
.globl _Z17cufft_check_errorPKci14hipfftResult_t # -- Begin function _Z17cufft_check_errorPKci14hipfftResult_t
.p2align 4, 0x90
.type _Z17cufft_check_errorPKci14hipfftResult_t,@function
_Z17cufft_check_errorPKci14hipfftResult_t: # @_Z17cufft_check_errorPKci14hipfftResult_t
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edx, %ebx
testl %edx, %edx
je .LBB0_10
# %bb.1:
movq %rdi, %rdx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leal -1(%rbx), %eax
cmpl $7, %eax
ja .LBB0_9
# %bb.2:
jmpq *.LJTI0_0(,%rax,8)
.LBB0_3:
movl $.Lstr.5, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB0_10:
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 16
movl $.Lstr.3, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB0_8:
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB0_9:
.cfi_def_cfa_offset 16
movl $.L.str.7, %edi
movl %ebx, %esi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB0_4:
.cfi_def_cfa_offset 16
movl $.Lstr.4, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB0_6:
.cfi_def_cfa_offset 16
movl $.Lstr.2, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB0_7:
.cfi_def_cfa_offset 16
movl $.Lstr.1, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size _Z17cufft_check_errorPKci14hipfftResult_t, .Lfunc_end0-_Z17cufft_check_errorPKci14hipfftResult_t
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI0_0:
.quad .LBB0_3
.quad .LBB0_4
.quad .LBB0_9
.quad .LBB0_5
.quad .LBB0_6
.quad .LBB0_9
.quad .LBB0_7
.quad .LBB0_8
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
xorl %edi, %edi
callq hipInit
leaq 32(%rsp), %rdi
callq hipfftCreate
movl $.L.str.8, %edi
movl $57, %esi
movl %eax, %edx
callq _Z17cufft_check_errorPKci14hipfftResult_t
movabsq $429496729700, %rax # imm = 0x6400000064
movq %rax, 20(%rsp)
movl $100, 28(%rsp)
subq $8, %rsp
.cfi_adjust_cfa_offset 8
leaq 16(%rsp), %rax
leaq 28(%rsp), %rsi
movl $3, %edi
xorl %edx, %edx
movl $1, %ecx
movl $1000000, %r8d # imm = 0xF4240
xorl %r9d, %r9d
pushq %rax
.cfi_adjust_cfa_offset 8
pushq $4
.cfi_adjust_cfa_offset 8
pushq $105
.cfi_adjust_cfa_offset 8
pushq $1000000 # imm = 0xF4240
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq hipfftEstimateMany
addq $48, %rsp
.cfi_adjust_cfa_offset -48
movl $.L.str.8, %edi
movl $66, %esi
movl %eax, %edx
callq _Z17cufft_check_errorPKci14hipfftResult_t
movl $.L.str.9, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.10, %edi
movl $4, %esi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUFFT error at line %i of file %s: "
.size .L.str, 36
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "unknown error code %i\n"
.size .L.str.7, 23
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/toxa81/testing/master/cufftGetSizeMany/test_cufftGetSizeMany.hip"
.size .L.str.8, 122
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "FFT size: %i\n"
.size .L.str.9, 14
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "number of FFTs: %i\n"
.size .L.str.10, 20
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "estimated work size: %li\n"
.size .L.str.11, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "CUFFT_INVALID_SIZE"
.size .Lstr, 19
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "CUFFT_SETUP_FAILED"
.size .Lstr.1, 19
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "CUFFT_INTERNAL_ERROR"
.size .Lstr.2, 21
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "CUFFT_INVALID_VALUE"
.size .Lstr.3, 20
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "CUFFT_ALLOC_FAILED"
.size .Lstr.4, 19
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "CUFFT_INVALID_PLAN"
.size .Lstr.5, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000479c3_00000000-6_test_cufftGetSizeMany.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "CUFFT error at line %i of file %s: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CUFFT_INVALID_PLAN\n"
.LC2:
.string "CUFFT_ALLOC_FAILED\n"
.LC3:
.string "CUFFT_INVALID_VALUE\n"
.LC4:
.string "CUFFT_INTERNAL_ERROR\n"
.LC5:
.string "CUFFT_SETUP_FAILED\n"
.LC6:
.string "CUFFT_INVALID_SIZE\n"
.LC7:
.string "unknown error code %i\n"
.text
.globl _Z17cufft_check_errorPKci13cufftResult_t
.type _Z17cufft_check_errorPKci13cufftResult_t, @function
_Z17cufft_check_errorPKci13cufftResult_t:
.LFB2080:
.cfi_startproc
endbr64
testl %edx, %edx
jne .L17
ret
.L17:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edx, %ebx
movq %rdi, %rcx
movl %esi, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $8, %ebx
ja .L5
movl %ebx, %eax
leaq .L7(%rip), %rdx
movslq (%rdx,%rax,4), %rax
addq %rdx, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L7:
.long .L5-.L7
.long .L12-.L7
.long .L11-.L7
.long .L5-.L7
.long .L10-.L7
.long .L9-.L7
.long .L5-.L7
.long .L8-.L7
.long .L6-.L7
.text
.L12:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L10:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L9:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L8:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L6:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L5:
movl %ebx, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.cfi_endproc
.LFE2080:
.size _Z17cufft_check_errorPKci13cufftResult_t, .-_Z17cufft_check_errorPKci13cufftResult_t
.section .rodata.str1.8
.align 8
.LC8:
.string "/home/ubuntu/Datasets/stackv2/train-structured/toxa81/testing/master/cufftGetSizeMany/test_cufftGetSizeMany.cu"
.section .rodata.str1.1
.LC9:
.string "FFT size: %i\n"
.LC10:
.string "number of FFTs: %i\n"
.LC11:
.string "estimated work size: %li\n"
.text
.globl main
.type main, @function
main:
.LFB2081:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call cuInit@PLT
leaq 12(%rsp), %rdi
call cufftCreate@PLT
movl %eax, %edx
movl $57, %esi
leaq .LC8(%rip), %rbx
movq %rbx, %rdi
call _Z17cufft_check_errorPKci13cufftResult_t
movl $100, 28(%rsp)
movl $100, 32(%rsp)
movl $100, 36(%rsp)
leaq 28(%rsp), %rsi
subq $8, %rsp
.cfi_def_cfa_offset 72
leaq 24(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 80
pushq $4
.cfi_def_cfa_offset 88
pushq $105
.cfi_def_cfa_offset 96
pushq $1000000
.cfi_def_cfa_offset 104
pushq $1
.cfi_def_cfa_offset 112
movl $0, %r9d
movl $1000000, %r8d
movl $1, %ecx
movl $0, %edx
movl $3, %edi
call cufftEstimateMany@PLT
movl %eax, %edx
addq $48, %rsp
.cfi_def_cfa_offset 64
movl $66, %esi
movq %rbx, %rdi
call _Z17cufft_check_errorPKci13cufftResult_t
movl $1000000, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test_cufftGetSizeMany.hip"
.globl _Z17cufft_check_errorPKci14hipfftResult_t # -- Begin function _Z17cufft_check_errorPKci14hipfftResult_t
.p2align 4, 0x90
.type _Z17cufft_check_errorPKci14hipfftResult_t,@function
_Z17cufft_check_errorPKci14hipfftResult_t: # @_Z17cufft_check_errorPKci14hipfftResult_t
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edx, %ebx
testl %edx, %edx
je .LBB0_10
# %bb.1:
movq %rdi, %rdx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leal -1(%rbx), %eax
cmpl $7, %eax
ja .LBB0_9
# %bb.2:
jmpq *.LJTI0_0(,%rax,8)
.LBB0_3:
movl $.Lstr.5, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB0_10:
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 16
movl $.Lstr.3, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB0_8:
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB0_9:
.cfi_def_cfa_offset 16
movl $.L.str.7, %edi
movl %ebx, %esi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB0_4:
.cfi_def_cfa_offset 16
movl $.Lstr.4, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB0_6:
.cfi_def_cfa_offset 16
movl $.Lstr.2, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB0_7:
.cfi_def_cfa_offset 16
movl $.Lstr.1, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size _Z17cufft_check_errorPKci14hipfftResult_t, .Lfunc_end0-_Z17cufft_check_errorPKci14hipfftResult_t
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI0_0:
.quad .LBB0_3
.quad .LBB0_4
.quad .LBB0_9
.quad .LBB0_5
.quad .LBB0_6
.quad .LBB0_9
.quad .LBB0_7
.quad .LBB0_8
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
xorl %edi, %edi
callq hipInit
leaq 32(%rsp), %rdi
callq hipfftCreate
movl $.L.str.8, %edi
movl $57, %esi
movl %eax, %edx
callq _Z17cufft_check_errorPKci14hipfftResult_t
movabsq $429496729700, %rax # imm = 0x6400000064
movq %rax, 20(%rsp)
movl $100, 28(%rsp)
subq $8, %rsp
.cfi_adjust_cfa_offset 8
leaq 16(%rsp), %rax
leaq 28(%rsp), %rsi
movl $3, %edi
xorl %edx, %edx
movl $1, %ecx
movl $1000000, %r8d # imm = 0xF4240
xorl %r9d, %r9d
pushq %rax
.cfi_adjust_cfa_offset 8
pushq $4
.cfi_adjust_cfa_offset 8
pushq $105
.cfi_adjust_cfa_offset 8
pushq $1000000 # imm = 0xF4240
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq hipfftEstimateMany
addq $48, %rsp
.cfi_adjust_cfa_offset -48
movl $.L.str.8, %edi
movl $66, %esi
movl %eax, %edx
callq _Z17cufft_check_errorPKci14hipfftResult_t
movl $.L.str.9, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.10, %edi
movl $4, %esi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUFFT error at line %i of file %s: "
.size .L.str, 36
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "unknown error code %i\n"
.size .L.str.7, 23
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/toxa81/testing/master/cufftGetSizeMany/test_cufftGetSizeMany.hip"
.size .L.str.8, 122
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "FFT size: %i\n"
.size .L.str.9, 14
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "number of FFTs: %i\n"
.size .L.str.10, 20
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "estimated work size: %li\n"
.size .L.str.11, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "CUFFT_INVALID_SIZE"
.size .Lstr, 19
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "CUFFT_SETUP_FAILED"
.size .Lstr.1, 19
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "CUFFT_INTERNAL_ERROR"
.size .Lstr.2, 21
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "CUFFT_INVALID_VALUE"
.size .Lstr.3, 20
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "CUFFT_ALLOC_FAILED"
.size .Lstr.4, 19
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "CUFFT_INVALID_PLAN"
.size .Lstr.5, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Created 25-Jan-2014 by Daniel Margala (University of California, Irvine) <dmargala@uci.edu>
#include <iostream>
int main(int argc, char **argv) {
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
std::cout << "No CUDA GPU has been detected" << std::endl;
return -1;
}
else {
std::cout << "Number CUDA GPU devices detected: " << deviceCount << std::endl;
}
for (int dev = 0; dev < deviceCount; dev++) {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
std::cout << "Device " << dev << " name: " << deviceProp.name << std::endl;
std::cout << " Computational Capabilities: " << deviceProp.major << "." << deviceProp.minor << std::endl;
std::cout << " Maximum global memory size: " << deviceProp.totalGlobalMem << std::endl;
std::cout << " Maximum constant memory size: " << deviceProp.totalConstMem << std::endl;
std::cout << " Maximum shared memory size per block: " << deviceProp.sharedMemPerBlock << std::endl;
std::cout << " Maximum block dimensions: " << deviceProp.maxThreadsDim[0] << " x "
<< deviceProp.maxThreadsDim[1] << " x " << deviceProp.maxThreadsDim[2] << std::endl;
std::cout << " Maximum grid dimensions: " << deviceProp.maxGridSize[0] << " x "
<< deviceProp.maxGridSize[1] << " x " << deviceProp.maxGridSize[2] << std::endl;
std::cout << " Warp size: " << deviceProp.warpSize << std::endl;
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Created 25-Jan-2014 by Daniel Margala (University of California, Irvine) <dmargala@uci.edu>
#include <iostream>
int main(int argc, char **argv) {
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
std::cout << "No CUDA GPU has been detected" << std::endl;
return -1;
}
else {
std::cout << "Number CUDA GPU devices detected: " << deviceCount << std::endl;
}
for (int dev = 0; dev < deviceCount; dev++) {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
std::cout << "Device " << dev << " name: " << deviceProp.name << std::endl;
std::cout << " Computational Capabilities: " << deviceProp.major << "." << deviceProp.minor << std::endl;
std::cout << " Maximum global memory size: " << deviceProp.totalGlobalMem << std::endl;
std::cout << " Maximum constant memory size: " << deviceProp.totalConstMem << std::endl;
std::cout << " Maximum shared memory size per block: " << deviceProp.sharedMemPerBlock << std::endl;
std::cout << " Maximum block dimensions: " << deviceProp.maxThreadsDim[0] << " x "
<< deviceProp.maxThreadsDim[1] << " x " << deviceProp.maxThreadsDim[2] << std::endl;
std::cout << " Maximum grid dimensions: " << deviceProp.maxGridSize[0] << " x "
<< deviceProp.maxGridSize[1] << " x " << deviceProp.maxGridSize[2] << std::endl;
std::cout << " Warp size: " << deviceProp.warpSize << std::endl;
}
return 0;
} | .file "tmpxft_0009fc0c_00000000-6_deviceQuery.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "No CUDA GPU has been detected"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Number CUDA GPU devices detected: "
.section .rodata.str1.1
.LC2:
.string "Device "
.LC3:
.string " name: "
.LC4:
.string " Computational Capabilities: "
.LC5:
.string "."
.LC6:
.string " Maximum global memory size: "
.section .rodata.str1.8
.align 8
.LC7:
.string " Maximum constant memory size: "
.align 8
.LC8:
.string " Maximum shared memory size per block: "
.section .rodata.str1.1
.LC9:
.string " Maximum block dimensions: "
.LC10:
.string " x "
.LC11:
.string " Maximum grid dimensions: "
.LC12:
.string " Warp size: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
je .L43
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpl $0, 12(%rsp)
jle .L40
movl $0, %r12d
leaq .LC2(%rip), %r14
leaq _ZSt4cout(%rip), %rbx
leaq .LC3(%rip), %r13
jmp .L38
.L43:
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $-1, %eax
jmp .L3
.L53:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L44
call _ZSt16__throw_bad_castv@PLT
.L44:
call __stack_chk_fail@PLT
.L8:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L9
.L54:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L45
call _ZSt16__throw_bad_castv@PLT
.L45:
call __stack_chk_fail@PLT
.L12:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L13
.L55:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L46
call _ZSt16__throw_bad_castv@PLT
.L46:
call __stack_chk_fail@PLT
.L16:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L17
.L56:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L47
call _ZSt16__throw_bad_castv@PLT
.L47:
call __stack_chk_fail@PLT
.L20:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L21
.L57:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L48:
call __stack_chk_fail@PLT
.L24:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L25
.L58:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L49
call _ZSt16__throw_bad_castv@PLT
.L49:
call __stack_chk_fail@PLT
.L28:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L29
.L59:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L50
call _ZSt16__throw_bad_castv@PLT
.L50:
call __stack_chk_fail@PLT
.L32:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L33
.L60:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L51
call _ZSt16__throw_bad_castv@PLT
.L51:
call __stack_chk_fail@PLT
.L36:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L37:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r12d
cmpl %r12d, 12(%rsp)
jle .L52
.L38:
leaq 16(%rsp), %r15
movl %r12d, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movl $7, %edx
movq %r14, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $7, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r15, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r15, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L53
cmpb $0, 56(%r15)
je .L8
movzbl 67(%r15), %esi
.L9:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $29, %edx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 376(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 380(%rsp), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L54
cmpb $0, 56(%r15)
je .L12
movzbl 67(%r15), %esi
.L13:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $29, %edx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 304(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L55
cmpb $0, 56(%r15)
je .L16
movzbl 67(%r15), %esi
.L17:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $31, %edx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 368(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L56
cmpb $0, 56(%r15)
je .L20
movzbl 67(%r15), %esi
.L21:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $39, %edx
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 312(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L57
cmpb $0, 56(%r15)
je .L24
movzbl 67(%r15), %esi
.L25:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $27, %edx
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 340(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC10(%rip), %r15
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 344(%rsp), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $3, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 348(%rsp), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L58
cmpb $0, 56(%r15)
je .L28
movzbl 67(%r15), %esi
.L29:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $26, %edx
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 352(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC10(%rip), %r15
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 356(%rsp), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $3, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 360(%rsp), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L59
cmpb $0, 56(%r15)
je .L32
movzbl 67(%r15), %esi
.L33:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $12, %edx
leaq .LC12(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 324(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L60
cmpb $0, 56(%r15)
je .L36
movzbl 67(%r15), %esi
jmp .L37
.L52:
movl $0, %eax
.L3:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L61
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movl $0, %eax
jmp .L3
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Created 25-Jan-2014 by Daniel Margala (University of California, Irvine) <dmargala@uci.edu>
#include <iostream>
int main(int argc, char **argv) {
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
std::cout << "No CUDA GPU has been detected" << std::endl;
return -1;
}
else {
std::cout << "Number CUDA GPU devices detected: " << deviceCount << std::endl;
}
for (int dev = 0; dev < deviceCount; dev++) {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
std::cout << "Device " << dev << " name: " << deviceProp.name << std::endl;
std::cout << " Computational Capabilities: " << deviceProp.major << "." << deviceProp.minor << std::endl;
std::cout << " Maximum global memory size: " << deviceProp.totalGlobalMem << std::endl;
std::cout << " Maximum constant memory size: " << deviceProp.totalConstMem << std::endl;
std::cout << " Maximum shared memory size per block: " << deviceProp.sharedMemPerBlock << std::endl;
std::cout << " Maximum block dimensions: " << deviceProp.maxThreadsDim[0] << " x "
<< deviceProp.maxThreadsDim[1] << " x " << deviceProp.maxThreadsDim[2] << std::endl;
std::cout << " Maximum grid dimensions: " << deviceProp.maxGridSize[0] << " x "
<< deviceProp.maxGridSize[1] << " x " << deviceProp.maxGridSize[2] << std::endl;
std::cout << " Warp size: " << deviceProp.warpSize << std::endl;
}
return 0;
} | // Created 25-Jan-2014 by Daniel Margala (University of California, Irvine) <dmargala@uci.edu>
#include <hip/hip_runtime.h>
#include <iostream>
int main(int argc, char **argv) {
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
std::cout << "No CUDA GPU has been detected" << std::endl;
return -1;
}
else {
std::cout << "Number CUDA GPU devices detected: " << deviceCount << std::endl;
}
for (int dev = 0; dev < deviceCount; dev++) {
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
std::cout << "Device " << dev << " name: " << deviceProp.name << std::endl;
std::cout << " Computational Capabilities: " << deviceProp.major << "." << deviceProp.minor << std::endl;
std::cout << " Maximum global memory size: " << deviceProp.totalGlobalMem << std::endl;
std::cout << " Maximum constant memory size: " << deviceProp.totalConstMem << std::endl;
std::cout << " Maximum shared memory size per block: " << deviceProp.sharedMemPerBlock << std::endl;
std::cout << " Maximum block dimensions: " << deviceProp.maxThreadsDim[0] << " x "
<< deviceProp.maxThreadsDim[1] << " x " << deviceProp.maxThreadsDim[2] << std::endl;
std::cout << " Maximum grid dimensions: " << deviceProp.maxGridSize[0] << " x "
<< deviceProp.maxGridSize[1] << " x " << deviceProp.maxGridSize[2] << std::endl;
std::cout << " Warp size: " << deviceProp.warpSize << std::endl;
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Created 25-Jan-2014 by Daniel Margala (University of California, Irvine) <dmargala@uci.edu>
#include <hip/hip_runtime.h>
#include <iostream>
int main(int argc, char **argv) {
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
std::cout << "No CUDA GPU has been detected" << std::endl;
return -1;
}
else {
std::cout << "Number CUDA GPU devices detected: " << deviceCount << std::endl;
}
for (int dev = 0; dev < deviceCount; dev++) {
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
std::cout << "Device " << dev << " name: " << deviceProp.name << std::endl;
std::cout << " Computational Capabilities: " << deviceProp.major << "." << deviceProp.minor << std::endl;
std::cout << " Maximum global memory size: " << deviceProp.totalGlobalMem << std::endl;
std::cout << " Maximum constant memory size: " << deviceProp.totalConstMem << std::endl;
std::cout << " Maximum shared memory size per block: " << deviceProp.sharedMemPerBlock << std::endl;
std::cout << " Maximum block dimensions: " << deviceProp.maxThreadsDim[0] << " x "
<< deviceProp.maxThreadsDim[1] << " x " << deviceProp.maxThreadsDim[2] << std::endl;
std::cout << " Maximum grid dimensions: " << deviceProp.maxGridSize[0] << " x "
<< deviceProp.maxGridSize[1] << " x " << deviceProp.maxGridSize[2] << std::endl;
std::cout << " Warp size: " << deviceProp.warpSize << std::endl;
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Created 25-Jan-2014 by Daniel Margala (University of California, Irvine) <dmargala@uci.edu>
#include <hip/hip_runtime.h>
#include <iostream>
int main(int argc, char **argv) {
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
std::cout << "No CUDA GPU has been detected" << std::endl;
return -1;
}
else {
std::cout << "Number CUDA GPU devices detected: " << deviceCount << std::endl;
}
for (int dev = 0; dev < deviceCount; dev++) {
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
std::cout << "Device " << dev << " name: " << deviceProp.name << std::endl;
std::cout << " Computational Capabilities: " << deviceProp.major << "." << deviceProp.minor << std::endl;
std::cout << " Maximum global memory size: " << deviceProp.totalGlobalMem << std::endl;
std::cout << " Maximum constant memory size: " << deviceProp.totalConstMem << std::endl;
std::cout << " Maximum shared memory size per block: " << deviceProp.sharedMemPerBlock << std::endl;
std::cout << " Maximum block dimensions: " << deviceProp.maxThreadsDim[0] << " x "
<< deviceProp.maxThreadsDim[1] << " x " << deviceProp.maxThreadsDim[2] << std::endl;
std::cout << " Maximum grid dimensions: " << deviceProp.maxGridSize[0] << " x "
<< deviceProp.maxGridSize[1] << " x " << deviceProp.maxGridSize[2] << std::endl;
std::cout << " Warp size: " << deviceProp.warpSize << std::endl;
}
return 0;
} | .text
.file "deviceQuery.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
je .LBB0_1
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_47
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i7
cmpb $0, 56(%rbx)
je .LBB0_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB0_10
.LBB0_1:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_47
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB0_5
.LBB0_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit10
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 4(%rsp)
jle .LBB0_45
# %bb.11: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB0_12
.p2align 4, 0x90
.LBB0_43: # in Loop: Header=BB0_12 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_44: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit50
# in Loop: Header=BB0_12 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB0_45
.LBB0_12: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.3, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
callq strlen
movq %r15, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_47
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i12
# in Loop: Header=BB0_12 Depth=1
cmpb $0, 56(%r12)
je .LBB0_15
# %bb.14: # in Loop: Header=BB0_12 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_16
.p2align 4, 0x90
.LBB0_15: # in Loop: Header=BB0_12 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
# in Loop: Header=BB0_12 Depth=1
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 368(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 372(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_47
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
# in Loop: Header=BB0_12 Depth=1
cmpb $0, 56(%r15)
je .LBB0_19
# %bb.18: # in Loop: Header=BB0_12 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_20
.p2align 4, 0x90
.LBB0_19: # in Loop: Header=BB0_12 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
# in Loop: Header=BB0_12 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 296(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_47
# %bb.21: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
# in Loop: Header=BB0_12 Depth=1
cmpb $0, 56(%r15)
je .LBB0_23
# %bb.22: # in Loop: Header=BB0_12 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_24
.p2align 4, 0x90
.LBB0_23: # in Loop: Header=BB0_12 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
# in Loop: Header=BB0_12 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 360(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_47
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
# in Loop: Header=BB0_12 Depth=1
cmpb $0, 56(%r15)
je .LBB0_27
# %bb.26: # in Loop: Header=BB0_12 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_28
.p2align 4, 0x90
.LBB0_27: # in Loop: Header=BB0_12 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
# in Loop: Header=BB0_12 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $39, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 304(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_47
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
# in Loop: Header=BB0_12 Depth=1
cmpb $0, 56(%r15)
je .LBB0_31
# %bb.30: # in Loop: Header=BB0_12 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_32
.p2align 4, 0x90
.LBB0_31: # in Loop: Header=BB0_12 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
# in Loop: Header=BB0_12 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 332(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.10, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 336(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.10, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 340(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_47
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
# in Loop: Header=BB0_12 Depth=1
cmpb $0, 56(%r15)
je .LBB0_35
# %bb.34: # in Loop: Header=BB0_12 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_36
.p2align 4, 0x90
.LBB0_35: # in Loop: Header=BB0_12 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_36: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit40
# in Loop: Header=BB0_12 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 344(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.10, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 348(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.10, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 352(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_47
# %bb.37: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i42
# in Loop: Header=BB0_12 Depth=1
cmpb $0, 56(%r15)
je .LBB0_39
# %bb.38: # in Loop: Header=BB0_12 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_40
.p2align 4, 0x90
.LBB0_39: # in Loop: Header=BB0_12 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_40: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit45
# in Loop: Header=BB0_12 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 316(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_47
# %bb.41: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i47
# in Loop: Header=BB0_12 Depth=1
cmpb $0, 56(%r15)
je .LBB0_43
# %bb.42: # in Loop: Header=BB0_12 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_44
.LBB0_45:
xorl %eax, %eax
jmp .LBB0_46
.LBB0_4:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $-1, %eax
.LBB0_46: # %.loopexit
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_47:
.cfi_def_cfa_offset 1520
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "No CUDA GPU has been detected"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Number CUDA GPU devices detected: "
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device "
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " name: "
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Computational Capabilities: "
.size .L.str.4, 30
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "."
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " Maximum global memory size: "
.size .L.str.6, 30
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Maximum constant memory size: "
.size .L.str.7, 32
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " Maximum shared memory size per block: "
.size .L.str.8, 40
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " Maximum block dimensions: "
.size .L.str.9, 28
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " x "
.size .L.str.10, 4
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " Maximum grid dimensions: "
.size .L.str.11, 27
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " Warp size: "
.size .L.str.12, 13
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009fc0c_00000000-6_deviceQuery.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "No CUDA GPU has been detected"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Number CUDA GPU devices detected: "
.section .rodata.str1.1
.LC2:
.string "Device "
.LC3:
.string " name: "
.LC4:
.string " Computational Capabilities: "
.LC5:
.string "."
.LC6:
.string " Maximum global memory size: "
.section .rodata.str1.8
.align 8
.LC7:
.string " Maximum constant memory size: "
.align 8
.LC8:
.string " Maximum shared memory size per block: "
.section .rodata.str1.1
.LC9:
.string " Maximum block dimensions: "
.LC10:
.string " x "
.LC11:
.string " Maximum grid dimensions: "
.LC12:
.string " Warp size: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
je .L43
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpl $0, 12(%rsp)
jle .L40
movl $0, %r12d
leaq .LC2(%rip), %r14
leaq _ZSt4cout(%rip), %rbx
leaq .LC3(%rip), %r13
jmp .L38
.L43:
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $-1, %eax
jmp .L3
.L53:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L44
call _ZSt16__throw_bad_castv@PLT
.L44:
call __stack_chk_fail@PLT
.L8:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L9
.L54:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L45
call _ZSt16__throw_bad_castv@PLT
.L45:
call __stack_chk_fail@PLT
.L12:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L13
.L55:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L46
call _ZSt16__throw_bad_castv@PLT
.L46:
call __stack_chk_fail@PLT
.L16:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L17
.L56:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L47
call _ZSt16__throw_bad_castv@PLT
.L47:
call __stack_chk_fail@PLT
.L20:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L21
.L57:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L48:
call __stack_chk_fail@PLT
.L24:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L25
.L58:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L49
call _ZSt16__throw_bad_castv@PLT
.L49:
call __stack_chk_fail@PLT
.L28:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L29
.L59:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L50
call _ZSt16__throw_bad_castv@PLT
.L50:
call __stack_chk_fail@PLT
.L32:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L33
.L60:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L51
call _ZSt16__throw_bad_castv@PLT
.L51:
call __stack_chk_fail@PLT
.L36:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L37:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r12d
cmpl %r12d, 12(%rsp)
jle .L52
.L38:
leaq 16(%rsp), %r15
movl %r12d, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movl $7, %edx
movq %r14, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $7, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r15, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r15, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L53
cmpb $0, 56(%r15)
je .L8
movzbl 67(%r15), %esi
.L9:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $29, %edx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 376(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 380(%rsp), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L54
cmpb $0, 56(%r15)
je .L12
movzbl 67(%r15), %esi
.L13:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $29, %edx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 304(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L55
cmpb $0, 56(%r15)
je .L16
movzbl 67(%r15), %esi
.L17:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $31, %edx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 368(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L56
cmpb $0, 56(%r15)
je .L20
movzbl 67(%r15), %esi
.L21:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $39, %edx
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 312(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L57
cmpb $0, 56(%r15)
je .L24
movzbl 67(%r15), %esi
.L25:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $27, %edx
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 340(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC10(%rip), %r15
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 344(%rsp), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $3, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 348(%rsp), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L58
cmpb $0, 56(%r15)
je .L28
movzbl 67(%r15), %esi
.L29:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $26, %edx
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 352(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC10(%rip), %r15
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 356(%rsp), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $3, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 360(%rsp), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L59
cmpb $0, 56(%r15)
je .L32
movzbl 67(%r15), %esi
.L33:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $12, %edx
leaq .LC12(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 324(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L60
cmpb $0, 56(%r15)
je .L36
movzbl 67(%r15), %esi
jmp .L37
.L52:
movl $0, %eax
.L3:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L61
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movl $0, %eax
jmp .L3
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "deviceQuery.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
je .LBB0_1
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_47
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i7
cmpb $0, 56(%rbx)
je .LBB0_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB0_10
.LBB0_1:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_47
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB0_5
.LBB0_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit10
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 4(%rsp)
jle .LBB0_45
# %bb.11: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB0_12
.p2align 4, 0x90
.LBB0_43: # in Loop: Header=BB0_12 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_44: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit50
# in Loop: Header=BB0_12 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB0_45
.LBB0_12: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.3, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
callq strlen
movq %r15, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_47
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i12
# in Loop: Header=BB0_12 Depth=1
cmpb $0, 56(%r12)
je .LBB0_15
# %bb.14: # in Loop: Header=BB0_12 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_16
.p2align 4, 0x90
.LBB0_15: # in Loop: Header=BB0_12 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
# in Loop: Header=BB0_12 Depth=1
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 368(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 372(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_47
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
# in Loop: Header=BB0_12 Depth=1
cmpb $0, 56(%r15)
je .LBB0_19
# %bb.18: # in Loop: Header=BB0_12 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_20
.p2align 4, 0x90
.LBB0_19: # in Loop: Header=BB0_12 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
# in Loop: Header=BB0_12 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 296(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_47
# %bb.21: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
# in Loop: Header=BB0_12 Depth=1
cmpb $0, 56(%r15)
je .LBB0_23
# %bb.22: # in Loop: Header=BB0_12 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_24
.p2align 4, 0x90
.LBB0_23: # in Loop: Header=BB0_12 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
# in Loop: Header=BB0_12 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 360(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_47
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
# in Loop: Header=BB0_12 Depth=1
cmpb $0, 56(%r15)
je .LBB0_27
# %bb.26: # in Loop: Header=BB0_12 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_28
.p2align 4, 0x90
.LBB0_27: # in Loop: Header=BB0_12 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
# in Loop: Header=BB0_12 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $39, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 304(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_47
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
# in Loop: Header=BB0_12 Depth=1
cmpb $0, 56(%r15)
je .LBB0_31
# %bb.30: # in Loop: Header=BB0_12 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_32
.p2align 4, 0x90
.LBB0_31: # in Loop: Header=BB0_12 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
# in Loop: Header=BB0_12 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 332(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.10, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 336(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.10, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 340(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_47
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
# in Loop: Header=BB0_12 Depth=1
cmpb $0, 56(%r15)
je .LBB0_35
# %bb.34: # in Loop: Header=BB0_12 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_36
.p2align 4, 0x90
.LBB0_35: # in Loop: Header=BB0_12 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_36: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit40
# in Loop: Header=BB0_12 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 344(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.10, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 348(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.10, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 352(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_47
# %bb.37: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i42
# in Loop: Header=BB0_12 Depth=1
cmpb $0, 56(%r15)
je .LBB0_39
# %bb.38: # in Loop: Header=BB0_12 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_40
.p2align 4, 0x90
.LBB0_39: # in Loop: Header=BB0_12 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_40: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit45
# in Loop: Header=BB0_12 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 316(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_47
# %bb.41: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i47
# in Loop: Header=BB0_12 Depth=1
cmpb $0, 56(%r15)
je .LBB0_43
# %bb.42: # in Loop: Header=BB0_12 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_44
.LBB0_45:
xorl %eax, %eax
jmp .LBB0_46
.LBB0_4:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $-1, %eax
.LBB0_46: # %.loopexit
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_47:
.cfi_def_cfa_offset 1520
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "No CUDA GPU has been detected"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Number CUDA GPU devices detected: "
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device "
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " name: "
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Computational Capabilities: "
.size .L.str.4, 30
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "."
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " Maximum global memory size: "
.size .L.str.6, 30
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Maximum constant memory size: "
.size .L.str.7, 32
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " Maximum shared memory size per block: "
.size .L.str.8, 40
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " Maximum block dimensions: "
.size .L.str.9, 28
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " x "
.size .L.str.10, 4
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " Maximum grid dimensions: "
.size .L.str.11, 27
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " Warp size: "
.size .L.str.12, 13
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void gpu_reduce_kernel (int N, float * vector, float * sum)
{
extern __shared__ float partialSum[];
int tid = threadIdx.x + blockIdx.x*blockDim.x;
partialSum[threadIdx.x] = 0.f;
__syncthreads();
while(tid < N)
{
partialSum[threadIdx.x] += vector[tid];
tid += blockDim.x*gridDim.x;
}
__syncthreads();
int nTotalThreads = blockDim.x; /// Total number of active threads
/// Algoritme per calcular la reduccio dels valors actuals a la cache del block
while(nTotalThreads > 1)
{
int halfPoint = (nTotalThreads >> 1); /// divide by two
/// only the first half of the threads will be active.
if (threadIdx.x < halfPoint)
{
partialSum[threadIdx.x] += partialSum[threadIdx.x + halfPoint];
}
/// imprescindible per les reduccions
__syncthreads();
/// Reducing the binary tree size by two:
nTotalThreads = halfPoint;
}
/// El primer thread del primer block es el k s'encarrega de fer els calculs finals
if(threadIdx.x == 0)
(*sum) = partialSum[0];
} | code for sm_80
Function : _Z17gpu_reduce_kerneliPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x190 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0040*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fc600078e00ff */
/*0070*/ STS [R7.X4], RZ ; /* 0x000000ff07007388 */
/* 0x0011e20000004800 */
/*0080*/ SHF.L.U32 R4, R7, 0x2, RZ ; /* 0x0000000207047819 */
/* 0x000fe200000006ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x002fe400078e0207 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*00c0*/ @P0 BRA 0x180 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*00d0*/ LDS R6, [R7.X4] ; /* 0x0000000007067984 */
/* 0x0010620000004800 */
/*00e0*/ BSSY B1, 0x170 ; /* 0x0000008000017945 */
/* 0x000fe40003800000 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*0130*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*0140*/ FADD R6, R3, R6 ; /* 0x0000000603067221 */
/* 0x006fd80000000000 */
/*0150*/ @!P0 BRA 0xf0 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*0160*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0170*/ STS [R7.X4], R6 ; /* 0x0000000607007388 */
/* 0x0003e40000004800 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ ISETP.GE.AND P1, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fe40003f26270 */
/*01b0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fd60003f05270 */
/*01c0*/ @!P1 BRA 0x280 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*01d0*/ SHF.R.U32.HI R6, RZ, 0x1, R5 ; /* 0x00000001ff067819 */
/* 0x002fc80000011605 */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fda0003f26070 */
/*01f0*/ @!P1 LEA R0, R6, R4, 0x2 ; /* 0x0000000406009211 */
/* 0x000fe200078e10ff */
/*0200*/ @!P1 LDS R2, [R7.X4] ; /* 0x0000000007029984 */
/* 0x000fe80000004800 */
/*0210*/ @!P1 LDS R3, [R0] ; /* 0x0000000000039984 */
/* 0x000e240000000800 */
/*0220*/ @!P1 FADD R2, R2, R3 ; /* 0x0000000302029221 */
/* 0x001fca0000000000 */
/*0230*/ @!P1 STS [R7.X4], R2 ; /* 0x0000000207009388 */
/* 0x0001e80000004800 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0250*/ ISETP.GT.U32.AND P1, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe20003f24070 */
/*0260*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fd800078e0006 */
/*0270*/ @P1 BRA 0x1d0 ; /* 0xffffff5000001947 */
/* 0x001fea000383ffff */
/*0280*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0290*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02a0*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*02b0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*02c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ BRA 0x2e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void gpu_reduce_kernel (int N, float * vector, float * sum)
{
extern __shared__ float partialSum[];
int tid = threadIdx.x + blockIdx.x*blockDim.x;
partialSum[threadIdx.x] = 0.f;
__syncthreads();
while(tid < N)
{
partialSum[threadIdx.x] += vector[tid];
tid += blockDim.x*gridDim.x;
}
__syncthreads();
int nTotalThreads = blockDim.x; /// Total number of active threads
/// Algoritme per calcular la reduccio dels valors actuals a la cache del block
while(nTotalThreads > 1)
{
int halfPoint = (nTotalThreads >> 1); /// divide by two
/// only the first half of the threads will be active.
if (threadIdx.x < halfPoint)
{
partialSum[threadIdx.x] += partialSum[threadIdx.x + halfPoint];
}
/// imprescindible per les reduccions
__syncthreads();
/// Reducing the binary tree size by two:
nTotalThreads = halfPoint;
}
/// El primer thread del primer block es el k s'encarrega de fer els calculs finals
if(threadIdx.x == 0)
(*sum) = partialSum[0];
} | .file "tmpxft_0010ca84_00000000-6_gpu_reduce_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z17gpu_reduce_kerneliPfS_iPfS_
.type _Z40__device_stub__Z17gpu_reduce_kerneliPfS_iPfS_, @function
_Z40__device_stub__Z17gpu_reduce_kerneliPfS_iPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17gpu_reduce_kerneliPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z17gpu_reduce_kerneliPfS_iPfS_, .-_Z40__device_stub__Z17gpu_reduce_kerneliPfS_iPfS_
.globl _Z17gpu_reduce_kerneliPfS_
.type _Z17gpu_reduce_kerneliPfS_, @function
_Z17gpu_reduce_kerneliPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17gpu_reduce_kerneliPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17gpu_reduce_kerneliPfS_, .-_Z17gpu_reduce_kerneliPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17gpu_reduce_kerneliPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17gpu_reduce_kerneliPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void gpu_reduce_kernel (int N, float * vector, float * sum)
{
extern __shared__ float partialSum[];
int tid = threadIdx.x + blockIdx.x*blockDim.x;
partialSum[threadIdx.x] = 0.f;
__syncthreads();
while(tid < N)
{
partialSum[threadIdx.x] += vector[tid];
tid += blockDim.x*gridDim.x;
}
__syncthreads();
int nTotalThreads = blockDim.x; /// Total number of active threads
/// Algoritme per calcular la reduccio dels valors actuals a la cache del block
while(nTotalThreads > 1)
{
int halfPoint = (nTotalThreads >> 1); /// divide by two
/// only the first half of the threads will be active.
if (threadIdx.x < halfPoint)
{
partialSum[threadIdx.x] += partialSum[threadIdx.x + halfPoint];
}
/// imprescindible per les reduccions
__syncthreads();
/// Reducing the binary tree size by two:
nTotalThreads = halfPoint;
}
/// El primer thread del primer block es el k s'encarrega de fer els calculs finals
if(threadIdx.x == 0)
(*sum) = partialSum[0];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_reduce_kernel (int N, float * vector, float * sum)
{
extern __shared__ float partialSum[];
int tid = threadIdx.x + blockIdx.x*blockDim.x;
partialSum[threadIdx.x] = 0.f;
__syncthreads();
while(tid < N)
{
partialSum[threadIdx.x] += vector[tid];
tid += blockDim.x*gridDim.x;
}
__syncthreads();
int nTotalThreads = blockDim.x; /// Total number of active threads
/// Algoritme per calcular la reduccio dels valors actuals a la cache del block
while(nTotalThreads > 1)
{
int halfPoint = (nTotalThreads >> 1); /// divide by two
/// only the first half of the threads will be active.
if (threadIdx.x < halfPoint)
{
partialSum[threadIdx.x] += partialSum[threadIdx.x + halfPoint];
}
/// imprescindible per les reduccions
__syncthreads();
/// Reducing the binary tree size by two:
nTotalThreads = halfPoint;
}
/// El primer thread del primer block es el k s'encarrega de fer els calculs finals
if(threadIdx.x == 0)
(*sum) = partialSum[0];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_reduce_kernel (int N, float * vector, float * sum)
{
extern __shared__ float partialSum[];
int tid = threadIdx.x + blockIdx.x*blockDim.x;
partialSum[threadIdx.x] = 0.f;
__syncthreads();
while(tid < N)
{
partialSum[threadIdx.x] += vector[tid];
tid += blockDim.x*gridDim.x;
}
__syncthreads();
int nTotalThreads = blockDim.x; /// Total number of active threads
/// Algoritme per calcular la reduccio dels valors actuals a la cache del block
while(nTotalThreads > 1)
{
int halfPoint = (nTotalThreads >> 1); /// divide by two
/// only the first half of the threads will be active.
if (threadIdx.x < halfPoint)
{
partialSum[threadIdx.x] += partialSum[threadIdx.x + halfPoint];
}
/// imprescindible per les reduccions
__syncthreads();
/// Reducing the binary tree size by two:
nTotalThreads = halfPoint;
}
/// El primer thread del primer block es el k s'encarrega de fer els calculs finals
if(threadIdx.x == 0)
(*sum) = partialSum[0];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17gpu_reduce_kerneliPfS_
.globl _Z17gpu_reduce_kerneliPfS_
.p2align 8
.type _Z17gpu_reduce_kerneliPfS_,@function
_Z17gpu_reduce_kerneliPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
v_lshl_add_u32 v3, v0, 2, 0
s_mov_b32 s6, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
ds_store_b32 v3, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_4
s_load_b32 s8, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x8
ds_load_b32 v4, v3
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s8, s4
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v2, v[5:6], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v4, v2, v4 :: v_dual_add_nc_u32 v1, s8, v1
v_cmp_le_i32_e32 vcc_lo, s5, v1
s_or_b32 s6, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s6
ds_store_b32 v3, v4
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_lt_u32 s4, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_9
.LBB0_5:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x10
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_cmp_gt_u32 s4, 3
s_mov_b32 s4, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_9:
s_lshr_b32 s2, s4, 1
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, v1, 2, 0
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
s_branch .LBB0_8
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17gpu_reduce_kerneliPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17gpu_reduce_kerneliPfS_, .Lfunc_end0-_Z17gpu_reduce_kerneliPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17gpu_reduce_kerneliPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17gpu_reduce_kerneliPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_reduce_kernel (int N, float * vector, float * sum)
{
extern __shared__ float partialSum[];
int tid = threadIdx.x + blockIdx.x*blockDim.x;
partialSum[threadIdx.x] = 0.f;
__syncthreads();
while(tid < N)
{
partialSum[threadIdx.x] += vector[tid];
tid += blockDim.x*gridDim.x;
}
__syncthreads();
int nTotalThreads = blockDim.x; /// Total number of active threads
/// Algoritme per calcular la reduccio dels valors actuals a la cache del block
while(nTotalThreads > 1)
{
int halfPoint = (nTotalThreads >> 1); /// divide by two
/// only the first half of the threads will be active.
if (threadIdx.x < halfPoint)
{
partialSum[threadIdx.x] += partialSum[threadIdx.x + halfPoint];
}
/// imprescindible per les reduccions
__syncthreads();
/// Reducing the binary tree size by two:
nTotalThreads = halfPoint;
}
/// El primer thread del primer block es el k s'encarrega de fer els calculs finals
if(threadIdx.x == 0)
(*sum) = partialSum[0];
} | .text
.file "gpu_reduce_kernel.hip"
.globl _Z32__device_stub__gpu_reduce_kerneliPfS_ # -- Begin function _Z32__device_stub__gpu_reduce_kerneliPfS_
.p2align 4, 0x90
.type _Z32__device_stub__gpu_reduce_kerneliPfS_,@function
_Z32__device_stub__gpu_reduce_kerneliPfS_: # @_Z32__device_stub__gpu_reduce_kerneliPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17gpu_reduce_kerneliPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z32__device_stub__gpu_reduce_kerneliPfS_, .Lfunc_end0-_Z32__device_stub__gpu_reduce_kerneliPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17gpu_reduce_kerneliPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17gpu_reduce_kerneliPfS_,@object # @_Z17gpu_reduce_kerneliPfS_
.section .rodata,"a",@progbits
.globl _Z17gpu_reduce_kerneliPfS_
.p2align 3, 0x0
_Z17gpu_reduce_kerneliPfS_:
.quad _Z32__device_stub__gpu_reduce_kerneliPfS_
.size _Z17gpu_reduce_kerneliPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17gpu_reduce_kerneliPfS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__gpu_reduce_kerneliPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17gpu_reduce_kerneliPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17gpu_reduce_kerneliPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x190 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0040*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fc600078e00ff */
/*0070*/ STS [R7.X4], RZ ; /* 0x000000ff07007388 */
/* 0x0011e20000004800 */
/*0080*/ SHF.L.U32 R4, R7, 0x2, RZ ; /* 0x0000000207047819 */
/* 0x000fe200000006ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x002fe400078e0207 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*00c0*/ @P0 BRA 0x180 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*00d0*/ LDS R6, [R7.X4] ; /* 0x0000000007067984 */
/* 0x0010620000004800 */
/*00e0*/ BSSY B1, 0x170 ; /* 0x0000008000017945 */
/* 0x000fe40003800000 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*0130*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*0140*/ FADD R6, R3, R6 ; /* 0x0000000603067221 */
/* 0x006fd80000000000 */
/*0150*/ @!P0 BRA 0xf0 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*0160*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0170*/ STS [R7.X4], R6 ; /* 0x0000000607007388 */
/* 0x0003e40000004800 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ ISETP.GE.AND P1, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fe40003f26270 */
/*01b0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fd60003f05270 */
/*01c0*/ @!P1 BRA 0x280 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*01d0*/ SHF.R.U32.HI R6, RZ, 0x1, R5 ; /* 0x00000001ff067819 */
/* 0x002fc80000011605 */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fda0003f26070 */
/*01f0*/ @!P1 LEA R0, R6, R4, 0x2 ; /* 0x0000000406009211 */
/* 0x000fe200078e10ff */
/*0200*/ @!P1 LDS R2, [R7.X4] ; /* 0x0000000007029984 */
/* 0x000fe80000004800 */
/*0210*/ @!P1 LDS R3, [R0] ; /* 0x0000000000039984 */
/* 0x000e240000000800 */
/*0220*/ @!P1 FADD R2, R2, R3 ; /* 0x0000000302029221 */
/* 0x001fca0000000000 */
/*0230*/ @!P1 STS [R7.X4], R2 ; /* 0x0000000207009388 */
/* 0x0001e80000004800 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0250*/ ISETP.GT.U32.AND P1, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe20003f24070 */
/*0260*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fd800078e0006 */
/*0270*/ @P1 BRA 0x1d0 ; /* 0xffffff5000001947 */
/* 0x001fea000383ffff */
/*0280*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0290*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02a0*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*02b0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*02c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ BRA 0x2e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17gpu_reduce_kerneliPfS_
.globl _Z17gpu_reduce_kerneliPfS_
.p2align 8
.type _Z17gpu_reduce_kerneliPfS_,@function
_Z17gpu_reduce_kerneliPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
v_lshl_add_u32 v3, v0, 2, 0
s_mov_b32 s6, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
ds_store_b32 v3, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_4
s_load_b32 s8, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x8
ds_load_b32 v4, v3
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s8, s4
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v2, v[5:6], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v4, v2, v4 :: v_dual_add_nc_u32 v1, s8, v1
v_cmp_le_i32_e32 vcc_lo, s5, v1
s_or_b32 s6, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s6
ds_store_b32 v3, v4
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_lt_u32 s4, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_9
.LBB0_5:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x10
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_cmp_gt_u32 s4, 3
s_mov_b32 s4, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_9:
s_lshr_b32 s2, s4, 1
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, v1, 2, 0
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
s_branch .LBB0_8
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17gpu_reduce_kerneliPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17gpu_reduce_kerneliPfS_, .Lfunc_end0-_Z17gpu_reduce_kerneliPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17gpu_reduce_kerneliPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17gpu_reduce_kerneliPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010ca84_00000000-6_gpu_reduce_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z17gpu_reduce_kerneliPfS_iPfS_
.type _Z40__device_stub__Z17gpu_reduce_kerneliPfS_iPfS_, @function
_Z40__device_stub__Z17gpu_reduce_kerneliPfS_iPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17gpu_reduce_kerneliPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z17gpu_reduce_kerneliPfS_iPfS_, .-_Z40__device_stub__Z17gpu_reduce_kerneliPfS_iPfS_
.globl _Z17gpu_reduce_kerneliPfS_
.type _Z17gpu_reduce_kerneliPfS_, @function
_Z17gpu_reduce_kerneliPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17gpu_reduce_kerneliPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17gpu_reduce_kerneliPfS_, .-_Z17gpu_reduce_kerneliPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17gpu_reduce_kerneliPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17gpu_reduce_kerneliPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_reduce_kernel.hip"
.globl _Z32__device_stub__gpu_reduce_kerneliPfS_ # -- Begin function _Z32__device_stub__gpu_reduce_kerneliPfS_
.p2align 4, 0x90
.type _Z32__device_stub__gpu_reduce_kerneliPfS_,@function
_Z32__device_stub__gpu_reduce_kerneliPfS_: # @_Z32__device_stub__gpu_reduce_kerneliPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17gpu_reduce_kerneliPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z32__device_stub__gpu_reduce_kerneliPfS_, .Lfunc_end0-_Z32__device_stub__gpu_reduce_kerneliPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17gpu_reduce_kerneliPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17gpu_reduce_kerneliPfS_,@object # @_Z17gpu_reduce_kerneliPfS_
.section .rodata,"a",@progbits
.globl _Z17gpu_reduce_kerneliPfS_
.p2align 3, 0x0
_Z17gpu_reduce_kerneliPfS_:
.quad _Z32__device_stub__gpu_reduce_kerneliPfS_
.size _Z17gpu_reduce_kerneliPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17gpu_reduce_kerneliPfS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__gpu_reduce_kerneliPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17gpu_reduce_kerneliPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// Contains GPU Cuda code that executes BFS algorithm
// STL
// Internal Headers
// taken from global_memory.cu, Creates event and records time
__global__ void BFSLevels(int *vertices, int *edges, int *distances, int *predecessors, int *vertIndices, int *edgeSize, bool *levels, bool *visitedVertices, bool *foundDest, int numVert, int destination)
{
// Grab ThreadID
int thrID = threadIdx.x + blockIdx.x * blockDim.x;
__shared__ bool destFound;
destFound = false;
if (thrID < numVert && !destFound)
{
int curVert = vertices[thrID];
// Iterate through level if true
if (levels[curVert])
{
levels[curVert] = false;
visitedVertices[curVert] = true;
// Grab indexes for curVert edges in edge array
int edgesEnd = edgeSize[thrID] + vertIndices[thrID];
// Iterate through all edges for current vertex
for (int edgeIter = vertIndices[thrID]; edgeIter < edgesEnd; ++edgeIter)
{
// Grab next Vertex at end of edge
int nextVert = edges[edgeIter];
// If it hasn't been visited store info
// for distance and predecessors and set level
// to true for next level of vertices
if (!visitedVertices[nextVert])
{
distances[nextVert] = distances[curVert] + 1;
levels[nextVert] = true;
predecessors[nextVert] = curVert;
// Set found destination to true and sync threads
if (nextVert == destination)
{
*foundDest = true;
destFound = true;
__syncthreads();
}
}
}
}
}
} | code for sm_80
Function : _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ STS.U8 [RZ], RZ ; /* 0x000000ffff007388 */
/* 0x000fe20000000000 */
/*0040*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x1a8], PT ; /* 0x00006a0006007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R2, R6, R9, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e0209 */
/*00a0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ SHF.R.S32.HI R13, RZ, 0x1f, R0 ; /* 0x0000001fff0d7819 */
/* 0x004fe40000011400 */
/*00c0*/ IADD3 R4, P0, R0, c[0x0][0x190], RZ ; /* 0x0000640000047a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ IADD3.X R5, R13, c[0x0][0x194], RZ, P0, !PT ; /* 0x000065000d057a10 */
/* 0x000fca00007fe4ff */
/*00e0*/ LDG.E.U8 R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1100 */
/*00f0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x004fda0003f05270 */
/*0100*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0110*/ SHF.R.S32.HI R3, RZ, 0x1f, R6 ; /* 0x0000001fff037819 */
/* 0x000fe20000011406 */
/*0120*/ IMAD.SHL.U32 R10, R6, 0x4, RZ ; /* 0x00000004060a7824 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R2, P0, R0, c[0x0][0x198], RZ ; /* 0x0000660000027a10 */
/* 0x000fe20007f1e0ff */
/*0140*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe200078e00ff */
/*0150*/ SHF.L.U64.HI R8, R6, 0x2, R3 ; /* 0x0000000206087819 */
/* 0x000fe20000010203 */
/*0160*/ STG.E.U8 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101104 */
/*0170*/ IADD3 R6, P1, R10, c[0x0][0x188], RZ ; /* 0x000062000a067a10 */
/* 0x000fe40007f3e0ff */
/*0180*/ IADD3.X R3, R13, c[0x0][0x19c], RZ, P0, !PT ; /* 0x000067000d037a10 */
/* 0x000fe400007fe4ff */
/*0190*/ IADD3.X R7, R8, c[0x0][0x18c], RZ, P1, !PT ; /* 0x0000630008077a10 */
/* 0x000fc60000ffe4ff */
/*01a0*/ STG.E.U8 [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101104 */
/*01b0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IADD3 R10, P1, R10, c[0x0][0x180], RZ ; /* 0x000060000a0a7a10 */
/* 0x000fc80007f3e0ff */
/*01d0*/ IADD3.X R11, R8, c[0x0][0x184], RZ, P1, !PT ; /* 0x00006100080b7a10 */
/* 0x001fe40000ffe4ff */
/*01e0*/ ISETP.GE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x004fda0003f06270 */
/*01f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0200*/ LDG.E R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x000ea2000c1e1900 */
/*0210*/ LEA R2, P1, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000027a11 */
/* 0x000fe200078210ff */
/*0220*/ BSSY B0, 0x540 ; /* 0x0000031000007945 */
/* 0x000fe20003800000 */
/*0230*/ IMAD.IADD R4, R6.reuse, 0x1, R7 ; /* 0x0000000106047824 */
/* 0x044fe200078e0207 */
/*0240*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x000fe20007ffe0ff */
/*0250*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fc600078e0006 */
/*0260*/ IMNMX R7, R4, R7, !PT ; /* 0x0000000704077217 */
/* 0x000fca0007800200 */
/*0270*/ IMAD.IADD R3, R7, 0x1, -R6 ; /* 0x0000000107037824 */
/* 0x000fca00078e0a06 */
/*0280*/ LOP3.LUT P0, R15, R3, 0x3, RZ, 0xc0, !PT ; /* 0x00000003030f7812 */
/* 0x000fe4000780c0ff */
/*0290*/ LEA.HI.X R3, R0, c[0x0][0x174], R13, 0x2, P1 ; /* 0x00005d0000037a11 */
/* 0x000fd600008f140d */
/*02a0*/ @!P0 BRA 0x530 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.WIDE R16, R6, R9, c[0x0][0x168] ; /* 0x00005a0006107625 */
/* 0x000fc800078e0209 */
/*02c0*/ IMAD.MOV.U32 R14, RZ, RZ, R16 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0010 */
/*02d0*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0006 */
/*02e0*/ IMAD.MOV.U32 R16, RZ, RZ, R14 ; /* 0x000000ffff107224 */
/* 0x001fca00078e000e */
/*02f0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ SHF.R.S32.HI R18, RZ, 0x1f, R11 ; /* 0x0000001fff127819 */
/* 0x004fe4000001140b */
/*0310*/ IADD3 R8, P0, R11, c[0x0][0x198], RZ ; /* 0x000066000b087a10 */
/* 0x000fc80007f1e0ff */
/*0320*/ IADD3.X R9, R18, c[0x0][0x19c], RZ, P0, !PT ; /* 0x0000670012097a10 */
/* 0x000fca00007fe4ff */
/*0330*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*0340*/ IADD3 R15, R15, -0x1, RZ ; /* 0xffffffff0f0f7810 */
/* 0x000fe20007ffe0ff */
/*0350*/ BSSY B1, 0x500 ; /* 0x000001a000017945 */
/* 0x000fe20003800000 */
/*0360*/ IADD3 R14, P1, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe40007f3e0ff */
/*0370*/ ISETP.NE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f05270 */
/*0380*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f45270 */
/*0390*/ @P2 BRA 0x4f0 ; /* 0x0000015000002947 */
/* 0x000fea0003800000 */
/*03a0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.SHL.U32 R12, R11.reuse, 0x4, RZ ; /* 0x000000040b0c7824 */
/* 0x040fe200078e00ff */
/*03c0*/ ISETP.NE.AND P2, PT, R11.reuse, c[0x0][0x1ac], PT ; /* 0x00006b000b007a0c */
/* 0x040fe20003f45270 */
/*03d0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*03e0*/ SHF.L.U64.HI R13, R11.reuse, 0x2, R18 ; /* 0x000000020b0d7819 */
/* 0x040fe40000010212 */
/*03f0*/ IADD3 R10, P4, R12, c[0x0][0x170], RZ ; /* 0x00005c000c0a7a10 */
/* 0x000fe40007f9e0ff */
/*0400*/ IADD3 R8, P3, R11, c[0x0][0x190], RZ ; /* 0x000064000b087a10 */
/* 0x000fe40007f7e0ff */
/*0410*/ IADD3.X R11, R13, c[0x0][0x174], RZ, P4, !PT ; /* 0x00005d000d0b7a10 */
/* 0x000fc400027fe4ff */
/*0420*/ IADD3 R12, P4, R12, c[0x0][0x178], RZ ; /* 0x00005e000c0c7a10 */
/* 0x000fc60007f9e0ff */
/*0430*/ @!P2 IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x1a4] ; /* 0x00006900ff13a624 */
/* 0x000fe200078e00ff */
/*0440*/ IADD3.X R13, R13, c[0x0][0x17c], RZ, P4, !PT ; /* 0x00005f000d0d7a10 */
/* 0x000fe200027fe4ff */
/*0450*/ @!P2 WARPSYNC 0xffffffff ; /* 0xffffffff0000a948 */
/* 0x000fe20003800000 */
/*0460*/ @!P2 STS.U8 [RZ], R16 ; /* 0x00000010ff00a388 */
/* 0x0001e20000000000 */
/*0470*/ IADD3 R21, R9, 0x1, RZ ; /* 0x0000000109157810 */
/* 0x004fe40007ffe0ff */
/*0480*/ IADD3.X R9, R18, c[0x0][0x194], RZ, P3, !PT ; /* 0x0000650012097a10 */
/* 0x000fe20001ffe4ff */
/*0490*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x1a0] ; /* 0x00006800ff12a624 */
/* 0x000fe400078e00ff */
/*04a0*/ STG.E [R10.64], R21 ; /* 0x000000150a007986 */
/* 0x0001e8000c101904 */
/*04b0*/ STG.E.U8 [R8.64], R16 ; /* 0x0000001008007986 */
/* 0x0001e8000c101104 */
/*04c0*/ STG.E [R12.64], R0 ; /* 0x000000000c007986 */
/* 0x0001e8000c101904 */
/*04d0*/ @!P2 STG.E.U8 [R18.64], R16 ; /* 0x000000101200a986 */
/* 0x0001e8000c101104 */
/*04e0*/ @!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000ab1d */
/* 0x000fec0000010000 */
/*04f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0500*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*0510*/ IMAD.X R17, RZ, RZ, R17, P1 ; /* 0x000000ffff117224 */
/* 0x000fe200008e0611 */
/*0520*/ @P0 BRA 0x2e0 ; /* 0xfffffdb000000947 */
/* 0x000fea000383ffff */
/*0530*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0540*/ LOP3.LUT R6, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff067212 */
/* 0x000fca00078e33ff */
/*0550*/ IMAD.IADD R6, R7, 0x1, R6 ; /* 0x0000000107067824 */
/* 0x000fca00078e0206 */
/*0560*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fda0003f06070 */
/*0570*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0580*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc800078e00ff */
/*0590*/ IMAD.WIDE R6, R5, R6, c[0x0][0x168] ; /* 0x00005a0005067625 */
/* 0x000fca00078e0206 */
/*05a0*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x001ea4000c1e1900 */
/*05b0*/ SHF.R.S32.HI R14, RZ, 0x1f, R11 ; /* 0x0000001fff0e7819 */
/* 0x004fe4000001140b */
/*05c0*/ IADD3 R8, P0, R11, c[0x0][0x198], RZ ; /* 0x000066000b087a10 */
/* 0x000fc80007f1e0ff */
/*05d0*/ IADD3.X R9, R14, c[0x0][0x19c], RZ, P0, !PT ; /* 0x000067000e097a10 */
/* 0x000fca00007fe4ff */
/*05e0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*05f0*/ BSSY B0, 0x780 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*0600*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f05270 */
/*0610*/ @P0 BRA 0x770 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*0620*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*0630*/ IMAD.SHL.U32 R12, R11.reuse, 0x4, RZ ; /* 0x000000040b0c7824 */
/* 0x040fe200078e00ff */
/*0640*/ ISETP.NE.AND P0, PT, R11.reuse, c[0x0][0x1ac], PT ; /* 0x00006b000b007a0c */
/* 0x040fe20003f05270 */
/*0650*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0660*/ SHF.L.U64.HI R13, R11.reuse, 0x2, R14 ; /* 0x000000020b0d7819 */
/* 0x040fe4000001020e */
/*0670*/ IADD3 R10, P1, R12, c[0x0][0x170], RZ ; /* 0x00005c000c0a7a10 */
/* 0x000fe40007f3e0ff */
/*0680*/ IADD3 R8, P2, R11, c[0x0][0x190], RZ ; /* 0x000064000b087a10 */
/* 0x000fe40007f5e0ff */
/*0690*/ IADD3.X R11, R13, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d000d0b7a10 */
/* 0x000fc40000ffe4ff */
/*06a0*/ IADD3 R12, P1, R12, c[0x0][0x178], RZ ; /* 0x00005e000c0c7a10 */
/* 0x000fc60007f3e0ff */
/*06b0*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x1a4] ; /* 0x00006900ff0f8624 */
/* 0x000fe200078e00ff */
/*06c0*/ IADD3.X R13, R13, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f000d0d7a10 */
/* 0x000fe20000ffe4ff */
/*06d0*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*06e0*/ @!P0 STS.U8 [RZ], R16 ; /* 0x00000010ff008388 */
/* 0x0001e20000000000 */
/*06f0*/ IADD3 R17, R9, 0x1, RZ ; /* 0x0000000109117810 */
/* 0x004fe40007ffe0ff */
/*0700*/ IADD3.X R9, R14, c[0x0][0x194], RZ, P2, !PT ; /* 0x000065000e097a10 */
/* 0x000fe200017fe4ff */
/*0710*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x1a0] ; /* 0x00006800ff0e8624 */
/* 0x000fe400078e00ff */
/*0720*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0001e8000c101904 */
/*0730*/ STG.E.U8 [R8.64], R16 ; /* 0x0000001008007986 */
/* 0x0001e8000c101104 */
/*0740*/ STG.E [R12.64], R0 ; /* 0x000000000c007986 */
/* 0x0001e8000c101904 */
/*0750*/ @!P0 STG.E.U8 [R14.64], R16 ; /* 0x000000100e008986 */
/* 0x0001e8000c101104 */
/*0760*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*0770*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0780*/ LDG.E R11, [R6.64+0x4] ; /* 0x00000404060b7981 */
/* 0x001ea4000c1e1900 */
/*0790*/ SHF.R.S32.HI R14, RZ, 0x1f, R11 ; /* 0x0000001fff0e7819 */
/* 0x004fc4000001140b */
/*07a0*/ IADD3 R8, P0, R11, c[0x0][0x198], RZ ; /* 0x000066000b087a10 */
/* 0x000fc80007f1e0ff */
/*07b0*/ IADD3.X R9, R14, c[0x0][0x19c], RZ, P0, !PT ; /* 0x000067000e097a10 */
/* 0x000fca00007fe4ff */
/*07c0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*07d0*/ BSSY B0, 0x960 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*07e0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f05270 */
/*07f0*/ @P0 BRA 0x950 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*0800*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*0810*/ IMAD.SHL.U32 R12, R11.reuse, 0x4, RZ ; /* 0x000000040b0c7824 */
/* 0x040fe200078e00ff */
/*0820*/ ISETP.NE.AND P0, PT, R11.reuse, c[0x0][0x1ac], PT ; /* 0x00006b000b007a0c */
/* 0x040fe20003f05270 */
/*0830*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0840*/ SHF.L.U64.HI R13, R11.reuse, 0x2, R14 ; /* 0x000000020b0d7819 */
/* 0x040fe4000001020e */
/*0850*/ IADD3 R10, P1, R12, c[0x0][0x170], RZ ; /* 0x00005c000c0a7a10 */
/* 0x000fe40007f3e0ff */
/*0860*/ IADD3 R8, P2, R11, c[0x0][0x190], RZ ; /* 0x000064000b087a10 */
/* 0x000fe40007f5e0ff */
/*0870*/ IADD3.X R11, R13, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d000d0b7a10 */
/* 0x000fc40000ffe4ff */
/*0880*/ IADD3 R12, P1, R12, c[0x0][0x178], RZ ; /* 0x00005e000c0c7a10 */
/* 0x000fc60007f3e0ff */
/*0890*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x1a4] ; /* 0x00006900ff0f8624 */
/* 0x000fe200078e00ff */
/*08a0*/ IADD3.X R13, R13, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f000d0d7a10 */
/* 0x000fe20000ffe4ff */
/*08b0*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*08c0*/ @!P0 STS.U8 [RZ], R16 ; /* 0x00000010ff008388 */
/* 0x0001e20000000000 */
/*08d0*/ IADD3 R17, R9, 0x1, RZ ; /* 0x0000000109117810 */
/* 0x004fe40007ffe0ff */
/*08e0*/ IADD3.X R9, R14, c[0x0][0x194], RZ, P2, !PT ; /* 0x000065000e097a10 */
/* 0x000fe200017fe4ff */
/*08f0*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x1a0] ; /* 0x00006800ff0e8624 */
/* 0x000fe400078e00ff */
/*0900*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0001e8000c101904 */
/*0910*/ STG.E.U8 [R8.64], R16 ; /* 0x0000001008007986 */
/* 0x0001e8000c101104 */
/*0920*/ STG.E [R12.64], R0 ; /* 0x000000000c007986 */
/* 0x0001e8000c101904 */
/*0930*/ @!P0 STG.E.U8 [R14.64], R16 ; /* 0x000000100e008986 */
/* 0x0001e8000c101104 */
/*0940*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*0950*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0960*/ LDG.E R11, [R6.64+0x8] ; /* 0x00000804060b7981 */
/* 0x001ea4000c1e1900 */
/*0970*/ SHF.R.S32.HI R14, RZ, 0x1f, R11 ; /* 0x0000001fff0e7819 */
/* 0x004fc4000001140b */
/*0980*/ IADD3 R8, P0, R11, c[0x0][0x198], RZ ; /* 0x000066000b087a10 */
/* 0x000fc80007f1e0ff */
/*0990*/ IADD3.X R9, R14, c[0x0][0x19c], RZ, P0, !PT ; /* 0x000067000e097a10 */
/* 0x000fca00007fe4ff */
/*09a0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*09b0*/ BSSY B0, 0xb40 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*09c0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f05270 */
/*09d0*/ @P0 BRA 0xb30 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*09e0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*09f0*/ IMAD.SHL.U32 R12, R11.reuse, 0x4, RZ ; /* 0x000000040b0c7824 */
/* 0x040fe200078e00ff */
/*0a00*/ ISETP.NE.AND P0, PT, R11.reuse, c[0x0][0x1ac], PT ; /* 0x00006b000b007a0c */
/* 0x040fe20003f05270 */
/*0a10*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0a20*/ SHF.L.U64.HI R13, R11.reuse, 0x2, R14 ; /* 0x000000020b0d7819 */
/* 0x040fe4000001020e */
/*0a30*/ IADD3 R10, P1, R12, c[0x0][0x170], RZ ; /* 0x00005c000c0a7a10 */
/* 0x000fe40007f3e0ff */
/*0a40*/ IADD3 R8, P2, R11, c[0x0][0x190], RZ ; /* 0x000064000b087a10 */
/* 0x000fe40007f5e0ff */
/*0a50*/ IADD3.X R11, R13, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d000d0b7a10 */
/* 0x000fc40000ffe4ff */
/*0a60*/ IADD3 R12, P1, R12, c[0x0][0x178], RZ ; /* 0x00005e000c0c7a10 */
/* 0x000fc60007f3e0ff */
/*0a70*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x1a4] ; /* 0x00006900ff0f8624 */
/* 0x000fe200078e00ff */
/*0a80*/ IADD3.X R13, R13, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f000d0d7a10 */
/* 0x000fe20000ffe4ff */
/*0a90*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*0aa0*/ @!P0 STS.U8 [RZ], R16 ; /* 0x00000010ff008388 */
/* 0x0001e20000000000 */
/*0ab0*/ IADD3 R17, R9, 0x1, RZ ; /* 0x0000000109117810 */
/* 0x004fe40007ffe0ff */
/*0ac0*/ IADD3.X R9, R14, c[0x0][0x194], RZ, P2, !PT ; /* 0x000065000e097a10 */
/* 0x000fe200017fe4ff */
/*0ad0*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x1a0] ; /* 0x00006800ff0e8624 */
/* 0x000fe400078e00ff */
/*0ae0*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0001e8000c101904 */
/*0af0*/ STG.E.U8 [R8.64], R16 ; /* 0x0000001008007986 */
/* 0x0001e8000c101104 */
/*0b00*/ STG.E [R12.64], R0 ; /* 0x000000000c007986 */
/* 0x0001e8000c101904 */
/*0b10*/ @!P0 STG.E.U8 [R14.64], R16 ; /* 0x000000100e008986 */
/* 0x0001e8000c101104 */
/*0b20*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*0b30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b40*/ LDG.E R11, [R6.64+0xc] ; /* 0x00000c04060b7981 */
/* 0x001ea4000c1e1900 */
/*0b50*/ SHF.R.S32.HI R14, RZ, 0x1f, R11 ; /* 0x0000001fff0e7819 */
/* 0x004fc4000001140b */
/*0b60*/ IADD3 R8, P0, R11, c[0x0][0x198], RZ ; /* 0x000066000b087a10 */
/* 0x000fc80007f1e0ff */
/*0b70*/ IADD3.X R9, R14, c[0x0][0x19c], RZ, P0, !PT ; /* 0x000067000e097a10 */
/* 0x000fca00007fe4ff */
/*0b80*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*0b90*/ BSSY B0, 0xd20 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*0ba0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f05270 */
/*0bb0*/ @P0 BRA 0xd10 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*0bc0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*0bd0*/ IMAD.SHL.U32 R12, R11.reuse, 0x4, RZ ; /* 0x000000040b0c7824 */
/* 0x040fe200078e00ff */
/*0be0*/ ISETP.NE.AND P0, PT, R11.reuse, c[0x0][0x1ac], PT ; /* 0x00006b000b007a0c */
/* 0x040fe20003f05270 */
/*0bf0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0c00*/ SHF.L.U64.HI R13, R11.reuse, 0x2, R14 ; /* 0x000000020b0d7819 */
/* 0x040fe4000001020e */
/*0c10*/ IADD3 R10, P1, R12, c[0x0][0x170], RZ ; /* 0x00005c000c0a7a10 */
/* 0x000fe40007f3e0ff */
/*0c20*/ IADD3 R8, P2, R11, c[0x0][0x190], RZ ; /* 0x000064000b087a10 */
/* 0x000fe40007f5e0ff */
/*0c30*/ IADD3.X R11, R13, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d000d0b7a10 */
/* 0x000fc40000ffe4ff */
/*0c40*/ IADD3 R12, P1, R12, c[0x0][0x178], RZ ; /* 0x00005e000c0c7a10 */
/* 0x000fc60007f3e0ff */
/*0c50*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x1a4] ; /* 0x00006900ff0f8624 */
/* 0x000fe200078e00ff */
/*0c60*/ IADD3.X R13, R13, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f000d0d7a10 */
/* 0x000fe20000ffe4ff */
/*0c70*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*0c80*/ @!P0 STS.U8 [RZ], R16 ; /* 0x00000010ff008388 */
/* 0x0001e20000000000 */
/*0c90*/ IADD3 R17, R9, 0x1, RZ ; /* 0x0000000109117810 */
/* 0x004fe40007ffe0ff */
/*0ca0*/ IADD3.X R9, R14, c[0x0][0x194], RZ, P2, !PT ; /* 0x000065000e097a10 */
/* 0x000fe200017fe4ff */
/*0cb0*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x1a0] ; /* 0x00006800ff0e8624 */
/* 0x000fe400078e00ff */
/*0cc0*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0001e8000c101904 */
/*0cd0*/ STG.E.U8 [R8.64], R16 ; /* 0x0000001008007986 */
/* 0x0001e8000c101104 */
/*0ce0*/ STG.E [R12.64], R0 ; /* 0x000000000c007986 */
/* 0x0001e8000c101904 */
/*0cf0*/ @!P0 STG.E.U8 [R14.64], R16 ; /* 0x000000100e008986 */
/* 0x0001e8000c101104 */
/*0d00*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*0d10*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d20*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*0d30*/ IADD3 R6, P1, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc40007f3e0ff */
/*0d40*/ ISETP.GE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fc60003f06270 */
/*0d50*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fd400008e0607 */
/*0d60*/ @!P0 BRA 0x5a0 ; /* 0xfffff83000008947 */
/* 0x000fea000383ffff */
/*0d70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d80*/ BRA 0xd80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// Contains GPU Cuda code that executes BFS algorithm
// STL
// Internal Headers
// taken from global_memory.cu, Creates event and records time
__global__ void BFSLevels(int *vertices, int *edges, int *distances, int *predecessors, int *vertIndices, int *edgeSize, bool *levels, bool *visitedVertices, bool *foundDest, int numVert, int destination)
{
// Grab ThreadID
int thrID = threadIdx.x + blockIdx.x * blockDim.x;
__shared__ bool destFound;
destFound = false;
if (thrID < numVert && !destFound)
{
int curVert = vertices[thrID];
// Iterate through level if true
if (levels[curVert])
{
levels[curVert] = false;
visitedVertices[curVert] = true;
// Grab indexes for curVert edges in edge array
int edgesEnd = edgeSize[thrID] + vertIndices[thrID];
// Iterate through all edges for current vertex
for (int edgeIter = vertIndices[thrID]; edgeIter < edgesEnd; ++edgeIter)
{
// Grab next Vertex at end of edge
int nextVert = edges[edgeIter];
// If it hasn't been visited store info
// for distance and predecessors and set level
// to true for next level of vertices
if (!visitedVertices[nextVert])
{
distances[nextVert] = distances[curVert] + 1;
levels[nextVert] = true;
predecessors[nextVert] = curVert;
// Set found destination to true and sync threads
if (nextVert == destination)
{
*foundDest = true;
destFound = true;
__syncthreads();
}
}
}
}
}
} | .file "tmpxft_0010278f_00000000-6_BFSLevels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_iiPiS_S_S_S_S_PbS0_S0_ii
.type _Z48__device_stub__Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_iiPiS_S_S_S_S_PbS0_S0_ii, @function
_Z48__device_stub__Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_iiPiS_S_S_S_S_PbS0_S0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 256(%rsp), %rax
movq %rax, 24(%rsp)
movq 264(%rsp), %rax
movq %rax, 16(%rsp)
movq 272(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
leaq 280(%rsp), %rax
movq %rax, 216(%rsp)
leaq 288(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_iiPiS_S_S_S_S_PbS0_S0_ii, .-_Z48__device_stub__Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_iiPiS_S_S_S_S_PbS0_S0_ii
.globl _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.type _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii, @function
_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z48__device_stub__Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_iiPiS_S_S_S_S_PbS0_S0_ii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii, .-_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// Contains GPU Cuda code that executes BFS algorithm
// STL
// Internal Headers
// taken from global_memory.cu, Creates event and records time
__global__ void BFSLevels(int *vertices, int *edges, int *distances, int *predecessors, int *vertIndices, int *edgeSize, bool *levels, bool *visitedVertices, bool *foundDest, int numVert, int destination)
{
// Grab ThreadID
int thrID = threadIdx.x + blockIdx.x * blockDim.x;
__shared__ bool destFound;
destFound = false;
if (thrID < numVert && !destFound)
{
int curVert = vertices[thrID];
// Iterate through level if true
if (levels[curVert])
{
levels[curVert] = false;
visitedVertices[curVert] = true;
// Grab indexes for curVert edges in edge array
int edgesEnd = edgeSize[thrID] + vertIndices[thrID];
// Iterate through all edges for current vertex
for (int edgeIter = vertIndices[thrID]; edgeIter < edgesEnd; ++edgeIter)
{
// Grab next Vertex at end of edge
int nextVert = edges[edgeIter];
// If it hasn't been visited store info
// for distance and predecessors and set level
// to true for next level of vertices
if (!visitedVertices[nextVert])
{
distances[nextVert] = distances[curVert] + 1;
levels[nextVert] = true;
predecessors[nextVert] = curVert;
// Set found destination to true and sync threads
if (nextVert == destination)
{
*foundDest = true;
destFound = true;
__syncthreads();
}
}
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// Contains GPU Cuda code that executes BFS algorithm
// STL
// Internal Headers
// taken from global_memory.cu, Creates event and records time
__global__ void BFSLevels(int *vertices, int *edges, int *distances, int *predecessors, int *vertIndices, int *edgeSize, bool *levels, bool *visitedVertices, bool *foundDest, int numVert, int destination)
{
// Grab ThreadID
int thrID = threadIdx.x + blockIdx.x * blockDim.x;
__shared__ bool destFound;
destFound = false;
if (thrID < numVert && !destFound)
{
int curVert = vertices[thrID];
// Iterate through level if true
if (levels[curVert])
{
levels[curVert] = false;
visitedVertices[curVert] = true;
// Grab indexes for curVert edges in edge array
int edgesEnd = edgeSize[thrID] + vertIndices[thrID];
// Iterate through all edges for current vertex
for (int edgeIter = vertIndices[thrID]; edgeIter < edgesEnd; ++edgeIter)
{
// Grab next Vertex at end of edge
int nextVert = edges[edgeIter];
// If it hasn't been visited store info
// for distance and predecessors and set level
// to true for next level of vertices
if (!visitedVertices[nextVert])
{
distances[nextVert] = distances[curVert] + 1;
levels[nextVert] = true;
predecessors[nextVert] = curVert;
// Set found destination to true and sync threads
if (nextVert == destination)
{
*foundDest = true;
destFound = true;
__syncthreads();
}
}
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// Contains GPU Cuda code that executes BFS algorithm
// STL
// Internal Headers
// taken from global_memory.cu, Creates event and records time
__global__ void BFSLevels(int *vertices, int *edges, int *distances, int *predecessors, int *vertIndices, int *edgeSize, bool *levels, bool *visitedVertices, bool *foundDest, int numVert, int destination)
{
// Grab ThreadID
int thrID = threadIdx.x + blockIdx.x * blockDim.x;
__shared__ bool destFound;
destFound = false;
if (thrID < numVert && !destFound)
{
int curVert = vertices[thrID];
// Iterate through level if true
if (levels[curVert])
{
levels[curVert] = false;
visitedVertices[curVert] = true;
// Grab indexes for curVert edges in edge array
int edgesEnd = edgeSize[thrID] + vertIndices[thrID];
// Iterate through all edges for current vertex
for (int edgeIter = vertIndices[thrID]; edgeIter < edgesEnd; ++edgeIter)
{
// Grab next Vertex at end of edge
int nextVert = edges[edgeIter];
// If it hasn't been visited store info
// for distance and predecessors and set level
// to true for next level of vertices
if (!visitedVertices[nextVert])
{
distances[nextVert] = distances[curVert] + 1;
levels[nextVert] = true;
predecessors[nextVert] = curVert;
// Set found destination to true and sync threads
if (nextVert == destination)
{
*foundDest = true;
destFound = true;
__syncthreads();
}
}
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.globl _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.p2align 8
.type _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii,@function
_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x5c
s_load_b32 s3, s[0:1], 0x48
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_8
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x30
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v7, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
global_load_u8 v8, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x28
s_load_b64 s[12:13], s[0:1], 0x38
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, 1
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v6, v[6:7], off
v_add_co_u32 v7, vcc_lo, s12, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s13, v1, vcc_lo
global_store_b8 v[4:5], v9, off
global_store_b8 v[7:8], v10, off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, 0, v6
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b256 s[4:11], s[0:1], 0x8
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_mov_b32_e32 v9, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x40
s_load_b32 s1, s[0:1], 0x4c
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v1, v2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v8, vcc_lo
s_branch .LBB0_5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v2, 1, v2
v_add_co_u32 v5, s0, v5, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
v_cmp_ge_i32_e32 vcc_lo, v2, v1
s_or_b32 s14, vcc_lo, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_8
.LBB0_5:
global_load_b32 v7, v[5:6], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v8, 31, v7
v_add_co_u32 v10, vcc_lo, s12, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s13, v8, vcc_lo
global_load_u8 v10, v[10:11], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u16_e32 0, v10
s_cbranch_execz .LBB0_4
global_load_b32 v16, v[3:4], off
v_lshlrev_b64 v[10:11], 2, v[7:8]
v_add_co_u32 v12, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v8, vcc_lo
v_mov_b32_e32 v8, 1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v15, vcc_lo, s7, v11, vcc_lo
v_add_co_u32 v10, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s1, v7
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v16, 1, v16
global_store_b8 v[12:13], v8, off
global_store_b32 v[14:15], v16, off
global_store_b32 v[10:11], v0, off
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v7, 1
global_store_b8 v9, v7, s[10:11]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_branch .LBB0_4
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 336
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii, .Lfunc_end0-_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 76
.size: 4
.value_kind: by_value
- .offset: 80
.size: 4
.value_kind: hidden_block_count_x
- .offset: 84
.size: 4
.value_kind: hidden_block_count_y
- .offset: 88
.size: 4
.value_kind: hidden_block_count_z
- .offset: 92
.size: 2
.value_kind: hidden_group_size_x
- .offset: 94
.size: 2
.value_kind: hidden_group_size_y
- .offset: 96
.size: 2
.value_kind: hidden_group_size_z
- .offset: 98
.size: 2
.value_kind: hidden_remainder_x
- .offset: 100
.size: 2
.value_kind: hidden_remainder_y
- .offset: 102
.size: 2
.value_kind: hidden_remainder_z
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 144
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 336
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// Contains GPU Cuda code that executes BFS algorithm
// STL
// Internal Headers
// taken from global_memory.cu, Creates event and records time
__global__ void BFSLevels(int *vertices, int *edges, int *distances, int *predecessors, int *vertIndices, int *edgeSize, bool *levels, bool *visitedVertices, bool *foundDest, int numVert, int destination)
{
// Grab ThreadID
int thrID = threadIdx.x + blockIdx.x * blockDim.x;
__shared__ bool destFound;
destFound = false;
if (thrID < numVert && !destFound)
{
int curVert = vertices[thrID];
// Iterate through level if true
if (levels[curVert])
{
levels[curVert] = false;
visitedVertices[curVert] = true;
// Grab indexes for curVert edges in edge array
int edgesEnd = edgeSize[thrID] + vertIndices[thrID];
// Iterate through all edges for current vertex
for (int edgeIter = vertIndices[thrID]; edgeIter < edgesEnd; ++edgeIter)
{
// Grab next Vertex at end of edge
int nextVert = edges[edgeIter];
// If it hasn't been visited store info
// for distance and predecessors and set level
// to true for next level of vertices
if (!visitedVertices[nextVert])
{
distances[nextVert] = distances[curVert] + 1;
levels[nextVert] = true;
predecessors[nextVert] = curVert;
// Set found destination to true and sync threads
if (nextVert == destination)
{
*foundDest = true;
destFound = true;
__syncthreads();
}
}
}
}
}
} | .text
.file "BFSLevels.hip"
.globl _Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii # -- Begin function _Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.p2align 4, 0x90
.type _Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii,@function
_Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii: # @_Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii, .Lfunc_end0-_Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii,@object # @_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.section .rodata,"a",@progbits
.globl _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.p2align 3, 0x0
_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii:
.quad _Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.size _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ STS.U8 [RZ], RZ ; /* 0x000000ffff007388 */
/* 0x000fe20000000000 */
/*0040*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x1a8], PT ; /* 0x00006a0006007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R2, R6, R9, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e0209 */
/*00a0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ SHF.R.S32.HI R13, RZ, 0x1f, R0 ; /* 0x0000001fff0d7819 */
/* 0x004fe40000011400 */
/*00c0*/ IADD3 R4, P0, R0, c[0x0][0x190], RZ ; /* 0x0000640000047a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ IADD3.X R5, R13, c[0x0][0x194], RZ, P0, !PT ; /* 0x000065000d057a10 */
/* 0x000fca00007fe4ff */
/*00e0*/ LDG.E.U8 R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1100 */
/*00f0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x004fda0003f05270 */
/*0100*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0110*/ SHF.R.S32.HI R3, RZ, 0x1f, R6 ; /* 0x0000001fff037819 */
/* 0x000fe20000011406 */
/*0120*/ IMAD.SHL.U32 R10, R6, 0x4, RZ ; /* 0x00000004060a7824 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R2, P0, R0, c[0x0][0x198], RZ ; /* 0x0000660000027a10 */
/* 0x000fe20007f1e0ff */
/*0140*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe200078e00ff */
/*0150*/ SHF.L.U64.HI R8, R6, 0x2, R3 ; /* 0x0000000206087819 */
/* 0x000fe20000010203 */
/*0160*/ STG.E.U8 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101104 */
/*0170*/ IADD3 R6, P1, R10, c[0x0][0x188], RZ ; /* 0x000062000a067a10 */
/* 0x000fe40007f3e0ff */
/*0180*/ IADD3.X R3, R13, c[0x0][0x19c], RZ, P0, !PT ; /* 0x000067000d037a10 */
/* 0x000fe400007fe4ff */
/*0190*/ IADD3.X R7, R8, c[0x0][0x18c], RZ, P1, !PT ; /* 0x0000630008077a10 */
/* 0x000fc60000ffe4ff */
/*01a0*/ STG.E.U8 [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101104 */
/*01b0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IADD3 R10, P1, R10, c[0x0][0x180], RZ ; /* 0x000060000a0a7a10 */
/* 0x000fc80007f3e0ff */
/*01d0*/ IADD3.X R11, R8, c[0x0][0x184], RZ, P1, !PT ; /* 0x00006100080b7a10 */
/* 0x001fe40000ffe4ff */
/*01e0*/ ISETP.GE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x004fda0003f06270 */
/*01f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0200*/ LDG.E R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x000ea2000c1e1900 */
/*0210*/ LEA R2, P1, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000027a11 */
/* 0x000fe200078210ff */
/*0220*/ BSSY B0, 0x540 ; /* 0x0000031000007945 */
/* 0x000fe20003800000 */
/*0230*/ IMAD.IADD R4, R6.reuse, 0x1, R7 ; /* 0x0000000106047824 */
/* 0x044fe200078e0207 */
/*0240*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x000fe20007ffe0ff */
/*0250*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fc600078e0006 */
/*0260*/ IMNMX R7, R4, R7, !PT ; /* 0x0000000704077217 */
/* 0x000fca0007800200 */
/*0270*/ IMAD.IADD R3, R7, 0x1, -R6 ; /* 0x0000000107037824 */
/* 0x000fca00078e0a06 */
/*0280*/ LOP3.LUT P0, R15, R3, 0x3, RZ, 0xc0, !PT ; /* 0x00000003030f7812 */
/* 0x000fe4000780c0ff */
/*0290*/ LEA.HI.X R3, R0, c[0x0][0x174], R13, 0x2, P1 ; /* 0x00005d0000037a11 */
/* 0x000fd600008f140d */
/*02a0*/ @!P0 BRA 0x530 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.WIDE R16, R6, R9, c[0x0][0x168] ; /* 0x00005a0006107625 */
/* 0x000fc800078e0209 */
/*02c0*/ IMAD.MOV.U32 R14, RZ, RZ, R16 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0010 */
/*02d0*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0006 */
/*02e0*/ IMAD.MOV.U32 R16, RZ, RZ, R14 ; /* 0x000000ffff107224 */
/* 0x001fca00078e000e */
/*02f0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ SHF.R.S32.HI R18, RZ, 0x1f, R11 ; /* 0x0000001fff127819 */
/* 0x004fe4000001140b */
/*0310*/ IADD3 R8, P0, R11, c[0x0][0x198], RZ ; /* 0x000066000b087a10 */
/* 0x000fc80007f1e0ff */
/*0320*/ IADD3.X R9, R18, c[0x0][0x19c], RZ, P0, !PT ; /* 0x0000670012097a10 */
/* 0x000fca00007fe4ff */
/*0330*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*0340*/ IADD3 R15, R15, -0x1, RZ ; /* 0xffffffff0f0f7810 */
/* 0x000fe20007ffe0ff */
/*0350*/ BSSY B1, 0x500 ; /* 0x000001a000017945 */
/* 0x000fe20003800000 */
/*0360*/ IADD3 R14, P1, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe40007f3e0ff */
/*0370*/ ISETP.NE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f05270 */
/*0380*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f45270 */
/*0390*/ @P2 BRA 0x4f0 ; /* 0x0000015000002947 */
/* 0x000fea0003800000 */
/*03a0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.SHL.U32 R12, R11.reuse, 0x4, RZ ; /* 0x000000040b0c7824 */
/* 0x040fe200078e00ff */
/*03c0*/ ISETP.NE.AND P2, PT, R11.reuse, c[0x0][0x1ac], PT ; /* 0x00006b000b007a0c */
/* 0x040fe20003f45270 */
/*03d0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*03e0*/ SHF.L.U64.HI R13, R11.reuse, 0x2, R18 ; /* 0x000000020b0d7819 */
/* 0x040fe40000010212 */
/*03f0*/ IADD3 R10, P4, R12, c[0x0][0x170], RZ ; /* 0x00005c000c0a7a10 */
/* 0x000fe40007f9e0ff */
/*0400*/ IADD3 R8, P3, R11, c[0x0][0x190], RZ ; /* 0x000064000b087a10 */
/* 0x000fe40007f7e0ff */
/*0410*/ IADD3.X R11, R13, c[0x0][0x174], RZ, P4, !PT ; /* 0x00005d000d0b7a10 */
/* 0x000fc400027fe4ff */
/*0420*/ IADD3 R12, P4, R12, c[0x0][0x178], RZ ; /* 0x00005e000c0c7a10 */
/* 0x000fc60007f9e0ff */
/*0430*/ @!P2 IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x1a4] ; /* 0x00006900ff13a624 */
/* 0x000fe200078e00ff */
/*0440*/ IADD3.X R13, R13, c[0x0][0x17c], RZ, P4, !PT ; /* 0x00005f000d0d7a10 */
/* 0x000fe200027fe4ff */
/*0450*/ @!P2 WARPSYNC 0xffffffff ; /* 0xffffffff0000a948 */
/* 0x000fe20003800000 */
/*0460*/ @!P2 STS.U8 [RZ], R16 ; /* 0x00000010ff00a388 */
/* 0x0001e20000000000 */
/*0470*/ IADD3 R21, R9, 0x1, RZ ; /* 0x0000000109157810 */
/* 0x004fe40007ffe0ff */
/*0480*/ IADD3.X R9, R18, c[0x0][0x194], RZ, P3, !PT ; /* 0x0000650012097a10 */
/* 0x000fe20001ffe4ff */
/*0490*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x1a0] ; /* 0x00006800ff12a624 */
/* 0x000fe400078e00ff */
/*04a0*/ STG.E [R10.64], R21 ; /* 0x000000150a007986 */
/* 0x0001e8000c101904 */
/*04b0*/ STG.E.U8 [R8.64], R16 ; /* 0x0000001008007986 */
/* 0x0001e8000c101104 */
/*04c0*/ STG.E [R12.64], R0 ; /* 0x000000000c007986 */
/* 0x0001e8000c101904 */
/*04d0*/ @!P2 STG.E.U8 [R18.64], R16 ; /* 0x000000101200a986 */
/* 0x0001e8000c101104 */
/*04e0*/ @!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000ab1d */
/* 0x000fec0000010000 */
/*04f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0500*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*0510*/ IMAD.X R17, RZ, RZ, R17, P1 ; /* 0x000000ffff117224 */
/* 0x000fe200008e0611 */
/*0520*/ @P0 BRA 0x2e0 ; /* 0xfffffdb000000947 */
/* 0x000fea000383ffff */
/*0530*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0540*/ LOP3.LUT R6, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff067212 */
/* 0x000fca00078e33ff */
/*0550*/ IMAD.IADD R6, R7, 0x1, R6 ; /* 0x0000000107067824 */
/* 0x000fca00078e0206 */
/*0560*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fda0003f06070 */
/*0570*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0580*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc800078e00ff */
/*0590*/ IMAD.WIDE R6, R5, R6, c[0x0][0x168] ; /* 0x00005a0005067625 */
/* 0x000fca00078e0206 */
/*05a0*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x001ea4000c1e1900 */
/*05b0*/ SHF.R.S32.HI R14, RZ, 0x1f, R11 ; /* 0x0000001fff0e7819 */
/* 0x004fe4000001140b */
/*05c0*/ IADD3 R8, P0, R11, c[0x0][0x198], RZ ; /* 0x000066000b087a10 */
/* 0x000fc80007f1e0ff */
/*05d0*/ IADD3.X R9, R14, c[0x0][0x19c], RZ, P0, !PT ; /* 0x000067000e097a10 */
/* 0x000fca00007fe4ff */
/*05e0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*05f0*/ BSSY B0, 0x780 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*0600*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f05270 */
/*0610*/ @P0 BRA 0x770 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*0620*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*0630*/ IMAD.SHL.U32 R12, R11.reuse, 0x4, RZ ; /* 0x000000040b0c7824 */
/* 0x040fe200078e00ff */
/*0640*/ ISETP.NE.AND P0, PT, R11.reuse, c[0x0][0x1ac], PT ; /* 0x00006b000b007a0c */
/* 0x040fe20003f05270 */
/*0650*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0660*/ SHF.L.U64.HI R13, R11.reuse, 0x2, R14 ; /* 0x000000020b0d7819 */
/* 0x040fe4000001020e */
/*0670*/ IADD3 R10, P1, R12, c[0x0][0x170], RZ ; /* 0x00005c000c0a7a10 */
/* 0x000fe40007f3e0ff */
/*0680*/ IADD3 R8, P2, R11, c[0x0][0x190], RZ ; /* 0x000064000b087a10 */
/* 0x000fe40007f5e0ff */
/*0690*/ IADD3.X R11, R13, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d000d0b7a10 */
/* 0x000fc40000ffe4ff */
/*06a0*/ IADD3 R12, P1, R12, c[0x0][0x178], RZ ; /* 0x00005e000c0c7a10 */
/* 0x000fc60007f3e0ff */
/*06b0*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x1a4] ; /* 0x00006900ff0f8624 */
/* 0x000fe200078e00ff */
/*06c0*/ IADD3.X R13, R13, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f000d0d7a10 */
/* 0x000fe20000ffe4ff */
/*06d0*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*06e0*/ @!P0 STS.U8 [RZ], R16 ; /* 0x00000010ff008388 */
/* 0x0001e20000000000 */
/*06f0*/ IADD3 R17, R9, 0x1, RZ ; /* 0x0000000109117810 */
/* 0x004fe40007ffe0ff */
/*0700*/ IADD3.X R9, R14, c[0x0][0x194], RZ, P2, !PT ; /* 0x000065000e097a10 */
/* 0x000fe200017fe4ff */
/*0710*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x1a0] ; /* 0x00006800ff0e8624 */
/* 0x000fe400078e00ff */
/*0720*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0001e8000c101904 */
/*0730*/ STG.E.U8 [R8.64], R16 ; /* 0x0000001008007986 */
/* 0x0001e8000c101104 */
/*0740*/ STG.E [R12.64], R0 ; /* 0x000000000c007986 */
/* 0x0001e8000c101904 */
/*0750*/ @!P0 STG.E.U8 [R14.64], R16 ; /* 0x000000100e008986 */
/* 0x0001e8000c101104 */
/*0760*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*0770*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0780*/ LDG.E R11, [R6.64+0x4] ; /* 0x00000404060b7981 */
/* 0x001ea4000c1e1900 */
/*0790*/ SHF.R.S32.HI R14, RZ, 0x1f, R11 ; /* 0x0000001fff0e7819 */
/* 0x004fc4000001140b */
/*07a0*/ IADD3 R8, P0, R11, c[0x0][0x198], RZ ; /* 0x000066000b087a10 */
/* 0x000fc80007f1e0ff */
/*07b0*/ IADD3.X R9, R14, c[0x0][0x19c], RZ, P0, !PT ; /* 0x000067000e097a10 */
/* 0x000fca00007fe4ff */
/*07c0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*07d0*/ BSSY B0, 0x960 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*07e0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f05270 */
/*07f0*/ @P0 BRA 0x950 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*0800*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*0810*/ IMAD.SHL.U32 R12, R11.reuse, 0x4, RZ ; /* 0x000000040b0c7824 */
/* 0x040fe200078e00ff */
/*0820*/ ISETP.NE.AND P0, PT, R11.reuse, c[0x0][0x1ac], PT ; /* 0x00006b000b007a0c */
/* 0x040fe20003f05270 */
/*0830*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0840*/ SHF.L.U64.HI R13, R11.reuse, 0x2, R14 ; /* 0x000000020b0d7819 */
/* 0x040fe4000001020e */
/*0850*/ IADD3 R10, P1, R12, c[0x0][0x170], RZ ; /* 0x00005c000c0a7a10 */
/* 0x000fe40007f3e0ff */
/*0860*/ IADD3 R8, P2, R11, c[0x0][0x190], RZ ; /* 0x000064000b087a10 */
/* 0x000fe40007f5e0ff */
/*0870*/ IADD3.X R11, R13, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d000d0b7a10 */
/* 0x000fc40000ffe4ff */
/*0880*/ IADD3 R12, P1, R12, c[0x0][0x178], RZ ; /* 0x00005e000c0c7a10 */
/* 0x000fc60007f3e0ff */
/*0890*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x1a4] ; /* 0x00006900ff0f8624 */
/* 0x000fe200078e00ff */
/*08a0*/ IADD3.X R13, R13, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f000d0d7a10 */
/* 0x000fe20000ffe4ff */
/*08b0*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*08c0*/ @!P0 STS.U8 [RZ], R16 ; /* 0x00000010ff008388 */
/* 0x0001e20000000000 */
/*08d0*/ IADD3 R17, R9, 0x1, RZ ; /* 0x0000000109117810 */
/* 0x004fe40007ffe0ff */
/*08e0*/ IADD3.X R9, R14, c[0x0][0x194], RZ, P2, !PT ; /* 0x000065000e097a10 */
/* 0x000fe200017fe4ff */
/*08f0*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x1a0] ; /* 0x00006800ff0e8624 */
/* 0x000fe400078e00ff */
/*0900*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0001e8000c101904 */
/*0910*/ STG.E.U8 [R8.64], R16 ; /* 0x0000001008007986 */
/* 0x0001e8000c101104 */
/*0920*/ STG.E [R12.64], R0 ; /* 0x000000000c007986 */
/* 0x0001e8000c101904 */
/*0930*/ @!P0 STG.E.U8 [R14.64], R16 ; /* 0x000000100e008986 */
/* 0x0001e8000c101104 */
/*0940*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*0950*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0960*/ LDG.E R11, [R6.64+0x8] ; /* 0x00000804060b7981 */
/* 0x001ea4000c1e1900 */
/*0970*/ SHF.R.S32.HI R14, RZ, 0x1f, R11 ; /* 0x0000001fff0e7819 */
/* 0x004fc4000001140b */
/*0980*/ IADD3 R8, P0, R11, c[0x0][0x198], RZ ; /* 0x000066000b087a10 */
/* 0x000fc80007f1e0ff */
/*0990*/ IADD3.X R9, R14, c[0x0][0x19c], RZ, P0, !PT ; /* 0x000067000e097a10 */
/* 0x000fca00007fe4ff */
/*09a0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*09b0*/ BSSY B0, 0xb40 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*09c0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f05270 */
/*09d0*/ @P0 BRA 0xb30 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*09e0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*09f0*/ IMAD.SHL.U32 R12, R11.reuse, 0x4, RZ ; /* 0x000000040b0c7824 */
/* 0x040fe200078e00ff */
/*0a00*/ ISETP.NE.AND P0, PT, R11.reuse, c[0x0][0x1ac], PT ; /* 0x00006b000b007a0c */
/* 0x040fe20003f05270 */
/*0a10*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0a20*/ SHF.L.U64.HI R13, R11.reuse, 0x2, R14 ; /* 0x000000020b0d7819 */
/* 0x040fe4000001020e */
/*0a30*/ IADD3 R10, P1, R12, c[0x0][0x170], RZ ; /* 0x00005c000c0a7a10 */
/* 0x000fe40007f3e0ff */
/*0a40*/ IADD3 R8, P2, R11, c[0x0][0x190], RZ ; /* 0x000064000b087a10 */
/* 0x000fe40007f5e0ff */
/*0a50*/ IADD3.X R11, R13, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d000d0b7a10 */
/* 0x000fc40000ffe4ff */
/*0a60*/ IADD3 R12, P1, R12, c[0x0][0x178], RZ ; /* 0x00005e000c0c7a10 */
/* 0x000fc60007f3e0ff */
/*0a70*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x1a4] ; /* 0x00006900ff0f8624 */
/* 0x000fe200078e00ff */
/*0a80*/ IADD3.X R13, R13, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f000d0d7a10 */
/* 0x000fe20000ffe4ff */
/*0a90*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*0aa0*/ @!P0 STS.U8 [RZ], R16 ; /* 0x00000010ff008388 */
/* 0x0001e20000000000 */
/*0ab0*/ IADD3 R17, R9, 0x1, RZ ; /* 0x0000000109117810 */
/* 0x004fe40007ffe0ff */
/*0ac0*/ IADD3.X R9, R14, c[0x0][0x194], RZ, P2, !PT ; /* 0x000065000e097a10 */
/* 0x000fe200017fe4ff */
/*0ad0*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x1a0] ; /* 0x00006800ff0e8624 */
/* 0x000fe400078e00ff */
/*0ae0*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0001e8000c101904 */
/*0af0*/ STG.E.U8 [R8.64], R16 ; /* 0x0000001008007986 */
/* 0x0001e8000c101104 */
/*0b00*/ STG.E [R12.64], R0 ; /* 0x000000000c007986 */
/* 0x0001e8000c101904 */
/*0b10*/ @!P0 STG.E.U8 [R14.64], R16 ; /* 0x000000100e008986 */
/* 0x0001e8000c101104 */
/*0b20*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*0b30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b40*/ LDG.E R11, [R6.64+0xc] ; /* 0x00000c04060b7981 */
/* 0x001ea4000c1e1900 */
/*0b50*/ SHF.R.S32.HI R14, RZ, 0x1f, R11 ; /* 0x0000001fff0e7819 */
/* 0x004fc4000001140b */
/*0b60*/ IADD3 R8, P0, R11, c[0x0][0x198], RZ ; /* 0x000066000b087a10 */
/* 0x000fc80007f1e0ff */
/*0b70*/ IADD3.X R9, R14, c[0x0][0x19c], RZ, P0, !PT ; /* 0x000067000e097a10 */
/* 0x000fca00007fe4ff */
/*0b80*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*0b90*/ BSSY B0, 0xd20 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*0ba0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f05270 */
/*0bb0*/ @P0 BRA 0xd10 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*0bc0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*0bd0*/ IMAD.SHL.U32 R12, R11.reuse, 0x4, RZ ; /* 0x000000040b0c7824 */
/* 0x040fe200078e00ff */
/*0be0*/ ISETP.NE.AND P0, PT, R11.reuse, c[0x0][0x1ac], PT ; /* 0x00006b000b007a0c */
/* 0x040fe20003f05270 */
/*0bf0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0c00*/ SHF.L.U64.HI R13, R11.reuse, 0x2, R14 ; /* 0x000000020b0d7819 */
/* 0x040fe4000001020e */
/*0c10*/ IADD3 R10, P1, R12, c[0x0][0x170], RZ ; /* 0x00005c000c0a7a10 */
/* 0x000fe40007f3e0ff */
/*0c20*/ IADD3 R8, P2, R11, c[0x0][0x190], RZ ; /* 0x000064000b087a10 */
/* 0x000fe40007f5e0ff */
/*0c30*/ IADD3.X R11, R13, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d000d0b7a10 */
/* 0x000fc40000ffe4ff */
/*0c40*/ IADD3 R12, P1, R12, c[0x0][0x178], RZ ; /* 0x00005e000c0c7a10 */
/* 0x000fc60007f3e0ff */
/*0c50*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x1a4] ; /* 0x00006900ff0f8624 */
/* 0x000fe200078e00ff */
/*0c60*/ IADD3.X R13, R13, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f000d0d7a10 */
/* 0x000fe20000ffe4ff */
/*0c70*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*0c80*/ @!P0 STS.U8 [RZ], R16 ; /* 0x00000010ff008388 */
/* 0x0001e20000000000 */
/*0c90*/ IADD3 R17, R9, 0x1, RZ ; /* 0x0000000109117810 */
/* 0x004fe40007ffe0ff */
/*0ca0*/ IADD3.X R9, R14, c[0x0][0x194], RZ, P2, !PT ; /* 0x000065000e097a10 */
/* 0x000fe200017fe4ff */
/*0cb0*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x1a0] ; /* 0x00006800ff0e8624 */
/* 0x000fe400078e00ff */
/*0cc0*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0001e8000c101904 */
/*0cd0*/ STG.E.U8 [R8.64], R16 ; /* 0x0000001008007986 */
/* 0x0001e8000c101104 */
/*0ce0*/ STG.E [R12.64], R0 ; /* 0x000000000c007986 */
/* 0x0001e8000c101904 */
/*0cf0*/ @!P0 STG.E.U8 [R14.64], R16 ; /* 0x000000100e008986 */
/* 0x0001e8000c101104 */
/*0d00*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*0d10*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d20*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*0d30*/ IADD3 R6, P1, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc40007f3e0ff */
/*0d40*/ ISETP.GE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fc60003f06270 */
/*0d50*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fd400008e0607 */
/*0d60*/ @!P0 BRA 0x5a0 ; /* 0xfffff83000008947 */
/* 0x000fea000383ffff */
/*0d70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d80*/ BRA 0xd80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.globl _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.p2align 8
.type _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii,@function
_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x5c
s_load_b32 s3, s[0:1], 0x48
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_8
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x30
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v7, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
global_load_u8 v8, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x28
s_load_b64 s[12:13], s[0:1], 0x38
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, 1
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v6, v[6:7], off
v_add_co_u32 v7, vcc_lo, s12, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s13, v1, vcc_lo
global_store_b8 v[4:5], v9, off
global_store_b8 v[7:8], v10, off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, 0, v6
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b256 s[4:11], s[0:1], 0x8
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_mov_b32_e32 v9, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x40
s_load_b32 s1, s[0:1], 0x4c
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v1, v2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v8, vcc_lo
s_branch .LBB0_5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v2, 1, v2
v_add_co_u32 v5, s0, v5, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
v_cmp_ge_i32_e32 vcc_lo, v2, v1
s_or_b32 s14, vcc_lo, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_8
.LBB0_5:
global_load_b32 v7, v[5:6], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v8, 31, v7
v_add_co_u32 v10, vcc_lo, s12, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s13, v8, vcc_lo
global_load_u8 v10, v[10:11], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u16_e32 0, v10
s_cbranch_execz .LBB0_4
global_load_b32 v16, v[3:4], off
v_lshlrev_b64 v[10:11], 2, v[7:8]
v_add_co_u32 v12, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v8, vcc_lo
v_mov_b32_e32 v8, 1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v15, vcc_lo, s7, v11, vcc_lo
v_add_co_u32 v10, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s1, v7
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v16, 1, v16
global_store_b8 v[12:13], v8, off
global_store_b32 v[14:15], v16, off
global_store_b32 v[10:11], v0, off
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v7, 1
global_store_b8 v9, v7, s[10:11]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_branch .LBB0_4
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 336
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii, .Lfunc_end0-_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 76
.size: 4
.value_kind: by_value
- .offset: 80
.size: 4
.value_kind: hidden_block_count_x
- .offset: 84
.size: 4
.value_kind: hidden_block_count_y
- .offset: 88
.size: 4
.value_kind: hidden_block_count_z
- .offset: 92
.size: 2
.value_kind: hidden_group_size_x
- .offset: 94
.size: 2
.value_kind: hidden_group_size_y
- .offset: 96
.size: 2
.value_kind: hidden_group_size_z
- .offset: 98
.size: 2
.value_kind: hidden_remainder_x
- .offset: 100
.size: 2
.value_kind: hidden_remainder_y
- .offset: 102
.size: 2
.value_kind: hidden_remainder_z
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 144
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 336
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010278f_00000000-6_BFSLevels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_iiPiS_S_S_S_S_PbS0_S0_ii
.type _Z48__device_stub__Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_iiPiS_S_S_S_S_PbS0_S0_ii, @function
_Z48__device_stub__Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_iiPiS_S_S_S_S_PbS0_S0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 256(%rsp), %rax
movq %rax, 24(%rsp)
movq 264(%rsp), %rax
movq %rax, 16(%rsp)
movq 272(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
leaq 280(%rsp), %rax
movq %rax, 216(%rsp)
leaq 288(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_iiPiS_S_S_S_S_PbS0_S0_ii, .-_Z48__device_stub__Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_iiPiS_S_S_S_S_PbS0_S0_ii
.globl _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.type _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii, @function
_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z48__device_stub__Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_iiPiS_S_S_S_S_PbS0_S0_ii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii, .-_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "BFSLevels.hip"
.globl _Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii # -- Begin function _Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.p2align 4, 0x90
.type _Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii,@function
_Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii: # @_Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii, .Lfunc_end0-_Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii,@object # @_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.section .rodata,"a",@progbits
.globl _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.p2align 3, 0x0
_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii:
.quad _Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.size _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9BFSLevelsPiS_S_S_S_S_PbS0_S0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void updateVel(float2 *__restrict__ oldVel, float2 *__restrict__ newVel, unsigned int simWidth)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
oldVel[y*simWidth+x] = newVel[y*simWidth+x];
} | code for sm_80
Function : _Z9updateVelP6float2S0_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff027435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fce00078e0200 */
/*00a0*/ IMAD.WIDE.U32 R4, R3, R2, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fcc00078e0002 */
/*00b0*/ LDG.E.64.CONSTANT R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e9b00 */
/*00c0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0002 */
/*00d0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x004fe2000c101b04 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void updateVel(float2 *__restrict__ oldVel, float2 *__restrict__ newVel, unsigned int simWidth)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
oldVel[y*simWidth+x] = newVel[y*simWidth+x];
} | .file "tmpxft_00075ae8_00000000-6_updateVel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z9updateVelP6float2S0_jP6float2S0_j
.type _Z38__device_stub__Z9updateVelP6float2S0_jP6float2S0_j, @function
_Z38__device_stub__Z9updateVelP6float2S0_jP6float2S0_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9updateVelP6float2S0_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z9updateVelP6float2S0_jP6float2S0_j, .-_Z38__device_stub__Z9updateVelP6float2S0_jP6float2S0_j
.globl _Z9updateVelP6float2S0_j
.type _Z9updateVelP6float2S0_j, @function
_Z9updateVelP6float2S0_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z9updateVelP6float2S0_jP6float2S0_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9updateVelP6float2S0_j, .-_Z9updateVelP6float2S0_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9updateVelP6float2S0_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9updateVelP6float2S0_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void updateVel(float2 *__restrict__ oldVel, float2 *__restrict__ newVel, unsigned int simWidth)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
oldVel[y*simWidth+x] = newVel[y*simWidth+x];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void updateVel(float2 *__restrict__ oldVel, float2 *__restrict__ newVel, unsigned int simWidth)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
oldVel[y*simWidth+x] = newVel[y*simWidth+x];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void updateVel(float2 *__restrict__ oldVel, float2 *__restrict__ newVel, unsigned int simWidth)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
oldVel[y*simWidth+x] = newVel[y*simWidth+x];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9updateVelP15HIP_vector_typeIfLj2EES1_j
.globl _Z9updateVelP15HIP_vector_typeIfLj2EES1_j
.p2align 8
.type _Z9updateVelP15HIP_vector_typeIfLj2EES1_j,@function
_Z9updateVelP15HIP_vector_typeIfLj2EES1_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
v_mov_b32_e32 v1, 0
s_load_b128 s[0:3], s[0:1], 0x0
s_mul_i32 s14, s14, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s5
v_add3_u32 v0, s14, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9updateVelP15HIP_vector_typeIfLj2EES1_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9updateVelP15HIP_vector_typeIfLj2EES1_j, .Lfunc_end0-_Z9updateVelP15HIP_vector_typeIfLj2EES1_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: write_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9updateVelP15HIP_vector_typeIfLj2EES1_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9updateVelP15HIP_vector_typeIfLj2EES1_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void updateVel(float2 *__restrict__ oldVel, float2 *__restrict__ newVel, unsigned int simWidth)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
oldVel[y*simWidth+x] = newVel[y*simWidth+x];
} | .text
.file "updateVel.hip"
.globl _Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j # -- Begin function _Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j
.p2align 4, 0x90
.type _Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j,@function
_Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j: # @_Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9updateVelP15HIP_vector_typeIfLj2EES1_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j, .Lfunc_end0-_Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9updateVelP15HIP_vector_typeIfLj2EES1_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9updateVelP15HIP_vector_typeIfLj2EES1_j,@object # @_Z9updateVelP15HIP_vector_typeIfLj2EES1_j
.section .rodata,"a",@progbits
.globl _Z9updateVelP15HIP_vector_typeIfLj2EES1_j
.p2align 3, 0x0
_Z9updateVelP15HIP_vector_typeIfLj2EES1_j:
.quad _Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j
.size _Z9updateVelP15HIP_vector_typeIfLj2EES1_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9updateVelP15HIP_vector_typeIfLj2EES1_j"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9updateVelP15HIP_vector_typeIfLj2EES1_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9updateVelP6float2S0_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff027435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fce00078e0200 */
/*00a0*/ IMAD.WIDE.U32 R4, R3, R2, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fcc00078e0002 */
/*00b0*/ LDG.E.64.CONSTANT R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e9b00 */
/*00c0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0002 */
/*00d0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x004fe2000c101b04 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9updateVelP15HIP_vector_typeIfLj2EES1_j
.globl _Z9updateVelP15HIP_vector_typeIfLj2EES1_j
.p2align 8
.type _Z9updateVelP15HIP_vector_typeIfLj2EES1_j,@function
_Z9updateVelP15HIP_vector_typeIfLj2EES1_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
v_mov_b32_e32 v1, 0
s_load_b128 s[0:3], s[0:1], 0x0
s_mul_i32 s14, s14, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s5
v_add3_u32 v0, s14, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9updateVelP15HIP_vector_typeIfLj2EES1_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9updateVelP15HIP_vector_typeIfLj2EES1_j, .Lfunc_end0-_Z9updateVelP15HIP_vector_typeIfLj2EES1_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: write_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9updateVelP15HIP_vector_typeIfLj2EES1_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9updateVelP15HIP_vector_typeIfLj2EES1_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00075ae8_00000000-6_updateVel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z9updateVelP6float2S0_jP6float2S0_j
.type _Z38__device_stub__Z9updateVelP6float2S0_jP6float2S0_j, @function
_Z38__device_stub__Z9updateVelP6float2S0_jP6float2S0_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9updateVelP6float2S0_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z9updateVelP6float2S0_jP6float2S0_j, .-_Z38__device_stub__Z9updateVelP6float2S0_jP6float2S0_j
.globl _Z9updateVelP6float2S0_j
.type _Z9updateVelP6float2S0_j, @function
_Z9updateVelP6float2S0_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z9updateVelP6float2S0_jP6float2S0_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9updateVelP6float2S0_j, .-_Z9updateVelP6float2S0_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9updateVelP6float2S0_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9updateVelP6float2S0_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "updateVel.hip"
.globl _Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j # -- Begin function _Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j
.p2align 4, 0x90
.type _Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j,@function
_Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j: # @_Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9updateVelP15HIP_vector_typeIfLj2EES1_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j, .Lfunc_end0-_Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9updateVelP15HIP_vector_typeIfLj2EES1_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9updateVelP15HIP_vector_typeIfLj2EES1_j,@object # @_Z9updateVelP15HIP_vector_typeIfLj2EES1_j
.section .rodata,"a",@progbits
.globl _Z9updateVelP15HIP_vector_typeIfLj2EES1_j
.p2align 3, 0x0
_Z9updateVelP15HIP_vector_typeIfLj2EES1_j:
.quad _Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j
.size _Z9updateVelP15HIP_vector_typeIfLj2EES1_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9updateVelP15HIP_vector_typeIfLj2EES1_j"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__updateVelP15HIP_vector_typeIfLj2EES1_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9updateVelP15HIP_vector_typeIfLj2EES1_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void reduceInterleaved (int *g_idata, int *g_odata, unsigned int n)
{
// set thread ID
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
// boundary check
if(idx >= n) return;
// in-place reduction in global memory
for (int stride = blockDim.x / 2; stride > 0; stride /= 2)
{
if (tid < stride)
{
g_idata[idx] += g_idata[idx + stride];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = g_idata[idx];
} | code for sm_80
Function : _Z17reduceInterleavedPiS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R8, c[0x0][0x0], R9 ; /* 0x0000000008007a24 */
/* 0x001fca00078e0209 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0080*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe40008011604 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*00a0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf05270 */
/*00b0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fd400078e0003 */
/*00c0*/ @!P0 BRA 0x1c0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x000fe2000bf06070 */
/*00e0*/ BSSY B0, 0x180 ; /* 0x0000009000007945 */
/* 0x000fd80003800000 */
/*00f0*/ @P0 BRA 0x170 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*0100*/ IADD3 R4, R0, UR4, RZ ; /* 0x0000000400047c10 */
/* 0x000fe2000fffe0ff */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0120*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea6000c1e1900 */
/*0130*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0005 */
/*0140*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea4000c1e1900 */
/*0150*/ IADD3 R7, R6, R5, RZ ; /* 0x0000000506077210 */
/* 0x004fca0007ffe0ff */
/*0160*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101906 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fea0000010000 */
/*01a0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*01b0*/ @P0 BRA 0xd0 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*01c0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*01d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01e0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x001ea2000c1e1900 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fca00078e0005 */
/*0210*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void reduceInterleaved (int *g_idata, int *g_odata, unsigned int n)
{
// set thread ID
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
// boundary check
if(idx >= n) return;
// in-place reduction in global memory
for (int stride = blockDim.x / 2; stride > 0; stride /= 2)
{
if (tid < stride)
{
g_idata[idx] += g_idata[idx + stride];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = g_idata[idx];
} | .file "tmpxft_0001df1c_00000000-6_reduceInterleaved.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j
.type _Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j, @function
_Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17reduceInterleavedPiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j, .-_Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j
.globl _Z17reduceInterleavedPiS_j
.type _Z17reduceInterleavedPiS_j, @function
_Z17reduceInterleavedPiS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17reduceInterleavedPiS_j, .-_Z17reduceInterleavedPiS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17reduceInterleavedPiS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17reduceInterleavedPiS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void reduceInterleaved (int *g_idata, int *g_odata, unsigned int n)
{
// set thread ID
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
// boundary check
if(idx >= n) return;
// in-place reduction in global memory
for (int stride = blockDim.x / 2; stride > 0; stride /= 2)
{
if (tid < stride)
{
g_idata[idx] += g_idata[idx + stride];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = g_idata[idx];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduceInterleaved (int *g_idata, int *g_odata, unsigned int n)
{
// set thread ID
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
// boundary check
if(idx >= n) return;
// in-place reduction in global memory
for (int stride = blockDim.x / 2; stride > 0; stride /= 2)
{
if (tid < stride)
{
g_idata[idx] += g_idata[idx + stride];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = g_idata[idx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduceInterleaved (int *g_idata, int *g_odata, unsigned int n)
{
// set thread ID
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
// boundary check
if(idx >= n) return;
// in-place reduction in global memory
for (int stride = blockDim.x / 2; stride > 0; stride /= 2)
{
if (tid < stride)
{
g_idata[idx] += g_idata[idx + stride];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = g_idata[idx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17reduceInterleavedPiS_j
.globl _Z17reduceInterleavedPiS_j
.p2align 8
.type _Z17reduceInterleavedPiS_j,@function
_Z17reduceInterleavedPiS_j:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmp_gt_u32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[4:5], s[0:1], 0x0
s_cmp_lt_u32 s3, 2
s_cbranch_scc1 .LBB0_6
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v2, v3
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s6
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_4:
s_lshr_b32 s6, s3, 1
s_mov_b32 s7, exec_lo
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v2, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_clause 0x1
global_load_b32 v2, v[6:7], off
global_load_b32 v6, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v6, v2
global_store_b32 v[4:5], v2, off
s_branch .LBB0_3
.LBB0_6:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s3, 0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17reduceInterleavedPiS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17reduceInterleavedPiS_j, .Lfunc_end0-_Z17reduceInterleavedPiS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17reduceInterleavedPiS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17reduceInterleavedPiS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduceInterleaved (int *g_idata, int *g_odata, unsigned int n)
{
// set thread ID
unsigned int tid = threadIdx.x;
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
// boundary check
if(idx >= n) return;
// in-place reduction in global memory
for (int stride = blockDim.x / 2; stride > 0; stride /= 2)
{
if (tid < stride)
{
g_idata[idx] += g_idata[idx + stride];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = g_idata[idx];
} | .text
.file "reduceInterleaved.hip"
.globl _Z32__device_stub__reduceInterleavedPiS_j # -- Begin function _Z32__device_stub__reduceInterleavedPiS_j
.p2align 4, 0x90
.type _Z32__device_stub__reduceInterleavedPiS_j,@function
_Z32__device_stub__reduceInterleavedPiS_j: # @_Z32__device_stub__reduceInterleavedPiS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17reduceInterleavedPiS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z32__device_stub__reduceInterleavedPiS_j, .Lfunc_end0-_Z32__device_stub__reduceInterleavedPiS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17reduceInterleavedPiS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17reduceInterleavedPiS_j,@object # @_Z17reduceInterleavedPiS_j
.section .rodata,"a",@progbits
.globl _Z17reduceInterleavedPiS_j
.p2align 3, 0x0
_Z17reduceInterleavedPiS_j:
.quad _Z32__device_stub__reduceInterleavedPiS_j
.size _Z17reduceInterleavedPiS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17reduceInterleavedPiS_j"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__reduceInterleavedPiS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17reduceInterleavedPiS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17reduceInterleavedPiS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R8, c[0x0][0x0], R9 ; /* 0x0000000008007a24 */
/* 0x001fca00078e0209 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0080*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe40008011604 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*00a0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf05270 */
/*00b0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fd400078e0003 */
/*00c0*/ @!P0 BRA 0x1c0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x000fe2000bf06070 */
/*00e0*/ BSSY B0, 0x180 ; /* 0x0000009000007945 */
/* 0x000fd80003800000 */
/*00f0*/ @P0 BRA 0x170 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*0100*/ IADD3 R4, R0, UR4, RZ ; /* 0x0000000400047c10 */
/* 0x000fe2000fffe0ff */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0120*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea6000c1e1900 */
/*0130*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0005 */
/*0140*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea4000c1e1900 */
/*0150*/ IADD3 R7, R6, R5, RZ ; /* 0x0000000506077210 */
/* 0x004fca0007ffe0ff */
/*0160*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101906 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fea0000010000 */
/*01a0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*01b0*/ @P0 BRA 0xd0 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*01c0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*01d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01e0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x001ea2000c1e1900 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fca00078e0005 */
/*0210*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17reduceInterleavedPiS_j
.globl _Z17reduceInterleavedPiS_j
.p2align 8
.type _Z17reduceInterleavedPiS_j,@function
_Z17reduceInterleavedPiS_j:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmp_gt_u32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[4:5], s[0:1], 0x0
s_cmp_lt_u32 s3, 2
s_cbranch_scc1 .LBB0_6
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v2, v3
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s6
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_4:
s_lshr_b32 s6, s3, 1
s_mov_b32 s7, exec_lo
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v2, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_clause 0x1
global_load_b32 v2, v[6:7], off
global_load_b32 v6, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v6, v2
global_store_b32 v[4:5], v2, off
s_branch .LBB0_3
.LBB0_6:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s3, 0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17reduceInterleavedPiS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17reduceInterleavedPiS_j, .Lfunc_end0-_Z17reduceInterleavedPiS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17reduceInterleavedPiS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17reduceInterleavedPiS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001df1c_00000000-6_reduceInterleaved.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j
.type _Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j, @function
_Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17reduceInterleavedPiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j, .-_Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j
.globl _Z17reduceInterleavedPiS_j
.type _Z17reduceInterleavedPiS_j, @function
_Z17reduceInterleavedPiS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17reduceInterleavedPiS_jPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17reduceInterleavedPiS_j, .-_Z17reduceInterleavedPiS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17reduceInterleavedPiS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17reduceInterleavedPiS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduceInterleaved.hip"
.globl _Z32__device_stub__reduceInterleavedPiS_j # -- Begin function _Z32__device_stub__reduceInterleavedPiS_j
.p2align 4, 0x90
.type _Z32__device_stub__reduceInterleavedPiS_j,@function
_Z32__device_stub__reduceInterleavedPiS_j: # @_Z32__device_stub__reduceInterleavedPiS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17reduceInterleavedPiS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z32__device_stub__reduceInterleavedPiS_j, .Lfunc_end0-_Z32__device_stub__reduceInterleavedPiS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17reduceInterleavedPiS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17reduceInterleavedPiS_j,@object # @_Z17reduceInterleavedPiS_j
.section .rodata,"a",@progbits
.globl _Z17reduceInterleavedPiS_j
.p2align 3, 0x0
_Z17reduceInterleavedPiS_j:
.quad _Z32__device_stub__reduceInterleavedPiS_j
.size _Z17reduceInterleavedPiS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17reduceInterleavedPiS_j"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__reduceInterleavedPiS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17reduceInterleavedPiS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Copyright (c) 2020 Saurabh Yadav
//
// This software is released under the MIT License.
// https://opensource.org/licenses/MIT
/* This example to analyse practically the performance benefits of
using tiled algorithms that use shared memory of the gpu */
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <math.h>
#include <cuda_runtime.h>
#define MAT_A_TOTAL_ROWS 4000U
#define MAT_A_TOTAL_COLS 5000U
#define MAT_B_TOTAL_ROWS MAT_A_TOTAL_COLS
#define MAT_B_TOTAL_COLS 6000U
#define TILE_WIDTH 16
__global__
void init_matrix(float *matrix, int width, int height, float val) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = idx; i < width * height; i += gridDim.x * blockDim.x) {
matrix[i]=val;
}
}
__global__
void tiled_matrix_multiplication(float * mat_A_arr, float * mat_B_arr, float * mat_C_arr,
int num_A_rows, int num_A_cols, int num_B_cols) {
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH]; // tiled shared memory for matrix A
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH]; // tiled shared memory for matrix B
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = ty + by * blockDim.y;
int col = tx + bx * blockDim.x;
float c_value = 0.0;
for(size_t t=0; t<((num_A_cols-1)/TILE_WIDTH+1); t++) {
if( row < num_A_rows && (t*TILE_WIDTH+tx) < num_A_cols ) {
ds_A[ty][tx] = mat_A_arr[row*num_A_cols + t*TILE_WIDTH+tx];
} else {
ds_A[ty][tx] = 0.0;
}
if( (t*TILE_WIDTH+ty) < num_A_cols && col < num_B_cols ) {
ds_B[ty][tx] = mat_B_arr[(t*TILE_WIDTH+ty)*num_B_cols + col];
} else {
ds_B[ty][tx] = 0.0;
}
__syncthreads();
for(size_t i=0; i<TILE_WIDTH; i++) {
c_value += ds_A[ty][i] * ds_B[i][tx];
}
__syncthreads();
}
if (row < num_A_rows && col < num_B_cols) {
mat_C_arr[row*num_B_cols + col] = c_value;
}
}
int main() {
cudaError_t err = cudaSuccess;
float *mat_A, *mat_B, *mat_C;
size_t memsize_A = MAT_A_TOTAL_ROWS * MAT_A_TOTAL_COLS * sizeof(float);
size_t memsize_B = MAT_B_TOTAL_ROWS * MAT_B_TOTAL_COLS * sizeof(float);
size_t memsize_C = MAT_A_TOTAL_ROWS * MAT_B_TOTAL_COLS * sizeof(float);
/* Allocate memories for the matrices*/
err = cudaMallocManaged(&mat_A, memsize_A);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix A (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMallocManaged(&mat_B, memsize_B);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix B (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMallocManaged(&mat_C, memsize_C);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix C (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Initialize matrices A and B */
int blocksize_for_init = 256;
int blocks_for_matA = (MAT_A_TOTAL_ROWS*MAT_A_TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
int blocks_for_matB = (MAT_B_TOTAL_ROWS*MAT_B_TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
init_matrix<<<blocks_for_matA, blocksize_for_init>>>(mat_A, MAT_A_TOTAL_COLS,
MAT_A_TOTAL_ROWS, 1);
init_matrix<<<blocks_for_matB, blocksize_for_init>>>(mat_B, MAT_B_TOTAL_COLS,
MAT_B_TOTAL_ROWS, 2);
err = cudaGetLastError();
if( err != cudaSuccess) {
fprintf(stderr, "Failed to initialize matrix (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Do the matrix addition */
size_t blocksizeX = TILE_WIDTH;
size_t blocksizeY = TILE_WIDTH;
dim3 DimGrid( (MAT_B_TOTAL_COLS-1)/blocksizeX + 1, (MAT_A_TOTAL_ROWS-1)/blocksizeY + 1);
dim3 DimBlock( blocksizeX, blocksizeY);
tiled_matrix_multiplication<<<DimGrid, DimBlock>>>(mat_A, mat_B, mat_C,
MAT_A_TOTAL_ROWS, MAT_A_TOTAL_COLS, MAT_B_TOTAL_COLS);
err = cudaGetLastError();
if( err != cudaSuccess) {
fprintf(stderr, "Failed to perform matrix addition (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaDeviceSynchronize();
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z27tiled_matrix_multiplicationPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ULDC UR6, c[0x0][0x17c] ; /* 0x00005f0000067ab9 */
/* 0x000fe20000000800 */
/*0020*/ S2R R25, SR_CTAID.X ; /* 0x0000000000197919 */
/* 0x000e220000002500 */
/*0030*/ UIADD3 UR4, UR6, -0x1, URZ ; /* 0xffffffff06047890 */
/* 0x000fe2000fffe03f */
/*0040*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0060*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0070*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fc60008011404 */
/*0080*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002600 */
/*0090*/ ULEA.HI UR5, UR5, UR4, URZ, 0x4 ; /* 0x0000000405057291 */
/* 0x000fc6000f8f203f */
/*00a0*/ S2R R16, SR_TID.Y ; /* 0x0000000000107919 */
/* 0x000e620000002200 */
/*00b0*/ ULEA.HI.SX32 UR5, UR5, 0x1, 0x1c ; /* 0x0000000105057891 */
/* 0x000fcc000f8fe23f */
/*00c0*/ ISETP.NE.AND P1, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fe2000bf25270 */
/*00d0*/ IMAD R24, R25, c[0x0][0x0], R2 ; /* 0x0000000019187a24 */
/* 0x001fca00078e0202 */
/*00e0*/ ISETP.GE.AND P0, PT, R24, c[0x0][0x180], PT ; /* 0x0000600018007a0c */
/* 0x000fe20003f06270 */
/*00f0*/ IMAD R3, R3, c[0x0][0x4], R16 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0210 */
/*0100*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*0110*/ @!P1 BRA 0x650 ; /* 0x0000053000009947 */
/* 0x000fd80003800000 */
/*0120*/ SHF.R.S32.HI R25, RZ, 0x1f, R24 ; /* 0x0000001fff197819 */
/* 0x000fe20000011418 */
/*0130*/ IMAD R5, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003057a24 */
/* 0x000fe200078e02ff */
/*0140*/ SHF.R.S32.HI R18, RZ, 0x1f, R2 ; /* 0x0000001fff127819 */
/* 0x000fe20000011402 */
/*0150*/ IMAD.SHL.U32 R17, R16.reuse, 0x40, RZ ; /* 0x0000004010117824 */
/* 0x040fe200078e00ff */
/*0160*/ SHF.R.S32.HI R4, RZ, 0x1f, R16 ; /* 0x0000001fff047819 */
/* 0x000fe20000011410 */
/*0170*/ IMAD.WIDE R6, R16, c[0x0][0x180], R24 ; /* 0x0000600010067a25 */
/* 0x000fe200078e0218 */
/*0180*/ IADD3 R0, P1, R5.reuse, R2.reuse, RZ ; /* 0x0000000205007210 */
/* 0x0c0fe20007f3e0ff */
/*0190*/ USHF.R.S32.HI UR7, URZ, 0x1f, UR5 ; /* 0x0000001f3f077899 */
/* 0x000fe20008011405 */
/*01a0*/ MOV R19, R2 ; /* 0x0000000200137202 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*01c0*/ LEA.HI.X.SX32 R5, R5, R18, 0x1, P1 ; /* 0x0000001205057211 */
/* 0x000fe200008f0eff */
/*01d0*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR6 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011406 */
/*01e0*/ LEA R20, P2, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000147a11 */
/* 0x000fc400078410ff */
/*01f0*/ LEA R22, P1, R6, c[0x0][0x168], 0x2 ; /* 0x00005a0006167a11 */
/* 0x000fe400078210ff */
/*0200*/ LEA.HI.X R5, R0, c[0x0][0x164], R5, 0x2, P2 ; /* 0x0000590000057a11 */
/* 0x000fe200010f1405 */
/*0210*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0220*/ LEA.HI.X R23, R6, c[0x0][0x16c], R7, 0x2, P1 ; /* 0x00005b0006177a11 */
/* 0x000fe400008f1407 */
/*0230*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fe40000000f00 */
/*0240*/ LEA R7, R2, R17, 0x2 ; /* 0x0000001102077211 */
/* 0x000fe400078e10ff */
/*0250*/ ISETP.GE.U32.AND P1, PT, R19, c[0x0][0x17c], PT ; /* 0x00005f0013007a0c */
/* 0x000fe20003f26070 */
/*0260*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0270*/ ISETP.GE.U32.AND P2, PT, R16, c[0x0][0x17c], PT ; /* 0x00005f0010007a0c */
/* 0x000fc40003f46070 */
/*0280*/ ISETP.GE.U32.AND.EX P1, PT, R18, UR4, PT, P1 ; /* 0x0000000412007c0c */
/* 0x000fe4000bf26110 */
/*0290*/ ISETP.GE.U32.AND.EX P2, PT, R4, UR4, PT, P2 ; /* 0x0000000404007c0c */
/* 0x000fe4000bf46120 */
/*02a0*/ ISETP.GE.OR P1, PT, R3, c[0x0][0x178], P1 ; /* 0x00005e0003007a0c */
/* 0x000fe40000f26670 */
/*02b0*/ ISETP.GE.OR P2, PT, R24, c[0x0][0x180], P2 ; /* 0x0000600018007a0c */
/* 0x000fe40001746670 */
/*02c0*/ MOV R26, RZ ; /* 0x000000ff001a7202 */
/* 0x000fd20000000f00 */
/*02d0*/ @!P1 IMAD.MOV.U32 R21, RZ, RZ, R5 ; /* 0x000000ffff159224 */
/* 0x000fe400078e0005 */
/*02e0*/ @!P2 LDG.E R8, [R22.64] ; /* 0x000000081608a981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ @!P1 LDG.E R26, [R20.64] ; /* 0x00000008141a9981 */
/* 0x0000e2000c1e1900 */
/*0300*/ IADD3 R0, P1, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007f3e0ff */
/*0310*/ IADD3 R19, P2, R19, 0x10, RZ ; /* 0x0000001013137810 */
/* 0x000fe40007f5e0ff */
/*0320*/ IADD3 R16, P3, R16, 0x10, RZ ; /* 0x0000001010107810 */
/* 0x000fe20007f7e0ff */
/*0330*/ IMAD.X R6, RZ, RZ, R6, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0606 */
/*0340*/ ISETP.GE.U32.AND P1, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fe2000bf26070 */
/*0350*/ IMAD.X R18, RZ, RZ, R18, P2 ; /* 0x000000ffff127224 */
/* 0x000fe200010e0612 */
/*0360*/ IADD3.X R4, RZ, R4, RZ, P3, !PT ; /* 0x00000004ff047210 */
/* 0x000fc40001ffe4ff */
/*0370*/ ISETP.GE.U32.AND.EX P1, PT, R6, UR7, PT, P1 ; /* 0x0000000706007c0c */
/* 0x000fe4000bf26110 */
/*0380*/ IADD3 R20, P4, R20, 0x40, RZ ; /* 0x0000004014147810 */
/* 0x001fc80007f9e0ff */
/*0390*/ IADD3.X R5, RZ, R5, RZ, P4, !PT ; /* 0x00000005ff057210 */
/* 0x000fe200027fe4ff */
/*03a0*/ STS [R7+0x400], R8 ; /* 0x0004000807007388 */
/* 0x004fe80000000800 */
/*03b0*/ STS [R7], R26 ; /* 0x0000001a07007388 */
/* 0x008fe80000000800 */
/*03c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03d0*/ LDS R9, [R2.X4+0x400] ; /* 0x0004000002097984 */
/* 0x000fe80000004800 */
/*03e0*/ LDS.128 R12, [R17] ; /* 0x00000000110c7984 */
/* 0x000e280000000c00 */
/*03f0*/ LDS R28, [R2.X4+0x440] ; /* 0x00044000021c7984 */
/* 0x000e680000004800 */
/*0400*/ LDS R27, [R2.X4+0x480] ; /* 0x00048000021b7984 */
/* 0x000ea80000004800 */
/*0410*/ LDS R26, [R2.X4+0x540] ; /* 0x00054000021a7984 */
/* 0x000fe80000004800 */
/*0420*/ LDS R21, [R2.X4+0x580] ; /* 0x0005800002157984 */
/* 0x000fe20000004800 */
/*0430*/ FFMA R10, R9, R12, R11 ; /* 0x0000000c090a7223 */
/* 0x001fc6000000000b */
/*0440*/ LDS R12, [R2.X4+0x4c0] ; /* 0x0004c000020c7984 */
/* 0x000e220000004800 */
/*0450*/ FFMA R28, R28, R13, R10 ; /* 0x0000000d1c1c7223 */
/* 0x002fc6000000000a */
/*0460*/ LDS R13, [R2.X4+0x500] ; /* 0x00050000020d7984 */
/* 0x000fe20000004800 */
/*0470*/ FFMA R14, R27, R14, R28 ; /* 0x0000000e1b0e7223 */
/* 0x004fc6000000001c */
/*0480*/ LDS.128 R8, [R17+0x10] ; /* 0x0000100011087984 */
/* 0x000e620000000c00 */
/*0490*/ FFMA R12, R12, R15, R14 ; /* 0x0000000f0c0c7223 */
/* 0x001fc8000000000e */
/*04a0*/ FFMA R12, R13, R8, R12 ; /* 0x000000080d0c7223 */
/* 0x002fe4000000000c */
/*04b0*/ LDS R8, [R2.X4+0x5c0] ; /* 0x0005c00002087984 */
/* 0x000e240000004800 */
/*04c0*/ FFMA R27, R26, R9, R12 ; /* 0x000000091a1b7223 */
/* 0x000fe4000000000c */
/*04d0*/ LDS R9, [R2.X4+0x600] ; /* 0x0006000002097984 */
/* 0x000fe40000004800 */
/*04e0*/ FFMA R10, R21, R10, R27 ; /* 0x0000000a150a7223 */
/* 0x000fe4000000001b */
/*04f0*/ LDS.128 R12, [R17+0x20] ; /* 0x00002000110c7984 */
/* 0x000e680000000c00 */
/*0500*/ LDS R26, [R2.X4+0x640] ; /* 0x00064000021a7984 */
/* 0x000ea80000004800 */
/*0510*/ LDS R21, [R2.X4+0x680] ; /* 0x0006800002157984 */
/* 0x000ee20000004800 */
/*0520*/ FFMA R8, R8, R11, R10 ; /* 0x0000000b08087223 */
/* 0x001fc8000000000a */
/*0530*/ FFMA R8, R9, R12, R8 ; /* 0x0000000c09087223 */
/* 0x002fe40000000008 */
/*0540*/ LDS R12, [R2.X4+0x6c0] ; /* 0x0006c000020c7984 */
/* 0x000e240000004800 */
/*0550*/ FFMA R26, R26, R13, R8 ; /* 0x0000000d1a1a7223 */
/* 0x004fe40000000008 */
/*0560*/ LDS R13, [R2.X4+0x700] ; /* 0x00070000020d7984 */
/* 0x000fe40000004800 */
/*0570*/ FFMA R27, R21, R14, R26 ; /* 0x0000000e151b7223 */
/* 0x008fe4000000001a */
/*0580*/ LDS.128 R8, [R17+0x30] ; /* 0x0000300011087984 */
/* 0x000e680000000c00 */
/*0590*/ LDS R26, [R2.X4+0x740] ; /* 0x00074000021a7984 */
/* 0x000ea80000004800 */
/*05a0*/ LDS R21, [R2.X4+0x780] ; /* 0x0007800002157984 */
/* 0x000ee80000004800 */
/*05b0*/ LDS R14, [R2.X4+0x7c0] ; /* 0x0007c000020e7984 */
/* 0x000f220000004800 */
/*05c0*/ FFMA R12, R12, R15, R27 ; /* 0x0000000f0c0c7223 */
/* 0x001fc8000000001b */
/*05d0*/ FFMA R8, R13, R8, R12 ; /* 0x000000080d087223 */
/* 0x002fe2000000000c */
/*05e0*/ HFMA2.MMA R13, -RZ, RZ, 0, 3.814697265625e-06 ; /* 0x00000040ff0d7435 */
/* 0x000fc600000001ff */
/*05f0*/ FFMA R8, R26, R9, R8 ; /* 0x000000091a087223 */
/* 0x004fc80000000008 */
/*0600*/ FFMA R8, R21, R10, R8 ; /* 0x0000000a15087223 */
/* 0x008fc60000000008 */
/*0610*/ IMAD.WIDE R22, R13, c[0x0][0x180], R22 ; /* 0x000060000d167a25 */
/* 0x000fc800078e0216 */
/*0620*/ FFMA R11, R14, R11, R8 ; /* 0x0000000b0e0b7223 */
/* 0x010fe20000000008 */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0640*/ @!P1 BRA 0x250 ; /* 0xfffffc0000009947 */
/* 0x000fea000383ffff */
/*0650*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0660*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0670*/ IMAD R3, R3, c[0x0][0x180], R24 ; /* 0x0000600003037a24 */
/* 0x000fc800078e0218 */
/*0680*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0690*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101908 */
/*06a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06b0*/ BRA 0x6b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11init_matrixPfiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ MOV R9, c[0x0][0xc] ; /* 0x0000030000097a02 */
/* 0x000fce0000000f00 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD R0, R9, c[0x0][0x0], R0 ; /* 0x0000000009007a24 */
/* 0x000fe200078e0200 */
/*00e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101906 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0100*/ @!P0 BRA 0xc0 ; /* 0xffffffb000008947 */
/* 0x001fea000383ffff */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Copyright (c) 2020 Saurabh Yadav
//
// This software is released under the MIT License.
// https://opensource.org/licenses/MIT
/* This example to analyse practically the performance benefits of
using tiled algorithms that use shared memory of the gpu */
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <math.h>
#include <cuda_runtime.h>
#define MAT_A_TOTAL_ROWS 4000U
#define MAT_A_TOTAL_COLS 5000U
#define MAT_B_TOTAL_ROWS MAT_A_TOTAL_COLS
#define MAT_B_TOTAL_COLS 6000U
#define TILE_WIDTH 16
__global__
void init_matrix(float *matrix, int width, int height, float val) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = idx; i < width * height; i += gridDim.x * blockDim.x) {
matrix[i]=val;
}
}
__global__
void tiled_matrix_multiplication(float * mat_A_arr, float * mat_B_arr, float * mat_C_arr,
int num_A_rows, int num_A_cols, int num_B_cols) {
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH]; // tiled shared memory for matrix A
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH]; // tiled shared memory for matrix B
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = ty + by * blockDim.y;
int col = tx + bx * blockDim.x;
float c_value = 0.0;
for(size_t t=0; t<((num_A_cols-1)/TILE_WIDTH+1); t++) {
if( row < num_A_rows && (t*TILE_WIDTH+tx) < num_A_cols ) {
ds_A[ty][tx] = mat_A_arr[row*num_A_cols + t*TILE_WIDTH+tx];
} else {
ds_A[ty][tx] = 0.0;
}
if( (t*TILE_WIDTH+ty) < num_A_cols && col < num_B_cols ) {
ds_B[ty][tx] = mat_B_arr[(t*TILE_WIDTH+ty)*num_B_cols + col];
} else {
ds_B[ty][tx] = 0.0;
}
__syncthreads();
for(size_t i=0; i<TILE_WIDTH; i++) {
c_value += ds_A[ty][i] * ds_B[i][tx];
}
__syncthreads();
}
if (row < num_A_rows && col < num_B_cols) {
mat_C_arr[row*num_B_cols + col] = c_value;
}
}
int main() {
cudaError_t err = cudaSuccess;
float *mat_A, *mat_B, *mat_C;
size_t memsize_A = MAT_A_TOTAL_ROWS * MAT_A_TOTAL_COLS * sizeof(float);
size_t memsize_B = MAT_B_TOTAL_ROWS * MAT_B_TOTAL_COLS * sizeof(float);
size_t memsize_C = MAT_A_TOTAL_ROWS * MAT_B_TOTAL_COLS * sizeof(float);
/* Allocate memories for the matrices*/
err = cudaMallocManaged(&mat_A, memsize_A);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix A (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMallocManaged(&mat_B, memsize_B);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix B (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMallocManaged(&mat_C, memsize_C);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix C (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Initialize matrices A and B */
int blocksize_for_init = 256;
int blocks_for_matA = (MAT_A_TOTAL_ROWS*MAT_A_TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
int blocks_for_matB = (MAT_B_TOTAL_ROWS*MAT_B_TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
init_matrix<<<blocks_for_matA, blocksize_for_init>>>(mat_A, MAT_A_TOTAL_COLS,
MAT_A_TOTAL_ROWS, 1);
init_matrix<<<blocks_for_matB, blocksize_for_init>>>(mat_B, MAT_B_TOTAL_COLS,
MAT_B_TOTAL_ROWS, 2);
err = cudaGetLastError();
if( err != cudaSuccess) {
fprintf(stderr, "Failed to initialize matrix (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Do the matrix addition */
size_t blocksizeX = TILE_WIDTH;
size_t blocksizeY = TILE_WIDTH;
dim3 DimGrid( (MAT_B_TOTAL_COLS-1)/blocksizeX + 1, (MAT_A_TOTAL_ROWS-1)/blocksizeY + 1);
dim3 DimBlock( blocksizeX, blocksizeY);
tiled_matrix_multiplication<<<DimGrid, DimBlock>>>(mat_A, mat_B, mat_C,
MAT_A_TOTAL_ROWS, MAT_A_TOTAL_COLS, MAT_B_TOTAL_COLS);
err = cudaGetLastError();
if( err != cudaSuccess) {
fprintf(stderr, "Failed to perform matrix addition (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaDeviceSynchronize();
return EXIT_SUCCESS;
} | .file "tmpxft_0007b1b4_00000000-6_tiled_matrix_multiplication.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11init_matrixPfiifPfiif
.type _Z34__device_stub__Z11init_matrixPfiifPfiif, @function
_Z34__device_stub__Z11init_matrixPfiifPfiif:
.LFB2095:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11init_matrixPfiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z34__device_stub__Z11init_matrixPfiifPfiif, .-_Z34__device_stub__Z11init_matrixPfiifPfiif
.globl _Z11init_matrixPfiif
.type _Z11init_matrixPfiif, @function
_Z11init_matrixPfiif:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11init_matrixPfiifPfiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z11init_matrixPfiif, .-_Z11init_matrixPfiif
.globl _Z54__device_stub__Z27tiled_matrix_multiplicationPfS_S_iiiPfS_S_iii
.type _Z54__device_stub__Z27tiled_matrix_multiplicationPfS_S_iiiPfS_S_iii, @function
_Z54__device_stub__Z27tiled_matrix_multiplicationPfS_S_iiiPfS_S_iii:
.LFB2097:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27tiled_matrix_multiplicationPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2097:
.size _Z54__device_stub__Z27tiled_matrix_multiplicationPfS_S_iiiPfS_S_iii, .-_Z54__device_stub__Z27tiled_matrix_multiplicationPfS_S_iiiPfS_S_iii
.globl _Z27tiled_matrix_multiplicationPfS_S_iii
.type _Z27tiled_matrix_multiplicationPfS_S_iii, @function
_Z27tiled_matrix_multiplicationPfS_S_iii:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z27tiled_matrix_multiplicationPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _Z27tiled_matrix_multiplicationPfS_S_iii, .-_Z27tiled_matrix_multiplicationPfS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Failed to allocate memory for matrix A (error code %s)!\n"
.align 8
.LC1:
.string "Failed to allocate memory for matrix B (error code %s)!\n"
.align 8
.LC2:
.string "Failed to allocate memory for matrix C (error code %s)!\n"
.align 8
.LC5:
.string "Failed to initialize matrix (error code %s)!\n"
.align 8
.LC6:
.string "Failed to perform matrix addition (error code %s)!\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $80000000, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L30
leaq 16(%rsp), %rdi
movl $1, %edx
movl $120000000, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L31
leaq 24(%rsp), %rdi
movl $1, %edx
movl $96000000, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L32
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $78125, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L23:
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $117188, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L24:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L35
movl $375, 32(%rsp)
movl $250, 36(%rsp)
movl $1, 40(%rsp)
movl $16, 44(%rsp)
movl $16, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L26:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L37
call cudaDeviceSynchronize@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movss .LC3(%rip), %xmm0
movl $4000, %edx
movl $5000, %esi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z11init_matrixPfiifPfiif
jmp .L23
.L34:
movss .LC4(%rip), %xmm0
movl $5000, %edx
movl $6000, %esi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z11init_matrixPfiifPfiif
jmp .L24
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
movl $6000, %r9d
movl $5000, %r8d
movl $4000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z54__device_stub__Z27tiled_matrix_multiplicationPfS_S_iiiPfS_S_iii
jmp .L26
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC7:
.string "_Z27tiled_matrix_multiplicationPfS_S_iii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "_Z11init_matrixPfiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2100:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z27tiled_matrix_multiplicationPfS_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z11init_matrixPfiif(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.