system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
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You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Copyright (c) 2020 Saurabh Yadav
//
// This software is released under the MIT License.
// https://opensource.org/licenses/MIT
/* This example to analyse practically the performance benefits of
using tiled algorithms that use shared memory of the gpu */
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <math.h>
#include <cuda_runtime.h>
#define MAT_A_TOTAL_ROWS 4000U
#define MAT_A_TOTAL_COLS 5000U
#define MAT_B_TOTAL_ROWS MAT_A_TOTAL_COLS
#define MAT_B_TOTAL_COLS 6000U
#define TILE_WIDTH 16
__global__
void init_matrix(float *matrix, int width, int height, float val) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = idx; i < width * height; i += gridDim.x * blockDim.x) {
matrix[i]=val;
}
}
__global__
void tiled_matrix_multiplication(float * mat_A_arr, float * mat_B_arr, float * mat_C_arr,
int num_A_rows, int num_A_cols, int num_B_cols) {
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH]; // tiled shared memory for matrix A
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH]; // tiled shared memory for matrix B
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = ty + by * blockDim.y;
int col = tx + bx * blockDim.x;
float c_value = 0.0;
for(size_t t=0; t<((num_A_cols-1)/TILE_WIDTH+1); t++) {
if( row < num_A_rows && (t*TILE_WIDTH+tx) < num_A_cols ) {
ds_A[ty][tx] = mat_A_arr[row*num_A_cols + t*TILE_WIDTH+tx];
} else {
ds_A[ty][tx] = 0.0;
}
if( (t*TILE_WIDTH+ty) < num_A_cols && col < num_B_cols ) {
ds_B[ty][tx] = mat_B_arr[(t*TILE_WIDTH+ty)*num_B_cols + col];
} else {
ds_B[ty][tx] = 0.0;
}
__syncthreads();
for(size_t i=0; i<TILE_WIDTH; i++) {
c_value += ds_A[ty][i] * ds_B[i][tx];
}
__syncthreads();
}
if (row < num_A_rows && col < num_B_cols) {
mat_C_arr[row*num_B_cols + col] = c_value;
}
}
int main() {
cudaError_t err = cudaSuccess;
float *mat_A, *mat_B, *mat_C;
size_t memsize_A = MAT_A_TOTAL_ROWS * MAT_A_TOTAL_COLS * sizeof(float);
size_t memsize_B = MAT_B_TOTAL_ROWS * MAT_B_TOTAL_COLS * sizeof(float);
size_t memsize_C = MAT_A_TOTAL_ROWS * MAT_B_TOTAL_COLS * sizeof(float);
/* Allocate memories for the matrices*/
err = cudaMallocManaged(&mat_A, memsize_A);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix A (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMallocManaged(&mat_B, memsize_B);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix B (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMallocManaged(&mat_C, memsize_C);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix C (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Initialize matrices A and B */
int blocksize_for_init = 256;
int blocks_for_matA = (MAT_A_TOTAL_ROWS*MAT_A_TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
int blocks_for_matB = (MAT_B_TOTAL_ROWS*MAT_B_TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
init_matrix<<<blocks_for_matA, blocksize_for_init>>>(mat_A, MAT_A_TOTAL_COLS,
MAT_A_TOTAL_ROWS, 1);
init_matrix<<<blocks_for_matB, blocksize_for_init>>>(mat_B, MAT_B_TOTAL_COLS,
MAT_B_TOTAL_ROWS, 2);
err = cudaGetLastError();
if( err != cudaSuccess) {
fprintf(stderr, "Failed to initialize matrix (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Do the matrix addition */
size_t blocksizeX = TILE_WIDTH;
size_t blocksizeY = TILE_WIDTH;
dim3 DimGrid( (MAT_B_TOTAL_COLS-1)/blocksizeX + 1, (MAT_A_TOTAL_ROWS-1)/blocksizeY + 1);
dim3 DimBlock( blocksizeX, blocksizeY);
tiled_matrix_multiplication<<<DimGrid, DimBlock>>>(mat_A, mat_B, mat_C,
MAT_A_TOTAL_ROWS, MAT_A_TOTAL_COLS, MAT_B_TOTAL_COLS);
err = cudaGetLastError();
if( err != cudaSuccess) {
fprintf(stderr, "Failed to perform matrix addition (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaDeviceSynchronize();
return EXIT_SUCCESS;
} | // Copyright (c) 2020 Saurabh Yadav
//
// This software is released under the MIT License.
// https://opensource.org/licenses/MIT
/* This example to analyse practically the performance benefits of
using tiled algorithms that use shared memory of the gpu */
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define MAT_A_TOTAL_ROWS 4000U
#define MAT_A_TOTAL_COLS 5000U
#define MAT_B_TOTAL_ROWS MAT_A_TOTAL_COLS
#define MAT_B_TOTAL_COLS 6000U
#define TILE_WIDTH 16
__global__
void init_matrix(float *matrix, int width, int height, float val) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = idx; i < width * height; i += gridDim.x * blockDim.x) {
matrix[i]=val;
}
}
__global__
void tiled_matrix_multiplication(float * mat_A_arr, float * mat_B_arr, float * mat_C_arr,
int num_A_rows, int num_A_cols, int num_B_cols) {
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH]; // tiled shared memory for matrix A
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH]; // tiled shared memory for matrix B
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = ty + by * blockDim.y;
int col = tx + bx * blockDim.x;
float c_value = 0.0;
for(size_t t=0; t<((num_A_cols-1)/TILE_WIDTH+1); t++) {
if( row < num_A_rows && (t*TILE_WIDTH+tx) < num_A_cols ) {
ds_A[ty][tx] = mat_A_arr[row*num_A_cols + t*TILE_WIDTH+tx];
} else {
ds_A[ty][tx] = 0.0;
}
if( (t*TILE_WIDTH+ty) < num_A_cols && col < num_B_cols ) {
ds_B[ty][tx] = mat_B_arr[(t*TILE_WIDTH+ty)*num_B_cols + col];
} else {
ds_B[ty][tx] = 0.0;
}
__syncthreads();
for(size_t i=0; i<TILE_WIDTH; i++) {
c_value += ds_A[ty][i] * ds_B[i][tx];
}
__syncthreads();
}
if (row < num_A_rows && col < num_B_cols) {
mat_C_arr[row*num_B_cols + col] = c_value;
}
}
int main() {
hipError_t err = hipSuccess;
float *mat_A, *mat_B, *mat_C;
size_t memsize_A = MAT_A_TOTAL_ROWS * MAT_A_TOTAL_COLS * sizeof(float);
size_t memsize_B = MAT_B_TOTAL_ROWS * MAT_B_TOTAL_COLS * sizeof(float);
size_t memsize_C = MAT_A_TOTAL_ROWS * MAT_B_TOTAL_COLS * sizeof(float);
/* Allocate memories for the matrices*/
err = hipMallocManaged(&mat_A, memsize_A);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix A (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMallocManaged(&mat_B, memsize_B);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix B (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMallocManaged(&mat_C, memsize_C);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix C (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Initialize matrices A and B */
int blocksize_for_init = 256;
int blocks_for_matA = (MAT_A_TOTAL_ROWS*MAT_A_TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
int blocks_for_matB = (MAT_B_TOTAL_ROWS*MAT_B_TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
init_matrix<<<blocks_for_matA, blocksize_for_init>>>(mat_A, MAT_A_TOTAL_COLS,
MAT_A_TOTAL_ROWS, 1);
init_matrix<<<blocks_for_matB, blocksize_for_init>>>(mat_B, MAT_B_TOTAL_COLS,
MAT_B_TOTAL_ROWS, 2);
err = hipGetLastError();
if( err != hipSuccess) {
fprintf(stderr, "Failed to initialize matrix (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Do the matrix addition */
size_t blocksizeX = TILE_WIDTH;
size_t blocksizeY = TILE_WIDTH;
dim3 DimGrid( (MAT_B_TOTAL_COLS-1)/blocksizeX + 1, (MAT_A_TOTAL_ROWS-1)/blocksizeY + 1);
dim3 DimBlock( blocksizeX, blocksizeY);
tiled_matrix_multiplication<<<DimGrid, DimBlock>>>(mat_A, mat_B, mat_C,
MAT_A_TOTAL_ROWS, MAT_A_TOTAL_COLS, MAT_B_TOTAL_COLS);
err = hipGetLastError();
if( err != hipSuccess) {
fprintf(stderr, "Failed to perform matrix addition (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Copyright (c) 2020 Saurabh Yadav
//
// This software is released under the MIT License.
// https://opensource.org/licenses/MIT
/* This example to analyse practically the performance benefits of
using tiled algorithms that use shared memory of the gpu */
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define MAT_A_TOTAL_ROWS 4000U
#define MAT_A_TOTAL_COLS 5000U
#define MAT_B_TOTAL_ROWS MAT_A_TOTAL_COLS
#define MAT_B_TOTAL_COLS 6000U
#define TILE_WIDTH 16
__global__
void init_matrix(float *matrix, int width, int height, float val) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = idx; i < width * height; i += gridDim.x * blockDim.x) {
matrix[i]=val;
}
}
__global__
void tiled_matrix_multiplication(float * mat_A_arr, float * mat_B_arr, float * mat_C_arr,
int num_A_rows, int num_A_cols, int num_B_cols) {
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH]; // tiled shared memory for matrix A
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH]; // tiled shared memory for matrix B
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = ty + by * blockDim.y;
int col = tx + bx * blockDim.x;
float c_value = 0.0;
for(size_t t=0; t<((num_A_cols-1)/TILE_WIDTH+1); t++) {
if( row < num_A_rows && (t*TILE_WIDTH+tx) < num_A_cols ) {
ds_A[ty][tx] = mat_A_arr[row*num_A_cols + t*TILE_WIDTH+tx];
} else {
ds_A[ty][tx] = 0.0;
}
if( (t*TILE_WIDTH+ty) < num_A_cols && col < num_B_cols ) {
ds_B[ty][tx] = mat_B_arr[(t*TILE_WIDTH+ty)*num_B_cols + col];
} else {
ds_B[ty][tx] = 0.0;
}
__syncthreads();
for(size_t i=0; i<TILE_WIDTH; i++) {
c_value += ds_A[ty][i] * ds_B[i][tx];
}
__syncthreads();
}
if (row < num_A_rows && col < num_B_cols) {
mat_C_arr[row*num_B_cols + col] = c_value;
}
}
int main() {
hipError_t err = hipSuccess;
float *mat_A, *mat_B, *mat_C;
size_t memsize_A = MAT_A_TOTAL_ROWS * MAT_A_TOTAL_COLS * sizeof(float);
size_t memsize_B = MAT_B_TOTAL_ROWS * MAT_B_TOTAL_COLS * sizeof(float);
size_t memsize_C = MAT_A_TOTAL_ROWS * MAT_B_TOTAL_COLS * sizeof(float);
/* Allocate memories for the matrices*/
err = hipMallocManaged(&mat_A, memsize_A);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix A (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMallocManaged(&mat_B, memsize_B);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix B (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMallocManaged(&mat_C, memsize_C);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix C (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Initialize matrices A and B */
int blocksize_for_init = 256;
int blocks_for_matA = (MAT_A_TOTAL_ROWS*MAT_A_TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
int blocks_for_matB = (MAT_B_TOTAL_ROWS*MAT_B_TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
init_matrix<<<blocks_for_matA, blocksize_for_init>>>(mat_A, MAT_A_TOTAL_COLS,
MAT_A_TOTAL_ROWS, 1);
init_matrix<<<blocks_for_matB, blocksize_for_init>>>(mat_B, MAT_B_TOTAL_COLS,
MAT_B_TOTAL_ROWS, 2);
err = hipGetLastError();
if( err != hipSuccess) {
fprintf(stderr, "Failed to initialize matrix (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Do the matrix addition */
size_t blocksizeX = TILE_WIDTH;
size_t blocksizeY = TILE_WIDTH;
dim3 DimGrid( (MAT_B_TOTAL_COLS-1)/blocksizeX + 1, (MAT_A_TOTAL_ROWS-1)/blocksizeY + 1);
dim3 DimBlock( blocksizeX, blocksizeY);
tiled_matrix_multiplication<<<DimGrid, DimBlock>>>(mat_A, mat_B, mat_C,
MAT_A_TOTAL_ROWS, MAT_A_TOTAL_COLS, MAT_B_TOTAL_COLS);
err = hipGetLastError();
if( err != hipSuccess) {
fprintf(stderr, "Failed to perform matrix addition (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11init_matrixPfiif
.globl _Z11init_matrixPfiif
.p2align 8
.type _Z11init_matrixPfiif,@function
_Z11init_matrixPfiif:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x8
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_mul_i32 s4, s7, s6
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[0:1], 0x10
s_load_b32 s7, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s6
s_mul_i32 s1, s7, s5
s_mov_b32 s5, 0
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s2, v2
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s5, vcc_lo, s5
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11init_matrixPfiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11init_matrixPfiif, .Lfunc_end0-_Z11init_matrixPfiif
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z27tiled_matrix_multiplicationPfS_S_iii
.globl _Z27tiled_matrix_multiplicationPfS_S_iii
.p2align 8
.type _Z27tiled_matrix_multiplicationPfS_S_iii,@function
_Z27tiled_matrix_multiplicationPfS_S_iii:
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s12, s[0:1], 0x20
v_bfe_u32 v4, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s9, -1
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_ashr_i32 s5, s4, 31
v_mad_u64_u32 v[0:1], null, s15, s3, v[4:5]
s_lshr_b32 s3, s5, 28
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_mov_b32_e32 v2, 0
s_add_i32 s4, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s2, s4, 4
v_add_co_u32 v5, s3, s2, 1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_gt_i32_e64 s2, s8, v0
s_and_b32 vcc_lo, exec_lo, s3
v_cmp_gt_i32_e64 s3, s12, v1
s_cbranch_vccnz .LBB1_15
s_mov_b32 s10, s9
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v7, v0, s10
v_ashrrev_i32_e32 v2, 31, v1
v_dual_mov_b32 v12, 0 :: v_dual_lshlrev_b32 v17, 2, v3
v_lshlrev_b32_e32 v11, 6, v4
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 2, v[1:2]
v_dual_mov_b32 v14, v12 :: v_dual_add_nc_u32 v15, 0x400, v17
v_ashrrev_i32_e32 v8, 31, v7
v_add_nc_u32_e32 v13, v11, v17
v_cmp_le_i32_e64 s9, s8, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_mov_b32 v21, 0 :: v_dual_add_nc_u32 v16, v15, v11
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_ashr_i32 s11, s10, 31
s_ashr_i32 s13, s12, 31
s_xor_b32 s3, s3, -1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v8, vcc_lo
s_mov_b64 s[4:5], 0
v_add_co_u32 v17, vcc_lo, v2, v17
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v7, vcc_lo
v_add_co_u32 v19, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v20, vcc_lo, s7, v10, vcc_lo
v_mov_b32_e32 v2, 0
.LBB1_2:
s_mov_b32 s14, s9
s_mov_b32 s6, 0
s_and_saveexec_b32 s7, s2
s_lshl_b64 s[14:15], s[4:5], 4
s_mov_b32 s6, exec_lo
v_add_co_u32 v7, vcc_lo, s14, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s15, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_cmp_le_u64_e32 vcc_lo, s[10:11], v[7:8]
v_dual_mov_b32 v7, s14 :: v_dual_mov_b32 v8, s15
s_and_not1_b32 s14, s9, exec_lo
s_and_b32 s15, vcc_lo, exec_lo
s_or_b32 s14, s14, s15
s_or_b32 exec_lo, exec_lo, s7
s_and_saveexec_b32 s7, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB1_6
s_and_not1_b32 s6, s6, exec_lo
ds_store_b32 v13, v21
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s7
s_and_saveexec_b32 s7, s6
s_cbranch_execz .LBB1_8
v_lshlrev_b64 v[9:10], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v17, v9
v_add_co_ci_u32_e32 v10, vcc_lo, v18, v10, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
ds_store_b32 v13, v9
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s7
s_lshl_b64 s[6:7], s[4:5], 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_u32 v9, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v14, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[10:11], v[9:10]
s_or_b32 s6, s3, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s7, s6
s_xor_b32 s6, exec_lo, s7
s_cbranch_execz .LBB1_10
ds_store_b32 v16, v21
.LBB1_10:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB1_12
v_mul_lo_u32 v10, v10, s12
v_mul_lo_u32 v24, v9, s13
v_mad_u64_u32 v[22:23], null, v9, s12, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v23, v23, v24, v10
v_lshlrev_b64 v[9:10], 2, v[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v19, v9
v_add_co_ci_u32_e32 v10, vcc_lo, v20, v10, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
ds_store_b32 v16, v9
.LBB1_12:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v9, v15
v_mov_b32_e32 v10, v11
s_mov_b64 s[6:7], 16
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_13:
ds_load_b32 v22, v10
ds_load_b32 v23, v9
s_add_u32 s6, s6, -1
v_add_nc_u32_e32 v10, 4, v10
v_add_nc_u32_e32 v9, 64, v9
s_addc_u32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[6:7], 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v22, v23
s_cbranch_scc0 .LBB1_13
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[5:6]
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB1_2
.LBB1_15:
v_cmp_gt_i32_e32 vcc_lo, s8, v0
v_cmp_gt_i32_e64 s2, s12, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_17
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v0, s12, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27tiled_matrix_multiplicationPfS_S_iii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z27tiled_matrix_multiplicationPfS_S_iii, .Lfunc_end1-_Z27tiled_matrix_multiplicationPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11init_matrixPfiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11init_matrixPfiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27tiled_matrix_multiplicationPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27tiled_matrix_multiplicationPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Copyright (c) 2020 Saurabh Yadav
//
// This software is released under the MIT License.
// https://opensource.org/licenses/MIT
/* This example to analyse practically the performance benefits of
using tiled algorithms that use shared memory of the gpu */
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define MAT_A_TOTAL_ROWS 4000U
#define MAT_A_TOTAL_COLS 5000U
#define MAT_B_TOTAL_ROWS MAT_A_TOTAL_COLS
#define MAT_B_TOTAL_COLS 6000U
#define TILE_WIDTH 16
__global__
void init_matrix(float *matrix, int width, int height, float val) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = idx; i < width * height; i += gridDim.x * blockDim.x) {
matrix[i]=val;
}
}
__global__
void tiled_matrix_multiplication(float * mat_A_arr, float * mat_B_arr, float * mat_C_arr,
int num_A_rows, int num_A_cols, int num_B_cols) {
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH]; // tiled shared memory for matrix A
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH]; // tiled shared memory for matrix B
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = ty + by * blockDim.y;
int col = tx + bx * blockDim.x;
float c_value = 0.0;
for(size_t t=0; t<((num_A_cols-1)/TILE_WIDTH+1); t++) {
if( row < num_A_rows && (t*TILE_WIDTH+tx) < num_A_cols ) {
ds_A[ty][tx] = mat_A_arr[row*num_A_cols + t*TILE_WIDTH+tx];
} else {
ds_A[ty][tx] = 0.0;
}
if( (t*TILE_WIDTH+ty) < num_A_cols && col < num_B_cols ) {
ds_B[ty][tx] = mat_B_arr[(t*TILE_WIDTH+ty)*num_B_cols + col];
} else {
ds_B[ty][tx] = 0.0;
}
__syncthreads();
for(size_t i=0; i<TILE_WIDTH; i++) {
c_value += ds_A[ty][i] * ds_B[i][tx];
}
__syncthreads();
}
if (row < num_A_rows && col < num_B_cols) {
mat_C_arr[row*num_B_cols + col] = c_value;
}
}
int main() {
hipError_t err = hipSuccess;
float *mat_A, *mat_B, *mat_C;
size_t memsize_A = MAT_A_TOTAL_ROWS * MAT_A_TOTAL_COLS * sizeof(float);
size_t memsize_B = MAT_B_TOTAL_ROWS * MAT_B_TOTAL_COLS * sizeof(float);
size_t memsize_C = MAT_A_TOTAL_ROWS * MAT_B_TOTAL_COLS * sizeof(float);
/* Allocate memories for the matrices*/
err = hipMallocManaged(&mat_A, memsize_A);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix A (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMallocManaged(&mat_B, memsize_B);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix B (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMallocManaged(&mat_C, memsize_C);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix C (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Initialize matrices A and B */
int blocksize_for_init = 256;
int blocks_for_matA = (MAT_A_TOTAL_ROWS*MAT_A_TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
int blocks_for_matB = (MAT_B_TOTAL_ROWS*MAT_B_TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
init_matrix<<<blocks_for_matA, blocksize_for_init>>>(mat_A, MAT_A_TOTAL_COLS,
MAT_A_TOTAL_ROWS, 1);
init_matrix<<<blocks_for_matB, blocksize_for_init>>>(mat_B, MAT_B_TOTAL_COLS,
MAT_B_TOTAL_ROWS, 2);
err = hipGetLastError();
if( err != hipSuccess) {
fprintf(stderr, "Failed to initialize matrix (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Do the matrix addition */
size_t blocksizeX = TILE_WIDTH;
size_t blocksizeY = TILE_WIDTH;
dim3 DimGrid( (MAT_B_TOTAL_COLS-1)/blocksizeX + 1, (MAT_A_TOTAL_ROWS-1)/blocksizeY + 1);
dim3 DimBlock( blocksizeX, blocksizeY);
tiled_matrix_multiplication<<<DimGrid, DimBlock>>>(mat_A, mat_B, mat_C,
MAT_A_TOTAL_ROWS, MAT_A_TOTAL_COLS, MAT_B_TOTAL_COLS);
err = hipGetLastError();
if( err != hipSuccess) {
fprintf(stderr, "Failed to perform matrix addition (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
return EXIT_SUCCESS;
} | .text
.file "tiled_matrix_multiplication.hip"
.globl _Z26__device_stub__init_matrixPfiif # -- Begin function _Z26__device_stub__init_matrixPfiif
.p2align 4, 0x90
.type _Z26__device_stub__init_matrixPfiif,@function
_Z26__device_stub__init_matrixPfiif: # @_Z26__device_stub__init_matrixPfiif
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11init_matrixPfiif, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__init_matrixPfiif, .Lfunc_end0-_Z26__device_stub__init_matrixPfiif
.cfi_endproc
# -- End function
.globl _Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii # -- Begin function _Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii
.p2align 4, 0x90
.type _Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii,@function
_Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii: # @_Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27tiled_matrix_multiplicationPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii, .Lfunc_end1-_Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $176, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -16
leaq 104(%rsp), %rdi
movl $80000000, %esi # imm = 0x4C4B400
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB2_1
# %bb.3:
leaq 96(%rsp), %rdi
movl $120000000, %esi # imm = 0x7270E00
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB2_4
# %bb.5:
leaq 168(%rsp), %rdi
movl $96000000, %esi # imm = 0x5B8D800
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB2_6
# %bb.7:
movabsq $4294967552, %rbx # imm = 0x100000100
leaq 77869(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 104(%rsp), %rax
movq %rax, 80(%rsp)
movl $5000, 24(%rsp) # imm = 0x1388
movl $4000, 16(%rsp) # imm = 0xFA0
movl $1065353216, 12(%rsp) # imm = 0x3F800000
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11init_matrixPfiif, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_9:
leaq 116932(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq 96(%rsp), %rax
movq %rax, 80(%rsp)
movl $6000, 24(%rsp) # imm = 0x1770
movl $5000, 16(%rsp) # imm = 0x1388
movl $1073741824, 12(%rsp) # imm = 0x40000000
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11init_matrixPfiif, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_12
# %bb.13:
movabsq $1073741824375, %rdi # imm = 0xFA00000177
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movq 168(%rsp), %rdx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movl $4000, 12(%rsp) # imm = 0xFA0
movl $5000, 92(%rsp) # imm = 0x1388
movl $6000, 88(%rsp) # imm = 0x1770
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 92(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z27tiled_matrix_multiplicationPfS_S_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_16
# %bb.17:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB2_2
.LBB2_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB2_2
.LBB2_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
.LBB2_2:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11init_matrixPfiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27tiled_matrix_multiplicationPfS_S_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11init_matrixPfiif,@object # @_Z11init_matrixPfiif
.section .rodata,"a",@progbits
.globl _Z11init_matrixPfiif
.p2align 3, 0x0
_Z11init_matrixPfiif:
.quad _Z26__device_stub__init_matrixPfiif
.size _Z11init_matrixPfiif, 8
.type _Z27tiled_matrix_multiplicationPfS_S_iii,@object # @_Z27tiled_matrix_multiplicationPfS_S_iii
.globl _Z27tiled_matrix_multiplicationPfS_S_iii
.p2align 3, 0x0
_Z27tiled_matrix_multiplicationPfS_S_iii:
.quad _Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii
.size _Z27tiled_matrix_multiplicationPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate memory for matrix A (error code %s)!\n"
.size .L.str, 57
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to allocate memory for matrix B (error code %s)!\n"
.size .L.str.1, 57
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate memory for matrix C (error code %s)!\n"
.size .L.str.2, 57
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to initialize matrix (error code %s)!\n"
.size .L.str.3, 46
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to perform matrix addition (error code %s)!\n"
.size .L.str.4, 52
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11init_matrixPfiif"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z27tiled_matrix_multiplicationPfS_S_iii"
.size .L__unnamed_2, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__init_matrixPfiif
.addrsig_sym _Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11init_matrixPfiif
.addrsig_sym _Z27tiled_matrix_multiplicationPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z27tiled_matrix_multiplicationPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ULDC UR6, c[0x0][0x17c] ; /* 0x00005f0000067ab9 */
/* 0x000fe20000000800 */
/*0020*/ S2R R25, SR_CTAID.X ; /* 0x0000000000197919 */
/* 0x000e220000002500 */
/*0030*/ UIADD3 UR4, UR6, -0x1, URZ ; /* 0xffffffff06047890 */
/* 0x000fe2000fffe03f */
/*0040*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0060*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0070*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fc60008011404 */
/*0080*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002600 */
/*0090*/ ULEA.HI UR5, UR5, UR4, URZ, 0x4 ; /* 0x0000000405057291 */
/* 0x000fc6000f8f203f */
/*00a0*/ S2R R16, SR_TID.Y ; /* 0x0000000000107919 */
/* 0x000e620000002200 */
/*00b0*/ ULEA.HI.SX32 UR5, UR5, 0x1, 0x1c ; /* 0x0000000105057891 */
/* 0x000fcc000f8fe23f */
/*00c0*/ ISETP.NE.AND P1, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fe2000bf25270 */
/*00d0*/ IMAD R24, R25, c[0x0][0x0], R2 ; /* 0x0000000019187a24 */
/* 0x001fca00078e0202 */
/*00e0*/ ISETP.GE.AND P0, PT, R24, c[0x0][0x180], PT ; /* 0x0000600018007a0c */
/* 0x000fe20003f06270 */
/*00f0*/ IMAD R3, R3, c[0x0][0x4], R16 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0210 */
/*0100*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*0110*/ @!P1 BRA 0x650 ; /* 0x0000053000009947 */
/* 0x000fd80003800000 */
/*0120*/ SHF.R.S32.HI R25, RZ, 0x1f, R24 ; /* 0x0000001fff197819 */
/* 0x000fe20000011418 */
/*0130*/ IMAD R5, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003057a24 */
/* 0x000fe200078e02ff */
/*0140*/ SHF.R.S32.HI R18, RZ, 0x1f, R2 ; /* 0x0000001fff127819 */
/* 0x000fe20000011402 */
/*0150*/ IMAD.SHL.U32 R17, R16.reuse, 0x40, RZ ; /* 0x0000004010117824 */
/* 0x040fe200078e00ff */
/*0160*/ SHF.R.S32.HI R4, RZ, 0x1f, R16 ; /* 0x0000001fff047819 */
/* 0x000fe20000011410 */
/*0170*/ IMAD.WIDE R6, R16, c[0x0][0x180], R24 ; /* 0x0000600010067a25 */
/* 0x000fe200078e0218 */
/*0180*/ IADD3 R0, P1, R5.reuse, R2.reuse, RZ ; /* 0x0000000205007210 */
/* 0x0c0fe20007f3e0ff */
/*0190*/ USHF.R.S32.HI UR7, URZ, 0x1f, UR5 ; /* 0x0000001f3f077899 */
/* 0x000fe20008011405 */
/*01a0*/ MOV R19, R2 ; /* 0x0000000200137202 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*01c0*/ LEA.HI.X.SX32 R5, R5, R18, 0x1, P1 ; /* 0x0000001205057211 */
/* 0x000fe200008f0eff */
/*01d0*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR6 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011406 */
/*01e0*/ LEA R20, P2, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000147a11 */
/* 0x000fc400078410ff */
/*01f0*/ LEA R22, P1, R6, c[0x0][0x168], 0x2 ; /* 0x00005a0006167a11 */
/* 0x000fe400078210ff */
/*0200*/ LEA.HI.X R5, R0, c[0x0][0x164], R5, 0x2, P2 ; /* 0x0000590000057a11 */
/* 0x000fe200010f1405 */
/*0210*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0220*/ LEA.HI.X R23, R6, c[0x0][0x16c], R7, 0x2, P1 ; /* 0x00005b0006177a11 */
/* 0x000fe400008f1407 */
/*0230*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fe40000000f00 */
/*0240*/ LEA R7, R2, R17, 0x2 ; /* 0x0000001102077211 */
/* 0x000fe400078e10ff */
/*0250*/ ISETP.GE.U32.AND P1, PT, R19, c[0x0][0x17c], PT ; /* 0x00005f0013007a0c */
/* 0x000fe20003f26070 */
/*0260*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0270*/ ISETP.GE.U32.AND P2, PT, R16, c[0x0][0x17c], PT ; /* 0x00005f0010007a0c */
/* 0x000fc40003f46070 */
/*0280*/ ISETP.GE.U32.AND.EX P1, PT, R18, UR4, PT, P1 ; /* 0x0000000412007c0c */
/* 0x000fe4000bf26110 */
/*0290*/ ISETP.GE.U32.AND.EX P2, PT, R4, UR4, PT, P2 ; /* 0x0000000404007c0c */
/* 0x000fe4000bf46120 */
/*02a0*/ ISETP.GE.OR P1, PT, R3, c[0x0][0x178], P1 ; /* 0x00005e0003007a0c */
/* 0x000fe40000f26670 */
/*02b0*/ ISETP.GE.OR P2, PT, R24, c[0x0][0x180], P2 ; /* 0x0000600018007a0c */
/* 0x000fe40001746670 */
/*02c0*/ MOV R26, RZ ; /* 0x000000ff001a7202 */
/* 0x000fd20000000f00 */
/*02d0*/ @!P1 IMAD.MOV.U32 R21, RZ, RZ, R5 ; /* 0x000000ffff159224 */
/* 0x000fe400078e0005 */
/*02e0*/ @!P2 LDG.E R8, [R22.64] ; /* 0x000000081608a981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ @!P1 LDG.E R26, [R20.64] ; /* 0x00000008141a9981 */
/* 0x0000e2000c1e1900 */
/*0300*/ IADD3 R0, P1, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007f3e0ff */
/*0310*/ IADD3 R19, P2, R19, 0x10, RZ ; /* 0x0000001013137810 */
/* 0x000fe40007f5e0ff */
/*0320*/ IADD3 R16, P3, R16, 0x10, RZ ; /* 0x0000001010107810 */
/* 0x000fe20007f7e0ff */
/*0330*/ IMAD.X R6, RZ, RZ, R6, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0606 */
/*0340*/ ISETP.GE.U32.AND P1, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fe2000bf26070 */
/*0350*/ IMAD.X R18, RZ, RZ, R18, P2 ; /* 0x000000ffff127224 */
/* 0x000fe200010e0612 */
/*0360*/ IADD3.X R4, RZ, R4, RZ, P3, !PT ; /* 0x00000004ff047210 */
/* 0x000fc40001ffe4ff */
/*0370*/ ISETP.GE.U32.AND.EX P1, PT, R6, UR7, PT, P1 ; /* 0x0000000706007c0c */
/* 0x000fe4000bf26110 */
/*0380*/ IADD3 R20, P4, R20, 0x40, RZ ; /* 0x0000004014147810 */
/* 0x001fc80007f9e0ff */
/*0390*/ IADD3.X R5, RZ, R5, RZ, P4, !PT ; /* 0x00000005ff057210 */
/* 0x000fe200027fe4ff */
/*03a0*/ STS [R7+0x400], R8 ; /* 0x0004000807007388 */
/* 0x004fe80000000800 */
/*03b0*/ STS [R7], R26 ; /* 0x0000001a07007388 */
/* 0x008fe80000000800 */
/*03c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03d0*/ LDS R9, [R2.X4+0x400] ; /* 0x0004000002097984 */
/* 0x000fe80000004800 */
/*03e0*/ LDS.128 R12, [R17] ; /* 0x00000000110c7984 */
/* 0x000e280000000c00 */
/*03f0*/ LDS R28, [R2.X4+0x440] ; /* 0x00044000021c7984 */
/* 0x000e680000004800 */
/*0400*/ LDS R27, [R2.X4+0x480] ; /* 0x00048000021b7984 */
/* 0x000ea80000004800 */
/*0410*/ LDS R26, [R2.X4+0x540] ; /* 0x00054000021a7984 */
/* 0x000fe80000004800 */
/*0420*/ LDS R21, [R2.X4+0x580] ; /* 0x0005800002157984 */
/* 0x000fe20000004800 */
/*0430*/ FFMA R10, R9, R12, R11 ; /* 0x0000000c090a7223 */
/* 0x001fc6000000000b */
/*0440*/ LDS R12, [R2.X4+0x4c0] ; /* 0x0004c000020c7984 */
/* 0x000e220000004800 */
/*0450*/ FFMA R28, R28, R13, R10 ; /* 0x0000000d1c1c7223 */
/* 0x002fc6000000000a */
/*0460*/ LDS R13, [R2.X4+0x500] ; /* 0x00050000020d7984 */
/* 0x000fe20000004800 */
/*0470*/ FFMA R14, R27, R14, R28 ; /* 0x0000000e1b0e7223 */
/* 0x004fc6000000001c */
/*0480*/ LDS.128 R8, [R17+0x10] ; /* 0x0000100011087984 */
/* 0x000e620000000c00 */
/*0490*/ FFMA R12, R12, R15, R14 ; /* 0x0000000f0c0c7223 */
/* 0x001fc8000000000e */
/*04a0*/ FFMA R12, R13, R8, R12 ; /* 0x000000080d0c7223 */
/* 0x002fe4000000000c */
/*04b0*/ LDS R8, [R2.X4+0x5c0] ; /* 0x0005c00002087984 */
/* 0x000e240000004800 */
/*04c0*/ FFMA R27, R26, R9, R12 ; /* 0x000000091a1b7223 */
/* 0x000fe4000000000c */
/*04d0*/ LDS R9, [R2.X4+0x600] ; /* 0x0006000002097984 */
/* 0x000fe40000004800 */
/*04e0*/ FFMA R10, R21, R10, R27 ; /* 0x0000000a150a7223 */
/* 0x000fe4000000001b */
/*04f0*/ LDS.128 R12, [R17+0x20] ; /* 0x00002000110c7984 */
/* 0x000e680000000c00 */
/*0500*/ LDS R26, [R2.X4+0x640] ; /* 0x00064000021a7984 */
/* 0x000ea80000004800 */
/*0510*/ LDS R21, [R2.X4+0x680] ; /* 0x0006800002157984 */
/* 0x000ee20000004800 */
/*0520*/ FFMA R8, R8, R11, R10 ; /* 0x0000000b08087223 */
/* 0x001fc8000000000a */
/*0530*/ FFMA R8, R9, R12, R8 ; /* 0x0000000c09087223 */
/* 0x002fe40000000008 */
/*0540*/ LDS R12, [R2.X4+0x6c0] ; /* 0x0006c000020c7984 */
/* 0x000e240000004800 */
/*0550*/ FFMA R26, R26, R13, R8 ; /* 0x0000000d1a1a7223 */
/* 0x004fe40000000008 */
/*0560*/ LDS R13, [R2.X4+0x700] ; /* 0x00070000020d7984 */
/* 0x000fe40000004800 */
/*0570*/ FFMA R27, R21, R14, R26 ; /* 0x0000000e151b7223 */
/* 0x008fe4000000001a */
/*0580*/ LDS.128 R8, [R17+0x30] ; /* 0x0000300011087984 */
/* 0x000e680000000c00 */
/*0590*/ LDS R26, [R2.X4+0x740] ; /* 0x00074000021a7984 */
/* 0x000ea80000004800 */
/*05a0*/ LDS R21, [R2.X4+0x780] ; /* 0x0007800002157984 */
/* 0x000ee80000004800 */
/*05b0*/ LDS R14, [R2.X4+0x7c0] ; /* 0x0007c000020e7984 */
/* 0x000f220000004800 */
/*05c0*/ FFMA R12, R12, R15, R27 ; /* 0x0000000f0c0c7223 */
/* 0x001fc8000000001b */
/*05d0*/ FFMA R8, R13, R8, R12 ; /* 0x000000080d087223 */
/* 0x002fe2000000000c */
/*05e0*/ HFMA2.MMA R13, -RZ, RZ, 0, 3.814697265625e-06 ; /* 0x00000040ff0d7435 */
/* 0x000fc600000001ff */
/*05f0*/ FFMA R8, R26, R9, R8 ; /* 0x000000091a087223 */
/* 0x004fc80000000008 */
/*0600*/ FFMA R8, R21, R10, R8 ; /* 0x0000000a15087223 */
/* 0x008fc60000000008 */
/*0610*/ IMAD.WIDE R22, R13, c[0x0][0x180], R22 ; /* 0x000060000d167a25 */
/* 0x000fc800078e0216 */
/*0620*/ FFMA R11, R14, R11, R8 ; /* 0x0000000b0e0b7223 */
/* 0x010fe20000000008 */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0640*/ @!P1 BRA 0x250 ; /* 0xfffffc0000009947 */
/* 0x000fea000383ffff */
/*0650*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0660*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0670*/ IMAD R3, R3, c[0x0][0x180], R24 ; /* 0x0000600003037a24 */
/* 0x000fc800078e0218 */
/*0680*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0690*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101908 */
/*06a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06b0*/ BRA 0x6b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11init_matrixPfiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ MOV R9, c[0x0][0xc] ; /* 0x0000030000097a02 */
/* 0x000fce0000000f00 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD R0, R9, c[0x0][0x0], R0 ; /* 0x0000000009007a24 */
/* 0x000fe200078e0200 */
/*00e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101906 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0100*/ @!P0 BRA 0xc0 ; /* 0xffffffb000008947 */
/* 0x001fea000383ffff */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11init_matrixPfiif
.globl _Z11init_matrixPfiif
.p2align 8
.type _Z11init_matrixPfiif,@function
_Z11init_matrixPfiif:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x8
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_mul_i32 s4, s7, s6
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[0:1], 0x10
s_load_b32 s7, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s6
s_mul_i32 s1, s7, s5
s_mov_b32 s5, 0
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s2, v2
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s5, vcc_lo, s5
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11init_matrixPfiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11init_matrixPfiif, .Lfunc_end0-_Z11init_matrixPfiif
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z27tiled_matrix_multiplicationPfS_S_iii
.globl _Z27tiled_matrix_multiplicationPfS_S_iii
.p2align 8
.type _Z27tiled_matrix_multiplicationPfS_S_iii,@function
_Z27tiled_matrix_multiplicationPfS_S_iii:
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s12, s[0:1], 0x20
v_bfe_u32 v4, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s9, -1
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_ashr_i32 s5, s4, 31
v_mad_u64_u32 v[0:1], null, s15, s3, v[4:5]
s_lshr_b32 s3, s5, 28
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_mov_b32_e32 v2, 0
s_add_i32 s4, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s2, s4, 4
v_add_co_u32 v5, s3, s2, 1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_gt_i32_e64 s2, s8, v0
s_and_b32 vcc_lo, exec_lo, s3
v_cmp_gt_i32_e64 s3, s12, v1
s_cbranch_vccnz .LBB1_15
s_mov_b32 s10, s9
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v7, v0, s10
v_ashrrev_i32_e32 v2, 31, v1
v_dual_mov_b32 v12, 0 :: v_dual_lshlrev_b32 v17, 2, v3
v_lshlrev_b32_e32 v11, 6, v4
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 2, v[1:2]
v_dual_mov_b32 v14, v12 :: v_dual_add_nc_u32 v15, 0x400, v17
v_ashrrev_i32_e32 v8, 31, v7
v_add_nc_u32_e32 v13, v11, v17
v_cmp_le_i32_e64 s9, s8, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_mov_b32 v21, 0 :: v_dual_add_nc_u32 v16, v15, v11
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_ashr_i32 s11, s10, 31
s_ashr_i32 s13, s12, 31
s_xor_b32 s3, s3, -1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v8, vcc_lo
s_mov_b64 s[4:5], 0
v_add_co_u32 v17, vcc_lo, v2, v17
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v7, vcc_lo
v_add_co_u32 v19, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v20, vcc_lo, s7, v10, vcc_lo
v_mov_b32_e32 v2, 0
.LBB1_2:
s_mov_b32 s14, s9
s_mov_b32 s6, 0
s_and_saveexec_b32 s7, s2
s_lshl_b64 s[14:15], s[4:5], 4
s_mov_b32 s6, exec_lo
v_add_co_u32 v7, vcc_lo, s14, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s15, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_cmp_le_u64_e32 vcc_lo, s[10:11], v[7:8]
v_dual_mov_b32 v7, s14 :: v_dual_mov_b32 v8, s15
s_and_not1_b32 s14, s9, exec_lo
s_and_b32 s15, vcc_lo, exec_lo
s_or_b32 s14, s14, s15
s_or_b32 exec_lo, exec_lo, s7
s_and_saveexec_b32 s7, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB1_6
s_and_not1_b32 s6, s6, exec_lo
ds_store_b32 v13, v21
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s7
s_and_saveexec_b32 s7, s6
s_cbranch_execz .LBB1_8
v_lshlrev_b64 v[9:10], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v17, v9
v_add_co_ci_u32_e32 v10, vcc_lo, v18, v10, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
ds_store_b32 v13, v9
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s7
s_lshl_b64 s[6:7], s[4:5], 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_u32 v9, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v14, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[10:11], v[9:10]
s_or_b32 s6, s3, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s7, s6
s_xor_b32 s6, exec_lo, s7
s_cbranch_execz .LBB1_10
ds_store_b32 v16, v21
.LBB1_10:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB1_12
v_mul_lo_u32 v10, v10, s12
v_mul_lo_u32 v24, v9, s13
v_mad_u64_u32 v[22:23], null, v9, s12, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v23, v23, v24, v10
v_lshlrev_b64 v[9:10], 2, v[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v19, v9
v_add_co_ci_u32_e32 v10, vcc_lo, v20, v10, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
ds_store_b32 v16, v9
.LBB1_12:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v9, v15
v_mov_b32_e32 v10, v11
s_mov_b64 s[6:7], 16
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_13:
ds_load_b32 v22, v10
ds_load_b32 v23, v9
s_add_u32 s6, s6, -1
v_add_nc_u32_e32 v10, 4, v10
v_add_nc_u32_e32 v9, 64, v9
s_addc_u32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[6:7], 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v22, v23
s_cbranch_scc0 .LBB1_13
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[5:6]
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB1_2
.LBB1_15:
v_cmp_gt_i32_e32 vcc_lo, s8, v0
v_cmp_gt_i32_e64 s2, s12, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_17
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v0, s12, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27tiled_matrix_multiplicationPfS_S_iii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z27tiled_matrix_multiplicationPfS_S_iii, .Lfunc_end1-_Z27tiled_matrix_multiplicationPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
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.size: 4
.value_kind: by_value
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.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
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.size: 4
.value_kind: hidden_block_count_y
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.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
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.size: 2
.value_kind: hidden_group_size_y
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.size: 2
.value_kind: hidden_group_size_z
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.size: 2
.value_kind: hidden_remainder_x
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.size: 2
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.size: 2
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.size: 8
.value_kind: hidden_global_offset_x
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.size: 8
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.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11init_matrixPfiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11init_matrixPfiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
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.size: 8
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.size: 8
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.size: 8
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.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27tiled_matrix_multiplicationPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27tiled_matrix_multiplicationPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007b1b4_00000000-6_tiled_matrix_multiplication.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11init_matrixPfiifPfiif
.type _Z34__device_stub__Z11init_matrixPfiifPfiif, @function
_Z34__device_stub__Z11init_matrixPfiifPfiif:
.LFB2095:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11init_matrixPfiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z34__device_stub__Z11init_matrixPfiifPfiif, .-_Z34__device_stub__Z11init_matrixPfiifPfiif
.globl _Z11init_matrixPfiif
.type _Z11init_matrixPfiif, @function
_Z11init_matrixPfiif:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11init_matrixPfiifPfiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z11init_matrixPfiif, .-_Z11init_matrixPfiif
.globl _Z54__device_stub__Z27tiled_matrix_multiplicationPfS_S_iiiPfS_S_iii
.type _Z54__device_stub__Z27tiled_matrix_multiplicationPfS_S_iiiPfS_S_iii, @function
_Z54__device_stub__Z27tiled_matrix_multiplicationPfS_S_iiiPfS_S_iii:
.LFB2097:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27tiled_matrix_multiplicationPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2097:
.size _Z54__device_stub__Z27tiled_matrix_multiplicationPfS_S_iiiPfS_S_iii, .-_Z54__device_stub__Z27tiled_matrix_multiplicationPfS_S_iiiPfS_S_iii
.globl _Z27tiled_matrix_multiplicationPfS_S_iii
.type _Z27tiled_matrix_multiplicationPfS_S_iii, @function
_Z27tiled_matrix_multiplicationPfS_S_iii:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z27tiled_matrix_multiplicationPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _Z27tiled_matrix_multiplicationPfS_S_iii, .-_Z27tiled_matrix_multiplicationPfS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Failed to allocate memory for matrix A (error code %s)!\n"
.align 8
.LC1:
.string "Failed to allocate memory for matrix B (error code %s)!\n"
.align 8
.LC2:
.string "Failed to allocate memory for matrix C (error code %s)!\n"
.align 8
.LC5:
.string "Failed to initialize matrix (error code %s)!\n"
.align 8
.LC6:
.string "Failed to perform matrix addition (error code %s)!\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $80000000, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L30
leaq 16(%rsp), %rdi
movl $1, %edx
movl $120000000, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L31
leaq 24(%rsp), %rdi
movl $1, %edx
movl $96000000, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L32
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $78125, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L23:
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $117188, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L24:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L35
movl $375, 32(%rsp)
movl $250, 36(%rsp)
movl $1, 40(%rsp)
movl $16, 44(%rsp)
movl $16, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L26:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L37
call cudaDeviceSynchronize@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movss .LC3(%rip), %xmm0
movl $4000, %edx
movl $5000, %esi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z11init_matrixPfiifPfiif
jmp .L23
.L34:
movss .LC4(%rip), %xmm0
movl $5000, %edx
movl $6000, %esi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z11init_matrixPfiifPfiif
jmp .L24
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
movl $6000, %r9d
movl $5000, %r8d
movl $4000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z54__device_stub__Z27tiled_matrix_multiplicationPfS_S_iiiPfS_S_iii
jmp .L26
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC7:
.string "_Z27tiled_matrix_multiplicationPfS_S_iii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "_Z11init_matrixPfiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2100:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z27tiled_matrix_multiplicationPfS_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z11init_matrixPfiif(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tiled_matrix_multiplication.hip"
.globl _Z26__device_stub__init_matrixPfiif # -- Begin function _Z26__device_stub__init_matrixPfiif
.p2align 4, 0x90
.type _Z26__device_stub__init_matrixPfiif,@function
_Z26__device_stub__init_matrixPfiif: # @_Z26__device_stub__init_matrixPfiif
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11init_matrixPfiif, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__init_matrixPfiif, .Lfunc_end0-_Z26__device_stub__init_matrixPfiif
.cfi_endproc
# -- End function
.globl _Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii # -- Begin function _Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii
.p2align 4, 0x90
.type _Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii,@function
_Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii: # @_Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27tiled_matrix_multiplicationPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii, .Lfunc_end1-_Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $176, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -16
leaq 104(%rsp), %rdi
movl $80000000, %esi # imm = 0x4C4B400
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB2_1
# %bb.3:
leaq 96(%rsp), %rdi
movl $120000000, %esi # imm = 0x7270E00
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB2_4
# %bb.5:
leaq 168(%rsp), %rdi
movl $96000000, %esi # imm = 0x5B8D800
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB2_6
# %bb.7:
movabsq $4294967552, %rbx # imm = 0x100000100
leaq 77869(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 104(%rsp), %rax
movq %rax, 80(%rsp)
movl $5000, 24(%rsp) # imm = 0x1388
movl $4000, 16(%rsp) # imm = 0xFA0
movl $1065353216, 12(%rsp) # imm = 0x3F800000
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11init_matrixPfiif, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_9:
leaq 116932(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq 96(%rsp), %rax
movq %rax, 80(%rsp)
movl $6000, 24(%rsp) # imm = 0x1770
movl $5000, 16(%rsp) # imm = 0x1388
movl $1073741824, 12(%rsp) # imm = 0x40000000
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11init_matrixPfiif, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_12
# %bb.13:
movabsq $1073741824375, %rdi # imm = 0xFA00000177
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movq 168(%rsp), %rdx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movl $4000, 12(%rsp) # imm = 0xFA0
movl $5000, 92(%rsp) # imm = 0x1388
movl $6000, 88(%rsp) # imm = 0x1770
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 92(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z27tiled_matrix_multiplicationPfS_S_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_16
# %bb.17:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB2_2
.LBB2_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB2_2
.LBB2_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
.LBB2_2:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11init_matrixPfiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27tiled_matrix_multiplicationPfS_S_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11init_matrixPfiif,@object # @_Z11init_matrixPfiif
.section .rodata,"a",@progbits
.globl _Z11init_matrixPfiif
.p2align 3, 0x0
_Z11init_matrixPfiif:
.quad _Z26__device_stub__init_matrixPfiif
.size _Z11init_matrixPfiif, 8
.type _Z27tiled_matrix_multiplicationPfS_S_iii,@object # @_Z27tiled_matrix_multiplicationPfS_S_iii
.globl _Z27tiled_matrix_multiplicationPfS_S_iii
.p2align 3, 0x0
_Z27tiled_matrix_multiplicationPfS_S_iii:
.quad _Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii
.size _Z27tiled_matrix_multiplicationPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate memory for matrix A (error code %s)!\n"
.size .L.str, 57
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to allocate memory for matrix B (error code %s)!\n"
.size .L.str.1, 57
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate memory for matrix C (error code %s)!\n"
.size .L.str.2, 57
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to initialize matrix (error code %s)!\n"
.size .L.str.3, 46
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to perform matrix addition (error code %s)!\n"
.size .L.str.4, 52
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11init_matrixPfiif"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z27tiled_matrix_multiplicationPfS_S_iii"
.size .L__unnamed_2, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__init_matrixPfiif
.addrsig_sym _Z42__device_stub__tiled_matrix_multiplicationPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11init_matrixPfiif
.addrsig_sym _Z27tiled_matrix_multiplicationPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
__global__ void helloFromGPU()
{
printf("Hello world from GPU using C++\n");
// A line below doesn't work!
// std::cout << "Hello world from GPU using C++" << std::endl;
}
int main(int argc, char const* argv[])
{
std::cout << "Hello world from cpu using C++" << std::endl;
helloFromGPU <<<1, 10>>>();
return 0;
} | code for sm_80
Function : _Z12helloFromGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
__global__ void helloFromGPU()
{
printf("Hello world from GPU using C++\n");
// A line below doesn't work!
// std::cout << "Hello world from GPU using C++" << std::endl;
}
int main(int argc, char const* argv[])
{
std::cout << "Hello world from cpu using C++" << std::endl;
helloFromGPU <<<1, 10>>>();
return 0;
} | .file "tmpxft_00061b3b_00000000-6_helloworld2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Hello world from cpu using C++"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
__global__ void helloFromGPU()
{
printf("Hello world from GPU using C++\n");
// A line below doesn't work!
// std::cout << "Hello world from GPU using C++" << std::endl;
}
int main(int argc, char const* argv[])
{
std::cout << "Hello world from cpu using C++" << std::endl;
helloFromGPU <<<1, 10>>>();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
__global__ void helloFromGPU()
{
printf("Hello world from GPU using C++\n");
// A line below doesn't work!
// std::cout << "Hello world from GPU using C++" << std::endl;
}
int main(int argc, char const* argv[])
{
std::cout << "Hello world from cpu using C++" << std::endl;
helloFromGPU <<<1, 10>>>();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
__global__ void helloFromGPU()
{
printf("Hello world from GPU using C++\n");
// A line below doesn't work!
// std::cout << "Hello world from GPU using C++" << std::endl;
}
int main(int argc, char const* argv[])
{
std::cout << "Hello world from cpu using C++" << std::endl;
helloFromGPU <<<1, 10>>>();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12helloFromGPUv
.globl _Z12helloFromGPUv
.p2align 8
.type _Z12helloFromGPUv,@function
_Z12helloFromGPUv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 32
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12helloFromGPUv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12helloFromGPUv, .Lfunc_end0-_Z12helloFromGPUv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello world from GPU using C++\n"
.size .str, 32
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12helloFromGPUv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z12helloFromGPUv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
__global__ void helloFromGPU()
{
printf("Hello world from GPU using C++\n");
// A line below doesn't work!
// std::cout << "Hello world from GPU using C++" << std::endl;
}
int main(int argc, char const* argv[])
{
std::cout << "Hello world from cpu using C++" << std::endl;
helloFromGPU <<<1, 10>>>();
return 0;
} | .text
.file "helloworld2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Hello world from cpu using C++"
.size .L.str, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12helloFromGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12helloFromGPUv
.globl _Z12helloFromGPUv
.p2align 8
.type _Z12helloFromGPUv,@function
_Z12helloFromGPUv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 32
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12helloFromGPUv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12helloFromGPUv, .Lfunc_end0-_Z12helloFromGPUv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello world from GPU using C++\n"
.size .str, 32
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12helloFromGPUv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z12helloFromGPUv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00061b3b_00000000-6_helloworld2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Hello world from cpu using C++"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "helloworld2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Hello world from cpu using C++"
.size .L.str, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Copyright (c) 2018 Preferred Networks, Inc. All rights reserved.
*/
#include <cuda_fp16.h>
namespace chainer_trt {
namespace plugin {
template <typename T>
__global__ void slice_kernel(const T* src_gpu, T* dest_gpu,
int* mapping_gpu, int n_src, int n_dst) {
const int dst_idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_dst <= dst_idx)
return;
const int src_idx = mapping_gpu[dst_idx];
dest_gpu[blockIdx.y * n_dst + dst_idx] =
src_gpu[blockIdx.y * n_src + src_idx]; // blockIdx.y is batch idx
}
template <typename T>
void apply_slice(const T* src_gpu, T* dest_gpu, int* mapping_gpu, int n_src,
int n_dst, int batch_size, cudaStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_dst / block_size);
dim3 grid(grid_size, batch_size);
slice_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, dest_gpu, mapping_gpu, n_src, n_dst);
}
template void apply_slice(const float*, float*, int*, int, int, int,
cudaStream_t);
template void apply_slice(const __half*, __half*, int*, int, int, int,
cudaStream_t);
}
} | code for sm_80
Function : _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff097435 */
/* 0x000fc600000001ff */
/*00b0*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000ea40000002600 */
/*00c0*/ IMAD R4, R7, c[0x0][0x178], R2 ; /* 0x00005e0007047a24 */
/* 0x004fca00078e0202 */
/*00d0*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0009 */
/*00e0*/ LDG.E.U16 R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1500 */
/*00f0*/ IMAD R6, R7, c[0x0][0x17c], R0 ; /* 0x00005f0007067a24 */
/* 0x000fc800078e0200 */
/*0100*/ IMAD.WIDE.U32 R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fca00078e0009 */
/*0110*/ STG.E.U16 [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe2000c101504 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000ea40000002600 */
/*00b0*/ IMAD R4, R7, c[0x0][0x178], R2 ; /* 0x00005e0007047a24 */
/* 0x004fc800078e0202 */
/*00c0*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0009 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD R6, R7, c[0x0][0x17c], R0 ; /* 0x00005f0007067a24 */
/* 0x000fc800078e0200 */
/*00f0*/ IMAD.WIDE.U32 R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fca00078e0009 */
/*0100*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright (c) 2018 Preferred Networks, Inc. All rights reserved.
*/
#include <cuda_fp16.h>
namespace chainer_trt {
namespace plugin {
template <typename T>
__global__ void slice_kernel(const T* src_gpu, T* dest_gpu,
int* mapping_gpu, int n_src, int n_dst) {
const int dst_idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_dst <= dst_idx)
return;
const int src_idx = mapping_gpu[dst_idx];
dest_gpu[blockIdx.y * n_dst + dst_idx] =
src_gpu[blockIdx.y * n_src + src_idx]; // blockIdx.y is batch idx
}
template <typename T>
void apply_slice(const T* src_gpu, T* dest_gpu, int* mapping_gpu, int n_src,
int n_dst, int batch_size, cudaStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_dst / block_size);
dim3 grid(grid_size, batch_size);
slice_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, dest_gpu, mapping_gpu, n_src, n_dst);
}
template void apply_slice(const float*, float*, int*, int, int, int,
cudaStream_t);
template void apply_slice(const __half*, __half*, int*, int, int, int,
cudaStream_t);
}
} | .file "tmpxft_0014f5a4_00000000-6_slice.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL68__device_stub__ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_PiiiPKfPfPiii, @function
_ZL68__device_stub__ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_PiiiPKfPfPiii:
.LFB2428:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2428:
.size _ZL68__device_stub__ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_PiiiPKfPfPiii, .-_ZL68__device_stub__ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_PiiiPKfPfPiii
.section .text._ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,"axG",@progbits,_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,comdat
.weak _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.type _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii, @function
_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii:
.LFB2481:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL68__device_stub__ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_PiiiPKfPfPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2481:
.size _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii, .-_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.text
.type _ZL74__device_stub__ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_PiiiPK6__halfPS_Piii, @function
_ZL74__device_stub__ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_PiiiPK6__halfPS_Piii:
.LFB2430:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2430:
.size _ZL74__device_stub__ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_PiiiPK6__halfPS_Piii, .-_ZL74__device_stub__ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_PiiiPK6__halfPS_Piii
.section .text._ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,"axG",@progbits,_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,comdat
.weak _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.type _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii, @function
_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii:
.LFB2483:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL74__device_stub__ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_PiiiPK6__halfPS_Piii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2483:
.size _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii, .-_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2406:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2406:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP11CUstream_st,"axG",@progbits,_ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP11CUstream_st,comdat
.weak _ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP11CUstream_st
.type _ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP11CUstream_st, @function
_ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP11CUstream_st:
.LFB2479:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %r14d
movl %r8d, %ebx
pxor %xmm0, %xmm0
cvtsi2sdl %r8d, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L20
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L20:
cvttsd2sil %xmm3, %eax
movl %eax, 8(%rsp)
movl %r9d, 12(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movq 80(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl %ebx, %r8d
movl %r14d, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _ZL68__device_stub__ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_PiiiPKfPfPiii
jmp .L19
.cfi_endproc
.LFE2479:
.size _ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP11CUstream_st, .-_ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP11CUstream_st
.section .text._ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP11CUstream_st,"axG",@progbits,_ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP11CUstream_st,comdat
.weak _ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP11CUstream_st
.type _ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP11CUstream_st, @function
_ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP11CUstream_st:
.LFB2480:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %r14d
movl %r8d, %ebx
pxor %xmm0, %xmm0
cvtsi2sdl %r8d, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L25
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L25:
cvttsd2sil %xmm3, %eax
movl %eax, 8(%rsp)
movl %r9d, 12(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movq 80(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl %ebx, %r8d
movl %r14d, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _ZL74__device_stub__ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_PiiiPK6__halfPS_Piii
jmp .L24
.cfi_endproc
.LFE2480:
.size _ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP11CUstream_st, .-_ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii"
.align 8
.LC6:
.string "_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2433:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2433:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1062207488
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright (c) 2018 Preferred Networks, Inc. All rights reserved.
*/
#include <cuda_fp16.h>
namespace chainer_trt {
namespace plugin {
template <typename T>
__global__ void slice_kernel(const T* src_gpu, T* dest_gpu,
int* mapping_gpu, int n_src, int n_dst) {
const int dst_idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_dst <= dst_idx)
return;
const int src_idx = mapping_gpu[dst_idx];
dest_gpu[blockIdx.y * n_dst + dst_idx] =
src_gpu[blockIdx.y * n_src + src_idx]; // blockIdx.y is batch idx
}
template <typename T>
void apply_slice(const T* src_gpu, T* dest_gpu, int* mapping_gpu, int n_src,
int n_dst, int batch_size, cudaStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_dst / block_size);
dim3 grid(grid_size, batch_size);
slice_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, dest_gpu, mapping_gpu, n_src, n_dst);
}
template void apply_slice(const float*, float*, int*, int, int, int,
cudaStream_t);
template void apply_slice(const __half*, __half*, int*, int, int, int,
cudaStream_t);
}
} | /*
* Copyright (c) 2018 Preferred Networks, Inc. All rights reserved.
*/
#include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>
namespace chainer_trt {
namespace plugin {
template <typename T>
__global__ void slice_kernel(const T* src_gpu, T* dest_gpu,
int* mapping_gpu, int n_src, int n_dst) {
const int dst_idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_dst <= dst_idx)
return;
const int src_idx = mapping_gpu[dst_idx];
dest_gpu[blockIdx.y * n_dst + dst_idx] =
src_gpu[blockIdx.y * n_src + src_idx]; // blockIdx.y is batch idx
}
template <typename T>
void apply_slice(const T* src_gpu, T* dest_gpu, int* mapping_gpu, int n_src,
int n_dst, int batch_size, hipStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_dst / block_size);
dim3 grid(grid_size, batch_size);
slice_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, dest_gpu, mapping_gpu, n_src, n_dst);
}
template void apply_slice(const float*, float*, int*, int, int, int,
hipStream_t);
template void apply_slice(const __half*, __half*, int*, int, int, int,
hipStream_t);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Copyright (c) 2018 Preferred Networks, Inc. All rights reserved.
*/
#include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>
namespace chainer_trt {
namespace plugin {
template <typename T>
__global__ void slice_kernel(const T* src_gpu, T* dest_gpu,
int* mapping_gpu, int n_src, int n_dst) {
const int dst_idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_dst <= dst_idx)
return;
const int src_idx = mapping_gpu[dst_idx];
dest_gpu[blockIdx.y * n_dst + dst_idx] =
src_gpu[blockIdx.y * n_src + src_idx]; // blockIdx.y is batch idx
}
template <typename T>
void apply_slice(const T* src_gpu, T* dest_gpu, int* mapping_gpu, int n_src,
int n_dst, int batch_size, hipStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_dst / block_size);
dim3 grid(grid_size, batch_size);
slice_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, dest_gpu, mapping_gpu, n_src, n_dst);
}
template void apply_slice(const float*, float*, int*, int, int, int,
hipStream_t);
template void apply_slice(const __half*, __half*, int*, int, int, int,
hipStream_t);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,"axG",@progbits,_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,comdat
.protected _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.globl _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.p2align 8
.type _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,@function
_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_clause 0x1
s_load_b32 s3, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, s15, s2, v[1:2]
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,"axG",@progbits,_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,comdat
.Lfunc_end0:
.size _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii, .Lfunc_end0-_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,"axG",@progbits,_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,comdat
.protected _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.globl _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.p2align 8
.type _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,@function
_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB1_2
s_load_b64 s[4:5], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_clause 0x1
s_load_b32 s3, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 1, v[2:3]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_u16 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, s15, s2, v[1:2]
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[0:1], 1, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b16 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,"axG",@progbits,_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,comdat
.Lfunc_end1:
.size _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii, .Lfunc_end1-_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Copyright (c) 2018 Preferred Networks, Inc. All rights reserved.
*/
#include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>
namespace chainer_trt {
namespace plugin {
template <typename T>
__global__ void slice_kernel(const T* src_gpu, T* dest_gpu,
int* mapping_gpu, int n_src, int n_dst) {
const int dst_idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_dst <= dst_idx)
return;
const int src_idx = mapping_gpu[dst_idx];
dest_gpu[blockIdx.y * n_dst + dst_idx] =
src_gpu[blockIdx.y * n_src + src_idx]; // blockIdx.y is batch idx
}
template <typename T>
void apply_slice(const T* src_gpu, T* dest_gpu, int* mapping_gpu, int n_src,
int n_dst, int batch_size, hipStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_dst / block_size);
dim3 grid(grid_size, batch_size);
slice_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, dest_gpu, mapping_gpu, n_src, n_dst);
}
template void apply_slice(const float*, float*, int*, int, int, int,
hipStream_t);
template void apply_slice(const __half*, __half*, int*, int, int, int,
hipStream_t);
}
} | .text
.file "slice.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t
.LCPI0_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.section .text._ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t,"axG",@progbits,_ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t,comdat
.weak _ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t
.p2align 4, 0x90
.type _ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t,@function
_ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t: # @_ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r13d
movl %r8d, %ebx
movl %ecx, %ebp
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
cvtsi2sd %r8d, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %eax
shlq $32, %r13
orq %rax, %r13
movabsq $4294968320, %rdx # imm = 0x100000400
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
movq 176(%rsp), %r9
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebp, 4(%rsp)
movl %ebx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t, .Lfunc_end0-_ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t
.cfi_endproc
# -- End function
.section .text._ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii,"axG",@progbits,_ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii,comdat
.weak _ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii # -- Begin function _ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii
.p2align 4, 0x90
.type _ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii,@function
_ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii: # @_ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii, .Lfunc_end1-_ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t
.LCPI2_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.section .text._ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t,"axG",@progbits,_ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t,comdat
.weak _ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t
.p2align 4, 0x90
.type _ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t,@function
_ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t: # @_ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r13d
movl %r8d, %ebx
movl %ecx, %ebp
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
cvtsi2sd %r8d, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %eax
shlq $32, %r13
orq %rax, %r13
movabsq $4294968320, %rdx # imm = 0x100000400
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
movq 176(%rsp), %r9
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebp, 4(%rsp)
movl %ebx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t, .Lfunc_end2-_ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t
.cfi_endproc
# -- End function
.section .text._ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii,"axG",@progbits,_ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii,comdat
.weak _ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii # -- Begin function _ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii
.p2align 4, 0x90
.type _ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii,@function
_ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii: # @_ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii, .Lfunc_end3-_ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,@object # @_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.section .rodata._ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,"aG",@progbits,_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,comdat
.weak _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.p2align 3, 0x0
_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii:
.quad _ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii
.size _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii, 8
.type _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,@object # @_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.section .rodata._ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,"aG",@progbits,_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,comdat
.weak _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.p2align 3, 0x0
_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii:
.quad _ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii
.size _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii"
.size .L__unnamed_1, 55
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii"
.size .L__unnamed_2, 61
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii
.addrsig_sym _ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.addrsig_sym _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff097435 */
/* 0x000fc600000001ff */
/*00b0*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000ea40000002600 */
/*00c0*/ IMAD R4, R7, c[0x0][0x178], R2 ; /* 0x00005e0007047a24 */
/* 0x004fca00078e0202 */
/*00d0*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0009 */
/*00e0*/ LDG.E.U16 R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1500 */
/*00f0*/ IMAD R6, R7, c[0x0][0x17c], R0 ; /* 0x00005f0007067a24 */
/* 0x000fc800078e0200 */
/*0100*/ IMAD.WIDE.U32 R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fca00078e0009 */
/*0110*/ STG.E.U16 [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe2000c101504 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000ea40000002600 */
/*00b0*/ IMAD R4, R7, c[0x0][0x178], R2 ; /* 0x00005e0007047a24 */
/* 0x004fc800078e0202 */
/*00c0*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0009 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD R6, R7, c[0x0][0x17c], R0 ; /* 0x00005f0007067a24 */
/* 0x000fc800078e0200 */
/*00f0*/ IMAD.WIDE.U32 R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fca00078e0009 */
/*0100*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,"axG",@progbits,_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,comdat
.protected _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.globl _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.p2align 8
.type _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,@function
_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_clause 0x1
s_load_b32 s3, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, s15, s2, v[1:2]
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,"axG",@progbits,_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,comdat
.Lfunc_end0:
.size _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii, .Lfunc_end0-_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,"axG",@progbits,_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,comdat
.protected _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.globl _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.p2align 8
.type _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,@function
_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB1_2
s_load_b64 s[4:5], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_clause 0x1
s_load_b32 s3, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 1, v[2:3]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_u16 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, s15, s2, v[1:2]
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[0:1], 1, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b16 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,"axG",@progbits,_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,comdat
.Lfunc_end1:
.size _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii, .Lfunc_end1-_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014f5a4_00000000-6_slice.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL68__device_stub__ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_PiiiPKfPfPiii, @function
_ZL68__device_stub__ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_PiiiPKfPfPiii:
.LFB2428:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2428:
.size _ZL68__device_stub__ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_PiiiPKfPfPiii, .-_ZL68__device_stub__ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_PiiiPKfPfPiii
.section .text._ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,"axG",@progbits,_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,comdat
.weak _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.type _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii, @function
_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii:
.LFB2481:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL68__device_stub__ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_PiiiPKfPfPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2481:
.size _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii, .-_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.text
.type _ZL74__device_stub__ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_PiiiPK6__halfPS_Piii, @function
_ZL74__device_stub__ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_PiiiPK6__halfPS_Piii:
.LFB2430:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2430:
.size _ZL74__device_stub__ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_PiiiPK6__halfPS_Piii, .-_ZL74__device_stub__ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_PiiiPK6__halfPS_Piii
.section .text._ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,"axG",@progbits,_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,comdat
.weak _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.type _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii, @function
_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii:
.LFB2483:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL74__device_stub__ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_PiiiPK6__halfPS_Piii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2483:
.size _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii, .-_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2406:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2406:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP11CUstream_st,"axG",@progbits,_ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP11CUstream_st,comdat
.weak _ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP11CUstream_st
.type _ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP11CUstream_st, @function
_ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP11CUstream_st:
.LFB2479:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %r14d
movl %r8d, %ebx
pxor %xmm0, %xmm0
cvtsi2sdl %r8d, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L20
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L20:
cvttsd2sil %xmm3, %eax
movl %eax, 8(%rsp)
movl %r9d, 12(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movq 80(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl %ebx, %r8d
movl %r14d, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _ZL68__device_stub__ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_PiiiPKfPfPiii
jmp .L19
.cfi_endproc
.LFE2479:
.size _ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP11CUstream_st, .-_ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP11CUstream_st
.section .text._ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP11CUstream_st,"axG",@progbits,_ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP11CUstream_st,comdat
.weak _ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP11CUstream_st
.type _ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP11CUstream_st, @function
_ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP11CUstream_st:
.LFB2480:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %r14d
movl %r8d, %ebx
pxor %xmm0, %xmm0
cvtsi2sdl %r8d, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L25
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L25:
cvttsd2sil %xmm3, %eax
movl %eax, 8(%rsp)
movl %r9d, 12(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movq 80(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl %ebx, %r8d
movl %r14d, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _ZL74__device_stub__ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_PiiiPK6__halfPS_Piii
jmp .L24
.cfi_endproc
.LFE2480:
.size _ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP11CUstream_st, .-_ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii"
.align 8
.LC6:
.string "_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2433:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2433:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1062207488
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "slice.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t
.LCPI0_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.section .text._ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t,"axG",@progbits,_ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t,comdat
.weak _ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t
.p2align 4, 0x90
.type _ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t,@function
_ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t: # @_ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r13d
movl %r8d, %ebx
movl %ecx, %ebp
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
cvtsi2sd %r8d, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %eax
shlq $32, %r13
orq %rax, %r13
movabsq $4294968320, %rdx # imm = 0x100000400
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
movq 176(%rsp), %r9
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebp, 4(%rsp)
movl %ebx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t, .Lfunc_end0-_ZN11chainer_trt6plugin11apply_sliceIfEEvPKT_PS2_PiiiiP12ihipStream_t
.cfi_endproc
# -- End function
.section .text._ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii,"axG",@progbits,_ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii,comdat
.weak _ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii # -- Begin function _ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii
.p2align 4, 0x90
.type _ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii,@function
_ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii: # @_ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii, .Lfunc_end1-_ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t
.LCPI2_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.section .text._ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t,"axG",@progbits,_ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t,comdat
.weak _ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t
.p2align 4, 0x90
.type _ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t,@function
_ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t: # @_ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r13d
movl %r8d, %ebx
movl %ecx, %ebp
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
cvtsi2sd %r8d, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %eax
shlq $32, %r13
orq %rax, %r13
movabsq $4294968320, %rdx # imm = 0x100000400
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
movq 176(%rsp), %r9
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebp, 4(%rsp)
movl %ebx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t, .Lfunc_end2-_ZN11chainer_trt6plugin11apply_sliceI6__halfEEvPKT_PS3_PiiiiP12ihipStream_t
.cfi_endproc
# -- End function
.section .text._ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii,"axG",@progbits,_ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii,comdat
.weak _ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii # -- Begin function _ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii
.p2align 4, 0x90
.type _ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii,@function
_ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii: # @_ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii, .Lfunc_end3-_ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,@object # @_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.section .rodata._ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,"aG",@progbits,_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii,comdat
.weak _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.p2align 3, 0x0
_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii:
.quad _ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii
.size _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii, 8
.type _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,@object # @_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.section .rodata._ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,"aG",@progbits,_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii,comdat
.weak _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.p2align 3, 0x0
_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii:
.quad _ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii
.size _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii"
.size .L__unnamed_1, 55
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii"
.size .L__unnamed_2, 61
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN11chainer_trt6plugin27__device_stub__slice_kernelIfEEvPKT_PS2_Piii
.addrsig_sym _ZN11chainer_trt6plugin27__device_stub__slice_kernelI6__halfEEvPKT_PS3_Piii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN11chainer_trt6plugin12slice_kernelIfEEvPKT_PS2_Piii
.addrsig_sym _ZN11chainer_trt6plugin12slice_kernelI6__halfEEvPKT_PS3_Piii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <ctime>
#include <cstdlib>
#include <vector>
#include <cmath>
#include <list>
using namespace std;
//size at which the sequential multiplication is used instead of recursive Strassen
int thresholdSize = 128;
void initMat(vector< vector<double> > &a, vector< vector<double> > &b, int n)
{
// initialize matrices and fill them with random values
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
a[i][j] = (double)rand()/RAND_MAX*10;
b[i][j] = (double)rand()/RAND_MAX*10;
}
}
}
void multiplyMatStandard(vector< vector<double> > &a,
vector< vector<double> > &b, vector< vector<double> > &c, int n)
{
// standard matrix multipmlication: C <- C + A x B
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
double temp = 0;
for (int k = 0; k < n; ++k) {
temp += a[i][k] * b[k][j];
}
c[i][j]=temp;
}
}
}
int getNextPowerOfTwo(int n)
{
return pow(2, int(ceil(log2(n))));
}
void fillZeros(vector< vector<double> > &newA, vector< vector<double> > &newB,
vector< vector<double> > &a, vector< vector<double> > &b, int n)
{
//pad matrix with zeros
for (int i=0; i<n; i++){
for (int j=0; j<n; j++){
newA[i][j] = a[i][j];
newB[i][j] = b[i][j];
}
}
}
void add(vector< vector<double> > &a, vector< vector<double> > &b,
vector< vector<double> > &resultMatrix, int n)
{
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
resultMatrix[i][j] = a[i][j] + b[i][j];
}
}
}
void subtract(vector< vector<double> > &a, vector< vector<double> > &b,
vector< vector<double> > &resultMatrix, int n)
{
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
resultMatrix[i][j] = a[i][j] - b[i][j];
}
}
}
void multiplyStrassen(vector< vector<double> > &a,
vector< vector<double> > &b, vector< vector<double> > &c, int n)
{
if(n<=thresholdSize){
multiplyMatStandard(a, b, c, n);
}
else{
//expand and fill with zeros if matrix size is not a power of two
int newSize = getNextPowerOfTwo(n);
vector< vector<double> >
newA(newSize, vector<double>(newSize)),
newB(newSize, vector<double>(newSize)),
newC(newSize, vector<double>(newSize));
if(n==newSize){ //matrix size is already a power of two
newA = a;
newB = b;
}
else{
fillZeros(newA, newB, a, b, n);
}
//initialize submatrices
int blockSize = newSize/2; //size for a partition matrix
vector<double> block (blockSize);
vector< vector<double> >
/*partitions of newA*/
a11(blockSize, block), a12(blockSize, block),
a21(blockSize, block), a22(blockSize, block),
/*partitions of newB*/
b11(blockSize, block), b12(blockSize, block),
b21(blockSize, block), b22(blockSize, block),
/*partitions of newC*/
c11(blockSize, block), c12(blockSize, block),
c21(blockSize, block), c22(blockSize, block),
/*matrices storing intermediate results*/
aBlock(blockSize, block), bBlock(blockSize, block),
/*set of submatrices derived from partitions*/
m1(blockSize, block), m2(blockSize, block),
m3(blockSize, block), m4(blockSize, block),
m5(blockSize, block), m6(blockSize, block),
m7(blockSize, block);
//partition matrices
for (int i=0; i<blockSize; i++){
for (int j=0; j<blockSize; j++){
a11[i][j] = newA[i][j];
a12[i][j] = newA[i][j+blockSize];
a21[i][j] = newA[i+blockSize][j];
a22[i][j] = newA[i+blockSize][j+blockSize];
b11[i][j] = newB[i][j];
b12[i][j] = newB[i][j+blockSize];
b21[i][j] = newB[i+blockSize][j];
b22[i][j] = newB[i+blockSize][j+blockSize];
}
}
//compute submatrices
//m1 = (a11+a22)(b11+b22)
add(a11, a22, aBlock, blockSize);
add(b11, b22, bBlock, blockSize);
multiplyStrassen(aBlock, bBlock, m1, blockSize);
//m2 = (a21+a22)b11
add(a21, a22, aBlock, blockSize);
multiplyStrassen(aBlock, b11, m2, blockSize);
//m3 = a11(b12-b22)
subtract(b12, b22, bBlock, blockSize);
multiplyStrassen(a11, bBlock, m3, blockSize);
//m4 = a22(b21-b11)
subtract(b21, b11, bBlock, blockSize);
multiplyStrassen(a22, bBlock, m4, blockSize);
//m5 = (a11+a12)b22
add(a11, a12, aBlock, blockSize);
multiplyStrassen(aBlock, b22, m5, blockSize);
//m6 = (a21-a11)(b11+b12)
subtract(a21, a11, aBlock, blockSize);
add(b11, b12, bBlock, blockSize);
multiplyStrassen(aBlock, bBlock, m6, blockSize);
//m7 = (a12-a22)(b12+b22)
subtract(a12, a22, aBlock, blockSize);
add(b12, b22, bBlock, blockSize);
multiplyStrassen(aBlock, bBlock, m7, blockSize);
//calculate result submatrices
//c11 = m1+m4-m5+m7
add(m1, m4, aBlock, blockSize);
subtract(aBlock, m5, bBlock, blockSize);
add(bBlock, m7, c11, blockSize);
//c12 = m3+m5
add(m3, m5, c12, blockSize);
//c21 = m2+m4
add(m2, m4, c12, blockSize);
//c22 = m1-m2+m3+m6
subtract(m1, m2, aBlock, blockSize);
add(aBlock, m3, bBlock, blockSize);
add(bBlock, m6, c22, blockSize);
//calculate final result matrix
for(int i=0; i<blockSize; i++){
for(int j=0; j<blockSize; j++){
newC[i][j] = c11[i][j];
newC[i][blockSize+j] = c12[i][j];
newC[blockSize+i][j] = c21[i][j];
newC[blockSize+i][blockSize+j] = c22[i][j];
}
}
//remove additional values from expanded matrix
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
c[i][j] = newC[i][j];
}
}
}
}
double calculateMean(vector<double> data, int size)
{
double sum = 0.0, mean = 0.0;
for (int i = 0; i < size; ++i) {
sum += data[i];
}
mean = sum / size;
return mean;
}
int main()
{
//srand(time(0)); //seed for random number generation
// number of sample size considered to evaluate average execution time
FILE * fp;
fp=fopen("Strassen_Multiplication_UPDATED_CPU.csv","w+");
fprintf(fp, "Algorithm_Name,Input_Dimensions,Execution_Time(ms)");
double startTime;
double elapsedTime;
double standardMean;
double strassenMean;
float cpu_elapsed_time_ms;
char algoname[100]="Strassen_Matrix_Multiplication_CPU";
int my_list[]={1008, 1040, 1072, 1104, 1136, 1168, 1200, 1232, 1264, 1296, 1328, 1360, 1392, 1424, 1456, 1488, 1520, 1552, 1584, 1616, 1648, 1680, 1712, 1744, 1776, 1808, 1840, 1872, 1904, 1936, 1968, 2000, 2032, 2064, 2096, 2128, 2160, 2192, 2224, 2256, 2288, 2320, 2352, 2384, 2416, 2448, 2480, 2512, 2544, 2576, 2608, 2640, 2672, 2704, 2736, 2768, 2800, 2832, 2864, 2896, 2928, 2960, 2992, 3024, 3056, 3088, 3120, 3152, 3184, 3216, 3248, 3280, 3312, 3344, 3376, 3408, 3440, 3472, 3504, 3536, 3568, 3600, 3632, 3664, 3696, 3728, 3760, 3792, 3824, 3856, 3888, 3920, 3952, 3984, 4016, 4080, 4144, 4208, 4272, 4336, 4400, 4464, 4528, 4592, 4656, 4720, 4784, 4848, 4912, 4976, 5040, 5104, 5168, 5232, 5296, 5360, 5424, 5488, 5552, 5616, 5680, 5744, 5808, 5872, 5936, 6000, 6064, 6128, 6192, 6256, 6320, 6384, 6448, 6512, 6576, 6640, 6704, 6768, 6832, 6896, 6960, 7024, 7088, 7152, 7216, 7280, 7344, 7408, 7472, 7536, 7600, 7664, 7728, 7792, 7856, 7920, 7984, 8048, 8112, 8176, 8240, 8304, 8368, 8432, 8496, 8560, 8624, 8688, 8752, 8816, 8880, 8944, 9008, 9072, 9136, 9200, 9264, 9328, 9392, 9456, 9520, 9584, 9648, 9712, 9776, 9840, 9904, 9968, 10032, 10096, 10160, 10224, 10288, 10352, 10416, 10480, 10544, 10608, 10672, 10736, 10800, 10864, 10928, 10992};
int length=sizeof(my_list)/sizeof(my_list[0]);
printf("%d\n",length);
//set threshold value if given by user
// if(argc>1){
// thresholdSize = atoi(argv[1]);
// }
//vectors storing execution time values
// vector<double> standardTime(sampleSize);
// vector<double> strassenTime(sampleSize);
for (int k = 0; k < length; k++) {
//initialize vectors for matrices a, b, c: a*b = c
if(my_list[k]<=3500){
int matSize = my_list[k];
vector< vector<double> >
a(matSize,vector<double>(matSize)),
b(matSize,vector<double>(matSize)),
c(matSize,vector<double>(matSize));
initMat(a,b,matSize);
double l[5];
// //standard execution
// startTime = time(0);
// multiplyMatStandard(a,b,c,matSize);
// elapsedTime = time(0) - startTime;
// standardTime[k] = elapsedTime;
//multiplication using Strassen'
if(my_list[k]<=1000){
for(int j=0;j<5;j++){
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// cout<<startTime<<endl;
multiplyStrassen(a,b,c,matSize);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
l[j]=cpu_elapsed_time_ms;
//printf("%lf\n",cpu_elapsed_time_ms);
}// elapsedTime = time(0) - startTime;
// double duration = elapsedTime;
// clock_t begin1 = clock();
// multiplyStrassen(a,b,c,matSize);
// clock_t end1 = clock();
// double time_spent1 = (double)1000*(end1 - begin1) / CLOCKS_PER_SEC;
double avg;
avg=(l[0]+l[1]+l[2]+l[3]+l[4])/5;
cout << "Using Milliseconds Clock: (AVG)"<< endl;
cout << " CPU time taken to execute for strassen matrices of size - "
<< matSize << " : " <<avg<<" ms"<< endl;
cout << endl;
fprintf(fp,"\n%s,%d,%lf",algoname,matSize,avg);
}else{
int matSize = my_list[k];
vector< vector<double> >
a(matSize,vector<double>(matSize)),
b(matSize,vector<double>(matSize)),
c(matSize,vector<double>(matSize));
initMat(a,b,matSize);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// cout<<startTime<<endl;
multiplyStrassen(a,b,c,matSize);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
cout << "Using Milliseconds Clock:(else above 1000) "<< endl;
cout << " CPU time taken to execute for strassen matrices of size - "
<< matSize << " : " <<cpu_elapsed_time_ms<<" ms"<< endl;
cout << endl;
fprintf(fp,"\n%s,%d,%lf",algoname,matSize,cpu_elapsed_time_ms);
}
// }
// cout << "Standard multiplication"<< endl;
// standardMean = calculateMean(standardTime, sampleSize);
// cout << "Average time taken to execute matrices of size - "
// << matSize << " : " << standardMean << endl;
// cout << endl;
// cout << "Multiplication using given Original Clock Strassen's"<< endl;
// cout << "Average time taken to execute matrices of size - "
// << matSize << " : " << time_spent1 << endl;
// cout << endl;
// cout << "Speed up gained by using Strassen's-" << matSize
// << " : " << standardMean/strassenMean << endl;
// cout << endl;
}else{
cout<<"MAX LIMIT"<<endl;
int max_limit=800000;
fprintf(fp,"\n%s,%d,%d",algoname,my_list[k],max_limit);
}
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <ctime>
#include <cstdlib>
#include <vector>
#include <cmath>
#include <list>
using namespace std;
//size at which the sequential multiplication is used instead of recursive Strassen
int thresholdSize = 128;
void initMat(vector< vector<double> > &a, vector< vector<double> > &b, int n)
{
// initialize matrices and fill them with random values
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
a[i][j] = (double)rand()/RAND_MAX*10;
b[i][j] = (double)rand()/RAND_MAX*10;
}
}
}
void multiplyMatStandard(vector< vector<double> > &a,
vector< vector<double> > &b, vector< vector<double> > &c, int n)
{
// standard matrix multipmlication: C <- C + A x B
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
double temp = 0;
for (int k = 0; k < n; ++k) {
temp += a[i][k] * b[k][j];
}
c[i][j]=temp;
}
}
}
int getNextPowerOfTwo(int n)
{
return pow(2, int(ceil(log2(n))));
}
void fillZeros(vector< vector<double> > &newA, vector< vector<double> > &newB,
vector< vector<double> > &a, vector< vector<double> > &b, int n)
{
//pad matrix with zeros
for (int i=0; i<n; i++){
for (int j=0; j<n; j++){
newA[i][j] = a[i][j];
newB[i][j] = b[i][j];
}
}
}
void add(vector< vector<double> > &a, vector< vector<double> > &b,
vector< vector<double> > &resultMatrix, int n)
{
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
resultMatrix[i][j] = a[i][j] + b[i][j];
}
}
}
void subtract(vector< vector<double> > &a, vector< vector<double> > &b,
vector< vector<double> > &resultMatrix, int n)
{
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
resultMatrix[i][j] = a[i][j] - b[i][j];
}
}
}
void multiplyStrassen(vector< vector<double> > &a,
vector< vector<double> > &b, vector< vector<double> > &c, int n)
{
if(n<=thresholdSize){
multiplyMatStandard(a, b, c, n);
}
else{
//expand and fill with zeros if matrix size is not a power of two
int newSize = getNextPowerOfTwo(n);
vector< vector<double> >
newA(newSize, vector<double>(newSize)),
newB(newSize, vector<double>(newSize)),
newC(newSize, vector<double>(newSize));
if(n==newSize){ //matrix size is already a power of two
newA = a;
newB = b;
}
else{
fillZeros(newA, newB, a, b, n);
}
//initialize submatrices
int blockSize = newSize/2; //size for a partition matrix
vector<double> block (blockSize);
vector< vector<double> >
/*partitions of newA*/
a11(blockSize, block), a12(blockSize, block),
a21(blockSize, block), a22(blockSize, block),
/*partitions of newB*/
b11(blockSize, block), b12(blockSize, block),
b21(blockSize, block), b22(blockSize, block),
/*partitions of newC*/
c11(blockSize, block), c12(blockSize, block),
c21(blockSize, block), c22(blockSize, block),
/*matrices storing intermediate results*/
aBlock(blockSize, block), bBlock(blockSize, block),
/*set of submatrices derived from partitions*/
m1(blockSize, block), m2(blockSize, block),
m3(blockSize, block), m4(blockSize, block),
m5(blockSize, block), m6(blockSize, block),
m7(blockSize, block);
//partition matrices
for (int i=0; i<blockSize; i++){
for (int j=0; j<blockSize; j++){
a11[i][j] = newA[i][j];
a12[i][j] = newA[i][j+blockSize];
a21[i][j] = newA[i+blockSize][j];
a22[i][j] = newA[i+blockSize][j+blockSize];
b11[i][j] = newB[i][j];
b12[i][j] = newB[i][j+blockSize];
b21[i][j] = newB[i+blockSize][j];
b22[i][j] = newB[i+blockSize][j+blockSize];
}
}
//compute submatrices
//m1 = (a11+a22)(b11+b22)
add(a11, a22, aBlock, blockSize);
add(b11, b22, bBlock, blockSize);
multiplyStrassen(aBlock, bBlock, m1, blockSize);
//m2 = (a21+a22)b11
add(a21, a22, aBlock, blockSize);
multiplyStrassen(aBlock, b11, m2, blockSize);
//m3 = a11(b12-b22)
subtract(b12, b22, bBlock, blockSize);
multiplyStrassen(a11, bBlock, m3, blockSize);
//m4 = a22(b21-b11)
subtract(b21, b11, bBlock, blockSize);
multiplyStrassen(a22, bBlock, m4, blockSize);
//m5 = (a11+a12)b22
add(a11, a12, aBlock, blockSize);
multiplyStrassen(aBlock, b22, m5, blockSize);
//m6 = (a21-a11)(b11+b12)
subtract(a21, a11, aBlock, blockSize);
add(b11, b12, bBlock, blockSize);
multiplyStrassen(aBlock, bBlock, m6, blockSize);
//m7 = (a12-a22)(b12+b22)
subtract(a12, a22, aBlock, blockSize);
add(b12, b22, bBlock, blockSize);
multiplyStrassen(aBlock, bBlock, m7, blockSize);
//calculate result submatrices
//c11 = m1+m4-m5+m7
add(m1, m4, aBlock, blockSize);
subtract(aBlock, m5, bBlock, blockSize);
add(bBlock, m7, c11, blockSize);
//c12 = m3+m5
add(m3, m5, c12, blockSize);
//c21 = m2+m4
add(m2, m4, c12, blockSize);
//c22 = m1-m2+m3+m6
subtract(m1, m2, aBlock, blockSize);
add(aBlock, m3, bBlock, blockSize);
add(bBlock, m6, c22, blockSize);
//calculate final result matrix
for(int i=0; i<blockSize; i++){
for(int j=0; j<blockSize; j++){
newC[i][j] = c11[i][j];
newC[i][blockSize+j] = c12[i][j];
newC[blockSize+i][j] = c21[i][j];
newC[blockSize+i][blockSize+j] = c22[i][j];
}
}
//remove additional values from expanded matrix
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
c[i][j] = newC[i][j];
}
}
}
}
double calculateMean(vector<double> data, int size)
{
double sum = 0.0, mean = 0.0;
for (int i = 0; i < size; ++i) {
sum += data[i];
}
mean = sum / size;
return mean;
}
int main()
{
//srand(time(0)); //seed for random number generation
// number of sample size considered to evaluate average execution time
FILE * fp;
fp=fopen("Strassen_Multiplication_UPDATED_CPU.csv","w+");
fprintf(fp, "Algorithm_Name,Input_Dimensions,Execution_Time(ms)");
double startTime;
double elapsedTime;
double standardMean;
double strassenMean;
float cpu_elapsed_time_ms;
char algoname[100]="Strassen_Matrix_Multiplication_CPU";
int my_list[]={1008, 1040, 1072, 1104, 1136, 1168, 1200, 1232, 1264, 1296, 1328, 1360, 1392, 1424, 1456, 1488, 1520, 1552, 1584, 1616, 1648, 1680, 1712, 1744, 1776, 1808, 1840, 1872, 1904, 1936, 1968, 2000, 2032, 2064, 2096, 2128, 2160, 2192, 2224, 2256, 2288, 2320, 2352, 2384, 2416, 2448, 2480, 2512, 2544, 2576, 2608, 2640, 2672, 2704, 2736, 2768, 2800, 2832, 2864, 2896, 2928, 2960, 2992, 3024, 3056, 3088, 3120, 3152, 3184, 3216, 3248, 3280, 3312, 3344, 3376, 3408, 3440, 3472, 3504, 3536, 3568, 3600, 3632, 3664, 3696, 3728, 3760, 3792, 3824, 3856, 3888, 3920, 3952, 3984, 4016, 4080, 4144, 4208, 4272, 4336, 4400, 4464, 4528, 4592, 4656, 4720, 4784, 4848, 4912, 4976, 5040, 5104, 5168, 5232, 5296, 5360, 5424, 5488, 5552, 5616, 5680, 5744, 5808, 5872, 5936, 6000, 6064, 6128, 6192, 6256, 6320, 6384, 6448, 6512, 6576, 6640, 6704, 6768, 6832, 6896, 6960, 7024, 7088, 7152, 7216, 7280, 7344, 7408, 7472, 7536, 7600, 7664, 7728, 7792, 7856, 7920, 7984, 8048, 8112, 8176, 8240, 8304, 8368, 8432, 8496, 8560, 8624, 8688, 8752, 8816, 8880, 8944, 9008, 9072, 9136, 9200, 9264, 9328, 9392, 9456, 9520, 9584, 9648, 9712, 9776, 9840, 9904, 9968, 10032, 10096, 10160, 10224, 10288, 10352, 10416, 10480, 10544, 10608, 10672, 10736, 10800, 10864, 10928, 10992};
int length=sizeof(my_list)/sizeof(my_list[0]);
printf("%d\n",length);
//set threshold value if given by user
// if(argc>1){
// thresholdSize = atoi(argv[1]);
// }
//vectors storing execution time values
// vector<double> standardTime(sampleSize);
// vector<double> strassenTime(sampleSize);
for (int k = 0; k < length; k++) {
//initialize vectors for matrices a, b, c: a*b = c
if(my_list[k]<=3500){
int matSize = my_list[k];
vector< vector<double> >
a(matSize,vector<double>(matSize)),
b(matSize,vector<double>(matSize)),
c(matSize,vector<double>(matSize));
initMat(a,b,matSize);
double l[5];
// //standard execution
// startTime = time(0);
// multiplyMatStandard(a,b,c,matSize);
// elapsedTime = time(0) - startTime;
// standardTime[k] = elapsedTime;
//multiplication using Strassen'
if(my_list[k]<=1000){
for(int j=0;j<5;j++){
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// cout<<startTime<<endl;
multiplyStrassen(a,b,c,matSize);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
l[j]=cpu_elapsed_time_ms;
//printf("%lf\n",cpu_elapsed_time_ms);
}// elapsedTime = time(0) - startTime;
// double duration = elapsedTime;
// clock_t begin1 = clock();
// multiplyStrassen(a,b,c,matSize);
// clock_t end1 = clock();
// double time_spent1 = (double)1000*(end1 - begin1) / CLOCKS_PER_SEC;
double avg;
avg=(l[0]+l[1]+l[2]+l[3]+l[4])/5;
cout << "Using Milliseconds Clock: (AVG)"<< endl;
cout << " CPU time taken to execute for strassen matrices of size - "
<< matSize << " : " <<avg<<" ms"<< endl;
cout << endl;
fprintf(fp,"\n%s,%d,%lf",algoname,matSize,avg);
}else{
int matSize = my_list[k];
vector< vector<double> >
a(matSize,vector<double>(matSize)),
b(matSize,vector<double>(matSize)),
c(matSize,vector<double>(matSize));
initMat(a,b,matSize);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// cout<<startTime<<endl;
multiplyStrassen(a,b,c,matSize);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
cout << "Using Milliseconds Clock:(else above 1000) "<< endl;
cout << " CPU time taken to execute for strassen matrices of size - "
<< matSize << " : " <<cpu_elapsed_time_ms<<" ms"<< endl;
cout << endl;
fprintf(fp,"\n%s,%d,%lf",algoname,matSize,cpu_elapsed_time_ms);
}
// }
// cout << "Standard multiplication"<< endl;
// standardMean = calculateMean(standardTime, sampleSize);
// cout << "Average time taken to execute matrices of size - "
// << matSize << " : " << standardMean << endl;
// cout << endl;
// cout << "Multiplication using given Original Clock Strassen's"<< endl;
// cout << "Average time taken to execute matrices of size - "
// << matSize << " : " << time_spent1 << endl;
// cout << endl;
// cout << "Speed up gained by using Strassen's-" << matSize
// << " : " << standardMean/strassenMean << endl;
// cout << endl;
}else{
cout<<"MAX LIMIT"<<endl;
int max_limit=800000;
fprintf(fp,"\n%s,%d,%d",algoname,my_list[k],max_limit);
}
}
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <ctime>
#include <cstdlib>
#include <vector>
#include <cmath>
#include <list>
using namespace std;
//size at which the sequential multiplication is used instead of recursive Strassen
int thresholdSize = 128;
void initMat(vector< vector<double> > &a, vector< vector<double> > &b, int n)
{
// initialize matrices and fill them with random values
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
a[i][j] = (double)rand()/RAND_MAX*10;
b[i][j] = (double)rand()/RAND_MAX*10;
}
}
}
void multiplyMatStandard(vector< vector<double> > &a,
vector< vector<double> > &b, vector< vector<double> > &c, int n)
{
// standard matrix multipmlication: C <- C + A x B
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
double temp = 0;
for (int k = 0; k < n; ++k) {
temp += a[i][k] * b[k][j];
}
c[i][j]=temp;
}
}
}
int getNextPowerOfTwo(int n)
{
return pow(2, int(ceil(log2(n))));
}
void fillZeros(vector< vector<double> > &newA, vector< vector<double> > &newB,
vector< vector<double> > &a, vector< vector<double> > &b, int n)
{
//pad matrix with zeros
for (int i=0; i<n; i++){
for (int j=0; j<n; j++){
newA[i][j] = a[i][j];
newB[i][j] = b[i][j];
}
}
}
void add(vector< vector<double> > &a, vector< vector<double> > &b,
vector< vector<double> > &resultMatrix, int n)
{
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
resultMatrix[i][j] = a[i][j] + b[i][j];
}
}
}
void subtract(vector< vector<double> > &a, vector< vector<double> > &b,
vector< vector<double> > &resultMatrix, int n)
{
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
resultMatrix[i][j] = a[i][j] - b[i][j];
}
}
}
void multiplyStrassen(vector< vector<double> > &a,
vector< vector<double> > &b, vector< vector<double> > &c, int n)
{
if(n<=thresholdSize){
multiplyMatStandard(a, b, c, n);
}
else{
//expand and fill with zeros if matrix size is not a power of two
int newSize = getNextPowerOfTwo(n);
vector< vector<double> >
newA(newSize, vector<double>(newSize)),
newB(newSize, vector<double>(newSize)),
newC(newSize, vector<double>(newSize));
if(n==newSize){ //matrix size is already a power of two
newA = a;
newB = b;
}
else{
fillZeros(newA, newB, a, b, n);
}
//initialize submatrices
int blockSize = newSize/2; //size for a partition matrix
vector<double> block (blockSize);
vector< vector<double> >
/*partitions of newA*/
a11(blockSize, block), a12(blockSize, block),
a21(blockSize, block), a22(blockSize, block),
/*partitions of newB*/
b11(blockSize, block), b12(blockSize, block),
b21(blockSize, block), b22(blockSize, block),
/*partitions of newC*/
c11(blockSize, block), c12(blockSize, block),
c21(blockSize, block), c22(blockSize, block),
/*matrices storing intermediate results*/
aBlock(blockSize, block), bBlock(blockSize, block),
/*set of submatrices derived from partitions*/
m1(blockSize, block), m2(blockSize, block),
m3(blockSize, block), m4(blockSize, block),
m5(blockSize, block), m6(blockSize, block),
m7(blockSize, block);
//partition matrices
for (int i=0; i<blockSize; i++){
for (int j=0; j<blockSize; j++){
a11[i][j] = newA[i][j];
a12[i][j] = newA[i][j+blockSize];
a21[i][j] = newA[i+blockSize][j];
a22[i][j] = newA[i+blockSize][j+blockSize];
b11[i][j] = newB[i][j];
b12[i][j] = newB[i][j+blockSize];
b21[i][j] = newB[i+blockSize][j];
b22[i][j] = newB[i+blockSize][j+blockSize];
}
}
//compute submatrices
//m1 = (a11+a22)(b11+b22)
add(a11, a22, aBlock, blockSize);
add(b11, b22, bBlock, blockSize);
multiplyStrassen(aBlock, bBlock, m1, blockSize);
//m2 = (a21+a22)b11
add(a21, a22, aBlock, blockSize);
multiplyStrassen(aBlock, b11, m2, blockSize);
//m3 = a11(b12-b22)
subtract(b12, b22, bBlock, blockSize);
multiplyStrassen(a11, bBlock, m3, blockSize);
//m4 = a22(b21-b11)
subtract(b21, b11, bBlock, blockSize);
multiplyStrassen(a22, bBlock, m4, blockSize);
//m5 = (a11+a12)b22
add(a11, a12, aBlock, blockSize);
multiplyStrassen(aBlock, b22, m5, blockSize);
//m6 = (a21-a11)(b11+b12)
subtract(a21, a11, aBlock, blockSize);
add(b11, b12, bBlock, blockSize);
multiplyStrassen(aBlock, bBlock, m6, blockSize);
//m7 = (a12-a22)(b12+b22)
subtract(a12, a22, aBlock, blockSize);
add(b12, b22, bBlock, blockSize);
multiplyStrassen(aBlock, bBlock, m7, blockSize);
//calculate result submatrices
//c11 = m1+m4-m5+m7
add(m1, m4, aBlock, blockSize);
subtract(aBlock, m5, bBlock, blockSize);
add(bBlock, m7, c11, blockSize);
//c12 = m3+m5
add(m3, m5, c12, blockSize);
//c21 = m2+m4
add(m2, m4, c12, blockSize);
//c22 = m1-m2+m3+m6
subtract(m1, m2, aBlock, blockSize);
add(aBlock, m3, bBlock, blockSize);
add(bBlock, m6, c22, blockSize);
//calculate final result matrix
for(int i=0; i<blockSize; i++){
for(int j=0; j<blockSize; j++){
newC[i][j] = c11[i][j];
newC[i][blockSize+j] = c12[i][j];
newC[blockSize+i][j] = c21[i][j];
newC[blockSize+i][blockSize+j] = c22[i][j];
}
}
//remove additional values from expanded matrix
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
c[i][j] = newC[i][j];
}
}
}
}
double calculateMean(vector<double> data, int size)
{
double sum = 0.0, mean = 0.0;
for (int i = 0; i < size; ++i) {
sum += data[i];
}
mean = sum / size;
return mean;
}
int main()
{
//srand(time(0)); //seed for random number generation
// number of sample size considered to evaluate average execution time
FILE * fp;
fp=fopen("Strassen_Multiplication_UPDATED_CPU.csv","w+");
fprintf(fp, "Algorithm_Name,Input_Dimensions,Execution_Time(ms)");
double startTime;
double elapsedTime;
double standardMean;
double strassenMean;
float cpu_elapsed_time_ms;
char algoname[100]="Strassen_Matrix_Multiplication_CPU";
int my_list[]={1008, 1040, 1072, 1104, 1136, 1168, 1200, 1232, 1264, 1296, 1328, 1360, 1392, 1424, 1456, 1488, 1520, 1552, 1584, 1616, 1648, 1680, 1712, 1744, 1776, 1808, 1840, 1872, 1904, 1936, 1968, 2000, 2032, 2064, 2096, 2128, 2160, 2192, 2224, 2256, 2288, 2320, 2352, 2384, 2416, 2448, 2480, 2512, 2544, 2576, 2608, 2640, 2672, 2704, 2736, 2768, 2800, 2832, 2864, 2896, 2928, 2960, 2992, 3024, 3056, 3088, 3120, 3152, 3184, 3216, 3248, 3280, 3312, 3344, 3376, 3408, 3440, 3472, 3504, 3536, 3568, 3600, 3632, 3664, 3696, 3728, 3760, 3792, 3824, 3856, 3888, 3920, 3952, 3984, 4016, 4080, 4144, 4208, 4272, 4336, 4400, 4464, 4528, 4592, 4656, 4720, 4784, 4848, 4912, 4976, 5040, 5104, 5168, 5232, 5296, 5360, 5424, 5488, 5552, 5616, 5680, 5744, 5808, 5872, 5936, 6000, 6064, 6128, 6192, 6256, 6320, 6384, 6448, 6512, 6576, 6640, 6704, 6768, 6832, 6896, 6960, 7024, 7088, 7152, 7216, 7280, 7344, 7408, 7472, 7536, 7600, 7664, 7728, 7792, 7856, 7920, 7984, 8048, 8112, 8176, 8240, 8304, 8368, 8432, 8496, 8560, 8624, 8688, 8752, 8816, 8880, 8944, 9008, 9072, 9136, 9200, 9264, 9328, 9392, 9456, 9520, 9584, 9648, 9712, 9776, 9840, 9904, 9968, 10032, 10096, 10160, 10224, 10288, 10352, 10416, 10480, 10544, 10608, 10672, 10736, 10800, 10864, 10928, 10992};
int length=sizeof(my_list)/sizeof(my_list[0]);
printf("%d\n",length);
//set threshold value if given by user
// if(argc>1){
// thresholdSize = atoi(argv[1]);
// }
//vectors storing execution time values
// vector<double> standardTime(sampleSize);
// vector<double> strassenTime(sampleSize);
for (int k = 0; k < length; k++) {
//initialize vectors for matrices a, b, c: a*b = c
if(my_list[k]<=3500){
int matSize = my_list[k];
vector< vector<double> >
a(matSize,vector<double>(matSize)),
b(matSize,vector<double>(matSize)),
c(matSize,vector<double>(matSize));
initMat(a,b,matSize);
double l[5];
// //standard execution
// startTime = time(0);
// multiplyMatStandard(a,b,c,matSize);
// elapsedTime = time(0) - startTime;
// standardTime[k] = elapsedTime;
//multiplication using Strassen'
if(my_list[k]<=1000){
for(int j=0;j<5;j++){
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// cout<<startTime<<endl;
multiplyStrassen(a,b,c,matSize);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
l[j]=cpu_elapsed_time_ms;
//printf("%lf\n",cpu_elapsed_time_ms);
}// elapsedTime = time(0) - startTime;
// double duration = elapsedTime;
// clock_t begin1 = clock();
// multiplyStrassen(a,b,c,matSize);
// clock_t end1 = clock();
// double time_spent1 = (double)1000*(end1 - begin1) / CLOCKS_PER_SEC;
double avg;
avg=(l[0]+l[1]+l[2]+l[3]+l[4])/5;
cout << "Using Milliseconds Clock: (AVG)"<< endl;
cout << " CPU time taken to execute for strassen matrices of size - "
<< matSize << " : " <<avg<<" ms"<< endl;
cout << endl;
fprintf(fp,"\n%s,%d,%lf",algoname,matSize,avg);
}else{
int matSize = my_list[k];
vector< vector<double> >
a(matSize,vector<double>(matSize)),
b(matSize,vector<double>(matSize)),
c(matSize,vector<double>(matSize));
initMat(a,b,matSize);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// cout<<startTime<<endl;
multiplyStrassen(a,b,c,matSize);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
cout << "Using Milliseconds Clock:(else above 1000) "<< endl;
cout << " CPU time taken to execute for strassen matrices of size - "
<< matSize << " : " <<cpu_elapsed_time_ms<<" ms"<< endl;
cout << endl;
fprintf(fp,"\n%s,%d,%lf",algoname,matSize,cpu_elapsed_time_ms);
}
// }
// cout << "Standard multiplication"<< endl;
// standardMean = calculateMean(standardTime, sampleSize);
// cout << "Average time taken to execute matrices of size - "
// << matSize << " : " << standardMean << endl;
// cout << endl;
// cout << "Multiplication using given Original Clock Strassen's"<< endl;
// cout << "Average time taken to execute matrices of size - "
// << matSize << " : " << time_spent1 << endl;
// cout << endl;
// cout << "Speed up gained by using Strassen's-" << matSize
// << " : " << standardMean/strassenMean << endl;
// cout << endl;
}else{
cout<<"MAX LIMIT"<<endl;
int max_limit=800000;
fprintf(fp,"\n%s,%d,%d",algoname,my_list[k],max_limit);
}
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <ctime>
#include <cstdlib>
#include <vector>
#include <cmath>
#include <list>
using namespace std;
//size at which the sequential multiplication is used instead of recursive Strassen
int thresholdSize = 128;
void initMat(vector< vector<double> > &a, vector< vector<double> > &b, int n)
{
// initialize matrices and fill them with random values
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
a[i][j] = (double)rand()/RAND_MAX*10;
b[i][j] = (double)rand()/RAND_MAX*10;
}
}
}
void multiplyMatStandard(vector< vector<double> > &a,
vector< vector<double> > &b, vector< vector<double> > &c, int n)
{
// standard matrix multipmlication: C <- C + A x B
for (int i = 0; i < n; ++i) {
for (int j = 0; j < n; ++j) {
double temp = 0;
for (int k = 0; k < n; ++k) {
temp += a[i][k] * b[k][j];
}
c[i][j]=temp;
}
}
}
int getNextPowerOfTwo(int n)
{
return pow(2, int(ceil(log2(n))));
}
void fillZeros(vector< vector<double> > &newA, vector< vector<double> > &newB,
vector< vector<double> > &a, vector< vector<double> > &b, int n)
{
//pad matrix with zeros
for (int i=0; i<n; i++){
for (int j=0; j<n; j++){
newA[i][j] = a[i][j];
newB[i][j] = b[i][j];
}
}
}
void add(vector< vector<double> > &a, vector< vector<double> > &b,
vector< vector<double> > &resultMatrix, int n)
{
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
resultMatrix[i][j] = a[i][j] + b[i][j];
}
}
}
void subtract(vector< vector<double> > &a, vector< vector<double> > &b,
vector< vector<double> > &resultMatrix, int n)
{
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
resultMatrix[i][j] = a[i][j] - b[i][j];
}
}
}
void multiplyStrassen(vector< vector<double> > &a,
vector< vector<double> > &b, vector< vector<double> > &c, int n)
{
if(n<=thresholdSize){
multiplyMatStandard(a, b, c, n);
}
else{
//expand and fill with zeros if matrix size is not a power of two
int newSize = getNextPowerOfTwo(n);
vector< vector<double> >
newA(newSize, vector<double>(newSize)),
newB(newSize, vector<double>(newSize)),
newC(newSize, vector<double>(newSize));
if(n==newSize){ //matrix size is already a power of two
newA = a;
newB = b;
}
else{
fillZeros(newA, newB, a, b, n);
}
//initialize submatrices
int blockSize = newSize/2; //size for a partition matrix
vector<double> block (blockSize);
vector< vector<double> >
/*partitions of newA*/
a11(blockSize, block), a12(blockSize, block),
a21(blockSize, block), a22(blockSize, block),
/*partitions of newB*/
b11(blockSize, block), b12(blockSize, block),
b21(blockSize, block), b22(blockSize, block),
/*partitions of newC*/
c11(blockSize, block), c12(blockSize, block),
c21(blockSize, block), c22(blockSize, block),
/*matrices storing intermediate results*/
aBlock(blockSize, block), bBlock(blockSize, block),
/*set of submatrices derived from partitions*/
m1(blockSize, block), m2(blockSize, block),
m3(blockSize, block), m4(blockSize, block),
m5(blockSize, block), m6(blockSize, block),
m7(blockSize, block);
//partition matrices
for (int i=0; i<blockSize; i++){
for (int j=0; j<blockSize; j++){
a11[i][j] = newA[i][j];
a12[i][j] = newA[i][j+blockSize];
a21[i][j] = newA[i+blockSize][j];
a22[i][j] = newA[i+blockSize][j+blockSize];
b11[i][j] = newB[i][j];
b12[i][j] = newB[i][j+blockSize];
b21[i][j] = newB[i+blockSize][j];
b22[i][j] = newB[i+blockSize][j+blockSize];
}
}
//compute submatrices
//m1 = (a11+a22)(b11+b22)
add(a11, a22, aBlock, blockSize);
add(b11, b22, bBlock, blockSize);
multiplyStrassen(aBlock, bBlock, m1, blockSize);
//m2 = (a21+a22)b11
add(a21, a22, aBlock, blockSize);
multiplyStrassen(aBlock, b11, m2, blockSize);
//m3 = a11(b12-b22)
subtract(b12, b22, bBlock, blockSize);
multiplyStrassen(a11, bBlock, m3, blockSize);
//m4 = a22(b21-b11)
subtract(b21, b11, bBlock, blockSize);
multiplyStrassen(a22, bBlock, m4, blockSize);
//m5 = (a11+a12)b22
add(a11, a12, aBlock, blockSize);
multiplyStrassen(aBlock, b22, m5, blockSize);
//m6 = (a21-a11)(b11+b12)
subtract(a21, a11, aBlock, blockSize);
add(b11, b12, bBlock, blockSize);
multiplyStrassen(aBlock, bBlock, m6, blockSize);
//m7 = (a12-a22)(b12+b22)
subtract(a12, a22, aBlock, blockSize);
add(b12, b22, bBlock, blockSize);
multiplyStrassen(aBlock, bBlock, m7, blockSize);
//calculate result submatrices
//c11 = m1+m4-m5+m7
add(m1, m4, aBlock, blockSize);
subtract(aBlock, m5, bBlock, blockSize);
add(bBlock, m7, c11, blockSize);
//c12 = m3+m5
add(m3, m5, c12, blockSize);
//c21 = m2+m4
add(m2, m4, c12, blockSize);
//c22 = m1-m2+m3+m6
subtract(m1, m2, aBlock, blockSize);
add(aBlock, m3, bBlock, blockSize);
add(bBlock, m6, c22, blockSize);
//calculate final result matrix
for(int i=0; i<blockSize; i++){
for(int j=0; j<blockSize; j++){
newC[i][j] = c11[i][j];
newC[i][blockSize+j] = c12[i][j];
newC[blockSize+i][j] = c21[i][j];
newC[blockSize+i][blockSize+j] = c22[i][j];
}
}
//remove additional values from expanded matrix
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
c[i][j] = newC[i][j];
}
}
}
}
double calculateMean(vector<double> data, int size)
{
double sum = 0.0, mean = 0.0;
for (int i = 0; i < size; ++i) {
sum += data[i];
}
mean = sum / size;
return mean;
}
int main()
{
//srand(time(0)); //seed for random number generation
// number of sample size considered to evaluate average execution time
FILE * fp;
fp=fopen("Strassen_Multiplication_UPDATED_CPU.csv","w+");
fprintf(fp, "Algorithm_Name,Input_Dimensions,Execution_Time(ms)");
double startTime;
double elapsedTime;
double standardMean;
double strassenMean;
float cpu_elapsed_time_ms;
char algoname[100]="Strassen_Matrix_Multiplication_CPU";
int my_list[]={1008, 1040, 1072, 1104, 1136, 1168, 1200, 1232, 1264, 1296, 1328, 1360, 1392, 1424, 1456, 1488, 1520, 1552, 1584, 1616, 1648, 1680, 1712, 1744, 1776, 1808, 1840, 1872, 1904, 1936, 1968, 2000, 2032, 2064, 2096, 2128, 2160, 2192, 2224, 2256, 2288, 2320, 2352, 2384, 2416, 2448, 2480, 2512, 2544, 2576, 2608, 2640, 2672, 2704, 2736, 2768, 2800, 2832, 2864, 2896, 2928, 2960, 2992, 3024, 3056, 3088, 3120, 3152, 3184, 3216, 3248, 3280, 3312, 3344, 3376, 3408, 3440, 3472, 3504, 3536, 3568, 3600, 3632, 3664, 3696, 3728, 3760, 3792, 3824, 3856, 3888, 3920, 3952, 3984, 4016, 4080, 4144, 4208, 4272, 4336, 4400, 4464, 4528, 4592, 4656, 4720, 4784, 4848, 4912, 4976, 5040, 5104, 5168, 5232, 5296, 5360, 5424, 5488, 5552, 5616, 5680, 5744, 5808, 5872, 5936, 6000, 6064, 6128, 6192, 6256, 6320, 6384, 6448, 6512, 6576, 6640, 6704, 6768, 6832, 6896, 6960, 7024, 7088, 7152, 7216, 7280, 7344, 7408, 7472, 7536, 7600, 7664, 7728, 7792, 7856, 7920, 7984, 8048, 8112, 8176, 8240, 8304, 8368, 8432, 8496, 8560, 8624, 8688, 8752, 8816, 8880, 8944, 9008, 9072, 9136, 9200, 9264, 9328, 9392, 9456, 9520, 9584, 9648, 9712, 9776, 9840, 9904, 9968, 10032, 10096, 10160, 10224, 10288, 10352, 10416, 10480, 10544, 10608, 10672, 10736, 10800, 10864, 10928, 10992};
int length=sizeof(my_list)/sizeof(my_list[0]);
printf("%d\n",length);
//set threshold value if given by user
// if(argc>1){
// thresholdSize = atoi(argv[1]);
// }
//vectors storing execution time values
// vector<double> standardTime(sampleSize);
// vector<double> strassenTime(sampleSize);
for (int k = 0; k < length; k++) {
//initialize vectors for matrices a, b, c: a*b = c
if(my_list[k]<=3500){
int matSize = my_list[k];
vector< vector<double> >
a(matSize,vector<double>(matSize)),
b(matSize,vector<double>(matSize)),
c(matSize,vector<double>(matSize));
initMat(a,b,matSize);
double l[5];
// //standard execution
// startTime = time(0);
// multiplyMatStandard(a,b,c,matSize);
// elapsedTime = time(0) - startTime;
// standardTime[k] = elapsedTime;
//multiplication using Strassen'
if(my_list[k]<=1000){
for(int j=0;j<5;j++){
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// cout<<startTime<<endl;
multiplyStrassen(a,b,c,matSize);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
l[j]=cpu_elapsed_time_ms;
//printf("%lf\n",cpu_elapsed_time_ms);
}// elapsedTime = time(0) - startTime;
// double duration = elapsedTime;
// clock_t begin1 = clock();
// multiplyStrassen(a,b,c,matSize);
// clock_t end1 = clock();
// double time_spent1 = (double)1000*(end1 - begin1) / CLOCKS_PER_SEC;
double avg;
avg=(l[0]+l[1]+l[2]+l[3]+l[4])/5;
cout << "Using Milliseconds Clock: (AVG)"<< endl;
cout << " CPU time taken to execute for strassen matrices of size - "
<< matSize << " : " <<avg<<" ms"<< endl;
cout << endl;
fprintf(fp,"\n%s,%d,%lf",algoname,matSize,avg);
}else{
int matSize = my_list[k];
vector< vector<double> >
a(matSize,vector<double>(matSize)),
b(matSize,vector<double>(matSize)),
c(matSize,vector<double>(matSize));
initMat(a,b,matSize);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// cout<<startTime<<endl;
multiplyStrassen(a,b,c,matSize);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
cout << "Using Milliseconds Clock:(else above 1000) "<< endl;
cout << " CPU time taken to execute for strassen matrices of size - "
<< matSize << " : " <<cpu_elapsed_time_ms<<" ms"<< endl;
cout << endl;
fprintf(fp,"\n%s,%d,%lf",algoname,matSize,cpu_elapsed_time_ms);
}
// }
// cout << "Standard multiplication"<< endl;
// standardMean = calculateMean(standardTime, sampleSize);
// cout << "Average time taken to execute matrices of size - "
// << matSize << " : " << standardMean << endl;
// cout << endl;
// cout << "Multiplication using given Original Clock Strassen's"<< endl;
// cout << "Average time taken to execute matrices of size - "
// << matSize << " : " << time_spent1 << endl;
// cout << endl;
// cout << "Speed up gained by using Strassen's-" << matSize
// << " : " << standardMean/strassenMean << endl;
// cout << endl;
}else{
cout<<"MAX LIMIT"<<endl;
int max_limit=800000;
fprintf(fp,"\n%s,%d,%d",algoname,my_list[k],max_limit);
}
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <curand_kernel.h>
#include <curand.h>
#include <stdio.h>
#define NUM_PARTICLES 10000
#define NUM_ITERATIONS 10000
#define TPB 256
#define N (NUM_PARTICLES/TPB + 1)
struct Particle {
float position_x;
float position_y;
float position_z;
float velocity_x;
float velocity_y;
float velocity_z;
};
__global__ void simulate(Particle* particles) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
Particle* p = &particles[id];
curandState state;
curand_init(id, id, 0, &state);
p->velocity_x += curand_uniform(&state);
p->velocity_y += curand_uniform(&state);
p->velocity_z += curand_uniform(&state);
p->position_x += p->velocity_x;
p->position_y += p->velocity_y;
p->position_z += p->velocity_z;
}
int main()
{
Particle *particles = new Particle[NUM_PARTICLES];
Particle *d_particles = new Particle[NUM_PARTICLES];
//cudaMalloc(&d_particles, sizeof(Particle) * NUM_PARTICLES);
cudaMallocHost(&d_particles, sizeof(Particle) * NUM_PARTICLES);
for (int i = 0; i < NUM_ITERATIONS; i++) {
cudaMemcpy(d_particles, particles, sizeof(Particle) * NUM_PARTICLES, cudaMemcpyHostToDevice);
simulate<<<N, TPB>>>(d_particles);
cudaMemcpy(particles, d_particles, sizeof(Particle) * NUM_PARTICLES, cudaMemcpyDeviceToHost);
}
} | .file "tmpxft_000f3188_00000000-6_exercise_2a.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z8simulateP8ParticleP8Particle
.type _Z35__device_stub__Z8simulateP8ParticleP8Particle, @function
_Z35__device_stub__Z8simulateP8ParticleP8Particle:
.LFB2296:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8simulateP8Particle(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z35__device_stub__Z8simulateP8ParticleP8Particle, .-_Z35__device_stub__Z8simulateP8ParticleP8Particle
.globl _Z8simulateP8Particle
.type _Z8simulateP8Particle, @function
_Z8simulateP8Particle:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8simulateP8ParticleP8Particle
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z8simulateP8Particle, .-_Z8simulateP8Particle
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $240000, %edi
call _Znam@PLT
movq %rax, %rbp
movl $240000, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
leaq 8(%rsp), %rdi
movl $0, %edx
movl $240000, %esi
call cudaHostAlloc@PLT
movl $10000, %ebx
jmp .L13
.L12:
movl $2, %ecx
movl $240000, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
subl $1, %ebx
je .L17
.L13:
movl $1, %ecx
movl $240000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $40, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
movq 8(%rsp), %rdi
call _Z35__device_stub__Z8simulateP8ParticleP8Particle
jmp .L12
.L17:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8simulateP8Particle"
.LC1:
.string "precalc_xorwow_matrix"
.LC2:
.string "precalc_xorwow_offset_matrix"
.LC3:
.string "mrg32k3aM1"
.LC4:
.string "mrg32k3aM2"
.LC5:
.string "mrg32k3aM1SubSeq"
.LC6:
.string "mrg32k3aM2SubSeq"
.LC7:
.string "mrg32k3aM1Seq"
.LC8:
.string "mrg32k3aM2Seq"
.LC9:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8simulateP8Particle(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <curand_kernel.h>
#include <curand.h>
#include <stdio.h>
#define NUM_PARTICLES 10000
#define NUM_ITERATIONS 10000
#define TPB 256
#define N (NUM_PARTICLES/TPB + 1)
struct Particle {
float position_x;
float position_y;
float position_z;
float velocity_x;
float velocity_y;
float velocity_z;
};
__global__ void simulate(Particle* particles) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
Particle* p = &particles[id];
curandState state;
curand_init(id, id, 0, &state);
p->velocity_x += curand_uniform(&state);
p->velocity_y += curand_uniform(&state);
p->velocity_z += curand_uniform(&state);
p->position_x += p->velocity_x;
p->position_y += p->velocity_y;
p->position_z += p->velocity_z;
}
int main()
{
Particle *particles = new Particle[NUM_PARTICLES];
Particle *d_particles = new Particle[NUM_PARTICLES];
//cudaMalloc(&d_particles, sizeof(Particle) * NUM_PARTICLES);
cudaMallocHost(&d_particles, sizeof(Particle) * NUM_PARTICLES);
for (int i = 0; i < NUM_ITERATIONS; i++) {
cudaMemcpy(d_particles, particles, sizeof(Particle) * NUM_PARTICLES, cudaMemcpyHostToDevice);
simulate<<<N, TPB>>>(d_particles);
cudaMemcpy(particles, d_particles, sizeof(Particle) * NUM_PARTICLES, cudaMemcpyDeviceToHost);
}
} | #include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include <hiprand/hiprand.h>
#include <stdio.h>
#define NUM_PARTICLES 10000
#define NUM_ITERATIONS 10000
#define TPB 256
#define N (NUM_PARTICLES/TPB + 1)
struct Particle {
float position_x;
float position_y;
float position_z;
float velocity_x;
float velocity_y;
float velocity_z;
};
__global__ void simulate(Particle* particles) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
Particle* p = &particles[id];
hiprandState state;
hiprand_init(id, id, 0, &state);
p->velocity_x += hiprand_uniform(&state);
p->velocity_y += hiprand_uniform(&state);
p->velocity_z += hiprand_uniform(&state);
p->position_x += p->velocity_x;
p->position_y += p->velocity_y;
p->position_z += p->velocity_z;
}
int main()
{
Particle *particles = new Particle[NUM_PARTICLES];
Particle *d_particles = new Particle[NUM_PARTICLES];
//cudaMalloc(&d_particles, sizeof(Particle) * NUM_PARTICLES);
hipHostMalloc(&d_particles, sizeof(Particle) * NUM_PARTICLES, hipHostMallocDefault);
for (int i = 0; i < NUM_ITERATIONS; i++) {
hipMemcpy(d_particles, particles, sizeof(Particle) * NUM_PARTICLES, hipMemcpyHostToDevice);
simulate<<<N, TPB>>>(d_particles);
hipMemcpy(particles, d_particles, sizeof(Particle) * NUM_PARTICLES, hipMemcpyDeviceToHost);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include <hiprand/hiprand.h>
#include <stdio.h>
#define NUM_PARTICLES 10000
#define NUM_ITERATIONS 10000
#define TPB 256
#define N (NUM_PARTICLES/TPB + 1)
struct Particle {
float position_x;
float position_y;
float position_z;
float velocity_x;
float velocity_y;
float velocity_z;
};
__global__ void simulate(Particle* particles) {
int id = threadIdx.x + blockIdx.x * blockDim.x;
Particle* p = &particles[id];
hiprandState state;
hiprand_init(id, id, 0, &state);
p->velocity_x += hiprand_uniform(&state);
p->velocity_y += hiprand_uniform(&state);
p->velocity_z += hiprand_uniform(&state);
p->position_x += p->velocity_x;
p->position_y += p->velocity_y;
p->position_z += p->velocity_z;
}
int main()
{
Particle *particles = new Particle[NUM_PARTICLES];
Particle *d_particles = new Particle[NUM_PARTICLES];
//cudaMalloc(&d_particles, sizeof(Particle) * NUM_PARTICLES);
hipHostMalloc(&d_particles, sizeof(Particle) * NUM_PARTICLES, hipHostMallocDefault);
for (int i = 0; i < NUM_ITERATIONS; i++) {
hipMemcpy(d_particles, particles, sizeof(Particle) * NUM_PARTICLES, hipMemcpyHostToDevice);
simulate<<<N, TPB>>>(d_particles);
hipMemcpy(particles, d_particles, sizeof(Particle) * NUM_PARTICLES, hipMemcpyDeviceToHost);
}
} | .text
.file "exercise_2a.hip"
.globl _Z23__device_stub__simulateP8Particle # -- Begin function _Z23__device_stub__simulateP8Particle
.p2align 4, 0x90
.type _Z23__device_stub__simulateP8Particle,@function
_Z23__device_stub__simulateP8Particle: # @_Z23__device_stub__simulateP8Particle
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8simulateP8Particle, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__simulateP8Particle, .Lfunc_end0-_Z23__device_stub__simulateP8Particle
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967336, %rbx # imm = 0x100000028
movl $240000, %edi # imm = 0x3A980
callq _Znam
movq %rax, %r14
movl $240000, %edi # imm = 0x3A980
callq _Znam
movq %rax, 8(%rsp)
leaq 8(%rsp), %rdi
movl $240000, %esi # imm = 0x3A980
xorl %edx, %edx
callq hipHostMalloc
movl $10000, %ebp # imm = 0x2710
leaq 216(%rbx), %r15
leaq 32(%rsp), %r12
leaq 16(%rsp), %r13
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rsi
movl $240000, %edx # imm = 0x3A980
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
decl %ebp
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rdi
movl $240000, %edx # imm = 0x3A980
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z8simulateP8Particle, %edi
movq %r13, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_3
.LBB1_4:
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8simulateP8Particle, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8simulateP8Particle,@object # @_Z8simulateP8Particle
.section .rodata,"a",@progbits
.globl _Z8simulateP8Particle
.p2align 3, 0x0
_Z8simulateP8Particle:
.quad _Z23__device_stub__simulateP8Particle
.size _Z8simulateP8Particle, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8simulateP8Particle"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__simulateP8Particle
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8simulateP8Particle
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f3188_00000000-6_exercise_2a.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z8simulateP8ParticleP8Particle
.type _Z35__device_stub__Z8simulateP8ParticleP8Particle, @function
_Z35__device_stub__Z8simulateP8ParticleP8Particle:
.LFB2296:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8simulateP8Particle(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z35__device_stub__Z8simulateP8ParticleP8Particle, .-_Z35__device_stub__Z8simulateP8ParticleP8Particle
.globl _Z8simulateP8Particle
.type _Z8simulateP8Particle, @function
_Z8simulateP8Particle:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8simulateP8ParticleP8Particle
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z8simulateP8Particle, .-_Z8simulateP8Particle
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $240000, %edi
call _Znam@PLT
movq %rax, %rbp
movl $240000, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
leaq 8(%rsp), %rdi
movl $0, %edx
movl $240000, %esi
call cudaHostAlloc@PLT
movl $10000, %ebx
jmp .L13
.L12:
movl $2, %ecx
movl $240000, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
subl $1, %ebx
je .L17
.L13:
movl $1, %ecx
movl $240000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $40, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
movq 8(%rsp), %rdi
call _Z35__device_stub__Z8simulateP8ParticleP8Particle
jmp .L12
.L17:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8simulateP8Particle"
.LC1:
.string "precalc_xorwow_matrix"
.LC2:
.string "precalc_xorwow_offset_matrix"
.LC3:
.string "mrg32k3aM1"
.LC4:
.string "mrg32k3aM2"
.LC5:
.string "mrg32k3aM1SubSeq"
.LC6:
.string "mrg32k3aM2SubSeq"
.LC7:
.string "mrg32k3aM1Seq"
.LC8:
.string "mrg32k3aM2Seq"
.LC9:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8simulateP8Particle(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exercise_2a.hip"
.globl _Z23__device_stub__simulateP8Particle # -- Begin function _Z23__device_stub__simulateP8Particle
.p2align 4, 0x90
.type _Z23__device_stub__simulateP8Particle,@function
_Z23__device_stub__simulateP8Particle: # @_Z23__device_stub__simulateP8Particle
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8simulateP8Particle, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__simulateP8Particle, .Lfunc_end0-_Z23__device_stub__simulateP8Particle
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967336, %rbx # imm = 0x100000028
movl $240000, %edi # imm = 0x3A980
callq _Znam
movq %rax, %r14
movl $240000, %edi # imm = 0x3A980
callq _Znam
movq %rax, 8(%rsp)
leaq 8(%rsp), %rdi
movl $240000, %esi # imm = 0x3A980
xorl %edx, %edx
callq hipHostMalloc
movl $10000, %ebp # imm = 0x2710
leaq 216(%rbx), %r15
leaq 32(%rsp), %r12
leaq 16(%rsp), %r13
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rsi
movl $240000, %edx # imm = 0x3A980
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
decl %ebp
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rdi
movl $240000, %edx # imm = 0x3A980
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z8simulateP8Particle, %edi
movq %r13, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_3
.LBB1_4:
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8simulateP8Particle, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8simulateP8Particle,@object # @_Z8simulateP8Particle
.section .rodata,"a",@progbits
.globl _Z8simulateP8Particle
.p2align 3, 0x0
_Z8simulateP8Particle:
.quad _Z23__device_stub__simulateP8Particle
.size _Z8simulateP8Particle, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8simulateP8Particle"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__simulateP8Particle
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8simulateP8Particle
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //Based on the work of Andrew Krepps
#include <chrono>
#include <fstream>
#include <random>
#include <stdio.h>
#include <string>
// Uses the GPU to add the block + thread index in array_a to array_b to array_results
__global__
void add_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] + array_b[index];
}
// Uses the GPU to subtract the block + thread index in array_b from array_a to array_results
__global__
void sub_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] - array_b[index];
}
// Uses the GPU to multiply the block + thread index in array_a by array_b to array_results
__global__
void mult_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] * array_b[index];
}
// Uses the GPU to mudulot the block + thread index in array_a by array_b to array_results
__global__
void mod_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] % array_b[index];
}
int main(int argc, char** argv)
{
// read command line arguments
int totalThreads = 512;
int blockSize = 256;
bool outputResults = false;
std::string outputName;
if (argc >= 2)
{
totalThreads = atoi(argv[1]);
}
if (argc >= 3)
{
blockSize = atoi(argv[2]);
}
if (argc >= 4)
{
outputResults = true;
outputName = argv[3];
}
int numBlocks = totalThreads/blockSize;
// validate command line arguments
if (totalThreads % blockSize != 0)
{
++numBlocks;
totalThreads = numBlocks*blockSize;
printf("Warning: Total thread count is not evenly divisible by the block size\n");
printf("The total number of threads will be rounded up to %d\n", totalThreads);
}
// Used for random number generation
std::default_random_engine generator;
std::uniform_int_distribution<int> distribution(0,3);
// Device variables
int* d_array_a;
int* d_array_b;
int* d_add_results;
int* d_sub_results;
int* d_mult_results;
int* d_mod_results;
// Host Variables
int array_a[totalThreads];
int array_b[totalThreads];
int add_results[totalThreads];
int sub_results[totalThreads];
int mult_results[totalThreads];
int mod_results[totalThreads];
// Generate values for arrays.
for( int i = 0; i < totalThreads; i++ )
{
array_a[i] = i;
array_b[i] = distribution( generator );
}
auto array_size = totalThreads * sizeof(int);
// Malloc GPU arrays
cudaMalloc((void **)&d_array_a, array_size);
cudaMalloc((void **)&d_array_b, array_size);
cudaMalloc((void **)&d_add_results, array_size);
cudaMalloc((void **)&d_sub_results, array_size);
cudaMalloc((void **)&d_mult_results, array_size);
cudaMalloc((void **)&d_mod_results, array_size);
// Copy array values to Device
cudaMemcpy( d_array_a, array_a, array_size, cudaMemcpyHostToDevice );
cudaMemcpy( d_array_b, array_b, array_size, cudaMemcpyHostToDevice );
// Execute assignment operations
auto start = std::chrono::high_resolution_clock::now();
add_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_add_results);
auto stop = std::chrono::high_resolution_clock::now();
auto add_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
start = std::chrono::high_resolution_clock::now();
sub_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_sub_results);
stop = std::chrono::high_resolution_clock::now();
auto sub_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
start = std::chrono::high_resolution_clock::now();
mult_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_mult_results);
stop = std::chrono::high_resolution_clock::now();
auto mult_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
start = std::chrono::high_resolution_clock::now();
mod_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_mod_results);
stop = std::chrono::high_resolution_clock::now();
auto mod_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
// Copy results to host
cudaMemcpy( &add_results, d_add_results, array_size, cudaMemcpyDeviceToHost);
cudaMemcpy( &sub_results, d_sub_results, array_size, cudaMemcpyDeviceToHost);
cudaMemcpy( &mult_results, d_mult_results, array_size, cudaMemcpyDeviceToHost);
cudaMemcpy( &mod_results, d_mod_results, array_size, cudaMemcpyDeviceToHost);
// cleanup
cudaFree(d_array_a);
cudaFree(d_array_b);
cudaFree(d_add_results);
cudaFree(d_sub_results);
cudaFree(d_mult_results);
cudaFree(d_mod_results);
printf("Results with Thread Count: %d and Block Size: %d\n", totalThreads, blockSize);
printf("Add Time nanoseconds:\t %ld\n", add_time);
printf("Sub Time nanoseconds:\t %ld\n", sub_time);
printf("Mult Time nanoseconds:\t %ld\n", mult_time);
printf("Mod Time nanoseconds:\t %ld\n", mod_time);
if (outputResults)
{
std::ofstream stream(outputName);
if (stream.is_open())
{
stream << "Results with Thread Count: " << totalThreads << " and Block Size: " << blockSize << "\n";
stream << "Add Time nanoseconds:\t" << add_time << "\n";
stream << "Sub Time nanoseconds:\t" << sub_time << "\n";
stream << "Mult Time nanoseconds:\t" << mult_time << "\n";
stream << "Mod Time nanoseconds:\t" << mod_time << "\n";
stream << "Add Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") + B(" << array_b[i] << ") = " << add_results[i] << "\n";
}
stream << "\n\nSub Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") - B(" << array_b[i] << ") = " << sub_results[i] << "\n";
}
stream << "\n\nMult Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") * B(" << array_b[i] << ") = " << mult_results[i] << "\n";
}
stream << "\n\nMult Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") % B(" << array_b[i] << ") = " << mod_results[i] << "\n";
}
}
else{
printf("FILE NOT OPEN?\n");
}
stream.close();
}
printf("\n");
} | code for sm_80
Function : _Z10mod_arraysPKiS0_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0060*/ IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0209 */
/*0070*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000e2000c1e1900 */
/*00a0*/ IABS R10, R4.reuse ; /* 0x00000004000a7213 */
/* 0x084fe40000000000 */
/*00b0*/ IABS R3, R4 ; /* 0x0000000400037213 */
/* 0x001fe40000000000 */
/*00c0*/ I2F.RP R8, R10 ; /* 0x0000000a00087306 */
/* 0x000e240000209400 */
/*00d0*/ IADD3 R3, RZ, -R3, RZ ; /* 0x80000003ff037210 */
/* 0x000fe40007ffe0ff */
/*00e0*/ IABS R12, R2 ; /* 0x00000002000c7213 */
/* 0x008fe40000000000 */
/*00f0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc40003f46270 */
/*0100*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe200078e00ff */
/*0140*/ IADD3 R11, RZ, -R7, RZ ; /* 0x80000007ff0b7210 */
/* 0x002fca0007ffe0ff */
/*0150*/ IMAD R5, R11, R10, RZ ; /* 0x0000000a0b057224 */
/* 0x000fc800078e02ff */
/*0160*/ IMAD.HI.U32 R7, R7, R5, R6 ; /* 0x0000000507077227 */
/* 0x000fcc00078e0006 */
/*0170*/ IMAD.HI.U32 R7, R7, R12, RZ ; /* 0x0000000c07077227 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD R7, R7, R3, R12 ; /* 0x0000000307077224 */
/* 0x000fe400078e020c */
/*0190*/ IMAD.WIDE R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc600078e0209 */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f04070 */
/*01b0*/ @!P0 IMAD.IADD R7, R7, 0x1, -R10 ; /* 0x0000000107078824 */
/* 0x000fe200078e0a0a */
/*01c0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f05270 */
/*01d0*/ ISETP.GT.U32.AND P1, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f24070 */
/*01e0*/ @!P1 IADD3 R7, R7, -R10, RZ ; /* 0x8000000a07079210 */
/* 0x000fc80007ffe0ff */
/*01f0*/ @!P2 IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff0707a210 */
/* 0x000fe40007ffe1ff */
/*0200*/ @!P0 LOP3.LUT R7, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff078212 */
/* 0x000fca00078e33ff */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11mult_arraysPKiS0_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD R9, R2, R5, RZ ; /* 0x0000000502097224 */
/* 0x004fca00078e02ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10sub_arraysPKiS0_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, -R5, RZ ; /* 0x8000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10add_arraysPKiS0_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //Based on the work of Andrew Krepps
#include <chrono>
#include <fstream>
#include <random>
#include <stdio.h>
#include <string>
// Uses the GPU to add the block + thread index in array_a to array_b to array_results
__global__
void add_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] + array_b[index];
}
// Uses the GPU to subtract the block + thread index in array_b from array_a to array_results
__global__
void sub_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] - array_b[index];
}
// Uses the GPU to multiply the block + thread index in array_a by array_b to array_results
__global__
void mult_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] * array_b[index];
}
// Uses the GPU to mudulot the block + thread index in array_a by array_b to array_results
__global__
void mod_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] % array_b[index];
}
int main(int argc, char** argv)
{
// read command line arguments
int totalThreads = 512;
int blockSize = 256;
bool outputResults = false;
std::string outputName;
if (argc >= 2)
{
totalThreads = atoi(argv[1]);
}
if (argc >= 3)
{
blockSize = atoi(argv[2]);
}
if (argc >= 4)
{
outputResults = true;
outputName = argv[3];
}
int numBlocks = totalThreads/blockSize;
// validate command line arguments
if (totalThreads % blockSize != 0)
{
++numBlocks;
totalThreads = numBlocks*blockSize;
printf("Warning: Total thread count is not evenly divisible by the block size\n");
printf("The total number of threads will be rounded up to %d\n", totalThreads);
}
// Used for random number generation
std::default_random_engine generator;
std::uniform_int_distribution<int> distribution(0,3);
// Device variables
int* d_array_a;
int* d_array_b;
int* d_add_results;
int* d_sub_results;
int* d_mult_results;
int* d_mod_results;
// Host Variables
int array_a[totalThreads];
int array_b[totalThreads];
int add_results[totalThreads];
int sub_results[totalThreads];
int mult_results[totalThreads];
int mod_results[totalThreads];
// Generate values for arrays.
for( int i = 0; i < totalThreads; i++ )
{
array_a[i] = i;
array_b[i] = distribution( generator );
}
auto array_size = totalThreads * sizeof(int);
// Malloc GPU arrays
cudaMalloc((void **)&d_array_a, array_size);
cudaMalloc((void **)&d_array_b, array_size);
cudaMalloc((void **)&d_add_results, array_size);
cudaMalloc((void **)&d_sub_results, array_size);
cudaMalloc((void **)&d_mult_results, array_size);
cudaMalloc((void **)&d_mod_results, array_size);
// Copy array values to Device
cudaMemcpy( d_array_a, array_a, array_size, cudaMemcpyHostToDevice );
cudaMemcpy( d_array_b, array_b, array_size, cudaMemcpyHostToDevice );
// Execute assignment operations
auto start = std::chrono::high_resolution_clock::now();
add_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_add_results);
auto stop = std::chrono::high_resolution_clock::now();
auto add_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
start = std::chrono::high_resolution_clock::now();
sub_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_sub_results);
stop = std::chrono::high_resolution_clock::now();
auto sub_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
start = std::chrono::high_resolution_clock::now();
mult_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_mult_results);
stop = std::chrono::high_resolution_clock::now();
auto mult_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
start = std::chrono::high_resolution_clock::now();
mod_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_mod_results);
stop = std::chrono::high_resolution_clock::now();
auto mod_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
// Copy results to host
cudaMemcpy( &add_results, d_add_results, array_size, cudaMemcpyDeviceToHost);
cudaMemcpy( &sub_results, d_sub_results, array_size, cudaMemcpyDeviceToHost);
cudaMemcpy( &mult_results, d_mult_results, array_size, cudaMemcpyDeviceToHost);
cudaMemcpy( &mod_results, d_mod_results, array_size, cudaMemcpyDeviceToHost);
// cleanup
cudaFree(d_array_a);
cudaFree(d_array_b);
cudaFree(d_add_results);
cudaFree(d_sub_results);
cudaFree(d_mult_results);
cudaFree(d_mod_results);
printf("Results with Thread Count: %d and Block Size: %d\n", totalThreads, blockSize);
printf("Add Time nanoseconds:\t %ld\n", add_time);
printf("Sub Time nanoseconds:\t %ld\n", sub_time);
printf("Mult Time nanoseconds:\t %ld\n", mult_time);
printf("Mod Time nanoseconds:\t %ld\n", mod_time);
if (outputResults)
{
std::ofstream stream(outputName);
if (stream.is_open())
{
stream << "Results with Thread Count: " << totalThreads << " and Block Size: " << blockSize << "\n";
stream << "Add Time nanoseconds:\t" << add_time << "\n";
stream << "Sub Time nanoseconds:\t" << sub_time << "\n";
stream << "Mult Time nanoseconds:\t" << mult_time << "\n";
stream << "Mod Time nanoseconds:\t" << mod_time << "\n";
stream << "Add Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") + B(" << array_b[i] << ") = " << add_results[i] << "\n";
}
stream << "\n\nSub Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") - B(" << array_b[i] << ") = " << sub_results[i] << "\n";
}
stream << "\n\nMult Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") * B(" << array_b[i] << ") = " << mult_results[i] << "\n";
}
stream << "\n\nMult Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") % B(" << array_b[i] << ") = " << mod_results[i] << "\n";
}
}
else{
printf("FILE NOT OPEN?\n");
}
stream.close();
}
printf("\n");
} | .file "tmpxft_00071b60_00000000-6_assignment.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4989:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4989:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z10add_arraysPKiS0_PiPKiS0_Pi
.type _Z36__device_stub__Z10add_arraysPKiS0_PiPKiS0_Pi, @function
_Z36__device_stub__Z10add_arraysPKiS0_PiPKiS0_Pi:
.LFB5011:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_arraysPKiS0_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5011:
.size _Z36__device_stub__Z10add_arraysPKiS0_PiPKiS0_Pi, .-_Z36__device_stub__Z10add_arraysPKiS0_PiPKiS0_Pi
.globl _Z10add_arraysPKiS0_Pi
.type _Z10add_arraysPKiS0_Pi, @function
_Z10add_arraysPKiS0_Pi:
.LFB5012:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10add_arraysPKiS0_PiPKiS0_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5012:
.size _Z10add_arraysPKiS0_Pi, .-_Z10add_arraysPKiS0_Pi
.globl _Z36__device_stub__Z10sub_arraysPKiS0_PiPKiS0_Pi
.type _Z36__device_stub__Z10sub_arraysPKiS0_PiPKiS0_Pi, @function
_Z36__device_stub__Z10sub_arraysPKiS0_PiPKiS0_Pi:
.LFB5013:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10sub_arraysPKiS0_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5013:
.size _Z36__device_stub__Z10sub_arraysPKiS0_PiPKiS0_Pi, .-_Z36__device_stub__Z10sub_arraysPKiS0_PiPKiS0_Pi
.globl _Z10sub_arraysPKiS0_Pi
.type _Z10sub_arraysPKiS0_Pi, @function
_Z10sub_arraysPKiS0_Pi:
.LFB5014:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10sub_arraysPKiS0_PiPKiS0_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5014:
.size _Z10sub_arraysPKiS0_Pi, .-_Z10sub_arraysPKiS0_Pi
.globl _Z37__device_stub__Z11mult_arraysPKiS0_PiPKiS0_Pi
.type _Z37__device_stub__Z11mult_arraysPKiS0_PiPKiS0_Pi, @function
_Z37__device_stub__Z11mult_arraysPKiS0_PiPKiS0_Pi:
.LFB5015:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11mult_arraysPKiS0_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5015:
.size _Z37__device_stub__Z11mult_arraysPKiS0_PiPKiS0_Pi, .-_Z37__device_stub__Z11mult_arraysPKiS0_PiPKiS0_Pi
.globl _Z11mult_arraysPKiS0_Pi
.type _Z11mult_arraysPKiS0_Pi, @function
_Z11mult_arraysPKiS0_Pi:
.LFB5016:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11mult_arraysPKiS0_PiPKiS0_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5016:
.size _Z11mult_arraysPKiS0_Pi, .-_Z11mult_arraysPKiS0_Pi
.globl _Z36__device_stub__Z10mod_arraysPKiS0_PiPKiS0_Pi
.type _Z36__device_stub__Z10mod_arraysPKiS0_PiPKiS0_Pi, @function
_Z36__device_stub__Z10mod_arraysPKiS0_PiPKiS0_Pi:
.LFB5017:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10mod_arraysPKiS0_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5017:
.size _Z36__device_stub__Z10mod_arraysPKiS0_PiPKiS0_Pi, .-_Z36__device_stub__Z10mod_arraysPKiS0_PiPKiS0_Pi
.globl _Z10mod_arraysPKiS0_Pi
.type _Z10mod_arraysPKiS0_Pi, @function
_Z10mod_arraysPKiS0_Pi:
.LFB5018:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10mod_arraysPKiS0_PiPKiS0_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5018:
.size _Z10mod_arraysPKiS0_Pi, .-_Z10mod_arraysPKiS0_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10mod_arraysPKiS0_Pi"
.LC1:
.string "_Z11mult_arraysPKiS0_Pi"
.LC2:
.string "_Z10sub_arraysPKiS0_Pi"
.LC3:
.string "_Z10add_arraysPKiS0_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5020:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mod_arraysPKiS0_Pi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11mult_arraysPKiS0_Pi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10sub_arraysPKiS0_Pi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_arraysPKiS0_Pi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5020:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE,comdat
.align 2
.weak _ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
.type _ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE, @function
_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE:
.LFB5575:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbx
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq 4(%rdx), %r12
movslq (%rdx), %rax
subq %rax, %r12
cmpq $2147483644, %r12
ja .L38
addq $1, %r12
movl $2147483645, %eax
movl $0, %edx
divq %r12
movq %rax, %r8
imulq %rax, %r12
movq (%rsi), %rdx
movabsq $8589934597, %rdi
.L39:
imulq $16807, %rdx, %rsi
movq %rsi, %rax
mulq %rdi
movq %rsi, %rcx
subq %rdx, %rcx
shrq %rcx
addq %rcx, %rdx
shrq $30, %rdx
movq %rdx, %rcx
salq $31, %rcx
subq %rdx, %rcx
subq %rcx, %rsi
movq %rsi, %rdx
leaq -1(%rsi), %rax
cmpq %r12, %rax
jnb .L39
movq %rsi, (%rbx)
movl $0, %edx
divq %r8
.L40:
addl 0(%rbp), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L47
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq %rdi, %r13
cmpq $2147483645, %r12
jbe .L41
movq %r12, %rdx
shrq %rdx
movabsq $-9223372028264841207, %rcx
movq %rdx, %rax
mulq %rcx
shrq $29, %rdx
movl %edx, %r14d
movabsq $8589934597, %r15
.L45:
movl $0, (%rsp)
movl %r14d, 4(%rsp)
movq %rsp, %rdx
movq %rbx, %rsi
movq %r13, %rdi
call _ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
cltq
movq %rax, %rcx
salq $30, %rcx
subq %rax, %rcx
addq %rcx, %rcx
imulq $16807, (%rbx), %rsi
movq %rsi, %rax
mulq %r15
movq %rsi, %rax
subq %rdx, %rax
shrq %rax
addq %rax, %rdx
shrq $30, %rdx
movq %rdx, %rax
salq $31, %rax
subq %rdx, %rax
subq %rax, %rsi
movq %rsi, (%rbx)
leaq -1(%rsi,%rcx), %rax
cmpq %rax, %r12
jb .L45
cmpq %rcx, %rax
jb .L45
jmp .L40
.L41:
imulq $16807, (%rsi), %rcx
movabsq $8589934597, %rdx
movq %rcx, %rax
mulq %rdx
movq %rcx, %rax
subq %rdx, %rax
shrq %rax
addq %rdx, %rax
shrq $30, %rax
movq %rax, %rdx
salq $31, %rdx
subq %rax, %rdx
movq %rcx, %rax
subq %rdx, %rax
movq %rax, (%rsi)
subq $1, %rax
jmp .L40
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5575:
.size _ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE, .-_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Warning: Total thread count is not evenly divisible by the block size\n"
.align 8
.LC5:
.string "The total number of threads will be rounded up to %d\n"
.align 8
.LC6:
.string "Results with Thread Count: %d and Block Size: %d\n"
.section .rodata.str1.1
.LC7:
.string "Add Time nanoseconds:\t %ld\n"
.LC8:
.string "Sub Time nanoseconds:\t %ld\n"
.LC9:
.string "Mult Time nanoseconds:\t %ld\n"
.LC10:
.string "Mod Time nanoseconds:\t %ld\n"
.LC11:
.string "Results with Thread Count: "
.LC12:
.string " and Block Size: "
.LC13:
.string "\n"
.LC14:
.string "Add Time nanoseconds:\t"
.LC15:
.string "Sub Time nanoseconds:\t"
.LC16:
.string "Mult Time nanoseconds:\t"
.LC17:
.string "Mod Time nanoseconds:\t"
.LC18:
.string "Add Results:\n"
.LC19:
.string "A("
.LC20:
.string ") + B("
.LC21:
.string ") = "
.LC22:
.string "\n\nSub Results:\n"
.LC23:
.string ") - B("
.LC24:
.string "\n\nMult Results:\n"
.LC25:
.string ") * B("
.LC26:
.string ") % B("
.LC27:
.string "FILE NOT OPEN?\n"
.text
.globl main
.type main, @function
main:
.LFB4983:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4983
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $744, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq -592(%rbp), %rax
movq %rax, -608(%rbp)
movq $0, -600(%rbp)
movb $0, -592(%rbp)
cmpl $1, %edi
jg .L101
movl $256, -720(%rbp)
movb $0, -769(%rbp)
movl $2, -760(%rbp)
movl $512, -716(%rbp)
.L49:
movq $1, -696(%rbp)
movl $0, -640(%rbp)
movl $3, -636(%rbp)
movslq -716(%rbp), %r14
leaq 0(,%r14,4), %rax
movq %rax, -712(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L51:
cmpq %rdx, %rsp
je .L52
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L51
.L101:
movl %edi, %ebx
movq %rsi, %r12
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, -716(%rbp)
cmpl $2, %ebx
jg .L102
movl $256, -720(%rbp)
movb $0, -769(%rbp)
.L50:
movl -716(%rbp), %eax
movl -720(%rbp), %ecx
cltd
idivl %ecx
movl %eax, -760(%rbp)
testl %edx, %edx
je .L49
addl $1, %eax
movl %eax, -760(%rbp)
imull %eax, %ecx
movl %ecx, %ebx
movl %ecx, -716(%rbp)
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB0:
call __printf_chk@PLT
jmp .L103
.L102:
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, -720(%rbp)
cmpl $3, %ebx
jle .L91
movq 24(%r12), %rsi
leaq -608(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignEPKc@PLT
movb $1, -769(%rbp)
jmp .L50
.L91:
movb $0, -769(%rbp)
jmp .L50
.L103:
movl %ebx, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L49
.L52:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L53
orq $0, -8(%rsp,%rax)
.L53:
movq %rsp, %r13
movq -712(%rbp), %rax
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L54:
cmpq %rdx, %rsp
je .L55
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L54
.L55:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L56
orq $0, -8(%rsp,%rax)
.L56:
movq %rsp, %r15
movq -712(%rbp), %rax
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L57:
cmpq %rdx, %rsp
je .L58
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L57
.L58:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L59
orq $0, -8(%rsp,%rax)
.L59:
movq %rsp, -728(%rbp)
movq -712(%rbp), %rax
addq $15, %rax
movq %rax, %rdx
andq $-16, %rdx
andq $-4096, %rax
movq %rsp, %rcx
subq %rax, %rcx
.L60:
cmpq %rcx, %rsp
je .L61
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L60
.L61:
movq %rdx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L62
orq $0, -8(%rsp,%rax)
.L62:
movq %rsp, -736(%rbp)
movq -712(%rbp), %rax
leaq 15(%rax), %rdx
movq %rdx, %rax
andq $-16, %rax
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L63:
cmpq %rcx, %rsp
je .L64
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L63
.L64:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L65
orq $0, -8(%rsp,%rdx)
.L65:
movq %rsp, -744(%rbp)
movq -712(%rbp), %rax
leaq 15(%rax), %rdx
movq %rdx, %rax
andq $-16, %rax
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L66:
cmpq %rcx, %rsp
je .L67
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L66
.L67:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L68
orq $0, -8(%rsp,%rdx)
.L68:
movq %rsp, -752(%rbp)
cmpl $0, -716(%rbp)
jle .L69
movl $0, %ebx
leaq -640(%rbp), %r12
.L70:
movl %ebx, 0(%r13,%rbx,4)
leaq -696(%rbp), %rsi
movq %r12, %rdx
movq %r12, %rdi
call _ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
movl %eax, (%r15,%rbx,4)
addq $1, %rbx
cmpq %rbx, %r14
jne .L70
.L69:
leaq -688(%rbp), %rdi
movq -712(%rbp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -680(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -672(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -664(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -656(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -648(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq -688(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq -680(%rbp), %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl -720(%rbp), %eax
movl %eax, %r12d
movl %eax, -620(%rbp)
movl $1, -616(%rbp)
movl $1, -612(%rbp)
movl -760(%rbp), %eax
movl %eax, %r14d
movl %eax, -632(%rbp)
movl $1, -628(%rbp)
movl $1, -624(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -620(%rbp), %rdx
movl $1, %ecx
movq -632(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L71
movq -672(%rbp), %rdx
movq -680(%rbp), %rsi
movq -688(%rbp), %rdi
call _Z36__device_stub__Z10add_arraysPKiS0_PiPKiS0_Pi
.L71:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
movq %rax, -760(%rbp)
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl %r12d, -620(%rbp)
movl $1, -616(%rbp)
movl $1, -612(%rbp)
movl %r14d, -632(%rbp)
movl $1, -628(%rbp)
movl $1, -624(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -620(%rbp), %rdx
movl $1, %ecx
movq -632(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L72
movq -664(%rbp), %rdx
movq -680(%rbp), %rsi
movq -688(%rbp), %rdi
call _Z36__device_stub__Z10sub_arraysPKiS0_PiPKiS0_Pi
.L72:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
movq %rax, -768(%rbp)
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl %r12d, -620(%rbp)
movl $1, -616(%rbp)
movl $1, -612(%rbp)
movl %r14d, -632(%rbp)
movl $1, -628(%rbp)
movl $1, -624(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -620(%rbp), %rdx
movl $1, %ecx
movq -632(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L73
movq -656(%rbp), %rdx
movq -680(%rbp), %rsi
movq -688(%rbp), %rdi
call _Z37__device_stub__Z11mult_arraysPKiS0_PiPKiS0_Pi
.L73:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
movq %rax, -784(%rbp)
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl %r12d, -620(%rbp)
movl $1, -616(%rbp)
movl $1, -612(%rbp)
movl %r14d, -632(%rbp)
movl $1, -628(%rbp)
movl $1, -624(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -620(%rbp), %rdx
movl $1, %ecx
movq -632(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L74
movq -648(%rbp), %rdx
movq -680(%rbp), %rsi
movq -688(%rbp), %rdi
call _Z36__device_stub__Z10mod_arraysPKiS0_PiPKiS0_Pi
.L74:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
movq %rax, %r12
movl $2, %ecx
movq -712(%rbp), %rbx
movq %rbx, %rdx
movq -672(%rbp), %rsi
movq -728(%rbp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -664(%rbp), %rsi
movq -736(%rbp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -656(%rbp), %rsi
movq -744(%rbp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -648(%rbp), %rsi
movq -752(%rbp), %rdi
call cudaMemcpy@PLT
movq -688(%rbp), %rdi
call cudaFree@PLT
movq -680(%rbp), %rdi
call cudaFree@PLT
movq -672(%rbp), %rdi
call cudaFree@PLT
movq -664(%rbp), %rdi
call cudaFree@PLT
movq -656(%rbp), %rdi
call cudaFree@PLT
movq -648(%rbp), %rdi
call cudaFree@PLT
movl -720(%rbp), %ecx
movl -716(%rbp), %ebx
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq -760(%rbp), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq -768(%rbp), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq -784(%rbp), %r14
movq %r14, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpb $0, -769(%rbp)
je .L75
leaq -608(%rbp), %rsi
leaq -576(%rbp), %rdi
movl $16, %edx
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1ERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@PLT
.LEHE0:
leaq -464(%rbp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L76
leaq -576(%rbp), %rdi
leaq .LC11(%rip), %rsi
.LEHB1:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl -720(%rbp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq -576(%rbp), %rdi
leaq .LC14(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq -760(%rbp), %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq -576(%rbp), %rdi
leaq .LC15(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq -768(%rbp), %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq -576(%rbp), %rdi
leaq .LC16(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r14, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq -576(%rbp), %rdi
leaq .LC17(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq -576(%rbp), %rdi
leaq .LC18(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
testl %ebx, %ebx
jle .L77
movl $0, %ebx
leaq .LC21(%rip), %r14
jmp .L78
.L104:
movl 0(%r13,%rbx), %esi
leaq -576(%rbp), %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $6, %edx
leaq .LC20(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r15,%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $4, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq -728(%rbp), %rax
movl (%rax,%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC13(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, -712(%rbp)
je .L77
.L78:
leaq -576(%rbp), %rdi
movl $2, %edx
leaq .LC19(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L104
.L77:
leaq -576(%rbp), %rdi
leaq .LC22(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, -716(%rbp)
jle .L79
movl $0, %ebx
leaq .LC21(%rip), %r14
jmp .L80
.L105:
movl 0(%r13,%rbx), %esi
leaq -576(%rbp), %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $6, %edx
leaq .LC23(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r15,%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $4, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq -736(%rbp), %rax
movl (%rax,%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC13(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, -712(%rbp)
je .L79
.L80:
leaq -576(%rbp), %rdi
movl $2, %edx
leaq .LC19(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L105
.L79:
leaq -576(%rbp), %rdi
leaq .LC24(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, -716(%rbp)
jle .L81
movl $0, %ebx
leaq .LC21(%rip), %r14
jmp .L82
.L106:
movl 0(%r13,%rbx), %esi
leaq -576(%rbp), %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $6, %edx
leaq .LC25(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r15,%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $4, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq -744(%rbp), %rax
movl (%rax,%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC13(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, -712(%rbp)
je .L81
.L82:
leaq -576(%rbp), %rdi
movl $2, %edx
leaq .LC19(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L106
.L81:
leaq -576(%rbp), %rdi
leaq .LC24(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, -716(%rbp)
jle .L83
movl $0, %ebx
leaq .LC21(%rip), %r14
jmp .L84
.L107:
movl 0(%r13,%rbx), %esi
leaq -576(%rbp), %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $6, %edx
leaq .LC26(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r15,%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $4, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq -752(%rbp), %rax
movl (%rax,%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC13(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, -712(%rbp)
je .L83
.L84:
leaq -576(%rbp), %rdi
movl $2, %edx
leaq .LC19(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L107
.L76:
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L83:
leaq -576(%rbp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
.LEHE1:
leaq -576(%rbp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L75:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB2:
call __printf_chk@PLT
.LEHE2:
leaq -608(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L108
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L93:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -576(%rbp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L86:
leaq -608(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L87
call __stack_chk_fail@PLT
.L92:
endbr64
movq %rax, %rbx
jmp .L86
.L87:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L108:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4983:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4983:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4983-.LLSDACSB4983
.LLSDACSB4983:
.uleb128 .LEHB0-.LFB4983
.uleb128 .LEHE0-.LEHB0
.uleb128 .L92-.LFB4983
.uleb128 0
.uleb128 .LEHB1-.LFB4983
.uleb128 .LEHE1-.LEHB1
.uleb128 .L93-.LFB4983
.uleb128 0
.uleb128 .LEHB2-.LFB4983
.uleb128 .LEHE2-.LEHB2
.uleb128 .L92-.LFB4983
.uleb128 0
.uleb128 .LEHB3-.LFB4983
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4983:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //Based on the work of Andrew Krepps
#include <chrono>
#include <fstream>
#include <random>
#include <stdio.h>
#include <string>
// Uses the GPU to add the block + thread index in array_a to array_b to array_results
__global__
void add_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] + array_b[index];
}
// Uses the GPU to subtract the block + thread index in array_b from array_a to array_results
__global__
void sub_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] - array_b[index];
}
// Uses the GPU to multiply the block + thread index in array_a by array_b to array_results
__global__
void mult_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] * array_b[index];
}
// Uses the GPU to mudulot the block + thread index in array_a by array_b to array_results
__global__
void mod_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] % array_b[index];
}
int main(int argc, char** argv)
{
// read command line arguments
int totalThreads = 512;
int blockSize = 256;
bool outputResults = false;
std::string outputName;
if (argc >= 2)
{
totalThreads = atoi(argv[1]);
}
if (argc >= 3)
{
blockSize = atoi(argv[2]);
}
if (argc >= 4)
{
outputResults = true;
outputName = argv[3];
}
int numBlocks = totalThreads/blockSize;
// validate command line arguments
if (totalThreads % blockSize != 0)
{
++numBlocks;
totalThreads = numBlocks*blockSize;
printf("Warning: Total thread count is not evenly divisible by the block size\n");
printf("The total number of threads will be rounded up to %d\n", totalThreads);
}
// Used for random number generation
std::default_random_engine generator;
std::uniform_int_distribution<int> distribution(0,3);
// Device variables
int* d_array_a;
int* d_array_b;
int* d_add_results;
int* d_sub_results;
int* d_mult_results;
int* d_mod_results;
// Host Variables
int array_a[totalThreads];
int array_b[totalThreads];
int add_results[totalThreads];
int sub_results[totalThreads];
int mult_results[totalThreads];
int mod_results[totalThreads];
// Generate values for arrays.
for( int i = 0; i < totalThreads; i++ )
{
array_a[i] = i;
array_b[i] = distribution( generator );
}
auto array_size = totalThreads * sizeof(int);
// Malloc GPU arrays
cudaMalloc((void **)&d_array_a, array_size);
cudaMalloc((void **)&d_array_b, array_size);
cudaMalloc((void **)&d_add_results, array_size);
cudaMalloc((void **)&d_sub_results, array_size);
cudaMalloc((void **)&d_mult_results, array_size);
cudaMalloc((void **)&d_mod_results, array_size);
// Copy array values to Device
cudaMemcpy( d_array_a, array_a, array_size, cudaMemcpyHostToDevice );
cudaMemcpy( d_array_b, array_b, array_size, cudaMemcpyHostToDevice );
// Execute assignment operations
auto start = std::chrono::high_resolution_clock::now();
add_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_add_results);
auto stop = std::chrono::high_resolution_clock::now();
auto add_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
start = std::chrono::high_resolution_clock::now();
sub_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_sub_results);
stop = std::chrono::high_resolution_clock::now();
auto sub_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
start = std::chrono::high_resolution_clock::now();
mult_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_mult_results);
stop = std::chrono::high_resolution_clock::now();
auto mult_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
start = std::chrono::high_resolution_clock::now();
mod_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_mod_results);
stop = std::chrono::high_resolution_clock::now();
auto mod_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
// Copy results to host
cudaMemcpy( &add_results, d_add_results, array_size, cudaMemcpyDeviceToHost);
cudaMemcpy( &sub_results, d_sub_results, array_size, cudaMemcpyDeviceToHost);
cudaMemcpy( &mult_results, d_mult_results, array_size, cudaMemcpyDeviceToHost);
cudaMemcpy( &mod_results, d_mod_results, array_size, cudaMemcpyDeviceToHost);
// cleanup
cudaFree(d_array_a);
cudaFree(d_array_b);
cudaFree(d_add_results);
cudaFree(d_sub_results);
cudaFree(d_mult_results);
cudaFree(d_mod_results);
printf("Results with Thread Count: %d and Block Size: %d\n", totalThreads, blockSize);
printf("Add Time nanoseconds:\t %ld\n", add_time);
printf("Sub Time nanoseconds:\t %ld\n", sub_time);
printf("Mult Time nanoseconds:\t %ld\n", mult_time);
printf("Mod Time nanoseconds:\t %ld\n", mod_time);
if (outputResults)
{
std::ofstream stream(outputName);
if (stream.is_open())
{
stream << "Results with Thread Count: " << totalThreads << " and Block Size: " << blockSize << "\n";
stream << "Add Time nanoseconds:\t" << add_time << "\n";
stream << "Sub Time nanoseconds:\t" << sub_time << "\n";
stream << "Mult Time nanoseconds:\t" << mult_time << "\n";
stream << "Mod Time nanoseconds:\t" << mod_time << "\n";
stream << "Add Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") + B(" << array_b[i] << ") = " << add_results[i] << "\n";
}
stream << "\n\nSub Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") - B(" << array_b[i] << ") = " << sub_results[i] << "\n";
}
stream << "\n\nMult Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") * B(" << array_b[i] << ") = " << mult_results[i] << "\n";
}
stream << "\n\nMult Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") % B(" << array_b[i] << ") = " << mod_results[i] << "\n";
}
}
else{
printf("FILE NOT OPEN?\n");
}
stream.close();
}
printf("\n");
} | //Based on the work of Andrew Krepps
#include <hip/hip_runtime.h>
#include <chrono>
#include <fstream>
#include <random>
#include <stdio.h>
#include <string>
// Uses the GPU to add the block + thread index in array_a to array_b to array_results
__global__
void add_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] + array_b[index];
}
// Uses the GPU to subtract the block + thread index in array_b from array_a to array_results
__global__
void sub_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] - array_b[index];
}
// Uses the GPU to multiply the block + thread index in array_a by array_b to array_results
__global__
void mult_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] * array_b[index];
}
// Uses the GPU to mudulot the block + thread index in array_a by array_b to array_results
__global__
void mod_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] % array_b[index];
}
int main(int argc, char** argv)
{
// read command line arguments
int totalThreads = 512;
int blockSize = 256;
bool outputResults = false;
std::string outputName;
if (argc >= 2)
{
totalThreads = atoi(argv[1]);
}
if (argc >= 3)
{
blockSize = atoi(argv[2]);
}
if (argc >= 4)
{
outputResults = true;
outputName = argv[3];
}
int numBlocks = totalThreads/blockSize;
// validate command line arguments
if (totalThreads % blockSize != 0)
{
++numBlocks;
totalThreads = numBlocks*blockSize;
printf("Warning: Total thread count is not evenly divisible by the block size\n");
printf("The total number of threads will be rounded up to %d\n", totalThreads);
}
// Used for random number generation
std::default_random_engine generator;
std::uniform_int_distribution<int> distribution(0,3);
// Device variables
int* d_array_a;
int* d_array_b;
int* d_add_results;
int* d_sub_results;
int* d_mult_results;
int* d_mod_results;
// Host Variables
int array_a[totalThreads];
int array_b[totalThreads];
int add_results[totalThreads];
int sub_results[totalThreads];
int mult_results[totalThreads];
int mod_results[totalThreads];
// Generate values for arrays.
for( int i = 0; i < totalThreads; i++ )
{
array_a[i] = i;
array_b[i] = distribution( generator );
}
auto array_size = totalThreads * sizeof(int);
// Malloc GPU arrays
hipMalloc((void **)&d_array_a, array_size);
hipMalloc((void **)&d_array_b, array_size);
hipMalloc((void **)&d_add_results, array_size);
hipMalloc((void **)&d_sub_results, array_size);
hipMalloc((void **)&d_mult_results, array_size);
hipMalloc((void **)&d_mod_results, array_size);
// Copy array values to Device
hipMemcpy( d_array_a, array_a, array_size, hipMemcpyHostToDevice );
hipMemcpy( d_array_b, array_b, array_size, hipMemcpyHostToDevice );
// Execute assignment operations
auto start = std::chrono::high_resolution_clock::now();
add_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_add_results);
auto stop = std::chrono::high_resolution_clock::now();
auto add_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
start = std::chrono::high_resolution_clock::now();
sub_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_sub_results);
stop = std::chrono::high_resolution_clock::now();
auto sub_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
start = std::chrono::high_resolution_clock::now();
mult_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_mult_results);
stop = std::chrono::high_resolution_clock::now();
auto mult_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
start = std::chrono::high_resolution_clock::now();
mod_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_mod_results);
stop = std::chrono::high_resolution_clock::now();
auto mod_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
// Copy results to host
hipMemcpy( &add_results, d_add_results, array_size, hipMemcpyDeviceToHost);
hipMemcpy( &sub_results, d_sub_results, array_size, hipMemcpyDeviceToHost);
hipMemcpy( &mult_results, d_mult_results, array_size, hipMemcpyDeviceToHost);
hipMemcpy( &mod_results, d_mod_results, array_size, hipMemcpyDeviceToHost);
// cleanup
hipFree(d_array_a);
hipFree(d_array_b);
hipFree(d_add_results);
hipFree(d_sub_results);
hipFree(d_mult_results);
hipFree(d_mod_results);
printf("Results with Thread Count: %d and Block Size: %d\n", totalThreads, blockSize);
printf("Add Time nanoseconds:\t %ld\n", add_time);
printf("Sub Time nanoseconds:\t %ld\n", sub_time);
printf("Mult Time nanoseconds:\t %ld\n", mult_time);
printf("Mod Time nanoseconds:\t %ld\n", mod_time);
if (outputResults)
{
std::ofstream stream(outputName);
if (stream.is_open())
{
stream << "Results with Thread Count: " << totalThreads << " and Block Size: " << blockSize << "\n";
stream << "Add Time nanoseconds:\t" << add_time << "\n";
stream << "Sub Time nanoseconds:\t" << sub_time << "\n";
stream << "Mult Time nanoseconds:\t" << mult_time << "\n";
stream << "Mod Time nanoseconds:\t" << mod_time << "\n";
stream << "Add Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") + B(" << array_b[i] << ") = " << add_results[i] << "\n";
}
stream << "\n\nSub Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") - B(" << array_b[i] << ") = " << sub_results[i] << "\n";
}
stream << "\n\nMult Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") * B(" << array_b[i] << ") = " << mult_results[i] << "\n";
}
stream << "\n\nMult Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") % B(" << array_b[i] << ") = " << mod_results[i] << "\n";
}
}
else{
printf("FILE NOT OPEN?\n");
}
stream.close();
}
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //Based on the work of Andrew Krepps
#include <hip/hip_runtime.h>
#include <chrono>
#include <fstream>
#include <random>
#include <stdio.h>
#include <string>
// Uses the GPU to add the block + thread index in array_a to array_b to array_results
__global__
void add_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] + array_b[index];
}
// Uses the GPU to subtract the block + thread index in array_b from array_a to array_results
__global__
void sub_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] - array_b[index];
}
// Uses the GPU to multiply the block + thread index in array_a by array_b to array_results
__global__
void mult_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] * array_b[index];
}
// Uses the GPU to mudulot the block + thread index in array_a by array_b to array_results
__global__
void mod_arrays(
const int* const array_a,
const int* const array_b,
int* const array_results)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
array_results[index] = array_a[index] % array_b[index];
}
int main(int argc, char** argv)
{
// read command line arguments
int totalThreads = 512;
int blockSize = 256;
bool outputResults = false;
std::string outputName;
if (argc >= 2)
{
totalThreads = atoi(argv[1]);
}
if (argc >= 3)
{
blockSize = atoi(argv[2]);
}
if (argc >= 4)
{
outputResults = true;
outputName = argv[3];
}
int numBlocks = totalThreads/blockSize;
// validate command line arguments
if (totalThreads % blockSize != 0)
{
++numBlocks;
totalThreads = numBlocks*blockSize;
printf("Warning: Total thread count is not evenly divisible by the block size\n");
printf("The total number of threads will be rounded up to %d\n", totalThreads);
}
// Used for random number generation
std::default_random_engine generator;
std::uniform_int_distribution<int> distribution(0,3);
// Device variables
int* d_array_a;
int* d_array_b;
int* d_add_results;
int* d_sub_results;
int* d_mult_results;
int* d_mod_results;
// Host Variables
int array_a[totalThreads];
int array_b[totalThreads];
int add_results[totalThreads];
int sub_results[totalThreads];
int mult_results[totalThreads];
int mod_results[totalThreads];
// Generate values for arrays.
for( int i = 0; i < totalThreads; i++ )
{
array_a[i] = i;
array_b[i] = distribution( generator );
}
auto array_size = totalThreads * sizeof(int);
// Malloc GPU arrays
hipMalloc((void **)&d_array_a, array_size);
hipMalloc((void **)&d_array_b, array_size);
hipMalloc((void **)&d_add_results, array_size);
hipMalloc((void **)&d_sub_results, array_size);
hipMalloc((void **)&d_mult_results, array_size);
hipMalloc((void **)&d_mod_results, array_size);
// Copy array values to Device
hipMemcpy( d_array_a, array_a, array_size, hipMemcpyHostToDevice );
hipMemcpy( d_array_b, array_b, array_size, hipMemcpyHostToDevice );
// Execute assignment operations
auto start = std::chrono::high_resolution_clock::now();
add_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_add_results);
auto stop = std::chrono::high_resolution_clock::now();
auto add_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
start = std::chrono::high_resolution_clock::now();
sub_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_sub_results);
stop = std::chrono::high_resolution_clock::now();
auto sub_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
start = std::chrono::high_resolution_clock::now();
mult_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_mult_results);
stop = std::chrono::high_resolution_clock::now();
auto mult_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
start = std::chrono::high_resolution_clock::now();
mod_arrays<<<numBlocks, blockSize>>>(d_array_a, d_array_b, d_mod_results);
stop = std::chrono::high_resolution_clock::now();
auto mod_time = std::chrono::duration_cast<std::chrono::nanoseconds>(stop - start).count();
// Copy results to host
hipMemcpy( &add_results, d_add_results, array_size, hipMemcpyDeviceToHost);
hipMemcpy( &sub_results, d_sub_results, array_size, hipMemcpyDeviceToHost);
hipMemcpy( &mult_results, d_mult_results, array_size, hipMemcpyDeviceToHost);
hipMemcpy( &mod_results, d_mod_results, array_size, hipMemcpyDeviceToHost);
// cleanup
hipFree(d_array_a);
hipFree(d_array_b);
hipFree(d_add_results);
hipFree(d_sub_results);
hipFree(d_mult_results);
hipFree(d_mod_results);
printf("Results with Thread Count: %d and Block Size: %d\n", totalThreads, blockSize);
printf("Add Time nanoseconds:\t %ld\n", add_time);
printf("Sub Time nanoseconds:\t %ld\n", sub_time);
printf("Mult Time nanoseconds:\t %ld\n", mult_time);
printf("Mod Time nanoseconds:\t %ld\n", mod_time);
if (outputResults)
{
std::ofstream stream(outputName);
if (stream.is_open())
{
stream << "Results with Thread Count: " << totalThreads << " and Block Size: " << blockSize << "\n";
stream << "Add Time nanoseconds:\t" << add_time << "\n";
stream << "Sub Time nanoseconds:\t" << sub_time << "\n";
stream << "Mult Time nanoseconds:\t" << mult_time << "\n";
stream << "Mod Time nanoseconds:\t" << mod_time << "\n";
stream << "Add Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") + B(" << array_b[i] << ") = " << add_results[i] << "\n";
}
stream << "\n\nSub Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") - B(" << array_b[i] << ") = " << sub_results[i] << "\n";
}
stream << "\n\nMult Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") * B(" << array_b[i] << ") = " << mult_results[i] << "\n";
}
stream << "\n\nMult Results:\n";
for( int i = 0; i < totalThreads; i++ )
{
stream << "A(" << array_a[i] << ") % B(" << array_b[i] << ") = " << mod_results[i] << "\n";
}
}
else{
printf("FILE NOT OPEN?\n");
}
stream.close();
}
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_arraysPKiS0_Pi
.globl _Z10add_arraysPKiS0_Pi
.p2align 8
.type _Z10add_arraysPKiS0_Pi,@function
_Z10add_arraysPKiS0_Pi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_arraysPKiS0_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_arraysPKiS0_Pi, .Lfunc_end0-_Z10add_arraysPKiS0_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10sub_arraysPKiS0_Pi
.globl _Z10sub_arraysPKiS0_Pi
.p2align 8
.type _Z10sub_arraysPKiS0_Pi,@function
_Z10sub_arraysPKiS0_Pi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10sub_arraysPKiS0_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10sub_arraysPKiS0_Pi, .Lfunc_end1-_Z10sub_arraysPKiS0_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11mult_arraysPKiS0_Pi
.globl _Z11mult_arraysPKiS0_Pi
.p2align 8
.type _Z11mult_arraysPKiS0_Pi,@function
_Z11mult_arraysPKiS0_Pi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11mult_arraysPKiS0_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z11mult_arraysPKiS0_Pi, .Lfunc_end2-_Z11mult_arraysPKiS0_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10mod_arraysPKiS0_Pi
.globl _Z10mod_arraysPKiS0_Pi
.p2align 8
.type _Z10mod_arraysPKiS0_Pi,@function
_Z10mod_arraysPKiS0_Pi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v3, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v3
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v2
v_xor_b32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v6
v_cvt_f32_u32_e32 v4, v3
v_sub_nc_u32_e32 v5, 0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v2, v6
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v2, v4
v_mul_lo_u32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v4
v_sub_nc_u32_e32 v4, v2, v3
v_cmp_ge_u32_e32 vcc_lo, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_sub_nc_u32_e32 v4, v2, v3
v_cmp_ge_u32_e32 vcc_lo, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_xor_b32_e32 v2, v2, v6
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10mod_arraysPKiS0_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z10mod_arraysPKiS0_Pi, .Lfunc_end3-_Z10mod_arraysPKiS0_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_arraysPKiS0_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add_arraysPKiS0_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10sub_arraysPKiS0_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10sub_arraysPKiS0_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11mult_arraysPKiS0_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11mult_arraysPKiS0_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10mod_arraysPKiS0_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10mod_arraysPKiS0_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10mod_arraysPKiS0_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0060*/ IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0209 */
/*0070*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000e2000c1e1900 */
/*00a0*/ IABS R10, R4.reuse ; /* 0x00000004000a7213 */
/* 0x084fe40000000000 */
/*00b0*/ IABS R3, R4 ; /* 0x0000000400037213 */
/* 0x001fe40000000000 */
/*00c0*/ I2F.RP R8, R10 ; /* 0x0000000a00087306 */
/* 0x000e240000209400 */
/*00d0*/ IADD3 R3, RZ, -R3, RZ ; /* 0x80000003ff037210 */
/* 0x000fe40007ffe0ff */
/*00e0*/ IABS R12, R2 ; /* 0x00000002000c7213 */
/* 0x008fe40000000000 */
/*00f0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc40003f46270 */
/*0100*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe200078e00ff */
/*0140*/ IADD3 R11, RZ, -R7, RZ ; /* 0x80000007ff0b7210 */
/* 0x002fca0007ffe0ff */
/*0150*/ IMAD R5, R11, R10, RZ ; /* 0x0000000a0b057224 */
/* 0x000fc800078e02ff */
/*0160*/ IMAD.HI.U32 R7, R7, R5, R6 ; /* 0x0000000507077227 */
/* 0x000fcc00078e0006 */
/*0170*/ IMAD.HI.U32 R7, R7, R12, RZ ; /* 0x0000000c07077227 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD R7, R7, R3, R12 ; /* 0x0000000307077224 */
/* 0x000fe400078e020c */
/*0190*/ IMAD.WIDE R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc600078e0209 */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f04070 */
/*01b0*/ @!P0 IMAD.IADD R7, R7, 0x1, -R10 ; /* 0x0000000107078824 */
/* 0x000fe200078e0a0a */
/*01c0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f05270 */
/*01d0*/ ISETP.GT.U32.AND P1, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f24070 */
/*01e0*/ @!P1 IADD3 R7, R7, -R10, RZ ; /* 0x8000000a07079210 */
/* 0x000fc80007ffe0ff */
/*01f0*/ @!P2 IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff0707a210 */
/* 0x000fe40007ffe1ff */
/*0200*/ @!P0 LOP3.LUT R7, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff078212 */
/* 0x000fca00078e33ff */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11mult_arraysPKiS0_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD R9, R2, R5, RZ ; /* 0x0000000502097224 */
/* 0x004fca00078e02ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10sub_arraysPKiS0_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, -R5, RZ ; /* 0x8000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10add_arraysPKiS0_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_arraysPKiS0_Pi
.globl _Z10add_arraysPKiS0_Pi
.p2align 8
.type _Z10add_arraysPKiS0_Pi,@function
_Z10add_arraysPKiS0_Pi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_arraysPKiS0_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_arraysPKiS0_Pi, .Lfunc_end0-_Z10add_arraysPKiS0_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10sub_arraysPKiS0_Pi
.globl _Z10sub_arraysPKiS0_Pi
.p2align 8
.type _Z10sub_arraysPKiS0_Pi,@function
_Z10sub_arraysPKiS0_Pi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10sub_arraysPKiS0_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10sub_arraysPKiS0_Pi, .Lfunc_end1-_Z10sub_arraysPKiS0_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11mult_arraysPKiS0_Pi
.globl _Z11mult_arraysPKiS0_Pi
.p2align 8
.type _Z11mult_arraysPKiS0_Pi,@function
_Z11mult_arraysPKiS0_Pi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11mult_arraysPKiS0_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z11mult_arraysPKiS0_Pi, .Lfunc_end2-_Z11mult_arraysPKiS0_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10mod_arraysPKiS0_Pi
.globl _Z10mod_arraysPKiS0_Pi
.p2align 8
.type _Z10mod_arraysPKiS0_Pi,@function
_Z10mod_arraysPKiS0_Pi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v3, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v3
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v2
v_xor_b32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v6
v_cvt_f32_u32_e32 v4, v3
v_sub_nc_u32_e32 v5, 0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v2, v6
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v2, v4
v_mul_lo_u32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v4
v_sub_nc_u32_e32 v4, v2, v3
v_cmp_ge_u32_e32 vcc_lo, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_sub_nc_u32_e32 v4, v2, v3
v_cmp_ge_u32_e32 vcc_lo, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_xor_b32_e32 v2, v2, v6
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10mod_arraysPKiS0_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z10mod_arraysPKiS0_Pi, .Lfunc_end3-_Z10mod_arraysPKiS0_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_arraysPKiS0_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add_arraysPKiS0_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10sub_arraysPKiS0_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10sub_arraysPKiS0_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11mult_arraysPKiS0_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11mult_arraysPKiS0_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10mod_arraysPKiS0_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10mod_arraysPKiS0_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __device__
double _sum_reduce(double buffer[]) {
int nTotalThreads = blockDim.x;
__syncthreads();
while (nTotalThreads > 1) {
int halfPoint = ((1 + nTotalThreads) >> 1);
if (threadIdx.x >= halfPoint) {
double temp = 0.0;
if (threadIdx.x < nTotalThreads) {
temp = buffer[threadIdx.x];
}
buffer[threadIdx.x - halfPoint] += temp;
}
__syncthreads();
nTotalThreads = ((1 + nTotalThreads) >> 1);
}
return buffer[0];
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __device__
double _sum_reduce(double buffer[]) {
int nTotalThreads = blockDim.x;
__syncthreads();
while (nTotalThreads > 1) {
int halfPoint = ((1 + nTotalThreads) >> 1);
if (threadIdx.x >= halfPoint) {
double temp = 0.0;
if (threadIdx.x < nTotalThreads) {
temp = buffer[threadIdx.x];
}
buffer[threadIdx.x - halfPoint] += temp;
}
__syncthreads();
nTotalThreads = ((1 + nTotalThreads) >> 1);
}
return buffer[0];
} | .file "tmpxft_0011d20a_00000000-6_fse-func.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11_sum_reducePd
.type _Z11_sum_reducePd, @function
_Z11_sum_reducePd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z11_sum_reducePd, .-_Z11_sum_reducePd
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __device__
double _sum_reduce(double buffer[]) {
int nTotalThreads = blockDim.x;
__syncthreads();
while (nTotalThreads > 1) {
int halfPoint = ((1 + nTotalThreads) >> 1);
if (threadIdx.x >= halfPoint) {
double temp = 0.0;
if (threadIdx.x < nTotalThreads) {
temp = buffer[threadIdx.x];
}
buffer[threadIdx.x - halfPoint] += temp;
}
__syncthreads();
nTotalThreads = ((1 + nTotalThreads) >> 1);
}
return buffer[0];
} | #include <hip/hip_runtime.h>
__device__
double _sum_reduce(double buffer[]) {
int nTotalThreads = blockDim.x;
__syncthreads();
while (nTotalThreads > 1) {
int halfPoint = ((1 + nTotalThreads) >> 1);
if (threadIdx.x >= halfPoint) {
double temp = 0.0;
if (threadIdx.x < nTotalThreads) {
temp = buffer[threadIdx.x];
}
buffer[threadIdx.x - halfPoint] += temp;
}
__syncthreads();
nTotalThreads = ((1 + nTotalThreads) >> 1);
}
return buffer[0];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__device__
double _sum_reduce(double buffer[]) {
int nTotalThreads = blockDim.x;
__syncthreads();
while (nTotalThreads > 1) {
int halfPoint = ((1 + nTotalThreads) >> 1);
if (threadIdx.x >= halfPoint) {
double temp = 0.0;
if (threadIdx.x < nTotalThreads) {
temp = buffer[threadIdx.x];
}
buffer[threadIdx.x - halfPoint] += temp;
}
__syncthreads();
nTotalThreads = ((1 + nTotalThreads) >> 1);
}
return buffer[0];
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__device__
double _sum_reduce(double buffer[]) {
int nTotalThreads = blockDim.x;
__syncthreads();
while (nTotalThreads > 1) {
int halfPoint = ((1 + nTotalThreads) >> 1);
if (threadIdx.x >= halfPoint) {
double temp = 0.0;
if (threadIdx.x < nTotalThreads) {
temp = buffer[threadIdx.x];
}
buffer[threadIdx.x - halfPoint] += temp;
}
__syncthreads();
nTotalThreads = ((1 + nTotalThreads) >> 1);
}
return buffer[0];
} | .text
.file "fse-func.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011d20a_00000000-6_fse-func.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11_sum_reducePd
.type _Z11_sum_reducePd, @function
_Z11_sum_reducePd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z11_sum_reducePd, .-_Z11_sum_reducePd
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fse-func.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <ctime>
#include <cuda.h>
#include <cuda_runtime.h>
using namespace std;
#define TILE_WIDTH 100 // for shared kernel
// CPU computation
__host__ void cpuTranspose(float* M, float* R, int dim1, int dim2){
for (int i = 0; i < dim1; i++){
for (int j = 0; j < dim2; j++){
R[j*dim2 + i] = M[i*dim2 + j];
}
}
}
// NAIVE APPROACH - global memory access only
__global__ void transpose(float* M, float* R, int dim1, int dim2){
int column = blockDim.x* blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
if(column < dim2 && row < dim1){
R[column*dim2 + row] = M[column + row*dim2];
}
// __syncthreads() not needed above as only non-conflicting read/write operations occuring
}
// SHARED MEM APROACH - use shared memory
__global__ void sharedMem_transpose(float* M, float* R, int dim1, int dim2){
// fill data into shared memory
__shared__ float M_Shared[TILE_WIDTH][TILE_WIDTH];
int column = TILE_WIDTH * blockIdx.x + threadIdx.x;
int row = TILE_WIDTH * blockIdx.y + threadIdx.y;
int index_in = row*dim2 + column;
int index_out = column*dim2 + row;
if(row < dim1 && column < dim2 && index_in < dim1*dim2){
M_Shared[threadIdx.y][threadIdx.x] = M[index_in];
}
__syncthreads(); // transfer to global mem after all threads finish computation
if(row < dim1 && column < dim2 && index_out < dim1*dim2){
R[index_out] = M_Shared[threadIdx.y][threadIdx.x];
}
}
int main(void){
int const dim1 = 3000;
int const dim2 = 3000;
float *M_h;
float *R_h;
float *M_d;
float *R_d;
size_t size = dim1*dim2*sizeof(float);
cudaMallocHost((float**)&M_h,size); //page locked host mem allocation
R_h = (float*)malloc(size);
cudaMalloc((float **)&M_d, size);
// init matrix
for (int i = 0; i < dim1*dim2; ++i) {
M_h[i]=i;
}
// asynchronous mem copies can only happen from pinned memory (direct RAM transfer)
// CPU cannot be held up in mem copies for async copy
cudaMemcpyAsync(M_d,M_h,size,cudaMemcpyHostToDevice);
cudaMalloc((float**)&R_d,size);
cudaMemset(R_d,0,size);
// init kernel
// TILE_WIDTH is chosen as per shared memory availaibility in a block
// TILE_WIDTH doesn't have much use for naive access and we could lump computatiom into fewer blocks.
int threadNumX = TILE_WIDTH;
int threadNumY = TILE_WIDTH;
int blockNumX = dim1 / TILE_WIDTH + (dim1%TILE_WIDTH == 0 ? 0 : 1 );
int blockNumY = dim2 / TILE_WIDTH + (dim2%TILE_WIDTH == 0 ? 0 : 1 );
dim3 blockSize(threadNumX,threadNumY);
dim3 gridSize(blockNumX, blockNumY);
// CUDA TIMER to Measure the performance
cudaEvent_t start_naive, start_shared, stop_shared, stop_naive;
float elapsedTime1, elapsedTime2;
cudaEventCreate(&start_naive);
cudaEventCreate(&stop_naive);
cudaEventCreate(&start_shared);
cudaEventCreate(&stop_shared);
cudaEventRecord(start_naive, 0);
transpose<<<gridSize,blockSize>>>(M_d,R_d,dim1,dim2);
cudaEventRecord(stop_naive, 0);
cudaEventSynchronize(stop_naive);
cudaEventElapsedTime(&elapsedTime1, start_naive, stop_naive);
cudaEventRecord(start_shared,0);
sharedMem_transpose<<<gridSize,blockSize>>>(M_d,R_d,dim1,dim2);
cudaEventRecord(stop_shared, 0);
cudaEventSynchronize(stop_shared);
cudaEventElapsedTime(&elapsedTime2, start_shared, stop_shared);
clock_t begin = clock();
cpuTranspose(M_h, R_h, dim1, dim2); //matrix multiplication on cpu
clock_t end = clock();
double elapsedTime3 = (double)1000*(end - begin) / CLOCKS_PER_SEC;
cout <<"Time for the NAIVE kernel: "<<elapsedTime1<<" ms"<<endl;
cout <<"Time for the SHARED kernel: "<<elapsedTime2<<" ms"<<endl;
cout <<"Time for the CPU code "<<elapsedTime3<<" ms"<<endl;
cudaFreeHost(M_h);
free(R_h);
cudaFree(R_d);
cudaFree(M_d);
return 0;
} | code for sm_80
Function : _Z19sharedMem_transposePfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x180 ; /* 0x0000014000007945 */
/* 0x000fe20003800000 */
/*0040*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, 0x64, R5 ; /* 0x0000006400007824 */
/* 0x001fca00078e0205 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R3, R3, 0x64, R4 ; /* 0x0000006403037824 */
/* 0x002fe400078e0204 */
/*00c0*/ IMAD R5, R4, 0x64, R5 ; /* 0x0000006404057824 */
/* 0x000fe400078e0205 */
/*00d0*/ IMAD R2, R3.reuse, c[0x0][0x174], R0 ; /* 0x00005d0003027a24 */
/* 0x040fe200078e0200 */
/*00e0*/ ISETP.LT.AND P0, PT, R3, c[0x0][0x170], !P0 ; /* 0x00005c0003007a0c */
/* 0x000fe20004701270 */
/*00f0*/ IMAD R0, R0, c[0x0][0x174], R3 ; /* 0x00005d0000007a24 */
/* 0x000fc600078e0203 */
/*0100*/ ISETP.GE.OR P1, PT, R2, UR4, !P0 ; /* 0x0000000402007c0c */
/* 0x000fe4000c726670 */
/*0110*/ ISETP.GE.OR P0, PT, R0, UR4, !P0 ; /* 0x0000000400007c0c */
/* 0x000fd6000c706670 */
/*0120*/ @P1 BRA 0x170 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0130*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0140*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0150*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*0160*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0041e40000004800 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01a0*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x001e220000004800 */
/*01b0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*01d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9transposePfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x174], R0 ; /* 0x00005d0005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0204 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R0, c[0x0][0x174], R5 ; /* 0x00005d0000057a24 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <ctime>
#include <cuda.h>
#include <cuda_runtime.h>
using namespace std;
#define TILE_WIDTH 100 // for shared kernel
// CPU computation
__host__ void cpuTranspose(float* M, float* R, int dim1, int dim2){
for (int i = 0; i < dim1; i++){
for (int j = 0; j < dim2; j++){
R[j*dim2 + i] = M[i*dim2 + j];
}
}
}
// NAIVE APPROACH - global memory access only
__global__ void transpose(float* M, float* R, int dim1, int dim2){
int column = blockDim.x* blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
if(column < dim2 && row < dim1){
R[column*dim2 + row] = M[column + row*dim2];
}
// __syncthreads() not needed above as only non-conflicting read/write operations occuring
}
// SHARED MEM APROACH - use shared memory
__global__ void sharedMem_transpose(float* M, float* R, int dim1, int dim2){
// fill data into shared memory
__shared__ float M_Shared[TILE_WIDTH][TILE_WIDTH];
int column = TILE_WIDTH * blockIdx.x + threadIdx.x;
int row = TILE_WIDTH * blockIdx.y + threadIdx.y;
int index_in = row*dim2 + column;
int index_out = column*dim2 + row;
if(row < dim1 && column < dim2 && index_in < dim1*dim2){
M_Shared[threadIdx.y][threadIdx.x] = M[index_in];
}
__syncthreads(); // transfer to global mem after all threads finish computation
if(row < dim1 && column < dim2 && index_out < dim1*dim2){
R[index_out] = M_Shared[threadIdx.y][threadIdx.x];
}
}
int main(void){
int const dim1 = 3000;
int const dim2 = 3000;
float *M_h;
float *R_h;
float *M_d;
float *R_d;
size_t size = dim1*dim2*sizeof(float);
cudaMallocHost((float**)&M_h,size); //page locked host mem allocation
R_h = (float*)malloc(size);
cudaMalloc((float **)&M_d, size);
// init matrix
for (int i = 0; i < dim1*dim2; ++i) {
M_h[i]=i;
}
// asynchronous mem copies can only happen from pinned memory (direct RAM transfer)
// CPU cannot be held up in mem copies for async copy
cudaMemcpyAsync(M_d,M_h,size,cudaMemcpyHostToDevice);
cudaMalloc((float**)&R_d,size);
cudaMemset(R_d,0,size);
// init kernel
// TILE_WIDTH is chosen as per shared memory availaibility in a block
// TILE_WIDTH doesn't have much use for naive access and we could lump computatiom into fewer blocks.
int threadNumX = TILE_WIDTH;
int threadNumY = TILE_WIDTH;
int blockNumX = dim1 / TILE_WIDTH + (dim1%TILE_WIDTH == 0 ? 0 : 1 );
int blockNumY = dim2 / TILE_WIDTH + (dim2%TILE_WIDTH == 0 ? 0 : 1 );
dim3 blockSize(threadNumX,threadNumY);
dim3 gridSize(blockNumX, blockNumY);
// CUDA TIMER to Measure the performance
cudaEvent_t start_naive, start_shared, stop_shared, stop_naive;
float elapsedTime1, elapsedTime2;
cudaEventCreate(&start_naive);
cudaEventCreate(&stop_naive);
cudaEventCreate(&start_shared);
cudaEventCreate(&stop_shared);
cudaEventRecord(start_naive, 0);
transpose<<<gridSize,blockSize>>>(M_d,R_d,dim1,dim2);
cudaEventRecord(stop_naive, 0);
cudaEventSynchronize(stop_naive);
cudaEventElapsedTime(&elapsedTime1, start_naive, stop_naive);
cudaEventRecord(start_shared,0);
sharedMem_transpose<<<gridSize,blockSize>>>(M_d,R_d,dim1,dim2);
cudaEventRecord(stop_shared, 0);
cudaEventSynchronize(stop_shared);
cudaEventElapsedTime(&elapsedTime2, start_shared, stop_shared);
clock_t begin = clock();
cpuTranspose(M_h, R_h, dim1, dim2); //matrix multiplication on cpu
clock_t end = clock();
double elapsedTime3 = (double)1000*(end - begin) / CLOCKS_PER_SEC;
cout <<"Time for the NAIVE kernel: "<<elapsedTime1<<" ms"<<endl;
cout <<"Time for the SHARED kernel: "<<elapsedTime2<<" ms"<<endl;
cout <<"Time for the CPU code "<<elapsedTime3<<" ms"<<endl;
cudaFreeHost(M_h);
free(R_h);
cudaFree(R_d);
cudaFree(M_d);
return 0;
} | .file "tmpxft_001552a7_00000000-6_transpose.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12cpuTransposePfS_ii
.type _Z12cpuTransposePfS_ii, @function
_Z12cpuTransposePfS_ii:
.LFB3669:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L11
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdi, %r11
movl %edx, %ebx
movslq %ecx, %rbp
leaq 0(,%rbp,4), %r8
movl $0, %r10d
movl $0, %r9d
jmp .L5
.L7:
movslq %r10d, %rdx
leaq (%r11,%rdx,4), %rax
addq %rbp, %rdx
leaq (%r11,%rdx,4), %rdi
movq %rsi, %rdx
.L6:
movss (%rax), %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
addq %r8, %rdx
cmpq %rdi, %rax
jne .L6
.L8:
addl $1, %r9d
addq $4, %rsi
addl %ecx, %r10d
cmpl %r9d, %ebx
je .L3
.L5:
testl %ecx, %ecx
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z12cpuTransposePfS_ii, .-_Z12cpuTransposePfS_ii
.globl _Z32__device_stub__Z9transposePfS_iiPfS_ii
.type _Z32__device_stub__Z9transposePfS_iiPfS_ii, @function
_Z32__device_stub__Z9transposePfS_iiPfS_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9transposePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z32__device_stub__Z9transposePfS_iiPfS_ii, .-_Z32__device_stub__Z9transposePfS_iiPfS_ii
.globl _Z9transposePfS_ii
.type _Z9transposePfS_ii, @function
_Z9transposePfS_ii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9transposePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9transposePfS_ii, .-_Z9transposePfS_ii
.globl _Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii
.type _Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii, @function
_Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19sharedMem_transposePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii, .-_Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii
.globl _Z19sharedMem_transposePfS_ii
.type _Z19sharedMem_transposePfS_ii, @function
_Z19sharedMem_transposePfS_ii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z19sharedMem_transposePfS_ii, .-_Z19sharedMem_transposePfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Time for the NAIVE kernel: "
.LC3:
.string " ms"
.LC4:
.string "Time for the SHARED kernel: "
.LC5:
.string "Time for the CPU code "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $0, %edx
movl $36000000, %esi
call cudaHostAlloc@PLT
movl $36000000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $36000000, %esi
call cudaMalloc@PLT
movl $0, %eax
.L31:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $9000000, %rax
jne .L31
movl $0, %r8d
movl $1, %ecx
movl $36000000, %edx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpyAsync@PLT
leaq 40(%rsp), %rdi
movl $36000000, %esi
call cudaMalloc@PLT
movl $36000000, %edx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
movl $100, 80(%rsp)
movl $100, 84(%rsp)
movl $1, 88(%rsp)
movl $30, 92(%rsp)
movl $30, 96(%rsp)
movl $1, 100(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L32:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 16(%rsp), %rdi
movq 72(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L33:
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
call clock@PLT
movq %rax, %rbp
movl $3000, %ecx
movl $3000, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call _Z12cpuTransposePfS_ii
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC0(%rip), %xmm0
divsd .LC1(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC4(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC5(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movl $3000, %ecx
movl $3000, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z32__device_stub__Z9transposePfS_iiPfS_ii
jmp .L32
.L38:
movl $3000, %ecx
movl $3000, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii
jmp .L33
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z19sharedMem_transposePfS_ii"
.LC7:
.string "_Z9transposePfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z19sharedMem_transposePfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <ctime>
#include <cuda.h>
#include <cuda_runtime.h>
using namespace std;
#define TILE_WIDTH 100 // for shared kernel
// CPU computation
__host__ void cpuTranspose(float* M, float* R, int dim1, int dim2){
for (int i = 0; i < dim1; i++){
for (int j = 0; j < dim2; j++){
R[j*dim2 + i] = M[i*dim2 + j];
}
}
}
// NAIVE APPROACH - global memory access only
__global__ void transpose(float* M, float* R, int dim1, int dim2){
int column = blockDim.x* blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
if(column < dim2 && row < dim1){
R[column*dim2 + row] = M[column + row*dim2];
}
// __syncthreads() not needed above as only non-conflicting read/write operations occuring
}
// SHARED MEM APROACH - use shared memory
__global__ void sharedMem_transpose(float* M, float* R, int dim1, int dim2){
// fill data into shared memory
__shared__ float M_Shared[TILE_WIDTH][TILE_WIDTH];
int column = TILE_WIDTH * blockIdx.x + threadIdx.x;
int row = TILE_WIDTH * blockIdx.y + threadIdx.y;
int index_in = row*dim2 + column;
int index_out = column*dim2 + row;
if(row < dim1 && column < dim2 && index_in < dim1*dim2){
M_Shared[threadIdx.y][threadIdx.x] = M[index_in];
}
__syncthreads(); // transfer to global mem after all threads finish computation
if(row < dim1 && column < dim2 && index_out < dim1*dim2){
R[index_out] = M_Shared[threadIdx.y][threadIdx.x];
}
}
int main(void){
int const dim1 = 3000;
int const dim2 = 3000;
float *M_h;
float *R_h;
float *M_d;
float *R_d;
size_t size = dim1*dim2*sizeof(float);
cudaMallocHost((float**)&M_h,size); //page locked host mem allocation
R_h = (float*)malloc(size);
cudaMalloc((float **)&M_d, size);
// init matrix
for (int i = 0; i < dim1*dim2; ++i) {
M_h[i]=i;
}
// asynchronous mem copies can only happen from pinned memory (direct RAM transfer)
// CPU cannot be held up in mem copies for async copy
cudaMemcpyAsync(M_d,M_h,size,cudaMemcpyHostToDevice);
cudaMalloc((float**)&R_d,size);
cudaMemset(R_d,0,size);
// init kernel
// TILE_WIDTH is chosen as per shared memory availaibility in a block
// TILE_WIDTH doesn't have much use for naive access and we could lump computatiom into fewer blocks.
int threadNumX = TILE_WIDTH;
int threadNumY = TILE_WIDTH;
int blockNumX = dim1 / TILE_WIDTH + (dim1%TILE_WIDTH == 0 ? 0 : 1 );
int blockNumY = dim2 / TILE_WIDTH + (dim2%TILE_WIDTH == 0 ? 0 : 1 );
dim3 blockSize(threadNumX,threadNumY);
dim3 gridSize(blockNumX, blockNumY);
// CUDA TIMER to Measure the performance
cudaEvent_t start_naive, start_shared, stop_shared, stop_naive;
float elapsedTime1, elapsedTime2;
cudaEventCreate(&start_naive);
cudaEventCreate(&stop_naive);
cudaEventCreate(&start_shared);
cudaEventCreate(&stop_shared);
cudaEventRecord(start_naive, 0);
transpose<<<gridSize,blockSize>>>(M_d,R_d,dim1,dim2);
cudaEventRecord(stop_naive, 0);
cudaEventSynchronize(stop_naive);
cudaEventElapsedTime(&elapsedTime1, start_naive, stop_naive);
cudaEventRecord(start_shared,0);
sharedMem_transpose<<<gridSize,blockSize>>>(M_d,R_d,dim1,dim2);
cudaEventRecord(stop_shared, 0);
cudaEventSynchronize(stop_shared);
cudaEventElapsedTime(&elapsedTime2, start_shared, stop_shared);
clock_t begin = clock();
cpuTranspose(M_h, R_h, dim1, dim2); //matrix multiplication on cpu
clock_t end = clock();
double elapsedTime3 = (double)1000*(end - begin) / CLOCKS_PER_SEC;
cout <<"Time for the NAIVE kernel: "<<elapsedTime1<<" ms"<<endl;
cout <<"Time for the SHARED kernel: "<<elapsedTime2<<" ms"<<endl;
cout <<"Time for the CPU code "<<elapsedTime3<<" ms"<<endl;
cudaFreeHost(M_h);
free(R_h);
cudaFree(R_d);
cudaFree(M_d);
return 0;
} | #include <iostream>
#include <ctime>
#include <hip/hip_runtime.h>
using namespace std;
#define TILE_WIDTH 100 // for shared kernel
// CPU computation
__host__ void cpuTranspose(float* M, float* R, int dim1, int dim2){
for (int i = 0; i < dim1; i++){
for (int j = 0; j < dim2; j++){
R[j*dim2 + i] = M[i*dim2 + j];
}
}
}
// NAIVE APPROACH - global memory access only
__global__ void transpose(float* M, float* R, int dim1, int dim2){
int column = blockDim.x* blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
if(column < dim2 && row < dim1){
R[column*dim2 + row] = M[column + row*dim2];
}
// __syncthreads() not needed above as only non-conflicting read/write operations occuring
}
// SHARED MEM APROACH - use shared memory
__global__ void sharedMem_transpose(float* M, float* R, int dim1, int dim2){
// fill data into shared memory
__shared__ float M_Shared[TILE_WIDTH][TILE_WIDTH];
int column = TILE_WIDTH * blockIdx.x + threadIdx.x;
int row = TILE_WIDTH * blockIdx.y + threadIdx.y;
int index_in = row*dim2 + column;
int index_out = column*dim2 + row;
if(row < dim1 && column < dim2 && index_in < dim1*dim2){
M_Shared[threadIdx.y][threadIdx.x] = M[index_in];
}
__syncthreads(); // transfer to global mem after all threads finish computation
if(row < dim1 && column < dim2 && index_out < dim1*dim2){
R[index_out] = M_Shared[threadIdx.y][threadIdx.x];
}
}
int main(void){
int const dim1 = 3000;
int const dim2 = 3000;
float *M_h;
float *R_h;
float *M_d;
float *R_d;
size_t size = dim1*dim2*sizeof(float);
hipHostMalloc((float**)&M_h,size, hipHostMallocDefault); //page locked host mem allocation
R_h = (float*)malloc(size);
hipMalloc((float **)&M_d, size);
// init matrix
for (int i = 0; i < dim1*dim2; ++i) {
M_h[i]=i;
}
// asynchronous mem copies can only happen from pinned memory (direct RAM transfer)
// CPU cannot be held up in mem copies for async copy
hipMemcpyAsync(M_d,M_h,size,hipMemcpyHostToDevice);
hipMalloc((float**)&R_d,size);
hipMemset(R_d,0,size);
// init kernel
// TILE_WIDTH is chosen as per shared memory availaibility in a block
// TILE_WIDTH doesn't have much use for naive access and we could lump computatiom into fewer blocks.
int threadNumX = TILE_WIDTH;
int threadNumY = TILE_WIDTH;
int blockNumX = dim1 / TILE_WIDTH + (dim1%TILE_WIDTH == 0 ? 0 : 1 );
int blockNumY = dim2 / TILE_WIDTH + (dim2%TILE_WIDTH == 0 ? 0 : 1 );
dim3 blockSize(threadNumX,threadNumY);
dim3 gridSize(blockNumX, blockNumY);
// CUDA TIMER to Measure the performance
hipEvent_t start_naive, start_shared, stop_shared, stop_naive;
float elapsedTime1, elapsedTime2;
hipEventCreate(&start_naive);
hipEventCreate(&stop_naive);
hipEventCreate(&start_shared);
hipEventCreate(&stop_shared);
hipEventRecord(start_naive, 0);
transpose<<<gridSize,blockSize>>>(M_d,R_d,dim1,dim2);
hipEventRecord(stop_naive, 0);
hipEventSynchronize(stop_naive);
hipEventElapsedTime(&elapsedTime1, start_naive, stop_naive);
hipEventRecord(start_shared,0);
sharedMem_transpose<<<gridSize,blockSize>>>(M_d,R_d,dim1,dim2);
hipEventRecord(stop_shared, 0);
hipEventSynchronize(stop_shared);
hipEventElapsedTime(&elapsedTime2, start_shared, stop_shared);
clock_t begin = clock();
cpuTranspose(M_h, R_h, dim1, dim2); //matrix multiplication on cpu
clock_t end = clock();
double elapsedTime3 = (double)1000*(end - begin) / CLOCKS_PER_SEC;
cout <<"Time for the NAIVE kernel: "<<elapsedTime1<<" ms"<<endl;
cout <<"Time for the SHARED kernel: "<<elapsedTime2<<" ms"<<endl;
cout <<"Time for the CPU code "<<elapsedTime3<<" ms"<<endl;
hipHostFree(M_h);
free(R_h);
hipFree(R_d);
hipFree(M_d);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <ctime>
#include <hip/hip_runtime.h>
using namespace std;
#define TILE_WIDTH 100 // for shared kernel
// CPU computation
__host__ void cpuTranspose(float* M, float* R, int dim1, int dim2){
for (int i = 0; i < dim1; i++){
for (int j = 0; j < dim2; j++){
R[j*dim2 + i] = M[i*dim2 + j];
}
}
}
// NAIVE APPROACH - global memory access only
__global__ void transpose(float* M, float* R, int dim1, int dim2){
int column = blockDim.x* blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
if(column < dim2 && row < dim1){
R[column*dim2 + row] = M[column + row*dim2];
}
// __syncthreads() not needed above as only non-conflicting read/write operations occuring
}
// SHARED MEM APROACH - use shared memory
__global__ void sharedMem_transpose(float* M, float* R, int dim1, int dim2){
// fill data into shared memory
__shared__ float M_Shared[TILE_WIDTH][TILE_WIDTH];
int column = TILE_WIDTH * blockIdx.x + threadIdx.x;
int row = TILE_WIDTH * blockIdx.y + threadIdx.y;
int index_in = row*dim2 + column;
int index_out = column*dim2 + row;
if(row < dim1 && column < dim2 && index_in < dim1*dim2){
M_Shared[threadIdx.y][threadIdx.x] = M[index_in];
}
__syncthreads(); // transfer to global mem after all threads finish computation
if(row < dim1 && column < dim2 && index_out < dim1*dim2){
R[index_out] = M_Shared[threadIdx.y][threadIdx.x];
}
}
int main(void){
int const dim1 = 3000;
int const dim2 = 3000;
float *M_h;
float *R_h;
float *M_d;
float *R_d;
size_t size = dim1*dim2*sizeof(float);
hipHostMalloc((float**)&M_h,size, hipHostMallocDefault); //page locked host mem allocation
R_h = (float*)malloc(size);
hipMalloc((float **)&M_d, size);
// init matrix
for (int i = 0; i < dim1*dim2; ++i) {
M_h[i]=i;
}
// asynchronous mem copies can only happen from pinned memory (direct RAM transfer)
// CPU cannot be held up in mem copies for async copy
hipMemcpyAsync(M_d,M_h,size,hipMemcpyHostToDevice);
hipMalloc((float**)&R_d,size);
hipMemset(R_d,0,size);
// init kernel
// TILE_WIDTH is chosen as per shared memory availaibility in a block
// TILE_WIDTH doesn't have much use for naive access and we could lump computatiom into fewer blocks.
int threadNumX = TILE_WIDTH;
int threadNumY = TILE_WIDTH;
int blockNumX = dim1 / TILE_WIDTH + (dim1%TILE_WIDTH == 0 ? 0 : 1 );
int blockNumY = dim2 / TILE_WIDTH + (dim2%TILE_WIDTH == 0 ? 0 : 1 );
dim3 blockSize(threadNumX,threadNumY);
dim3 gridSize(blockNumX, blockNumY);
// CUDA TIMER to Measure the performance
hipEvent_t start_naive, start_shared, stop_shared, stop_naive;
float elapsedTime1, elapsedTime2;
hipEventCreate(&start_naive);
hipEventCreate(&stop_naive);
hipEventCreate(&start_shared);
hipEventCreate(&stop_shared);
hipEventRecord(start_naive, 0);
transpose<<<gridSize,blockSize>>>(M_d,R_d,dim1,dim2);
hipEventRecord(stop_naive, 0);
hipEventSynchronize(stop_naive);
hipEventElapsedTime(&elapsedTime1, start_naive, stop_naive);
hipEventRecord(start_shared,0);
sharedMem_transpose<<<gridSize,blockSize>>>(M_d,R_d,dim1,dim2);
hipEventRecord(stop_shared, 0);
hipEventSynchronize(stop_shared);
hipEventElapsedTime(&elapsedTime2, start_shared, stop_shared);
clock_t begin = clock();
cpuTranspose(M_h, R_h, dim1, dim2); //matrix multiplication on cpu
clock_t end = clock();
double elapsedTime3 = (double)1000*(end - begin) / CLOCKS_PER_SEC;
cout <<"Time for the NAIVE kernel: "<<elapsedTime1<<" ms"<<endl;
cout <<"Time for the SHARED kernel: "<<elapsedTime2<<" ms"<<endl;
cout <<"Time for the CPU code "<<elapsedTime3<<" ms"<<endl;
hipHostFree(M_h);
free(R_h);
hipFree(R_d);
hipFree(M_d);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9transposePfS_ii
.globl _Z9transposePfS_ii
.p2align 8
.type _Z9transposePfS_ii,@function
_Z9transposePfS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9transposePfS_ii, .Lfunc_end0-_Z9transposePfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19sharedMem_transposePfS_ii
.globl _Z19sharedMem_transposePfS_ii
.p2align 8
.type _Z19sharedMem_transposePfS_ii,@function
_Z19sharedMem_transposePfS_ii:
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s14, 0x64, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, 0x64, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v3, s5, v[2:3]
v_cmp_gt_i32_e32 vcc_lo, s4, v3
v_cmp_gt_i32_e64 s2, s5, v2
s_mul_i32 s4, s5, s4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s3, s4, v4
s_and_b32 s6, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s6
s_cbranch_execz .LBB1_2
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v4, v[4:5], off
v_lshlrev_b32_e32 v5, 2, v1
v_mad_u32_u24 v5, v0, 0x190, v5
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s3
v_mad_u64_u32 v[4:5], null, v2, s5, v[3:4]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_i32_e32 vcc_lo, s4, v4
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_4
v_lshlrev_b32_e32 v1, 2, v1
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u32_u24 v0, v0, 0x190, v1
ds_load_b32 v2, v0
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19sharedMem_transposePfS_ii
.amdhsa_group_segment_fixed_size 40000
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19sharedMem_transposePfS_ii, .Lfunc_end1-_Z19sharedMem_transposePfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 40000
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19sharedMem_transposePfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19sharedMem_transposePfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <ctime>
#include <hip/hip_runtime.h>
using namespace std;
#define TILE_WIDTH 100 // for shared kernel
// CPU computation
__host__ void cpuTranspose(float* M, float* R, int dim1, int dim2){
for (int i = 0; i < dim1; i++){
for (int j = 0; j < dim2; j++){
R[j*dim2 + i] = M[i*dim2 + j];
}
}
}
// NAIVE APPROACH - global memory access only
__global__ void transpose(float* M, float* R, int dim1, int dim2){
int column = blockDim.x* blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
if(column < dim2 && row < dim1){
R[column*dim2 + row] = M[column + row*dim2];
}
// __syncthreads() not needed above as only non-conflicting read/write operations occuring
}
// SHARED MEM APROACH - use shared memory
__global__ void sharedMem_transpose(float* M, float* R, int dim1, int dim2){
// fill data into shared memory
__shared__ float M_Shared[TILE_WIDTH][TILE_WIDTH];
int column = TILE_WIDTH * blockIdx.x + threadIdx.x;
int row = TILE_WIDTH * blockIdx.y + threadIdx.y;
int index_in = row*dim2 + column;
int index_out = column*dim2 + row;
if(row < dim1 && column < dim2 && index_in < dim1*dim2){
M_Shared[threadIdx.y][threadIdx.x] = M[index_in];
}
__syncthreads(); // transfer to global mem after all threads finish computation
if(row < dim1 && column < dim2 && index_out < dim1*dim2){
R[index_out] = M_Shared[threadIdx.y][threadIdx.x];
}
}
int main(void){
int const dim1 = 3000;
int const dim2 = 3000;
float *M_h;
float *R_h;
float *M_d;
float *R_d;
size_t size = dim1*dim2*sizeof(float);
hipHostMalloc((float**)&M_h,size, hipHostMallocDefault); //page locked host mem allocation
R_h = (float*)malloc(size);
hipMalloc((float **)&M_d, size);
// init matrix
for (int i = 0; i < dim1*dim2; ++i) {
M_h[i]=i;
}
// asynchronous mem copies can only happen from pinned memory (direct RAM transfer)
// CPU cannot be held up in mem copies for async copy
hipMemcpyAsync(M_d,M_h,size,hipMemcpyHostToDevice);
hipMalloc((float**)&R_d,size);
hipMemset(R_d,0,size);
// init kernel
// TILE_WIDTH is chosen as per shared memory availaibility in a block
// TILE_WIDTH doesn't have much use for naive access and we could lump computatiom into fewer blocks.
int threadNumX = TILE_WIDTH;
int threadNumY = TILE_WIDTH;
int blockNumX = dim1 / TILE_WIDTH + (dim1%TILE_WIDTH == 0 ? 0 : 1 );
int blockNumY = dim2 / TILE_WIDTH + (dim2%TILE_WIDTH == 0 ? 0 : 1 );
dim3 blockSize(threadNumX,threadNumY);
dim3 gridSize(blockNumX, blockNumY);
// CUDA TIMER to Measure the performance
hipEvent_t start_naive, start_shared, stop_shared, stop_naive;
float elapsedTime1, elapsedTime2;
hipEventCreate(&start_naive);
hipEventCreate(&stop_naive);
hipEventCreate(&start_shared);
hipEventCreate(&stop_shared);
hipEventRecord(start_naive, 0);
transpose<<<gridSize,blockSize>>>(M_d,R_d,dim1,dim2);
hipEventRecord(stop_naive, 0);
hipEventSynchronize(stop_naive);
hipEventElapsedTime(&elapsedTime1, start_naive, stop_naive);
hipEventRecord(start_shared,0);
sharedMem_transpose<<<gridSize,blockSize>>>(M_d,R_d,dim1,dim2);
hipEventRecord(stop_shared, 0);
hipEventSynchronize(stop_shared);
hipEventElapsedTime(&elapsedTime2, start_shared, stop_shared);
clock_t begin = clock();
cpuTranspose(M_h, R_h, dim1, dim2); //matrix multiplication on cpu
clock_t end = clock();
double elapsedTime3 = (double)1000*(end - begin) / CLOCKS_PER_SEC;
cout <<"Time for the NAIVE kernel: "<<elapsedTime1<<" ms"<<endl;
cout <<"Time for the SHARED kernel: "<<elapsedTime2<<" ms"<<endl;
cout <<"Time for the CPU code "<<elapsedTime3<<" ms"<<endl;
hipHostFree(M_h);
free(R_h);
hipFree(R_d);
hipFree(M_d);
return 0;
} | .text
.file "transpose.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z12cpuTransposePfS_ii # -- Begin function _Z12cpuTransposePfS_ii
.p2align 4, 0x90
.type _Z12cpuTransposePfS_ii,@function
_Z12cpuTransposePfS_ii: # @_Z12cpuTransposePfS_ii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB0_7
# %bb.1: # %.preheader.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movslq %ecx, %rax
movl %edx, %edx
movl %eax, %r8d
shlq $2, %rax
xorl %r9d, %r9d
xorl %r10d, %r10d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r10
addl %ecx, %r9d
addq $4, %rsi
cmpq %rdx, %r10
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %ecx, %ecx
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r9d, %r11d
leaq (%rdi,%r11,4), %r11
movq %rsi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r11,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rbx)
incq %r14
addq %rax, %rbx
cmpq %r14, %r8
jne .LBB0_4
jmp .LBB0_5
.LBB0_6:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB0_7: # %._crit_edge17
retq
.Lfunc_end0:
.size _Z12cpuTransposePfS_ii, .Lfunc_end0-_Z12cpuTransposePfS_ii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__transposePfS_ii # -- Begin function _Z24__device_stub__transposePfS_ii
.p2align 4, 0x90
.type _Z24__device_stub__transposePfS_ii,@function
_Z24__device_stub__transposePfS_ii: # @_Z24__device_stub__transposePfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9transposePfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__transposePfS_ii, .Lfunc_end1-_Z24__device_stub__transposePfS_ii
.cfi_endproc
# -- End function
.globl _Z34__device_stub__sharedMem_transposePfS_ii # -- Begin function _Z34__device_stub__sharedMem_transposePfS_ii
.p2align 4, 0x90
.type _Z34__device_stub__sharedMem_transposePfS_ii,@function
_Z34__device_stub__sharedMem_transposePfS_ii: # @_Z34__device_stub__sharedMem_transposePfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19sharedMem_transposePfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z34__device_stub__sharedMem_transposePfS_ii, .Lfunc_end2-_Z34__device_stub__sharedMem_transposePfS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x408f400000000000 # double 1000
.LCPI3_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $184, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 48(%rsp), %rdi
xorl %ebx, %ebx
movl $36000000, %esi # imm = 0x2255100
xorl %edx, %edx
callq hipHostMalloc
leaq 24(%rsp), %rdi
movl $36000000, %esi # imm = 0x2255100
callq hipMalloc
movq 48(%rsp), %rax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
movss %xmm0, (%rax,%rbx,4)
incq %rbx
cmpq $9000000, %rbx # imm = 0x895440
jne .LBB3_1
# %bb.2:
movabsq $429496729700, %rbx # imm = 0x6400000064
movabsq $128849018910, %r14 # imm = 0x1E0000001E
movq 24(%rsp), %rdi
movq 48(%rsp), %rsi
movl $36000000, %edx # imm = 0x2255100
movl $1, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
leaq 16(%rsp), %rdi
movl $36000000, %esi # imm = 0x2255100
callq hipMalloc
movq 16(%rsp), %rdi
movl $36000000, %edx # imm = 0x2255100
xorl %esi, %esi
callq hipMemset
leaq 168(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 160(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
movq 168(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movl $3000, 12(%rsp) # imm = 0xBB8
movl $3000, 8(%rsp) # imm = 0xBB8
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9transposePfS_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 168(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 124(%rsp), %rdi
callq hipEventElapsedTime
movq 160(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movl $3000, 12(%rsp) # imm = 0xBB8
movl $3000, 8(%rsp) # imm = 0xBB8
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z19sharedMem_transposePfS_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6: # %_Z12cpuTransposePfS_ii.exit
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 160(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
callq clock
movq %rax, %rbx
callq clock
movq %rax, %r14
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 124(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB3_19
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB3_9
# %bb.8:
movzbl 67(%r12), %eax
jmp .LBB3_10
.LBB3_9:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB3_19
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i40
subq %rbx, %r14
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
divsd .LCPI3_1(%rip), %xmm0
movsd %xmm0, 176(%rsp) # 8-byte Spill
cmpb $0, 56(%r12)
je .LBB3_13
# %bb.12:
movzbl 67(%r12), %eax
jmp .LBB3_14
.LBB3_13:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit43
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i45
cmpb $0, 56(%r14)
je .LBB3_17
# %bb.16:
movzbl 67(%r14), %eax
jmp .LBB3_18
.LBB3_17:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit48
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 48(%rsp), %rdi
callq hipHostFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_19:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19sharedMem_transposePfS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9transposePfS_ii,@object # @_Z9transposePfS_ii
.section .rodata,"a",@progbits
.globl _Z9transposePfS_ii
.p2align 3, 0x0
_Z9transposePfS_ii:
.quad _Z24__device_stub__transposePfS_ii
.size _Z9transposePfS_ii, 8
.type _Z19sharedMem_transposePfS_ii,@object # @_Z19sharedMem_transposePfS_ii
.globl _Z19sharedMem_transposePfS_ii
.p2align 3, 0x0
_Z19sharedMem_transposePfS_ii:
.quad _Z34__device_stub__sharedMem_transposePfS_ii
.size _Z19sharedMem_transposePfS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time for the NAIVE kernel: "
.size .L.str, 28
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ms"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time for the SHARED kernel: "
.size .L.str.2, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time for the CPU code "
.size .L.str.3, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9transposePfS_ii"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19sharedMem_transposePfS_ii"
.size .L__unnamed_2, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__transposePfS_ii
.addrsig_sym _Z34__device_stub__sharedMem_transposePfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9transposePfS_ii
.addrsig_sym _Z19sharedMem_transposePfS_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19sharedMem_transposePfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x180 ; /* 0x0000014000007945 */
/* 0x000fe20003800000 */
/*0040*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, 0x64, R5 ; /* 0x0000006400007824 */
/* 0x001fca00078e0205 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R3, R3, 0x64, R4 ; /* 0x0000006403037824 */
/* 0x002fe400078e0204 */
/*00c0*/ IMAD R5, R4, 0x64, R5 ; /* 0x0000006404057824 */
/* 0x000fe400078e0205 */
/*00d0*/ IMAD R2, R3.reuse, c[0x0][0x174], R0 ; /* 0x00005d0003027a24 */
/* 0x040fe200078e0200 */
/*00e0*/ ISETP.LT.AND P0, PT, R3, c[0x0][0x170], !P0 ; /* 0x00005c0003007a0c */
/* 0x000fe20004701270 */
/*00f0*/ IMAD R0, R0, c[0x0][0x174], R3 ; /* 0x00005d0000007a24 */
/* 0x000fc600078e0203 */
/*0100*/ ISETP.GE.OR P1, PT, R2, UR4, !P0 ; /* 0x0000000402007c0c */
/* 0x000fe4000c726670 */
/*0110*/ ISETP.GE.OR P0, PT, R0, UR4, !P0 ; /* 0x0000000400007c0c */
/* 0x000fd6000c706670 */
/*0120*/ @P1 BRA 0x170 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0130*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0140*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0150*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*0160*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0041e40000004800 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01a0*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x001e220000004800 */
/*01b0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*01d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9transposePfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x174], R0 ; /* 0x00005d0005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0204 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R0, c[0x0][0x174], R5 ; /* 0x00005d0000057a24 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9transposePfS_ii
.globl _Z9transposePfS_ii
.p2align 8
.type _Z9transposePfS_ii,@function
_Z9transposePfS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9transposePfS_ii, .Lfunc_end0-_Z9transposePfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19sharedMem_transposePfS_ii
.globl _Z19sharedMem_transposePfS_ii
.p2align 8
.type _Z19sharedMem_transposePfS_ii,@function
_Z19sharedMem_transposePfS_ii:
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s14, 0x64, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, 0x64, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v3, s5, v[2:3]
v_cmp_gt_i32_e32 vcc_lo, s4, v3
v_cmp_gt_i32_e64 s2, s5, v2
s_mul_i32 s4, s5, s4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s3, s4, v4
s_and_b32 s6, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s6
s_cbranch_execz .LBB1_2
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v4, v[4:5], off
v_lshlrev_b32_e32 v5, 2, v1
v_mad_u32_u24 v5, v0, 0x190, v5
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s3
v_mad_u64_u32 v[4:5], null, v2, s5, v[3:4]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_i32_e32 vcc_lo, s4, v4
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_4
v_lshlrev_b32_e32 v1, 2, v1
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u32_u24 v0, v0, 0x190, v1
ds_load_b32 v2, v0
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19sharedMem_transposePfS_ii
.amdhsa_group_segment_fixed_size 40000
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19sharedMem_transposePfS_ii, .Lfunc_end1-_Z19sharedMem_transposePfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 40000
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19sharedMem_transposePfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19sharedMem_transposePfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001552a7_00000000-6_transpose.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12cpuTransposePfS_ii
.type _Z12cpuTransposePfS_ii, @function
_Z12cpuTransposePfS_ii:
.LFB3669:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L11
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdi, %r11
movl %edx, %ebx
movslq %ecx, %rbp
leaq 0(,%rbp,4), %r8
movl $0, %r10d
movl $0, %r9d
jmp .L5
.L7:
movslq %r10d, %rdx
leaq (%r11,%rdx,4), %rax
addq %rbp, %rdx
leaq (%r11,%rdx,4), %rdi
movq %rsi, %rdx
.L6:
movss (%rax), %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
addq %r8, %rdx
cmpq %rdi, %rax
jne .L6
.L8:
addl $1, %r9d
addq $4, %rsi
addl %ecx, %r10d
cmpl %r9d, %ebx
je .L3
.L5:
testl %ecx, %ecx
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z12cpuTransposePfS_ii, .-_Z12cpuTransposePfS_ii
.globl _Z32__device_stub__Z9transposePfS_iiPfS_ii
.type _Z32__device_stub__Z9transposePfS_iiPfS_ii, @function
_Z32__device_stub__Z9transposePfS_iiPfS_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9transposePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z32__device_stub__Z9transposePfS_iiPfS_ii, .-_Z32__device_stub__Z9transposePfS_iiPfS_ii
.globl _Z9transposePfS_ii
.type _Z9transposePfS_ii, @function
_Z9transposePfS_ii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9transposePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9transposePfS_ii, .-_Z9transposePfS_ii
.globl _Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii
.type _Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii, @function
_Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19sharedMem_transposePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii, .-_Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii
.globl _Z19sharedMem_transposePfS_ii
.type _Z19sharedMem_transposePfS_ii, @function
_Z19sharedMem_transposePfS_ii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z19sharedMem_transposePfS_ii, .-_Z19sharedMem_transposePfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Time for the NAIVE kernel: "
.LC3:
.string " ms"
.LC4:
.string "Time for the SHARED kernel: "
.LC5:
.string "Time for the CPU code "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $0, %edx
movl $36000000, %esi
call cudaHostAlloc@PLT
movl $36000000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $36000000, %esi
call cudaMalloc@PLT
movl $0, %eax
.L31:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $9000000, %rax
jne .L31
movl $0, %r8d
movl $1, %ecx
movl $36000000, %edx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpyAsync@PLT
leaq 40(%rsp), %rdi
movl $36000000, %esi
call cudaMalloc@PLT
movl $36000000, %edx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
movl $100, 80(%rsp)
movl $100, 84(%rsp)
movl $1, 88(%rsp)
movl $30, 92(%rsp)
movl $30, 96(%rsp)
movl $1, 100(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L32:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 16(%rsp), %rdi
movq 72(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L33:
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
call clock@PLT
movq %rax, %rbp
movl $3000, %ecx
movl $3000, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call _Z12cpuTransposePfS_ii
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC0(%rip), %xmm0
divsd .LC1(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC4(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC5(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movl $3000, %ecx
movl $3000, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z32__device_stub__Z9transposePfS_iiPfS_ii
jmp .L32
.L38:
movl $3000, %ecx
movl $3000, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z43__device_stub__Z19sharedMem_transposePfS_iiPfS_ii
jmp .L33
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z19sharedMem_transposePfS_ii"
.LC7:
.string "_Z9transposePfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z19sharedMem_transposePfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "transpose.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z12cpuTransposePfS_ii # -- Begin function _Z12cpuTransposePfS_ii
.p2align 4, 0x90
.type _Z12cpuTransposePfS_ii,@function
_Z12cpuTransposePfS_ii: # @_Z12cpuTransposePfS_ii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB0_7
# %bb.1: # %.preheader.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movslq %ecx, %rax
movl %edx, %edx
movl %eax, %r8d
shlq $2, %rax
xorl %r9d, %r9d
xorl %r10d, %r10d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r10
addl %ecx, %r9d
addq $4, %rsi
cmpq %rdx, %r10
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %ecx, %ecx
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r9d, %r11d
leaq (%rdi,%r11,4), %r11
movq %rsi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r11,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rbx)
incq %r14
addq %rax, %rbx
cmpq %r14, %r8
jne .LBB0_4
jmp .LBB0_5
.LBB0_6:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB0_7: # %._crit_edge17
retq
.Lfunc_end0:
.size _Z12cpuTransposePfS_ii, .Lfunc_end0-_Z12cpuTransposePfS_ii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__transposePfS_ii # -- Begin function _Z24__device_stub__transposePfS_ii
.p2align 4, 0x90
.type _Z24__device_stub__transposePfS_ii,@function
_Z24__device_stub__transposePfS_ii: # @_Z24__device_stub__transposePfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9transposePfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__transposePfS_ii, .Lfunc_end1-_Z24__device_stub__transposePfS_ii
.cfi_endproc
# -- End function
.globl _Z34__device_stub__sharedMem_transposePfS_ii # -- Begin function _Z34__device_stub__sharedMem_transposePfS_ii
.p2align 4, 0x90
.type _Z34__device_stub__sharedMem_transposePfS_ii,@function
_Z34__device_stub__sharedMem_transposePfS_ii: # @_Z34__device_stub__sharedMem_transposePfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19sharedMem_transposePfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z34__device_stub__sharedMem_transposePfS_ii, .Lfunc_end2-_Z34__device_stub__sharedMem_transposePfS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x408f400000000000 # double 1000
.LCPI3_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $184, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 48(%rsp), %rdi
xorl %ebx, %ebx
movl $36000000, %esi # imm = 0x2255100
xorl %edx, %edx
callq hipHostMalloc
leaq 24(%rsp), %rdi
movl $36000000, %esi # imm = 0x2255100
callq hipMalloc
movq 48(%rsp), %rax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
movss %xmm0, (%rax,%rbx,4)
incq %rbx
cmpq $9000000, %rbx # imm = 0x895440
jne .LBB3_1
# %bb.2:
movabsq $429496729700, %rbx # imm = 0x6400000064
movabsq $128849018910, %r14 # imm = 0x1E0000001E
movq 24(%rsp), %rdi
movq 48(%rsp), %rsi
movl $36000000, %edx # imm = 0x2255100
movl $1, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
leaq 16(%rsp), %rdi
movl $36000000, %esi # imm = 0x2255100
callq hipMalloc
movq 16(%rsp), %rdi
movl $36000000, %edx # imm = 0x2255100
xorl %esi, %esi
callq hipMemset
leaq 168(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 160(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
movq 168(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movl $3000, 12(%rsp) # imm = 0xBB8
movl $3000, 8(%rsp) # imm = 0xBB8
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9transposePfS_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 168(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 124(%rsp), %rdi
callq hipEventElapsedTime
movq 160(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movl $3000, 12(%rsp) # imm = 0xBB8
movl $3000, 8(%rsp) # imm = 0xBB8
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z19sharedMem_transposePfS_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6: # %_Z12cpuTransposePfS_ii.exit
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 160(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
callq clock
movq %rax, %rbx
callq clock
movq %rax, %r14
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 124(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB3_19
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB3_9
# %bb.8:
movzbl 67(%r12), %eax
jmp .LBB3_10
.LBB3_9:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB3_19
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i40
subq %rbx, %r14
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
divsd .LCPI3_1(%rip), %xmm0
movsd %xmm0, 176(%rsp) # 8-byte Spill
cmpb $0, 56(%r12)
je .LBB3_13
# %bb.12:
movzbl 67(%r12), %eax
jmp .LBB3_14
.LBB3_13:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit43
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i45
cmpb $0, 56(%r14)
je .LBB3_17
# %bb.16:
movzbl 67(%r14), %eax
jmp .LBB3_18
.LBB3_17:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit48
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 48(%rsp), %rdi
callq hipHostFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_19:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19sharedMem_transposePfS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9transposePfS_ii,@object # @_Z9transposePfS_ii
.section .rodata,"a",@progbits
.globl _Z9transposePfS_ii
.p2align 3, 0x0
_Z9transposePfS_ii:
.quad _Z24__device_stub__transposePfS_ii
.size _Z9transposePfS_ii, 8
.type _Z19sharedMem_transposePfS_ii,@object # @_Z19sharedMem_transposePfS_ii
.globl _Z19sharedMem_transposePfS_ii
.p2align 3, 0x0
_Z19sharedMem_transposePfS_ii:
.quad _Z34__device_stub__sharedMem_transposePfS_ii
.size _Z19sharedMem_transposePfS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time for the NAIVE kernel: "
.size .L.str, 28
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ms"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time for the SHARED kernel: "
.size .L.str.2, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time for the CPU code "
.size .L.str.3, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9transposePfS_ii"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19sharedMem_transposePfS_ii"
.size .L__unnamed_2, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__transposePfS_ii
.addrsig_sym _Z34__device_stub__sharedMem_transposePfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9transposePfS_ii
.addrsig_sym _Z19sharedMem_transposePfS_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <algorithm>
#include <cstdlib>
int main(void)
{
std::cout << "Start Thrust\n";
// generate 32M random numbers serially
thrust::host_vector<int> h_vec(32 << 20);
std::generate(h_vec.begin(), h_vec.end(), rand);
// transfer data to the device
thrust::device_vector<int> d_vec = h_vec;
// sort data on the device (846M keys per second on GeForce GTX 480)
thrust::sort(d_vec.begin(), d_vec.end());
// transfer data back to host
thrust::copy(d_vec.begin(), d_vec.end(), h_vec.begin());
std::cout << "Finish Thrust\n";
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <algorithm>
#include <cstdlib>
int main(void)
{
std::cout << "Start Thrust\n";
// generate 32M random numbers serially
thrust::host_vector<int> h_vec(32 << 20);
std::generate(h_vec.begin(), h_vec.end(), rand);
// transfer data to the device
thrust::device_vector<int> d_vec = h_vec;
// sort data on the device (846M keys per second on GeForce GTX 480)
thrust::sort(d_vec.begin(), d_vec.end());
// transfer data back to host
thrust::copy(d_vec.begin(), d_vec.end(), h_vec.begin());
std::cout << "Finish Thrust\n";
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright (c) 2018 Preferred Networks, Inc. All rights reserved.
*/
#include <cuda_fp16.h>
namespace chainer_trt {
namespace plugin {
template <typename T>
__global__ void eltw_sum_kernel(const T* src_gpu, int n_in,
const T* vals_gpu, int n_values,
T* dst_gpu) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_in <= idx)
return;
const int batch = blockIdx.y;
const int idx_in_vals = (n_values == 1 ? 0 : idx);
dst_gpu[batch * n_in + idx] =
vals_gpu[idx_in_vals] + src_gpu[batch * n_in + idx];
}
template <typename T>
void apply_eltw_sum(const T* src_gpu, int n_in, const T* vals_gpu,
int n_values, T* dst_gpu, int batch_size,
cudaStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_in / block_size);
dim3 grid(grid_size, batch_size);
eltw_sum_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, n_in, vals_gpu, n_values, dst_gpu);
}
template <typename T>
__global__ void eltw_sub_kernel(const T* src_gpu, int n_in,
const T* vals_gpu, int n_values,
T* dst_gpu) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_in <= idx)
return;
const int batch = blockIdx.y;
const int idx_in_vals = (n_values == 1 ? 0 : idx);
dst_gpu[batch * n_in + idx] =
vals_gpu[idx_in_vals] - src_gpu[batch * n_in + idx];
}
template <typename T>
void apply_eltw_sub(const T* src_gpu, int n_in, const T* vals_gpu,
int n_values, T* dst_gpu, int batch_size,
cudaStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_in / block_size);
dim3 grid(grid_size, batch_size);
eltw_sub_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, n_in, vals_gpu, n_values, dst_gpu);
}
template <typename T>
__global__ void eltw_mul_kernel(const T* src_gpu, int n_in,
const T* vals_gpu, int n_values,
T* dst_gpu) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_in <= idx)
return;
const int batch = blockIdx.y;
const int idx_in_vals = (n_values == 1 ? 0 : idx);
dst_gpu[batch * n_in + idx] =
vals_gpu[idx_in_vals] * src_gpu[batch * n_in + idx];
}
template <typename T>
void apply_eltw_mul(const T* src_gpu, int n_in, const T* vals_gpu,
int n_values, T* dst_gpu, int batch_size,
cudaStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_in / block_size);
dim3 grid(grid_size, batch_size);
eltw_mul_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, n_in, vals_gpu, n_values, dst_gpu);
}
template <typename T>
__global__ void eltw_div_kernel(const T* src_gpu, int n_in,
const T* vals_gpu, int n_values,
T* dst_gpu) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_in <= idx)
return;
const int batch = blockIdx.y;
const int idx_in_vals = (n_values == 1 ? 0 : idx);
dst_gpu[batch * n_in + idx] =
vals_gpu[idx_in_vals] / src_gpu[batch * n_in + idx];
}
template <typename T>
void apply_eltw_div(const T* src_gpu, int n_in, const T* vals_gpu,
int n_values, T* dst_gpu, int batch_size,
cudaStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_in / block_size);
dim3 grid(grid_size, batch_size);
eltw_div_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, n_in, vals_gpu, n_values, dst_gpu);
}
// explicit instantiation (without this, link error will happen)
template void apply_eltw_sum(const float*, int, const float*, int, float*,
int, cudaStream_t);
template void apply_eltw_sub(const float*, int, const float*, int, float*,
int, cudaStream_t);
template void apply_eltw_mul(const float*, int, const float*, int, float*,
int, cudaStream_t);
template void apply_eltw_div(const float*, int, const float*, int, float*,
int, cudaStream_t);
template void apply_eltw_sum(const __half*, int, const __half*, int,
__half*, int, cudaStream_t);
template void apply_eltw_sub(const __half*, int, const __half*, int,
__half*, int, cudaStream_t);
template void apply_eltw_mul(const __half*, int, const __half*, int,
__half*, int, cudaStream_t);
template void apply_eltw_div(const __half*, int, const __half*, int,
__half*, int, cudaStream_t);
}
} | .file "tmpxft_00094be1_00000000-6_constant_eltw.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL72__device_stub__ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf, @function
_ZL72__device_stub__ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf:
.LFB2437:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2437:
.size _ZL72__device_stub__ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf, .-_ZL72__device_stub__ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf
.section .text._ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_,comdat
.weak _ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_
.type _ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_, @function
_ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_:
.LFB2508:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL72__device_stub__ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2508:
.size _ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_, .-_ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_
.text
.type _ZL72__device_stub__ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf, @function
_ZL72__device_stub__ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf:
.LFB2439:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2439:
.size _ZL72__device_stub__ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf, .-_ZL72__device_stub__ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf
.section .text._ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_,comdat
.weak _ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_
.type _ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_, @function
_ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_:
.LFB2510:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL72__device_stub__ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2510:
.size _ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_, .-_ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_
.text
.type _ZL72__device_stub__ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf, @function
_ZL72__device_stub__ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf:
.LFB2441:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2441:
.size _ZL72__device_stub__ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf, .-_ZL72__device_stub__ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf
.section .text._ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_,comdat
.weak _ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_
.type _ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_, @function
_ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_:
.LFB2511:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL72__device_stub__ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2511:
.size _ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_, .-_ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_
.text
.type _ZL72__device_stub__ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf, @function
_ZL72__device_stub__ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf:
.LFB2443:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2443:
.size _ZL72__device_stub__ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf, .-_ZL72__device_stub__ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf
.section .text._ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_,comdat
.weak _ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_
.type _ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_, @function
_ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_:
.LFB2512:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL72__device_stub__ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2512:
.size _ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_, .-_ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_
.text
.type _ZL78__device_stub__ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_, @function
_ZL78__device_stub__ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_:
.LFB2445:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2445:
.size _ZL78__device_stub__ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_, .-_ZL78__device_stub__ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_
.section .text._ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_,comdat
.weak _ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_
.type _ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_, @function
_ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_:
.LFB2513:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL78__device_stub__ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2513:
.size _ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_, .-_ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_
.text
.type _ZL78__device_stub__ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_, @function
_ZL78__device_stub__ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_:
.LFB2447:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2447:
.size _ZL78__device_stub__ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_, .-_ZL78__device_stub__ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_
.section .text._ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_,comdat
.weak _ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_
.type _ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_, @function
_ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_:
.LFB2514:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL78__device_stub__ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2514:
.size _ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_, .-_ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_
.text
.type _ZL78__device_stub__ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_, @function
_ZL78__device_stub__ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_:
.LFB2449:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2449:
.size _ZL78__device_stub__ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_, .-_ZL78__device_stub__ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_
.section .text._ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_,comdat
.weak _ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_
.type _ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_, @function
_ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_:
.LFB2515:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL78__device_stub__ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2515:
.size _ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_, .-_ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_
.text
.type _ZL78__device_stub__ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_, @function
_ZL78__device_stub__ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_:
.LFB2451:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L61
.L57:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L62
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L57
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2451:
.size _ZL78__device_stub__ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_, .-_ZL78__device_stub__ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_
.section .text._ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_,comdat
.weak _ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_
.type _ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_, @function
_ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_:
.LFB2516:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL78__device_stub__ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2516:
.size _ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_, .-_ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2415:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2415:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN11chainer_trt6plugin14apply_eltw_sumIfEEvPKT_iS4_iPS2_iP11CUstream_st,"axG",@progbits,_ZN11chainer_trt6plugin14apply_eltw_sumIfEEvPKT_iS4_iPS2_iP11CUstream_st,comdat
.weak _ZN11chainer_trt6plugin14apply_eltw_sumIfEEvPKT_iS4_iPS2_iP11CUstream_st
.type _ZN11chainer_trt6plugin14apply_eltw_sumIfEEvPKT_iS4_iPS2_iP11CUstream_st, @function
_ZN11chainer_trt6plugin14apply_eltw_sumIfEEvPKT_iS4_iPS2_iP11CUstream_st:
.LFB2500:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movl %ecx, %r13d
movq %r8, %r14
pxor %xmm0, %xmm0
cvtsi2sdl %esi, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L68
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L68:
cvttsd2sil %xmm3, %eax
movl %eax, 8(%rsp)
movl %r9d, 12(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movq 80(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L71
.L67:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
movq %r14, %r8
movl %r13d, %ecx
movq %r12, %rdx
movl %ebx, %esi
movq %rbp, %rdi
call _ZL72__device_stub__ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf
jmp .L67
.cfi_endproc
.LFE2500:
.size _ZN11chainer_trt6plugin14apply_eltw_sumIfEEvPKT_iS4_iPS2_iP11CUstream_st, .-_ZN11chainer_trt6plugin14apply_eltw_sumIfEEvPKT_iS4_iPS2_iP11CUstream_st
.section .text._ZN11chainer_trt6plugin14apply_eltw_subIfEEvPKT_iS4_iPS2_iP11CUstream_st,"axG",@progbits,_ZN11chainer_trt6plugin14apply_eltw_subIfEEvPKT_iS4_iPS2_iP11CUstream_st,comdat
.weak _ZN11chainer_trt6plugin14apply_eltw_subIfEEvPKT_iS4_iPS2_iP11CUstream_st
.type _ZN11chainer_trt6plugin14apply_eltw_subIfEEvPKT_iS4_iPS2_iP11CUstream_st, @function
_ZN11chainer_trt6plugin14apply_eltw_subIfEEvPKT_iS4_iPS2_iP11CUstream_st:
.LFB2501:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movl %ecx, %r13d
movq %r8, %r14
pxor %xmm0, %xmm0
cvtsi2sdl %esi, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L73
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L73:
cvttsd2sil %xmm3, %eax
movl %eax, 8(%rsp)
movl %r9d, 12(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movq 80(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L76
.L72:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L76:
.cfi_restore_state
movq %r14, %r8
movl %r13d, %ecx
movq %r12, %rdx
movl %ebx, %esi
movq %rbp, %rdi
call _ZL72__device_stub__ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf
jmp .L72
.cfi_endproc
.LFE2501:
.size _ZN11chainer_trt6plugin14apply_eltw_subIfEEvPKT_iS4_iPS2_iP11CUstream_st, .-_ZN11chainer_trt6plugin14apply_eltw_subIfEEvPKT_iS4_iPS2_iP11CUstream_st
.section .text._ZN11chainer_trt6plugin14apply_eltw_mulIfEEvPKT_iS4_iPS2_iP11CUstream_st,"axG",@progbits,_ZN11chainer_trt6plugin14apply_eltw_mulIfEEvPKT_iS4_iPS2_iP11CUstream_st,comdat
.weak _ZN11chainer_trt6plugin14apply_eltw_mulIfEEvPKT_iS4_iPS2_iP11CUstream_st
.type _ZN11chainer_trt6plugin14apply_eltw_mulIfEEvPKT_iS4_iPS2_iP11CUstream_st, @function
_ZN11chainer_trt6plugin14apply_eltw_mulIfEEvPKT_iS4_iPS2_iP11CUstream_st:
.LFB2502:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movl %ecx, %r13d
movq %r8, %r14
pxor %xmm0, %xmm0
cvtsi2sdl %esi, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L78
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L78:
cvttsd2sil %xmm3, %eax
movl %eax, 8(%rsp)
movl %r9d, 12(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movq 80(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L81
.L77:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L81:
.cfi_restore_state
movq %r14, %r8
movl %r13d, %ecx
movq %r12, %rdx
movl %ebx, %esi
movq %rbp, %rdi
call _ZL72__device_stub__ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf
jmp .L77
.cfi_endproc
.LFE2502:
.size _ZN11chainer_trt6plugin14apply_eltw_mulIfEEvPKT_iS4_iPS2_iP11CUstream_st, .-_ZN11chainer_trt6plugin14apply_eltw_mulIfEEvPKT_iS4_iPS2_iP11CUstream_st
.section .text._ZN11chainer_trt6plugin14apply_eltw_divIfEEvPKT_iS4_iPS2_iP11CUstream_st,"axG",@progbits,_ZN11chainer_trt6plugin14apply_eltw_divIfEEvPKT_iS4_iPS2_iP11CUstream_st,comdat
.weak _ZN11chainer_trt6plugin14apply_eltw_divIfEEvPKT_iS4_iPS2_iP11CUstream_st
.type _ZN11chainer_trt6plugin14apply_eltw_divIfEEvPKT_iS4_iPS2_iP11CUstream_st, @function
_ZN11chainer_trt6plugin14apply_eltw_divIfEEvPKT_iS4_iPS2_iP11CUstream_st:
.LFB2503:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movl %ecx, %r13d
movq %r8, %r14
pxor %xmm0, %xmm0
cvtsi2sdl %esi, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L83
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L83:
cvttsd2sil %xmm3, %eax
movl %eax, 8(%rsp)
movl %r9d, 12(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movq 80(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L86
.L82:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
movq %r14, %r8
movl %r13d, %ecx
movq %r12, %rdx
movl %ebx, %esi
movq %rbp, %rdi
call _ZL72__device_stub__ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_PKfiS0_iPf
jmp .L82
.cfi_endproc
.LFE2503:
.size _ZN11chainer_trt6plugin14apply_eltw_divIfEEvPKT_iS4_iPS2_iP11CUstream_st, .-_ZN11chainer_trt6plugin14apply_eltw_divIfEEvPKT_iS4_iPS2_iP11CUstream_st
.section .text._ZN11chainer_trt6plugin14apply_eltw_sumI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st,"axG",@progbits,_ZN11chainer_trt6plugin14apply_eltw_sumI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st,comdat
.weak _ZN11chainer_trt6plugin14apply_eltw_sumI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st
.type _ZN11chainer_trt6plugin14apply_eltw_sumI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st, @function
_ZN11chainer_trt6plugin14apply_eltw_sumI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st:
.LFB2504:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movl %ecx, %r13d
movq %r8, %r14
pxor %xmm0, %xmm0
cvtsi2sdl %esi, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L88
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L88:
cvttsd2sil %xmm3, %eax
movl %eax, 8(%rsp)
movl %r9d, 12(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movq 80(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L91
.L87:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L91:
.cfi_restore_state
movq %r14, %r8
movl %r13d, %ecx
movq %r12, %rdx
movl %ebx, %esi
movq %rbp, %rdi
call _ZL78__device_stub__ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_
jmp .L87
.cfi_endproc
.LFE2504:
.size _ZN11chainer_trt6plugin14apply_eltw_sumI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st, .-_ZN11chainer_trt6plugin14apply_eltw_sumI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st
.section .text._ZN11chainer_trt6plugin14apply_eltw_subI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st,"axG",@progbits,_ZN11chainer_trt6plugin14apply_eltw_subI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st,comdat
.weak _ZN11chainer_trt6plugin14apply_eltw_subI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st
.type _ZN11chainer_trt6plugin14apply_eltw_subI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st, @function
_ZN11chainer_trt6plugin14apply_eltw_subI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st:
.LFB2505:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movl %ecx, %r13d
movq %r8, %r14
pxor %xmm0, %xmm0
cvtsi2sdl %esi, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L93
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L93:
cvttsd2sil %xmm3, %eax
movl %eax, 8(%rsp)
movl %r9d, 12(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movq 80(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L96
.L92:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L96:
.cfi_restore_state
movq %r14, %r8
movl %r13d, %ecx
movq %r12, %rdx
movl %ebx, %esi
movq %rbp, %rdi
call _ZL78__device_stub__ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_
jmp .L92
.cfi_endproc
.LFE2505:
.size _ZN11chainer_trt6plugin14apply_eltw_subI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st, .-_ZN11chainer_trt6plugin14apply_eltw_subI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st
.section .text._ZN11chainer_trt6plugin14apply_eltw_mulI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st,"axG",@progbits,_ZN11chainer_trt6plugin14apply_eltw_mulI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st,comdat
.weak _ZN11chainer_trt6plugin14apply_eltw_mulI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st
.type _ZN11chainer_trt6plugin14apply_eltw_mulI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st, @function
_ZN11chainer_trt6plugin14apply_eltw_mulI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st:
.LFB2506:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movl %ecx, %r13d
movq %r8, %r14
pxor %xmm0, %xmm0
cvtsi2sdl %esi, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L98
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L98:
cvttsd2sil %xmm3, %eax
movl %eax, 8(%rsp)
movl %r9d, 12(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movq 80(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L101
.L97:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L101:
.cfi_restore_state
movq %r14, %r8
movl %r13d, %ecx
movq %r12, %rdx
movl %ebx, %esi
movq %rbp, %rdi
call _ZL78__device_stub__ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_
jmp .L97
.cfi_endproc
.LFE2506:
.size _ZN11chainer_trt6plugin14apply_eltw_mulI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st, .-_ZN11chainer_trt6plugin14apply_eltw_mulI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st
.section .text._ZN11chainer_trt6plugin14apply_eltw_divI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st,"axG",@progbits,_ZN11chainer_trt6plugin14apply_eltw_divI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st,comdat
.weak _ZN11chainer_trt6plugin14apply_eltw_divI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st
.type _ZN11chainer_trt6plugin14apply_eltw_divI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st, @function
_ZN11chainer_trt6plugin14apply_eltw_divI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st:
.LFB2507:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movl %ecx, %r13d
movq %r8, %r14
pxor %xmm0, %xmm0
cvtsi2sdl %esi, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L103
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L103:
cvttsd2sil %xmm3, %eax
movl %eax, 8(%rsp)
movl %r9d, 12(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movq 80(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L106
.L102:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L106:
.cfi_restore_state
movq %r14, %r8
movl %r13d, %ecx
movq %r12, %rdx
movl %ebx, %esi
movq %rbp, %rdi
call _ZL78__device_stub__ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_PK6__halfiS1_iPS_
jmp .L102
.cfi_endproc
.LFE2507:
.size _ZN11chainer_trt6plugin14apply_eltw_divI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st, .-_ZN11chainer_trt6plugin14apply_eltw_divI6__halfEEvPKT_iS5_iPS3_iP11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_"
.align 8
.LC6:
.string "_ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_"
.align 8
.LC7:
.string "_ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_"
.align 8
.LC8:
.string "_ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_"
.align 8
.LC9:
.string "_ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_"
.align 8
.LC10:
.string "_ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_"
.align 8
.LC11:
.string "_ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_"
.align 8
.LC12:
.string "_ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2454:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2454:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1062207488
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright (c) 2018 Preferred Networks, Inc. All rights reserved.
*/
#include <cuda_fp16.h>
namespace chainer_trt {
namespace plugin {
template <typename T>
__global__ void eltw_sum_kernel(const T* src_gpu, int n_in,
const T* vals_gpu, int n_values,
T* dst_gpu) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_in <= idx)
return;
const int batch = blockIdx.y;
const int idx_in_vals = (n_values == 1 ? 0 : idx);
dst_gpu[batch * n_in + idx] =
vals_gpu[idx_in_vals] + src_gpu[batch * n_in + idx];
}
template <typename T>
void apply_eltw_sum(const T* src_gpu, int n_in, const T* vals_gpu,
int n_values, T* dst_gpu, int batch_size,
cudaStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_in / block_size);
dim3 grid(grid_size, batch_size);
eltw_sum_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, n_in, vals_gpu, n_values, dst_gpu);
}
template <typename T>
__global__ void eltw_sub_kernel(const T* src_gpu, int n_in,
const T* vals_gpu, int n_values,
T* dst_gpu) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_in <= idx)
return;
const int batch = blockIdx.y;
const int idx_in_vals = (n_values == 1 ? 0 : idx);
dst_gpu[batch * n_in + idx] =
vals_gpu[idx_in_vals] - src_gpu[batch * n_in + idx];
}
template <typename T>
void apply_eltw_sub(const T* src_gpu, int n_in, const T* vals_gpu,
int n_values, T* dst_gpu, int batch_size,
cudaStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_in / block_size);
dim3 grid(grid_size, batch_size);
eltw_sub_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, n_in, vals_gpu, n_values, dst_gpu);
}
template <typename T>
__global__ void eltw_mul_kernel(const T* src_gpu, int n_in,
const T* vals_gpu, int n_values,
T* dst_gpu) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_in <= idx)
return;
const int batch = blockIdx.y;
const int idx_in_vals = (n_values == 1 ? 0 : idx);
dst_gpu[batch * n_in + idx] =
vals_gpu[idx_in_vals] * src_gpu[batch * n_in + idx];
}
template <typename T>
void apply_eltw_mul(const T* src_gpu, int n_in, const T* vals_gpu,
int n_values, T* dst_gpu, int batch_size,
cudaStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_in / block_size);
dim3 grid(grid_size, batch_size);
eltw_mul_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, n_in, vals_gpu, n_values, dst_gpu);
}
template <typename T>
__global__ void eltw_div_kernel(const T* src_gpu, int n_in,
const T* vals_gpu, int n_values,
T* dst_gpu) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_in <= idx)
return;
const int batch = blockIdx.y;
const int idx_in_vals = (n_values == 1 ? 0 : idx);
dst_gpu[batch * n_in + idx] =
vals_gpu[idx_in_vals] / src_gpu[batch * n_in + idx];
}
template <typename T>
void apply_eltw_div(const T* src_gpu, int n_in, const T* vals_gpu,
int n_values, T* dst_gpu, int batch_size,
cudaStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_in / block_size);
dim3 grid(grid_size, batch_size);
eltw_div_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, n_in, vals_gpu, n_values, dst_gpu);
}
// explicit instantiation (without this, link error will happen)
template void apply_eltw_sum(const float*, int, const float*, int, float*,
int, cudaStream_t);
template void apply_eltw_sub(const float*, int, const float*, int, float*,
int, cudaStream_t);
template void apply_eltw_mul(const float*, int, const float*, int, float*,
int, cudaStream_t);
template void apply_eltw_div(const float*, int, const float*, int, float*,
int, cudaStream_t);
template void apply_eltw_sum(const __half*, int, const __half*, int,
__half*, int, cudaStream_t);
template void apply_eltw_sub(const __half*, int, const __half*, int,
__half*, int, cudaStream_t);
template void apply_eltw_mul(const __half*, int, const __half*, int,
__half*, int, cudaStream_t);
template void apply_eltw_div(const __half*, int, const __half*, int,
__half*, int, cudaStream_t);
}
} | /*
* Copyright (c) 2018 Preferred Networks, Inc. All rights reserved.
*/
#include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>
namespace chainer_trt {
namespace plugin {
template <typename T>
__global__ void eltw_sum_kernel(const T* src_gpu, int n_in,
const T* vals_gpu, int n_values,
T* dst_gpu) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_in <= idx)
return;
const int batch = blockIdx.y;
const int idx_in_vals = (n_values == 1 ? 0 : idx);
dst_gpu[batch * n_in + idx] =
vals_gpu[idx_in_vals] + src_gpu[batch * n_in + idx];
}
template <typename T>
void apply_eltw_sum(const T* src_gpu, int n_in, const T* vals_gpu,
int n_values, T* dst_gpu, int batch_size,
hipStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_in / block_size);
dim3 grid(grid_size, batch_size);
eltw_sum_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, n_in, vals_gpu, n_values, dst_gpu);
}
template <typename T>
__global__ void eltw_sub_kernel(const T* src_gpu, int n_in,
const T* vals_gpu, int n_values,
T* dst_gpu) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_in <= idx)
return;
const int batch = blockIdx.y;
const int idx_in_vals = (n_values == 1 ? 0 : idx);
dst_gpu[batch * n_in + idx] =
vals_gpu[idx_in_vals] - src_gpu[batch * n_in + idx];
}
template <typename T>
void apply_eltw_sub(const T* src_gpu, int n_in, const T* vals_gpu,
int n_values, T* dst_gpu, int batch_size,
hipStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_in / block_size);
dim3 grid(grid_size, batch_size);
eltw_sub_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, n_in, vals_gpu, n_values, dst_gpu);
}
template <typename T>
__global__ void eltw_mul_kernel(const T* src_gpu, int n_in,
const T* vals_gpu, int n_values,
T* dst_gpu) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_in <= idx)
return;
const int batch = blockIdx.y;
const int idx_in_vals = (n_values == 1 ? 0 : idx);
dst_gpu[batch * n_in + idx] =
vals_gpu[idx_in_vals] * src_gpu[batch * n_in + idx];
}
template <typename T>
void apply_eltw_mul(const T* src_gpu, int n_in, const T* vals_gpu,
int n_values, T* dst_gpu, int batch_size,
hipStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_in / block_size);
dim3 grid(grid_size, batch_size);
eltw_mul_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, n_in, vals_gpu, n_values, dst_gpu);
}
template <typename T>
__global__ void eltw_div_kernel(const T* src_gpu, int n_in,
const T* vals_gpu, int n_values,
T* dst_gpu) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_in <= idx)
return;
const int batch = blockIdx.y;
const int idx_in_vals = (n_values == 1 ? 0 : idx);
dst_gpu[batch * n_in + idx] =
vals_gpu[idx_in_vals] / src_gpu[batch * n_in + idx];
}
template <typename T>
void apply_eltw_div(const T* src_gpu, int n_in, const T* vals_gpu,
int n_values, T* dst_gpu, int batch_size,
hipStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_in / block_size);
dim3 grid(grid_size, batch_size);
eltw_div_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, n_in, vals_gpu, n_values, dst_gpu);
}
// explicit instantiation (without this, link error will happen)
template void apply_eltw_sum(const float*, int, const float*, int, float*,
int, hipStream_t);
template void apply_eltw_sub(const float*, int, const float*, int, float*,
int, hipStream_t);
template void apply_eltw_mul(const float*, int, const float*, int, float*,
int, hipStream_t);
template void apply_eltw_div(const float*, int, const float*, int, float*,
int, hipStream_t);
template void apply_eltw_sum(const __half*, int, const __half*, int,
__half*, int, hipStream_t);
template void apply_eltw_sub(const __half*, int, const __half*, int,
__half*, int, hipStream_t);
template void apply_eltw_mul(const __half*, int, const __half*, int,
__half*, int, hipStream_t);
template void apply_eltw_div(const __half*, int, const __half*, int,
__half*, int, hipStream_t);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Copyright (c) 2018 Preferred Networks, Inc. All rights reserved.
*/
#include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>
namespace chainer_trt {
namespace plugin {
template <typename T>
__global__ void eltw_sum_kernel(const T* src_gpu, int n_in,
const T* vals_gpu, int n_values,
T* dst_gpu) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_in <= idx)
return;
const int batch = blockIdx.y;
const int idx_in_vals = (n_values == 1 ? 0 : idx);
dst_gpu[batch * n_in + idx] =
vals_gpu[idx_in_vals] + src_gpu[batch * n_in + idx];
}
template <typename T>
void apply_eltw_sum(const T* src_gpu, int n_in, const T* vals_gpu,
int n_values, T* dst_gpu, int batch_size,
hipStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_in / block_size);
dim3 grid(grid_size, batch_size);
eltw_sum_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, n_in, vals_gpu, n_values, dst_gpu);
}
template <typename T>
__global__ void eltw_sub_kernel(const T* src_gpu, int n_in,
const T* vals_gpu, int n_values,
T* dst_gpu) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_in <= idx)
return;
const int batch = blockIdx.y;
const int idx_in_vals = (n_values == 1 ? 0 : idx);
dst_gpu[batch * n_in + idx] =
vals_gpu[idx_in_vals] - src_gpu[batch * n_in + idx];
}
template <typename T>
void apply_eltw_sub(const T* src_gpu, int n_in, const T* vals_gpu,
int n_values, T* dst_gpu, int batch_size,
hipStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_in / block_size);
dim3 grid(grid_size, batch_size);
eltw_sub_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, n_in, vals_gpu, n_values, dst_gpu);
}
template <typename T>
__global__ void eltw_mul_kernel(const T* src_gpu, int n_in,
const T* vals_gpu, int n_values,
T* dst_gpu) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_in <= idx)
return;
const int batch = blockIdx.y;
const int idx_in_vals = (n_values == 1 ? 0 : idx);
dst_gpu[batch * n_in + idx] =
vals_gpu[idx_in_vals] * src_gpu[batch * n_in + idx];
}
template <typename T>
void apply_eltw_mul(const T* src_gpu, int n_in, const T* vals_gpu,
int n_values, T* dst_gpu, int batch_size,
hipStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_in / block_size);
dim3 grid(grid_size, batch_size);
eltw_mul_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, n_in, vals_gpu, n_values, dst_gpu);
}
template <typename T>
__global__ void eltw_div_kernel(const T* src_gpu, int n_in,
const T* vals_gpu, int n_values,
T* dst_gpu) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(n_in <= idx)
return;
const int batch = blockIdx.y;
const int idx_in_vals = (n_values == 1 ? 0 : idx);
dst_gpu[batch * n_in + idx] =
vals_gpu[idx_in_vals] / src_gpu[batch * n_in + idx];
}
template <typename T>
void apply_eltw_div(const T* src_gpu, int n_in, const T* vals_gpu,
int n_values, T* dst_gpu, int batch_size,
hipStream_t stream) {
const int block_size = 1024;
const int grid_size = (int)std::ceil(1.0 * n_in / block_size);
dim3 grid(grid_size, batch_size);
eltw_div_kernel<T><<<grid, block_size, 0, stream>>>(
src_gpu, n_in, vals_gpu, n_values, dst_gpu);
}
// explicit instantiation (without this, link error will happen)
template void apply_eltw_sum(const float*, int, const float*, int, float*,
int, hipStream_t);
template void apply_eltw_sub(const float*, int, const float*, int, float*,
int, hipStream_t);
template void apply_eltw_mul(const float*, int, const float*, int, float*,
int, hipStream_t);
template void apply_eltw_div(const float*, int, const float*, int, float*,
int, hipStream_t);
template void apply_eltw_sum(const __half*, int, const __half*, int,
__half*, int, hipStream_t);
template void apply_eltw_sub(const __half*, int, const __half*, int,
__half*, int, hipStream_t);
template void apply_eltw_mul(const __half*, int, const __half*, int,
__half*, int, hipStream_t);
template void apply_eltw_div(const __half*, int, const __half*, int,
__half*, int, hipStream_t);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_,comdat
.protected _ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_
.globl _ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_
.p2align 8
.type _ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_,@function
_ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s6, s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x20
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s6, 1
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v0, 0, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v0, v4
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_,comdat
.Lfunc_end0:
.size _ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_, .Lfunc_end0-_ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_,comdat
.protected _ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_
.globl _ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_
.p2align 8
.type _ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_,@function
_ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b32 s6, s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x20
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s6, 1
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v0, 0, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v4, v0, v4
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_,comdat
.Lfunc_end1:
.size _ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_, .Lfunc_end1-_ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_,comdat
.protected _ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_
.globl _ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_
.p2align 8
.type _ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_,@function
_ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB2_2
s_clause 0x1
s_load_b32 s6, s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x20
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s6, 1
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v0, 0, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, v0, v4
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_,comdat
.Lfunc_end2:
.size _ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_, .Lfunc_end2-_ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_,comdat
.protected _ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_
.globl _ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_
.p2align 8
.type _ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_,@function
_ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB3_2
s_clause 0x1
s_load_b32 s6, s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x20
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s6, 1
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v0, 0, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v1, null, v4, v4, v0
v_div_scale_f32 v7, vcc_lo, v0, v4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v1, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v1, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v1, -v1, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v1, v1, v5, v6
v_div_fixup_f32 v4, v1, v4, v0
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_,comdat
.Lfunc_end3:
.size _ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_, .Lfunc_end3-_ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_,comdat
.protected _ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_
.globl _ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_
.p2align 8
.type _ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_,@function
_ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB4_2
s_clause 0x1
s_load_b32 s6, s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x20
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s6, 1
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v0, 0, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_u16 v4, v[4:5], off
global_load_u16 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f16_e32 v4, v0, v4
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b16 v[0:1], v4, off
.LBB4_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_,comdat
.Lfunc_end4:
.size _ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_, .Lfunc_end4-_ZN11chainer_trt6plugin15eltw_sum_kernelI6__halfEEvPKT_iS5_iPS3_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_,comdat
.protected _ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_
.globl _ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_
.p2align 8
.type _ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_,@function
_ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB5_2
s_clause 0x1
s_load_b32 s6, s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x20
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s6, 1
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v0, 0, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_u16 v4, v[4:5], off
global_load_u16 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_sub_f16_e32 v4, v0, v4
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b16 v[0:1], v4, off
.LBB5_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_,comdat
.Lfunc_end5:
.size _ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_, .Lfunc_end5-_ZN11chainer_trt6plugin15eltw_sub_kernelI6__halfEEvPKT_iS5_iPS3_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_,comdat
.protected _ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_
.globl _ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_
.p2align 8
.type _ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_,@function
_ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB6_2
s_clause 0x1
s_load_b32 s6, s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x20
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s6, 1
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v0, 0, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_u16 v4, v[4:5], off
global_load_u16 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f16_e32 v4, v0, v4
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b16 v[0:1], v4, off
.LBB6_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_,comdat
.Lfunc_end6:
.size _ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_, .Lfunc_end6-_ZN11chainer_trt6plugin15eltw_mul_kernelI6__halfEEvPKT_iS5_iPS3_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_,comdat
.protected _ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_
.globl _ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_
.p2align 8
.type _ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_,@function
_ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB7_2
s_clause 0x1
s_load_b32 s6, s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x20
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s6, 1
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v0, 0, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
global_load_u16 v4, v[4:5], off
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_u16 v0, v[0:1], off
s_waitcnt vmcnt(1)
v_cvt_f32_f16_e32 v1, v4
v_rcp_f32_e32 v1, v1
s_waitcnt vmcnt(0)
s_waitcnt_depctr 0xfff
v_fma_mixlo_f16 v1, v0, v1, 0 op_sel_hi:[1,0,0]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f16 v4, v1, v4, v0
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b16 v[0:1], v4, off
.LBB7_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_,"axG",@progbits,_ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_,comdat
.Lfunc_end7:
.size _ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_, .Lfunc_end7-_ZN11chainer_trt6plugin15eltw_div_kernelI6__halfEEvPKT_iS5_iPS3_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN11chainer_trt6plugin15eltw_sum_kernelIfEEvPKT_iS4_iPS2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN11chainer_trt6plugin15eltw_sub_kernelIfEEvPKT_iS4_iPS2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN11chainer_trt6plugin15eltw_mul_kernelIfEEvPKT_iS4_iPS2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN11chainer_trt6plugin15eltw_div_kernelIfEEvPKT_iS4_iPS2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
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amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define BLOCK_SIZE 16
#define MAX(i,j) ( (i)<(j) ? (j):(i) )
#define MIN(i,j) ( (i)<(j) ? (i):(j) )
#define SubArrayA(x,y) subArrayA[(x)*BLOCK_SIZE+(y)]
#define SubArrayB(x,y) subArrayB[(x)*BLOCK_SIZE+(y)]
#define InputArrayA(x,y) inputArrayA[(x)*BLOCK_SIZE+(y)]
#define InputArrayB(x,y) inputArrayB[(x)*BLOCK_SIZE+(y)]
#define ImageOut(x,y) imageOut[(x)*imageSize+(y)]
#define ZiArray(x,y) ziArray[(x)*imageSize+(y)]
__device__ float gaussianDistance(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth);
__device__ float weightingFunct(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth,float sigma,float Zi);
__device__ float normFactor(float *inputArrayA,float *inputArrayB,int halfPatchWidth,float sigma);
__device__ float nonLocalMeans(float *inputArrayA,float *inputArrayB,float *imageOut,int xi,int yi,int halfPatchWidth,int imageSize,float sigma,float Zi);
__global__ void mainGpuFunction(float const * const inputArray,float *imageOut,float *ziArray,int halfPatchWidth,int imageSize,float sigma,int flag)
{
//ÐÜñå ôéò óõíôåôáãìÝíåò ôïõ áíôßóôïé÷ïõ pixel ðïõ êÜíïõìå áðïèïñõâïðïßçóç
int xi = blockIdx.x * blockDim.x + threadIdx.x;
int yi = blockIdx.y * blockDim.y + threadIdx.y;
//ÐñÝðåé íá åßìáé ìÝóá óôá üñéá ôçò åéêüíáò
if((xi<imageSize)&&(yi<imageSize)){
__shared__ float subArrayA[BLOCK_SIZE*BLOCK_SIZE];
__shared__ float subArrayB[BLOCK_SIZE*BLOCK_SIZE];
//Áí áíïßêù óå åðßðåäï Z=0
//if(blockIdx.z==0) ImageOut(xi,yi)=0;
//===========================
//Õðïëüãéæïõìå óýìöùíá ìå ôçí ìåôáâëçôÞ blockIdx.z ðïéü block èá
//öïñôþóïõìå ãéá õðïëïãéóìü ìáæß ìå ôï êýñéï block.
//Éó÷ýåé ç ó÷Ýóç blockIdx.z=neighblockX*blockDim.x+neighblockY
int neighblockX;
int neighblockY;
for(int i=0;i<blockDim.x;i++){
for(int j=0;j<blockDim.y;j++){
if(blockIdx.z==(i*blockDim.x+j))
{
neighblockX=i;
neighblockY=j;
i=blockDim.x;//Ãéá íá âãïýìå áðï ôï loop
break;
}
}
}
//===========================
int xj = neighblockX*blockDim.x + threadIdx.x;
int yj = neighblockY* blockDim.y + threadIdx.y;
//Áí èÝëù íá õðïëïãßóù ôçí ôéìÞ Zi
if(flag==1)
{
//Öïñôþíïõìå ôï êýñéï block
//ÊÜèå thread öïñôþíåé ìïíÜ÷á åíá óôïé÷åßï óôïí ðßíáêá
SubArrayA(threadIdx.x,threadIdx.y)=inputArray[xi*imageSize+yi];
__syncthreads();
//Öïñôþíïõìå óôïí ðßíáêá  Ýíá áðï ôá block åéêüíáò áíÜëïãá ìå ôïí
//áñéèìü ôïõ blockIdx.z óôïí ïðïßï âñéóêüìáóôå
SubArrayB(threadIdx.x,threadIdx.y)=inputArray[xj*imageSize+yj];
__syncthreads();
float Zi=normFactor(subArrayA,subArrayB,halfPatchWidth,sigma);
atomicAdd(&ZiArray(xi,yi),Zi);
//ÐåñéìÝíïõìå íá õðïëïãéóôïýí êáé íá ðñïóôåèïýí ïëá ôá Æi
__syncthreads();
}
else //Áí èÝëù íá õðïëïãßóù ôá áèñïßóìáôá w(i,j)*f(j)
{
//Öïñôþíïõìå ôï êýñéï block
//ÊÜèå thread öïñôþíåé ìïíá÷á åíá óôïé÷åßï óôïí ðßíáêá
SubArrayA(threadIdx.x,threadIdx.y)=inputArray[xi*imageSize+yi];
__syncthreads();
//Öïñôþíïõìå óôïí ðßíáêá  Ýíá áðï ôá block åéêüíáò áíÜëïãá ìå ôïí
//áñéèìü ôïõ blockIdx.z óôïí ïðïßï âñéóêüìáóôå
SubArrayB(threadIdx.x,threadIdx.y)=inputArray[xj*imageSize+yj];
__syncthreads();
float SumWeight=nonLocalMeans(subArrayA,subArrayB,imageOut,xi,yi,halfPatchWidth,imageSize,sigma,ZiArray(xi,yi));
atomicAdd(&ImageOut(xi,yi),SumWeight);
__syncthreads();
}
}
}
__device__ float nonLocalMeans(float *inputArrayA,float *inputArrayB,float *imageOut,int xi,int yi,int halfPatchWidth,int imageSize,float sigma,float Zi){
float ww=0;
for(int xj=0;xj<BLOCK_SIZE;xj++)
{
for(int yj=0;yj<BLOCK_SIZE;yj++)
{
ww+=weightingFunct(inputArrayA,inputArrayB,xj,yj,halfPatchWidth,sigma,Zi)*InputArrayB(xj,yj); //w(i,j)*f(j)
}
}
return(ww);
}
//Ç ìåôáâëçôÞ w(i,j)=w([xi,yi] [xj,yj])
__device__ float weightingFunct(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth,float sigma,float Zi){
float distance=gaussianDistance(inputArrayA,inputArrayB,xj,yj,halfPatchWidth);
return ( ( expf(-(distance/(sigma*sigma))) )/Zi);
}
//Ç ìåôáâëçôç Z(i)=Z(xi,yi)
__device__ float normFactor(float *inputArrayA,float *inputArrayB,int halfPatchWidth,float sigma){
float square_sigma=sigma*sigma;
float z=0;
for(int i=0;i<BLOCK_SIZE;i++)
{
for(int j=0;j<BLOCK_SIZE;j++)
{
float distance=gaussianDistance(inputArrayA,inputArrayB,i,j,halfPatchWidth);
z+=expf(-(distance/square_sigma) );
}
}
return (z);
}
//Õðïëïãéóìüò ôçò äéáöïñÜò |f(Ni)-f(Nj)|
//×ñçóéìïðïéïýìå Gaussian Euclidean Distance
__device__ float gaussianDistance(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth){
int xi=threadIdx.x;
int yi=threadIdx.y;
//Ï äåßêôçò i áíáöÝñåôáé óôï pixel ôïõ ïðïßï õðïëïãßæïõìå ôçí íÝá ôéìÞ
//åíþ ï äåßêôçò j óôá õðüëïéðá pixel ìå ôá ïðïßá ãßíåôáé óýãêñéóç
int ai;
int bi;
int aj;
int bj;
int SumWeight=0; //¶èñïéóìá âáñþí
float distance=0;//ÓõíïëéêÞ äéáöïñÜ ãåéôïíéÜò pixel
float diff=0; //ÄéáöïñÜ ìåôáîý 2 pixel ãåéôüíùí
for(int i=-halfPatchWidth;i<=halfPatchWidth;i++)
{
for(int j=-halfPatchWidth;j<=halfPatchWidth;j++)
{
ai=xi+i;
bi=yi+j;
aj=xj+i;
bj=yj+j;
if((aj<0)||(aj>=BLOCK_SIZE)) aj=xj-i;
if((bj<0)||(bj>=BLOCK_SIZE)) bj=yj-j;
if((ai<0)||(ai>=BLOCK_SIZE)) ai=xi-i;
if((bi<0)||(bi>=BLOCK_SIZE)) bi=yi-j;
if (ai!=xi || bi!=yi)//ÊÜíå óýãêñéóç ãéá üëç ôçí ãåéôïíéÜ åêôþò ôïõ êåíôñéêïý
{
int weight=1/(MAX(ai-xi,xi-ai)+MAX(bi-yi,yi-bi));
SumWeight+=weight;
diff=InputArrayA(ai,bi)-InputArrayB(aj,bj);
distance+=diff*diff*weight;
}
}
}
return (distance/SumWeight);
} | .file "tmpxft_0014d41c_00000000-6_gpu_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13nonLocalMeansPfS_S_iiiiff
.type _Z13nonLocalMeansPfS_S_iiiiff, @function
_Z13nonLocalMeansPfS_S_iiiiff:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z13nonLocalMeansPfS_S_iiiiff, .-_Z13nonLocalMeansPfS_S_iiiiff
.globl _Z14weightingFunctPfS_iiiff
.type _Z14weightingFunctPfS_iiiff, @function
_Z14weightingFunctPfS_iiiff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z14weightingFunctPfS_iiiff, .-_Z14weightingFunctPfS_iiiff
.globl _Z10normFactorPfS_if
.type _Z10normFactorPfS_if, @function
_Z10normFactorPfS_if:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10normFactorPfS_if, .-_Z10normFactorPfS_if
.globl _Z16gaussianDistancePfS_iii
.type _Z16gaussianDistancePfS_iii, @function
_Z16gaussianDistancePfS_iii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z16gaussianDistancePfS_iii, .-_Z16gaussianDistancePfS_iii
.globl _Z45__device_stub__Z15mainGpuFunctionPKfPfS1_iifiPKfPfS1_iifi
.type _Z45__device_stub__Z15mainGpuFunctionPKfPfS1_iifiPKfPfS1_iifi, @function
_Z45__device_stub__Z15mainGpuFunctionPKfPfS1_iifiPKfPfS1_iifi:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15mainGpuFunctionPKfPfS1_iifi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z45__device_stub__Z15mainGpuFunctionPKfPfS1_iifiPKfPfS1_iifi, .-_Z45__device_stub__Z15mainGpuFunctionPKfPfS1_iifiPKfPfS1_iifi
.globl _Z15mainGpuFunctionPKfPfS1_iifi
.type _Z15mainGpuFunctionPKfPfS1_iifi, @function
_Z15mainGpuFunctionPKfPfS1_iifi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z15mainGpuFunctionPKfPfS1_iifiPKfPfS1_iifi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z15mainGpuFunctionPKfPfS1_iifi, .-_Z15mainGpuFunctionPKfPfS1_iifi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15mainGpuFunctionPKfPfS1_iifi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15mainGpuFunctionPKfPfS1_iifi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define BLOCK_SIZE 16
#define MAX(i,j) ( (i)<(j) ? (j):(i) )
#define MIN(i,j) ( (i)<(j) ? (i):(j) )
#define SubArrayA(x,y) subArrayA[(x)*BLOCK_SIZE+(y)]
#define SubArrayB(x,y) subArrayB[(x)*BLOCK_SIZE+(y)]
#define InputArrayA(x,y) inputArrayA[(x)*BLOCK_SIZE+(y)]
#define InputArrayB(x,y) inputArrayB[(x)*BLOCK_SIZE+(y)]
#define ImageOut(x,y) imageOut[(x)*imageSize+(y)]
#define ZiArray(x,y) ziArray[(x)*imageSize+(y)]
__device__ float gaussianDistance(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth);
__device__ float weightingFunct(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth,float sigma,float Zi);
__device__ float normFactor(float *inputArrayA,float *inputArrayB,int halfPatchWidth,float sigma);
__device__ float nonLocalMeans(float *inputArrayA,float *inputArrayB,float *imageOut,int xi,int yi,int halfPatchWidth,int imageSize,float sigma,float Zi);
__global__ void mainGpuFunction(float const * const inputArray,float *imageOut,float *ziArray,int halfPatchWidth,int imageSize,float sigma,int flag)
{
//ÐÜñå ôéò óõíôåôáãìÝíåò ôïõ áíôßóôïé÷ïõ pixel ðïõ êÜíïõìå áðïèïñõâïðïßçóç
int xi = blockIdx.x * blockDim.x + threadIdx.x;
int yi = blockIdx.y * blockDim.y + threadIdx.y;
//ÐñÝðåé íá åßìáé ìÝóá óôá üñéá ôçò åéêüíáò
if((xi<imageSize)&&(yi<imageSize)){
__shared__ float subArrayA[BLOCK_SIZE*BLOCK_SIZE];
__shared__ float subArrayB[BLOCK_SIZE*BLOCK_SIZE];
//Áí áíïßêù óå åðßðåäï Z=0
//if(blockIdx.z==0) ImageOut(xi,yi)=0;
//===========================
//Õðïëüãéæïõìå óýìöùíá ìå ôçí ìåôáâëçôÞ blockIdx.z ðïéü block èá
//öïñôþóïõìå ãéá õðïëïãéóìü ìáæß ìå ôï êýñéï block.
//Éó÷ýåé ç ó÷Ýóç blockIdx.z=neighblockX*blockDim.x+neighblockY
int neighblockX;
int neighblockY;
for(int i=0;i<blockDim.x;i++){
for(int j=0;j<blockDim.y;j++){
if(blockIdx.z==(i*blockDim.x+j))
{
neighblockX=i;
neighblockY=j;
i=blockDim.x;//Ãéá íá âãïýìå áðï ôï loop
break;
}
}
}
//===========================
int xj = neighblockX*blockDim.x + threadIdx.x;
int yj = neighblockY* blockDim.y + threadIdx.y;
//Áí èÝëù íá õðïëïãßóù ôçí ôéìÞ Zi
if(flag==1)
{
//Öïñôþíïõìå ôï êýñéï block
//ÊÜèå thread öïñôþíåé ìïíÜ÷á åíá óôïé÷åßï óôïí ðßíáêá
SubArrayA(threadIdx.x,threadIdx.y)=inputArray[xi*imageSize+yi];
__syncthreads();
//Öïñôþíïõìå óôïí ðßíáêá  Ýíá áðï ôá block åéêüíáò áíÜëïãá ìå ôïí
//áñéèìü ôïõ blockIdx.z óôïí ïðïßï âñéóêüìáóôå
SubArrayB(threadIdx.x,threadIdx.y)=inputArray[xj*imageSize+yj];
__syncthreads();
float Zi=normFactor(subArrayA,subArrayB,halfPatchWidth,sigma);
atomicAdd(&ZiArray(xi,yi),Zi);
//ÐåñéìÝíïõìå íá õðïëïãéóôïýí êáé íá ðñïóôåèïýí ïëá ôá Æi
__syncthreads();
}
else //Áí èÝëù íá õðïëïãßóù ôá áèñïßóìáôá w(i,j)*f(j)
{
//Öïñôþíïõìå ôï êýñéï block
//ÊÜèå thread öïñôþíåé ìïíá÷á åíá óôïé÷åßï óôïí ðßíáêá
SubArrayA(threadIdx.x,threadIdx.y)=inputArray[xi*imageSize+yi];
__syncthreads();
//Öïñôþíïõìå óôïí ðßíáêá  Ýíá áðï ôá block åéêüíáò áíÜëïãá ìå ôïí
//áñéèìü ôïõ blockIdx.z óôïí ïðïßï âñéóêüìáóôå
SubArrayB(threadIdx.x,threadIdx.y)=inputArray[xj*imageSize+yj];
__syncthreads();
float SumWeight=nonLocalMeans(subArrayA,subArrayB,imageOut,xi,yi,halfPatchWidth,imageSize,sigma,ZiArray(xi,yi));
atomicAdd(&ImageOut(xi,yi),SumWeight);
__syncthreads();
}
}
}
__device__ float nonLocalMeans(float *inputArrayA,float *inputArrayB,float *imageOut,int xi,int yi,int halfPatchWidth,int imageSize,float sigma,float Zi){
float ww=0;
for(int xj=0;xj<BLOCK_SIZE;xj++)
{
for(int yj=0;yj<BLOCK_SIZE;yj++)
{
ww+=weightingFunct(inputArrayA,inputArrayB,xj,yj,halfPatchWidth,sigma,Zi)*InputArrayB(xj,yj); //w(i,j)*f(j)
}
}
return(ww);
}
//Ç ìåôáâëçôÞ w(i,j)=w([xi,yi] [xj,yj])
__device__ float weightingFunct(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth,float sigma,float Zi){
float distance=gaussianDistance(inputArrayA,inputArrayB,xj,yj,halfPatchWidth);
return ( ( expf(-(distance/(sigma*sigma))) )/Zi);
}
//Ç ìåôáâëçôç Z(i)=Z(xi,yi)
__device__ float normFactor(float *inputArrayA,float *inputArrayB,int halfPatchWidth,float sigma){
float square_sigma=sigma*sigma;
float z=0;
for(int i=0;i<BLOCK_SIZE;i++)
{
for(int j=0;j<BLOCK_SIZE;j++)
{
float distance=gaussianDistance(inputArrayA,inputArrayB,i,j,halfPatchWidth);
z+=expf(-(distance/square_sigma) );
}
}
return (z);
}
//Õðïëïãéóìüò ôçò äéáöïñÜò |f(Ni)-f(Nj)|
//×ñçóéìïðïéïýìå Gaussian Euclidean Distance
__device__ float gaussianDistance(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth){
int xi=threadIdx.x;
int yi=threadIdx.y;
//Ï äåßêôçò i áíáöÝñåôáé óôï pixel ôïõ ïðïßï õðïëïãßæïõìå ôçí íÝá ôéìÞ
//åíþ ï äåßêôçò j óôá õðüëïéðá pixel ìå ôá ïðïßá ãßíåôáé óýãêñéóç
int ai;
int bi;
int aj;
int bj;
int SumWeight=0; //¶èñïéóìá âáñþí
float distance=0;//ÓõíïëéêÞ äéáöïñÜ ãåéôïíéÜò pixel
float diff=0; //ÄéáöïñÜ ìåôáîý 2 pixel ãåéôüíùí
for(int i=-halfPatchWidth;i<=halfPatchWidth;i++)
{
for(int j=-halfPatchWidth;j<=halfPatchWidth;j++)
{
ai=xi+i;
bi=yi+j;
aj=xj+i;
bj=yj+j;
if((aj<0)||(aj>=BLOCK_SIZE)) aj=xj-i;
if((bj<0)||(bj>=BLOCK_SIZE)) bj=yj-j;
if((ai<0)||(ai>=BLOCK_SIZE)) ai=xi-i;
if((bi<0)||(bi>=BLOCK_SIZE)) bi=yi-j;
if (ai!=xi || bi!=yi)//ÊÜíå óýãêñéóç ãéá üëç ôçí ãåéôïíéÜ åêôþò ôïõ êåíôñéêïý
{
int weight=1/(MAX(ai-xi,xi-ai)+MAX(bi-yi,yi-bi));
SumWeight+=weight;
diff=InputArrayA(ai,bi)-InputArrayB(aj,bj);
distance+=diff*diff*weight;
}
}
}
return (distance/SumWeight);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define BLOCK_SIZE 16
#define MAX(i,j) ( (i)<(j) ? (j):(i) )
#define MIN(i,j) ( (i)<(j) ? (i):(j) )
#define SubArrayA(x,y) subArrayA[(x)*BLOCK_SIZE+(y)]
#define SubArrayB(x,y) subArrayB[(x)*BLOCK_SIZE+(y)]
#define InputArrayA(x,y) inputArrayA[(x)*BLOCK_SIZE+(y)]
#define InputArrayB(x,y) inputArrayB[(x)*BLOCK_SIZE+(y)]
#define ImageOut(x,y) imageOut[(x)*imageSize+(y)]
#define ZiArray(x,y) ziArray[(x)*imageSize+(y)]
__device__ float gaussianDistance(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth);
__device__ float weightingFunct(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth,float sigma,float Zi);
__device__ float normFactor(float *inputArrayA,float *inputArrayB,int halfPatchWidth,float sigma);
__device__ float nonLocalMeans(float *inputArrayA,float *inputArrayB,float *imageOut,int xi,int yi,int halfPatchWidth,int imageSize,float sigma,float Zi);
__global__ void mainGpuFunction(float const * const inputArray,float *imageOut,float *ziArray,int halfPatchWidth,int imageSize,float sigma,int flag)
{
//ÐÜñå ôéò óõíôåôáãìÝíåò ôïõ áíôßóôïé÷ïõ pixel ðïõ êÜíïõìå áðïèïñõâïðïßçóç
int xi = blockIdx.x * blockDim.x + threadIdx.x;
int yi = blockIdx.y * blockDim.y + threadIdx.y;
//ÐñÝðåé íá åßìáé ìÝóá óôá üñéá ôçò åéêüíáò
if((xi<imageSize)&&(yi<imageSize)){
__shared__ float subArrayA[BLOCK_SIZE*BLOCK_SIZE];
__shared__ float subArrayB[BLOCK_SIZE*BLOCK_SIZE];
//Áí áíïßêù óå åðßðåäï Z=0
//if(blockIdx.z==0) ImageOut(xi,yi)=0;
//===========================
//Õðïëüãéæïõìå óýìöùíá ìå ôçí ìåôáâëçôÞ blockIdx.z ðïéü block èá
//öïñôþóïõìå ãéá õðïëïãéóìü ìáæß ìå ôï êýñéï block.
//Éó÷ýåé ç ó÷Ýóç blockIdx.z=neighblockX*blockDim.x+neighblockY
int neighblockX;
int neighblockY;
for(int i=0;i<blockDim.x;i++){
for(int j=0;j<blockDim.y;j++){
if(blockIdx.z==(i*blockDim.x+j))
{
neighblockX=i;
neighblockY=j;
i=blockDim.x;//Ãéá íá âãïýìå áðï ôï loop
break;
}
}
}
//===========================
int xj = neighblockX*blockDim.x + threadIdx.x;
int yj = neighblockY* blockDim.y + threadIdx.y;
//Áí èÝëù íá õðïëïãßóù ôçí ôéìÞ Zi
if(flag==1)
{
//Öïñôþíïõìå ôï êýñéï block
//ÊÜèå thread öïñôþíåé ìïíÜ÷á åíá óôïé÷åßï óôïí ðßíáêá
SubArrayA(threadIdx.x,threadIdx.y)=inputArray[xi*imageSize+yi];
__syncthreads();
//Öïñôþíïõìå óôïí ðßíáêá  Ýíá áðï ôá block åéêüíáò áíÜëïãá ìå ôïí
//áñéèìü ôïõ blockIdx.z óôïí ïðïßï âñéóêüìáóôå
SubArrayB(threadIdx.x,threadIdx.y)=inputArray[xj*imageSize+yj];
__syncthreads();
float Zi=normFactor(subArrayA,subArrayB,halfPatchWidth,sigma);
atomicAdd(&ZiArray(xi,yi),Zi);
//ÐåñéìÝíïõìå íá õðïëïãéóôïýí êáé íá ðñïóôåèïýí ïëá ôá Æi
__syncthreads();
}
else //Áí èÝëù íá õðïëïãßóù ôá áèñïßóìáôá w(i,j)*f(j)
{
//Öïñôþíïõìå ôï êýñéï block
//ÊÜèå thread öïñôþíåé ìïíá÷á åíá óôïé÷åßï óôïí ðßíáêá
SubArrayA(threadIdx.x,threadIdx.y)=inputArray[xi*imageSize+yi];
__syncthreads();
//Öïñôþíïõìå óôïí ðßíáêá  Ýíá áðï ôá block åéêüíáò áíÜëïãá ìå ôïí
//áñéèìü ôïõ blockIdx.z óôïí ïðïßï âñéóêüìáóôå
SubArrayB(threadIdx.x,threadIdx.y)=inputArray[xj*imageSize+yj];
__syncthreads();
float SumWeight=nonLocalMeans(subArrayA,subArrayB,imageOut,xi,yi,halfPatchWidth,imageSize,sigma,ZiArray(xi,yi));
atomicAdd(&ImageOut(xi,yi),SumWeight);
__syncthreads();
}
}
}
__device__ float nonLocalMeans(float *inputArrayA,float *inputArrayB,float *imageOut,int xi,int yi,int halfPatchWidth,int imageSize,float sigma,float Zi){
float ww=0;
for(int xj=0;xj<BLOCK_SIZE;xj++)
{
for(int yj=0;yj<BLOCK_SIZE;yj++)
{
ww+=weightingFunct(inputArrayA,inputArrayB,xj,yj,halfPatchWidth,sigma,Zi)*InputArrayB(xj,yj); //w(i,j)*f(j)
}
}
return(ww);
}
//Ç ìåôáâëçôÞ w(i,j)=w([xi,yi] [xj,yj])
__device__ float weightingFunct(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth,float sigma,float Zi){
float distance=gaussianDistance(inputArrayA,inputArrayB,xj,yj,halfPatchWidth);
return ( ( expf(-(distance/(sigma*sigma))) )/Zi);
}
//Ç ìåôáâëçôç Z(i)=Z(xi,yi)
__device__ float normFactor(float *inputArrayA,float *inputArrayB,int halfPatchWidth,float sigma){
float square_sigma=sigma*sigma;
float z=0;
for(int i=0;i<BLOCK_SIZE;i++)
{
for(int j=0;j<BLOCK_SIZE;j++)
{
float distance=gaussianDistance(inputArrayA,inputArrayB,i,j,halfPatchWidth);
z+=expf(-(distance/square_sigma) );
}
}
return (z);
}
//Õðïëïãéóìüò ôçò äéáöïñÜò |f(Ni)-f(Nj)|
//×ñçóéìïðïéïýìå Gaussian Euclidean Distance
__device__ float gaussianDistance(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth){
int xi=threadIdx.x;
int yi=threadIdx.y;
//Ï äåßêôçò i áíáöÝñåôáé óôï pixel ôïõ ïðïßï õðïëïãßæïõìå ôçí íÝá ôéìÞ
//åíþ ï äåßêôçò j óôá õðüëïéðá pixel ìå ôá ïðïßá ãßíåôáé óýãêñéóç
int ai;
int bi;
int aj;
int bj;
int SumWeight=0; //¶èñïéóìá âáñþí
float distance=0;//ÓõíïëéêÞ äéáöïñÜ ãåéôïíéÜò pixel
float diff=0; //ÄéáöïñÜ ìåôáîý 2 pixel ãåéôüíùí
for(int i=-halfPatchWidth;i<=halfPatchWidth;i++)
{
for(int j=-halfPatchWidth;j<=halfPatchWidth;j++)
{
ai=xi+i;
bi=yi+j;
aj=xj+i;
bj=yj+j;
if((aj<0)||(aj>=BLOCK_SIZE)) aj=xj-i;
if((bj<0)||(bj>=BLOCK_SIZE)) bj=yj-j;
if((ai<0)||(ai>=BLOCK_SIZE)) ai=xi-i;
if((bi<0)||(bi>=BLOCK_SIZE)) bi=yi-j;
if (ai!=xi || bi!=yi)//ÊÜíå óýãêñéóç ãéá üëç ôçí ãåéôïíéÜ åêôþò ôïõ êåíôñéêïý
{
int weight=1/(MAX(ai-xi,xi-ai)+MAX(bi-yi,yi-bi));
SumWeight+=weight;
diff=InputArrayA(ai,bi)-InputArrayB(aj,bj);
distance+=diff*diff*weight;
}
}
}
return (distance/SumWeight);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define BLOCK_SIZE 16
#define MAX(i,j) ( (i)<(j) ? (j):(i) )
#define MIN(i,j) ( (i)<(j) ? (i):(j) )
#define SubArrayA(x,y) subArrayA[(x)*BLOCK_SIZE+(y)]
#define SubArrayB(x,y) subArrayB[(x)*BLOCK_SIZE+(y)]
#define InputArrayA(x,y) inputArrayA[(x)*BLOCK_SIZE+(y)]
#define InputArrayB(x,y) inputArrayB[(x)*BLOCK_SIZE+(y)]
#define ImageOut(x,y) imageOut[(x)*imageSize+(y)]
#define ZiArray(x,y) ziArray[(x)*imageSize+(y)]
__device__ float gaussianDistance(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth);
__device__ float weightingFunct(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth,float sigma,float Zi);
__device__ float normFactor(float *inputArrayA,float *inputArrayB,int halfPatchWidth,float sigma);
__device__ float nonLocalMeans(float *inputArrayA,float *inputArrayB,float *imageOut,int xi,int yi,int halfPatchWidth,int imageSize,float sigma,float Zi);
__global__ void mainGpuFunction(float const * const inputArray,float *imageOut,float *ziArray,int halfPatchWidth,int imageSize,float sigma,int flag)
{
//ÐÜñå ôéò óõíôåôáãìÝíåò ôïõ áíôßóôïé÷ïõ pixel ðïõ êÜíïõìå áðïèïñõâïðïßçóç
int xi = blockIdx.x * blockDim.x + threadIdx.x;
int yi = blockIdx.y * blockDim.y + threadIdx.y;
//ÐñÝðåé íá åßìáé ìÝóá óôá üñéá ôçò åéêüíáò
if((xi<imageSize)&&(yi<imageSize)){
__shared__ float subArrayA[BLOCK_SIZE*BLOCK_SIZE];
__shared__ float subArrayB[BLOCK_SIZE*BLOCK_SIZE];
//Áí áíïßêù óå åðßðåäï Z=0
//if(blockIdx.z==0) ImageOut(xi,yi)=0;
//===========================
//Õðïëüãéæïõìå óýìöùíá ìå ôçí ìåôáâëçôÞ blockIdx.z ðïéü block èá
//öïñôþóïõìå ãéá õðïëïãéóìü ìáæß ìå ôï êýñéï block.
//Éó÷ýåé ç ó÷Ýóç blockIdx.z=neighblockX*blockDim.x+neighblockY
int neighblockX;
int neighblockY;
for(int i=0;i<blockDim.x;i++){
for(int j=0;j<blockDim.y;j++){
if(blockIdx.z==(i*blockDim.x+j))
{
neighblockX=i;
neighblockY=j;
i=blockDim.x;//Ãéá íá âãïýìå áðï ôï loop
break;
}
}
}
//===========================
int xj = neighblockX*blockDim.x + threadIdx.x;
int yj = neighblockY* blockDim.y + threadIdx.y;
//Áí èÝëù íá õðïëïãßóù ôçí ôéìÞ Zi
if(flag==1)
{
//Öïñôþíïõìå ôï êýñéï block
//ÊÜèå thread öïñôþíåé ìïíÜ÷á åíá óôïé÷åßï óôïí ðßíáêá
SubArrayA(threadIdx.x,threadIdx.y)=inputArray[xi*imageSize+yi];
__syncthreads();
//Öïñôþíïõìå óôïí ðßíáêá  Ýíá áðï ôá block åéêüíáò áíÜëïãá ìå ôïí
//áñéèìü ôïõ blockIdx.z óôïí ïðïßï âñéóêüìáóôå
SubArrayB(threadIdx.x,threadIdx.y)=inputArray[xj*imageSize+yj];
__syncthreads();
float Zi=normFactor(subArrayA,subArrayB,halfPatchWidth,sigma);
atomicAdd(&ZiArray(xi,yi),Zi);
//ÐåñéìÝíïõìå íá õðïëïãéóôïýí êáé íá ðñïóôåèïýí ïëá ôá Æi
__syncthreads();
}
else //Áí èÝëù íá õðïëïãßóù ôá áèñïßóìáôá w(i,j)*f(j)
{
//Öïñôþíïõìå ôï êýñéï block
//ÊÜèå thread öïñôþíåé ìïíá÷á åíá óôïé÷åßï óôïí ðßíáêá
SubArrayA(threadIdx.x,threadIdx.y)=inputArray[xi*imageSize+yi];
__syncthreads();
//Öïñôþíïõìå óôïí ðßíáêá  Ýíá áðï ôá block åéêüíáò áíÜëïãá ìå ôïí
//áñéèìü ôïõ blockIdx.z óôïí ïðïßï âñéóêüìáóôå
SubArrayB(threadIdx.x,threadIdx.y)=inputArray[xj*imageSize+yj];
__syncthreads();
float SumWeight=nonLocalMeans(subArrayA,subArrayB,imageOut,xi,yi,halfPatchWidth,imageSize,sigma,ZiArray(xi,yi));
atomicAdd(&ImageOut(xi,yi),SumWeight);
__syncthreads();
}
}
}
__device__ float nonLocalMeans(float *inputArrayA,float *inputArrayB,float *imageOut,int xi,int yi,int halfPatchWidth,int imageSize,float sigma,float Zi){
float ww=0;
for(int xj=0;xj<BLOCK_SIZE;xj++)
{
for(int yj=0;yj<BLOCK_SIZE;yj++)
{
ww+=weightingFunct(inputArrayA,inputArrayB,xj,yj,halfPatchWidth,sigma,Zi)*InputArrayB(xj,yj); //w(i,j)*f(j)
}
}
return(ww);
}
//Ç ìåôáâëçôÞ w(i,j)=w([xi,yi] [xj,yj])
__device__ float weightingFunct(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth,float sigma,float Zi){
float distance=gaussianDistance(inputArrayA,inputArrayB,xj,yj,halfPatchWidth);
return ( ( expf(-(distance/(sigma*sigma))) )/Zi);
}
//Ç ìåôáâëçôç Z(i)=Z(xi,yi)
__device__ float normFactor(float *inputArrayA,float *inputArrayB,int halfPatchWidth,float sigma){
float square_sigma=sigma*sigma;
float z=0;
for(int i=0;i<BLOCK_SIZE;i++)
{
for(int j=0;j<BLOCK_SIZE;j++)
{
float distance=gaussianDistance(inputArrayA,inputArrayB,i,j,halfPatchWidth);
z+=expf(-(distance/square_sigma) );
}
}
return (z);
}
//Õðïëïãéóìüò ôçò äéáöïñÜò |f(Ni)-f(Nj)|
//×ñçóéìïðïéïýìå Gaussian Euclidean Distance
__device__ float gaussianDistance(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth){
int xi=threadIdx.x;
int yi=threadIdx.y;
//Ï äåßêôçò i áíáöÝñåôáé óôï pixel ôïõ ïðïßï õðïëïãßæïõìå ôçí íÝá ôéìÞ
//åíþ ï äåßêôçò j óôá õðüëïéðá pixel ìå ôá ïðïßá ãßíåôáé óýãêñéóç
int ai;
int bi;
int aj;
int bj;
int SumWeight=0; //¶èñïéóìá âáñþí
float distance=0;//ÓõíïëéêÞ äéáöïñÜ ãåéôïíéÜò pixel
float diff=0; //ÄéáöïñÜ ìåôáîý 2 pixel ãåéôüíùí
for(int i=-halfPatchWidth;i<=halfPatchWidth;i++)
{
for(int j=-halfPatchWidth;j<=halfPatchWidth;j++)
{
ai=xi+i;
bi=yi+j;
aj=xj+i;
bj=yj+j;
if((aj<0)||(aj>=BLOCK_SIZE)) aj=xj-i;
if((bj<0)||(bj>=BLOCK_SIZE)) bj=yj-j;
if((ai<0)||(ai>=BLOCK_SIZE)) ai=xi-i;
if((bi<0)||(bi>=BLOCK_SIZE)) bi=yi-j;
if (ai!=xi || bi!=yi)//ÊÜíå óýãêñéóç ãéá üëç ôçí ãåéôïíéÜ åêôþò ôïõ êåíôñéêïý
{
int weight=1/(MAX(ai-xi,xi-ai)+MAX(bi-yi,yi-bi));
SumWeight+=weight;
diff=InputArrayA(ai,bi)-InputArrayB(aj,bj);
distance+=diff*diff*weight;
}
}
}
return (distance/SumWeight);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15mainGpuFunctionPKfPfS1_iifi
.globl _Z15mainGpuFunctionPKfPfS1_iifi
.p2align 8
.type _Z15mainGpuFunctionPKfPfS1_iifi,@function
_Z15mainGpuFunctionPKfPfS1_iifi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s5, s[0:1], 0x1c
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_lshr_b32 s6, s2, 16
v_mad_u64_u32 v[4:5], null, s13, s7, v[1:2]
v_mad_u64_u32 v[5:6], null, s14, s6, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v4, v5
v_cmpx_gt_i32_e64 s5, v2
s_cbranch_execz .LBB0_46
s_cmp_eq_u32 s7, 0
s_mov_b32 s3, 0
s_cbranch_scc1 .LBB0_10
s_cmp_lg_u32 s6, 0
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_7
.p2align 6
.LBB0_3:
s_mul_i32 s8, s3, s7
s_mov_b32 s12, 0
s_sub_i32 s11, s15, s8
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_add_i32 s12, s12, 1
s_mov_b32 s9, s4
s_cmp_eq_u32 s6, s12
s_mov_b32 s8, s10
s_cselect_b32 s14, -1, 0
s_mov_b32 s13, s3
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccz .LBB0_8
.LBB0_5:
s_cmp_eq_u32 s11, s12
s_mov_b32 s14, -1
s_cbranch_scc0 .LBB0_4
s_mov_b32 s9, s3
s_mov_b32 s8, s12
s_mov_b32 s13, s7
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB0_5
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_mov_b32 s9, s4
s_mov_b32 s8, s10
s_mov_b32 s13, s3
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s13, 1
s_cmp_ge_u32 s3, s7
s_cbranch_scc1 .LBB0_11
s_mov_b32 s4, s9
s_mov_b32 s10, s8
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccz .LBB0_3
s_branch .LBB0_7
.LBB0_10:
.LBB0_11:
s_load_b64 s[10:11], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v4, s5, v[5:6]
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x18
s_load_b64 s[12:13], s[0:1], 0x20
v_lshlrev_b32_e32 v9, 4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_lshl_u32 v9, v9, v0, 2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v12, 0x400, v9
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v7, vcc_lo
v_mul_f32_e64 v10, s12, s12
v_add_nc_u32_e32 v11, s4, v0
s_cmp_lg_u32 s13, 1
global_load_b32 v8, v[4:5], off
v_mad_u64_u32 v[4:5], null, s9, s7, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v4, v4, s5
s_mul_i32 s5, s8, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v4, s5, v0, v4
s_mov_b32 s5, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
s_waitcnt vmcnt(0)
ds_store_b32 v9, v8
s_waitcnt lgkmcnt(0)
s_cbranch_scc0 .LBB0_28
s_barrier
buffer_gl0_inv
global_load_b32 v8, v[4:5], off
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_sub_i32 s5, 0, s4
s_cmp_gt_i32 s4, -1
v_mov_b32_e32 v13, 0
s_cselect_b32 s6, -1, 0
s_lshl_b32 s8, s4, 1
s_mov_b32 s7, 0
s_not_b32 s8, s8
s_waitcnt vmcnt(0)
ds_store_b32 v12, v8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v6, v[6:7], off
s_branch .LBB0_14
.LBB0_13:
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, 16
s_cbranch_scc1 .LBB0_25
.LBB0_14:
s_lshl_b32 s9, s7, 6
s_mov_b32 s10, 0
s_addk_i32 s9, 0x400
s_branch .LBB0_17
.LBB0_15:
v_cvt_f32_i32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v9, null, v8, v8, v7
v_rcp_f32_e32 v14, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v15, -v9, v14, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v14, v15, v14
v_div_scale_f32 v15, vcc_lo, v7, v8, v7
v_mul_f32_e32 v16, v15, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v17, -v9, v16, v15
v_fmac_f32_e32 v16, v17, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v9, v16, v15
v_div_fmas_f32 v9, v9, v14, v16
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v7, v9, v8, v7
.LBB0_16:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_scale_f32 v8, null, v10, v10, -v7
v_div_scale_f32 v15, vcc_lo, -v7, v10, -v7
s_lshl_b32 s11, s10, 2
v_rcp_f32_e32 v9, v8
s_add_i32 s11, s9, s11
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s10, 16
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v8, v9, 1.0
v_fmac_f32_e32 v9, v14, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v14, v15, v9
v_fma_f32 v16, -v8, v14, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v14, v16, v9
v_mov_b32_e32 v16, s11
v_fma_f32 v8, -v8, v14, v15
ds_load_b32 v16, v16
v_div_fmas_f32 v8, v8, v9, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v7, v8, v10, -v7
v_mul_f32_e32 v8, 0x3fb8aa3b, v7
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v9, v7, 0x3fb8aa3b, -v8
v_rndne_f32_e32 v14, v8
v_dual_fmac_f32 v9, 0x32a5705f, v7 :: v_dual_sub_f32 v8, v8, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v8, v8, v9
v_cvt_i32_f32_e32 v9, v14
v_exp_f32_e32 v8, v8
s_waitcnt_depctr 0xfff
v_ldexp_f32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v8, 0, v8, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v7
v_cndmask_b32_e32 v7, 0x7f800000, v8, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v8, null, v6, v6, v7
v_div_scale_f32 v15, vcc_lo, v7, v6, v7
v_rcp_f32_e32 v9, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v8, v9, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v14, v9
v_mul_f32_e32 v14, v15, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v17, -v8, v14, v15
v_fmac_f32_e32 v14, v17, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v8, v14, v15
v_div_fmas_f32 v8, v8, v9, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v7, v8, v6, v7
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v13, v16, v7
s_cbranch_scc1 .LBB0_13
.LBB0_17:
v_mov_b32_e32 v7, 0x7fc00000
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_16
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, 0
s_add_i32 s11, s4, s10
s_mov_b32 s12, s5
.LBB0_19:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v9, s12, v1
v_subrev_nc_u32_e32 v14, s12, v1
s_add_i32 s14, s12, s7
s_sub_i32 s15, s7, s12
s_cmp_gt_u32 s14, 15
v_cmp_lt_u32_e32 vcc_lo, 15, v9
s_cselect_b32 s14, s15, s14
s_mov_b32 s13, 0
s_lshl_b32 s14, s14, 6
s_mov_b32 s16, s5
v_cndmask_b32_e32 v14, v9, v14, vcc_lo
s_addk_i32 s14, 0x400
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v9, v14, v1
v_cmp_eq_u32_e32 vcc_lo, v14, v1
v_lshlrev_b32_e32 v14, 6, v14
v_sub_nc_u32_e32 v15, 0, v9
s_xor_b32 s15, vcc_lo, -1
s_delay_alu instid0(VALU_DEP_1)
v_max_i32_e32 v9, v9, v15
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_21
.p2align 6
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s17
s_add_i32 s13, s13, -1
s_add_i32 s16, s16, 1
s_cmp_eq_u32 s8, s13
s_cbranch_scc1 .LBB0_23
.LBB0_21:
v_add_nc_u32_e32 v15, s16, v0
v_add_nc_u32_e32 v16, s13, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e32 vcc_lo, 15, v15
v_cndmask_b32_e32 v15, v15, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, v15, v0
s_or_b32 s18, s15, vcc_lo
s_and_saveexec_b32 s17, s18
s_cbranch_execz .LBB0_20
v_lshl_add_u32 v16, v15, 2, v14
v_sub_nc_u32_e32 v15, v15, v0
s_add_i32 s18, s10, s16
s_add_i32 s19, s11, s13
s_cmp_gt_u32 s18, 15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_sub_nc_u32_e32 v18, 0, v15
s_cselect_b32 s18, s19, s18
s_lshl_b32 s18, s18, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v15, v15, v18
s_add_i32 s18, s14, s18
v_add_nc_u32_e32 v15, v15, v9
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v17, s18 :: v_dual_add_nc_u32 v18, 1, v15
ds_load_b32 v16, v16
ds_load_b32 v17, v17
v_cmp_gt_u32_e32 vcc_lo, 3, v18
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v16, v16, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v16, v16, v16 :: v_dual_cndmask_b32 v15, 0, v15
v_cvt_f32_i32_e32 v17, v15
s_delay_alu instid0(VALU_DEP_1)
v_dual_fmac_f32 v7, v16, v17 :: v_dual_add_nc_u32 v8, v15, v8
s_branch .LBB0_20
.LBB0_23:
s_set_inst_prefetch_distance 0x2
s_add_i32 s13, s12, 1
s_cmp_eq_u32 s12, s4
s_cbranch_scc1 .LBB0_15
s_mov_b32 s12, s13
s_branch .LBB0_19
.LBB0_25:
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_mov_b32 s0, 0
global_load_b32 v9, v[6:7], off
.LBB0_26:
s_waitcnt vmcnt(0)
v_add_f32_e32 v8, v9, v13
global_atomic_cmpswap_b32 v8, v[6:7], v[8:9], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v8, v9
v_mov_b32_e32 v9, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_26
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s5, 0
s_barrier
.LBB0_28:
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccz .LBB0_45
s_barrier
buffer_gl0_inv
global_load_b32 v5, v[4:5], off
s_sub_i32 s1, 0, s4
s_cmp_gt_i32 s4, -1
v_mov_b32_e32 v4, 0
s_cselect_b32 s5, -1, 0
s_lshl_b32 s6, s4, 1
s_mov_b32 s0, 0
s_not_b32 s6, s6
s_waitcnt vmcnt(0)
ds_store_b32 v12, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_31
.LBB0_30:
s_add_i32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 16
s_cbranch_scc1 .LBB0_42
.LBB0_31:
s_mov_b32 s7, 0
s_branch .LBB0_34
.LBB0_32:
v_cvt_f32_i32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v7, null, v6, v6, v5
v_rcp_f32_e32 v8, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v7, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v8
v_div_scale_f32 v9, vcc_lo, v5, v6, v5
v_mul_f32_e32 v12, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v13, -v7, v12, v9
v_fmac_f32_e32 v12, v13, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v7, v12, v9
v_div_fmas_f32 v7, v7, v8, v12
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v5, v7, v6, v5
.LBB0_33:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_scale_f32 v6, null, v10, v10, -v5
v_div_scale_f32 v9, vcc_lo, -v5, v10, -v5
s_add_i32 s7, s7, 1
v_rcp_f32_e32 v7, v6
s_cmp_eq_u32 s7, 16
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v7
v_mul_f32_e32 v8, v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, -v6, v8, v9
v_fmac_f32_e32 v8, v12, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v6, v8, v9
v_div_fmas_f32 v6, v6, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v5, v6, v10, -v5
v_mul_f32_e32 v6, 0x3fb8aa3b, v5
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v7, v5, 0x3fb8aa3b, -v6
v_rndne_f32_e32 v8, v6
v_dual_fmac_f32 v7, 0x32a5705f, v5 :: v_dual_sub_f32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v6, v7
v_cvt_i32_f32_e32 v7, v8
v_exp_f32_e32 v6, v6
s_waitcnt_depctr 0xfff
v_ldexp_f32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v5
v_cndmask_b32_e32 v5, 0x7f800000, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v4, v4, v5
s_cbranch_scc1 .LBB0_30
.LBB0_34:
v_mov_b32_e32 v5, 0x7fc00000
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_33
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 0
s_add_i32 s8, s4, s7
s_mov_b32 s9, s1
.LBB0_36:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v7, s9, v1
v_subrev_nc_u32_e32 v8, s9, v1
s_add_i32 s11, s9, s0
s_sub_i32 s12, s0, s9
s_cmp_gt_u32 s11, 15
v_cmp_lt_u32_e32 vcc_lo, 15, v7
s_cselect_b32 s11, s12, s11
s_mov_b32 s10, 0
s_lshl_b32 s11, s11, 6
s_mov_b32 s13, s1
v_cndmask_b32_e32 v8, v7, v8, vcc_lo
s_addk_i32 s11, 0x400
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v7, v8, v1
v_cmp_eq_u32_e32 vcc_lo, v8, v1
v_lshlrev_b32_e32 v8, 6, v8
v_sub_nc_u32_e32 v9, 0, v7
s_xor_b32 s12, vcc_lo, -1
s_delay_alu instid0(VALU_DEP_1)
v_max_i32_e32 v7, v7, v9
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_38
.p2align 6
.LBB0_37:
s_or_b32 exec_lo, exec_lo, s14
s_add_i32 s10, s10, -1
s_add_i32 s13, s13, 1
s_cmp_eq_u32 s6, s10
s_cbranch_scc1 .LBB0_40
.LBB0_38:
v_add_nc_u32_e32 v9, s13, v0
v_add_nc_u32_e32 v12, s10, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e32 vcc_lo, 15, v9
v_cndmask_b32_e32 v9, v9, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, v9, v0
s_or_b32 s15, s12, vcc_lo
s_and_saveexec_b32 s14, s15
s_cbranch_execz .LBB0_37
v_lshl_add_u32 v12, v9, 2, v8
v_sub_nc_u32_e32 v9, v9, v0
s_add_i32 s15, s7, s13
s_add_i32 s16, s8, s10
s_cmp_gt_u32 s15, 15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_sub_nc_u32_e32 v14, 0, v9
s_cselect_b32 s15, s16, s15
s_lshl_b32 s15, s15, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v9, v9, v14
s_add_i32 s15, s11, s15
v_add_nc_u32_e32 v9, v9, v7
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v13, s15 :: v_dual_add_nc_u32 v14, 1, v9
ds_load_b32 v12, v12
ds_load_b32 v13, v13
v_cmp_gt_u32_e32 vcc_lo, 3, v14
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v12, v12, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v9, 0, v9 :: v_dual_mul_f32 v12, v12, v12
v_cvt_f32_i32_e32 v13, v9
s_delay_alu instid0(VALU_DEP_1)
v_dual_fmac_f32 v5, v12, v13 :: v_dual_add_nc_u32 v6, v9, v6
s_branch .LBB0_37
.LBB0_40:
s_set_inst_prefetch_distance 0x2
s_add_i32 s10, s9, 1
s_cmp_eq_u32 s9, s4
s_cbranch_scc1 .LBB0_32
s_mov_b32 s9, s10
s_branch .LBB0_36
.LBB0_42:
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v3, v[0:1], off
.LBB0_43:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v4
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v3, v2
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_43
s_barrier
.LBB0_45:
buffer_gl0_inv
.LBB0_46:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15mainGpuFunctionPKfPfS1_iifi
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15mainGpuFunctionPKfPfS1_iifi, .Lfunc_end0-_Z15mainGpuFunctionPKfPfS1_iifi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15mainGpuFunctionPKfPfS1_iifi
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z15mainGpuFunctionPKfPfS1_iifi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define BLOCK_SIZE 16
#define MAX(i,j) ( (i)<(j) ? (j):(i) )
#define MIN(i,j) ( (i)<(j) ? (i):(j) )
#define SubArrayA(x,y) subArrayA[(x)*BLOCK_SIZE+(y)]
#define SubArrayB(x,y) subArrayB[(x)*BLOCK_SIZE+(y)]
#define InputArrayA(x,y) inputArrayA[(x)*BLOCK_SIZE+(y)]
#define InputArrayB(x,y) inputArrayB[(x)*BLOCK_SIZE+(y)]
#define ImageOut(x,y) imageOut[(x)*imageSize+(y)]
#define ZiArray(x,y) ziArray[(x)*imageSize+(y)]
__device__ float gaussianDistance(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth);
__device__ float weightingFunct(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth,float sigma,float Zi);
__device__ float normFactor(float *inputArrayA,float *inputArrayB,int halfPatchWidth,float sigma);
__device__ float nonLocalMeans(float *inputArrayA,float *inputArrayB,float *imageOut,int xi,int yi,int halfPatchWidth,int imageSize,float sigma,float Zi);
__global__ void mainGpuFunction(float const * const inputArray,float *imageOut,float *ziArray,int halfPatchWidth,int imageSize,float sigma,int flag)
{
//ÐÜñå ôéò óõíôåôáãìÝíåò ôïõ áíôßóôïé÷ïõ pixel ðïõ êÜíïõìå áðïèïñõâïðïßçóç
int xi = blockIdx.x * blockDim.x + threadIdx.x;
int yi = blockIdx.y * blockDim.y + threadIdx.y;
//ÐñÝðåé íá åßìáé ìÝóá óôá üñéá ôçò åéêüíáò
if((xi<imageSize)&&(yi<imageSize)){
__shared__ float subArrayA[BLOCK_SIZE*BLOCK_SIZE];
__shared__ float subArrayB[BLOCK_SIZE*BLOCK_SIZE];
//Áí áíïßêù óå åðßðåäï Z=0
//if(blockIdx.z==0) ImageOut(xi,yi)=0;
//===========================
//Õðïëüãéæïõìå óýìöùíá ìå ôçí ìåôáâëçôÞ blockIdx.z ðïéü block èá
//öïñôþóïõìå ãéá õðïëïãéóìü ìáæß ìå ôï êýñéï block.
//Éó÷ýåé ç ó÷Ýóç blockIdx.z=neighblockX*blockDim.x+neighblockY
int neighblockX;
int neighblockY;
for(int i=0;i<blockDim.x;i++){
for(int j=0;j<blockDim.y;j++){
if(blockIdx.z==(i*blockDim.x+j))
{
neighblockX=i;
neighblockY=j;
i=blockDim.x;//Ãéá íá âãïýìå áðï ôï loop
break;
}
}
}
//===========================
int xj = neighblockX*blockDim.x + threadIdx.x;
int yj = neighblockY* blockDim.y + threadIdx.y;
//Áí èÝëù íá õðïëïãßóù ôçí ôéìÞ Zi
if(flag==1)
{
//Öïñôþíïõìå ôï êýñéï block
//ÊÜèå thread öïñôþíåé ìïíÜ÷á åíá óôïé÷åßï óôïí ðßíáêá
SubArrayA(threadIdx.x,threadIdx.y)=inputArray[xi*imageSize+yi];
__syncthreads();
//Öïñôþíïõìå óôïí ðßíáêá  Ýíá áðï ôá block åéêüíáò áíÜëïãá ìå ôïí
//áñéèìü ôïõ blockIdx.z óôïí ïðïßï âñéóêüìáóôå
SubArrayB(threadIdx.x,threadIdx.y)=inputArray[xj*imageSize+yj];
__syncthreads();
float Zi=normFactor(subArrayA,subArrayB,halfPatchWidth,sigma);
atomicAdd(&ZiArray(xi,yi),Zi);
//ÐåñéìÝíïõìå íá õðïëïãéóôïýí êáé íá ðñïóôåèïýí ïëá ôá Æi
__syncthreads();
}
else //Áí èÝëù íá õðïëïãßóù ôá áèñïßóìáôá w(i,j)*f(j)
{
//Öïñôþíïõìå ôï êýñéï block
//ÊÜèå thread öïñôþíåé ìïíá÷á åíá óôïé÷åßï óôïí ðßíáêá
SubArrayA(threadIdx.x,threadIdx.y)=inputArray[xi*imageSize+yi];
__syncthreads();
//Öïñôþíïõìå óôïí ðßíáêá  Ýíá áðï ôá block åéêüíáò áíÜëïãá ìå ôïí
//áñéèìü ôïõ blockIdx.z óôïí ïðïßï âñéóêüìáóôå
SubArrayB(threadIdx.x,threadIdx.y)=inputArray[xj*imageSize+yj];
__syncthreads();
float SumWeight=nonLocalMeans(subArrayA,subArrayB,imageOut,xi,yi,halfPatchWidth,imageSize,sigma,ZiArray(xi,yi));
atomicAdd(&ImageOut(xi,yi),SumWeight);
__syncthreads();
}
}
}
__device__ float nonLocalMeans(float *inputArrayA,float *inputArrayB,float *imageOut,int xi,int yi,int halfPatchWidth,int imageSize,float sigma,float Zi){
float ww=0;
for(int xj=0;xj<BLOCK_SIZE;xj++)
{
for(int yj=0;yj<BLOCK_SIZE;yj++)
{
ww+=weightingFunct(inputArrayA,inputArrayB,xj,yj,halfPatchWidth,sigma,Zi)*InputArrayB(xj,yj); //w(i,j)*f(j)
}
}
return(ww);
}
//Ç ìåôáâëçôÞ w(i,j)=w([xi,yi] [xj,yj])
__device__ float weightingFunct(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth,float sigma,float Zi){
float distance=gaussianDistance(inputArrayA,inputArrayB,xj,yj,halfPatchWidth);
return ( ( expf(-(distance/(sigma*sigma))) )/Zi);
}
//Ç ìåôáâëçôç Z(i)=Z(xi,yi)
__device__ float normFactor(float *inputArrayA,float *inputArrayB,int halfPatchWidth,float sigma){
float square_sigma=sigma*sigma;
float z=0;
for(int i=0;i<BLOCK_SIZE;i++)
{
for(int j=0;j<BLOCK_SIZE;j++)
{
float distance=gaussianDistance(inputArrayA,inputArrayB,i,j,halfPatchWidth);
z+=expf(-(distance/square_sigma) );
}
}
return (z);
}
//Õðïëïãéóìüò ôçò äéáöïñÜò |f(Ni)-f(Nj)|
//×ñçóéìïðïéïýìå Gaussian Euclidean Distance
__device__ float gaussianDistance(float *inputArrayA,float *inputArrayB,int xj,int yj,int halfPatchWidth){
int xi=threadIdx.x;
int yi=threadIdx.y;
//Ï äåßêôçò i áíáöÝñåôáé óôï pixel ôïõ ïðïßï õðïëïãßæïõìå ôçí íÝá ôéìÞ
//åíþ ï äåßêôçò j óôá õðüëïéðá pixel ìå ôá ïðïßá ãßíåôáé óýãêñéóç
int ai;
int bi;
int aj;
int bj;
int SumWeight=0; //¶èñïéóìá âáñþí
float distance=0;//ÓõíïëéêÞ äéáöïñÜ ãåéôïíéÜò pixel
float diff=0; //ÄéáöïñÜ ìåôáîý 2 pixel ãåéôüíùí
for(int i=-halfPatchWidth;i<=halfPatchWidth;i++)
{
for(int j=-halfPatchWidth;j<=halfPatchWidth;j++)
{
ai=xi+i;
bi=yi+j;
aj=xj+i;
bj=yj+j;
if((aj<0)||(aj>=BLOCK_SIZE)) aj=xj-i;
if((bj<0)||(bj>=BLOCK_SIZE)) bj=yj-j;
if((ai<0)||(ai>=BLOCK_SIZE)) ai=xi-i;
if((bi<0)||(bi>=BLOCK_SIZE)) bi=yi-j;
if (ai!=xi || bi!=yi)//ÊÜíå óýãêñéóç ãéá üëç ôçí ãåéôïíéÜ åêôþò ôïõ êåíôñéêïý
{
int weight=1/(MAX(ai-xi,xi-ai)+MAX(bi-yi,yi-bi));
SumWeight+=weight;
diff=InputArrayA(ai,bi)-InputArrayB(aj,bj);
distance+=diff*diff*weight;
}
}
}
return (distance/SumWeight);
} | .text
.file "gpu_kernel.hip"
.globl _Z30__device_stub__mainGpuFunctionPKfPfS1_iifi # -- Begin function _Z30__device_stub__mainGpuFunctionPKfPfS1_iifi
.p2align 4, 0x90
.type _Z30__device_stub__mainGpuFunctionPKfPfS1_iifi,@function
_Z30__device_stub__mainGpuFunctionPKfPfS1_iifi: # @_Z30__device_stub__mainGpuFunctionPKfPfS1_iifi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15mainGpuFunctionPKfPfS1_iifi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__mainGpuFunctionPKfPfS1_iifi, .Lfunc_end0-_Z30__device_stub__mainGpuFunctionPKfPfS1_iifi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15mainGpuFunctionPKfPfS1_iifi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15mainGpuFunctionPKfPfS1_iifi,@object # @_Z15mainGpuFunctionPKfPfS1_iifi
.section .rodata,"a",@progbits
.globl _Z15mainGpuFunctionPKfPfS1_iifi
.p2align 3, 0x0
_Z15mainGpuFunctionPKfPfS1_iifi:
.quad _Z30__device_stub__mainGpuFunctionPKfPfS1_iifi
.size _Z15mainGpuFunctionPKfPfS1_iifi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15mainGpuFunctionPKfPfS1_iifi"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__mainGpuFunctionPKfPfS1_iifi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15mainGpuFunctionPKfPfS1_iifi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014d41c_00000000-6_gpu_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13nonLocalMeansPfS_S_iiiiff
.type _Z13nonLocalMeansPfS_S_iiiiff, @function
_Z13nonLocalMeansPfS_S_iiiiff:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z13nonLocalMeansPfS_S_iiiiff, .-_Z13nonLocalMeansPfS_S_iiiiff
.globl _Z14weightingFunctPfS_iiiff
.type _Z14weightingFunctPfS_iiiff, @function
_Z14weightingFunctPfS_iiiff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z14weightingFunctPfS_iiiff, .-_Z14weightingFunctPfS_iiiff
.globl _Z10normFactorPfS_if
.type _Z10normFactorPfS_if, @function
_Z10normFactorPfS_if:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10normFactorPfS_if, .-_Z10normFactorPfS_if
.globl _Z16gaussianDistancePfS_iii
.type _Z16gaussianDistancePfS_iii, @function
_Z16gaussianDistancePfS_iii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z16gaussianDistancePfS_iii, .-_Z16gaussianDistancePfS_iii
.globl _Z45__device_stub__Z15mainGpuFunctionPKfPfS1_iifiPKfPfS1_iifi
.type _Z45__device_stub__Z15mainGpuFunctionPKfPfS1_iifiPKfPfS1_iifi, @function
_Z45__device_stub__Z15mainGpuFunctionPKfPfS1_iifiPKfPfS1_iifi:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15mainGpuFunctionPKfPfS1_iifi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z45__device_stub__Z15mainGpuFunctionPKfPfS1_iifiPKfPfS1_iifi, .-_Z45__device_stub__Z15mainGpuFunctionPKfPfS1_iifiPKfPfS1_iifi
.globl _Z15mainGpuFunctionPKfPfS1_iifi
.type _Z15mainGpuFunctionPKfPfS1_iifi, @function
_Z15mainGpuFunctionPKfPfS1_iifi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z15mainGpuFunctionPKfPfS1_iifiPKfPfS1_iifi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z15mainGpuFunctionPKfPfS1_iifi, .-_Z15mainGpuFunctionPKfPfS1_iifi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15mainGpuFunctionPKfPfS1_iifi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15mainGpuFunctionPKfPfS1_iifi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_kernel.hip"
.globl _Z30__device_stub__mainGpuFunctionPKfPfS1_iifi # -- Begin function _Z30__device_stub__mainGpuFunctionPKfPfS1_iifi
.p2align 4, 0x90
.type _Z30__device_stub__mainGpuFunctionPKfPfS1_iifi,@function
_Z30__device_stub__mainGpuFunctionPKfPfS1_iifi: # @_Z30__device_stub__mainGpuFunctionPKfPfS1_iifi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15mainGpuFunctionPKfPfS1_iifi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__mainGpuFunctionPKfPfS1_iifi, .Lfunc_end0-_Z30__device_stub__mainGpuFunctionPKfPfS1_iifi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15mainGpuFunctionPKfPfS1_iifi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15mainGpuFunctionPKfPfS1_iifi,@object # @_Z15mainGpuFunctionPKfPfS1_iifi
.section .rodata,"a",@progbits
.globl _Z15mainGpuFunctionPKfPfS1_iifi
.p2align 3, 0x0
_Z15mainGpuFunctionPKfPfS1_iifi:
.quad _Z30__device_stub__mainGpuFunctionPKfPfS1_iifi
.size _Z15mainGpuFunctionPKfPfS1_iifi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15mainGpuFunctionPKfPfS1_iifi"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__mainGpuFunctionPKfPfS1_iifi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15mainGpuFunctionPKfPfS1_iifi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/*
* Implements vector
*/
#ifdef DEBUG
#endif
__global__ void kern_vec_add_(float* x, float* y, float* r, size_t dim)
{
size_t _strd = blockDim.x * gridDim.x;
for(size_t _i = blockIdx.x * blockDim.x + threadIdx.x; _i < dim; _i += _strd)
r[_i] = x[_i] + y[_i];
} | code for sm_80
Function : _Z13kern_vec_add_PfS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x041fe200078e00ff */
/*00b0*/ SHF.L.U64.HI R7, R0, 0x2, R11 ; /* 0x0000000200077819 */
/* 0x000fc8000001020b */
/*00c0*/ IADD3 R4, P1, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x040fe40007f3e0ff */
/*00d0*/ IADD3 R2, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x000fe40007f1e0ff */
/*00e0*/ IADD3.X R5, R7.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590007057a10 */
/* 0x040fe40000ffe4ff */
/*00f0*/ IADD3.X R3, R7, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0007037a10 */
/* 0x000fc800007fe4ff */
/*0100*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fe20007f1e0ff */
/*0130*/ IMAD R13, R8, c[0x0][0xc], RZ ; /* 0x00000300080d7a24 */
/* 0x000fc600078e02ff */
/*0140*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0007077a10 */
/* 0x000fe400007fe4ff */
/*0150*/ IADD3 R0, P0, R13, R0, RZ ; /* 0x000000000d007210 */
/* 0x000fca0007f1e0ff */
/*0160*/ IMAD.X R11, RZ, RZ, R11, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200000e060b */
/*0170*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0180*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x17c], PT, P0 ; /* 0x00005f000b007a0c */
/* 0x000fe20003f06100 */
/*0190*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*01a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*01b0*/ @!P0 BRA 0xa0 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*
* Implements vector
*/
#ifdef DEBUG
#endif
__global__ void kern_vec_add_(float* x, float* y, float* r, size_t dim)
{
size_t _strd = blockDim.x * gridDim.x;
for(size_t _i = blockIdx.x * blockDim.x + threadIdx.x; _i < dim; _i += _strd)
r[_i] = x[_i] + y[_i];
} | .file "tmpxft_00077794_00000000-6_kern_vec_add_.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13kern_vec_add_PfS_S_mPfS_S_m
.type _Z38__device_stub__Z13kern_vec_add_PfS_S_mPfS_S_m, @function
_Z38__device_stub__Z13kern_vec_add_PfS_S_mPfS_S_m:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kern_vec_add_PfS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13kern_vec_add_PfS_S_mPfS_S_m, .-_Z38__device_stub__Z13kern_vec_add_PfS_S_mPfS_S_m
.globl _Z13kern_vec_add_PfS_S_m
.type _Z13kern_vec_add_PfS_S_m, @function
_Z13kern_vec_add_PfS_S_m:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13kern_vec_add_PfS_S_mPfS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13kern_vec_add_PfS_S_m, .-_Z13kern_vec_add_PfS_S_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13kern_vec_add_PfS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kern_vec_add_PfS_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*
* Implements vector
*/
#ifdef DEBUG
#endif
__global__ void kern_vec_add_(float* x, float* y, float* r, size_t dim)
{
size_t _strd = blockDim.x * gridDim.x;
for(size_t _i = blockIdx.x * blockDim.x + threadIdx.x; _i < dim; _i += _strd)
r[_i] = x[_i] + y[_i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* Implements vector
*/
#ifdef DEBUG
#endif
__global__ void kern_vec_add_(float* x, float* y, float* r, size_t dim)
{
size_t _strd = blockDim.x * gridDim.x;
for(size_t _i = blockIdx.x * blockDim.x + threadIdx.x; _i < dim; _i += _strd)
r[_i] = x[_i] + y[_i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* Implements vector
*/
#ifdef DEBUG
#endif
__global__ void kern_vec_add_(float* x, float* y, float* r, size_t dim)
{
size_t _strd = blockDim.x * gridDim.x;
for(size_t _i = blockIdx.x * blockDim.x + threadIdx.x; _i < dim; _i += _strd)
r[_i] = x[_i] + y[_i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kern_vec_add_PfS_S_m
.globl _Z13kern_vec_add_PfS_S_m
.p2align 8
.type _Z13kern_vec_add_PfS_S_m,@function
_Z13kern_vec_add_PfS_S_m:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s12, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s11, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mov_b32 s1, s11
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s12, s10
s_lshl_b64 s[12:13], s[10:11], 2
.p2align 6
.LBB0_2:
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s10
global_load_b32 v0, v[5:6], off
global_load_b32 v7, v[7:8], off
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_add_co_u32 v3, s0, v3, s12
v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v7
global_store_b32 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kern_vec_add_PfS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kern_vec_add_PfS_S_m, .Lfunc_end0-_Z13kern_vec_add_PfS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kern_vec_add_PfS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kern_vec_add_PfS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* Implements vector
*/
#ifdef DEBUG
#endif
__global__ void kern_vec_add_(float* x, float* y, float* r, size_t dim)
{
size_t _strd = blockDim.x * gridDim.x;
for(size_t _i = blockIdx.x * blockDim.x + threadIdx.x; _i < dim; _i += _strd)
r[_i] = x[_i] + y[_i];
} | .text
.file "kern_vec_add_.hip"
.globl _Z28__device_stub__kern_vec_add_PfS_S_m # -- Begin function _Z28__device_stub__kern_vec_add_PfS_S_m
.p2align 4, 0x90
.type _Z28__device_stub__kern_vec_add_PfS_S_m,@function
_Z28__device_stub__kern_vec_add_PfS_S_m: # @_Z28__device_stub__kern_vec_add_PfS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kern_vec_add_PfS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__kern_vec_add_PfS_S_m, .Lfunc_end0-_Z28__device_stub__kern_vec_add_PfS_S_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kern_vec_add_PfS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kern_vec_add_PfS_S_m,@object # @_Z13kern_vec_add_PfS_S_m
.section .rodata,"a",@progbits
.globl _Z13kern_vec_add_PfS_S_m
.p2align 3, 0x0
_Z13kern_vec_add_PfS_S_m:
.quad _Z28__device_stub__kern_vec_add_PfS_S_m
.size _Z13kern_vec_add_PfS_S_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kern_vec_add_PfS_S_m"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kern_vec_add_PfS_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kern_vec_add_PfS_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13kern_vec_add_PfS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x041fe200078e00ff */
/*00b0*/ SHF.L.U64.HI R7, R0, 0x2, R11 ; /* 0x0000000200077819 */
/* 0x000fc8000001020b */
/*00c0*/ IADD3 R4, P1, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x040fe40007f3e0ff */
/*00d0*/ IADD3 R2, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x000fe40007f1e0ff */
/*00e0*/ IADD3.X R5, R7.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590007057a10 */
/* 0x040fe40000ffe4ff */
/*00f0*/ IADD3.X R3, R7, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0007037a10 */
/* 0x000fc800007fe4ff */
/*0100*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fe20007f1e0ff */
/*0130*/ IMAD R13, R8, c[0x0][0xc], RZ ; /* 0x00000300080d7a24 */
/* 0x000fc600078e02ff */
/*0140*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0007077a10 */
/* 0x000fe400007fe4ff */
/*0150*/ IADD3 R0, P0, R13, R0, RZ ; /* 0x000000000d007210 */
/* 0x000fca0007f1e0ff */
/*0160*/ IMAD.X R11, RZ, RZ, R11, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200000e060b */
/*0170*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0180*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x17c], PT, P0 ; /* 0x00005f000b007a0c */
/* 0x000fe20003f06100 */
/*0190*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*01a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*01b0*/ @!P0 BRA 0xa0 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kern_vec_add_PfS_S_m
.globl _Z13kern_vec_add_PfS_S_m
.p2align 8
.type _Z13kern_vec_add_PfS_S_m,@function
_Z13kern_vec_add_PfS_S_m:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s12, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s11, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mov_b32 s1, s11
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s12, s10
s_lshl_b64 s[12:13], s[10:11], 2
.p2align 6
.LBB0_2:
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s10
global_load_b32 v0, v[5:6], off
global_load_b32 v7, v[7:8], off
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_add_co_u32 v3, s0, v3, s12
v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v7
global_store_b32 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kern_vec_add_PfS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kern_vec_add_PfS_S_m, .Lfunc_end0-_Z13kern_vec_add_PfS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kern_vec_add_PfS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kern_vec_add_PfS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00077794_00000000-6_kern_vec_add_.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13kern_vec_add_PfS_S_mPfS_S_m
.type _Z38__device_stub__Z13kern_vec_add_PfS_S_mPfS_S_m, @function
_Z38__device_stub__Z13kern_vec_add_PfS_S_mPfS_S_m:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kern_vec_add_PfS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13kern_vec_add_PfS_S_mPfS_S_m, .-_Z38__device_stub__Z13kern_vec_add_PfS_S_mPfS_S_m
.globl _Z13kern_vec_add_PfS_S_m
.type _Z13kern_vec_add_PfS_S_m, @function
_Z13kern_vec_add_PfS_S_m:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13kern_vec_add_PfS_S_mPfS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13kern_vec_add_PfS_S_m, .-_Z13kern_vec_add_PfS_S_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13kern_vec_add_PfS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kern_vec_add_PfS_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kern_vec_add_.hip"
.globl _Z28__device_stub__kern_vec_add_PfS_S_m # -- Begin function _Z28__device_stub__kern_vec_add_PfS_S_m
.p2align 4, 0x90
.type _Z28__device_stub__kern_vec_add_PfS_S_m,@function
_Z28__device_stub__kern_vec_add_PfS_S_m: # @_Z28__device_stub__kern_vec_add_PfS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kern_vec_add_PfS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__kern_vec_add_PfS_S_m, .Lfunc_end0-_Z28__device_stub__kern_vec_add_PfS_S_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kern_vec_add_PfS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kern_vec_add_PfS_S_m,@object # @_Z13kern_vec_add_PfS_S_m
.section .rodata,"a",@progbits
.globl _Z13kern_vec_add_PfS_S_m
.p2align 3, 0x0
_Z13kern_vec_add_PfS_S_m:
.quad _Z28__device_stub__kern_vec_add_PfS_S_m
.size _Z13kern_vec_add_PfS_S_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kern_vec_add_PfS_S_m"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kern_vec_add_PfS_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kern_vec_add_PfS_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#define THREADS_PER_BLOCK 256
__global__ void MatrixMul( float *Md , float *Nd , float *Pd , const int WIDTH )
{
int COL = threadIdx.x + blockIdx.x * blockDim.x;
int ROW = threadIdx.y + blockIdx.y * blockDim.y;
if (ROW < WIDTH && COL < WIDTH) {
for (int i = 0; i < WIDTH; i++) {
Pd[ROW * WIDTH + COL] += Md[ROW * WIDTH + i] * Nd [i * WIDTH + COL];
}
}
}
int main(int arg0, char *arg1[]){
cudaThreadSynchronize();
int WIDTH = atoi(arg1[1]);
int sqrtThreads = sqrt(THREADS_PER_BLOCK);
int nBlocks = WIDTH/sqrtThreads;
if (WIDTH % sqrtThreads != 0)
{
nBlocks++;
}
dim3 grid(nBlocks, nBlocks, 1);
dim3 block(sqrtThreads, sqrtThreads, 1);
float *a_h, *b_h, *c_h, *d_h, *a_d, *b_d, *c_d;
int size;
cudaEvent_t start;
cudaEvent_t stop;
float elapsed1;
size = WIDTH * WIDTH * sizeof(float);
a_h = (float*) malloc(size);
b_h = (float*) malloc(size);
c_h = (float*) malloc(size);
d_h = (float*) malloc(size);
for (int i = 0; i < WIDTH; i++)
{
for (int j = 0; j < WIDTH; j++)
{
a_h[i * WIDTH + j] = i;
b_h[i * WIDTH + j] = i;
}
}
cudaMalloc((void**)&a_d, size);
cudaMalloc((void**)&b_d, size);
cudaMalloc((void**)&c_d, size);
cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(b_d, b_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, size, cudaMemcpyHostToDevice);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
MatrixMul<<<grid, block>>>(a_d, b_d, c_d, WIDTH);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed1, start, stop);
printf("%f\n", elapsed1/1000);
cudaMemcpy(c_h, c_d, size, cudaMemcpyDeviceToHost);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
cudaFree(a_d);
cudaFree(b_d);
cudaFree(c_d);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | code for sm_80
Function : _Z9MatrixMulPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fe200078e0200 */
/*0060*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc80000000f00 */
/*0070*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R9, R9, c[0x0][0x4], R2 ; /* 0x0000010009097a24 */
/* 0x002fca00078e0202 */
/*0090*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x178], P0 ; /* 0x00005e0009007a0c */
/* 0x000fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD R9, R9, c[0x0][0x178], RZ ; /* 0x00005e0009097a24 */
/* 0x000fe200078e02ff */
/*00e0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0110*/ IADD3 R3, R5, R9, RZ ; /* 0x0000000905037210 */
/* 0x000fe40007ffe0ff */
/*0120*/ LOP3.LUT R4, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300047812 */
/* 0x000fe400078ec0ff */
/*0130*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fc40000000f00 */
/*0140*/ IMAD.WIDE R2, R3, R8, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0208 */
/*0150*/ @!P0 BRA 0xcb0 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R11, -R4, c[0x0][0x178], RZ ; /* 0x00005e00040b7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000162000c1e1900 */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe20000000f00 */
/*01a0*/ IMAD.WIDE R12, R5, R8, c[0x0][0x168] ; /* 0x00005a00050c7625 */
/* 0x000fe200078e0208 */
/*01b0*/ ISETP.GT.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fda0003f04270 */
/*01c0*/ @!P0 BRA 0xae0 ; /* 0x0000091000008947 */
/* 0x001fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x7a0 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x004ea2000c1e1900 */
/*0230*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0250*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ea4000c1e1900 */
/*0260*/ FFMA R19, R14, R16, R15 ; /* 0x000000100e137223 */
/* 0x024fe4000000000f */
/*0270*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0280*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0290*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*02b0*/ FFMA R21, R16, R17, R19 ; /* 0x0000001110157223 */
/* 0x004fc40000000013 */
/*02c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*02d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ LDG.E R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ FFMA R23, R18, R12, R21 ; /* 0x0000000c12177223 */
/* 0x004fc40000000015 */
/*0310*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0320*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0330*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*0340*/ LDG.E R14, [R6.64+0xc] ; /* 0x00000c04060e7981 */
/* 0x000e24000c1e1900 */
/*0350*/ FFMA R19, R18, R14, R23 ; /* 0x0000000e12137223 */
/* 0x001fc40000000017 */
/*0360*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0370*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0380*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0390*/ LDG.E R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000e64000c1e1900 */
/*03a0*/ FFMA R21, R18, R16, R19 ; /* 0x0000001012157223 */
/* 0x002fc40000000013 */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*03c0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*03d0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*03e0*/ LDG.E R12, [R6.64+0x14] ; /* 0x00001404060c7981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ FFMA R23, R18, R12, R21 ; /* 0x0000000c12177223 */
/* 0x004fc40000000015 */
/*0400*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0410*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0420*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*0430*/ LDG.E R14, [R6.64+0x18] ; /* 0x00001804060e7981 */
/* 0x000e24000c1e1900 */
/*0440*/ FFMA R19, R18, R14, R23 ; /* 0x0000000e12137223 */
/* 0x001fc40000000017 */
/*0450*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0460*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0470*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0480*/ LDG.E R16, [R6.64+0x1c] ; /* 0x00001c0406107981 */
/* 0x000e64000c1e1900 */
/*0490*/ FFMA R21, R18, R16, R19 ; /* 0x0000001012157223 */
/* 0x002fc40000000013 */
/*04a0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*04b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*04c0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R12, [R6.64+0x20] ; /* 0x00002004060c7981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ FFMA R23, R18, R12, R21 ; /* 0x0000000c12177223 */
/* 0x004fc40000000015 */
/*04f0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0500*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0510*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*0520*/ LDG.E R14, [R6.64+0x24] ; /* 0x00002404060e7981 */
/* 0x000e24000c1e1900 */
/*0530*/ FFMA R19, R18, R14, R23 ; /* 0x0000000e12137223 */
/* 0x001fc40000000017 */
/*0540*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0550*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe8000c101904 */
/*0560*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0570*/ LDG.E R16, [R6.64+0x28] ; /* 0x0000280406107981 */
/* 0x000e64000c1e1900 */
/*0580*/ FFMA R21, R18, R16, R19 ; /* 0x0000001012157223 */
/* 0x002fc40000000013 */
/*0590*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*05a0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*05b0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*05c0*/ LDG.E R12, [R6.64+0x2c] ; /* 0x00002c04060c7981 */
/* 0x000ea4000c1e1900 */
/*05d0*/ FFMA R23, R18, R12, R21 ; /* 0x0000000c12177223 */
/* 0x004fc40000000015 */
/*05e0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*05f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0600*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R14, [R6.64+0x30] ; /* 0x00003004060e7981 */
/* 0x000ea4000c1e1900 */
/*0620*/ FFMA R25, R18, R14, R23 ; /* 0x0000000e12197223 */
/* 0x004fc40000000017 */
/*0630*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0640*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0650*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e28000c1e1900 */
/*0660*/ LDG.E R16, [R6.64+0x34] ; /* 0x0000340406107981 */
/* 0x000e24000c1e1900 */
/*0670*/ FFMA R21, R18, R16, R25 ; /* 0x0000001012157223 */
/* 0x001fc40000000019 */
/*0680*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0690*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*06a0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000e68000c1e1900 */
/*06b0*/ LDG.E R12, [R6.64+0x38] ; /* 0x00003804060c7981 */
/* 0x000e62000c1e1900 */
/*06c0*/ IADD3 R11, R11, -0x10, RZ ; /* 0xfffffff00b0b7810 */
/* 0x000fe20007ffe0ff */
/*06d0*/ FFMA R23, R18, R12, R21 ; /* 0x0000000c12177223 */
/* 0x002fc40000000015 */
/*06e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*06f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0700*/ LDG.E R13, [R6.64+0x3c] ; /* 0x00003c04060d7981 */
/* 0x000ee8000c1e1900 */
/*0710*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ee2000c1e1900 */
/*0720*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe20003f24270 */
/*0730*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0740*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fc60007ffe0ff */
/*0750*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0760*/ FFMA R15, R12, R13, R23 ; /* 0x0000000d0c0f7223 */
/* 0x008fe40000000017 */
/*0770*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0212 */
/*0780*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e4000c101904 */
/*0790*/ @P1 BRA 0x210 ; /* 0xfffffa7000001947 */
/* 0x000fea000383ffff */
/*07a0*/ ISETP.GT.AND P1, PT, R11, 0x4, PT ; /* 0x000000040b00780c */
/* 0x000fda0003f24270 */
/*07b0*/ @!P1 BRA 0xac0 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*07c0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*07d0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ee2000c1e1900 */
/*07e0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*07f0*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0800*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ee4000c1e1900 */
/*0810*/ FFMA R19, R14, R16, R15 ; /* 0x000000100e137223 */
/* 0x028fe4000000000f */
/*0820*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x004fc600078e020c */
/*0830*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0840*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*0860*/ FFMA R21, R16, R17, R19 ; /* 0x0000001110157223 */
/* 0x004fc40000000013 */
/*0870*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0880*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0890*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*08a0*/ LDG.E R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea4000c1e1900 */
/*08b0*/ FFMA R23, R18, R12, R21 ; /* 0x0000000c12177223 */
/* 0x004fc40000000015 */
/*08c0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*08d0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*08e0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*08f0*/ LDG.E R14, [R6.64+0xc] ; /* 0x00000c04060e7981 */
/* 0x000e24000c1e1900 */
/*0900*/ FFMA R19, R18, R14, R23 ; /* 0x0000000e12137223 */
/* 0x001fc40000000017 */
/*0910*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0920*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0930*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0940*/ LDG.E R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000e64000c1e1900 */
/*0950*/ FFMA R21, R18, R16, R19 ; /* 0x0000001012157223 */
/* 0x002fc40000000013 */
/*0960*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0970*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0980*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0990*/ LDG.E R12, [R6.64+0x14] ; /* 0x00001404060c7981 */
/* 0x000ea4000c1e1900 */
/*09a0*/ FFMA R23, R18, R12, R21 ; /* 0x0000000c12177223 */
/* 0x004fc40000000015 */
/*09b0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*09c0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*09d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R6.64+0x18] ; /* 0x00001804060e7981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ FFMA R25, R18, R14, R23 ; /* 0x0000000e12197223 */
/* 0x004fc40000000017 */
/*0a00*/ IMAD.WIDE R18, R0, 0x4, R12 ; /* 0x0000000400127825 */
/* 0x001fc600078e020c */
/*0a10*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0a20*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c04060f7981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea2000c1e1900 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a60*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0212 */
/*0a70*/ IADD3 R10, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fc40007ffe0ff */
/*0a80*/ IADD3 R11, R11, -0x8, RZ ; /* 0xfffffff80b0b7810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R15, R14, R15, R25 ; /* 0x0000000f0e0f7223 */
/* 0x004fca0000000019 */
/*0ab0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*0ac0*/ ISETP.NE.OR P0, PT, R11, RZ, P0 ; /* 0x000000ff0b00720c */
/* 0x000fda0000705670 */
/*0ad0*/ @!P0 BRA 0xcb0 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0af0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ee2000c1e1900 */
/*0b00*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0b10*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0b20*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ee4000c1e1900 */
/*0b30*/ FFMA R21, R14, R16, R15 ; /* 0x000000100e157223 */
/* 0x02efe4000000000f */
/*0b40*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0b50*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0b60*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*0b70*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*0b80*/ FFMA R23, R16, R17, R21 ; /* 0x0000001110177223 */
/* 0x004fc40000000015 */
/*0b90*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0ba0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e8000c101904 */
/*0bb0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ LDG.E R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea2000c1e1900 */
/*0bd0*/ IADD3 R11, R11, -0x4, RZ ; /* 0xfffffffc0b0b7810 */
/* 0x000fe20007ffe0ff */
/*0be0*/ FFMA R25, R18, R12, R23 ; /* 0x0000000c12197223 */
/* 0x004fc40000000017 */
/*0bf0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0c00*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0001e8000c101904 */
/*0c10*/ LDG.E R13, [R6.64+0xc] ; /* 0x00000c04060d7981 */
/* 0x000ea8000c1e1900 */
/*0c20*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*0c30*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f05270 */
/*0c40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0c50*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc60007ffe0ff */
/*0c60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0c70*/ FFMA R15, R12, R13, R25 ; /* 0x0000000d0c0f7223 */
/* 0x004fe40000000019 */
/*0c80*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0212 */
/*0c90*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e4000c101904 */
/*0ca0*/ @P0 BRA 0xae0 ; /* 0xfffffe3000000947 */
/* 0x001fea000383ffff */
/*0cb0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0cc0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cd0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000162000c1e1900 */
/*0ce0*/ IADD3 R7, R9, R10, RZ ; /* 0x0000000a09077210 */
/* 0x000fe20007ffe0ff */
/*0cf0*/ IMAD R5, R10, c[0x0][0x178], R5 ; /* 0x00005e000a057a24 */
/* 0x000fc800078e0205 */
/*0d00*/ IMAD.WIDE R6, R7, R8, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fc800078e0208 */
/*0d10*/ IMAD.WIDE R8, R5, R8, c[0x0][0x168] ; /* 0x00005a0005087625 */
/* 0x001fca00078e0208 */
/*0d20*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0010e8000c1e1900 */
/*0d30*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x0008e2000c1e1900 */
/*0d40*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*0d50*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0d60*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0d70*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x010fc80007f3e0ff */
/*0d80*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0d90*/ FFMA R11, R10, R5, R11 ; /* 0x000000050a0b7223 */
/* 0x028fca000000000b */
/*0da0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e2000c101904 */
/*0db0*/ @P0 BRA 0xd20 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0dc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0dd0*/ BRA 0xdd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#define THREADS_PER_BLOCK 256
__global__ void MatrixMul( float *Md , float *Nd , float *Pd , const int WIDTH )
{
int COL = threadIdx.x + blockIdx.x * blockDim.x;
int ROW = threadIdx.y + blockIdx.y * blockDim.y;
if (ROW < WIDTH && COL < WIDTH) {
for (int i = 0; i < WIDTH; i++) {
Pd[ROW * WIDTH + COL] += Md[ROW * WIDTH + i] * Nd [i * WIDTH + COL];
}
}
}
int main(int arg0, char *arg1[]){
cudaThreadSynchronize();
int WIDTH = atoi(arg1[1]);
int sqrtThreads = sqrt(THREADS_PER_BLOCK);
int nBlocks = WIDTH/sqrtThreads;
if (WIDTH % sqrtThreads != 0)
{
nBlocks++;
}
dim3 grid(nBlocks, nBlocks, 1);
dim3 block(sqrtThreads, sqrtThreads, 1);
float *a_h, *b_h, *c_h, *d_h, *a_d, *b_d, *c_d;
int size;
cudaEvent_t start;
cudaEvent_t stop;
float elapsed1;
size = WIDTH * WIDTH * sizeof(float);
a_h = (float*) malloc(size);
b_h = (float*) malloc(size);
c_h = (float*) malloc(size);
d_h = (float*) malloc(size);
for (int i = 0; i < WIDTH; i++)
{
for (int j = 0; j < WIDTH; j++)
{
a_h[i * WIDTH + j] = i;
b_h[i * WIDTH + j] = i;
}
}
cudaMalloc((void**)&a_d, size);
cudaMalloc((void**)&b_d, size);
cudaMalloc((void**)&c_d, size);
cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(b_d, b_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, size, cudaMemcpyHostToDevice);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
MatrixMul<<<grid, block>>>(a_d, b_d, c_d, WIDTH);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed1, start, stop);
printf("%f\n", elapsed1/1000);
cudaMemcpy(c_h, c_d, size, cudaMemcpyDeviceToHost);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
cudaFree(a_d);
cudaFree(b_d);
cudaFree(c_d);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | .file "tmpxft_000aa272_00000000-6_Global.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9MatrixMulPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9MatrixMulPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9MatrixMulPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9MatrixMulPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z9MatrixMulPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9MatrixMulPfS_S_iPfS_S_i
.globl _Z9MatrixMulPfS_S_i
.type _Z9MatrixMulPfS_S_i, @function
_Z9MatrixMulPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9MatrixMulPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9MatrixMulPfS_S_i, .-_Z9MatrixMulPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
call cudaThreadSynchronize@PLT
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %r13d
leal 15(%rax), %eax
testl %r15d, %r15d
cmovns %r15d, %eax
sarl $4, %eax
movl %r15d, %edx
andl $15, %edx
cmpl $1, %edx
sbbl $-1, %eax
movl %eax, 48(%rsp)
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $16, 60(%rsp)
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movl %r15d, %r12d
imull %r15d, %r12d
sall $2, %r12d
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
testl %r15d, %r15d
jle .L13
movslq %r15d, %rdi
salq $2, %rdi
movl %r15d, %edx
salq $2, %rdx
movl $0, %ecx
movl %r15d, %r15d
negq %r15
leaq 0(,%r15,4), %rsi
.L14:
leaq (%rsi,%rdx), %rax
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
.L15:
movss %xmm0, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L15
addl $1, %ecx
addq %rdi, %rdx
cmpl %r13d, %ecx
jne .L14
.L13:
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 4(%rsp), %xmm0
divss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl %r13d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9MatrixMulPfS_S_iPfS_S_i
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z9MatrixMulPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9MatrixMulPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#define THREADS_PER_BLOCK 256
__global__ void MatrixMul( float *Md , float *Nd , float *Pd , const int WIDTH )
{
int COL = threadIdx.x + blockIdx.x * blockDim.x;
int ROW = threadIdx.y + blockIdx.y * blockDim.y;
if (ROW < WIDTH && COL < WIDTH) {
for (int i = 0; i < WIDTH; i++) {
Pd[ROW * WIDTH + COL] += Md[ROW * WIDTH + i] * Nd [i * WIDTH + COL];
}
}
}
int main(int arg0, char *arg1[]){
cudaThreadSynchronize();
int WIDTH = atoi(arg1[1]);
int sqrtThreads = sqrt(THREADS_PER_BLOCK);
int nBlocks = WIDTH/sqrtThreads;
if (WIDTH % sqrtThreads != 0)
{
nBlocks++;
}
dim3 grid(nBlocks, nBlocks, 1);
dim3 block(sqrtThreads, sqrtThreads, 1);
float *a_h, *b_h, *c_h, *d_h, *a_d, *b_d, *c_d;
int size;
cudaEvent_t start;
cudaEvent_t stop;
float elapsed1;
size = WIDTH * WIDTH * sizeof(float);
a_h = (float*) malloc(size);
b_h = (float*) malloc(size);
c_h = (float*) malloc(size);
d_h = (float*) malloc(size);
for (int i = 0; i < WIDTH; i++)
{
for (int j = 0; j < WIDTH; j++)
{
a_h[i * WIDTH + j] = i;
b_h[i * WIDTH + j] = i;
}
}
cudaMalloc((void**)&a_d, size);
cudaMalloc((void**)&b_d, size);
cudaMalloc((void**)&c_d, size);
cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(b_d, b_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(c_d, c_h, size, cudaMemcpyHostToDevice);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
MatrixMul<<<grid, block>>>(a_d, b_d, c_d, WIDTH);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed1, start, stop);
printf("%f\n", elapsed1/1000);
cudaMemcpy(c_h, c_d, size, cudaMemcpyDeviceToHost);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
cudaFree(a_d);
cudaFree(b_d);
cudaFree(c_d);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define THREADS_PER_BLOCK 256
__global__ void MatrixMul( float *Md , float *Nd , float *Pd , const int WIDTH )
{
int COL = threadIdx.x + blockIdx.x * blockDim.x;
int ROW = threadIdx.y + blockIdx.y * blockDim.y;
if (ROW < WIDTH && COL < WIDTH) {
for (int i = 0; i < WIDTH; i++) {
Pd[ROW * WIDTH + COL] += Md[ROW * WIDTH + i] * Nd [i * WIDTH + COL];
}
}
}
int main(int arg0, char *arg1[]){
hipDeviceSynchronize();
int WIDTH = atoi(arg1[1]);
int sqrtThreads = sqrt(THREADS_PER_BLOCK);
int nBlocks = WIDTH/sqrtThreads;
if (WIDTH % sqrtThreads != 0)
{
nBlocks++;
}
dim3 grid(nBlocks, nBlocks, 1);
dim3 block(sqrtThreads, sqrtThreads, 1);
float *a_h, *b_h, *c_h, *d_h, *a_d, *b_d, *c_d;
int size;
hipEvent_t start;
hipEvent_t stop;
float elapsed1;
size = WIDTH * WIDTH * sizeof(float);
a_h = (float*) malloc(size);
b_h = (float*) malloc(size);
c_h = (float*) malloc(size);
d_h = (float*) malloc(size);
for (int i = 0; i < WIDTH; i++)
{
for (int j = 0; j < WIDTH; j++)
{
a_h[i * WIDTH + j] = i;
b_h[i * WIDTH + j] = i;
}
}
hipMalloc((void**)&a_d, size);
hipMalloc((void**)&b_d, size);
hipMalloc((void**)&c_d, size);
hipMemcpy(a_d, a_h, size, hipMemcpyHostToDevice);
hipMemcpy(b_d, b_h, size, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, size, hipMemcpyHostToDevice);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
MatrixMul<<<grid, block>>>(a_d, b_d, c_d, WIDTH);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed1, start, stop);
printf("%f\n", elapsed1/1000);
hipMemcpy(c_h, c_d, size, hipMemcpyDeviceToHost);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
hipFree(a_d);
hipFree(b_d);
hipFree(c_d);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define THREADS_PER_BLOCK 256
__global__ void MatrixMul( float *Md , float *Nd , float *Pd , const int WIDTH )
{
int COL = threadIdx.x + blockIdx.x * blockDim.x;
int ROW = threadIdx.y + blockIdx.y * blockDim.y;
if (ROW < WIDTH && COL < WIDTH) {
for (int i = 0; i < WIDTH; i++) {
Pd[ROW * WIDTH + COL] += Md[ROW * WIDTH + i] * Nd [i * WIDTH + COL];
}
}
}
int main(int arg0, char *arg1[]){
hipDeviceSynchronize();
int WIDTH = atoi(arg1[1]);
int sqrtThreads = sqrt(THREADS_PER_BLOCK);
int nBlocks = WIDTH/sqrtThreads;
if (WIDTH % sqrtThreads != 0)
{
nBlocks++;
}
dim3 grid(nBlocks, nBlocks, 1);
dim3 block(sqrtThreads, sqrtThreads, 1);
float *a_h, *b_h, *c_h, *d_h, *a_d, *b_d, *c_d;
int size;
hipEvent_t start;
hipEvent_t stop;
float elapsed1;
size = WIDTH * WIDTH * sizeof(float);
a_h = (float*) malloc(size);
b_h = (float*) malloc(size);
c_h = (float*) malloc(size);
d_h = (float*) malloc(size);
for (int i = 0; i < WIDTH; i++)
{
for (int j = 0; j < WIDTH; j++)
{
a_h[i * WIDTH + j] = i;
b_h[i * WIDTH + j] = i;
}
}
hipMalloc((void**)&a_d, size);
hipMalloc((void**)&b_d, size);
hipMalloc((void**)&c_d, size);
hipMemcpy(a_d, a_h, size, hipMemcpyHostToDevice);
hipMemcpy(b_d, b_h, size, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, size, hipMemcpyHostToDevice);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
MatrixMul<<<grid, block>>>(a_d, b_d, c_d, WIDTH);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed1, start, stop);
printf("%f\n", elapsed1/1000);
hipMemcpy(c_h, c_d, size, hipMemcpyDeviceToHost);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
hipFree(a_d);
hipFree(b_d);
hipFree(c_d);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9MatrixMulPfS_S_i
.globl _Z9MatrixMulPfS_S_i
.p2align 8
.type _Z9MatrixMulPfS_S_i,@function
_Z9MatrixMulPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max3_i32 v2, v0, v1, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_3
v_mul_lo_u32 v4, v1, s4
s_load_b64 s[2:3], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, v4, v0
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v6, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b32 s0, s4
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s0, 0
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v1, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v1, v7
global_store_b32 v[2:3], v6, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9MatrixMulPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9MatrixMulPfS_S_i, .Lfunc_end0-_Z9MatrixMulPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9MatrixMulPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9MatrixMulPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define THREADS_PER_BLOCK 256
__global__ void MatrixMul( float *Md , float *Nd , float *Pd , const int WIDTH )
{
int COL = threadIdx.x + blockIdx.x * blockDim.x;
int ROW = threadIdx.y + blockIdx.y * blockDim.y;
if (ROW < WIDTH && COL < WIDTH) {
for (int i = 0; i < WIDTH; i++) {
Pd[ROW * WIDTH + COL] += Md[ROW * WIDTH + i] * Nd [i * WIDTH + COL];
}
}
}
int main(int arg0, char *arg1[]){
hipDeviceSynchronize();
int WIDTH = atoi(arg1[1]);
int sqrtThreads = sqrt(THREADS_PER_BLOCK);
int nBlocks = WIDTH/sqrtThreads;
if (WIDTH % sqrtThreads != 0)
{
nBlocks++;
}
dim3 grid(nBlocks, nBlocks, 1);
dim3 block(sqrtThreads, sqrtThreads, 1);
float *a_h, *b_h, *c_h, *d_h, *a_d, *b_d, *c_d;
int size;
hipEvent_t start;
hipEvent_t stop;
float elapsed1;
size = WIDTH * WIDTH * sizeof(float);
a_h = (float*) malloc(size);
b_h = (float*) malloc(size);
c_h = (float*) malloc(size);
d_h = (float*) malloc(size);
for (int i = 0; i < WIDTH; i++)
{
for (int j = 0; j < WIDTH; j++)
{
a_h[i * WIDTH + j] = i;
b_h[i * WIDTH + j] = i;
}
}
hipMalloc((void**)&a_d, size);
hipMalloc((void**)&b_d, size);
hipMalloc((void**)&c_d, size);
hipMemcpy(a_d, a_h, size, hipMemcpyHostToDevice);
hipMemcpy(b_d, b_h, size, hipMemcpyHostToDevice);
hipMemcpy(c_d, c_h, size, hipMemcpyHostToDevice);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
MatrixMul<<<grid, block>>>(a_d, b_d, c_d, WIDTH);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed1, start, stop);
printf("%f\n", elapsed1/1000);
hipMemcpy(c_h, c_d, size, hipMemcpyDeviceToHost);
free(a_h);
free(b_h);
free(c_h);
free(d_h);
hipFree(a_d);
hipFree(b_d);
hipFree(c_d);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.file "Global.hip"
.globl _Z24__device_stub__MatrixMulPfS_S_i # -- Begin function _Z24__device_stub__MatrixMulPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__MatrixMulPfS_S_i,@function
_Z24__device_stub__MatrixMulPfS_S_i: # @_Z24__device_stub__MatrixMulPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9MatrixMulPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__MatrixMulPfS_S_i, .Lfunc_end0-_Z24__device_stub__MatrixMulPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
callq hipDeviceSynchronize
movq 8(%rbx), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
addl $15, %eax
testl %r13d, %r13d
cmovnsl %r13d, %eax
sarl $4, %eax
movl %r13d, %ecx
andl $15, %ecx
cmpl $1, %ecx
sbbl $-1, %eax
movq %rax, %rbp
shlq $32, %rbp
orq %rax, %rbp
movl %r13d, %eax
imull %r13d, %eax
shll $2, %eax
movslq %eax, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq %rbx, %rdi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %r13d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r12d, %esi
leaq (%r15,%rsi,4), %rdx
leaq (%r14,%rsi,4), %rsi
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm0, (%rsi,%rdi,4)
movss %xmm0, (%rdx,%rdi,4)
incq %rdi
cmpq %rdi, %rax
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rcx
addl %r13d, %r12d
cmpq %rax, %rcx
jne .LBB1_2
.LBB1_5: # %._crit_edge62
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 48(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r13d, 44(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9MatrixMulPfS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movq %r12, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9MatrixMulPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9MatrixMulPfS_S_i,@object # @_Z9MatrixMulPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9MatrixMulPfS_S_i
.p2align 3, 0x0
_Z9MatrixMulPfS_S_i:
.quad _Z24__device_stub__MatrixMulPfS_S_i
.size _Z9MatrixMulPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9MatrixMulPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__MatrixMulPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9MatrixMulPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9MatrixMulPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fe200078e0200 */
/*0060*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc80000000f00 */
/*0070*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R9, R9, c[0x0][0x4], R2 ; /* 0x0000010009097a24 */
/* 0x002fca00078e0202 */
/*0090*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x178], P0 ; /* 0x00005e0009007a0c */
/* 0x000fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD R9, R9, c[0x0][0x178], RZ ; /* 0x00005e0009097a24 */
/* 0x000fe200078e02ff */
/*00e0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0110*/ IADD3 R3, R5, R9, RZ ; /* 0x0000000905037210 */
/* 0x000fe40007ffe0ff */
/*0120*/ LOP3.LUT R4, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300047812 */
/* 0x000fe400078ec0ff */
/*0130*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fc40000000f00 */
/*0140*/ IMAD.WIDE R2, R3, R8, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0208 */
/*0150*/ @!P0 BRA 0xcb0 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R11, -R4, c[0x0][0x178], RZ ; /* 0x00005e00040b7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000162000c1e1900 */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe20000000f00 */
/*01a0*/ IMAD.WIDE R12, R5, R8, c[0x0][0x168] ; /* 0x00005a00050c7625 */
/* 0x000fe200078e0208 */
/*01b0*/ ISETP.GT.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fda0003f04270 */
/*01c0*/ @!P0 BRA 0xae0 ; /* 0x0000091000008947 */
/* 0x001fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x7a0 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x004ea2000c1e1900 */
/*0230*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0250*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ea4000c1e1900 */
/*0260*/ FFMA R19, R14, R16, R15 ; /* 0x000000100e137223 */
/* 0x024fe4000000000f */
/*0270*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0280*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0290*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*02b0*/ FFMA R21, R16, R17, R19 ; /* 0x0000001110157223 */
/* 0x004fc40000000013 */
/*02c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*02d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ LDG.E R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ FFMA R23, R18, R12, R21 ; /* 0x0000000c12177223 */
/* 0x004fc40000000015 */
/*0310*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0320*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0330*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*0340*/ LDG.E R14, [R6.64+0xc] ; /* 0x00000c04060e7981 */
/* 0x000e24000c1e1900 */
/*0350*/ FFMA R19, R18, R14, R23 ; /* 0x0000000e12137223 */
/* 0x001fc40000000017 */
/*0360*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0370*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0380*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0390*/ LDG.E R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000e64000c1e1900 */
/*03a0*/ FFMA R21, R18, R16, R19 ; /* 0x0000001012157223 */
/* 0x002fc40000000013 */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*03c0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*03d0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*03e0*/ LDG.E R12, [R6.64+0x14] ; /* 0x00001404060c7981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ FFMA R23, R18, R12, R21 ; /* 0x0000000c12177223 */
/* 0x004fc40000000015 */
/*0400*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0410*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0420*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*0430*/ LDG.E R14, [R6.64+0x18] ; /* 0x00001804060e7981 */
/* 0x000e24000c1e1900 */
/*0440*/ FFMA R19, R18, R14, R23 ; /* 0x0000000e12137223 */
/* 0x001fc40000000017 */
/*0450*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0460*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0470*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0480*/ LDG.E R16, [R6.64+0x1c] ; /* 0x00001c0406107981 */
/* 0x000e64000c1e1900 */
/*0490*/ FFMA R21, R18, R16, R19 ; /* 0x0000001012157223 */
/* 0x002fc40000000013 */
/*04a0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*04b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*04c0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R12, [R6.64+0x20] ; /* 0x00002004060c7981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ FFMA R23, R18, R12, R21 ; /* 0x0000000c12177223 */
/* 0x004fc40000000015 */
/*04f0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0500*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0510*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*0520*/ LDG.E R14, [R6.64+0x24] ; /* 0x00002404060e7981 */
/* 0x000e24000c1e1900 */
/*0530*/ FFMA R19, R18, R14, R23 ; /* 0x0000000e12137223 */
/* 0x001fc40000000017 */
/*0540*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0550*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe8000c101904 */
/*0560*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0570*/ LDG.E R16, [R6.64+0x28] ; /* 0x0000280406107981 */
/* 0x000e64000c1e1900 */
/*0580*/ FFMA R21, R18, R16, R19 ; /* 0x0000001012157223 */
/* 0x002fc40000000013 */
/*0590*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*05a0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*05b0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*05c0*/ LDG.E R12, [R6.64+0x2c] ; /* 0x00002c04060c7981 */
/* 0x000ea4000c1e1900 */
/*05d0*/ FFMA R23, R18, R12, R21 ; /* 0x0000000c12177223 */
/* 0x004fc40000000015 */
/*05e0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*05f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0600*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R14, [R6.64+0x30] ; /* 0x00003004060e7981 */
/* 0x000ea4000c1e1900 */
/*0620*/ FFMA R25, R18, R14, R23 ; /* 0x0000000e12197223 */
/* 0x004fc40000000017 */
/*0630*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0640*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0650*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e28000c1e1900 */
/*0660*/ LDG.E R16, [R6.64+0x34] ; /* 0x0000340406107981 */
/* 0x000e24000c1e1900 */
/*0670*/ FFMA R21, R18, R16, R25 ; /* 0x0000001012157223 */
/* 0x001fc40000000019 */
/*0680*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0690*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*06a0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000e68000c1e1900 */
/*06b0*/ LDG.E R12, [R6.64+0x38] ; /* 0x00003804060c7981 */
/* 0x000e62000c1e1900 */
/*06c0*/ IADD3 R11, R11, -0x10, RZ ; /* 0xfffffff00b0b7810 */
/* 0x000fe20007ffe0ff */
/*06d0*/ FFMA R23, R18, R12, R21 ; /* 0x0000000c12177223 */
/* 0x002fc40000000015 */
/*06e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*06f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0700*/ LDG.E R13, [R6.64+0x3c] ; /* 0x00003c04060d7981 */
/* 0x000ee8000c1e1900 */
/*0710*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ee2000c1e1900 */
/*0720*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe20003f24270 */
/*0730*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0740*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fc60007ffe0ff */
/*0750*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0760*/ FFMA R15, R12, R13, R23 ; /* 0x0000000d0c0f7223 */
/* 0x008fe40000000017 */
/*0770*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0212 */
/*0780*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e4000c101904 */
/*0790*/ @P1 BRA 0x210 ; /* 0xfffffa7000001947 */
/* 0x000fea000383ffff */
/*07a0*/ ISETP.GT.AND P1, PT, R11, 0x4, PT ; /* 0x000000040b00780c */
/* 0x000fda0003f24270 */
/*07b0*/ @!P1 BRA 0xac0 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*07c0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*07d0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ee2000c1e1900 */
/*07e0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*07f0*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0800*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ee4000c1e1900 */
/*0810*/ FFMA R19, R14, R16, R15 ; /* 0x000000100e137223 */
/* 0x028fe4000000000f */
/*0820*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x004fc600078e020c */
/*0830*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0840*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*0860*/ FFMA R21, R16, R17, R19 ; /* 0x0000001110157223 */
/* 0x004fc40000000013 */
/*0870*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0880*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0890*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*08a0*/ LDG.E R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea4000c1e1900 */
/*08b0*/ FFMA R23, R18, R12, R21 ; /* 0x0000000c12177223 */
/* 0x004fc40000000015 */
/*08c0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*08d0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*08e0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*08f0*/ LDG.E R14, [R6.64+0xc] ; /* 0x00000c04060e7981 */
/* 0x000e24000c1e1900 */
/*0900*/ FFMA R19, R18, R14, R23 ; /* 0x0000000e12137223 */
/* 0x001fc40000000017 */
/*0910*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0920*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0930*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0940*/ LDG.E R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000e64000c1e1900 */
/*0950*/ FFMA R21, R18, R16, R19 ; /* 0x0000001012157223 */
/* 0x002fc40000000013 */
/*0960*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0970*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0980*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0990*/ LDG.E R12, [R6.64+0x14] ; /* 0x00001404060c7981 */
/* 0x000ea4000c1e1900 */
/*09a0*/ FFMA R23, R18, R12, R21 ; /* 0x0000000c12177223 */
/* 0x004fc40000000015 */
/*09b0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*09c0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*09d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R6.64+0x18] ; /* 0x00001804060e7981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ FFMA R25, R18, R14, R23 ; /* 0x0000000e12197223 */
/* 0x004fc40000000017 */
/*0a00*/ IMAD.WIDE R18, R0, 0x4, R12 ; /* 0x0000000400127825 */
/* 0x001fc600078e020c */
/*0a10*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0a20*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c04060f7981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea2000c1e1900 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a60*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0212 */
/*0a70*/ IADD3 R10, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fc40007ffe0ff */
/*0a80*/ IADD3 R11, R11, -0x8, RZ ; /* 0xfffffff80b0b7810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R15, R14, R15, R25 ; /* 0x0000000f0e0f7223 */
/* 0x004fca0000000019 */
/*0ab0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*0ac0*/ ISETP.NE.OR P0, PT, R11, RZ, P0 ; /* 0x000000ff0b00720c */
/* 0x000fda0000705670 */
/*0ad0*/ @!P0 BRA 0xcb0 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0af0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ee2000c1e1900 */
/*0b00*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0b10*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0b20*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ee4000c1e1900 */
/*0b30*/ FFMA R21, R14, R16, R15 ; /* 0x000000100e157223 */
/* 0x02efe4000000000f */
/*0b40*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0b50*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0b60*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*0b70*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*0b80*/ FFMA R23, R16, R17, R21 ; /* 0x0000001110177223 */
/* 0x004fc40000000015 */
/*0b90*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0ba0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e8000c101904 */
/*0bb0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ LDG.E R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea2000c1e1900 */
/*0bd0*/ IADD3 R11, R11, -0x4, RZ ; /* 0xfffffffc0b0b7810 */
/* 0x000fe20007ffe0ff */
/*0be0*/ FFMA R25, R18, R12, R23 ; /* 0x0000000c12197223 */
/* 0x004fc40000000017 */
/*0bf0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0c00*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0001e8000c101904 */
/*0c10*/ LDG.E R13, [R6.64+0xc] ; /* 0x00000c04060d7981 */
/* 0x000ea8000c1e1900 */
/*0c20*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*0c30*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f05270 */
/*0c40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0c50*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc60007ffe0ff */
/*0c60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0c70*/ FFMA R15, R12, R13, R25 ; /* 0x0000000d0c0f7223 */
/* 0x004fe40000000019 */
/*0c80*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0212 */
/*0c90*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e4000c101904 */
/*0ca0*/ @P0 BRA 0xae0 ; /* 0xfffffe3000000947 */
/* 0x001fea000383ffff */
/*0cb0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0cc0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cd0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000162000c1e1900 */
/*0ce0*/ IADD3 R7, R9, R10, RZ ; /* 0x0000000a09077210 */
/* 0x000fe20007ffe0ff */
/*0cf0*/ IMAD R5, R10, c[0x0][0x178], R5 ; /* 0x00005e000a057a24 */
/* 0x000fc800078e0205 */
/*0d00*/ IMAD.WIDE R6, R7, R8, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fc800078e0208 */
/*0d10*/ IMAD.WIDE R8, R5, R8, c[0x0][0x168] ; /* 0x00005a0005087625 */
/* 0x001fca00078e0208 */
/*0d20*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0010e8000c1e1900 */
/*0d30*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x0008e2000c1e1900 */
/*0d40*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*0d50*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0d60*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0d70*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x010fc80007f3e0ff */
/*0d80*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0d90*/ FFMA R11, R10, R5, R11 ; /* 0x000000050a0b7223 */
/* 0x028fca000000000b */
/*0da0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e2000c101904 */
/*0db0*/ @P0 BRA 0xd20 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0dc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0dd0*/ BRA 0xdd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9MatrixMulPfS_S_i
.globl _Z9MatrixMulPfS_S_i
.p2align 8
.type _Z9MatrixMulPfS_S_i,@function
_Z9MatrixMulPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max3_i32 v2, v0, v1, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_3
v_mul_lo_u32 v4, v1, s4
s_load_b64 s[2:3], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, v4, v0
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v6, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b32 s0, s4
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s0, 0
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v1, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v1, v7
global_store_b32 v[2:3], v6, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9MatrixMulPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9MatrixMulPfS_S_i, .Lfunc_end0-_Z9MatrixMulPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9MatrixMulPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9MatrixMulPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000aa272_00000000-6_Global.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9MatrixMulPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9MatrixMulPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9MatrixMulPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9MatrixMulPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z9MatrixMulPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9MatrixMulPfS_S_iPfS_S_i
.globl _Z9MatrixMulPfS_S_i
.type _Z9MatrixMulPfS_S_i, @function
_Z9MatrixMulPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9MatrixMulPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9MatrixMulPfS_S_i, .-_Z9MatrixMulPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
call cudaThreadSynchronize@PLT
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %r13d
leal 15(%rax), %eax
testl %r15d, %r15d
cmovns %r15d, %eax
sarl $4, %eax
movl %r15d, %edx
andl $15, %edx
cmpl $1, %edx
sbbl $-1, %eax
movl %eax, 48(%rsp)
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $16, 60(%rsp)
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movl %r15d, %r12d
imull %r15d, %r12d
sall $2, %r12d
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
testl %r15d, %r15d
jle .L13
movslq %r15d, %rdi
salq $2, %rdi
movl %r15d, %edx
salq $2, %rdx
movl $0, %ecx
movl %r15d, %r15d
negq %r15
leaq 0(,%r15,4), %rsi
.L14:
leaq (%rsi,%rdx), %rax
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
.L15:
movss %xmm0, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L15
addl $1, %ecx
addq %rdi, %rdx
cmpl %r13d, %ecx
jne .L14
.L13:
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 4(%rsp), %xmm0
divss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl %r13d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9MatrixMulPfS_S_iPfS_S_i
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z9MatrixMulPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9MatrixMulPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Global.hip"
.globl _Z24__device_stub__MatrixMulPfS_S_i # -- Begin function _Z24__device_stub__MatrixMulPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__MatrixMulPfS_S_i,@function
_Z24__device_stub__MatrixMulPfS_S_i: # @_Z24__device_stub__MatrixMulPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9MatrixMulPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__MatrixMulPfS_S_i, .Lfunc_end0-_Z24__device_stub__MatrixMulPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
callq hipDeviceSynchronize
movq 8(%rbx), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
addl $15, %eax
testl %r13d, %r13d
cmovnsl %r13d, %eax
sarl $4, %eax
movl %r13d, %ecx
andl $15, %ecx
cmpl $1, %ecx
sbbl $-1, %eax
movq %rax, %rbp
shlq $32, %rbp
orq %rax, %rbp
movl %r13d, %eax
imull %r13d, %eax
shll $2, %eax
movslq %eax, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq %rbx, %rdi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %r13d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r12d, %esi
leaq (%r15,%rsi,4), %rdx
leaq (%r14,%rsi,4), %rsi
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm0, (%rsi,%rdi,4)
movss %xmm0, (%rdx,%rdi,4)
incq %rdi
cmpq %rdi, %rax
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rcx
addl %r13d, %r12d
cmpq %rax, %rcx
jne .LBB1_2
.LBB1_5: # %._crit_edge62
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 48(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r13d, 44(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9MatrixMulPfS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movq %r12, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9MatrixMulPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9MatrixMulPfS_S_i,@object # @_Z9MatrixMulPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9MatrixMulPfS_S_i
.p2align 3, 0x0
_Z9MatrixMulPfS_S_i:
.quad _Z24__device_stub__MatrixMulPfS_S_i
.size _Z9MatrixMulPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9MatrixMulPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__MatrixMulPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9MatrixMulPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h> // for printf
// #include <math.h> // math lib already included
#define N 64 // constant, array len
#define TPB 32 // constant, threads per block
// converts int to evenly spaced floats
// ie) .1, .2, ..., .5, ..., .9
__device__
float scale(int i, int n)
{
return ((float) i) / (n - 1);
}
// Computes distance between 2 points on a line
__device__
float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
__global__
void distanceKernal(float *d_out, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const float x = scale(i, len);
d_out[i] = distance(x, ref);
printf("i = %2d: dist from %f to %f is %f.\n", i, ref, x, d_out[i]);
}
// Auto run main method
int main()
{
// reference point to be measured from
const float ref = 0.5f;
// declare pointeer to array of floats
float *d_out;
// allocate device memory tostore output array
cudaMalloc(&d_out, N * sizeof(float));
// launch kernel to copute and store distance values
distanceKernal<<<N/TPB, TPB>>>(d_out, ref, N);
// free memory
cudaFree(d_out);
return 0;
} | code for sm_80
Function : _Z14distanceKernalPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x16c] ; /* 0x00005b0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x150 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0040*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R1, R1, -0x20, RZ ; /* 0xffffffe001017810 */
/* 0x000fce0007ffe0ff */
/*0070*/ I2F R4, UR4 ; /* 0x0000000400047d06 */
/* 0x000e620008201400 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fce00078e0203 */
/*0090*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x002e300000001000 */
/*00a0*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000e620000201400 */
/*00b0*/ FFMA R2, -R4, R5, 1 ; /* 0x3f80000004027423 */
/* 0x001fc80000000105 */
/*00c0*/ FFMA R2, R5, R2, R5 ; /* 0x0000000205027223 */
/* 0x000fc60000000005 */
/*00d0*/ FCHK P0, R3, R4 ; /* 0x0000000403007302 */
/* 0x002e220000000000 */
/*00e0*/ FFMA R5, R3, R2, RZ ; /* 0x0000000203057223 */
/* 0x000fc800000000ff */
/*00f0*/ FFMA R6, -R4, R5, R3 ; /* 0x0000000504067223 */
/* 0x000fc80000000103 */
/*0100*/ FFMA R5, R2, R6, R5 ; /* 0x0000000602057223 */
/* 0x000fe20000000005 */
/*0110*/ @!P0 BRA 0x140 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0120*/ MOV R2, 0x140 ; /* 0x0000014000027802 */
/* 0x000fe40000000f00 */
/*0130*/ CALL.REL.NOINC 0x570 ; /* 0x0000043000007944 */
/* 0x000fea0003c00000 */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ FADD R2, -R5, c[0x0][0x168] ; /* 0x00005a0005027621 */
/* 0x000fe20000000100 */
/*0160*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f3e0ff */
/*0170*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0180*/ BSSY B0, 0x2a0 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0190*/ FMUL R3, R2, R2 ; /* 0x0000000202037220 */
/* 0x000fe40000400000 */
/*01a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe400008e06ff */
/*01b0*/ MUFU.RSQ R4, R3 ; /* 0x0000000300047308 */
/* 0x0000620000001400 */
/*01c0*/ IADD3 R2, R3, -0xd000000, RZ ; /* 0xf300000003027810 */
/* 0x000fc80007ffe0ff */
/*01d0*/ ISETP.GT.U32.AND P0, PT, R2, 0x727fffff, PT ; /* 0x727fffff0200780c */
/* 0x000fda0003f04070 */
/*01e0*/ @!P0 BRA 0x250 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*01f0*/ BSSY B1, 0x230 ; /* 0x0000003000017945 */
/* 0x003fe20003800000 */
/*0200*/ MOV R11, 0x220 ; /* 0x00000220000b7802 */
/* 0x000fe40000000f00 */
/*0210*/ CALL.REL.NOINC 0x400 ; /* 0x000001e000007944 */
/* 0x000fea0003c00000 */
/*0220*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0240*/ BRA 0x290 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0250*/ FMUL.FTZ R2, R3, R4 ; /* 0x0000000403027220 */
/* 0x003fe40000410000 */
/*0260*/ FMUL.FTZ R4, R4, 0.5 ; /* 0x3f00000004047820 */
/* 0x000fe40000410000 */
/*0270*/ FFMA R3, -R2, R2, R3 ; /* 0x0000000202037223 */
/* 0x000fc80000000103 */
/*0280*/ FFMA R2, R3, R4, R2 ; /* 0x0000000403027223 */
/* 0x000fe40000000002 */
/*0290*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02a0*/ F2F.F64.F32 R8, R5 ; /* 0x0000000500087310 */
/* 0x0001e20000201800 */
/*02b0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*02c0*/ MOV R3, 0x0 ; /* 0x0000000000037802 */
/* 0x000fe20000000f00 */
/*02d0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e20000100800 */
/*02e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*02f0*/ IMAD.WIDE R12, R0, R13, c[0x0][0x160] ; /* 0x00005800000c7625 */
/* 0x000fe200078e020d */
/*0300*/ LDC.64 R16, c[0x4][R3] ; /* 0x0100000003107b82 */
/* 0x0002a20000000a00 */
/*0310*/ F2F.F64.F32 R10, R2 ; /* 0x00000002000a7310 */
/* 0x000ee40000201800 */
/*0320*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x001fe200078e00ff */
/*0330*/ STG.E [R12.64], R2 ; /* 0x000000020c007986 */
/* 0x0003ea000c101904 */
/*0340*/ F2F.F64.F32 R14, c[0x0][0x168] ; /* 0x00005a00000e7b10 */
/* 0x000e220000201800 */
/*0350*/ STL.128 [R1+0x10], R8 ; /* 0x0000100801007387 */
/* 0x0083e80000100c00 */
/*0360*/ STL.64 [R1+0x8], R14 ; /* 0x0000080e01007387 */
/* 0x0013e40000100a00 */
/*0370*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x006fe20000000000 */
/*0380*/ MOV R9, 0x3f0 ; /* 0x000003f000097802 */
/* 0x000fc40000000f00 */
/*0390*/ MOV R20, 0x370 ; /* 0x0000037000147802 */
/* 0x000fe40000000f00 */
/*03a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*03b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*03c0*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*03d0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*03e0*/ CALL.ABS.NOINC R16 ; /* 0x0000000010007343 */
/* 0x000fea0003c00000 */
/*03f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0400*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*0410*/ @!P0 BRA 0x530 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0420*/ FSETP.GEU.FTZ.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fe20003f1e000 */
/*0430*/ IMAD.MOV.U32 R2, RZ, RZ, R3 ; /* 0x000000ffff027224 */
/* 0x000fd800078e0003 */
/*0440*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff038424 */
/* 0x000fe200078e00ff */
/*0450*/ @!P0 BRA 0x530 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0460*/ FSETP.GTU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1c200 */
/*0470*/ @P0 FADD.FTZ R3, R2, 1 ; /* 0x3f80000002030421 */
/* 0x000fe20000010000 */
/*0480*/ @P0 BRA 0x530 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0490*/ FSETP.NEU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1d200 */
/*04a0*/ @P0 FFMA R4, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002040823 */
/* 0x000fc800000000ff */
/*04b0*/ @P0 MUFU.RSQ R3, R4 ; /* 0x0000000400030308 */
/* 0x000e240000001400 */
/*04c0*/ @P0 FMUL.FTZ R9, R4, R3 ; /* 0x0000000304090220 */
/* 0x001fe40000410000 */
/*04d0*/ @P0 FMUL.FTZ R10, R3, 0.5 ; /* 0x3f000000030a0820 */
/* 0x000fe40000410000 */
/*04e0*/ @P0 FADD.FTZ R8, -R9.reuse, -RZ ; /* 0x800000ff09080221 */
/* 0x040fe40000010100 */
/*04f0*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, R2 ; /* 0x000000ffff038224 */
/* 0x000fe400078e0002 */
/*0500*/ @P0 FFMA R8, R9, R8, R4 ; /* 0x0000000809080223 */
/* 0x000fc80000000004 */
/*0510*/ @P0 FFMA R8, R8, R10, R9 ; /* 0x0000000a08080223 */
/* 0x000fc80000000009 */
/*0520*/ @P0 FMUL.FTZ R3, R8, 2.3283064365386962891e-10 ; /* 0x2f80000008030820 */
/* 0x000fc80000410000 */
/*0530*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0003 */
/*0540*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000b */
/*0550*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0560*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffa9002007950 */
/* 0x000fea0003c3ffff */
/*0570*/ SHF.R.U32.HI R6, RZ, 0x17, R4.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011604 */
/*0580*/ BSSY B1, 0xbd0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0590*/ SHF.R.U32.HI R5, RZ, 0x17, R3.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011603 */
/*05a0*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*05b0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*05c0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*05d0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*05e0*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*05f0*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fc40007ffe0ff */
/*0600*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0610*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0620*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0630*/ @!P0 BRA 0x7b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0640*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1c200 */
/*0650*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*0660*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0670*/ @P0 BRA 0xbb0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0680*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0690*/ @!P0 BRA 0xb90 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*06a0*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*06b0*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*06c0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*06d0*/ @!P1 BRA !P2, 0xb90 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*06e0*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*06f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0700*/ @P1 BRA 0xb70 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0710*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0720*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0730*/ @P0 BRA 0xb40 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0740*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0750*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0760*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0770*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0780*/ @!P0 FFMA R7, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003078823 */
/* 0x000fe400000000ff */
/*0790*/ @!P1 FFMA R8, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004089823 */
/* 0x000fe200000000ff */
/*07a0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ LEA R3, R6, 0xc0800000, 0x17 ; /* 0xc080000006037811 */
/* 0x000fe200078eb8ff */
/*07c0*/ BSSY B2, 0xb30 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*07d0*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*07e0*/ IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a03 */
/*07f0*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*0800*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*0810*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x000e220000001000 */
/*0820*/ FADD.FTZ R4, -R8, -RZ ; /* 0x800000ff08047221 */
/* 0x000fe40000010100 */
/*0830*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*0840*/ FFMA R10, R3, R4, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000004 */
/*0850*/ FFMA R12, R3, R10, R3 ; /* 0x0000000a030c7223 */
/* 0x000fc80000000003 */
/*0860*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*0870*/ FFMA R10, R4, R3, R7 ; /* 0x00000003040a7223 */
/* 0x000fc80000000007 */
/*0880*/ FFMA R11, R12, R10, R3 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000003 */
/*0890*/ FFMA R7, R4, R11, R7 ; /* 0x0000000b04077223 */
/* 0x000fc80000000007 */
/*08a0*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*08b0*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*08c0*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*08d0*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*08e0*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*08f0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0900*/ @!P0 BRA 0xb10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0910*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0920*/ @P0 BRA 0xae0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0930*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0940*/ @P0 BRA 0xb20 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0950*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*0960*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0970*/ @!P0 BRA 0xb20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0980*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*0990*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*09a0*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*09b0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*09c0*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*09d0*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*09e0*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*0a00*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0a10*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0a20*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*0a30*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0a40*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0a50*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*0a60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0a70*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*0a80*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0a90*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0aa0*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0ab0*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0ac0*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0ad0*/ BRA 0xb20 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0ae0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0af0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0b00*/ BRA 0xb20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b10*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0b20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b30*/ BRA 0xbc0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0b40*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*0b50*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0b60*/ BRA 0xbc0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b70*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*0b80*/ BRA 0xbc0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0b90*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0ba0*/ BRA 0xbc0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ FADD.FTZ R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x000fe40000010000 */
/*0bc0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0bd0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0003 */
/*0be0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0bf0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff40002007950 */
/* 0x000fea0003c3ffff */
/*0c00*/ BRA 0xc00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h> // for printf
// #include <math.h> // math lib already included
#define N 64 // constant, array len
#define TPB 32 // constant, threads per block
// converts int to evenly spaced floats
// ie) .1, .2, ..., .5, ..., .9
__device__
float scale(int i, int n)
{
return ((float) i) / (n - 1);
}
// Computes distance between 2 points on a line
__device__
float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
__global__
void distanceKernal(float *d_out, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const float x = scale(i, len);
d_out[i] = distance(x, ref);
printf("i = %2d: dist from %f to %f is %f.\n", i, ref, x, d_out[i]);
}
// Auto run main method
int main()
{
// reference point to be measured from
const float ref = 0.5f;
// declare pointeer to array of floats
float *d_out;
// allocate device memory tostore output array
cudaMalloc(&d_out, N * sizeof(float));
// launch kernel to copute and store distance values
distanceKernal<<<N/TPB, TPB>>>(d_out, ref, N);
// free memory
cudaFree(d_out);
return 0;
} | .file "tmpxft_001903c0_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5scaleii
.type _Z5scaleii, @function
_Z5scaleii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z5scaleii, .-_Z5scaleii
.globl _Z8distanceff
.type _Z8distanceff, @function
_Z8distanceff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8distanceff, .-_Z8distanceff
.globl _Z36__device_stub__Z14distanceKernalPffiPffi
.type _Z36__device_stub__Z14distanceKernalPffiPffi, @function
_Z36__device_stub__Z14distanceKernalPffiPffi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14distanceKernalPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z14distanceKernalPffiPffi, .-_Z36__device_stub__Z14distanceKernalPffiPffi
.globl _Z14distanceKernalPffi
.type _Z14distanceKernalPffi, @function
_Z14distanceKernalPffi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14distanceKernalPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14distanceKernalPffi, .-_Z14distanceKernalPffi
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $64, %esi
movss .LC0(%rip), %xmm0
movq 8(%rsp), %rdi
call _Z36__device_stub__Z14distanceKernalPffiPffi
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z14distanceKernalPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernalPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h> // for printf
// #include <math.h> // math lib already included
#define N 64 // constant, array len
#define TPB 32 // constant, threads per block
// converts int to evenly spaced floats
// ie) .1, .2, ..., .5, ..., .9
__device__
float scale(int i, int n)
{
return ((float) i) / (n - 1);
}
// Computes distance between 2 points on a line
__device__
float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
__global__
void distanceKernal(float *d_out, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const float x = scale(i, len);
d_out[i] = distance(x, ref);
printf("i = %2d: dist from %f to %f is %f.\n", i, ref, x, d_out[i]);
}
// Auto run main method
int main()
{
// reference point to be measured from
const float ref = 0.5f;
// declare pointeer to array of floats
float *d_out;
// allocate device memory tostore output array
cudaMalloc(&d_out, N * sizeof(float));
// launch kernel to copute and store distance values
distanceKernal<<<N/TPB, TPB>>>(d_out, ref, N);
// free memory
cudaFree(d_out);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h> // for printf
// #include <math.h> // math lib already included
#define N 64 // constant, array len
#define TPB 32 // constant, threads per block
// converts int to evenly spaced floats
// ie) .1, .2, ..., .5, ..., .9
__device__
float scale(int i, int n)
{
return ((float) i) / (n - 1);
}
// Computes distance between 2 points on a line
__device__
float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
__global__
void distanceKernal(float *d_out, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const float x = scale(i, len);
d_out[i] = distance(x, ref);
printf("i = %2d: dist from %f to %f is %f.\n", i, ref, x, d_out[i]);
}
// Auto run main method
int main()
{
// reference point to be measured from
const float ref = 0.5f;
// declare pointeer to array of floats
float *d_out;
// allocate device memory tostore output array
hipMalloc(&d_out, N * sizeof(float));
// launch kernel to copute and store distance values
distanceKernal<<<N/TPB, TPB>>>(d_out, ref, N);
// free memory
hipFree(d_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h> // for printf
// #include <math.h> // math lib already included
#define N 64 // constant, array len
#define TPB 32 // constant, threads per block
// converts int to evenly spaced floats
// ie) .1, .2, ..., .5, ..., .9
__device__
float scale(int i, int n)
{
return ((float) i) / (n - 1);
}
// Computes distance between 2 points on a line
__device__
float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
__global__
void distanceKernal(float *d_out, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const float x = scale(i, len);
d_out[i] = distance(x, ref);
printf("i = %2d: dist from %f to %f is %f.\n", i, ref, x, d_out[i]);
}
// Auto run main method
int main()
{
// reference point to be measured from
const float ref = 0.5f;
// declare pointeer to array of floats
float *d_out;
// allocate device memory tostore output array
hipMalloc(&d_out, N * sizeof(float));
// launch kernel to copute and store distance values
distanceKernal<<<N/TPB, TPB>>>(d_out, ref, N);
// free memory
hipFree(d_out);
return 0;
} | .text
.file "kernel.hip"
.globl _Z29__device_stub__distanceKernalPffi # -- Begin function _Z29__device_stub__distanceKernalPffi
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernalPffi,@function
_Z29__device_stub__distanceKernalPffi: # @_Z29__device_stub__distanceKernalPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14distanceKernalPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__distanceKernalPffi, .Lfunc_end0-_Z29__device_stub__distanceKernalPffi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
leaq 16(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $1056964608, 12(%rsp) # imm = 0x3F000000
movl $64, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernalPffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernalPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernalPffi,@object # @_Z14distanceKernalPffi
.section .rodata,"a",@progbits
.globl _Z14distanceKernalPffi
.p2align 3, 0x0
_Z14distanceKernalPffi:
.quad _Z29__device_stub__distanceKernalPffi
.size _Z14distanceKernalPffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14distanceKernalPffi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernalPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernalPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001903c0_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5scaleii
.type _Z5scaleii, @function
_Z5scaleii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z5scaleii, .-_Z5scaleii
.globl _Z8distanceff
.type _Z8distanceff, @function
_Z8distanceff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8distanceff, .-_Z8distanceff
.globl _Z36__device_stub__Z14distanceKernalPffiPffi
.type _Z36__device_stub__Z14distanceKernalPffiPffi, @function
_Z36__device_stub__Z14distanceKernalPffiPffi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14distanceKernalPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z14distanceKernalPffiPffi, .-_Z36__device_stub__Z14distanceKernalPffiPffi
.globl _Z14distanceKernalPffi
.type _Z14distanceKernalPffi, @function
_Z14distanceKernalPffi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14distanceKernalPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14distanceKernalPffi, .-_Z14distanceKernalPffi
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $64, %esi
movss .LC0(%rip), %xmm0
movq 8(%rsp), %rdi
call _Z36__device_stub__Z14distanceKernalPffiPffi
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z14distanceKernalPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernalPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z29__device_stub__distanceKernalPffi # -- Begin function _Z29__device_stub__distanceKernalPffi
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernalPffi,@function
_Z29__device_stub__distanceKernalPffi: # @_Z29__device_stub__distanceKernalPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14distanceKernalPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__distanceKernalPffi, .Lfunc_end0-_Z29__device_stub__distanceKernalPffi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
leaq 16(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $1056964608, 12(%rsp) # imm = 0x3F000000
movl $64, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernalPffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernalPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernalPffi,@object # @_Z14distanceKernalPffi
.section .rodata,"a",@progbits
.globl _Z14distanceKernalPffi
.p2align 3, 0x0
_Z14distanceKernalPffi:
.quad _Z29__device_stub__distanceKernalPffi
.size _Z14distanceKernalPffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14distanceKernalPffi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernalPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernalPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ int translate_idx_inv(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy, int off_time, int off_x, int off_y)
{
/* d1 = channel
d2 = time
d3, d4 = height, width
*/
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
t = t*scale_factor_t+off_time;
w = w*scale_factor_xy+off_x;
z = z*scale_factor_xy+off_y;
d2 *= scale_factor_t;
d3 *= scale_factor_xy;
d4 *= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__device__ int translate_idx(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy)
{
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor_xy;
z = z/scale_factor_xy;
t = t/scale_factor_t;
d2 /= scale_factor_t;
d3 /= scale_factor_xy;
d4 /= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__global__ void downscale(float *gradInput_data, float *gradOutput_data, long no_elements, int scale_factor_t, int scale_factor_xy, int d1, int d2, int d3, int d4)
{
// output offset:
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
for (int i=0; i < scale_factor_t; i++){
for(int j=0; j < scale_factor_xy; j++){
for(int k=0; k < scale_factor_xy; k++){
int ipidx = translate_idx_inv(ii, d1, d2, d3, d4, scale_factor_t, scale_factor_xy, i, j, k);
gradInput_data[ii] += gradOutput_data[ipidx];
}
}
}
} | code for sm_80
Function : _Z9downscalePfS_liiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fc6000f8e023f */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002600 */
/*0070*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R2, UR4, R5 ; /* 0x0000000402037c24 */
/* 0x002fe4000f8e0205 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fc600078e00ff */
/*00c0*/ IADD3 R0, P2, R0, R3, RZ ; /* 0x0000000300007210 */
/* 0x000fe40007f5e0ff */
/*00d0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f06270 */
/*00e0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f26070 */
/*00f0*/ IADD3.X R3, RZ, RZ, RZ, P2, !PT ; /* 0x000000ffff037210 */
/* 0x000fc800017fe4ff */
/*0100*/ ISETP.GE.OR.EX P0, PT, R3, c[0x0][0x174], !P0, P1 ; /* 0x00005d0003007a0c */
/* 0x000fda0004706710 */
/*0110*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff047624 */
/* 0x000fca00078e00ff */
/*0130*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*0140*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, R4, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x000fe20007ffe0ff */
/*0160*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0170*/ LEA R2, P1, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fe400078210ff */
/*0180*/ LOP3.LUT R18, R4.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304127812 */
/* 0x040fe200078ec0ff */
/*0190*/ IMAD R4, R4, c[0x0][0x18c], RZ ; /* 0x0000630004047a24 */
/* 0x000fe200078e02ff */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe20003f06070 */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*01c0*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P1 ; /* 0x0000590000037a11 */
/* 0x000fe400008f1403 */
/*01d0*/ IADD3 R6, R18, -c[0x0][0x17c], RZ ; /* 0x80005f0012067a10 */
/* 0x000fc40007ffe0ff */
/*01e0*/ IABS R14, c[0x0][0x18c] ; /* 0x00006300000e7a13 */
/* 0x000fe40000000000 */
/*01f0*/ IABS R7, c[0x0][0x188] ; /* 0x0000620000077a13 */
/* 0x000fc40000000000 */
/*0200*/ I2F.RP R10, R14 ; /* 0x0000000e000a7306 */
/* 0x001e300000209400 */
/*0210*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x001e240000001000 */
/*0220*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x001fc40007ffe0ff */
/*0230*/ IABS R10, R0 ; /* 0x00000000000a7213 */
/* 0x000fc80000000000 */
/*0240*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x002064000021f000 */
/*0250*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe200078e00ff */
/*0260*/ IADD3 R11, RZ, -R9, RZ ; /* 0x80000009ff0b7210 */
/* 0x00afca0007ffe0ff */
/*0270*/ IMAD R11, R11, R14, RZ ; /* 0x0000000e0b0b7224 */
/* 0x000fc800078e02ff */
/*0280*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fe400078e0008 */
/*0290*/ I2F.RP R11, R7 ; /* 0x00000007000b7306 */
/* 0x000e280000209400 */
/*02a0*/ IMAD.HI.U32 R8, R9, R10, RZ ; /* 0x0000000a09087227 */
/* 0x000fc800078e00ff */
/*02b0*/ IMAD.MOV R9, RZ, RZ, -R8 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0a08 */
/*02c0*/ IMAD R9, R14, R9, R10 ; /* 0x000000090e097224 */
/* 0x000fe200078e020a */
/*02d0*/ LOP3.LUT R10, R0, c[0x0][0x18c], RZ, 0x3c, !PT ; /* 0x00006300000a7a12 */
/* 0x000fe200078e3cff */
/*02e0*/ MUFU.RCP R11, R11 ; /* 0x0000000b000b7308 */
/* 0x001e260000001000 */
/*02f0*/ ISETP.GT.U32.AND P3, PT, R14, R9, PT ; /* 0x000000090e00720c */
/* 0x000fe40003f64070 */
/*0300*/ ISETP.GE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f46270 */
/*0310*/ @!P3 IADD3 R9, R9, -R14.reuse, RZ ; /* 0x8000000e0909b210 */
/* 0x080fe40007ffe0ff */
/*0320*/ IADD3 R12, R11, 0xffffffe, RZ ; /* 0x0ffffffe0b0c7810 */
/* 0x001fe40007ffe0ff */
/*0330*/ ISETP.GE.U32.AND P1, PT, R9, R14, PT ; /* 0x0000000e0900720c */
/* 0x000fe40003f26070 */
/*0340*/ F2I.FTZ.U32.TRUNC.NTZ R9, R12 ; /* 0x0000000c00097305 */
/* 0x000e22000021f000 */
/*0350*/ @!P3 IADD3 R8, R8, 0x1, RZ ; /* 0x000000010808b810 */
/* 0x000fe40007ffe0ff */
/*0360*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x18c], PT ; /* 0x00006300ff007a0c */
/* 0x000fd00003f65270 */
/*0370*/ @P1 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108081810 */
/* 0x000fca0007ffe0ff */
/*0380*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0008 */
/*0390*/ IADD3 R8, RZ, -R9, RZ ; /* 0x80000009ff087210 */
/* 0x001fc60007ffe0ff */
/*03a0*/ @!P2 IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0ea224 */
/* 0x000fe200078e0a0e */
/*03b0*/ @!P3 LOP3.LUT R14, RZ, c[0x0][0x18c], RZ, 0x33, !PT ; /* 0x00006300ff0eba12 */
/* 0x000fe200078e33ff */
/*03c0*/ IMAD R11, R8, R7, RZ ; /* 0x00000007080b7224 */
/* 0x000fe200078e02ff */
/*03d0*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe400000001ff */
/*03e0*/ IABS R10, R14 ; /* 0x0000000e000a7213 */
/* 0x000fd00000000000 */
/*03f0*/ IMAD.HI.U32 R8, R9, R11, R8 ; /* 0x0000000b09087227 */
/* 0x000fc800078e0008 */
/*0400*/ IMAD.MOV R11, RZ, RZ, -R14 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0a0e */
/*0410*/ IMAD.HI.U32 R8, R8, R10, RZ ; /* 0x0000000a08087227 */
/* 0x000fc800078e00ff */
/*0420*/ IMAD.MOV R9, RZ, RZ, -R8 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0a08 */
/*0430*/ IMAD R10, R7, R9, R10 ; /* 0x00000009070a7224 */
/* 0x000fca00078e020a */
/*0440*/ ISETP.GT.U32.AND P3, PT, R7, R10, PT ; /* 0x0000000a0700720c */
/* 0x000fda0003f64070 */
/*0450*/ @!P3 IADD3 R10, R10, -R7.reuse, RZ ; /* 0x800000070a0ab210 */
/* 0x080fe40007ffe0ff */
/*0460*/ @!P3 IADD3 R8, R8, 0x1, RZ ; /* 0x000000010808b810 */
/* 0x000fe40007ffe0ff */
/*0470*/ ISETP.GE.U32.AND P1, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fe40003f26070 */
/*0480*/ LOP3.LUT R7, R14, c[0x0][0x188], RZ, 0x3c, !PT ; /* 0x000062000e077a12 */
/* 0x000fe400078e3cff */
/*0490*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x000fe40003f65270 */
/*04a0*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fce0003f46270 */
/*04b0*/ @P1 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108081810 */
/* 0x000fcc0007ffe0ff */
/*04c0*/ @!P2 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e0a08 */
/*04d0*/ @!P3 LOP3.LUT R8, RZ, c[0x0][0x188], RZ, 0x33, !PT ; /* 0x00006200ff08ba12 */
/* 0x000fc800078e33ff */
/*04e0*/ IADD3 R7, -R8.reuse, RZ, RZ ; /* 0x000000ff08077210 */
/* 0x040fe20007ffe1ff */
/*04f0*/ IMAD R9, R8, c[0x0][0x178], R5 ; /* 0x00005e0008097a24 */
/* 0x000fc800078e0205 */
/*0500*/ IMAD R8, R7, c[0x0][0x188], R14 ; /* 0x0000620007087a24 */
/* 0x000fe400078e020e */
/*0510*/ IMAD R7, R11, c[0x0][0x18c], R0 ; /* 0x000063000b077a24 */
/* 0x000fe400078e0200 */
/*0520*/ IMAD R8, R9, c[0x0][0x188], R8 ; /* 0x0000620009087a24 */
/* 0x000fe200078e0208 */
/*0530*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fc60000000f00 */
/*0540*/ IMAD R10, R4, R8, R7 ; /* 0x00000008040a7224 */
/* 0x004fe400078e0207 */
/*0550*/ ISETP.NE.AND P2, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe20003f45270 */
/*0560*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x008fe200078e00ff */
/*0570*/ @!P0 BRA 0x710 ; /* 0x0000019000008947 */
/* 0x007ff60003800000 */
/*0580*/ LDG.E R23, [R2.64] ; /* 0x0000000402177981 */
/* 0x000162000c1e1900 */
/*0590*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*05a0*/ IMAD R19, R10, c[0x0][0x17c], R9 ; /* 0x00005f000a137a24 */
/* 0x000fe400078e0209 */
/*05b0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x4 ; /* 0x00000004ff0c7424 */
/* 0x000fc800078e00ff */
/*05c0*/ IMAD.WIDE R12, R19, R12, c[0x0][0x168] ; /* 0x00005a00130c7625 */
/* 0x000fca00078e020c */
/*05d0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea4000c1e1900 */
/*05e0*/ FADD R25, R14, R23 ; /* 0x000000170e197221 */
/* 0x026fe40000000000 */
/*05f0*/ IMAD.WIDE R14, R4, 0x4, R12 ; /* 0x00000004040e7825 */
/* 0x000fc600078e020c */
/*0600*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0610*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea4000c1e1900 */
/*0620*/ FADD R27, R25, R16 ; /* 0x00000010191b7221 */
/* 0x004fe40000000000 */
/*0630*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fc600078e020e */
/*0640*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0003e8000c101904 */
/*0650*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea2000c1e1900 */
/*0660*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FADD R29, R27, R20 ; /* 0x000000141b1d7221 */
/* 0x004fe40000000000 */
/*0680*/ IMAD.WIDE R20, R4, 0x4, R16 ; /* 0x0000000404147825 */
/* 0x000fc600078e0210 */
/*0690*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x0003e8000c101904 */
/*06a0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea2000c1e1900 */
/*06b0*/ IADD3 R12, R6, R11, RZ ; /* 0x0000000b060c7210 */
/* 0x000fe20007ffe0ff */
/*06c0*/ IMAD R19, R4, 0x4, R19 ; /* 0x0000000404137824 */
/* 0x000fc600078e0213 */
/*06d0*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f25270 */
/*06e0*/ FADD R23, R29, R20 ; /* 0x000000141d177221 */
/* 0x004fca0000000000 */
/*06f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003ee000c101904 */
/*0700*/ @P1 BRA 0x5b0 ; /* 0xfffffea000001947 */
/* 0x000fea000383ffff */
/*0710*/ @!P2 BRA 0x8d0 ; /* 0x000001b00000a947 */
/* 0x000fea0003800000 */
/*0720*/ IMAD R14, R8, c[0x0][0x17c], R11 ; /* 0x00005f00080e7a24 */
/* 0x000fe200078e020b */
/*0730*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fe20000000f00 */
/*0740*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea4000c1e1900 */
/*0750*/ IMAD R12, R14, c[0x0][0x18c], R7 ; /* 0x000063000e0c7a24 */
/* 0x000fc800078e0207 */
/*0760*/ IMAD R12, R12, c[0x0][0x17c], R9 ; /* 0x00005f000c0c7a24 */
/* 0x000fc800078e0209 */
/*0770*/ IMAD.WIDE R12, R12, R11, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fcc00078e020b */
/*0780*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1900 */
/*0790*/ ISETP.NE.AND P1, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fe20003f25270 */
/*07a0*/ FADD R15, R12, R15 ; /* 0x0000000f0c0f7221 */
/* 0x004fca0000000000 */
/*07b0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005ee000c101904 */
/*07c0*/ @!P1 BRA 0x8d0 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*07d0*/ IADD3 R12, R14, 0x1, RZ ; /* 0x000000010e0c7810 */
/* 0x000fca0007ffe0ff */
/*07e0*/ IMAD R12, R12, c[0x0][0x18c], R7 ; /* 0x000063000c0c7a24 */
/* 0x000fc800078e0207 */
/*07f0*/ IMAD R12, R12, c[0x0][0x17c], R9 ; /* 0x00005f000c0c7a24 */
/* 0x000fc800078e0209 */
/*0800*/ IMAD.WIDE R12, R12, R11, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fcc00078e020b */
/*0810*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1900 */
/*0820*/ ISETP.NE.AND P1, PT, R18, 0x2, PT ; /* 0x000000021200780c */
/* 0x000fe20003f25270 */
/*0830*/ FADD R15, R15, R12 ; /* 0x0000000c0f0f7221 */
/* 0x00cfca0000000000 */
/*0840*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005ee000c101904 */
/*0850*/ @!P1 BRA 0x8d0 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0860*/ IADD3 R12, R14, 0x2, RZ ; /* 0x000000020e0c7810 */
/* 0x000fca0007ffe0ff */
/*0870*/ IMAD R12, R12, c[0x0][0x18c], R7 ; /* 0x000063000c0c7a24 */
/* 0x000fc800078e0207 */
/*0880*/ IMAD R12, R12, c[0x0][0x17c], R9 ; /* 0x00005f000c0c7a24 */
/* 0x000fc800078e0209 */
/*0890*/ IMAD.WIDE R12, R12, R11, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fcc00078e020b */
/*08a0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee4000c1e1900 */
/*08b0*/ FADD R11, R15, R12 ; /* 0x0000000c0f0b7221 */
/* 0x008fca0000000000 */
/*08c0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0007e4000c101904 */
/*08d0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc80007ffe0ff */
/*08e0*/ ISETP.GE.AND P1, PT, R9, c[0x0][0x17c], PT ; /* 0x00005f0009007a0c */
/* 0x000fda0003f26270 */
/*08f0*/ @!P1 BRA 0x550 ; /* 0xfffffc5000009947 */
/* 0x000fea000383ffff */
/*0900*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fc80007ffe0ff */
/*0910*/ ISETP.GE.AND P1, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fda0003f26270 */
/*0920*/ @!P1 BRA 0x1e0 ; /* 0xfffff8b000009947 */
/* 0x000fea000383ffff */
/*0930*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0940*/ BRA 0x940; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ int translate_idx_inv(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy, int off_time, int off_x, int off_y)
{
/* d1 = channel
d2 = time
d3, d4 = height, width
*/
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
t = t*scale_factor_t+off_time;
w = w*scale_factor_xy+off_x;
z = z*scale_factor_xy+off_y;
d2 *= scale_factor_t;
d3 *= scale_factor_xy;
d4 *= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__device__ int translate_idx(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy)
{
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor_xy;
z = z/scale_factor_xy;
t = t/scale_factor_t;
d2 /= scale_factor_t;
d3 /= scale_factor_xy;
d4 /= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__global__ void downscale(float *gradInput_data, float *gradOutput_data, long no_elements, int scale_factor_t, int scale_factor_xy, int d1, int d2, int d3, int d4)
{
// output offset:
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
for (int i=0; i < scale_factor_t; i++){
for(int j=0; j < scale_factor_xy; j++){
for(int k=0; k < scale_factor_xy; k++){
int ipidx = translate_idx_inv(ii, d1, d2, d3, d4, scale_factor_t, scale_factor_xy, i, j, k);
gradInput_data[ii] += gradOutput_data[ipidx];
}
}
}
} | .file "tmpxft_0011c225_00000000-6_downscale.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17translate_idx_inviiiiiiiiii
.type _Z17translate_idx_inviiiiiiiiii, @function
_Z17translate_idx_inviiiiiiiiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z17translate_idx_inviiiiiiiiii, .-_Z17translate_idx_inviiiiiiiiii
.globl _Z13translate_idxiiiiiii
.type _Z13translate_idxiiiiiii, @function
_Z13translate_idxiiiiiii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z13translate_idxiiiiiii, .-_Z13translate_idxiiiiiii
.globl _Z37__device_stub__Z9downscalePfS_liiiiiiPfS_liiiiii
.type _Z37__device_stub__Z9downscalePfS_liiiiiiPfS_liiiiii, @function
_Z37__device_stub__Z9downscalePfS_liiiiiiPfS_liiiiii:
.LFB2053:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9downscalePfS_liiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z37__device_stub__Z9downscalePfS_liiiiiiPfS_liiiiii, .-_Z37__device_stub__Z9downscalePfS_liiiiiiPfS_liiiiii
.globl _Z9downscalePfS_liiiiii
.type _Z9downscalePfS_liiiiii, @function
_Z9downscalePfS_liiiiii:
.LFB2054:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z37__device_stub__Z9downscalePfS_liiiiiiPfS_liiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z9downscalePfS_liiiiii, .-_Z9downscalePfS_liiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9downscalePfS_liiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9downscalePfS_liiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ int translate_idx_inv(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy, int off_time, int off_x, int off_y)
{
/* d1 = channel
d2 = time
d3, d4 = height, width
*/
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
t = t*scale_factor_t+off_time;
w = w*scale_factor_xy+off_x;
z = z*scale_factor_xy+off_y;
d2 *= scale_factor_t;
d3 *= scale_factor_xy;
d4 *= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__device__ int translate_idx(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy)
{
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor_xy;
z = z/scale_factor_xy;
t = t/scale_factor_t;
d2 /= scale_factor_t;
d3 /= scale_factor_xy;
d4 /= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__global__ void downscale(float *gradInput_data, float *gradOutput_data, long no_elements, int scale_factor_t, int scale_factor_xy, int d1, int d2, int d3, int d4)
{
// output offset:
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
for (int i=0; i < scale_factor_t; i++){
for(int j=0; j < scale_factor_xy; j++){
for(int k=0; k < scale_factor_xy; k++){
int ipidx = translate_idx_inv(ii, d1, d2, d3, d4, scale_factor_t, scale_factor_xy, i, j, k);
gradInput_data[ii] += gradOutput_data[ipidx];
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int translate_idx_inv(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy, int off_time, int off_x, int off_y)
{
/* d1 = channel
d2 = time
d3, d4 = height, width
*/
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
t = t*scale_factor_t+off_time;
w = w*scale_factor_xy+off_x;
z = z*scale_factor_xy+off_y;
d2 *= scale_factor_t;
d3 *= scale_factor_xy;
d4 *= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__device__ int translate_idx(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy)
{
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor_xy;
z = z/scale_factor_xy;
t = t/scale_factor_t;
d2 /= scale_factor_t;
d3 /= scale_factor_xy;
d4 /= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__global__ void downscale(float *gradInput_data, float *gradOutput_data, long no_elements, int scale_factor_t, int scale_factor_xy, int d1, int d2, int d3, int d4)
{
// output offset:
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
for (int i=0; i < scale_factor_t; i++){
for(int j=0; j < scale_factor_xy; j++){
for(int k=0; k < scale_factor_xy; k++){
int ipidx = translate_idx_inv(ii, d1, d2, d3, d4, scale_factor_t, scale_factor_xy, i, j, k);
gradInput_data[ii] += gradOutput_data[ipidx];
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int translate_idx_inv(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy, int off_time, int off_x, int off_y)
{
/* d1 = channel
d2 = time
d3, d4 = height, width
*/
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
t = t*scale_factor_t+off_time;
w = w*scale_factor_xy+off_x;
z = z*scale_factor_xy+off_y;
d2 *= scale_factor_t;
d3 *= scale_factor_xy;
d4 *= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__device__ int translate_idx(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy)
{
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor_xy;
z = z/scale_factor_xy;
t = t/scale_factor_t;
d2 /= scale_factor_t;
d3 /= scale_factor_xy;
d4 /= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__global__ void downscale(float *gradInput_data, float *gradOutput_data, long no_elements, int scale_factor_t, int scale_factor_xy, int d1, int d2, int d3, int d4)
{
// output offset:
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
for (int i=0; i < scale_factor_t; i++){
for(int j=0; j < scale_factor_xy; j++){
for(int k=0; k < scale_factor_xy; k++){
int ipidx = translate_idx_inv(ii, d1, d2, d3, d4, scale_factor_t, scale_factor_xy, i, j, k);
gradInput_data[ii] += gradOutput_data[ipidx];
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9downscalePfS_liiiiii
.globl _Z9downscalePfS_liiiiii
.p2align 8
.type _Z9downscalePfS_liiiiii,@function
_Z9downscalePfS_liiiiii:
s_clause 0x3
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s5, s[0:1], 0x30
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s4, 0xffff
s_mul_i32 s5, s5, s15
s_lshr_b32 s4, s4, 16
s_mul_i32 s5, s5, s7
v_mad_u64_u32 v[2:3], null, s14, s7, v[1:2]
v_mad_u64_u32 v[3:4], null, s5, s4, v[0:1]
s_cmp_gt_i32 s6, 0
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s4, v3, v2
v_add_co_ci_u32_e64 v1, null, 0, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[0:1]
s_cselect_b32 s2, -1, 0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
s_clause 0x2
s_load_b32 s8, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x28
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v0
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s8, 0
s_cselect_b32 s9, -1, 0
s_ashr_i32 s13, s5, 31
s_ashr_i32 s10, s4, 31
s_add_i32 s11, s5, s13
s_add_i32 s12, s4, s10
s_xor_b32 s11, s11, s13
s_xor_b32 s12, s12, s10
v_cvt_f32_u32_e32 v2, s11
v_cvt_f32_u32_e32 v3, s12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v5, v2
v_rcp_iflag_f32_e32 v3, v3
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v6, v0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v5, 0x4f7ffffe, v5 :: v_dual_mul_f32 v8, 0x4f7ffffe, v3
v_xor_b32_e32 v6, v6, v4
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_xor_b32_e32 v3, s13, v4
s_delay_alu instid0(VALU_DEP_4)
v_cvt_u32_f32_e32 v7, v5
v_cvt_u32_f32_e32 v8, v8
s_mul_i32 s0, s5, s8
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, s6
s_cbranch_scc1 .LBB0_8
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_2
global_load_b32 v9, v[1:2], off
s_sub_i32 s1, 0, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, s1, v7
s_sub_i32 s1, 0, s12
v_mul_hi_u32 v4, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v7, v4
v_mul_hi_u32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, v4, s11
v_add_nc_u32_e32 v10, 1, v4
v_sub_nc_u32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v11, s11, v5
v_cmp_le_u32_e32 vcc_lo, s11, v5
v_dual_cndmask_b32 v4, v4, v10 :: v_dual_cndmask_b32 v5, v5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, 1, v4
v_cmp_le_u32_e32 vcc_lo, s11, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v10, vcc_lo
v_mul_lo_u32 v10, s1, v8
s_mov_b32 s1, 0
v_xor_b32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v10, v8, v10
v_sub_nc_u32_e32 v5, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v11, 31, v5
v_add_nc_u32_e32 v10, v8, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v11
v_xor_b32_e32 v5, v5, v11
v_xor_b32_e32 v11, s10, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v10, v5, v10
v_mul_lo_u32 v12, v10, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v5, v12
v_add_nc_u32_e32 v12, 1, v10
v_subrev_nc_u32_e32 v13, s12, v5
v_cmp_le_u32_e32 vcc_lo, s12, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v10, v10, v12 :: v_dual_cndmask_b32 v5, v5, v13
v_add_nc_u32_e32 v12, 1, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s12, v5
v_cndmask_b32_e32 v5, v10, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v11
v_sub_nc_u32_e32 v10, v5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v10, v10, s6
v_add3_u32 v10, v11, s7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v10, v5
v_mad_u64_u32 v[10:11], null, s4, v5, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v10, v3
v_mad_u64_u32 v[10:11], null, s8, v5, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v10, v10, v4
v_mad_u64_u32 v[4:5], null, s5, v10, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v10, s8, v4
.p2align 6
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v4, v10
s_mov_b32 s13, s8
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s13, s13, -1
s_cmp_eq_u32 s13, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[4:5]
v_add_nc_u32_e32 v4, s0, v4
v_add_co_u32 v11, vcc_lo, s2, v11
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
global_load_b32 v5, v[11:12], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v9, v5, v9
global_store_b32 v[1:2], v9, off
s_cbranch_scc0 .LBB0_6
v_add_nc_u32_e32 v10, 1, v10
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s1, s8
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_2
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9downscalePfS_liiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9downscalePfS_liiiiii, .Lfunc_end0-_Z9downscalePfS_liiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9downscalePfS_liiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9downscalePfS_liiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int translate_idx_inv(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy, int off_time, int off_x, int off_y)
{
/* d1 = channel
d2 = time
d3, d4 = height, width
*/
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
t = t*scale_factor_t+off_time;
w = w*scale_factor_xy+off_x;
z = z*scale_factor_xy+off_y;
d2 *= scale_factor_t;
d3 *= scale_factor_xy;
d4 *= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__device__ int translate_idx(int ii, int d1, int d2, int d3, int d4, int scale_factor_t, int scale_factor_xy)
{
int x, y, t, z, w;
w = ii % d4;
ii = ii/d4;
z = ii % d3;
ii = ii/d3;
t = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor_xy;
z = z/scale_factor_xy;
t = t/scale_factor_t;
d2 /= scale_factor_t;
d3 /= scale_factor_xy;
d4 /= scale_factor_xy;
return (((((x*d1+y)*d2)+t)*d3)+z)*d4+w;
}
__global__ void downscale(float *gradInput_data, float *gradOutput_data, long no_elements, int scale_factor_t, int scale_factor_xy, int d1, int d2, int d3, int d4)
{
// output offset:
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
for (int i=0; i < scale_factor_t; i++){
for(int j=0; j < scale_factor_xy; j++){
for(int k=0; k < scale_factor_xy; k++){
int ipidx = translate_idx_inv(ii, d1, d2, d3, d4, scale_factor_t, scale_factor_xy, i, j, k);
gradInput_data[ii] += gradOutput_data[ipidx];
}
}
}
} | .text
.file "downscale.hip"
.globl _Z24__device_stub__downscalePfS_liiiiii # -- Begin function _Z24__device_stub__downscalePfS_liiiiii
.p2align 4, 0x90
.type _Z24__device_stub__downscalePfS_liiiiii,@function
_Z24__device_stub__downscalePfS_liiiiii: # @_Z24__device_stub__downscalePfS_liiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9downscalePfS_liiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z24__device_stub__downscalePfS_liiiiii, .Lfunc_end0-_Z24__device_stub__downscalePfS_liiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9downscalePfS_liiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9downscalePfS_liiiiii,@object # @_Z9downscalePfS_liiiiii
.section .rodata,"a",@progbits
.globl _Z9downscalePfS_liiiiii
.p2align 3, 0x0
_Z9downscalePfS_liiiiii:
.quad _Z24__device_stub__downscalePfS_liiiiii
.size _Z9downscalePfS_liiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9downscalePfS_liiiiii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__downscalePfS_liiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9downscalePfS_liiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9downscalePfS_liiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fc6000f8e023f */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002600 */
/*0070*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R2, UR4, R5 ; /* 0x0000000402037c24 */
/* 0x002fe4000f8e0205 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fc600078e00ff */
/*00c0*/ IADD3 R0, P2, R0, R3, RZ ; /* 0x0000000300007210 */
/* 0x000fe40007f5e0ff */
/*00d0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f06270 */
/*00e0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f26070 */
/*00f0*/ IADD3.X R3, RZ, RZ, RZ, P2, !PT ; /* 0x000000ffff037210 */
/* 0x000fc800017fe4ff */
/*0100*/ ISETP.GE.OR.EX P0, PT, R3, c[0x0][0x174], !P0, P1 ; /* 0x00005d0003007a0c */
/* 0x000fda0004706710 */
/*0110*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff047624 */
/* 0x000fca00078e00ff */
/*0130*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*0140*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, R4, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x000fe20007ffe0ff */
/*0160*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0170*/ LEA R2, P1, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fe400078210ff */
/*0180*/ LOP3.LUT R18, R4.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304127812 */
/* 0x040fe200078ec0ff */
/*0190*/ IMAD R4, R4, c[0x0][0x18c], RZ ; /* 0x0000630004047a24 */
/* 0x000fe200078e02ff */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe20003f06070 */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*01c0*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P1 ; /* 0x0000590000037a11 */
/* 0x000fe400008f1403 */
/*01d0*/ IADD3 R6, R18, -c[0x0][0x17c], RZ ; /* 0x80005f0012067a10 */
/* 0x000fc40007ffe0ff */
/*01e0*/ IABS R14, c[0x0][0x18c] ; /* 0x00006300000e7a13 */
/* 0x000fe40000000000 */
/*01f0*/ IABS R7, c[0x0][0x188] ; /* 0x0000620000077a13 */
/* 0x000fc40000000000 */
/*0200*/ I2F.RP R10, R14 ; /* 0x0000000e000a7306 */
/* 0x001e300000209400 */
/*0210*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x001e240000001000 */
/*0220*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x001fc40007ffe0ff */
/*0230*/ IABS R10, R0 ; /* 0x00000000000a7213 */
/* 0x000fc80000000000 */
/*0240*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x002064000021f000 */
/*0250*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe200078e00ff */
/*0260*/ IADD3 R11, RZ, -R9, RZ ; /* 0x80000009ff0b7210 */
/* 0x00afca0007ffe0ff */
/*0270*/ IMAD R11, R11, R14, RZ ; /* 0x0000000e0b0b7224 */
/* 0x000fc800078e02ff */
/*0280*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fe400078e0008 */
/*0290*/ I2F.RP R11, R7 ; /* 0x00000007000b7306 */
/* 0x000e280000209400 */
/*02a0*/ IMAD.HI.U32 R8, R9, R10, RZ ; /* 0x0000000a09087227 */
/* 0x000fc800078e00ff */
/*02b0*/ IMAD.MOV R9, RZ, RZ, -R8 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0a08 */
/*02c0*/ IMAD R9, R14, R9, R10 ; /* 0x000000090e097224 */
/* 0x000fe200078e020a */
/*02d0*/ LOP3.LUT R10, R0, c[0x0][0x18c], RZ, 0x3c, !PT ; /* 0x00006300000a7a12 */
/* 0x000fe200078e3cff */
/*02e0*/ MUFU.RCP R11, R11 ; /* 0x0000000b000b7308 */
/* 0x001e260000001000 */
/*02f0*/ ISETP.GT.U32.AND P3, PT, R14, R9, PT ; /* 0x000000090e00720c */
/* 0x000fe40003f64070 */
/*0300*/ ISETP.GE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f46270 */
/*0310*/ @!P3 IADD3 R9, R9, -R14.reuse, RZ ; /* 0x8000000e0909b210 */
/* 0x080fe40007ffe0ff */
/*0320*/ IADD3 R12, R11, 0xffffffe, RZ ; /* 0x0ffffffe0b0c7810 */
/* 0x001fe40007ffe0ff */
/*0330*/ ISETP.GE.U32.AND P1, PT, R9, R14, PT ; /* 0x0000000e0900720c */
/* 0x000fe40003f26070 */
/*0340*/ F2I.FTZ.U32.TRUNC.NTZ R9, R12 ; /* 0x0000000c00097305 */
/* 0x000e22000021f000 */
/*0350*/ @!P3 IADD3 R8, R8, 0x1, RZ ; /* 0x000000010808b810 */
/* 0x000fe40007ffe0ff */
/*0360*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x18c], PT ; /* 0x00006300ff007a0c */
/* 0x000fd00003f65270 */
/*0370*/ @P1 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108081810 */
/* 0x000fca0007ffe0ff */
/*0380*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0008 */
/*0390*/ IADD3 R8, RZ, -R9, RZ ; /* 0x80000009ff087210 */
/* 0x001fc60007ffe0ff */
/*03a0*/ @!P2 IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0ea224 */
/* 0x000fe200078e0a0e */
/*03b0*/ @!P3 LOP3.LUT R14, RZ, c[0x0][0x18c], RZ, 0x33, !PT ; /* 0x00006300ff0eba12 */
/* 0x000fe200078e33ff */
/*03c0*/ IMAD R11, R8, R7, RZ ; /* 0x00000007080b7224 */
/* 0x000fe200078e02ff */
/*03d0*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe400000001ff */
/*03e0*/ IABS R10, R14 ; /* 0x0000000e000a7213 */
/* 0x000fd00000000000 */
/*03f0*/ IMAD.HI.U32 R8, R9, R11, R8 ; /* 0x0000000b09087227 */
/* 0x000fc800078e0008 */
/*0400*/ IMAD.MOV R11, RZ, RZ, -R14 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0a0e */
/*0410*/ IMAD.HI.U32 R8, R8, R10, RZ ; /* 0x0000000a08087227 */
/* 0x000fc800078e00ff */
/*0420*/ IMAD.MOV R9, RZ, RZ, -R8 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0a08 */
/*0430*/ IMAD R10, R7, R9, R10 ; /* 0x00000009070a7224 */
/* 0x000fca00078e020a */
/*0440*/ ISETP.GT.U32.AND P3, PT, R7, R10, PT ; /* 0x0000000a0700720c */
/* 0x000fda0003f64070 */
/*0450*/ @!P3 IADD3 R10, R10, -R7.reuse, RZ ; /* 0x800000070a0ab210 */
/* 0x080fe40007ffe0ff */
/*0460*/ @!P3 IADD3 R8, R8, 0x1, RZ ; /* 0x000000010808b810 */
/* 0x000fe40007ffe0ff */
/*0470*/ ISETP.GE.U32.AND P1, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fe40003f26070 */
/*0480*/ LOP3.LUT R7, R14, c[0x0][0x188], RZ, 0x3c, !PT ; /* 0x000062000e077a12 */
/* 0x000fe400078e3cff */
/*0490*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x000fe40003f65270 */
/*04a0*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fce0003f46270 */
/*04b0*/ @P1 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108081810 */
/* 0x000fcc0007ffe0ff */
/*04c0*/ @!P2 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e0a08 */
/*04d0*/ @!P3 LOP3.LUT R8, RZ, c[0x0][0x188], RZ, 0x33, !PT ; /* 0x00006200ff08ba12 */
/* 0x000fc800078e33ff */
/*04e0*/ IADD3 R7, -R8.reuse, RZ, RZ ; /* 0x000000ff08077210 */
/* 0x040fe20007ffe1ff */
/*04f0*/ IMAD R9, R8, c[0x0][0x178], R5 ; /* 0x00005e0008097a24 */
/* 0x000fc800078e0205 */
/*0500*/ IMAD R8, R7, c[0x0][0x188], R14 ; /* 0x0000620007087a24 */
/* 0x000fe400078e020e */
/*0510*/ IMAD R7, R11, c[0x0][0x18c], R0 ; /* 0x000063000b077a24 */
/* 0x000fe400078e0200 */
/*0520*/ IMAD R8, R9, c[0x0][0x188], R8 ; /* 0x0000620009087a24 */
/* 0x000fe200078e0208 */
/*0530*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fc60000000f00 */
/*0540*/ IMAD R10, R4, R8, R7 ; /* 0x00000008040a7224 */
/* 0x004fe400078e0207 */
/*0550*/ ISETP.NE.AND P2, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe20003f45270 */
/*0560*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x008fe200078e00ff */
/*0570*/ @!P0 BRA 0x710 ; /* 0x0000019000008947 */
/* 0x007ff60003800000 */
/*0580*/ LDG.E R23, [R2.64] ; /* 0x0000000402177981 */
/* 0x000162000c1e1900 */
/*0590*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*05a0*/ IMAD R19, R10, c[0x0][0x17c], R9 ; /* 0x00005f000a137a24 */
/* 0x000fe400078e0209 */
/*05b0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x4 ; /* 0x00000004ff0c7424 */
/* 0x000fc800078e00ff */
/*05c0*/ IMAD.WIDE R12, R19, R12, c[0x0][0x168] ; /* 0x00005a00130c7625 */
/* 0x000fca00078e020c */
/*05d0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea4000c1e1900 */
/*05e0*/ FADD R25, R14, R23 ; /* 0x000000170e197221 */
/* 0x026fe40000000000 */
/*05f0*/ IMAD.WIDE R14, R4, 0x4, R12 ; /* 0x00000004040e7825 */
/* 0x000fc600078e020c */
/*0600*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0610*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea4000c1e1900 */
/*0620*/ FADD R27, R25, R16 ; /* 0x00000010191b7221 */
/* 0x004fe40000000000 */
/*0630*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fc600078e020e */
/*0640*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0003e8000c101904 */
/*0650*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea2000c1e1900 */
/*0660*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FADD R29, R27, R20 ; /* 0x000000141b1d7221 */
/* 0x004fe40000000000 */
/*0680*/ IMAD.WIDE R20, R4, 0x4, R16 ; /* 0x0000000404147825 */
/* 0x000fc600078e0210 */
/*0690*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x0003e8000c101904 */
/*06a0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea2000c1e1900 */
/*06b0*/ IADD3 R12, R6, R11, RZ ; /* 0x0000000b060c7210 */
/* 0x000fe20007ffe0ff */
/*06c0*/ IMAD R19, R4, 0x4, R19 ; /* 0x0000000404137824 */
/* 0x000fc600078e0213 */
/*06d0*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f25270 */
/*06e0*/ FADD R23, R29, R20 ; /* 0x000000141d177221 */
/* 0x004fca0000000000 */
/*06f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003ee000c101904 */
/*0700*/ @P1 BRA 0x5b0 ; /* 0xfffffea000001947 */
/* 0x000fea000383ffff */
/*0710*/ @!P2 BRA 0x8d0 ; /* 0x000001b00000a947 */
/* 0x000fea0003800000 */
/*0720*/ IMAD R14, R8, c[0x0][0x17c], R11 ; /* 0x00005f00080e7a24 */
/* 0x000fe200078e020b */
/*0730*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fe20000000f00 */
/*0740*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea4000c1e1900 */
/*0750*/ IMAD R12, R14, c[0x0][0x18c], R7 ; /* 0x000063000e0c7a24 */
/* 0x000fc800078e0207 */
/*0760*/ IMAD R12, R12, c[0x0][0x17c], R9 ; /* 0x00005f000c0c7a24 */
/* 0x000fc800078e0209 */
/*0770*/ IMAD.WIDE R12, R12, R11, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fcc00078e020b */
/*0780*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1900 */
/*0790*/ ISETP.NE.AND P1, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fe20003f25270 */
/*07a0*/ FADD R15, R12, R15 ; /* 0x0000000f0c0f7221 */
/* 0x004fca0000000000 */
/*07b0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005ee000c101904 */
/*07c0*/ @!P1 BRA 0x8d0 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*07d0*/ IADD3 R12, R14, 0x1, RZ ; /* 0x000000010e0c7810 */
/* 0x000fca0007ffe0ff */
/*07e0*/ IMAD R12, R12, c[0x0][0x18c], R7 ; /* 0x000063000c0c7a24 */
/* 0x000fc800078e0207 */
/*07f0*/ IMAD R12, R12, c[0x0][0x17c], R9 ; /* 0x00005f000c0c7a24 */
/* 0x000fc800078e0209 */
/*0800*/ IMAD.WIDE R12, R12, R11, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fcc00078e020b */
/*0810*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1900 */
/*0820*/ ISETP.NE.AND P1, PT, R18, 0x2, PT ; /* 0x000000021200780c */
/* 0x000fe20003f25270 */
/*0830*/ FADD R15, R15, R12 ; /* 0x0000000c0f0f7221 */
/* 0x00cfca0000000000 */
/*0840*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005ee000c101904 */
/*0850*/ @!P1 BRA 0x8d0 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0860*/ IADD3 R12, R14, 0x2, RZ ; /* 0x000000020e0c7810 */
/* 0x000fca0007ffe0ff */
/*0870*/ IMAD R12, R12, c[0x0][0x18c], R7 ; /* 0x000063000c0c7a24 */
/* 0x000fc800078e0207 */
/*0880*/ IMAD R12, R12, c[0x0][0x17c], R9 ; /* 0x00005f000c0c7a24 */
/* 0x000fc800078e0209 */
/*0890*/ IMAD.WIDE R12, R12, R11, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fcc00078e020b */
/*08a0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee4000c1e1900 */
/*08b0*/ FADD R11, R15, R12 ; /* 0x0000000c0f0b7221 */
/* 0x008fca0000000000 */
/*08c0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0007e4000c101904 */
/*08d0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc80007ffe0ff */
/*08e0*/ ISETP.GE.AND P1, PT, R9, c[0x0][0x17c], PT ; /* 0x00005f0009007a0c */
/* 0x000fda0003f26270 */
/*08f0*/ @!P1 BRA 0x550 ; /* 0xfffffc5000009947 */
/* 0x000fea000383ffff */
/*0900*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fc80007ffe0ff */
/*0910*/ ISETP.GE.AND P1, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fda0003f26270 */
/*0920*/ @!P1 BRA 0x1e0 ; /* 0xfffff8b000009947 */
/* 0x000fea000383ffff */
/*0930*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0940*/ BRA 0x940; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9downscalePfS_liiiiii
.globl _Z9downscalePfS_liiiiii
.p2align 8
.type _Z9downscalePfS_liiiiii,@function
_Z9downscalePfS_liiiiii:
s_clause 0x3
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s5, s[0:1], 0x30
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s4, 0xffff
s_mul_i32 s5, s5, s15
s_lshr_b32 s4, s4, 16
s_mul_i32 s5, s5, s7
v_mad_u64_u32 v[2:3], null, s14, s7, v[1:2]
v_mad_u64_u32 v[3:4], null, s5, s4, v[0:1]
s_cmp_gt_i32 s6, 0
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s4, v3, v2
v_add_co_ci_u32_e64 v1, null, 0, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[0:1]
s_cselect_b32 s2, -1, 0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
s_clause 0x2
s_load_b32 s8, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x28
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v0
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s8, 0
s_cselect_b32 s9, -1, 0
s_ashr_i32 s13, s5, 31
s_ashr_i32 s10, s4, 31
s_add_i32 s11, s5, s13
s_add_i32 s12, s4, s10
s_xor_b32 s11, s11, s13
s_xor_b32 s12, s12, s10
v_cvt_f32_u32_e32 v2, s11
v_cvt_f32_u32_e32 v3, s12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v5, v2
v_rcp_iflag_f32_e32 v3, v3
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v6, v0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v5, 0x4f7ffffe, v5 :: v_dual_mul_f32 v8, 0x4f7ffffe, v3
v_xor_b32_e32 v6, v6, v4
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_xor_b32_e32 v3, s13, v4
s_delay_alu instid0(VALU_DEP_4)
v_cvt_u32_f32_e32 v7, v5
v_cvt_u32_f32_e32 v8, v8
s_mul_i32 s0, s5, s8
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, s6
s_cbranch_scc1 .LBB0_8
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_2
global_load_b32 v9, v[1:2], off
s_sub_i32 s1, 0, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, s1, v7
s_sub_i32 s1, 0, s12
v_mul_hi_u32 v4, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v7, v4
v_mul_hi_u32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, v4, s11
v_add_nc_u32_e32 v10, 1, v4
v_sub_nc_u32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v11, s11, v5
v_cmp_le_u32_e32 vcc_lo, s11, v5
v_dual_cndmask_b32 v4, v4, v10 :: v_dual_cndmask_b32 v5, v5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, 1, v4
v_cmp_le_u32_e32 vcc_lo, s11, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v10, vcc_lo
v_mul_lo_u32 v10, s1, v8
s_mov_b32 s1, 0
v_xor_b32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v10, v8, v10
v_sub_nc_u32_e32 v5, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v11, 31, v5
v_add_nc_u32_e32 v10, v8, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v11
v_xor_b32_e32 v5, v5, v11
v_xor_b32_e32 v11, s10, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v10, v5, v10
v_mul_lo_u32 v12, v10, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v5, v12
v_add_nc_u32_e32 v12, 1, v10
v_subrev_nc_u32_e32 v13, s12, v5
v_cmp_le_u32_e32 vcc_lo, s12, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v10, v10, v12 :: v_dual_cndmask_b32 v5, v5, v13
v_add_nc_u32_e32 v12, 1, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s12, v5
v_cndmask_b32_e32 v5, v10, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v11
v_sub_nc_u32_e32 v10, v5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v10, v10, s6
v_add3_u32 v10, v11, s7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v10, v5
v_mad_u64_u32 v[10:11], null, s4, v5, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v10, v3
v_mad_u64_u32 v[10:11], null, s8, v5, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v10, v10, v4
v_mad_u64_u32 v[4:5], null, s5, v10, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v10, s8, v4
.p2align 6
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v4, v10
s_mov_b32 s13, s8
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s13, s13, -1
s_cmp_eq_u32 s13, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[4:5]
v_add_nc_u32_e32 v4, s0, v4
v_add_co_u32 v11, vcc_lo, s2, v11
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
global_load_b32 v5, v[11:12], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v9, v5, v9
global_store_b32 v[1:2], v9, off
s_cbranch_scc0 .LBB0_6
v_add_nc_u32_e32 v10, 1, v10
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s1, s8
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_2
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9downscalePfS_liiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9downscalePfS_liiiiii, .Lfunc_end0-_Z9downscalePfS_liiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9downscalePfS_liiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9downscalePfS_liiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011c225_00000000-6_downscale.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17translate_idx_inviiiiiiiiii
.type _Z17translate_idx_inviiiiiiiiii, @function
_Z17translate_idx_inviiiiiiiiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z17translate_idx_inviiiiiiiiii, .-_Z17translate_idx_inviiiiiiiiii
.globl _Z13translate_idxiiiiiii
.type _Z13translate_idxiiiiiii, @function
_Z13translate_idxiiiiiii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z13translate_idxiiiiiii, .-_Z13translate_idxiiiiiii
.globl _Z37__device_stub__Z9downscalePfS_liiiiiiPfS_liiiiii
.type _Z37__device_stub__Z9downscalePfS_liiiiiiPfS_liiiiii, @function
_Z37__device_stub__Z9downscalePfS_liiiiiiPfS_liiiiii:
.LFB2053:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9downscalePfS_liiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z37__device_stub__Z9downscalePfS_liiiiiiPfS_liiiiii, .-_Z37__device_stub__Z9downscalePfS_liiiiiiPfS_liiiiii
.globl _Z9downscalePfS_liiiiii
.type _Z9downscalePfS_liiiiii, @function
_Z9downscalePfS_liiiiii:
.LFB2054:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z37__device_stub__Z9downscalePfS_liiiiiiPfS_liiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z9downscalePfS_liiiiii, .-_Z9downscalePfS_liiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9downscalePfS_liiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9downscalePfS_liiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "downscale.hip"
.globl _Z24__device_stub__downscalePfS_liiiiii # -- Begin function _Z24__device_stub__downscalePfS_liiiiii
.p2align 4, 0x90
.type _Z24__device_stub__downscalePfS_liiiiii,@function
_Z24__device_stub__downscalePfS_liiiiii: # @_Z24__device_stub__downscalePfS_liiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9downscalePfS_liiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z24__device_stub__downscalePfS_liiiiii, .Lfunc_end0-_Z24__device_stub__downscalePfS_liiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9downscalePfS_liiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9downscalePfS_liiiiii,@object # @_Z9downscalePfS_liiiiii
.section .rodata,"a",@progbits
.globl _Z9downscalePfS_liiiiii
.p2align 3, 0x0
_Z9downscalePfS_liiiiii:
.quad _Z24__device_stub__downscalePfS_liiiiii
.size _Z9downscalePfS_liiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9downscalePfS_liiiiii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__downscalePfS_liiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9downscalePfS_liiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Matrix multiplication Exercise : P = M . N.
*
* This program basically follows the tutorial in class.
*
* Given the 1024*1024 matrix test case, this program got the best performance
* boost using TILE_WIDTH = 16. This was also suggested in the slide set.
*
* This exercise was executed on a MacBook Pro, with GeForce GT 650M
* Using the CPU matrixMultiplication code, it takes about 18 seconds
* Using this TILED approach, it only take about 0.13 ~0.15 seconds
*
* See also:
* Zhou Bin@ Nvidia & USTC, 2014, October, "CUDA Programming (2)" Lecture Slides
*
*
*/
#include "stdio.h"
#include "stdlib.h"
#include "cuda.h"
#include "cuda_runtime.h"
#define W 1024
#define TILE_WIDTH 16
#define DEBUG 1
void printMatrix(float *Matrix)
{
const int MAX_SIZE_PRINTED = 4;
printf("This is a %d by %d matrix.\n", W,W);
if (W > MAX_SIZE_PRINTED) {
printf("Actual displayed size is cut in 2 parts shown as");
printf(" %d by %d matrix.\n", MAX_SIZE_PRINTED, MAX_SIZE_PRINTED);
printf(" The Top_LEFT CORNER OF the %d * %d matrix:\n", W, W);
}
for(int i=0;i<W;i++)
{
for(int j=0;j<W;j++)
if(i < MAX_SIZE_PRINTED && j < MAX_SIZE_PRINTED){
if (DEBUG) printf("%5.2f ",*(Matrix+i*W+j));
}
if(i < MAX_SIZE_PRINTED && DEBUG) printf("\n");
}
if (W > MAX_SIZE_PRINTED){
printf(" The LOWER_RIGHT CORNER OF the %d * %d matrix\n", W, W);
for(int i=W-MAX_SIZE_PRINTED;i<W;i++)
{
for(int j=W-MAX_SIZE_PRINTED;j<W;j++)
if (DEBUG) printf("%5.2f ",*(Matrix+i*W+j));
if(DEBUG) printf("\n");
}
}
}
/*
* This code is mostly copied from the slide set with some comments written by Ben Koo.
*
* In this test case, W = 1024, TILE_WIDTH = 16, making the dimGrid = 64 * 64
* Within each block, there are 16 * 16 threads.
*
*
*/
__global__ void matrixMulKernel_usingTile(float* Md, float* Nd, float* Pd, int Width)
{
//This delcares the device memory as 16 * 16 float matrices
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
// When W = 1024,t he block IDs (x * y) should be (64 * 64)
int bx = blockIdx.x; int by = blockIdx.y;
// When W = 1024, the thread IDs (x * y) should be (16 * 16)
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float PValue = 0;
// When W = 1024, m should go from 0 to 63
for (int m =0; m < Width/TILE_WIDTH; ++m){
// The following memory access takes place in shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH+ty)*Width];
//Make sure that all data are written in sync.
__syncthreads();
//Perform TILE level matrix multiplication and addition in synchrony.
for (int k = 0; k< TILE_WIDTH; ++k)
PValue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
//Take individually caldulated PValue and place it to the Pd (device memory array).
Pd[Row * Width + Col] = PValue;
}
int main()
{
int sNo = 0;
cudaSetDevice(sNo%8);
int size = W*W*sizeof(float);
float *M,*N,*P;
float *d_M,*d_N,*d_P;
M = (float *) malloc(size);
N = (float *) malloc(size);
P = (float *) malloc(size);
cudaMalloc((void **)&d_M,size);
cudaMalloc((void **)&d_N,size);
cudaMalloc((void **)&d_P,size);
//Populate initial values to the M, N and P matrices
for(int i=0;i<W*W;i++)
{
*(M+i) = i;
*(N+i) = i+1;
*(P+i) = 0;
}
cudaMemcpy(d_M, M,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_N, N,size,cudaMemcpyHostToDevice);
//Starting from here, set up CUDA timing mechanism
float time_elapsed = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
dim3 dimGrid(W /TILE_WIDTH, W / TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
matrixMulKernel_usingTile<<< dimGrid, dimBlock >>>(d_M,d_N,d_P,W);
cudaEventRecord(stop,0);
cudaEventSynchronize(start);
cudaEventSynchronize(stop);
//The following function returns time_elapsed using milli-seconds as time units
cudaEventElapsedTime(&time_elapsed, start, stop);
//Finished timing for CUDA execution
//To display time_elapsed into a number, divide it by 1000 first.
printf("\n\nGPU Elapsed Time:%f\n", time_elapsed/1000);
cudaMemcpy(P,d_P,size,cudaMemcpyDeviceToHost);
printMatrix(P);
free(M);free(N);free(P);
cudaFree(d_M);cudaFree(d_N);cudaFree(d_P);
return 0;
} | code for sm_80
Function : _Z25matrixMulKernel_usingTilePfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ MOV R19, c[0x0][0x178] ; /* 0x00005e0000137a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R17, SR_TID.Y ; /* 0x0000000000117919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R19, 0x10, PT ; /* 0x000000101300780c */
/* 0x000fe20003f06270 */
/*0070*/ HFMA2.MMA R23, -RZ, RZ, 0, 0 ; /* 0x00000000ff177435 */
/* 0x000fe400000001ff */
/*0080*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e680000002500 */
/*0090*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*00a0*/ LEA R5, R5, R17, 0x4 ; /* 0x0000001105057211 */
/* 0x001fc400078e20ff */
/*00b0*/ LEA R2, R7, R0, 0x4 ; /* 0x0000000007027211 */
/* 0x002fca00078e20ff */
/*00c0*/ IMAD R2, R5, c[0x0][0x178], R2 ; /* 0x00005e0005027a24 */
/* 0x000fc800078e0202 */
/*00d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0203 */
/*00e0*/ @!P0 BRA 0x4f0 ; /* 0x0000040000008947 */
/* 0x000fea0003800000 */
/*00f0*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD R14, R5, c[0x0][0x178], R0.reuse ; /* 0x00005e00050e7a24 */
/* 0x100fe200078e0200 */
/*0110*/ SHF.R.S32.HI R5, RZ, 0x1f, R19 ; /* 0x0000001fff057819 */
/* 0x000fe20000011413 */
/*0120*/ IMAD R4, R17.reuse, c[0x0][0x178], R0 ; /* 0x00005e0011047a24 */
/* 0x040fe200078e0200 */
/*0130*/ SHF.L.U32 R17, R17, 0x6, RZ ; /* 0x0000000611117819 */
/* 0x000fe200000006ff */
/*0140*/ IMAD.WIDE R14, R14, R13, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fe200078e020d */
/*0150*/ LEA.HI R5, R5, c[0x0][0x178], RZ, 0x4 ; /* 0x00005e0005057a11 */
/* 0x000fe200078f20ff */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0170*/ LEA R4, R7, R4, 0x4 ; /* 0x0000000407047211 */
/* 0x000fe400078e20ff */
/*0180*/ MOV R21, R15 ; /* 0x0000000f00157202 */
/* 0x000fc40000000f00 */
/*0190*/ SHF.L.U32 R19, R19, 0x4, RZ ; /* 0x0000000413137819 */
/* 0x000fe200000006ff */
/*01a0*/ IMAD.WIDE R12, R4, R13, c[0x0][0x168] ; /* 0x00005a00040c7625 */
/* 0x000fe200078e020d */
/*01b0*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fe40000000f00 */
/*01c0*/ LEA R16, R0, R17, 0x2 ; /* 0x0000001100107211 */
/* 0x000fe400078e10ff */
/*01d0*/ SHF.R.S32.HI R15, RZ, 0x4, R5 ; /* 0x00000004ff0f7819 */
/* 0x000fe40000011405 */
/*01e0*/ MOV R20, R14 ; /* 0x0000000e00147202 */
/* 0x000fe20000000f00 */
/*01f0*/ LDG.E R24, [R12.64] ; /* 0x000000060c187981 */
/* 0x0000a8000c1e1900 */
/*0200*/ LDG.E R27, [R20.64] ; /* 0x00000006141b7981 */
/* 0x0002e2000c1e1900 */
/*0210*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0220*/ IADD3 R14, P1, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x000fe20007f3e0ff */
/*0230*/ IMAD.WIDE R12, R19, 0x4, R12 ; /* 0x00000004130c7825 */
/* 0x001fc800078e020c */
/*0240*/ ISETP.LE.AND P0, PT, R15, UR4, PT ; /* 0x000000040f007c0c */
/* 0x000fe4000bf03270 */
/*0250*/ IADD3.X R21, RZ, R21, RZ, P1, !PT ; /* 0x00000015ff157210 */
/* 0x002fe20000ffe4ff */
/*0260*/ STS [R16+0x400], R24 ; /* 0x0004001810007388 */
/* 0x004fe80000000800 */
/*0270*/ STS [R16], R27 ; /* 0x0000001b10007388 */
/* 0x008fe80000000800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ LDS R26, [R0.X4+0x400] ; /* 0x00040000001a7984 */
/* 0x000fe80000004800 */
/*02a0*/ LDS.128 R8, [R17] ; /* 0x0000000011087984 */
/* 0x000e280000000c00 */
/*02b0*/ LDS R28, [R0.X4+0x440] ; /* 0x00044000001c7984 */
/* 0x000e680000004800 */
/*02c0*/ LDS R29, [R0.X4+0x480] ; /* 0x00048000001d7984 */
/* 0x000ea80000004800 */
/*02d0*/ LDS R22, [R0.X4+0x4c0] ; /* 0x0004c00000167984 */
/* 0x000ee80000004800 */
/*02e0*/ LDS R25, [R0.X4+0x500] ; /* 0x0005000000197984 */
/* 0x000fe80000004800 */
/*02f0*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000f280000000c00 */
/*0300*/ LDS R18, [R0.X4+0x540] ; /* 0x0005400000127984 */
/* 0x000f680000004800 */
/*0310*/ LDS R27, [R0.X4+0x580] ; /* 0x00058000001b7984 */
/* 0x000f680000004800 */
/*0320*/ LDS R20, [R0.X4+0x5c0] ; /* 0x0005c00000147984 */
/* 0x000f620000004800 */
/*0330*/ FFMA R8, R26, R8, R23 ; /* 0x000000081a087223 */
/* 0x001fc60000000017 */
/*0340*/ LDS R23, [R0.X4+0x600] ; /* 0x0006000000177984 */
/* 0x000fe20000004800 */
/*0350*/ FFMA R8, R28, R9, R8 ; /* 0x000000091c087223 */
/* 0x002fc80000000008 */
/*0360*/ FFMA R8, R29, R10, R8 ; /* 0x0000000a1d087223 */
/* 0x004fc80000000008 */
/*0370*/ FFMA R22, R22, R11, R8 ; /* 0x0000000b16167223 */
/* 0x008fe40000000008 */
/*0380*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e240000000c00 */
/*0390*/ FFMA R4, R25, R4, R22 ; /* 0x0000000419047223 */
/* 0x010fe40000000016 */
/*03a0*/ LDS R22, [R0.X4+0x640] ; /* 0x0006400000167984 */
/* 0x000e640000004800 */
/*03b0*/ FFMA R4, R18, R5, R4 ; /* 0x0000000512047223 */
/* 0x020fe40000000004 */
/*03c0*/ LDS R25, [R0.X4+0x680] ; /* 0x0006800000197984 */
/* 0x000ea40000004800 */
/*03d0*/ FFMA R4, R27, R6, R4 ; /* 0x000000061b047223 */
/* 0x000fc40000000004 */
/*03e0*/ LDS R18, [R0.X4+0x6c0] ; /* 0x0006c00000127984 */
/* 0x000ee40000004800 */
/*03f0*/ FFMA R24, R20, R7, R4 ; /* 0x0000000714187223 */
/* 0x000fe40000000004 */
/*0400*/ LDS R27, [R0.X4+0x700] ; /* 0x00070000001b7984 */
/* 0x000fe80000004800 */
/*0410*/ LDS.128 R4, [R17+0x30] ; /* 0x0000300011047984 */
/* 0x000f280000000c00 */
/*0420*/ LDS R20, [R0.X4+0x740] ; /* 0x0007400000147984 */
/* 0x000f620000004800 */
/*0430*/ FFMA R24, R23, R8, R24 ; /* 0x0000000817187223 */
/* 0x001fc60000000018 */
/*0440*/ LDS R23, [R0.X4+0x780] ; /* 0x0007800000177984 */
/* 0x000e280000004800 */
/*0450*/ LDS R8, [R0.X4+0x7c0] ; /* 0x0007c00000087984 */
/* 0x000e220000004800 */
/*0460*/ FFMA R9, R22, R9, R24 ; /* 0x0000000916097223 */
/* 0x002fc80000000018 */
/*0470*/ FFMA R9, R25, R10, R9 ; /* 0x0000000a19097223 */
/* 0x004fc80000000009 */
/*0480*/ FFMA R9, R18, R11, R9 ; /* 0x0000000b12097223 */
/* 0x008fc80000000009 */
/*0490*/ FFMA R4, R27, R4, R9 ; /* 0x000000041b047223 */
/* 0x010fc80000000009 */
/*04a0*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fc80000000004 */
/*04b0*/ FFMA R23, R23, R6, R4 ; /* 0x0000000617177223 */
/* 0x001fc80000000004 */
/*04c0*/ FFMA R23, R8, R7, R23 ; /* 0x0000000708177223 */
/* 0x000fe20000000017 */
/*04d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04e0*/ @!P0 BRA 0x1e0 ; /* 0xfffffcf000008947 */
/* 0x000fea000383ffff */
/*04f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe2000c101906 */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Matrix multiplication Exercise : P = M . N.
*
* This program basically follows the tutorial in class.
*
* Given the 1024*1024 matrix test case, this program got the best performance
* boost using TILE_WIDTH = 16. This was also suggested in the slide set.
*
* This exercise was executed on a MacBook Pro, with GeForce GT 650M
* Using the CPU matrixMultiplication code, it takes about 18 seconds
* Using this TILED approach, it only take about 0.13 ~0.15 seconds
*
* See also:
* Zhou Bin@ Nvidia & USTC, 2014, October, "CUDA Programming (2)" Lecture Slides
*
*
*/
#include "stdio.h"
#include "stdlib.h"
#include "cuda.h"
#include "cuda_runtime.h"
#define W 1024
#define TILE_WIDTH 16
#define DEBUG 1
void printMatrix(float *Matrix)
{
const int MAX_SIZE_PRINTED = 4;
printf("This is a %d by %d matrix.\n", W,W);
if (W > MAX_SIZE_PRINTED) {
printf("Actual displayed size is cut in 2 parts shown as");
printf(" %d by %d matrix.\n", MAX_SIZE_PRINTED, MAX_SIZE_PRINTED);
printf(" The Top_LEFT CORNER OF the %d * %d matrix:\n", W, W);
}
for(int i=0;i<W;i++)
{
for(int j=0;j<W;j++)
if(i < MAX_SIZE_PRINTED && j < MAX_SIZE_PRINTED){
if (DEBUG) printf("%5.2f ",*(Matrix+i*W+j));
}
if(i < MAX_SIZE_PRINTED && DEBUG) printf("\n");
}
if (W > MAX_SIZE_PRINTED){
printf(" The LOWER_RIGHT CORNER OF the %d * %d matrix\n", W, W);
for(int i=W-MAX_SIZE_PRINTED;i<W;i++)
{
for(int j=W-MAX_SIZE_PRINTED;j<W;j++)
if (DEBUG) printf("%5.2f ",*(Matrix+i*W+j));
if(DEBUG) printf("\n");
}
}
}
/*
* This code is mostly copied from the slide set with some comments written by Ben Koo.
*
* In this test case, W = 1024, TILE_WIDTH = 16, making the dimGrid = 64 * 64
* Within each block, there are 16 * 16 threads.
*
*
*/
__global__ void matrixMulKernel_usingTile(float* Md, float* Nd, float* Pd, int Width)
{
//This delcares the device memory as 16 * 16 float matrices
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
// When W = 1024,t he block IDs (x * y) should be (64 * 64)
int bx = blockIdx.x; int by = blockIdx.y;
// When W = 1024, the thread IDs (x * y) should be (16 * 16)
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float PValue = 0;
// When W = 1024, m should go from 0 to 63
for (int m =0; m < Width/TILE_WIDTH; ++m){
// The following memory access takes place in shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH+ty)*Width];
//Make sure that all data are written in sync.
__syncthreads();
//Perform TILE level matrix multiplication and addition in synchrony.
for (int k = 0; k< TILE_WIDTH; ++k)
PValue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
//Take individually caldulated PValue and place it to the Pd (device memory array).
Pd[Row * Width + Col] = PValue;
}
int main()
{
int sNo = 0;
cudaSetDevice(sNo%8);
int size = W*W*sizeof(float);
float *M,*N,*P;
float *d_M,*d_N,*d_P;
M = (float *) malloc(size);
N = (float *) malloc(size);
P = (float *) malloc(size);
cudaMalloc((void **)&d_M,size);
cudaMalloc((void **)&d_N,size);
cudaMalloc((void **)&d_P,size);
//Populate initial values to the M, N and P matrices
for(int i=0;i<W*W;i++)
{
*(M+i) = i;
*(N+i) = i+1;
*(P+i) = 0;
}
cudaMemcpy(d_M, M,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_N, N,size,cudaMemcpyHostToDevice);
//Starting from here, set up CUDA timing mechanism
float time_elapsed = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
dim3 dimGrid(W /TILE_WIDTH, W / TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
matrixMulKernel_usingTile<<< dimGrid, dimBlock >>>(d_M,d_N,d_P,W);
cudaEventRecord(stop,0);
cudaEventSynchronize(start);
cudaEventSynchronize(stop);
//The following function returns time_elapsed using milli-seconds as time units
cudaEventElapsedTime(&time_elapsed, start, stop);
//Finished timing for CUDA execution
//To display time_elapsed into a number, divide it by 1000 first.
printf("\n\nGPU Elapsed Time:%f\n", time_elapsed/1000);
cudaMemcpy(P,d_P,size,cudaMemcpyDeviceToHost);
printMatrix(P);
free(M);free(N);free(P);
cudaFree(d_M);cudaFree(d_N);cudaFree(d_P);
return 0;
} | .file "tmpxft_0001056b_00000000-6_Tiled_MatrixMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "This is a %d by %d matrix.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Actual displayed size is cut in 2 parts shown as"
.section .rodata.str1.1
.LC2:
.string " %d by %d matrix.\n"
.section .rodata.str1.8
.align 8
.LC3:
.string " The Top_LEFT CORNER OF the %d * %d matrix:\n"
.section .rodata.str1.1
.LC4:
.string "%5.2f "
.LC5:
.string "\n"
.section .rodata.str1.8
.align 8
.LC6:
.string " The LOWER_RIGHT CORNER OF the %d * %d matrix\n"
.text
.globl _Z11printMatrixPf
.type _Z11printMatrixPf, @function
_Z11printMatrixPf:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r14
movl $1024, %ecx
movl $1024, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, %ecx
movl $4, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, %ecx
movl $1024, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %r12
movl $0, %ebp
leaq .LC4(%rip), %r13
jmp .L4
.L5:
addq $1, %rbx
cmpq $1024, %rbx
je .L16
.L10:
movl %ebp, %eax
cmpl $3, %ebp
jg .L5
cmpl $3, %ebx
jg .L5
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
jmp .L10
.L16:
cmpl $3, %eax
jle .L17
addq $1, %rbp
addq $4096, %r12
cmpq $1024, %rbp
je .L9
.L4:
movl $0, %ebx
jmp .L10
.L17:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbp
addq $4096, %r12
jmp .L4
.L9:
movl $1024, %ecx
movl $1024, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 4177936(%r14), %rbx
movl $1044480, %r12d
leaq .LC4(%rip), %r14
leaq .LC5(%rip), %r13
.L11:
leaq -16(%rbx), %rbp
.L12:
pxor %xmm0, %xmm0
cvtss2sd 4080(%rbp), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %rbx, %rbp
jne .L12
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1024, %r12
addq $4096, %rbx
cmpq $1048576, %r12
jne .L11
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixPf, .-_Z11printMatrixPf
.globl _Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i
.type _Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i, @function
_Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25matrixMulKernel_usingTilePfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i, .-_Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i
.globl _Z25matrixMulKernel_usingTilePfS_S_i
.type _Z25matrixMulKernel_usingTilePfS_S_i, @function
_Z25matrixMulKernel_usingTilePfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z25matrixMulKernel_usingTilePfS_S_i, .-_Z25matrixMulKernel_usingTilePfS_S_i
.section .rodata.str1.1
.LC9:
.string "\n\nGPU Elapsed Time:%f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $0, %eax
.L27:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rax,4)
leal 1(%rax), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
movl $0x00000000, (%rbx,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L27
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 4(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $64, 48(%rsp)
movl $64, 52(%rsp)
movl $16, 60(%rsp)
movl $16, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 4(%rsp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdi
call _Z11printMatrixPf
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC10:
.string "_Z25matrixMulKernel_usingTilePfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z25matrixMulKernel_usingTilePfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC8:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Matrix multiplication Exercise : P = M . N.
*
* This program basically follows the tutorial in class.
*
* Given the 1024*1024 matrix test case, this program got the best performance
* boost using TILE_WIDTH = 16. This was also suggested in the slide set.
*
* This exercise was executed on a MacBook Pro, with GeForce GT 650M
* Using the CPU matrixMultiplication code, it takes about 18 seconds
* Using this TILED approach, it only take about 0.13 ~0.15 seconds
*
* See also:
* Zhou Bin@ Nvidia & USTC, 2014, October, "CUDA Programming (2)" Lecture Slides
*
*
*/
#include "stdio.h"
#include "stdlib.h"
#include "cuda.h"
#include "cuda_runtime.h"
#define W 1024
#define TILE_WIDTH 16
#define DEBUG 1
void printMatrix(float *Matrix)
{
const int MAX_SIZE_PRINTED = 4;
printf("This is a %d by %d matrix.\n", W,W);
if (W > MAX_SIZE_PRINTED) {
printf("Actual displayed size is cut in 2 parts shown as");
printf(" %d by %d matrix.\n", MAX_SIZE_PRINTED, MAX_SIZE_PRINTED);
printf(" The Top_LEFT CORNER OF the %d * %d matrix:\n", W, W);
}
for(int i=0;i<W;i++)
{
for(int j=0;j<W;j++)
if(i < MAX_SIZE_PRINTED && j < MAX_SIZE_PRINTED){
if (DEBUG) printf("%5.2f ",*(Matrix+i*W+j));
}
if(i < MAX_SIZE_PRINTED && DEBUG) printf("\n");
}
if (W > MAX_SIZE_PRINTED){
printf(" The LOWER_RIGHT CORNER OF the %d * %d matrix\n", W, W);
for(int i=W-MAX_SIZE_PRINTED;i<W;i++)
{
for(int j=W-MAX_SIZE_PRINTED;j<W;j++)
if (DEBUG) printf("%5.2f ",*(Matrix+i*W+j));
if(DEBUG) printf("\n");
}
}
}
/*
* This code is mostly copied from the slide set with some comments written by Ben Koo.
*
* In this test case, W = 1024, TILE_WIDTH = 16, making the dimGrid = 64 * 64
* Within each block, there are 16 * 16 threads.
*
*
*/
__global__ void matrixMulKernel_usingTile(float* Md, float* Nd, float* Pd, int Width)
{
//This delcares the device memory as 16 * 16 float matrices
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
// When W = 1024,t he block IDs (x * y) should be (64 * 64)
int bx = blockIdx.x; int by = blockIdx.y;
// When W = 1024, the thread IDs (x * y) should be (16 * 16)
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float PValue = 0;
// When W = 1024, m should go from 0 to 63
for (int m =0; m < Width/TILE_WIDTH; ++m){
// The following memory access takes place in shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH+ty)*Width];
//Make sure that all data are written in sync.
__syncthreads();
//Perform TILE level matrix multiplication and addition in synchrony.
for (int k = 0; k< TILE_WIDTH; ++k)
PValue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
//Take individually caldulated PValue and place it to the Pd (device memory array).
Pd[Row * Width + Col] = PValue;
}
int main()
{
int sNo = 0;
cudaSetDevice(sNo%8);
int size = W*W*sizeof(float);
float *M,*N,*P;
float *d_M,*d_N,*d_P;
M = (float *) malloc(size);
N = (float *) malloc(size);
P = (float *) malloc(size);
cudaMalloc((void **)&d_M,size);
cudaMalloc((void **)&d_N,size);
cudaMalloc((void **)&d_P,size);
//Populate initial values to the M, N and P matrices
for(int i=0;i<W*W;i++)
{
*(M+i) = i;
*(N+i) = i+1;
*(P+i) = 0;
}
cudaMemcpy(d_M, M,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_N, N,size,cudaMemcpyHostToDevice);
//Starting from here, set up CUDA timing mechanism
float time_elapsed = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
dim3 dimGrid(W /TILE_WIDTH, W / TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
matrixMulKernel_usingTile<<< dimGrid, dimBlock >>>(d_M,d_N,d_P,W);
cudaEventRecord(stop,0);
cudaEventSynchronize(start);
cudaEventSynchronize(stop);
//The following function returns time_elapsed using milli-seconds as time units
cudaEventElapsedTime(&time_elapsed, start, stop);
//Finished timing for CUDA execution
//To display time_elapsed into a number, divide it by 1000 first.
printf("\n\nGPU Elapsed Time:%f\n", time_elapsed/1000);
cudaMemcpy(P,d_P,size,cudaMemcpyDeviceToHost);
printMatrix(P);
free(M);free(N);free(P);
cudaFree(d_M);cudaFree(d_N);cudaFree(d_P);
return 0;
} | /**
* Matrix multiplication Exercise : P = M . N.
*
* This program basically follows the tutorial in class.
*
* Given the 1024*1024 matrix test case, this program got the best performance
* boost using TILE_WIDTH = 16. This was also suggested in the slide set.
*
* This exercise was executed on a MacBook Pro, with GeForce GT 650M
* Using the CPU matrixMultiplication code, it takes about 18 seconds
* Using this TILED approach, it only take about 0.13 ~0.15 seconds
*
* See also:
* Zhou Bin@ Nvidia & USTC, 2014, October, "CUDA Programming (2)" Lecture Slides
*
*
*/
#include "stdio.h"
#include "stdlib.h"
#include "hip/hip_runtime.h"
#define W 1024
#define TILE_WIDTH 16
#define DEBUG 1
void printMatrix(float *Matrix)
{
const int MAX_SIZE_PRINTED = 4;
printf("This is a %d by %d matrix.\n", W,W);
if (W > MAX_SIZE_PRINTED) {
printf("Actual displayed size is cut in 2 parts shown as");
printf(" %d by %d matrix.\n", MAX_SIZE_PRINTED, MAX_SIZE_PRINTED);
printf(" The Top_LEFT CORNER OF the %d * %d matrix:\n", W, W);
}
for(int i=0;i<W;i++)
{
for(int j=0;j<W;j++)
if(i < MAX_SIZE_PRINTED && j < MAX_SIZE_PRINTED){
if (DEBUG) printf("%5.2f ",*(Matrix+i*W+j));
}
if(i < MAX_SIZE_PRINTED && DEBUG) printf("\n");
}
if (W > MAX_SIZE_PRINTED){
printf(" The LOWER_RIGHT CORNER OF the %d * %d matrix\n", W, W);
for(int i=W-MAX_SIZE_PRINTED;i<W;i++)
{
for(int j=W-MAX_SIZE_PRINTED;j<W;j++)
if (DEBUG) printf("%5.2f ",*(Matrix+i*W+j));
if(DEBUG) printf("\n");
}
}
}
/*
* This code is mostly copied from the slide set with some comments written by Ben Koo.
*
* In this test case, W = 1024, TILE_WIDTH = 16, making the dimGrid = 64 * 64
* Within each block, there are 16 * 16 threads.
*
*
*/
__global__ void matrixMulKernel_usingTile(float* Md, float* Nd, float* Pd, int Width)
{
//This delcares the device memory as 16 * 16 float matrices
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
// When W = 1024,t he block IDs (x * y) should be (64 * 64)
int bx = blockIdx.x; int by = blockIdx.y;
// When W = 1024, the thread IDs (x * y) should be (16 * 16)
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float PValue = 0;
// When W = 1024, m should go from 0 to 63
for (int m =0; m < Width/TILE_WIDTH; ++m){
// The following memory access takes place in shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH+ty)*Width];
//Make sure that all data are written in sync.
__syncthreads();
//Perform TILE level matrix multiplication and addition in synchrony.
for (int k = 0; k< TILE_WIDTH; ++k)
PValue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
//Take individually caldulated PValue and place it to the Pd (device memory array).
Pd[Row * Width + Col] = PValue;
}
int main()
{
int sNo = 0;
hipSetDevice(sNo%8);
int size = W*W*sizeof(float);
float *M,*N,*P;
float *d_M,*d_N,*d_P;
M = (float *) malloc(size);
N = (float *) malloc(size);
P = (float *) malloc(size);
hipMalloc((void **)&d_M,size);
hipMalloc((void **)&d_N,size);
hipMalloc((void **)&d_P,size);
//Populate initial values to the M, N and P matrices
for(int i=0;i<W*W;i++)
{
*(M+i) = i;
*(N+i) = i+1;
*(P+i) = 0;
}
hipMemcpy(d_M, M,size,hipMemcpyHostToDevice);
hipMemcpy(d_N, N,size,hipMemcpyHostToDevice);
//Starting from here, set up CUDA timing mechanism
float time_elapsed = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
dim3 dimGrid(W /TILE_WIDTH, W / TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
matrixMulKernel_usingTile<<< dimGrid, dimBlock >>>(d_M,d_N,d_P,W);
hipEventRecord(stop,0);
hipEventSynchronize(start);
hipEventSynchronize(stop);
//The following function returns time_elapsed using milli-seconds as time units
hipEventElapsedTime(&time_elapsed, start, stop);
//Finished timing for CUDA execution
//To display time_elapsed into a number, divide it by 1000 first.
printf("\n\nGPU Elapsed Time:%f\n", time_elapsed/1000);
hipMemcpy(P,d_P,size,hipMemcpyDeviceToHost);
printMatrix(P);
free(M);free(N);free(P);
hipFree(d_M);hipFree(d_N);hipFree(d_P);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Matrix multiplication Exercise : P = M . N.
*
* This program basically follows the tutorial in class.
*
* Given the 1024*1024 matrix test case, this program got the best performance
* boost using TILE_WIDTH = 16. This was also suggested in the slide set.
*
* This exercise was executed on a MacBook Pro, with GeForce GT 650M
* Using the CPU matrixMultiplication code, it takes about 18 seconds
* Using this TILED approach, it only take about 0.13 ~0.15 seconds
*
* See also:
* Zhou Bin@ Nvidia & USTC, 2014, October, "CUDA Programming (2)" Lecture Slides
*
*
*/
#include "stdio.h"
#include "stdlib.h"
#include "hip/hip_runtime.h"
#define W 1024
#define TILE_WIDTH 16
#define DEBUG 1
void printMatrix(float *Matrix)
{
const int MAX_SIZE_PRINTED = 4;
printf("This is a %d by %d matrix.\n", W,W);
if (W > MAX_SIZE_PRINTED) {
printf("Actual displayed size is cut in 2 parts shown as");
printf(" %d by %d matrix.\n", MAX_SIZE_PRINTED, MAX_SIZE_PRINTED);
printf(" The Top_LEFT CORNER OF the %d * %d matrix:\n", W, W);
}
for(int i=0;i<W;i++)
{
for(int j=0;j<W;j++)
if(i < MAX_SIZE_PRINTED && j < MAX_SIZE_PRINTED){
if (DEBUG) printf("%5.2f ",*(Matrix+i*W+j));
}
if(i < MAX_SIZE_PRINTED && DEBUG) printf("\n");
}
if (W > MAX_SIZE_PRINTED){
printf(" The LOWER_RIGHT CORNER OF the %d * %d matrix\n", W, W);
for(int i=W-MAX_SIZE_PRINTED;i<W;i++)
{
for(int j=W-MAX_SIZE_PRINTED;j<W;j++)
if (DEBUG) printf("%5.2f ",*(Matrix+i*W+j));
if(DEBUG) printf("\n");
}
}
}
/*
* This code is mostly copied from the slide set with some comments written by Ben Koo.
*
* In this test case, W = 1024, TILE_WIDTH = 16, making the dimGrid = 64 * 64
* Within each block, there are 16 * 16 threads.
*
*
*/
__global__ void matrixMulKernel_usingTile(float* Md, float* Nd, float* Pd, int Width)
{
//This delcares the device memory as 16 * 16 float matrices
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
// When W = 1024,t he block IDs (x * y) should be (64 * 64)
int bx = blockIdx.x; int by = blockIdx.y;
// When W = 1024, the thread IDs (x * y) should be (16 * 16)
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float PValue = 0;
// When W = 1024, m should go from 0 to 63
for (int m =0; m < Width/TILE_WIDTH; ++m){
// The following memory access takes place in shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH+ty)*Width];
//Make sure that all data are written in sync.
__syncthreads();
//Perform TILE level matrix multiplication and addition in synchrony.
for (int k = 0; k< TILE_WIDTH; ++k)
PValue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
//Take individually caldulated PValue and place it to the Pd (device memory array).
Pd[Row * Width + Col] = PValue;
}
int main()
{
int sNo = 0;
hipSetDevice(sNo%8);
int size = W*W*sizeof(float);
float *M,*N,*P;
float *d_M,*d_N,*d_P;
M = (float *) malloc(size);
N = (float *) malloc(size);
P = (float *) malloc(size);
hipMalloc((void **)&d_M,size);
hipMalloc((void **)&d_N,size);
hipMalloc((void **)&d_P,size);
//Populate initial values to the M, N and P matrices
for(int i=0;i<W*W;i++)
{
*(M+i) = i;
*(N+i) = i+1;
*(P+i) = 0;
}
hipMemcpy(d_M, M,size,hipMemcpyHostToDevice);
hipMemcpy(d_N, N,size,hipMemcpyHostToDevice);
//Starting from here, set up CUDA timing mechanism
float time_elapsed = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
dim3 dimGrid(W /TILE_WIDTH, W / TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
matrixMulKernel_usingTile<<< dimGrid, dimBlock >>>(d_M,d_N,d_P,W);
hipEventRecord(stop,0);
hipEventSynchronize(start);
hipEventSynchronize(stop);
//The following function returns time_elapsed using milli-seconds as time units
hipEventElapsedTime(&time_elapsed, start, stop);
//Finished timing for CUDA execution
//To display time_elapsed into a number, divide it by 1000 first.
printf("\n\nGPU Elapsed Time:%f\n", time_elapsed/1000);
hipMemcpy(P,d_P,size,hipMemcpyDeviceToHost);
printMatrix(P);
free(M);free(N);free(P);
hipFree(d_M);hipFree(d_N);hipFree(d_P);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25matrixMulKernel_usingTilePfS_S_i
.globl _Z25matrixMulKernel_usingTilePfS_S_i
.p2align 8
.type _Z25matrixMulKernel_usingTilePfS_S_i,@function
_Z25matrixMulKernel_usingTilePfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 4, v5
v_lshl_add_u32 v0, s14, 4, v3
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 16
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v8, 2, v3
v_lshlrev_b32_e32 v6, 6, v5
s_ashr_i32 s3, s2, 31
v_mad_u64_u32 v[1:2], null, v4, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, 0x400, v8
s_lshr_b32 s3, s3, 28
v_add_nc_u32_e32 v3, v6, v8
s_add_i32 s3, s2, s3
v_add_nc_u32_e32 v8, v7, v6
s_ashr_i32 s3, s3, 4
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s9, s8, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, s9, v5
v_add_nc_u32_e32 v9, s9, v1
s_mov_b32 s9, 0
v_mad_u64_u32 v[11:12], null, v10, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v7
s_waitcnt vmcnt(1)
ds_store_b32 v3, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s9, v6
s_add_i32 s9, s9, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 64, v9
s_cmp_eq_u32 s9, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v10, v11
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v4, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25matrixMulKernel_usingTilePfS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25matrixMulKernel_usingTilePfS_S_i, .Lfunc_end0-_Z25matrixMulKernel_usingTilePfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25matrixMulKernel_usingTilePfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25matrixMulKernel_usingTilePfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Matrix multiplication Exercise : P = M . N.
*
* This program basically follows the tutorial in class.
*
* Given the 1024*1024 matrix test case, this program got the best performance
* boost using TILE_WIDTH = 16. This was also suggested in the slide set.
*
* This exercise was executed on a MacBook Pro, with GeForce GT 650M
* Using the CPU matrixMultiplication code, it takes about 18 seconds
* Using this TILED approach, it only take about 0.13 ~0.15 seconds
*
* See also:
* Zhou Bin@ Nvidia & USTC, 2014, October, "CUDA Programming (2)" Lecture Slides
*
*
*/
#include "stdio.h"
#include "stdlib.h"
#include "hip/hip_runtime.h"
#define W 1024
#define TILE_WIDTH 16
#define DEBUG 1
void printMatrix(float *Matrix)
{
const int MAX_SIZE_PRINTED = 4;
printf("This is a %d by %d matrix.\n", W,W);
if (W > MAX_SIZE_PRINTED) {
printf("Actual displayed size is cut in 2 parts shown as");
printf(" %d by %d matrix.\n", MAX_SIZE_PRINTED, MAX_SIZE_PRINTED);
printf(" The Top_LEFT CORNER OF the %d * %d matrix:\n", W, W);
}
for(int i=0;i<W;i++)
{
for(int j=0;j<W;j++)
if(i < MAX_SIZE_PRINTED && j < MAX_SIZE_PRINTED){
if (DEBUG) printf("%5.2f ",*(Matrix+i*W+j));
}
if(i < MAX_SIZE_PRINTED && DEBUG) printf("\n");
}
if (W > MAX_SIZE_PRINTED){
printf(" The LOWER_RIGHT CORNER OF the %d * %d matrix\n", W, W);
for(int i=W-MAX_SIZE_PRINTED;i<W;i++)
{
for(int j=W-MAX_SIZE_PRINTED;j<W;j++)
if (DEBUG) printf("%5.2f ",*(Matrix+i*W+j));
if(DEBUG) printf("\n");
}
}
}
/*
* This code is mostly copied from the slide set with some comments written by Ben Koo.
*
* In this test case, W = 1024, TILE_WIDTH = 16, making the dimGrid = 64 * 64
* Within each block, there are 16 * 16 threads.
*
*
*/
__global__ void matrixMulKernel_usingTile(float* Md, float* Nd, float* Pd, int Width)
{
//This delcares the device memory as 16 * 16 float matrices
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
// When W = 1024,t he block IDs (x * y) should be (64 * 64)
int bx = blockIdx.x; int by = blockIdx.y;
// When W = 1024, the thread IDs (x * y) should be (16 * 16)
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float PValue = 0;
// When W = 1024, m should go from 0 to 63
for (int m =0; m < Width/TILE_WIDTH; ++m){
// The following memory access takes place in shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH+ty)*Width];
//Make sure that all data are written in sync.
__syncthreads();
//Perform TILE level matrix multiplication and addition in synchrony.
for (int k = 0; k< TILE_WIDTH; ++k)
PValue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
//Take individually caldulated PValue and place it to the Pd (device memory array).
Pd[Row * Width + Col] = PValue;
}
int main()
{
int sNo = 0;
hipSetDevice(sNo%8);
int size = W*W*sizeof(float);
float *M,*N,*P;
float *d_M,*d_N,*d_P;
M = (float *) malloc(size);
N = (float *) malloc(size);
P = (float *) malloc(size);
hipMalloc((void **)&d_M,size);
hipMalloc((void **)&d_N,size);
hipMalloc((void **)&d_P,size);
//Populate initial values to the M, N and P matrices
for(int i=0;i<W*W;i++)
{
*(M+i) = i;
*(N+i) = i+1;
*(P+i) = 0;
}
hipMemcpy(d_M, M,size,hipMemcpyHostToDevice);
hipMemcpy(d_N, N,size,hipMemcpyHostToDevice);
//Starting from here, set up CUDA timing mechanism
float time_elapsed = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
dim3 dimGrid(W /TILE_WIDTH, W / TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
matrixMulKernel_usingTile<<< dimGrid, dimBlock >>>(d_M,d_N,d_P,W);
hipEventRecord(stop,0);
hipEventSynchronize(start);
hipEventSynchronize(stop);
//The following function returns time_elapsed using milli-seconds as time units
hipEventElapsedTime(&time_elapsed, start, stop);
//Finished timing for CUDA execution
//To display time_elapsed into a number, divide it by 1000 first.
printf("\n\nGPU Elapsed Time:%f\n", time_elapsed/1000);
hipMemcpy(P,d_P,size,hipMemcpyDeviceToHost);
printMatrix(P);
free(M);free(N);free(P);
hipFree(d_M);hipFree(d_N);hipFree(d_P);
return 0;
} | .text
.file "Tiled_MatrixMul.hip"
.globl _Z11printMatrixPf # -- Begin function _Z11printMatrixPf
.p2align 4, 0x90
.type _Z11printMatrixPf,@function
_Z11printMatrixPf: # @_Z11printMatrixPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r14d, %r14d
movl $.L.str, %edi
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl $4, %esi
movl $4, %edx
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
movq %rbx, %r15
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_1 Depth=1
incq %r14
addq $4096, %r15 # imm = 0x1000
cmpq $1024, %r14 # imm = 0x400
je .LBB0_8
.LBB0_1: # %.preheader21
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %r12d, %r12d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=2
incq %r12
cmpq $1024, %r12 # imm = 0x400
je .LBB0_5
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %r12d, %eax
orl %r14d, %eax
testl $-4, %eax
jne .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=2
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_5: # in Loop: Header=BB0_1 Depth=1
cmpq $4, %r14
jae .LBB0_7
# %bb.6: # in Loop: Header=BB0_1 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB0_7
.LBB0_8:
movl $.L.str.6, %edi
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
addq $4182000, %rbx # imm = 0x3FCFF0
movl $1020, %r14d # imm = 0x3FC
.p2align 4, 0x90
.LBB0_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_10 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_10: # Parent Loop BB0_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
incq %r15
cmpq $4, %r15
jne .LBB0_10
# %bb.11: # in Loop: Header=BB0_9 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $4096, %rbx # imm = 0x1000
cmpq $1024, %r14 # imm = 0x400
jne .LBB0_9
# %bb.12:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11printMatrixPf, .Lfunc_end0-_Z11printMatrixPf
.cfi_endproc
# -- End function
.globl _Z40__device_stub__matrixMulKernel_usingTilePfS_S_i # -- Begin function _Z40__device_stub__matrixMulKernel_usingTilePfS_S_i
.p2align 4, 0x90
.type _Z40__device_stub__matrixMulKernel_usingTilePfS_S_i,@function
_Z40__device_stub__matrixMulKernel_usingTilePfS_S_i: # @_Z40__device_stub__matrixMulKernel_usingTilePfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25matrixMulKernel_usingTilePfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z40__device_stub__matrixMulKernel_usingTilePfS_S_i, .Lfunc_end1-_Z40__device_stub__matrixMulKernel_usingTilePfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r12d, %r12d
xorl %edi, %edi
callq hipSetDevice
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
leaq 40(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
leaq 1(%r12), %rax
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
movss %xmm0, (%rbx,%r12,4)
movss %xmm1, (%r14,%r12,4)
movq %rax, %r12
cmpq $1048576, %rax # imm = 0x100000
jne .LBB2_1
# %bb.2:
movq 40(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $0, 4(%rsp)
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $1024, 52(%rsp) # imm = 0x400
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z25matrixMulKernel_usingTilePfS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r15, %rdi
callq _Z11printMatrixPf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25matrixMulKernel_usingTilePfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "This is a %d by %d matrix.\n"
.size .L.str, 28
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Actual displayed size is cut in 2 parts shown as"
.size .L.str.1, 49
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " %d by %d matrix.\n"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " The Top_LEFT CORNER OF the %d * %d matrix:\n"
.size .L.str.3, 47
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%5.2f "
.size .L.str.4, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " The LOWER_RIGHT CORNER OF the %d * %d matrix\n"
.size .L.str.6, 49
.type _Z25matrixMulKernel_usingTilePfS_S_i,@object # @_Z25matrixMulKernel_usingTilePfS_S_i
.section .rodata,"a",@progbits
.globl _Z25matrixMulKernel_usingTilePfS_S_i
.p2align 3, 0x0
_Z25matrixMulKernel_usingTilePfS_S_i:
.quad _Z40__device_stub__matrixMulKernel_usingTilePfS_S_i
.size _Z25matrixMulKernel_usingTilePfS_S_i, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "\n\nGPU Elapsed Time:%f\n"
.size .L.str.7, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z25matrixMulKernel_usingTilePfS_S_i"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__matrixMulKernel_usingTilePfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25matrixMulKernel_usingTilePfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25matrixMulKernel_usingTilePfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ MOV R19, c[0x0][0x178] ; /* 0x00005e0000137a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R17, SR_TID.Y ; /* 0x0000000000117919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R19, 0x10, PT ; /* 0x000000101300780c */
/* 0x000fe20003f06270 */
/*0070*/ HFMA2.MMA R23, -RZ, RZ, 0, 0 ; /* 0x00000000ff177435 */
/* 0x000fe400000001ff */
/*0080*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e680000002500 */
/*0090*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*00a0*/ LEA R5, R5, R17, 0x4 ; /* 0x0000001105057211 */
/* 0x001fc400078e20ff */
/*00b0*/ LEA R2, R7, R0, 0x4 ; /* 0x0000000007027211 */
/* 0x002fca00078e20ff */
/*00c0*/ IMAD R2, R5, c[0x0][0x178], R2 ; /* 0x00005e0005027a24 */
/* 0x000fc800078e0202 */
/*00d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0203 */
/*00e0*/ @!P0 BRA 0x4f0 ; /* 0x0000040000008947 */
/* 0x000fea0003800000 */
/*00f0*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD R14, R5, c[0x0][0x178], R0.reuse ; /* 0x00005e00050e7a24 */
/* 0x100fe200078e0200 */
/*0110*/ SHF.R.S32.HI R5, RZ, 0x1f, R19 ; /* 0x0000001fff057819 */
/* 0x000fe20000011413 */
/*0120*/ IMAD R4, R17.reuse, c[0x0][0x178], R0 ; /* 0x00005e0011047a24 */
/* 0x040fe200078e0200 */
/*0130*/ SHF.L.U32 R17, R17, 0x6, RZ ; /* 0x0000000611117819 */
/* 0x000fe200000006ff */
/*0140*/ IMAD.WIDE R14, R14, R13, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fe200078e020d */
/*0150*/ LEA.HI R5, R5, c[0x0][0x178], RZ, 0x4 ; /* 0x00005e0005057a11 */
/* 0x000fe200078f20ff */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0170*/ LEA R4, R7, R4, 0x4 ; /* 0x0000000407047211 */
/* 0x000fe400078e20ff */
/*0180*/ MOV R21, R15 ; /* 0x0000000f00157202 */
/* 0x000fc40000000f00 */
/*0190*/ SHF.L.U32 R19, R19, 0x4, RZ ; /* 0x0000000413137819 */
/* 0x000fe200000006ff */
/*01a0*/ IMAD.WIDE R12, R4, R13, c[0x0][0x168] ; /* 0x00005a00040c7625 */
/* 0x000fe200078e020d */
/*01b0*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fe40000000f00 */
/*01c0*/ LEA R16, R0, R17, 0x2 ; /* 0x0000001100107211 */
/* 0x000fe400078e10ff */
/*01d0*/ SHF.R.S32.HI R15, RZ, 0x4, R5 ; /* 0x00000004ff0f7819 */
/* 0x000fe40000011405 */
/*01e0*/ MOV R20, R14 ; /* 0x0000000e00147202 */
/* 0x000fe20000000f00 */
/*01f0*/ LDG.E R24, [R12.64] ; /* 0x000000060c187981 */
/* 0x0000a8000c1e1900 */
/*0200*/ LDG.E R27, [R20.64] ; /* 0x00000006141b7981 */
/* 0x0002e2000c1e1900 */
/*0210*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0220*/ IADD3 R14, P1, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x000fe20007f3e0ff */
/*0230*/ IMAD.WIDE R12, R19, 0x4, R12 ; /* 0x00000004130c7825 */
/* 0x001fc800078e020c */
/*0240*/ ISETP.LE.AND P0, PT, R15, UR4, PT ; /* 0x000000040f007c0c */
/* 0x000fe4000bf03270 */
/*0250*/ IADD3.X R21, RZ, R21, RZ, P1, !PT ; /* 0x00000015ff157210 */
/* 0x002fe20000ffe4ff */
/*0260*/ STS [R16+0x400], R24 ; /* 0x0004001810007388 */
/* 0x004fe80000000800 */
/*0270*/ STS [R16], R27 ; /* 0x0000001b10007388 */
/* 0x008fe80000000800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ LDS R26, [R0.X4+0x400] ; /* 0x00040000001a7984 */
/* 0x000fe80000004800 */
/*02a0*/ LDS.128 R8, [R17] ; /* 0x0000000011087984 */
/* 0x000e280000000c00 */
/*02b0*/ LDS R28, [R0.X4+0x440] ; /* 0x00044000001c7984 */
/* 0x000e680000004800 */
/*02c0*/ LDS R29, [R0.X4+0x480] ; /* 0x00048000001d7984 */
/* 0x000ea80000004800 */
/*02d0*/ LDS R22, [R0.X4+0x4c0] ; /* 0x0004c00000167984 */
/* 0x000ee80000004800 */
/*02e0*/ LDS R25, [R0.X4+0x500] ; /* 0x0005000000197984 */
/* 0x000fe80000004800 */
/*02f0*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000f280000000c00 */
/*0300*/ LDS R18, [R0.X4+0x540] ; /* 0x0005400000127984 */
/* 0x000f680000004800 */
/*0310*/ LDS R27, [R0.X4+0x580] ; /* 0x00058000001b7984 */
/* 0x000f680000004800 */
/*0320*/ LDS R20, [R0.X4+0x5c0] ; /* 0x0005c00000147984 */
/* 0x000f620000004800 */
/*0330*/ FFMA R8, R26, R8, R23 ; /* 0x000000081a087223 */
/* 0x001fc60000000017 */
/*0340*/ LDS R23, [R0.X4+0x600] ; /* 0x0006000000177984 */
/* 0x000fe20000004800 */
/*0350*/ FFMA R8, R28, R9, R8 ; /* 0x000000091c087223 */
/* 0x002fc80000000008 */
/*0360*/ FFMA R8, R29, R10, R8 ; /* 0x0000000a1d087223 */
/* 0x004fc80000000008 */
/*0370*/ FFMA R22, R22, R11, R8 ; /* 0x0000000b16167223 */
/* 0x008fe40000000008 */
/*0380*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e240000000c00 */
/*0390*/ FFMA R4, R25, R4, R22 ; /* 0x0000000419047223 */
/* 0x010fe40000000016 */
/*03a0*/ LDS R22, [R0.X4+0x640] ; /* 0x0006400000167984 */
/* 0x000e640000004800 */
/*03b0*/ FFMA R4, R18, R5, R4 ; /* 0x0000000512047223 */
/* 0x020fe40000000004 */
/*03c0*/ LDS R25, [R0.X4+0x680] ; /* 0x0006800000197984 */
/* 0x000ea40000004800 */
/*03d0*/ FFMA R4, R27, R6, R4 ; /* 0x000000061b047223 */
/* 0x000fc40000000004 */
/*03e0*/ LDS R18, [R0.X4+0x6c0] ; /* 0x0006c00000127984 */
/* 0x000ee40000004800 */
/*03f0*/ FFMA R24, R20, R7, R4 ; /* 0x0000000714187223 */
/* 0x000fe40000000004 */
/*0400*/ LDS R27, [R0.X4+0x700] ; /* 0x00070000001b7984 */
/* 0x000fe80000004800 */
/*0410*/ LDS.128 R4, [R17+0x30] ; /* 0x0000300011047984 */
/* 0x000f280000000c00 */
/*0420*/ LDS R20, [R0.X4+0x740] ; /* 0x0007400000147984 */
/* 0x000f620000004800 */
/*0430*/ FFMA R24, R23, R8, R24 ; /* 0x0000000817187223 */
/* 0x001fc60000000018 */
/*0440*/ LDS R23, [R0.X4+0x780] ; /* 0x0007800000177984 */
/* 0x000e280000004800 */
/*0450*/ LDS R8, [R0.X4+0x7c0] ; /* 0x0007c00000087984 */
/* 0x000e220000004800 */
/*0460*/ FFMA R9, R22, R9, R24 ; /* 0x0000000916097223 */
/* 0x002fc80000000018 */
/*0470*/ FFMA R9, R25, R10, R9 ; /* 0x0000000a19097223 */
/* 0x004fc80000000009 */
/*0480*/ FFMA R9, R18, R11, R9 ; /* 0x0000000b12097223 */
/* 0x008fc80000000009 */
/*0490*/ FFMA R4, R27, R4, R9 ; /* 0x000000041b047223 */
/* 0x010fc80000000009 */
/*04a0*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fc80000000004 */
/*04b0*/ FFMA R23, R23, R6, R4 ; /* 0x0000000617177223 */
/* 0x001fc80000000004 */
/*04c0*/ FFMA R23, R8, R7, R23 ; /* 0x0000000708177223 */
/* 0x000fe20000000017 */
/*04d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04e0*/ @!P0 BRA 0x1e0 ; /* 0xfffffcf000008947 */
/* 0x000fea000383ffff */
/*04f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe2000c101906 */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25matrixMulKernel_usingTilePfS_S_i
.globl _Z25matrixMulKernel_usingTilePfS_S_i
.p2align 8
.type _Z25matrixMulKernel_usingTilePfS_S_i,@function
_Z25matrixMulKernel_usingTilePfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 4, v5
v_lshl_add_u32 v0, s14, 4, v3
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 16
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v8, 2, v3
v_lshlrev_b32_e32 v6, 6, v5
s_ashr_i32 s3, s2, 31
v_mad_u64_u32 v[1:2], null, v4, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, 0x400, v8
s_lshr_b32 s3, s3, 28
v_add_nc_u32_e32 v3, v6, v8
s_add_i32 s3, s2, s3
v_add_nc_u32_e32 v8, v7, v6
s_ashr_i32 s3, s3, 4
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s9, s8, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, s9, v5
v_add_nc_u32_e32 v9, s9, v1
s_mov_b32 s9, 0
v_mad_u64_u32 v[11:12], null, v10, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v7
s_waitcnt vmcnt(1)
ds_store_b32 v3, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s9, v6
s_add_i32 s9, s9, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 64, v9
s_cmp_eq_u32 s9, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v10, v11
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v4, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25matrixMulKernel_usingTilePfS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25matrixMulKernel_usingTilePfS_S_i, .Lfunc_end0-_Z25matrixMulKernel_usingTilePfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25matrixMulKernel_usingTilePfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25matrixMulKernel_usingTilePfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001056b_00000000-6_Tiled_MatrixMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "This is a %d by %d matrix.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Actual displayed size is cut in 2 parts shown as"
.section .rodata.str1.1
.LC2:
.string " %d by %d matrix.\n"
.section .rodata.str1.8
.align 8
.LC3:
.string " The Top_LEFT CORNER OF the %d * %d matrix:\n"
.section .rodata.str1.1
.LC4:
.string "%5.2f "
.LC5:
.string "\n"
.section .rodata.str1.8
.align 8
.LC6:
.string " The LOWER_RIGHT CORNER OF the %d * %d matrix\n"
.text
.globl _Z11printMatrixPf
.type _Z11printMatrixPf, @function
_Z11printMatrixPf:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r14
movl $1024, %ecx
movl $1024, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, %ecx
movl $4, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, %ecx
movl $1024, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %r12
movl $0, %ebp
leaq .LC4(%rip), %r13
jmp .L4
.L5:
addq $1, %rbx
cmpq $1024, %rbx
je .L16
.L10:
movl %ebp, %eax
cmpl $3, %ebp
jg .L5
cmpl $3, %ebx
jg .L5
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
jmp .L10
.L16:
cmpl $3, %eax
jle .L17
addq $1, %rbp
addq $4096, %r12
cmpq $1024, %rbp
je .L9
.L4:
movl $0, %ebx
jmp .L10
.L17:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbp
addq $4096, %r12
jmp .L4
.L9:
movl $1024, %ecx
movl $1024, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 4177936(%r14), %rbx
movl $1044480, %r12d
leaq .LC4(%rip), %r14
leaq .LC5(%rip), %r13
.L11:
leaq -16(%rbx), %rbp
.L12:
pxor %xmm0, %xmm0
cvtss2sd 4080(%rbp), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %rbx, %rbp
jne .L12
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1024, %r12
addq $4096, %rbx
cmpq $1048576, %r12
jne .L11
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixPf, .-_Z11printMatrixPf
.globl _Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i
.type _Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i, @function
_Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25matrixMulKernel_usingTilePfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i, .-_Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i
.globl _Z25matrixMulKernel_usingTilePfS_S_i
.type _Z25matrixMulKernel_usingTilePfS_S_i, @function
_Z25matrixMulKernel_usingTilePfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z25matrixMulKernel_usingTilePfS_S_i, .-_Z25matrixMulKernel_usingTilePfS_S_i
.section .rodata.str1.1
.LC9:
.string "\n\nGPU Elapsed Time:%f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $0, %eax
.L27:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rax,4)
leal 1(%rax), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
movl $0x00000000, (%rbx,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L27
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 4(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $64, 48(%rsp)
movl $64, 52(%rsp)
movl $16, 60(%rsp)
movl $16, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 4(%rsp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdi
call _Z11printMatrixPf
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z50__device_stub__Z25matrixMulKernel_usingTilePfS_S_iPfS_S_i
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC10:
.string "_Z25matrixMulKernel_usingTilePfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z25matrixMulKernel_usingTilePfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC8:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Tiled_MatrixMul.hip"
.globl _Z11printMatrixPf # -- Begin function _Z11printMatrixPf
.p2align 4, 0x90
.type _Z11printMatrixPf,@function
_Z11printMatrixPf: # @_Z11printMatrixPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r14d, %r14d
movl $.L.str, %edi
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl $4, %esi
movl $4, %edx
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
movq %rbx, %r15
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_1 Depth=1
incq %r14
addq $4096, %r15 # imm = 0x1000
cmpq $1024, %r14 # imm = 0x400
je .LBB0_8
.LBB0_1: # %.preheader21
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %r12d, %r12d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=2
incq %r12
cmpq $1024, %r12 # imm = 0x400
je .LBB0_5
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %r12d, %eax
orl %r14d, %eax
testl $-4, %eax
jne .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=2
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_5: # in Loop: Header=BB0_1 Depth=1
cmpq $4, %r14
jae .LBB0_7
# %bb.6: # in Loop: Header=BB0_1 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB0_7
.LBB0_8:
movl $.L.str.6, %edi
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
addq $4182000, %rbx # imm = 0x3FCFF0
movl $1020, %r14d # imm = 0x3FC
.p2align 4, 0x90
.LBB0_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_10 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_10: # Parent Loop BB0_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
incq %r15
cmpq $4, %r15
jne .LBB0_10
# %bb.11: # in Loop: Header=BB0_9 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $4096, %rbx # imm = 0x1000
cmpq $1024, %r14 # imm = 0x400
jne .LBB0_9
# %bb.12:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11printMatrixPf, .Lfunc_end0-_Z11printMatrixPf
.cfi_endproc
# -- End function
.globl _Z40__device_stub__matrixMulKernel_usingTilePfS_S_i # -- Begin function _Z40__device_stub__matrixMulKernel_usingTilePfS_S_i
.p2align 4, 0x90
.type _Z40__device_stub__matrixMulKernel_usingTilePfS_S_i,@function
_Z40__device_stub__matrixMulKernel_usingTilePfS_S_i: # @_Z40__device_stub__matrixMulKernel_usingTilePfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25matrixMulKernel_usingTilePfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z40__device_stub__matrixMulKernel_usingTilePfS_S_i, .Lfunc_end1-_Z40__device_stub__matrixMulKernel_usingTilePfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r12d, %r12d
xorl %edi, %edi
callq hipSetDevice
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
leaq 40(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
leaq 1(%r12), %rax
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
movss %xmm0, (%rbx,%r12,4)
movss %xmm1, (%r14,%r12,4)
movq %rax, %r12
cmpq $1048576, %rax # imm = 0x100000
jne .LBB2_1
# %bb.2:
movq 40(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $0, 4(%rsp)
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $1024, 52(%rsp) # imm = 0x400
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z25matrixMulKernel_usingTilePfS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r15, %rdi
callq _Z11printMatrixPf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25matrixMulKernel_usingTilePfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "This is a %d by %d matrix.\n"
.size .L.str, 28
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Actual displayed size is cut in 2 parts shown as"
.size .L.str.1, 49
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " %d by %d matrix.\n"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " The Top_LEFT CORNER OF the %d * %d matrix:\n"
.size .L.str.3, 47
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%5.2f "
.size .L.str.4, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " The LOWER_RIGHT CORNER OF the %d * %d matrix\n"
.size .L.str.6, 49
.type _Z25matrixMulKernel_usingTilePfS_S_i,@object # @_Z25matrixMulKernel_usingTilePfS_S_i
.section .rodata,"a",@progbits
.globl _Z25matrixMulKernel_usingTilePfS_S_i
.p2align 3, 0x0
_Z25matrixMulKernel_usingTilePfS_S_i:
.quad _Z40__device_stub__matrixMulKernel_usingTilePfS_S_i
.size _Z25matrixMulKernel_usingTilePfS_S_i, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "\n\nGPU Elapsed Time:%f\n"
.size .L.str.7, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z25matrixMulKernel_usingTilePfS_S_i"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__matrixMulKernel_usingTilePfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25matrixMulKernel_usingTilePfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime_api.h>
__global__ void cuda_sum_kernel(float *a, float *b, float *c, size_t size)
{
size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size) {
return;
}
c[idx] = a[idx] + b[idx];
}
extern "C" {
void cuda_sum(float *a, float *b, float *c, size_t size)
{
float *d_a, *d_b, *d_c;
cudaMalloc((void **)&d_a, size * sizeof(float));
cudaMalloc((void **)&d_b, size * sizeof(float));
cudaMalloc((void **)&d_c, size * sizeof(float));
cudaMemcpy(d_a, a, size * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size * sizeof(float), cudaMemcpyHostToDevice);
cuda_sum_kernel <<< ceil(size / 256.0), 256 >>> (d_a, d_b, d_c, size);
cudaMemcpy(c, d_c, size * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
}
} | code for sm_80
Function : _Z15cuda_sum_kernelPfS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.SHL.U32 R6, R0, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x000fe200078e00ff */
/*0080*/ SHF.R.U32.HI R0, RZ, 0x1e, R0 ; /* 0x0000001eff007819 */
/* 0x000fe20000011600 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IADD3 R4, P0, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x040fe40007f1e0ff */
/*00b0*/ IADD3 R2, P1, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x000fe40007f3e0ff */
/*00c0*/ IADD3.X R5, R0.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000057a10 */
/* 0x040fe400007fe4ff */
/*00d0*/ IADD3.X R3, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000037a10 */
/* 0x000fc80000ffe4ff */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fc80007f1e0ff */
/*0110*/ IADD3.X R7, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000077a10 */
/* 0x000fe200007fe4ff */
/*0120*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime_api.h>
__global__ void cuda_sum_kernel(float *a, float *b, float *c, size_t size)
{
size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size) {
return;
}
c[idx] = a[idx] + b[idx];
}
extern "C" {
void cuda_sum(float *a, float *b, float *c, size_t size)
{
float *d_a, *d_b, *d_c;
cudaMalloc((void **)&d_a, size * sizeof(float));
cudaMalloc((void **)&d_b, size * sizeof(float));
cudaMalloc((void **)&d_c, size * sizeof(float));
cudaMemcpy(d_a, a, size * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size * sizeof(float), cudaMemcpyHostToDevice);
cuda_sum_kernel <<< ceil(size / 256.0), 256 >>> (d_a, d_b, d_c, size);
cudaMemcpy(c, d_c, size * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
}
} | .file "tmpxft_000ef347_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15cuda_sum_kernelPfS_S_mPfS_S_m
.type _Z40__device_stub__Z15cuda_sum_kernelPfS_S_mPfS_S_m, @function
_Z40__device_stub__Z15cuda_sum_kernelPfS_S_mPfS_S_m:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15cuda_sum_kernelPfS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z40__device_stub__Z15cuda_sum_kernelPfS_S_mPfS_S_m, .-_Z40__device_stub__Z15cuda_sum_kernelPfS_S_mPfS_S_m
.globl _Z15cuda_sum_kernelPfS_S_m
.type _Z15cuda_sum_kernelPfS_S_m, @function
_Z15cuda_sum_kernelPfS_S_m:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15cuda_sum_kernelPfS_S_mPfS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z15cuda_sum_kernelPfS_S_m, .-_Z15cuda_sum_kernelPfS_S_m
.globl cuda_sum
.type cuda_sum, @function
cuda_sum:
.LFB2027:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movq %rcx, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 0(,%rcx,4), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
testq %rbp, %rbp
js .L12
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
.L13:
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L14
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L14:
cvttsd2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L15:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq %rbp, %rax
shrq %rax
movq %rbp, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L13
.L18:
movq %rbp, %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z15cuda_sum_kernelPfS_S_mPfS_S_m
jmp .L15
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size cuda_sum, .-cuda_sum
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z15cuda_sum_kernelPfS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15cuda_sum_kernelPfS_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1064304640
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime_api.h>
__global__ void cuda_sum_kernel(float *a, float *b, float *c, size_t size)
{
size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size) {
return;
}
c[idx] = a[idx] + b[idx];
}
extern "C" {
void cuda_sum(float *a, float *b, float *c, size_t size)
{
float *d_a, *d_b, *d_c;
cudaMalloc((void **)&d_a, size * sizeof(float));
cudaMalloc((void **)&d_b, size * sizeof(float));
cudaMalloc((void **)&d_c, size * sizeof(float));
cudaMemcpy(d_a, a, size * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size * sizeof(float), cudaMemcpyHostToDevice);
cuda_sum_kernel <<< ceil(size / 256.0), 256 >>> (d_a, d_b, d_c, size);
cudaMemcpy(c, d_c, size * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
}
} | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
__global__ void cuda_sum_kernel(float *a, float *b, float *c, size_t size)
{
size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size) {
return;
}
c[idx] = a[idx] + b[idx];
}
extern "C" {
void cuda_sum(float *a, float *b, float *c, size_t size)
{
float *d_a, *d_b, *d_c;
hipMalloc((void **)&d_a, size * sizeof(float));
hipMalloc((void **)&d_b, size * sizeof(float));
hipMalloc((void **)&d_c, size * sizeof(float));
hipMemcpy(d_a, a, size * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size * sizeof(float), hipMemcpyHostToDevice);
cuda_sum_kernel <<< ceil(size / 256.0), 256 >>> (d_a, d_b, d_c, size);
hipMemcpy(c, d_c, size * sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
__global__ void cuda_sum_kernel(float *a, float *b, float *c, size_t size)
{
size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size) {
return;
}
c[idx] = a[idx] + b[idx];
}
extern "C" {
void cuda_sum(float *a, float *b, float *c, size_t size)
{
float *d_a, *d_b, *d_c;
hipMalloc((void **)&d_a, size * sizeof(float));
hipMalloc((void **)&d_b, size * sizeof(float));
hipMalloc((void **)&d_c, size * sizeof(float));
hipMemcpy(d_a, a, size * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size * sizeof(float), hipMemcpyHostToDevice);
cuda_sum_kernel <<< ceil(size / 256.0), 256 >>> (d_a, d_b, d_c, size);
hipMemcpy(c, d_c, size * sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15cuda_sum_kernelPfS_S_m
.globl _Z15cuda_sum_kernelPfS_S_m
.p2align 8
.type _Z15cuda_sum_kernelPfS_S_m,@function
_Z15cuda_sum_kernelPfS_S_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15cuda_sum_kernelPfS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15cuda_sum_kernelPfS_S_m, .Lfunc_end0-_Z15cuda_sum_kernelPfS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15cuda_sum_kernelPfS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15cuda_sum_kernelPfS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
__global__ void cuda_sum_kernel(float *a, float *b, float *c, size_t size)
{
size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size) {
return;
}
c[idx] = a[idx] + b[idx];
}
extern "C" {
void cuda_sum(float *a, float *b, float *c, size_t size)
{
float *d_a, *d_b, *d_c;
hipMalloc((void **)&d_a, size * sizeof(float));
hipMalloc((void **)&d_b, size * sizeof(float));
hipMalloc((void **)&d_c, size * sizeof(float));
hipMemcpy(d_a, a, size * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size * sizeof(float), hipMemcpyHostToDevice);
cuda_sum_kernel <<< ceil(size / 256.0), 256 >>> (d_a, d_b, d_c, size);
hipMemcpy(c, d_c, size * sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
}
} | .text
.file "test.hip"
.globl _Z30__device_stub__cuda_sum_kernelPfS_S_m # -- Begin function _Z30__device_stub__cuda_sum_kernelPfS_S_m
.p2align 4, 0x90
.type _Z30__device_stub__cuda_sum_kernelPfS_S_m,@function
_Z30__device_stub__cuda_sum_kernelPfS_S_m: # @_Z30__device_stub__cuda_sum_kernelPfS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15cuda_sum_kernelPfS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__cuda_sum_kernelPfS_S_m, .Lfunc_end0-_Z30__device_stub__cuda_sum_kernelPfS_S_m
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function cuda_sum
.LCPI1_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI1_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl cuda_sum
.p2align 4, 0x90
.type cuda_sum,@function
cuda_sum: # @cuda_sum
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r15
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
leaq (,%rcx,4), %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, %xmm1
punpckldq .LCPI1_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI1_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI1_2(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq %r15, 80(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15cuda_sum_kernelPfS_S_m, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size cuda_sum, .Lfunc_end1-cuda_sum
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15cuda_sum_kernelPfS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15cuda_sum_kernelPfS_S_m,@object # @_Z15cuda_sum_kernelPfS_S_m
.section .rodata,"a",@progbits
.globl _Z15cuda_sum_kernelPfS_S_m
.p2align 3, 0x0
_Z15cuda_sum_kernelPfS_S_m:
.quad _Z30__device_stub__cuda_sum_kernelPfS_S_m
.size _Z15cuda_sum_kernelPfS_S_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15cuda_sum_kernelPfS_S_m"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__cuda_sum_kernelPfS_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15cuda_sum_kernelPfS_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15cuda_sum_kernelPfS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.SHL.U32 R6, R0, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x000fe200078e00ff */
/*0080*/ SHF.R.U32.HI R0, RZ, 0x1e, R0 ; /* 0x0000001eff007819 */
/* 0x000fe20000011600 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IADD3 R4, P0, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x040fe40007f1e0ff */
/*00b0*/ IADD3 R2, P1, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x000fe40007f3e0ff */
/*00c0*/ IADD3.X R5, R0.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000057a10 */
/* 0x040fe400007fe4ff */
/*00d0*/ IADD3.X R3, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000037a10 */
/* 0x000fc80000ffe4ff */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fc80007f1e0ff */
/*0110*/ IADD3.X R7, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000077a10 */
/* 0x000fe200007fe4ff */
/*0120*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15cuda_sum_kernelPfS_S_m
.globl _Z15cuda_sum_kernelPfS_S_m
.p2align 8
.type _Z15cuda_sum_kernelPfS_S_m,@function
_Z15cuda_sum_kernelPfS_S_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15cuda_sum_kernelPfS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15cuda_sum_kernelPfS_S_m, .Lfunc_end0-_Z15cuda_sum_kernelPfS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15cuda_sum_kernelPfS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15cuda_sum_kernelPfS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ef347_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15cuda_sum_kernelPfS_S_mPfS_S_m
.type _Z40__device_stub__Z15cuda_sum_kernelPfS_S_mPfS_S_m, @function
_Z40__device_stub__Z15cuda_sum_kernelPfS_S_mPfS_S_m:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15cuda_sum_kernelPfS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z40__device_stub__Z15cuda_sum_kernelPfS_S_mPfS_S_m, .-_Z40__device_stub__Z15cuda_sum_kernelPfS_S_mPfS_S_m
.globl _Z15cuda_sum_kernelPfS_S_m
.type _Z15cuda_sum_kernelPfS_S_m, @function
_Z15cuda_sum_kernelPfS_S_m:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15cuda_sum_kernelPfS_S_mPfS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z15cuda_sum_kernelPfS_S_m, .-_Z15cuda_sum_kernelPfS_S_m
.globl cuda_sum
.type cuda_sum, @function
cuda_sum:
.LFB2027:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movq %rcx, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 0(,%rcx,4), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
testq %rbp, %rbp
js .L12
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
.L13:
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L14
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L14:
cvttsd2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L15:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq %rbp, %rax
shrq %rax
movq %rbp, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L13
.L18:
movq %rbp, %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z15cuda_sum_kernelPfS_S_mPfS_S_m
jmp .L15
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size cuda_sum, .-cuda_sum
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z15cuda_sum_kernelPfS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15cuda_sum_kernelPfS_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1064304640
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z30__device_stub__cuda_sum_kernelPfS_S_m # -- Begin function _Z30__device_stub__cuda_sum_kernelPfS_S_m
.p2align 4, 0x90
.type _Z30__device_stub__cuda_sum_kernelPfS_S_m,@function
_Z30__device_stub__cuda_sum_kernelPfS_S_m: # @_Z30__device_stub__cuda_sum_kernelPfS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15cuda_sum_kernelPfS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__cuda_sum_kernelPfS_S_m, .Lfunc_end0-_Z30__device_stub__cuda_sum_kernelPfS_S_m
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function cuda_sum
.LCPI1_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI1_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl cuda_sum
.p2align 4, 0x90
.type cuda_sum,@function
cuda_sum: # @cuda_sum
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r15
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
leaq (,%rcx,4), %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, %xmm1
punpckldq .LCPI1_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI1_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI1_2(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq %r15, 80(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15cuda_sum_kernelPfS_S_m, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size cuda_sum, .Lfunc_end1-cuda_sum
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15cuda_sum_kernelPfS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15cuda_sum_kernelPfS_S_m,@object # @_Z15cuda_sum_kernelPfS_S_m
.section .rodata,"a",@progbits
.globl _Z15cuda_sum_kernelPfS_S_m
.p2align 3, 0x0
_Z15cuda_sum_kernelPfS_S_m:
.quad _Z30__device_stub__cuda_sum_kernelPfS_S_m
.size _Z15cuda_sum_kernelPfS_S_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15cuda_sum_kernelPfS_S_m"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__cuda_sum_kernelPfS_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15cuda_sum_kernelPfS_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void find_all_sums_hub_kernel(int* hub, int nhub, double *node_weight, int *neighbor, int *neighbor_start, double *sum_weight_result){
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < nhub) {
int nid = hub[x];
double sum = 0.0;
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid+1]; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
}
sum_weight_result[nid] = sum;
}
} | code for sm_80
Function : _Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R6, R7, R4, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fca00078e0204 */
/*0090*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD.WIDE R10, R0, R4, c[0x0][0x180] ; /* 0x00006000000a7625 */
/* 0x004fca00078e0204 */
/*00b0*/ LDG.E R5, [R10.64] ; /* 0x000000040a057981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R2, [R10.64+0x4] ; /* 0x000004040a027981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ BSSY B0, 0xbf0 ; /* 0x00000b1000007945 */
/* 0x000fe20003800000 */
/*00e0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*00f0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*0100*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fda0003f06270 */
/*0110*/ @P0 BRA 0xbe0 ; /* 0x00000ac000000947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R7, R5, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x000fe20007ffe0ff */
/*0130*/ BSSY B1, 0x2f0 ; /* 0x000001b000017945 */
/* 0x000fe20003800000 */
/*0140*/ LOP3.LUT R9, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff097212 */
/* 0x000fe400078e33ff */
/*0150*/ IMNMX R6, R2, R7, !PT ; /* 0x0000000702067217 */
/* 0x000fc80007800200 */
/*0160*/ IADD3 R9, R6.reuse, R9, RZ ; /* 0x0000000906097210 */
/* 0x040fe20007ffe0ff */
/*0170*/ IMAD.IADD R7, R6, 0x1, -R5 ; /* 0x0000000106077824 */
/* 0x000fc600078e0a05 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fe40003f06070 */
/*0190*/ LOP3.LUT P1, R10, R7, 0x3, RZ, 0xc0, !PT ; /* 0x00000003070a7812 */
/* 0x000fe2000782c0ff */
/*01a0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0005 */
/*01b0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fd6000001ff00 */
/*01c0*/ @!P1 BRA 0x2e0 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.WIDE R6, R5, R4, c[0x0][0x178] ; /* 0x00005e0005067625 */
/* 0x000fe200078e0204 */
/*01e0*/ MOV R14, R10 ; /* 0x0000000a000e7202 */
/* 0x000fe20000000f00 */
/*01f0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fc6000001ff00 */
/*0200*/ MOV R13, R7 ; /* 0x00000007000d7202 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*0220*/ MOV R12, R6 ; /* 0x00000006000c7202 */
/* 0x000fca0000000f00 */
/*0230*/ LDG.E R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x001ea2000c1e1900 */
/*0240*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*0250*/ IADD3 R14, R14, -0x1, RZ ; /* 0xffffffff0e0e7810 */
/* 0x000fc80007ffe0ff */
/*0260*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fca0003f25270 */
/*0270*/ IMAD.WIDE R10, R10, R11, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x004fcc00078e020b */
/*0280*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*0290*/ IADD3 R6, P2, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f5e0ff */
/*02a0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc60007ffe0ff */
/*02b0*/ IMAD.X R13, RZ, RZ, R13, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe200010e060d */
/*02c0*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x0060620000000008 */
/*02d0*/ @P1 BRA 0x220 ; /* 0xffffff4000001947 */
/* 0x000fea000383ffff */
/*02e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02f0*/ @!P0 BRA 0xbe0 ; /* 0x000008e000008947 */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R6, R2, -R7, RZ ; /* 0x8000000702067210 */
/* 0x000fe20007ffe0ff */
/*0310*/ IMAD.WIDE R4, R7, R4, c[0x0][0x178] ; /* 0x00005e0007047625 */
/* 0x000fe200078e0204 */
/*0320*/ BSSY B1, 0x810 ; /* 0x000004e000017945 */
/* 0x000fe40003800000 */
/*0330*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0340*/ IADD3 R10, P0, R4, 0x8, RZ ; /* 0x00000008040a7810 */
/* 0x001fc80007f1e0ff */
/*0350*/ IADD3.X R11, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff0b7210 */
/* 0x000fe400007fe4ff */
/*0360*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fca0003f0f070 */
/*0370*/ @!P1 BRA 0x800 ; /* 0x0000048000009947 */
/* 0x000fea0003800000 */
/*0380*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0390*/ IADD3 R5, R2, -0xc, RZ ; /* 0xfffffff402057810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ LDG.E R15, [R10.64+-0x8] ; /* 0xfffff8040a0f7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R27, [R10.64+-0x4] ; /* 0xfffffc040a1b7981 */
/* 0x000ee8000c1e1900 */
/*03c0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R21, [R10.64+0x4] ; /* 0x000004040a157981 */
/* 0x000f62000c1e1900 */
/*03e0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x000fc600078e00ff */
/*03f0*/ LDG.E R19, [R10.64+0x8] ; /* 0x000008040a137981 */
/* 0x000f68000c1e1900 */
/*0400*/ LDG.E R13, [R10.64+0xc] ; /* 0x00000c040a0d7981 */
/* 0x001f68000c1e1900 */
/*0410*/ LDG.E R25, [R10.64+0x10] ; /* 0x000010040a197981 */
/* 0x000f68000c1e1900 */
/*0420*/ LDG.E R29, [R10.64+0x14] ; /* 0x000014040a1d7981 */
/* 0x000f68000c1e1900 */
/*0430*/ LDG.E R22, [R10.64+0x18] ; /* 0x000018040a167981 */
/* 0x000f68000c1e1900 */
/*0440*/ LDG.E R23, [R10.64+0x1c] ; /* 0x00001c040a177981 */
/* 0x000f68000c1e1900 */
/*0450*/ LDG.E R6, [R10.64+0x30] ; /* 0x000030040a067981 */
/* 0x000f62000c1e1900 */
/*0460*/ IMAD.WIDE R14, R15, R4, c[0x0][0x170] ; /* 0x00005c000f0e7625 */
/* 0x004fc800078e0204 */
/*0470*/ IMAD.WIDE R26, R27, R4.reuse, c[0x0][0x170] ; /* 0x00005c001b1a7625 */
/* 0x088fe400078e0204 */
/*0480*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1b00 */
/*0490*/ IMAD.WIDE R16, R17, R4.reuse, c[0x0][0x170] ; /* 0x00005c0011107625 */
/* 0x090fe400078e0204 */
/*04a0*/ LDG.E.64 R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000ee4000c1e1b00 */
/*04b0*/ IMAD.WIDE R20, R21, R4.reuse, c[0x0][0x170] ; /* 0x00005c0015147625 */
/* 0x0a0fe400078e0204 */
/*04c0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1b00 */
/*04d0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f62000c1e1b00 */
/*04e0*/ IMAD.WIDE R18, R19, R4, c[0x0][0x170] ; /* 0x00005c0013127625 */
/* 0x000fcc00078e0204 */
/*04f0*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f62000c1e1b00 */
/*0500*/ IMAD.WIDE R12, R13, R4, c[0x0][0x170] ; /* 0x00005c000d0c7625 */
/* 0x000fcc00078e0204 */
/*0510*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1b00 */
/*0520*/ DADD R14, R14, R8 ; /* 0x000000000e0e7229 */
/* 0x0060c60000000008 */
/*0530*/ LDG.E R9, [R10.64+0x20] ; /* 0x000020040a097981 */
/* 0x001ea6000c1e1900 */
/*0540*/ DADD R26, R14, R26 ; /* 0x000000000e1a7229 */
/* 0x008122000000001a */
/*0550*/ LDG.E R8, [R10.64+0x34] ; /* 0x000034040a087981 */
/* 0x000ee2000c1e1900 */
/*0560*/ IMAD.WIDE R14, R25, R4, c[0x0][0x170] ; /* 0x00005c00190e7625 */
/* 0x001fc600078e0204 */
/*0570*/ LDG.E R25, [R10.64+0x24] ; /* 0x000024040a197981 */
/* 0x000ee2000c1e1900 */
/*0580*/ DADD R16, R26, R16 ; /* 0x000000001a107229 */
/* 0x0101460000000010 */
/*0590*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1b00 */
/*05a0*/ LDG.E R27, [R10.64+0x28] ; /* 0x000028040a1b7981 */
/* 0x001f22000c1e1900 */
/*05b0*/ DADD R20, R16, R20 ; /* 0x0000000010147229 */
/* 0x0200640000000014 */
/*05c0*/ IMAD.WIDE R16, R29, R4, c[0x0][0x170] ; /* 0x00005c001d107625 */
/* 0x001fe400078e0204 */
/*05d0*/ LDG.E R29, [R10.64+0x2c] ; /* 0x00002c040a1d7981 */
/* 0x000f68000c1e1900 */
/*05e0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f62000c1e1b00 */
/*05f0*/ DADD R18, R20, R18 ; /* 0x0000000014127229 */
/* 0x0020440000000012 */
/*0600*/ IMAD.WIDE R20, R22, R4, c[0x0][0x170] ; /* 0x00005c0016147625 */
/* 0x001fc800078e0204 */
/*0610*/ IMAD.WIDE R22, R23, R4, c[0x0][0x170] ; /* 0x00005c0017167625 */
/* 0x000fe400078e0204 */
/*0620*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f62000c1e1b00 */
/*0630*/ DADD R12, R18, R12 ; /* 0x00000000120c7229 */
/* 0x002506000000000c */
/*0640*/ LDG.E.64 R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f62000c1e1b00 */
/*0650*/ IMAD.WIDE R18, R9, R4, c[0x0][0x170] ; /* 0x00005c0009127625 */
/* 0x004fcc00078e0204 */
/*0660*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea2000c1e1b00 */
/*0670*/ IMAD.WIDE R24, R25, R4, c[0x0][0x170] ; /* 0x00005c0019187625 */
/* 0x008fe200078e0204 */
/*0680*/ DADD R12, R12, R14 ; /* 0x000000000c0c7229 */
/* 0x01004a000000000e */
/*0690*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000ee2000c1e1b00 */
/*06a0*/ IMAD.WIDE R14, R27, R4, c[0x0][0x170] ; /* 0x00005c001b0e7625 */
/* 0x001fc800078e0204 */
/*06b0*/ IMAD.WIDE R26, R29, R4, c[0x0][0x170] ; /* 0x00005c001d1a7625 */
/* 0x020fe400078e0204 */
/*06c0*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f22000c1e1b00 */
/*06d0*/ DADD R12, R12, R16 ; /* 0x000000000c0c7229 */
/* 0x0020460000000010 */
/*06e0*/ LDG.E.64 R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000f62000c1e1b00 */
/*06f0*/ IMAD.WIDE R16, R6, R4, c[0x0][0x170] ; /* 0x00005c0006107625 */
/* 0x001fc800078e0204 */
/*0700*/ IMAD.WIDE R8, R8, R4, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe400078e0204 */
/*0710*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f68000c1e1b00 */
/*0720*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f62000c1e1b00 */
/*0730*/ DADD R12, R12, R20 ; /* 0x000000000c0c7229 */
/* 0x002e0c0000000014 */
/*0740*/ DADD R12, R12, R22 ; /* 0x000000000c0c7229 */
/* 0x001ea20000000016 */
/*0750*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fc80007ffe0ff */
/*0760*/ ISETP.GE.AND P1, PT, R7, R5, PT ; /* 0x000000050700720c */
/* 0x000fe40003f26270 */
/*0770*/ IADD3 R10, P2, R10, 0x40, RZ ; /* 0x000000400a0a7810 */
/* 0x000fc80007f5e0ff */
/*0780*/ IADD3.X R11, RZ, R11, RZ, P2, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe200017fe4ff */
/*0790*/ DADD R12, R12, R18 ; /* 0x000000000c0c7229 */
/* 0x004ecc0000000012 */
/*07a0*/ DADD R12, R12, R24 ; /* 0x000000000c0c7229 */
/* 0x008f0c0000000018 */
/*07b0*/ DADD R12, R12, R14 ; /* 0x000000000c0c7229 */
/* 0x010f4c000000000e */
/*07c0*/ DADD R12, R12, R26 ; /* 0x000000000c0c7229 */
/* 0x020e0c000000001a */
/*07d0*/ DADD R12, R12, R16 ; /* 0x000000000c0c7229 */
/* 0x001e0c0000000010 */
/*07e0*/ DADD R8, R12, R8 ; /* 0x000000000c087229 */
/* 0x0010620000000008 */
/*07f0*/ @!P1 BRA 0x3a0 ; /* 0xfffffba000009947 */
/* 0x000fea000383ffff */
/*0800*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0810*/ IADD3 R4, R2, -R7, RZ ; /* 0x8000000702047210 */
/* 0x000fe20007ffe0ff */
/*0820*/ BSSY B1, 0xab0 ; /* 0x0000028000017945 */
/* 0x000fe60003800000 */
/*0830*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0840*/ @!P1 BRA 0xaa0 ; /* 0x0000025000009947 */
/* 0x000fea0003800000 */
/*0850*/ LDG.E R5, [R10.64+-0x8] ; /* 0xfffff8040a057981 */
/* 0x000ea8000c1e1900 */
/*0860*/ LDG.E R19, [R10.64+-0x4] ; /* 0xfffffc040a137981 */
/* 0x000ee8000c1e1900 */
/*0870*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000f28000c1e1900 */
/*0880*/ LDG.E R15, [R10.64+0x4] ; /* 0x000004040a0f7981 */
/* 0x000f68000c1e1900 */
/*0890*/ LDG.E R13, [R10.64+0x8] ; /* 0x000008040a0d7981 */
/* 0x001f68000c1e1900 */
/*08a0*/ LDG.E R21, [R10.64+0xc] ; /* 0x00000c040a157981 */
/* 0x000f68000c1e1900 */
/*08b0*/ LDG.E R23, [R10.64+0x10] ; /* 0x000010040a177981 */
/* 0x000f68000c1e1900 */
/*08c0*/ LDG.E R25, [R10.64+0x14] ; /* 0x000014040a197981 */
/* 0x000f62000c1e1900 */
/*08d0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x8 ; /* 0x00000008ff067424 */
/* 0x000fc800078e00ff */
/*08e0*/ IMAD.WIDE R4, R5, R6, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x004fc800078e0206 */
/*08f0*/ IMAD.WIDE R18, R19, R6.reuse, c[0x0][0x170] ; /* 0x00005c0013127625 */
/* 0x088fe400078e0206 */
/*0900*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1b00 */
/*0910*/ IMAD.WIDE R16, R17, R6.reuse, c[0x0][0x170] ; /* 0x00005c0011107625 */
/* 0x090fe400078e0206 */
/*0920*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee4000c1e1b00 */
/*0930*/ IMAD.WIDE R14, R15, R6.reuse, c[0x0][0x170] ; /* 0x00005c000f0e7625 */
/* 0x0a0fe400078e0206 */
/*0940*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f24000c1e1b00 */
/*0950*/ IMAD.WIDE R12, R13, R6, c[0x0][0x170] ; /* 0x00005c000d0c7625 */
/* 0x000fc400078e0206 */
/*0960*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f64000c1e1b00 */
/*0970*/ IMAD.WIDE R20, R21, R6.reuse, c[0x0][0x170] ; /* 0x00005c0015147625 */
/* 0x080fe400078e0206 */
/*0980*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f64000c1e1b00 */
/*0990*/ IMAD.WIDE R22, R23, R6.reuse, c[0x0][0x170] ; /* 0x00005c0017167625 */
/* 0x080fe400078e0206 */
/*09a0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f64000c1e1b00 */
/*09b0*/ IMAD.WIDE R24, R25, R6, c[0x0][0x170] ; /* 0x00005c0019187625 */
/* 0x000fc400078e0206 */
/*09c0*/ LDG.E.64 R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f68000c1e1b00 */
/*09d0*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000f62000c1e1b00 */
/*09e0*/ IADD3 R10, P1, R10, 0x20, RZ ; /* 0x000000200a0a7810 */
/* 0x000fe40007f3e0ff */
/*09f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0a00*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe40000ffe4ff */
/*0a10*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe20007ffe0ff */
/*0a20*/ DADD R4, R8, R4 ; /* 0x0000000008047229 */
/* 0x006ecc0000000004 */
/*0a30*/ DADD R4, R4, R18 ; /* 0x0000000004047229 */
/* 0x008f0c0000000012 */
/*0a40*/ DADD R4, R4, R16 ; /* 0x0000000004047229 */
/* 0x010f4c0000000010 */
/*0a50*/ DADD R4, R4, R14 ; /* 0x0000000004047229 */
/* 0x020e0c000000000e */
/*0a60*/ DADD R4, R4, R12 ; /* 0x0000000004047229 */
/* 0x001e0c000000000c */
/*0a70*/ DADD R4, R4, R20 ; /* 0x0000000004047229 */
/* 0x001e0c0000000014 */
/*0a80*/ DADD R4, R4, R22 ; /* 0x0000000004047229 */
/* 0x001e0c0000000016 */
/*0a90*/ DADD R8, R4, R24 ; /* 0x0000000004087229 */
/* 0x00104c0000000018 */
/*0aa0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ab0*/ ISETP.LT.OR P0, PT, R7, R2, P0 ; /* 0x000000020700720c */
/* 0x000fda0000701670 */
/*0ac0*/ @!P0 BRA 0xbe0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0ad0*/ LDG.E R4, [R10.64+-0x8] ; /* 0xfffff8040a047981 */
/* 0x001ea8000c1e1900 */
/*0ae0*/ LDG.E R6, [R10.64+-0x4] ; /* 0xfffffc040a067981 */
/* 0x000ee8000c1e1900 */
/*0af0*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000f28000c1e1900 */
/*0b00*/ LDG.E R14, [R10.64+0x4] ; /* 0x000004040a0e7981 */
/* 0x000f62000c1e1900 */
/*0b10*/ MOV R15, 0x8 ; /* 0x00000008000f7802 */
/* 0x000fca0000000f00 */
/*0b20*/ IMAD.WIDE R4, R4, R15, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x004fc800078e020f */
/*0b30*/ IMAD.WIDE R6, R6, R15.reuse, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x088fe400078e020f */
/*0b40*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1b00 */
/*0b50*/ IMAD.WIDE R12, R12, R15.reuse, c[0x0][0x170] ; /* 0x00005c000c0c7625 */
/* 0x090fe400078e020f */
/*0b60*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee4000c1e1b00 */
/*0b70*/ IMAD.WIDE R14, R14, R15, c[0x0][0x170] ; /* 0x00005c000e0e7625 */
/* 0x020fe400078e020f */
/*0b80*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f28000c1e1b00 */
/*0b90*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f62000c1e1b00 */
/*0ba0*/ DADD R8, R8, R4 ; /* 0x0000000008087229 */
/* 0x006ecc0000000004 */
/*0bb0*/ DADD R8, R8, R6 ; /* 0x0000000008087229 */
/* 0x008f0c0000000006 */
/*0bc0*/ DADD R8, R8, R12 ; /* 0x0000000008087229 */
/* 0x010f4c000000000c */
/*0bd0*/ DADD R8, R8, R14 ; /* 0x0000000008087229 */
/* 0x02004c000000000e */
/*0be0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0bf0*/ LEA R2, P0, R0, c[0x0][0x188], 0x3 ; /* 0x0000620000027a11 */
/* 0x000fc800078018ff */
/*0c00*/ LEA.HI.X R3, R0, c[0x0][0x18c], R3, 0x3, P0 ; /* 0x0000630000037a11 */
/* 0x000fca00000f1c03 */
/*0c10*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0c20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void find_all_sums_hub_kernel(int* hub, int nhub, double *node_weight, int *neighbor, int *neighbor_start, double *sum_weight_result){
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < nhub) {
int nid = hub[x];
double sum = 0.0;
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid+1]; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
}
sum_weight_result[nid] = sum;
}
} | .file "tmpxft_0017a857_00000000-6_find_all_sums_hub_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z24find_all_sums_hub_kernelPiiPdS_S_S0_PiiPdS_S_S0_
.type _Z54__device_stub__Z24find_all_sums_hub_kernelPiiPdS_S_S0_PiiPdS_S_S0_, @function
_Z54__device_stub__Z24find_all_sums_hub_kernelPiiPdS_S_S0_PiiPdS_S_S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24find_all_sums_hub_kernelPiiPdS_S_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z24find_all_sums_hub_kernelPiiPdS_S_S0_PiiPdS_S_S0_, .-_Z54__device_stub__Z24find_all_sums_hub_kernelPiiPdS_S_S0_PiiPdS_S_S0_
.globl _Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.type _Z24find_all_sums_hub_kernelPiiPdS_S_S0_, @function
_Z24find_all_sums_hub_kernelPiiPdS_S_S0_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z24find_all_sums_hub_kernelPiiPdS_S_S0_PiiPdS_S_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24find_all_sums_hub_kernelPiiPdS_S_S0_, .-_Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24find_all_sums_hub_kernelPiiPdS_S_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24find_all_sums_hub_kernelPiiPdS_S_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void find_all_sums_hub_kernel(int* hub, int nhub, double *node_weight, int *neighbor, int *neighbor_start, double *sum_weight_result){
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < nhub) {
int nid = hub[x];
double sum = 0.0;
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid+1]; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
}
sum_weight_result[nid] = sum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void find_all_sums_hub_kernel(int* hub, int nhub, double *node_weight, int *neighbor, int *neighbor_start, double *sum_weight_result){
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < nhub) {
int nid = hub[x];
double sum = 0.0;
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid+1]; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
}
sum_weight_result[nid] = sum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void find_all_sums_hub_kernel(int* hub, int nhub, double *node_weight, int *neighbor, int *neighbor_start, double *sum_weight_result){
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < nhub) {
int nid = hub[x];
double sum = 0.0;
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid+1]; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
}
sum_weight_result[nid] = sum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.globl _Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.p2align 8
.type _Z24find_all_sums_hub_kernelPiiPdS_S_S0_,@function
_Z24find_all_sums_hub_kernelPiiPdS_S_S0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v2, v3
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x10
v_ashrrev_i32_e32 v5, 31, v2
v_mov_b32_e32 v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[4:5]
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
s_mov_b32 s6, 0
.p2align 6
.LBB0_3:
global_load_b32 v8, v[6:7], off
v_add_nc_u32_e32 v2, 1, v2
v_add_co_u32 v6, s2, v6, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s2, 0, v7, s2
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 3, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
v_cmp_ge_i32_e32 vcc_lo, v2, v3
global_load_b64 v[8:9], v[8:9], off
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[8:9]
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s6
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[4:5], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24find_all_sums_hub_kernelPiiPdS_S_S0_, .Lfunc_end0-_Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24find_all_sums_hub_kernelPiiPdS_S_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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