system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void find_all_sums_hub_kernel(int* hub, int nhub, double *node_weight, int *neighbor, int *neighbor_start, double *sum_weight_result){
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < nhub) {
int nid = hub[x];
double sum = 0.0;
for (int eid = neighbor_start[nid]; eid < neighbor_start[nid+1]; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
}
sum_weight_result[nid] = sum;
}
} | .text
.file "find_all_sums_hub_kernel.hip"
.globl _Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_ # -- Begin function _Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_
.p2align 4, 0x90
.type _Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_,@function
_Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_: # @_Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24find_all_sums_hub_kernelPiiPdS_S_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_, .Lfunc_end0-_Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24find_all_sums_hub_kernelPiiPdS_S_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24find_all_sums_hub_kernelPiiPdS_S_S0_,@object # @_Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.section .rodata,"a",@progbits
.globl _Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.p2align 3, 0x0
_Z24find_all_sums_hub_kernelPiiPdS_S_S0_:
.quad _Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_
.size _Z24find_all_sums_hub_kernelPiiPdS_S_S0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24find_all_sums_hub_kernelPiiPdS_S_S0_"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R6, R7, R4, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fca00078e0204 */
/*0090*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD.WIDE R10, R0, R4, c[0x0][0x180] ; /* 0x00006000000a7625 */
/* 0x004fca00078e0204 */
/*00b0*/ LDG.E R5, [R10.64] ; /* 0x000000040a057981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R2, [R10.64+0x4] ; /* 0x000004040a027981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ BSSY B0, 0xbf0 ; /* 0x00000b1000007945 */
/* 0x000fe20003800000 */
/*00e0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*00f0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*0100*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fda0003f06270 */
/*0110*/ @P0 BRA 0xbe0 ; /* 0x00000ac000000947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R7, R5, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x000fe20007ffe0ff */
/*0130*/ BSSY B1, 0x2f0 ; /* 0x000001b000017945 */
/* 0x000fe20003800000 */
/*0140*/ LOP3.LUT R9, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff097212 */
/* 0x000fe400078e33ff */
/*0150*/ IMNMX R6, R2, R7, !PT ; /* 0x0000000702067217 */
/* 0x000fc80007800200 */
/*0160*/ IADD3 R9, R6.reuse, R9, RZ ; /* 0x0000000906097210 */
/* 0x040fe20007ffe0ff */
/*0170*/ IMAD.IADD R7, R6, 0x1, -R5 ; /* 0x0000000106077824 */
/* 0x000fc600078e0a05 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fe40003f06070 */
/*0190*/ LOP3.LUT P1, R10, R7, 0x3, RZ, 0xc0, !PT ; /* 0x00000003070a7812 */
/* 0x000fe2000782c0ff */
/*01a0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0005 */
/*01b0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fd6000001ff00 */
/*01c0*/ @!P1 BRA 0x2e0 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.WIDE R6, R5, R4, c[0x0][0x178] ; /* 0x00005e0005067625 */
/* 0x000fe200078e0204 */
/*01e0*/ MOV R14, R10 ; /* 0x0000000a000e7202 */
/* 0x000fe20000000f00 */
/*01f0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fc6000001ff00 */
/*0200*/ MOV R13, R7 ; /* 0x00000007000d7202 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*0220*/ MOV R12, R6 ; /* 0x00000006000c7202 */
/* 0x000fca0000000f00 */
/*0230*/ LDG.E R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x001ea2000c1e1900 */
/*0240*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*0250*/ IADD3 R14, R14, -0x1, RZ ; /* 0xffffffff0e0e7810 */
/* 0x000fc80007ffe0ff */
/*0260*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fca0003f25270 */
/*0270*/ IMAD.WIDE R10, R10, R11, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x004fcc00078e020b */
/*0280*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*0290*/ IADD3 R6, P2, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f5e0ff */
/*02a0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc60007ffe0ff */
/*02b0*/ IMAD.X R13, RZ, RZ, R13, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe200010e060d */
/*02c0*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x0060620000000008 */
/*02d0*/ @P1 BRA 0x220 ; /* 0xffffff4000001947 */
/* 0x000fea000383ffff */
/*02e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02f0*/ @!P0 BRA 0xbe0 ; /* 0x000008e000008947 */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R6, R2, -R7, RZ ; /* 0x8000000702067210 */
/* 0x000fe20007ffe0ff */
/*0310*/ IMAD.WIDE R4, R7, R4, c[0x0][0x178] ; /* 0x00005e0007047625 */
/* 0x000fe200078e0204 */
/*0320*/ BSSY B1, 0x810 ; /* 0x000004e000017945 */
/* 0x000fe40003800000 */
/*0330*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0340*/ IADD3 R10, P0, R4, 0x8, RZ ; /* 0x00000008040a7810 */
/* 0x001fc80007f1e0ff */
/*0350*/ IADD3.X R11, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff0b7210 */
/* 0x000fe400007fe4ff */
/*0360*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fca0003f0f070 */
/*0370*/ @!P1 BRA 0x800 ; /* 0x0000048000009947 */
/* 0x000fea0003800000 */
/*0380*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0390*/ IADD3 R5, R2, -0xc, RZ ; /* 0xfffffff402057810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ LDG.E R15, [R10.64+-0x8] ; /* 0xfffff8040a0f7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R27, [R10.64+-0x4] ; /* 0xfffffc040a1b7981 */
/* 0x000ee8000c1e1900 */
/*03c0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R21, [R10.64+0x4] ; /* 0x000004040a157981 */
/* 0x000f62000c1e1900 */
/*03e0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x000fc600078e00ff */
/*03f0*/ LDG.E R19, [R10.64+0x8] ; /* 0x000008040a137981 */
/* 0x000f68000c1e1900 */
/*0400*/ LDG.E R13, [R10.64+0xc] ; /* 0x00000c040a0d7981 */
/* 0x001f68000c1e1900 */
/*0410*/ LDG.E R25, [R10.64+0x10] ; /* 0x000010040a197981 */
/* 0x000f68000c1e1900 */
/*0420*/ LDG.E R29, [R10.64+0x14] ; /* 0x000014040a1d7981 */
/* 0x000f68000c1e1900 */
/*0430*/ LDG.E R22, [R10.64+0x18] ; /* 0x000018040a167981 */
/* 0x000f68000c1e1900 */
/*0440*/ LDG.E R23, [R10.64+0x1c] ; /* 0x00001c040a177981 */
/* 0x000f68000c1e1900 */
/*0450*/ LDG.E R6, [R10.64+0x30] ; /* 0x000030040a067981 */
/* 0x000f62000c1e1900 */
/*0460*/ IMAD.WIDE R14, R15, R4, c[0x0][0x170] ; /* 0x00005c000f0e7625 */
/* 0x004fc800078e0204 */
/*0470*/ IMAD.WIDE R26, R27, R4.reuse, c[0x0][0x170] ; /* 0x00005c001b1a7625 */
/* 0x088fe400078e0204 */
/*0480*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1b00 */
/*0490*/ IMAD.WIDE R16, R17, R4.reuse, c[0x0][0x170] ; /* 0x00005c0011107625 */
/* 0x090fe400078e0204 */
/*04a0*/ LDG.E.64 R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000ee4000c1e1b00 */
/*04b0*/ IMAD.WIDE R20, R21, R4.reuse, c[0x0][0x170] ; /* 0x00005c0015147625 */
/* 0x0a0fe400078e0204 */
/*04c0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1b00 */
/*04d0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f62000c1e1b00 */
/*04e0*/ IMAD.WIDE R18, R19, R4, c[0x0][0x170] ; /* 0x00005c0013127625 */
/* 0x000fcc00078e0204 */
/*04f0*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f62000c1e1b00 */
/*0500*/ IMAD.WIDE R12, R13, R4, c[0x0][0x170] ; /* 0x00005c000d0c7625 */
/* 0x000fcc00078e0204 */
/*0510*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1b00 */
/*0520*/ DADD R14, R14, R8 ; /* 0x000000000e0e7229 */
/* 0x0060c60000000008 */
/*0530*/ LDG.E R9, [R10.64+0x20] ; /* 0x000020040a097981 */
/* 0x001ea6000c1e1900 */
/*0540*/ DADD R26, R14, R26 ; /* 0x000000000e1a7229 */
/* 0x008122000000001a */
/*0550*/ LDG.E R8, [R10.64+0x34] ; /* 0x000034040a087981 */
/* 0x000ee2000c1e1900 */
/*0560*/ IMAD.WIDE R14, R25, R4, c[0x0][0x170] ; /* 0x00005c00190e7625 */
/* 0x001fc600078e0204 */
/*0570*/ LDG.E R25, [R10.64+0x24] ; /* 0x000024040a197981 */
/* 0x000ee2000c1e1900 */
/*0580*/ DADD R16, R26, R16 ; /* 0x000000001a107229 */
/* 0x0101460000000010 */
/*0590*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1b00 */
/*05a0*/ LDG.E R27, [R10.64+0x28] ; /* 0x000028040a1b7981 */
/* 0x001f22000c1e1900 */
/*05b0*/ DADD R20, R16, R20 ; /* 0x0000000010147229 */
/* 0x0200640000000014 */
/*05c0*/ IMAD.WIDE R16, R29, R4, c[0x0][0x170] ; /* 0x00005c001d107625 */
/* 0x001fe400078e0204 */
/*05d0*/ LDG.E R29, [R10.64+0x2c] ; /* 0x00002c040a1d7981 */
/* 0x000f68000c1e1900 */
/*05e0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f62000c1e1b00 */
/*05f0*/ DADD R18, R20, R18 ; /* 0x0000000014127229 */
/* 0x0020440000000012 */
/*0600*/ IMAD.WIDE R20, R22, R4, c[0x0][0x170] ; /* 0x00005c0016147625 */
/* 0x001fc800078e0204 */
/*0610*/ IMAD.WIDE R22, R23, R4, c[0x0][0x170] ; /* 0x00005c0017167625 */
/* 0x000fe400078e0204 */
/*0620*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f62000c1e1b00 */
/*0630*/ DADD R12, R18, R12 ; /* 0x00000000120c7229 */
/* 0x002506000000000c */
/*0640*/ LDG.E.64 R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f62000c1e1b00 */
/*0650*/ IMAD.WIDE R18, R9, R4, c[0x0][0x170] ; /* 0x00005c0009127625 */
/* 0x004fcc00078e0204 */
/*0660*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea2000c1e1b00 */
/*0670*/ IMAD.WIDE R24, R25, R4, c[0x0][0x170] ; /* 0x00005c0019187625 */
/* 0x008fe200078e0204 */
/*0680*/ DADD R12, R12, R14 ; /* 0x000000000c0c7229 */
/* 0x01004a000000000e */
/*0690*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000ee2000c1e1b00 */
/*06a0*/ IMAD.WIDE R14, R27, R4, c[0x0][0x170] ; /* 0x00005c001b0e7625 */
/* 0x001fc800078e0204 */
/*06b0*/ IMAD.WIDE R26, R29, R4, c[0x0][0x170] ; /* 0x00005c001d1a7625 */
/* 0x020fe400078e0204 */
/*06c0*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f22000c1e1b00 */
/*06d0*/ DADD R12, R12, R16 ; /* 0x000000000c0c7229 */
/* 0x0020460000000010 */
/*06e0*/ LDG.E.64 R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000f62000c1e1b00 */
/*06f0*/ IMAD.WIDE R16, R6, R4, c[0x0][0x170] ; /* 0x00005c0006107625 */
/* 0x001fc800078e0204 */
/*0700*/ IMAD.WIDE R8, R8, R4, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe400078e0204 */
/*0710*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f68000c1e1b00 */
/*0720*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f62000c1e1b00 */
/*0730*/ DADD R12, R12, R20 ; /* 0x000000000c0c7229 */
/* 0x002e0c0000000014 */
/*0740*/ DADD R12, R12, R22 ; /* 0x000000000c0c7229 */
/* 0x001ea20000000016 */
/*0750*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fc80007ffe0ff */
/*0760*/ ISETP.GE.AND P1, PT, R7, R5, PT ; /* 0x000000050700720c */
/* 0x000fe40003f26270 */
/*0770*/ IADD3 R10, P2, R10, 0x40, RZ ; /* 0x000000400a0a7810 */
/* 0x000fc80007f5e0ff */
/*0780*/ IADD3.X R11, RZ, R11, RZ, P2, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe200017fe4ff */
/*0790*/ DADD R12, R12, R18 ; /* 0x000000000c0c7229 */
/* 0x004ecc0000000012 */
/*07a0*/ DADD R12, R12, R24 ; /* 0x000000000c0c7229 */
/* 0x008f0c0000000018 */
/*07b0*/ DADD R12, R12, R14 ; /* 0x000000000c0c7229 */
/* 0x010f4c000000000e */
/*07c0*/ DADD R12, R12, R26 ; /* 0x000000000c0c7229 */
/* 0x020e0c000000001a */
/*07d0*/ DADD R12, R12, R16 ; /* 0x000000000c0c7229 */
/* 0x001e0c0000000010 */
/*07e0*/ DADD R8, R12, R8 ; /* 0x000000000c087229 */
/* 0x0010620000000008 */
/*07f0*/ @!P1 BRA 0x3a0 ; /* 0xfffffba000009947 */
/* 0x000fea000383ffff */
/*0800*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0810*/ IADD3 R4, R2, -R7, RZ ; /* 0x8000000702047210 */
/* 0x000fe20007ffe0ff */
/*0820*/ BSSY B1, 0xab0 ; /* 0x0000028000017945 */
/* 0x000fe60003800000 */
/*0830*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0840*/ @!P1 BRA 0xaa0 ; /* 0x0000025000009947 */
/* 0x000fea0003800000 */
/*0850*/ LDG.E R5, [R10.64+-0x8] ; /* 0xfffff8040a057981 */
/* 0x000ea8000c1e1900 */
/*0860*/ LDG.E R19, [R10.64+-0x4] ; /* 0xfffffc040a137981 */
/* 0x000ee8000c1e1900 */
/*0870*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000f28000c1e1900 */
/*0880*/ LDG.E R15, [R10.64+0x4] ; /* 0x000004040a0f7981 */
/* 0x000f68000c1e1900 */
/*0890*/ LDG.E R13, [R10.64+0x8] ; /* 0x000008040a0d7981 */
/* 0x001f68000c1e1900 */
/*08a0*/ LDG.E R21, [R10.64+0xc] ; /* 0x00000c040a157981 */
/* 0x000f68000c1e1900 */
/*08b0*/ LDG.E R23, [R10.64+0x10] ; /* 0x000010040a177981 */
/* 0x000f68000c1e1900 */
/*08c0*/ LDG.E R25, [R10.64+0x14] ; /* 0x000014040a197981 */
/* 0x000f62000c1e1900 */
/*08d0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x8 ; /* 0x00000008ff067424 */
/* 0x000fc800078e00ff */
/*08e0*/ IMAD.WIDE R4, R5, R6, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x004fc800078e0206 */
/*08f0*/ IMAD.WIDE R18, R19, R6.reuse, c[0x0][0x170] ; /* 0x00005c0013127625 */
/* 0x088fe400078e0206 */
/*0900*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1b00 */
/*0910*/ IMAD.WIDE R16, R17, R6.reuse, c[0x0][0x170] ; /* 0x00005c0011107625 */
/* 0x090fe400078e0206 */
/*0920*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee4000c1e1b00 */
/*0930*/ IMAD.WIDE R14, R15, R6.reuse, c[0x0][0x170] ; /* 0x00005c000f0e7625 */
/* 0x0a0fe400078e0206 */
/*0940*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f24000c1e1b00 */
/*0950*/ IMAD.WIDE R12, R13, R6, c[0x0][0x170] ; /* 0x00005c000d0c7625 */
/* 0x000fc400078e0206 */
/*0960*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f64000c1e1b00 */
/*0970*/ IMAD.WIDE R20, R21, R6.reuse, c[0x0][0x170] ; /* 0x00005c0015147625 */
/* 0x080fe400078e0206 */
/*0980*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f64000c1e1b00 */
/*0990*/ IMAD.WIDE R22, R23, R6.reuse, c[0x0][0x170] ; /* 0x00005c0017167625 */
/* 0x080fe400078e0206 */
/*09a0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f64000c1e1b00 */
/*09b0*/ IMAD.WIDE R24, R25, R6, c[0x0][0x170] ; /* 0x00005c0019187625 */
/* 0x000fc400078e0206 */
/*09c0*/ LDG.E.64 R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f68000c1e1b00 */
/*09d0*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000f62000c1e1b00 */
/*09e0*/ IADD3 R10, P1, R10, 0x20, RZ ; /* 0x000000200a0a7810 */
/* 0x000fe40007f3e0ff */
/*09f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0a00*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe40000ffe4ff */
/*0a10*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe20007ffe0ff */
/*0a20*/ DADD R4, R8, R4 ; /* 0x0000000008047229 */
/* 0x006ecc0000000004 */
/*0a30*/ DADD R4, R4, R18 ; /* 0x0000000004047229 */
/* 0x008f0c0000000012 */
/*0a40*/ DADD R4, R4, R16 ; /* 0x0000000004047229 */
/* 0x010f4c0000000010 */
/*0a50*/ DADD R4, R4, R14 ; /* 0x0000000004047229 */
/* 0x020e0c000000000e */
/*0a60*/ DADD R4, R4, R12 ; /* 0x0000000004047229 */
/* 0x001e0c000000000c */
/*0a70*/ DADD R4, R4, R20 ; /* 0x0000000004047229 */
/* 0x001e0c0000000014 */
/*0a80*/ DADD R4, R4, R22 ; /* 0x0000000004047229 */
/* 0x001e0c0000000016 */
/*0a90*/ DADD R8, R4, R24 ; /* 0x0000000004087229 */
/* 0x00104c0000000018 */
/*0aa0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ab0*/ ISETP.LT.OR P0, PT, R7, R2, P0 ; /* 0x000000020700720c */
/* 0x000fda0000701670 */
/*0ac0*/ @!P0 BRA 0xbe0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0ad0*/ LDG.E R4, [R10.64+-0x8] ; /* 0xfffff8040a047981 */
/* 0x001ea8000c1e1900 */
/*0ae0*/ LDG.E R6, [R10.64+-0x4] ; /* 0xfffffc040a067981 */
/* 0x000ee8000c1e1900 */
/*0af0*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000f28000c1e1900 */
/*0b00*/ LDG.E R14, [R10.64+0x4] ; /* 0x000004040a0e7981 */
/* 0x000f62000c1e1900 */
/*0b10*/ MOV R15, 0x8 ; /* 0x00000008000f7802 */
/* 0x000fca0000000f00 */
/*0b20*/ IMAD.WIDE R4, R4, R15, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x004fc800078e020f */
/*0b30*/ IMAD.WIDE R6, R6, R15.reuse, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x088fe400078e020f */
/*0b40*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1b00 */
/*0b50*/ IMAD.WIDE R12, R12, R15.reuse, c[0x0][0x170] ; /* 0x00005c000c0c7625 */
/* 0x090fe400078e020f */
/*0b60*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee4000c1e1b00 */
/*0b70*/ IMAD.WIDE R14, R14, R15, c[0x0][0x170] ; /* 0x00005c000e0e7625 */
/* 0x020fe400078e020f */
/*0b80*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f28000c1e1b00 */
/*0b90*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f62000c1e1b00 */
/*0ba0*/ DADD R8, R8, R4 ; /* 0x0000000008087229 */
/* 0x006ecc0000000004 */
/*0bb0*/ DADD R8, R8, R6 ; /* 0x0000000008087229 */
/* 0x008f0c0000000006 */
/*0bc0*/ DADD R8, R8, R12 ; /* 0x0000000008087229 */
/* 0x010f4c000000000c */
/*0bd0*/ DADD R8, R8, R14 ; /* 0x0000000008087229 */
/* 0x02004c000000000e */
/*0be0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0bf0*/ LEA R2, P0, R0, c[0x0][0x188], 0x3 ; /* 0x0000620000027a11 */
/* 0x000fc800078018ff */
/*0c00*/ LEA.HI.X R3, R0, c[0x0][0x18c], R3, 0x3, P0 ; /* 0x0000630000037a11 */
/* 0x000fca00000f1c03 */
/*0c10*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0c20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.globl _Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.p2align 8
.type _Z24find_all_sums_hub_kernelPiiPdS_S_S0_,@function
_Z24find_all_sums_hub_kernelPiiPdS_S_S0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v2, v3
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x10
v_ashrrev_i32_e32 v5, 31, v2
v_mov_b32_e32 v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[4:5]
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
s_mov_b32 s6, 0
.p2align 6
.LBB0_3:
global_load_b32 v8, v[6:7], off
v_add_nc_u32_e32 v2, 1, v2
v_add_co_u32 v6, s2, v6, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s2, 0, v7, s2
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 3, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
v_cmp_ge_i32_e32 vcc_lo, v2, v3
global_load_b64 v[8:9], v[8:9], off
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[8:9]
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s6
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[4:5], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24find_all_sums_hub_kernelPiiPdS_S_S0_, .Lfunc_end0-_Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24find_all_sums_hub_kernelPiiPdS_S_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017a857_00000000-6_find_all_sums_hub_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z24find_all_sums_hub_kernelPiiPdS_S_S0_PiiPdS_S_S0_
.type _Z54__device_stub__Z24find_all_sums_hub_kernelPiiPdS_S_S0_PiiPdS_S_S0_, @function
_Z54__device_stub__Z24find_all_sums_hub_kernelPiiPdS_S_S0_PiiPdS_S_S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24find_all_sums_hub_kernelPiiPdS_S_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z24find_all_sums_hub_kernelPiiPdS_S_S0_PiiPdS_S_S0_, .-_Z54__device_stub__Z24find_all_sums_hub_kernelPiiPdS_S_S0_PiiPdS_S_S0_
.globl _Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.type _Z24find_all_sums_hub_kernelPiiPdS_S_S0_, @function
_Z24find_all_sums_hub_kernelPiiPdS_S_S0_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z24find_all_sums_hub_kernelPiiPdS_S_S0_PiiPdS_S_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24find_all_sums_hub_kernelPiiPdS_S_S0_, .-_Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24find_all_sums_hub_kernelPiiPdS_S_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24find_all_sums_hub_kernelPiiPdS_S_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "find_all_sums_hub_kernel.hip"
.globl _Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_ # -- Begin function _Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_
.p2align 4, 0x90
.type _Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_,@function
_Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_: # @_Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24find_all_sums_hub_kernelPiiPdS_S_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_, .Lfunc_end0-_Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24find_all_sums_hub_kernelPiiPdS_S_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24find_all_sums_hub_kernelPiiPdS_S_S0_,@object # @_Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.section .rodata,"a",@progbits
.globl _Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.p2align 3, 0x0
_Z24find_all_sums_hub_kernelPiiPdS_S_S0_:
.quad _Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_
.size _Z24find_all_sums_hub_kernelPiiPdS_S_S0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24find_all_sums_hub_kernelPiiPdS_S_S0_"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__find_all_sums_hub_kernelPiiPdS_S_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24find_all_sums_hub_kernelPiiPdS_S_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define __rose_lt(x,y) ((x)<(y)?(x):(y))
#define __rose_gt(x,y) ((x)>(y)?(x):(y))
#define D__(solventMol) D_[solventMol]
__global__ void Action_No_image_GPU(double *D_,double *maskCenter,double (*SolventMols_)[1024][3]);
//this is only used for cuda-chill
//heavy simplification
#define NsolventMolecules_ 1024
#define NsolventAtoms_ 1024
// struct MolDist {
// int mol; ///< Original solvent molecule number (starts from 1).
// double D; ///< Closest distance of solvent molecule to atoms in distanceMask.
// //AtomMask mask; ///< Original topology solvent molecule atom mask.
// double solventAtoms[NsolventAtoms_][3]; ///< Actual solvent atom #s to loop over.
// };
//using dist for no image
// and kernel for when we use solute molecule center
//extracting pulling out arrays out from struct
void Action_NoImage_Center(double SolventMols_[1024][1024][3],double D_[1024],double maskCenter[3],double maxD)
{
double *devI2Ptr;
double *devI1Ptr;
double *devO1Ptr;
int t8;
int t10;
int t4;
int t2;
double Dist;
int solventMol;
int solventAtom;
cudaMalloc(((void **)(&devO1Ptr)),3072 * sizeof(double ));
cudaMalloc(((void **)(&devI1Ptr)),3 * sizeof(double ));
cudaMemcpy(devI1Ptr,maskCenter,3 * sizeof(double ),cudaMemcpyHostToDevice);
cudaMalloc(((void **)(&devI2Ptr)),3145728 * sizeof(double ));
cudaMemcpy(devI2Ptr,SolventMols_,3145728 * sizeof(double ),cudaMemcpyHostToDevice);
dim3 dimGrid0 = dim3(32,32);
dim3 dimBlock0 = dim3(32,32);
Action_No_image_GPU<<<dimGrid0,dimBlock0>>>(devO1Ptr,devI1Ptr,((double (*)[1024][3])devI2Ptr));
cudaMemcpy(D_,devO1Ptr,3072 * sizeof(double ),cudaMemcpyDeviceToHost);
cudaFree(devO1Ptr);
cudaFree(devI1Ptr);
cudaFree(devI2Ptr);
}
__global__ void Action_No_image_GPU(double *D_,double *maskCenter,double (*SolventMols_)[1024][3])
{
int bx;
bx = blockIdx.x;
int by;
by = blockIdx.y;
int tx;
tx = threadIdx.x;
int ty;
ty = threadIdx.y;
double maxD;
double Dist;
int t2;
int t4;
int t10;
int t8;
D_[32 * bx + tx] = maxD;
//main dist2_noImage code
//double *a1 = maskCenter.Dptr(); //center of solute molecule
//double *a2 = frmIn.XYZ(*solvent_atom);
//double *a1 = maskCenter; //center of solute molecule
//double *a2 = SolventMols_[solventMol][solventAtom];
//double x = a1[0] - a2[0];
//double y = a1[1] - a2[1];
//double z = a1[2] - a2[2];
//Dist = (x*x + y*y + z*z);
Dist = maskCenter[0] * SolventMols_[32 * bx + tx][ty][0] + maskCenter[1] * SolventMols_[32 * bx + tx][ty][1] + maskCenter[2] * SolventMols_[32 * bx + tx][ty][2];
if (Dist + 1 <= D__(tx + 32 * bx))
D_[32 * bx + tx] = Dist;
} | code for sm_80
Function : _Z19Action_No_image_GPUPdS_PA1024_A3_d
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R18, SR_CTAID.X ; /* 0x0000000000127919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 512 ; /* 0x00006000ff077435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0060*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0070*/ LEA R18, R18, R3, 0x5 ; /* 0x0000000312127211 */
/* 0x001fca00078e28ff */
/*0080*/ IMAD.WIDE R2, R18, R7, c[0x0][0x170] ; /* 0x00005c0012027625 */
/* 0x000fe200078e0207 */
/*0090*/ MOV R7, c[0x0][0x16c] ; /* 0x00005b0000077a02 */
/* 0x000fca0000000f00 */
/*00a0*/ IMAD.WIDE R2, R5, 0x18, R2 ; /* 0x0000001805027825 */
/* 0x002fe200078e0202 */
/*00b0*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea8000c1e1b00 */
/*00c0*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000ea2000c1e1b00 */
/*00d0*/ HFMA2.MMA R19, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff137435 */
/* 0x000fc600000001ff */
/*00e0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ee8000c1e1b00 */
/*00f0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ee8000c1e1b00 */
/*0100*/ LDG.E.64 R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000f28000c1e1b00 */
/*0110*/ LDG.E.64 R14, [R2.64+0x10] ; /* 0x00001004020e7981 */
/* 0x000f22000c1e1b00 */
/*0120*/ IMAD.WIDE R18, R18, R19, c[0x0][0x160] ; /* 0x0000580012127625 */
/* 0x000fca00078e0213 */
/*0130*/ LDG.E.64 R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000f62000c1e1b00 */
/*0140*/ DMUL R10, R10, R12 ; /* 0x0000000c0a0a7228 */
/* 0x004ecc0000000000 */
/*0150*/ DFMA R4, R4, R8, R10 ; /* 0x000000080404722b */
/* 0x008f0c000000000a */
/*0160*/ DFMA R4, R14, R16, R4 ; /* 0x000000100e04722b */
/* 0x010e0c0000000004 */
/*0170*/ DADD R8, R4, 1 ; /* 0x3ff0000004087429 */
/* 0x001f4c0000000000 */
/*0180*/ DSETP.GTU.AND P0, PT, R8, R20, PT ; /* 0x000000140800722a */
/* 0x020e1c0003f0c000 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01a0*/ STG.E.64 [R18.64], R4 ; /* 0x0000000412007986 */
/* 0x000fe2000c101b04 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define __rose_lt(x,y) ((x)<(y)?(x):(y))
#define __rose_gt(x,y) ((x)>(y)?(x):(y))
#define D__(solventMol) D_[solventMol]
__global__ void Action_No_image_GPU(double *D_,double *maskCenter,double (*SolventMols_)[1024][3]);
//this is only used for cuda-chill
//heavy simplification
#define NsolventMolecules_ 1024
#define NsolventAtoms_ 1024
// struct MolDist {
// int mol; ///< Original solvent molecule number (starts from 1).
// double D; ///< Closest distance of solvent molecule to atoms in distanceMask.
// //AtomMask mask; ///< Original topology solvent molecule atom mask.
// double solventAtoms[NsolventAtoms_][3]; ///< Actual solvent atom #s to loop over.
// };
//using dist for no image
// and kernel for when we use solute molecule center
//extracting pulling out arrays out from struct
void Action_NoImage_Center(double SolventMols_[1024][1024][3],double D_[1024],double maskCenter[3],double maxD)
{
double *devI2Ptr;
double *devI1Ptr;
double *devO1Ptr;
int t8;
int t10;
int t4;
int t2;
double Dist;
int solventMol;
int solventAtom;
cudaMalloc(((void **)(&devO1Ptr)),3072 * sizeof(double ));
cudaMalloc(((void **)(&devI1Ptr)),3 * sizeof(double ));
cudaMemcpy(devI1Ptr,maskCenter,3 * sizeof(double ),cudaMemcpyHostToDevice);
cudaMalloc(((void **)(&devI2Ptr)),3145728 * sizeof(double ));
cudaMemcpy(devI2Ptr,SolventMols_,3145728 * sizeof(double ),cudaMemcpyHostToDevice);
dim3 dimGrid0 = dim3(32,32);
dim3 dimBlock0 = dim3(32,32);
Action_No_image_GPU<<<dimGrid0,dimBlock0>>>(devO1Ptr,devI1Ptr,((double (*)[1024][3])devI2Ptr));
cudaMemcpy(D_,devO1Ptr,3072 * sizeof(double ),cudaMemcpyDeviceToHost);
cudaFree(devO1Ptr);
cudaFree(devI1Ptr);
cudaFree(devI2Ptr);
}
__global__ void Action_No_image_GPU(double *D_,double *maskCenter,double (*SolventMols_)[1024][3])
{
int bx;
bx = blockIdx.x;
int by;
by = blockIdx.y;
int tx;
tx = threadIdx.x;
int ty;
ty = threadIdx.y;
double maxD;
double Dist;
int t2;
int t4;
int t10;
int t8;
D_[32 * bx + tx] = maxD;
//main dist2_noImage code
//double *a1 = maskCenter.Dptr(); //center of solute molecule
//double *a2 = frmIn.XYZ(*solvent_atom);
//double *a1 = maskCenter; //center of solute molecule
//double *a2 = SolventMols_[solventMol][solventAtom];
//double x = a1[0] - a2[0];
//double y = a1[1] - a2[1];
//double z = a1[2] - a2[2];
//Dist = (x*x + y*y + z*z);
Dist = maskCenter[0] * SolventMols_[32 * bx + tx][ty][0] + maskCenter[1] * SolventMols_[32 * bx + tx][ty][1] + maskCenter[2] * SolventMols_[32 * bx + tx][ty][2];
if (Dist + 1 <= D__(tx + 32 * bx))
D_[32 * bx + tx] = Dist;
} | .file "tmpxft_0018901e_00000000-6_rose_simple_action_noImage.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z19Action_No_image_GPUPdS_PA1024_A3_dPdS_PA1024_A3_d
.type _Z52__device_stub__Z19Action_No_image_GPUPdS_PA1024_A3_dPdS_PA1024_A3_d, @function
_Z52__device_stub__Z19Action_No_image_GPUPdS_PA1024_A3_dPdS_PA1024_A3_d:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19Action_No_image_GPUPdS_PA1024_A3_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z52__device_stub__Z19Action_No_image_GPUPdS_PA1024_A3_dPdS_PA1024_A3_d, .-_Z52__device_stub__Z19Action_No_image_GPUPdS_PA1024_A3_dPdS_PA1024_A3_d
.globl _Z19Action_No_image_GPUPdS_PA1024_A3_d
.type _Z19Action_No_image_GPUPdS_PA1024_A3_d, @function
_Z19Action_No_image_GPUPdS_PA1024_A3_d:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z19Action_No_image_GPUPdS_PA1024_A3_dPdS_PA1024_A3_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z19Action_No_image_GPUPdS_PA1024_A3_d, .-_Z19Action_No_image_GPUPdS_PA1024_A3_d
.globl _Z21Action_NoImage_CenterPA1024_A3_dPdS2_d
.type _Z21Action_NoImage_CenterPA1024_A3_dPdS2_d, @function
_Z21Action_NoImage_CenterPA1024_A3_dPdS2_d:
.LFB2027:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rsi, %rbx
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $24576, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $24, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $25165824, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $25165824, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $32, 44(%rsp)
movl $32, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $24576, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z52__device_stub__Z19Action_No_image_GPUPdS_PA1024_A3_dPdS_PA1024_A3_d
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z21Action_NoImage_CenterPA1024_A3_dPdS2_d, .-_Z21Action_NoImage_CenterPA1024_A3_dPdS2_d
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19Action_No_image_GPUPdS_PA1024_A3_d"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19Action_No_image_GPUPdS_PA1024_A3_d(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define __rose_lt(x,y) ((x)<(y)?(x):(y))
#define __rose_gt(x,y) ((x)>(y)?(x):(y))
#define D__(solventMol) D_[solventMol]
__global__ void Action_No_image_GPU(double *D_,double *maskCenter,double (*SolventMols_)[1024][3]);
//this is only used for cuda-chill
//heavy simplification
#define NsolventMolecules_ 1024
#define NsolventAtoms_ 1024
// struct MolDist {
// int mol; ///< Original solvent molecule number (starts from 1).
// double D; ///< Closest distance of solvent molecule to atoms in distanceMask.
// //AtomMask mask; ///< Original topology solvent molecule atom mask.
// double solventAtoms[NsolventAtoms_][3]; ///< Actual solvent atom #s to loop over.
// };
//using dist for no image
// and kernel for when we use solute molecule center
//extracting pulling out arrays out from struct
void Action_NoImage_Center(double SolventMols_[1024][1024][3],double D_[1024],double maskCenter[3],double maxD)
{
double *devI2Ptr;
double *devI1Ptr;
double *devO1Ptr;
int t8;
int t10;
int t4;
int t2;
double Dist;
int solventMol;
int solventAtom;
cudaMalloc(((void **)(&devO1Ptr)),3072 * sizeof(double ));
cudaMalloc(((void **)(&devI1Ptr)),3 * sizeof(double ));
cudaMemcpy(devI1Ptr,maskCenter,3 * sizeof(double ),cudaMemcpyHostToDevice);
cudaMalloc(((void **)(&devI2Ptr)),3145728 * sizeof(double ));
cudaMemcpy(devI2Ptr,SolventMols_,3145728 * sizeof(double ),cudaMemcpyHostToDevice);
dim3 dimGrid0 = dim3(32,32);
dim3 dimBlock0 = dim3(32,32);
Action_No_image_GPU<<<dimGrid0,dimBlock0>>>(devO1Ptr,devI1Ptr,((double (*)[1024][3])devI2Ptr));
cudaMemcpy(D_,devO1Ptr,3072 * sizeof(double ),cudaMemcpyDeviceToHost);
cudaFree(devO1Ptr);
cudaFree(devI1Ptr);
cudaFree(devI2Ptr);
}
__global__ void Action_No_image_GPU(double *D_,double *maskCenter,double (*SolventMols_)[1024][3])
{
int bx;
bx = blockIdx.x;
int by;
by = blockIdx.y;
int tx;
tx = threadIdx.x;
int ty;
ty = threadIdx.y;
double maxD;
double Dist;
int t2;
int t4;
int t10;
int t8;
D_[32 * bx + tx] = maxD;
//main dist2_noImage code
//double *a1 = maskCenter.Dptr(); //center of solute molecule
//double *a2 = frmIn.XYZ(*solvent_atom);
//double *a1 = maskCenter; //center of solute molecule
//double *a2 = SolventMols_[solventMol][solventAtom];
//double x = a1[0] - a2[0];
//double y = a1[1] - a2[1];
//double z = a1[2] - a2[2];
//Dist = (x*x + y*y + z*z);
Dist = maskCenter[0] * SolventMols_[32 * bx + tx][ty][0] + maskCenter[1] * SolventMols_[32 * bx + tx][ty][1] + maskCenter[2] * SolventMols_[32 * bx + tx][ty][2];
if (Dist + 1 <= D__(tx + 32 * bx))
D_[32 * bx + tx] = Dist;
} | #include <hip/hip_runtime.h>
#define __rose_lt(x,y) ((x)<(y)?(x):(y))
#define __rose_gt(x,y) ((x)>(y)?(x):(y))
#define D__(solventMol) D_[solventMol]
__global__ void Action_No_image_GPU(double *D_,double *maskCenter,double (*SolventMols_)[1024][3]);
//this is only used for cuda-chill
//heavy simplification
#define NsolventMolecules_ 1024
#define NsolventAtoms_ 1024
// struct MolDist {
// int mol; ///< Original solvent molecule number (starts from 1).
// double D; ///< Closest distance of solvent molecule to atoms in distanceMask.
// //AtomMask mask; ///< Original topology solvent molecule atom mask.
// double solventAtoms[NsolventAtoms_][3]; ///< Actual solvent atom #s to loop over.
// };
//using dist for no image
// and kernel for when we use solute molecule center
//extracting pulling out arrays out from struct
void Action_NoImage_Center(double SolventMols_[1024][1024][3],double D_[1024],double maskCenter[3],double maxD)
{
double *devI2Ptr;
double *devI1Ptr;
double *devO1Ptr;
int t8;
int t10;
int t4;
int t2;
double Dist;
int solventMol;
int solventAtom;
hipMalloc(((void **)(&devO1Ptr)),3072 * sizeof(double ));
hipMalloc(((void **)(&devI1Ptr)),3 * sizeof(double ));
hipMemcpy(devI1Ptr,maskCenter,3 * sizeof(double ),hipMemcpyHostToDevice);
hipMalloc(((void **)(&devI2Ptr)),3145728 * sizeof(double ));
hipMemcpy(devI2Ptr,SolventMols_,3145728 * sizeof(double ),hipMemcpyHostToDevice);
dim3 dimGrid0 = dim3(32,32);
dim3 dimBlock0 = dim3(32,32);
Action_No_image_GPU<<<dimGrid0,dimBlock0>>>(devO1Ptr,devI1Ptr,((double (*)[1024][3])devI2Ptr));
hipMemcpy(D_,devO1Ptr,3072 * sizeof(double ),hipMemcpyDeviceToHost);
hipFree(devO1Ptr);
hipFree(devI1Ptr);
hipFree(devI2Ptr);
}
__global__ void Action_No_image_GPU(double *D_,double *maskCenter,double (*SolventMols_)[1024][3])
{
int bx;
bx = blockIdx.x;
int by;
by = blockIdx.y;
int tx;
tx = threadIdx.x;
int ty;
ty = threadIdx.y;
double maxD;
double Dist;
int t2;
int t4;
int t10;
int t8;
D_[32 * bx + tx] = maxD;
//main dist2_noImage code
//double *a1 = maskCenter.Dptr(); //center of solute molecule
//double *a2 = frmIn.XYZ(*solvent_atom);
//double *a1 = maskCenter; //center of solute molecule
//double *a2 = SolventMols_[solventMol][solventAtom];
//double x = a1[0] - a2[0];
//double y = a1[1] - a2[1];
//double z = a1[2] - a2[2];
//Dist = (x*x + y*y + z*z);
Dist = maskCenter[0] * SolventMols_[32 * bx + tx][ty][0] + maskCenter[1] * SolventMols_[32 * bx + tx][ty][1] + maskCenter[2] * SolventMols_[32 * bx + tx][ty][2];
if (Dist + 1 <= D__(tx + 32 * bx))
D_[32 * bx + tx] = Dist;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define __rose_lt(x,y) ((x)<(y)?(x):(y))
#define __rose_gt(x,y) ((x)>(y)?(x):(y))
#define D__(solventMol) D_[solventMol]
__global__ void Action_No_image_GPU(double *D_,double *maskCenter,double (*SolventMols_)[1024][3]);
//this is only used for cuda-chill
//heavy simplification
#define NsolventMolecules_ 1024
#define NsolventAtoms_ 1024
// struct MolDist {
// int mol; ///< Original solvent molecule number (starts from 1).
// double D; ///< Closest distance of solvent molecule to atoms in distanceMask.
// //AtomMask mask; ///< Original topology solvent molecule atom mask.
// double solventAtoms[NsolventAtoms_][3]; ///< Actual solvent atom #s to loop over.
// };
//using dist for no image
// and kernel for when we use solute molecule center
//extracting pulling out arrays out from struct
void Action_NoImage_Center(double SolventMols_[1024][1024][3],double D_[1024],double maskCenter[3],double maxD)
{
double *devI2Ptr;
double *devI1Ptr;
double *devO1Ptr;
int t8;
int t10;
int t4;
int t2;
double Dist;
int solventMol;
int solventAtom;
hipMalloc(((void **)(&devO1Ptr)),3072 * sizeof(double ));
hipMalloc(((void **)(&devI1Ptr)),3 * sizeof(double ));
hipMemcpy(devI1Ptr,maskCenter,3 * sizeof(double ),hipMemcpyHostToDevice);
hipMalloc(((void **)(&devI2Ptr)),3145728 * sizeof(double ));
hipMemcpy(devI2Ptr,SolventMols_,3145728 * sizeof(double ),hipMemcpyHostToDevice);
dim3 dimGrid0 = dim3(32,32);
dim3 dimBlock0 = dim3(32,32);
Action_No_image_GPU<<<dimGrid0,dimBlock0>>>(devO1Ptr,devI1Ptr,((double (*)[1024][3])devI2Ptr));
hipMemcpy(D_,devO1Ptr,3072 * sizeof(double ),hipMemcpyDeviceToHost);
hipFree(devO1Ptr);
hipFree(devI1Ptr);
hipFree(devI2Ptr);
}
__global__ void Action_No_image_GPU(double *D_,double *maskCenter,double (*SolventMols_)[1024][3])
{
int bx;
bx = blockIdx.x;
int by;
by = blockIdx.y;
int tx;
tx = threadIdx.x;
int ty;
ty = threadIdx.y;
double maxD;
double Dist;
int t2;
int t4;
int t10;
int t8;
D_[32 * bx + tx] = maxD;
//main dist2_noImage code
//double *a1 = maskCenter.Dptr(); //center of solute molecule
//double *a2 = frmIn.XYZ(*solvent_atom);
//double *a1 = maskCenter; //center of solute molecule
//double *a2 = SolventMols_[solventMol][solventAtom];
//double x = a1[0] - a2[0];
//double y = a1[1] - a2[1];
//double z = a1[2] - a2[2];
//Dist = (x*x + y*y + z*z);
Dist = maskCenter[0] * SolventMols_[32 * bx + tx][ty][0] + maskCenter[1] * SolventMols_[32 * bx + tx][ty][1] + maskCenter[2] * SolventMols_[32 * bx + tx][ty][2];
if (Dist + 1 <= D__(tx + 32 * bx))
D_[32 * bx + tx] = Dist;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19Action_No_image_GPUPdS_PA1024_A3_d
.globl _Z19Action_No_image_GPUPdS_PA1024_A3_d
.p2align 8
.type _Z19Action_No_image_GPUPdS_PA1024_A3_d,@function
_Z19Action_No_image_GPUPdS_PA1024_A3_d:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19Action_No_image_GPUPdS_PA1024_A3_d
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19Action_No_image_GPUPdS_PA1024_A3_d, .Lfunc_end0-_Z19Action_No_image_GPUPdS_PA1024_A3_d
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19Action_No_image_GPUPdS_PA1024_A3_d
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z19Action_No_image_GPUPdS_PA1024_A3_d.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define __rose_lt(x,y) ((x)<(y)?(x):(y))
#define __rose_gt(x,y) ((x)>(y)?(x):(y))
#define D__(solventMol) D_[solventMol]
__global__ void Action_No_image_GPU(double *D_,double *maskCenter,double (*SolventMols_)[1024][3]);
//this is only used for cuda-chill
//heavy simplification
#define NsolventMolecules_ 1024
#define NsolventAtoms_ 1024
// struct MolDist {
// int mol; ///< Original solvent molecule number (starts from 1).
// double D; ///< Closest distance of solvent molecule to atoms in distanceMask.
// //AtomMask mask; ///< Original topology solvent molecule atom mask.
// double solventAtoms[NsolventAtoms_][3]; ///< Actual solvent atom #s to loop over.
// };
//using dist for no image
// and kernel for when we use solute molecule center
//extracting pulling out arrays out from struct
void Action_NoImage_Center(double SolventMols_[1024][1024][3],double D_[1024],double maskCenter[3],double maxD)
{
double *devI2Ptr;
double *devI1Ptr;
double *devO1Ptr;
int t8;
int t10;
int t4;
int t2;
double Dist;
int solventMol;
int solventAtom;
hipMalloc(((void **)(&devO1Ptr)),3072 * sizeof(double ));
hipMalloc(((void **)(&devI1Ptr)),3 * sizeof(double ));
hipMemcpy(devI1Ptr,maskCenter,3 * sizeof(double ),hipMemcpyHostToDevice);
hipMalloc(((void **)(&devI2Ptr)),3145728 * sizeof(double ));
hipMemcpy(devI2Ptr,SolventMols_,3145728 * sizeof(double ),hipMemcpyHostToDevice);
dim3 dimGrid0 = dim3(32,32);
dim3 dimBlock0 = dim3(32,32);
Action_No_image_GPU<<<dimGrid0,dimBlock0>>>(devO1Ptr,devI1Ptr,((double (*)[1024][3])devI2Ptr));
hipMemcpy(D_,devO1Ptr,3072 * sizeof(double ),hipMemcpyDeviceToHost);
hipFree(devO1Ptr);
hipFree(devI1Ptr);
hipFree(devI2Ptr);
}
__global__ void Action_No_image_GPU(double *D_,double *maskCenter,double (*SolventMols_)[1024][3])
{
int bx;
bx = blockIdx.x;
int by;
by = blockIdx.y;
int tx;
tx = threadIdx.x;
int ty;
ty = threadIdx.y;
double maxD;
double Dist;
int t2;
int t4;
int t10;
int t8;
D_[32 * bx + tx] = maxD;
//main dist2_noImage code
//double *a1 = maskCenter.Dptr(); //center of solute molecule
//double *a2 = frmIn.XYZ(*solvent_atom);
//double *a1 = maskCenter; //center of solute molecule
//double *a2 = SolventMols_[solventMol][solventAtom];
//double x = a1[0] - a2[0];
//double y = a1[1] - a2[1];
//double z = a1[2] - a2[2];
//Dist = (x*x + y*y + z*z);
Dist = maskCenter[0] * SolventMols_[32 * bx + tx][ty][0] + maskCenter[1] * SolventMols_[32 * bx + tx][ty][1] + maskCenter[2] * SolventMols_[32 * bx + tx][ty][2];
if (Dist + 1 <= D__(tx + 32 * bx))
D_[32 * bx + tx] = Dist;
} | .text
.file "rose_simple_action_noImage.hip"
.globl _Z21Action_NoImage_CenterPA1024_A3_dPdS2_d # -- Begin function _Z21Action_NoImage_CenterPA1024_A3_dPdS2_d
.p2align 4, 0x90
.type _Z21Action_NoImage_CenterPA1024_A3_dPdS2_d,@function
_Z21Action_NoImage_CenterPA1024_A3_dPdS2_d: # @_Z21Action_NoImage_CenterPA1024_A3_dPdS2_d
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r15
movq %rsi, %rbx
movq %rdi, %r14
movq %rsp, %rdi
movl $24576, %esi # imm = 0x6000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $24, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $24, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movl $25165824, %esi # imm = 0x1800000
callq hipMalloc
movq 16(%rsp), %rdi
movl $25165824, %edx # imm = 0x1800000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19Action_No_image_GPUPdS_PA1024_A3_d, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq (%rsp), %rsi
movl $24576, %edx # imm = 0x6000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21Action_NoImage_CenterPA1024_A3_dPdS2_d, .Lfunc_end0-_Z21Action_NoImage_CenterPA1024_A3_dPdS2_d
.cfi_endproc
# -- End function
.globl _Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d # -- Begin function _Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d
.p2align 4, 0x90
.type _Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d,@function
_Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d: # @_Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19Action_No_image_GPUPdS_PA1024_A3_d, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d, .Lfunc_end1-_Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19Action_No_image_GPUPdS_PA1024_A3_d, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19Action_No_image_GPUPdS_PA1024_A3_d,@object # @_Z19Action_No_image_GPUPdS_PA1024_A3_d
.section .rodata,"a",@progbits
.globl _Z19Action_No_image_GPUPdS_PA1024_A3_d
.p2align 3, 0x0
_Z19Action_No_image_GPUPdS_PA1024_A3_d:
.quad _Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d
.size _Z19Action_No_image_GPUPdS_PA1024_A3_d, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19Action_No_image_GPUPdS_PA1024_A3_d"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19Action_No_image_GPUPdS_PA1024_A3_d
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19Action_No_image_GPUPdS_PA1024_A3_d
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R18, SR_CTAID.X ; /* 0x0000000000127919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 512 ; /* 0x00006000ff077435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0060*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0070*/ LEA R18, R18, R3, 0x5 ; /* 0x0000000312127211 */
/* 0x001fca00078e28ff */
/*0080*/ IMAD.WIDE R2, R18, R7, c[0x0][0x170] ; /* 0x00005c0012027625 */
/* 0x000fe200078e0207 */
/*0090*/ MOV R7, c[0x0][0x16c] ; /* 0x00005b0000077a02 */
/* 0x000fca0000000f00 */
/*00a0*/ IMAD.WIDE R2, R5, 0x18, R2 ; /* 0x0000001805027825 */
/* 0x002fe200078e0202 */
/*00b0*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea8000c1e1b00 */
/*00c0*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000ea2000c1e1b00 */
/*00d0*/ HFMA2.MMA R19, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff137435 */
/* 0x000fc600000001ff */
/*00e0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ee8000c1e1b00 */
/*00f0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ee8000c1e1b00 */
/*0100*/ LDG.E.64 R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000f28000c1e1b00 */
/*0110*/ LDG.E.64 R14, [R2.64+0x10] ; /* 0x00001004020e7981 */
/* 0x000f22000c1e1b00 */
/*0120*/ IMAD.WIDE R18, R18, R19, c[0x0][0x160] ; /* 0x0000580012127625 */
/* 0x000fca00078e0213 */
/*0130*/ LDG.E.64 R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000f62000c1e1b00 */
/*0140*/ DMUL R10, R10, R12 ; /* 0x0000000c0a0a7228 */
/* 0x004ecc0000000000 */
/*0150*/ DFMA R4, R4, R8, R10 ; /* 0x000000080404722b */
/* 0x008f0c000000000a */
/*0160*/ DFMA R4, R14, R16, R4 ; /* 0x000000100e04722b */
/* 0x010e0c0000000004 */
/*0170*/ DADD R8, R4, 1 ; /* 0x3ff0000004087429 */
/* 0x001f4c0000000000 */
/*0180*/ DSETP.GTU.AND P0, PT, R8, R20, PT ; /* 0x000000140800722a */
/* 0x020e1c0003f0c000 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01a0*/ STG.E.64 [R18.64], R4 ; /* 0x0000000412007986 */
/* 0x000fe2000c101b04 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19Action_No_image_GPUPdS_PA1024_A3_d
.globl _Z19Action_No_image_GPUPdS_PA1024_A3_d
.p2align 8
.type _Z19Action_No_image_GPUPdS_PA1024_A3_d,@function
_Z19Action_No_image_GPUPdS_PA1024_A3_d:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19Action_No_image_GPUPdS_PA1024_A3_d
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19Action_No_image_GPUPdS_PA1024_A3_d, .Lfunc_end0-_Z19Action_No_image_GPUPdS_PA1024_A3_d
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19Action_No_image_GPUPdS_PA1024_A3_d
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z19Action_No_image_GPUPdS_PA1024_A3_d.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018901e_00000000-6_rose_simple_action_noImage.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z19Action_No_image_GPUPdS_PA1024_A3_dPdS_PA1024_A3_d
.type _Z52__device_stub__Z19Action_No_image_GPUPdS_PA1024_A3_dPdS_PA1024_A3_d, @function
_Z52__device_stub__Z19Action_No_image_GPUPdS_PA1024_A3_dPdS_PA1024_A3_d:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19Action_No_image_GPUPdS_PA1024_A3_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z52__device_stub__Z19Action_No_image_GPUPdS_PA1024_A3_dPdS_PA1024_A3_d, .-_Z52__device_stub__Z19Action_No_image_GPUPdS_PA1024_A3_dPdS_PA1024_A3_d
.globl _Z19Action_No_image_GPUPdS_PA1024_A3_d
.type _Z19Action_No_image_GPUPdS_PA1024_A3_d, @function
_Z19Action_No_image_GPUPdS_PA1024_A3_d:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z19Action_No_image_GPUPdS_PA1024_A3_dPdS_PA1024_A3_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z19Action_No_image_GPUPdS_PA1024_A3_d, .-_Z19Action_No_image_GPUPdS_PA1024_A3_d
.globl _Z21Action_NoImage_CenterPA1024_A3_dPdS2_d
.type _Z21Action_NoImage_CenterPA1024_A3_dPdS2_d, @function
_Z21Action_NoImage_CenterPA1024_A3_dPdS2_d:
.LFB2027:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rsi, %rbx
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $24576, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $24, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $25165824, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $25165824, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $32, 44(%rsp)
movl $32, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $24576, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z52__device_stub__Z19Action_No_image_GPUPdS_PA1024_A3_dPdS_PA1024_A3_d
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z21Action_NoImage_CenterPA1024_A3_dPdS2_d, .-_Z21Action_NoImage_CenterPA1024_A3_dPdS2_d
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19Action_No_image_GPUPdS_PA1024_A3_d"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19Action_No_image_GPUPdS_PA1024_A3_d(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rose_simple_action_noImage.hip"
.globl _Z21Action_NoImage_CenterPA1024_A3_dPdS2_d # -- Begin function _Z21Action_NoImage_CenterPA1024_A3_dPdS2_d
.p2align 4, 0x90
.type _Z21Action_NoImage_CenterPA1024_A3_dPdS2_d,@function
_Z21Action_NoImage_CenterPA1024_A3_dPdS2_d: # @_Z21Action_NoImage_CenterPA1024_A3_dPdS2_d
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r15
movq %rsi, %rbx
movq %rdi, %r14
movq %rsp, %rdi
movl $24576, %esi # imm = 0x6000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $24, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $24, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movl $25165824, %esi # imm = 0x1800000
callq hipMalloc
movq 16(%rsp), %rdi
movl $25165824, %edx # imm = 0x1800000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19Action_No_image_GPUPdS_PA1024_A3_d, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq (%rsp), %rsi
movl $24576, %edx # imm = 0x6000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21Action_NoImage_CenterPA1024_A3_dPdS2_d, .Lfunc_end0-_Z21Action_NoImage_CenterPA1024_A3_dPdS2_d
.cfi_endproc
# -- End function
.globl _Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d # -- Begin function _Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d
.p2align 4, 0x90
.type _Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d,@function
_Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d: # @_Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19Action_No_image_GPUPdS_PA1024_A3_d, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d, .Lfunc_end1-_Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19Action_No_image_GPUPdS_PA1024_A3_d, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19Action_No_image_GPUPdS_PA1024_A3_d,@object # @_Z19Action_No_image_GPUPdS_PA1024_A3_d
.section .rodata,"a",@progbits
.globl _Z19Action_No_image_GPUPdS_PA1024_A3_d
.p2align 3, 0x0
_Z19Action_No_image_GPUPdS_PA1024_A3_d:
.quad _Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d
.size _Z19Action_No_image_GPUPdS_PA1024_A3_d, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19Action_No_image_GPUPdS_PA1024_A3_d"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__Action_No_image_GPUPdS_PA1024_A3_d
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19Action_No_image_GPUPdS_PA1024_A3_d
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
using namespace std;
void print_matrix(int** world,int m, int n){
for (int i = 0; i < m; i++){
cout<<"| ";
for(int j =0; j < n; j++){
cout<<world[i][j]<<" ";
}
cout<<"|\n";
}
cout<<"\n";
}
int ** create_empty_world(int m, int n){
int **world = 0;
world = new int*[m];
for(int i = 0; i < m; i++){
world[i] = new int[n];
for(int j = 0; j < n; j++){
world[i][j] = 0;
}
}
return world;
}
//just a normal CPU function here. making a world filled with values of 0 or 1
int ** create_world(int m, int n){
int **world = 0;
world = new int*[m];
int value;
srand(time(0));
for (int i = 0; i < m; i ++){
world[i] = new int[n];
for(int j = 0 ; j < n; j ++){
//setting up padding
if(i == 0 || j == 0 || i == m -2 || j == n -2){
world[i][j] = 0;
}else{
//giving the world[m][n] a value between 1 and 0
value = rand() % 2;
world[i][j] = value;
}
}
}
return world;
}
/*
this will take the world, the new world, the hight and width of the worlds
We will then go through every value, sum the value of it's 8 neighbours
and give a result of 1 or 0 for each cell
we will do this for the number of turns that we have specified in the command line arguments.
*/
__global__
void next_turn(int **world, int **new_world, int m, int n ){
//getting the index that we are currently in
int const index_x = threadIdx.x + blockIdx.x * blockDim.x;
if(index_x < m + 1 && index_x != 0){
for(int index_y = 1; index_y < n - 1 ; index_y++){
int living = world[index_x-1][index_y-1] + world[index_x-1][index_y] + world[index_x-1][index_y+1] +
world[index_x][index_y+1] + world[index_x+1][index_y-1] + world[index_x+1][index_y] +
world[index_x+1][index_y+1] + world[index_x][index_y-1];
int current = world[index_x][index_y];
int new_cell = 0;
if((current == 1 && (living == 3 || living == 2)) || current == 0 && living == 3){
new_cell = 1;
}
new_world[index_x][index_y] = new_cell;
}
}
}
//set up numblocks to be a calculation of how many are needed
int const numblocks = 1;
int const blocksize = 1;
int main(int argc, char *argv[]){
//verifying the number of arguments
if(argc <5 || argc> 6){
cout<<"Usage: ./gol [width] [height] [iterations] [number of tests]";
return 1;
}
//gathering data from the arguments
int m = atoi(argv[1]);
m = m + 2;
int n = atoi(argv[2]);
n = n + 2;
int iterations = atoi(argv[3]);
int num_tests = atoi(argv[4]);
int size = sizeof(int) * m * n;
//verifying the arguments are able to be converted to int values
if((m == 0) || (n == 0) || (iterations == 0) || (num_tests == 0)){
cout<< "must enter INT values";
return 0;
}
//create a world and a new world
int **world = create_world(m, n);
int **new_world = create_empty_world(m, n);
print_matrix(world, m, n);
//create a matrix of ints for the device
int **dev_world;
int **dev_new_world;
cudaMalloc((void **)&dev_world, size);
cudaMalloc((void **)&dev_new_world, size);
if(dev_world == NULL) {std::cerr << "not able to alloc memory on device" << std::endl;}
if(dev_new_world == NULL) {std::cerr << "not able to alloc memory on device" << std::endl;}
//copy values from host to device
cudaMemcpy(dev_world, world, size, cudaMemcpyHostToDevice);
//cudaMemcpy(dev_new_world, new_world, size, cudaMemcpyHostToDevice);
//no output yet, don't need to copy it over
//set up timing here, no need to take into account how long it takes to copy stuffs over.
//do next_turn on GPU
//for(int i = 0; i < iterations; i ++){
next_turn<<< numblocks, blocksize >>>(dev_world, dev_new_world, m, n);
//}
//copy result back to host
cudaMemcpy(new_world, dev_new_world, size, cudaMemcpyDeviceToHost);
print_matrix(new_world, m, n);
//free space that we created
for(int i = 0; i < m ; i++){
free(world[i]);
free(new_world[i]);
}
free(world);
free(new_world);
cudaFree(dev_new_world);
cudaFree(dev_world);
} | code for sm_80
Function : _Z9next_turnPPiS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff027624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GT.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fc80003f04270 */
/*0060*/ ISETP.EQ.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fc80000702670 */
/*0070*/ ISETP.LT.OR P0, PT, R2, 0x3, P0 ; /* 0x000000030200780c */
/* 0x000fda0000701670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ ISETP.NE.AND P0, PT, R2.reuse, 0x3, PT ; /* 0x000000030200780c */
/* 0x040fe20003f05270 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R0, R2, -0x2, RZ ; /* 0xfffffffe02007810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*00d0*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fe200078e0205 */
/*00e0*/ LOP3.LUT R6, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100067812 */
/* 0x000fc600078ec0ff */
/*00f0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0100*/ ISETP.NE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f45270 */
/*0110*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe400078e0205 */
/*0120*/ @!P0 BRA 0x5f0 ; /* 0x000004c000008947 */
/* 0x000ff40003800000 */
/*0130*/ IADD3 R6, -R6, c[0x0][0x174], RZ ; /* 0x00005d0006067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0150*/ UMOV UR5, 0x8 ; /* 0x0000000800057882 */
/* 0x000fe40000000000 */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0170*/ LDG.E.64 R12, [R2.64+-0x8] ; /* 0xfffff806020c7981 */
/* 0x000ea8000c1e1b00 */
/*0180*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x001ee8000c1e1b00 */
/*0190*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000806020a7981 */
/* 0x000f22000c1e1b00 */
/*01a0*/ IADD3 R12, P0, R12, UR5, RZ ; /* 0x000000050c0c7c10 */
/* 0x004fc4000ff1e0ff */
/*01b0*/ IADD3 R8, P1, R8, UR5, RZ ; /* 0x0000000508087c10 */
/* 0x008fe4000ff3e0ff */
/*01c0*/ IADD3.X R13, R13, UR4, RZ, P0, !PT ; /* 0x000000040d0d7c10 */
/* 0x000fe400087fe4ff */
/*01d0*/ IADD3 R14, P3, R10, UR5, RZ ; /* 0x000000050a0e7c10 */
/* 0x010fe4000ff7e0ff */
/*01e0*/ IADD3.X R9, R9, UR4, RZ, P1, !PT ; /* 0x0000000409097c10 */
/* 0x000fe20008ffe4ff */
/*01f0*/ LDG.E R7, [R12.64+-0x4] ; /* 0xfffffc060c077981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3.X R15, R11, UR4, RZ, P3, !PT ; /* 0x000000040b0f7c10 */
/* 0x000fc60009ffe4ff */
/*0210*/ LDG.E R16, [R12.64+-0x8] ; /* 0xfffff8060c107981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R17, [R12.64] ; /* 0x000000060c117981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R18, [R8.64] ; /* 0x0000000608127981 */
/* 0x000ee8000c1e1900 */
/*0240*/ LDG.E R19, [R14.64+-0x8] ; /* 0xfffff8060e137981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R20, [R14.64+-0x4] ; /* 0xfffffc060e147981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R21, [R14.64] ; /* 0x000000060e157981 */
/* 0x000f28000c1e1900 */
/*0270*/ LDG.E R22, [R8.64+-0x8] ; /* 0xfffff80608167981 */
/* 0x000f68000c1e1900 */
/*0280*/ LDG.E R23, [R8.64+-0x4] ; /* 0xfffffc0608177981 */
/* 0x000f68000c1e1900 */
/*0290*/ LDG.E.64 R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000f62000c1e1b00 */
/*02a0*/ IADD3 R7, R17, R7, R16 ; /* 0x0000000711077210 */
/* 0x004fc80007ffe010 */
/*02b0*/ IADD3 R7, R19, R7, R18 ; /* 0x0000000713077210 */
/* 0x008fc80007ffe012 */
/*02c0*/ IADD3 R7, R21, R7, R20 ; /* 0x0000000715077210 */
/* 0x010fca0007ffe014 */
/*02d0*/ IMAD.IADD R7, R7, 0x1, R22 ; /* 0x0000000107077824 */
/* 0x020fca00078e0216 */
/*02e0*/ LOP3.LUT R12, R7.reuse, 0x1, RZ, 0xfc, !PT ; /* 0x00000001070c7812 */
/* 0x040fe400078efcff */
/*02f0*/ ISETP.NE.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe40003f05270 */
/*0300*/ ISETP.NE.AND P1, PT, R12, 0x3, PT ; /* 0x000000030c00780c */
/* 0x000fe40003f25270 */
/*0310*/ ISETP.EQ.AND P0, PT, R23.reuse, RZ, !P0 ; /* 0x000000ff1700720c */
/* 0x040fe40004702270 */
/*0320*/ ISETP.EQ.AND P1, PT, R23, 0x1, !P1 ; /* 0x000000011700780c */
/* 0x000fe40004f22270 */
/*0330*/ IADD3 R16, P3, R10, UR5, RZ ; /* 0x000000050a107c10 */
/* 0x000fc4000ff7e0ff */
/*0340*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0350*/ IADD3.X R17, R11, UR4, RZ, P3, !PT ; /* 0x000000040b117c10 */
/* 0x000fe40009ffe4ff */
/*0360*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fca0004000000 */
/*0370*/ STG.E [R16.64+-0x4], R7 ; /* 0xfffffc0710007986 */
/* 0x0001e8000c101906 */
/*0380*/ LDG.E.64 R8, [R2.64+-0x8] ; /* 0xfffff80602087981 */
/* 0x000ea8000c1e1b00 */
/*0390*/ LDG.E.64 R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ee8000c1e1b00 */
/*03a0*/ LDG.E.64 R14, [R2.64+0x8] ; /* 0x00000806020e7981 */
/* 0x000f22000c1e1b00 */
/*03b0*/ IADD3 R12, P0, R8, UR5, RZ ; /* 0x00000005080c7c10 */
/* 0x004fc4000ff1e0ff */
/*03c0*/ IADD3 R8, P1, R10, UR5, RZ ; /* 0x000000050a087c10 */
/* 0x008fe4000ff3e0ff */
/*03d0*/ IADD3.X R13, R9, UR4, RZ, P0, !PT ; /* 0x00000004090d7c10 */
/* 0x000fe400087fe4ff */
/*03e0*/ IADD3 R14, P3, R14, UR5, RZ ; /* 0x000000050e0e7c10 */
/* 0x010fe4000ff7e0ff */
/*03f0*/ IADD3.X R9, R11, UR4, RZ, P1, !PT ; /* 0x000000040b097c10 */
/* 0x000fe20008ffe4ff */
/*0400*/ LDG.E R18, [R12.64] ; /* 0x000000060c127981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IADD3.X R15, R15, UR4, RZ, P3, !PT ; /* 0x000000040f0f7c10 */
/* 0x000fc60009ffe4ff */
/*0420*/ LDG.E R7, [R12.64+-0x4] ; /* 0xfffffc060c077981 */
/* 0x001ea8000c1e1900 */
/*0430*/ LDG.E R16, [R12.64+0x4] ; /* 0x000004060c107981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R20, [R8.64+0x4] ; /* 0x0000040608147981 */
/* 0x000ee8000c1e1900 */
/*0450*/ LDG.E R17, [R14.64+-0x4] ; /* 0xfffffc060e117981 */
/* 0x000ee8000c1e1900 */
/*0460*/ LDG.E R22, [R14.64] ; /* 0x000000060e167981 */
/* 0x000f28000c1e1900 */
/*0470*/ LDG.E R19, [R14.64+0x4] ; /* 0x000004060e137981 */
/* 0x000f28000c1e1900 */
/*0480*/ LDG.E R24, [R8.64+-0x4] ; /* 0xfffffc0608187981 */
/* 0x000f68000c1e1900 */
/*0490*/ LDG.E R21, [R8.64] ; /* 0x0000000608157981 */
/* 0x000f68000c1e1900 */
/*04a0*/ LDG.E.64 R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000f62000c1e1b00 */
/*04b0*/ IADD3 R6, R6, -0x2, RZ ; /* 0xfffffffe06067810 */
/* 0x000fc40007ffe0ff */
/*04c0*/ IADD3 R0, R0, 0x2, RZ ; /* 0x0000000200007810 */
/* 0x000fe40007ffe0ff */
/*04d0*/ IADD3 R7, R16, R18, R7 ; /* 0x0000001210077210 */
/* 0x004fc80007ffe007 */
/*04e0*/ IADD3 R7, R17, R7, R20 ; /* 0x0000000711077210 */
/* 0x008fc80007ffe014 */
/*04f0*/ IADD3 R7, R19, R7, R22 ; /* 0x0000000713077210 */
/* 0x010fca0007ffe016 */
/*0500*/ IMAD.IADD R7, R7, 0x1, R24 ; /* 0x0000000107077824 */
/* 0x020fca00078e0218 */
/*0510*/ LOP3.LUT R12, R7.reuse, 0x1, RZ, 0xfc, !PT ; /* 0x00000001070c7812 */
/* 0x040fe400078efcff */
/*0520*/ ISETP.NE.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe40003f05270 */
/*0530*/ ISETP.NE.AND P1, PT, R12, 0x3, PT ; /* 0x000000030c00780c */
/* 0x000fe40003f25270 */
/*0540*/ ISETP.EQ.AND P0, PT, R21.reuse, RZ, !P0 ; /* 0x000000ff1500720c */
/* 0x040fe40004702270 */
/*0550*/ ISETP.EQ.AND P1, PT, R21, 0x1, !P1 ; /* 0x000000011500780c */
/* 0x000fc80004f22270 */
/*0560*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80000703570 */
/*0570*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fe40004000000 */
/*0580*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fe40003f05270 */
/*0590*/ IADD3 R8, P3, R10, UR5, RZ ; /* 0x000000050a087c10 */
/* 0x000fe2000ff7e0ff */
/*05a0*/ UIADD3 UR5, UP0, UR5, 0x8, URZ ; /* 0x0000000805057890 */
/* 0x000fc6000ff1e03f */
/*05b0*/ IADD3.X R9, R11, UR4, RZ, P3, !PT ; /* 0x000000040b097c10 */
/* 0x000fe20009ffe4ff */
/*05c0*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fc800087fe43f */
/*05d0*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x0001e4000c101906 */
/*05e0*/ @P0 BRA 0x170 ; /* 0xfffffb8000000947 */
/* 0x000fea000383ffff */
/*05f0*/ @!P2 EXIT ; /* 0x000000000000a94d */
/* 0x000fea0003800000 */
/*0600*/ LDG.E.64 R6, [R2.64+-0x8] ; /* 0xfffff80602067981 */
/* 0x001ea8000c1e1b00 */
/*0610*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x000ee8000c1e1b00 */
/*0620*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000806020a7981 */
/* 0x000f28000c1e1b00 */
/*0630*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000f62000c1e1b00 */
/*0640*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x004fc800078e0206 */
/*0650*/ IMAD.WIDE R8, R0.reuse, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x048fe200078e0208 */
/*0660*/ LDG.E R12, [R6.64] ; /* 0x00000006060c7981 */
/* 0x000ea6000c1e1900 */
/*0670*/ IMAD.WIDE R10, R0.reuse, 0x4, R10 ; /* 0x00000004000a7825 */
/* 0x050fe200078e020a */
/*0680*/ LDG.E R13, [R6.64+-0x4] ; /* 0xfffffc06060d7981 */
/* 0x000ea8000c1e1900 */
/*0690*/ LDG.E R14, [R6.64+0x4] ; /* 0x00000406060e7981 */
/* 0x000ea8000c1e1900 */
/*06a0*/ LDG.E R15, [R8.64+0x4] ; /* 0x00000406080f7981 */
/* 0x000ee8000c1e1900 */
/*06b0*/ LDG.E R16, [R10.64+-0x4] ; /* 0xfffffc060a107981 */
/* 0x000ee8000c1e1900 */
/*06c0*/ LDG.E R17, [R10.64] ; /* 0x000000060a117981 */
/* 0x000f28000c1e1900 */
/*06d0*/ LDG.E R18, [R10.64+0x4] ; /* 0x000004060a127981 */
/* 0x000f28000c1e1900 */
/*06e0*/ LDG.E R3, [R8.64+-0x4] ; /* 0xfffffc0608037981 */
/* 0x000f28000c1e1900 */
/*06f0*/ LDG.E R2, [R8.64] ; /* 0x0000000608027981 */
/* 0x000f22000c1e1900 */
/*0700*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x020fe200078e0204 */
/*0710*/ IADD3 R12, R14, R12, R13 ; /* 0x0000000c0e0c7210 */
/* 0x004fc80007ffe00d */
/*0720*/ IADD3 R12, R16, R12, R15 ; /* 0x0000000c100c7210 */
/* 0x008fc80007ffe00f */
/*0730*/ IADD3 R12, R18, R12, R17 ; /* 0x0000000c120c7210 */
/* 0x010fca0007ffe011 */
/*0740*/ IMAD.IADD R3, R12, 0x1, R3 ; /* 0x000000010c037824 */
/* 0x000fca00078e0203 */
/*0750*/ LOP3.LUT R6, R3.reuse, 0x1, RZ, 0xfc, !PT ; /* 0x0000000103067812 */
/* 0x040fe400078efcff */
/*0760*/ ISETP.NE.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f25270 */
/*0770*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f05270 */
/*0780*/ ISETP.EQ.AND P1, PT, R2.reuse, RZ, !P1 ; /* 0x000000ff0200720c */
/* 0x040fe40004f22270 */
/*0790*/ ISETP.EQ.AND P0, PT, R2, 0x1, !P0 ; /* 0x000000010200780c */
/* 0x000fc80004702270 */
/*07a0*/ PLOP3.LUT P0, PT, P1, P0, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80000f01570 */
/*07b0*/ SEL R3, RZ, 0x1, !P0 ; /* 0x00000001ff037807 */
/* 0x000fca0004000000 */
/*07c0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101906 */
/*07d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07e0*/ BRA 0x7e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
using namespace std;
void print_matrix(int** world,int m, int n){
for (int i = 0; i < m; i++){
cout<<"| ";
for(int j =0; j < n; j++){
cout<<world[i][j]<<" ";
}
cout<<"|\n";
}
cout<<"\n";
}
int ** create_empty_world(int m, int n){
int **world = 0;
world = new int*[m];
for(int i = 0; i < m; i++){
world[i] = new int[n];
for(int j = 0; j < n; j++){
world[i][j] = 0;
}
}
return world;
}
//just a normal CPU function here. making a world filled with values of 0 or 1
int ** create_world(int m, int n){
int **world = 0;
world = new int*[m];
int value;
srand(time(0));
for (int i = 0; i < m; i ++){
world[i] = new int[n];
for(int j = 0 ; j < n; j ++){
//setting up padding
if(i == 0 || j == 0 || i == m -2 || j == n -2){
world[i][j] = 0;
}else{
//giving the world[m][n] a value between 1 and 0
value = rand() % 2;
world[i][j] = value;
}
}
}
return world;
}
/*
this will take the world, the new world, the hight and width of the worlds
We will then go through every value, sum the value of it's 8 neighbours
and give a result of 1 or 0 for each cell
we will do this for the number of turns that we have specified in the command line arguments.
*/
__global__
void next_turn(int **world, int **new_world, int m, int n ){
//getting the index that we are currently in
int const index_x = threadIdx.x + blockIdx.x * blockDim.x;
if(index_x < m + 1 && index_x != 0){
for(int index_y = 1; index_y < n - 1 ; index_y++){
int living = world[index_x-1][index_y-1] + world[index_x-1][index_y] + world[index_x-1][index_y+1] +
world[index_x][index_y+1] + world[index_x+1][index_y-1] + world[index_x+1][index_y] +
world[index_x+1][index_y+1] + world[index_x][index_y-1];
int current = world[index_x][index_y];
int new_cell = 0;
if((current == 1 && (living == 3 || living == 2)) || current == 0 && living == 3){
new_cell = 1;
}
new_world[index_x][index_y] = new_cell;
}
}
}
//set up numblocks to be a calculation of how many are needed
int const numblocks = 1;
int const blocksize = 1;
int main(int argc, char *argv[]){
//verifying the number of arguments
if(argc <5 || argc> 6){
cout<<"Usage: ./gol [width] [height] [iterations] [number of tests]";
return 1;
}
//gathering data from the arguments
int m = atoi(argv[1]);
m = m + 2;
int n = atoi(argv[2]);
n = n + 2;
int iterations = atoi(argv[3]);
int num_tests = atoi(argv[4]);
int size = sizeof(int) * m * n;
//verifying the arguments are able to be converted to int values
if((m == 0) || (n == 0) || (iterations == 0) || (num_tests == 0)){
cout<< "must enter INT values";
return 0;
}
//create a world and a new world
int **world = create_world(m, n);
int **new_world = create_empty_world(m, n);
print_matrix(world, m, n);
//create a matrix of ints for the device
int **dev_world;
int **dev_new_world;
cudaMalloc((void **)&dev_world, size);
cudaMalloc((void **)&dev_new_world, size);
if(dev_world == NULL) {std::cerr << "not able to alloc memory on device" << std::endl;}
if(dev_new_world == NULL) {std::cerr << "not able to alloc memory on device" << std::endl;}
//copy values from host to device
cudaMemcpy(dev_world, world, size, cudaMemcpyHostToDevice);
//cudaMemcpy(dev_new_world, new_world, size, cudaMemcpyHostToDevice);
//no output yet, don't need to copy it over
//set up timing here, no need to take into account how long it takes to copy stuffs over.
//do next_turn on GPU
//for(int i = 0; i < iterations; i ++){
next_turn<<< numblocks, blocksize >>>(dev_world, dev_new_world, m, n);
//}
//copy result back to host
cudaMemcpy(new_world, dev_new_world, size, cudaMemcpyDeviceToHost);
print_matrix(new_world, m, n);
//free space that we created
for(int i = 0; i < m ; i++){
free(world[i]);
free(new_world[i]);
}
free(world);
free(new_world);
cudaFree(dev_new_world);
cudaFree(dev_world);
} | .file "tmpxft_000e68b1_00000000-6_game_of_life_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "| "
.LC1:
.string " "
.LC2:
.string "|\n"
.LC3:
.string "\n"
.text
.globl _Z12print_matrixPPiii
.type _Z12print_matrixPPiii, @function
_Z12print_matrixPPiii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
testl %esi, %esi
jle .L4
movl %edx, %r15d
movq %rdi, %rbp
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %rax
movq %rax, 8(%rsp)
movslq %edx, %r13
salq $2, %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %r14
.L7:
movl $2, %edx
leaq .LC0(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
testl %r15d, %r15d
jle .L5
movl $0, %ebx
.L6:
movq 0(%rbp), %rax
movl (%rax,%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L6
.L5:
movl $2, %edx
leaq .LC2(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, %rbp
cmpq %rbp, 8(%rsp)
jne .L7
.L4:
movl $1, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z12print_matrixPPiii, .-_Z12print_matrixPPiii
.globl _Z18create_empty_worldii
.type _Z18create_empty_worldii, @function
_Z18create_empty_worldii:
.LFB3670:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movslq %edi, %rax
movq %rax, %rcx
shrq $60, %rcx
jne .L12
movl %edi, %ebx
movl %esi, %r13d
leaq 0(,%rax,8), %r12
movq %r12, %rdi
call _Znam@PLT
movq %rax, %r14
testl %ebx, %ebx
jle .L11
movslq %r13d, %rbp
movabsq $2305843009213693950, %rax
cmpq %rbp, %rax
jb .L25
salq $2, %rbp
movq %r14, %rbx
addq %r14, %r12
.L19:
movq %rbp, %rdi
call _Znam@PLT
movq %rax, (%rbx)
movq %rax, %rdx
addq %rbp, %rax
testl %r13d, %r13d
jle .L17
.L18:
movl $0, (%rdx)
addq $4, %rdx
cmpq %rax, %rdx
jne .L18
.L17:
addq $8, %rbx
cmpq %r12, %rbx
jne .L19
.L11:
movq %r14, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.L25:
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE3670:
.size _Z18create_empty_worldii, .-_Z18create_empty_worldii
.globl _Z12create_worldii
.type _Z12create_worldii, @function
_Z12create_worldii:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %edi, 12(%rsp)
movslq %edi, %rax
movq %rax, %rdi
shrq $60, %rdi
jne .L27
movl %esi, %r15d
leaq 0(,%rax,8), %rdi
call _Znam@PLT
movq %rax, 24(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebx, %ebx
jle .L26
movslq %r15d, %r13
movabsq $2305843009213693950, %rax
cmpq %r13, %rax
jb .L43
leaq 0(,%r13,4), %rax
movq %rax, 16(%rsp)
movq 24(%rsp), %rax
movq %rax, (%rsp)
movl $0, %ebp
movl 12(%rsp), %eax
leal -2(%rax), %r14d
jmp .L36
.L27:
call __cxa_throw_bad_array_new_length@PLT
.L43:
call __cxa_throw_bad_array_new_length@PLT
.L33:
movq (%r12), %rax
movl $0, (%rax,%rbx,4)
.L35:
addq $1, %rbx
cmpq %r13, %rbx
je .L32
.L31:
testl %ebp, %ebp
je .L33
testl %ebx, %ebx
je .L33
cmpl %ebp, %r14d
je .L33
leal -2(%r15), %edx
cmpl %ebx, %edx
je .L33
call rand@PLT
movq (%r12), %rcx
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, (%rcx,%rbx,4)
jmp .L35
.L32:
addl $1, %ebp
addq $8, (%rsp)
cmpl %ebp, 12(%rsp)
je .L26
.L36:
movq 16(%rsp), %rdi
call _Znam@PLT
movq (%rsp), %rsi
movq %rsi, %r12
movq %rax, (%rsi)
movl $0, %ebx
testl %r15d, %r15d
jg .L31
jmp .L32
.L26:
movq 24(%rsp), %rax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z12create_worldii, .-_Z12create_worldii
.globl _Z34__device_stub__Z9next_turnPPiS0_iiPPiS0_ii
.type _Z34__device_stub__Z9next_turnPPiS0_iiPPiS0_ii, @function
_Z34__device_stub__Z9next_turnPPiS0_iiPPiS0_ii:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9next_turnPPiS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z34__device_stub__Z9next_turnPPiS0_iiPPiS0_ii, .-_Z34__device_stub__Z9next_turnPPiS0_iiPPiS0_ii
.globl _Z9next_turnPPiS0_ii
.type _Z9next_turnPPiS0_ii, @function
_Z9next_turnPPiS0_ii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9next_turnPPiS0_iiPPiS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z9next_turnPPiS0_ii, .-_Z9next_turnPPiS0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Usage: ./gol [width] [height] [iterations] [number of tests]"
.section .rodata.str1.1
.LC5:
.string "must enter INT values"
.section .rodata.str1.8
.align 8
.LC6:
.string "not able to alloc memory on device"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
subl $5, %edi
cmpl $1, %edi
ja .L66
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
leal 2(%rax), %r14d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
leal 2(%rax), %ebp
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
testl %r14d, %r14d
je .L55
testl %ebp, %ebp
je .L55
testl %r12d, %r12d
je .L55
testl %eax, %eax
je .L55
movl %ebp, %esi
movl %r14d, %edi
call _Z12create_worldii
movq %rax, %r13
movl %ebp, %esi
movl %r14d, %edi
call _Z18create_empty_worldii
movq %rax, %r12
movl %ebp, %edx
movl %r14d, %esi
movq %r13, %rdi
call _Z12print_matrixPPiii
movl %r14d, %ebx
imull %ebp, %ebx
sall $2, %ebx
movslq %ebx, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
cmpq $0, (%rsp)
je .L67
.L58:
cmpq $0, 8(%rsp)
je .L68
.L59:
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L60:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %ebp, %edx
movl %r14d, %esi
movq %r12, %rdi
call _Z12print_matrixPPiii
testl %r14d, %r14d
jle .L61
leal 1(%r15), %ebp
movl $0, %ebx
.L62:
movq 0(%r13,%rbx,8), %rdi
call free@PLT
movq (%r12,%rbx,8), %rdi
call free@PLT
movq %rbx, %rax
addq $1, %rbx
cmpq %rbp, %rax
jne .L62
.L61:
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L52
.L66:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %eax
.L52:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L70
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %eax
jmp .L52
.L67:
leaq .LC6(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L58
.L68:
leaq .LC6(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L59
.L69:
movl %ebp, %ecx
movl %r14d, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z9next_turnPPiS0_iiPPiS0_ii
jmp .L60
.L70:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z9next_turnPPiS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9next_turnPPiS0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
using namespace std;
void print_matrix(int** world,int m, int n){
for (int i = 0; i < m; i++){
cout<<"| ";
for(int j =0; j < n; j++){
cout<<world[i][j]<<" ";
}
cout<<"|\n";
}
cout<<"\n";
}
int ** create_empty_world(int m, int n){
int **world = 0;
world = new int*[m];
for(int i = 0; i < m; i++){
world[i] = new int[n];
for(int j = 0; j < n; j++){
world[i][j] = 0;
}
}
return world;
}
//just a normal CPU function here. making a world filled with values of 0 or 1
int ** create_world(int m, int n){
int **world = 0;
world = new int*[m];
int value;
srand(time(0));
for (int i = 0; i < m; i ++){
world[i] = new int[n];
for(int j = 0 ; j < n; j ++){
//setting up padding
if(i == 0 || j == 0 || i == m -2 || j == n -2){
world[i][j] = 0;
}else{
//giving the world[m][n] a value between 1 and 0
value = rand() % 2;
world[i][j] = value;
}
}
}
return world;
}
/*
this will take the world, the new world, the hight and width of the worlds
We will then go through every value, sum the value of it's 8 neighbours
and give a result of 1 or 0 for each cell
we will do this for the number of turns that we have specified in the command line arguments.
*/
__global__
void next_turn(int **world, int **new_world, int m, int n ){
//getting the index that we are currently in
int const index_x = threadIdx.x + blockIdx.x * blockDim.x;
if(index_x < m + 1 && index_x != 0){
for(int index_y = 1; index_y < n - 1 ; index_y++){
int living = world[index_x-1][index_y-1] + world[index_x-1][index_y] + world[index_x-1][index_y+1] +
world[index_x][index_y+1] + world[index_x+1][index_y-1] + world[index_x+1][index_y] +
world[index_x+1][index_y+1] + world[index_x][index_y-1];
int current = world[index_x][index_y];
int new_cell = 0;
if((current == 1 && (living == 3 || living == 2)) || current == 0 && living == 3){
new_cell = 1;
}
new_world[index_x][index_y] = new_cell;
}
}
}
//set up numblocks to be a calculation of how many are needed
int const numblocks = 1;
int const blocksize = 1;
int main(int argc, char *argv[]){
//verifying the number of arguments
if(argc <5 || argc> 6){
cout<<"Usage: ./gol [width] [height] [iterations] [number of tests]";
return 1;
}
//gathering data from the arguments
int m = atoi(argv[1]);
m = m + 2;
int n = atoi(argv[2]);
n = n + 2;
int iterations = atoi(argv[3]);
int num_tests = atoi(argv[4]);
int size = sizeof(int) * m * n;
//verifying the arguments are able to be converted to int values
if((m == 0) || (n == 0) || (iterations == 0) || (num_tests == 0)){
cout<< "must enter INT values";
return 0;
}
//create a world and a new world
int **world = create_world(m, n);
int **new_world = create_empty_world(m, n);
print_matrix(world, m, n);
//create a matrix of ints for the device
int **dev_world;
int **dev_new_world;
cudaMalloc((void **)&dev_world, size);
cudaMalloc((void **)&dev_new_world, size);
if(dev_world == NULL) {std::cerr << "not able to alloc memory on device" << std::endl;}
if(dev_new_world == NULL) {std::cerr << "not able to alloc memory on device" << std::endl;}
//copy values from host to device
cudaMemcpy(dev_world, world, size, cudaMemcpyHostToDevice);
//cudaMemcpy(dev_new_world, new_world, size, cudaMemcpyHostToDevice);
//no output yet, don't need to copy it over
//set up timing here, no need to take into account how long it takes to copy stuffs over.
//do next_turn on GPU
//for(int i = 0; i < iterations; i ++){
next_turn<<< numblocks, blocksize >>>(dev_world, dev_new_world, m, n);
//}
//copy result back to host
cudaMemcpy(new_world, dev_new_world, size, cudaMemcpyDeviceToHost);
print_matrix(new_world, m, n);
//free space that we created
for(int i = 0; i < m ; i++){
free(world[i]);
free(new_world[i]);
}
free(world);
free(new_world);
cudaFree(dev_new_world);
cudaFree(dev_world);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
using namespace std;
void print_matrix(int** world,int m, int n){
for (int i = 0; i < m; i++){
cout<<"| ";
for(int j =0; j < n; j++){
cout<<world[i][j]<<" ";
}
cout<<"|\n";
}
cout<<"\n";
}
int ** create_empty_world(int m, int n){
int **world = 0;
world = new int*[m];
for(int i = 0; i < m; i++){
world[i] = new int[n];
for(int j = 0; j < n; j++){
world[i][j] = 0;
}
}
return world;
}
//just a normal CPU function here. making a world filled with values of 0 or 1
int ** create_world(int m, int n){
int **world = 0;
world = new int*[m];
int value;
srand(time(0));
for (int i = 0; i < m; i ++){
world[i] = new int[n];
for(int j = 0 ; j < n; j ++){
//setting up padding
if(i == 0 || j == 0 || i == m -2 || j == n -2){
world[i][j] = 0;
}else{
//giving the world[m][n] a value between 1 and 0
value = rand() % 2;
world[i][j] = value;
}
}
}
return world;
}
/*
this will take the world, the new world, the hight and width of the worlds
We will then go through every value, sum the value of it's 8 neighbours
and give a result of 1 or 0 for each cell
we will do this for the number of turns that we have specified in the command line arguments.
*/
__global__
void next_turn(int **world, int **new_world, int m, int n ){
//getting the index that we are currently in
int const index_x = threadIdx.x + blockIdx.x * blockDim.x;
if(index_x < m + 1 && index_x != 0){
for(int index_y = 1; index_y < n - 1 ; index_y++){
int living = world[index_x-1][index_y-1] + world[index_x-1][index_y] + world[index_x-1][index_y+1] +
world[index_x][index_y+1] + world[index_x+1][index_y-1] + world[index_x+1][index_y] +
world[index_x+1][index_y+1] + world[index_x][index_y-1];
int current = world[index_x][index_y];
int new_cell = 0;
if((current == 1 && (living == 3 || living == 2)) || current == 0 && living == 3){
new_cell = 1;
}
new_world[index_x][index_y] = new_cell;
}
}
}
//set up numblocks to be a calculation of how many are needed
int const numblocks = 1;
int const blocksize = 1;
int main(int argc, char *argv[]){
//verifying the number of arguments
if(argc <5 || argc> 6){
cout<<"Usage: ./gol [width] [height] [iterations] [number of tests]";
return 1;
}
//gathering data from the arguments
int m = atoi(argv[1]);
m = m + 2;
int n = atoi(argv[2]);
n = n + 2;
int iterations = atoi(argv[3]);
int num_tests = atoi(argv[4]);
int size = sizeof(int) * m * n;
//verifying the arguments are able to be converted to int values
if((m == 0) || (n == 0) || (iterations == 0) || (num_tests == 0)){
cout<< "must enter INT values";
return 0;
}
//create a world and a new world
int **world = create_world(m, n);
int **new_world = create_empty_world(m, n);
print_matrix(world, m, n);
//create a matrix of ints for the device
int **dev_world;
int **dev_new_world;
hipMalloc((void **)&dev_world, size);
hipMalloc((void **)&dev_new_world, size);
if(dev_world == NULL) {std::cerr << "not able to alloc memory on device" << std::endl;}
if(dev_new_world == NULL) {std::cerr << "not able to alloc memory on device" << std::endl;}
//copy values from host to device
hipMemcpy(dev_world, world, size, hipMemcpyHostToDevice);
//cudaMemcpy(dev_new_world, new_world, size, cudaMemcpyHostToDevice);
//no output yet, don't need to copy it over
//set up timing here, no need to take into account how long it takes to copy stuffs over.
//do next_turn on GPU
//for(int i = 0; i < iterations; i ++){
next_turn<<< numblocks, blocksize >>>(dev_world, dev_new_world, m, n);
//}
//copy result back to host
hipMemcpy(new_world, dev_new_world, size, hipMemcpyDeviceToHost);
print_matrix(new_world, m, n);
//free space that we created
for(int i = 0; i < m ; i++){
free(world[i]);
free(new_world[i]);
}
free(world);
free(new_world);
hipFree(dev_new_world);
hipFree(dev_world);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
using namespace std;
void print_matrix(int** world,int m, int n){
for (int i = 0; i < m; i++){
cout<<"| ";
for(int j =0; j < n; j++){
cout<<world[i][j]<<" ";
}
cout<<"|\n";
}
cout<<"\n";
}
int ** create_empty_world(int m, int n){
int **world = 0;
world = new int*[m];
for(int i = 0; i < m; i++){
world[i] = new int[n];
for(int j = 0; j < n; j++){
world[i][j] = 0;
}
}
return world;
}
//just a normal CPU function here. making a world filled with values of 0 or 1
int ** create_world(int m, int n){
int **world = 0;
world = new int*[m];
int value;
srand(time(0));
for (int i = 0; i < m; i ++){
world[i] = new int[n];
for(int j = 0 ; j < n; j ++){
//setting up padding
if(i == 0 || j == 0 || i == m -2 || j == n -2){
world[i][j] = 0;
}else{
//giving the world[m][n] a value between 1 and 0
value = rand() % 2;
world[i][j] = value;
}
}
}
return world;
}
/*
this will take the world, the new world, the hight and width of the worlds
We will then go through every value, sum the value of it's 8 neighbours
and give a result of 1 or 0 for each cell
we will do this for the number of turns that we have specified in the command line arguments.
*/
__global__
void next_turn(int **world, int **new_world, int m, int n ){
//getting the index that we are currently in
int const index_x = threadIdx.x + blockIdx.x * blockDim.x;
if(index_x < m + 1 && index_x != 0){
for(int index_y = 1; index_y < n - 1 ; index_y++){
int living = world[index_x-1][index_y-1] + world[index_x-1][index_y] + world[index_x-1][index_y+1] +
world[index_x][index_y+1] + world[index_x+1][index_y-1] + world[index_x+1][index_y] +
world[index_x+1][index_y+1] + world[index_x][index_y-1];
int current = world[index_x][index_y];
int new_cell = 0;
if((current == 1 && (living == 3 || living == 2)) || current == 0 && living == 3){
new_cell = 1;
}
new_world[index_x][index_y] = new_cell;
}
}
}
//set up numblocks to be a calculation of how many are needed
int const numblocks = 1;
int const blocksize = 1;
int main(int argc, char *argv[]){
//verifying the number of arguments
if(argc <5 || argc> 6){
cout<<"Usage: ./gol [width] [height] [iterations] [number of tests]";
return 1;
}
//gathering data from the arguments
int m = atoi(argv[1]);
m = m + 2;
int n = atoi(argv[2]);
n = n + 2;
int iterations = atoi(argv[3]);
int num_tests = atoi(argv[4]);
int size = sizeof(int) * m * n;
//verifying the arguments are able to be converted to int values
if((m == 0) || (n == 0) || (iterations == 0) || (num_tests == 0)){
cout<< "must enter INT values";
return 0;
}
//create a world and a new world
int **world = create_world(m, n);
int **new_world = create_empty_world(m, n);
print_matrix(world, m, n);
//create a matrix of ints for the device
int **dev_world;
int **dev_new_world;
hipMalloc((void **)&dev_world, size);
hipMalloc((void **)&dev_new_world, size);
if(dev_world == NULL) {std::cerr << "not able to alloc memory on device" << std::endl;}
if(dev_new_world == NULL) {std::cerr << "not able to alloc memory on device" << std::endl;}
//copy values from host to device
hipMemcpy(dev_world, world, size, hipMemcpyHostToDevice);
//cudaMemcpy(dev_new_world, new_world, size, cudaMemcpyHostToDevice);
//no output yet, don't need to copy it over
//set up timing here, no need to take into account how long it takes to copy stuffs over.
//do next_turn on GPU
//for(int i = 0; i < iterations; i ++){
next_turn<<< numblocks, blocksize >>>(dev_world, dev_new_world, m, n);
//}
//copy result back to host
hipMemcpy(new_world, dev_new_world, size, hipMemcpyDeviceToHost);
print_matrix(new_world, m, n);
//free space that we created
for(int i = 0; i < m ; i++){
free(world[i]);
free(new_world[i]);
}
free(world);
free(new_world);
hipFree(dev_new_world);
hipFree(dev_world);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9next_turnPPiS0_ii
.globl _Z9next_turnPPiS0_ii
.p2align 8
.type _Z9next_turnPPiS0_ii,@function
_Z9next_turnPPiS0_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_ge_i32_e32 vcc_lo, s2, v1
v_cmp_ne_u32_e64 s2, 0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_cmp_gt_i32 s3, 2
s_cselect_b32 s4, -1, 0
s_and_b32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_7
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s1, s3, -2
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[4:5], v[2:3], off
s_clause 0x1
global_load_b64 v[7:8], v[0:1], off offset:-8
global_load_b128 v[0:3], v[0:1], off
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v5, vcc_lo
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_add_co_u32 v5, vcc_lo, v9, s2
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v10, vcc_lo
s_add_i32 s1, s1, -1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s1, 0
flat_store_b32 v[5:6], v4
s_cbranch_scc0 .LBB0_7
.LBB0_3:
s_waitcnt vmcnt(1)
v_add_co_u32 v4, vcc_lo, v7, s2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v8, vcc_lo
flat_load_b96 v[11:13], v[4:5]
s_waitcnt vmcnt(1)
v_add_co_u32 v4, vcc_lo, v0, s2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v14, vcc_lo, v2, s2
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v3, vcc_lo
flat_load_b96 v[4:6], v[4:5]
flat_load_b96 v[14:16], v[14:15]
s_waitcnt vmcnt(2) lgkmcnt(2)
v_add_nc_u32_e32 v11, v12, v11
s_waitcnt vmcnt(1) lgkmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add3_u32 v6, v11, v13, v6
v_cmp_ne_u32_e32 vcc_lo, 1, v5
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add3_u32 v6, v6, v14, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v4, v6, v16, v4
v_and_b32_e32 v6, -2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 2, v6
s_or_b32 s6, vcc_lo, s0
s_mov_b32 s0, -1
s_and_saveexec_b32 s4, s6
v_cmp_eq_u32_e32 vcc_lo, 0, v5
v_cmp_eq_u32_e64 s0, 3, v4
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_or_not1_b32 s0, s0, exec_lo
s_or_b32 exec_lo, exec_lo, s4
v_mov_b32_e32 v4, s5
s_and_saveexec_b32 s4, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v4, 1
s_branch .LBB0_2
.LBB0_7:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9next_turnPPiS0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9next_turnPPiS0_ii, .Lfunc_end0-_Z9next_turnPPiS0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9next_turnPPiS0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9next_turnPPiS0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
using namespace std;
void print_matrix(int** world,int m, int n){
for (int i = 0; i < m; i++){
cout<<"| ";
for(int j =0; j < n; j++){
cout<<world[i][j]<<" ";
}
cout<<"|\n";
}
cout<<"\n";
}
int ** create_empty_world(int m, int n){
int **world = 0;
world = new int*[m];
for(int i = 0; i < m; i++){
world[i] = new int[n];
for(int j = 0; j < n; j++){
world[i][j] = 0;
}
}
return world;
}
//just a normal CPU function here. making a world filled with values of 0 or 1
int ** create_world(int m, int n){
int **world = 0;
world = new int*[m];
int value;
srand(time(0));
for (int i = 0; i < m; i ++){
world[i] = new int[n];
for(int j = 0 ; j < n; j ++){
//setting up padding
if(i == 0 || j == 0 || i == m -2 || j == n -2){
world[i][j] = 0;
}else{
//giving the world[m][n] a value between 1 and 0
value = rand() % 2;
world[i][j] = value;
}
}
}
return world;
}
/*
this will take the world, the new world, the hight and width of the worlds
We will then go through every value, sum the value of it's 8 neighbours
and give a result of 1 or 0 for each cell
we will do this for the number of turns that we have specified in the command line arguments.
*/
__global__
void next_turn(int **world, int **new_world, int m, int n ){
//getting the index that we are currently in
int const index_x = threadIdx.x + blockIdx.x * blockDim.x;
if(index_x < m + 1 && index_x != 0){
for(int index_y = 1; index_y < n - 1 ; index_y++){
int living = world[index_x-1][index_y-1] + world[index_x-1][index_y] + world[index_x-1][index_y+1] +
world[index_x][index_y+1] + world[index_x+1][index_y-1] + world[index_x+1][index_y] +
world[index_x+1][index_y+1] + world[index_x][index_y-1];
int current = world[index_x][index_y];
int new_cell = 0;
if((current == 1 && (living == 3 || living == 2)) || current == 0 && living == 3){
new_cell = 1;
}
new_world[index_x][index_y] = new_cell;
}
}
}
//set up numblocks to be a calculation of how many are needed
int const numblocks = 1;
int const blocksize = 1;
int main(int argc, char *argv[]){
//verifying the number of arguments
if(argc <5 || argc> 6){
cout<<"Usage: ./gol [width] [height] [iterations] [number of tests]";
return 1;
}
//gathering data from the arguments
int m = atoi(argv[1]);
m = m + 2;
int n = atoi(argv[2]);
n = n + 2;
int iterations = atoi(argv[3]);
int num_tests = atoi(argv[4]);
int size = sizeof(int) * m * n;
//verifying the arguments are able to be converted to int values
if((m == 0) || (n == 0) || (iterations == 0) || (num_tests == 0)){
cout<< "must enter INT values";
return 0;
}
//create a world and a new world
int **world = create_world(m, n);
int **new_world = create_empty_world(m, n);
print_matrix(world, m, n);
//create a matrix of ints for the device
int **dev_world;
int **dev_new_world;
hipMalloc((void **)&dev_world, size);
hipMalloc((void **)&dev_new_world, size);
if(dev_world == NULL) {std::cerr << "not able to alloc memory on device" << std::endl;}
if(dev_new_world == NULL) {std::cerr << "not able to alloc memory on device" << std::endl;}
//copy values from host to device
hipMemcpy(dev_world, world, size, hipMemcpyHostToDevice);
//cudaMemcpy(dev_new_world, new_world, size, cudaMemcpyHostToDevice);
//no output yet, don't need to copy it over
//set up timing here, no need to take into account how long it takes to copy stuffs over.
//do next_turn on GPU
//for(int i = 0; i < iterations; i ++){
next_turn<<< numblocks, blocksize >>>(dev_world, dev_new_world, m, n);
//}
//copy result back to host
hipMemcpy(new_world, dev_new_world, size, hipMemcpyDeviceToHost);
print_matrix(new_world, m, n);
//free space that we created
for(int i = 0; i < m ; i++){
free(world[i]);
free(new_world[i]);
}
free(world);
free(new_world);
hipFree(dev_new_world);
hipFree(dev_world);
} | .text
.file "game_of_life_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z12print_matrixPPiii # -- Begin function _Z12print_matrixPPiii
.p2align 4, 0x90
.type _Z12print_matrixPPiii,@function
_Z12print_matrixPPiii: # @_Z12print_matrixPPiii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_7
# %bb.1: # %.lr.ph12
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rdi, %r14
movl %esi, %r15d
movl %edx, %r12d
xorl %r13d, %r13d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r13
cmpq %r15, %r13
je .LBB0_6
.LBB0_2: # =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebx, %ebx
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r14,%r13,8), %rax
movl (%rax,%rbp,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbp
cmpq %rbp, %r12
jne .LBB0_4
jmp .LBB0_5
.LBB0_6:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_7: # %._crit_edge13
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $1, %edx
jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.Lfunc_end0:
.size _Z12print_matrixPPiii, .Lfunc_end0-_Z12print_matrixPPiii
.cfi_endproc
# -- End function
.globl _Z18create_empty_worldii # -- Begin function _Z18create_empty_worldii
.p2align 4, 0x90
.type _Z18create_empty_worldii,@function
_Z18create_empty_worldii: # @_Z18create_empty_worldii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movslq %edi, %r15
leaq (,%r15,8), %rdi
testl %r15d, %r15d
movq $-1, %r12
cmovsq %r12, %rdi
callq _Znam
movq %rax, %r14
testl %r15d, %r15d
jle .LBB1_5
# %bb.1: # %.lr.ph17
movslq %ebx, %rax
leaq (,%rax,4), %r15
testl %eax, %eax
cmovsq %r12, %r15
movl %eax, %r12d
shlq $2, %r12
movl %ebp, %r13d
xorl %ebp, %ebp
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rbp
cmpq %rbp, %r13
je .LBB1_5
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
callq _Znam
movq %rax, (%r14,%rbp,8)
testl %ebx, %ebx
jle .LBB1_4
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
movq %rax, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
jmp .LBB1_4
.LBB1_5: # %._crit_edge18
movq %r14, %rax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18create_empty_worldii, .Lfunc_end1-_Z18create_empty_worldii
.cfi_endproc
# -- End function
.globl _Z12create_worldii # -- Begin function _Z12create_worldii
.p2align 4, 0x90
.type _Z12create_worldii,@function
_Z12create_worldii: # @_Z12create_worldii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, 12(%rsp) # 4-byte Spill
movl %edi, %r12d
movslq %edi, %r14
leaq (,%r14,8), %rdi
testl %r14d, %r14d
movq $-1, %rbx
cmovsq %rbx, %rdi
callq _Znam
movq %rax, 16(%rsp) # 8-byte Spill
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r14d, %r14d
jle .LBB2_11
# %bb.1: # %.lr.ph34
movslq 12(%rsp), %rax # 4-byte Folded Reload
leaq (,%rax,4), %rcx
testl %eax, %eax
cmovsq %rbx, %rcx
movq %rcx, 32(%rsp) # 8-byte Spill
leal -2(%r12), %r13d
leal -2(%rax), %ebp
movl %r12d, %ecx
movq %rcx, 24(%rsp) # 8-byte Spill
movl %eax, %r14d
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_10: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r15
cmpq 24(%rsp), %r15 # 8-byte Folded Reload
je .LBB2_11
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
movq 32(%rsp), %rdi # 8-byte Reload
callq _Znam
movq %rax, %r12
movq 16(%rsp), %rax # 8-byte Reload
movq %r12, (%rax,%r15,8)
cmpl $0, 12(%rsp) # 4-byte Folded Reload
jle .LBB2_10
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
xorl %ebx, %ebx
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_4 Depth=2
movl %eax, (%r12,%rbx,4)
incq %rbx
cmpq %rbx, %r14
je .LBB2_10
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
xorl %eax, %eax
testq %r15, %r15
je .LBB2_9
# %bb.5: # in Loop: Header=BB2_4 Depth=2
testq %rbx, %rbx
je .LBB2_9
# %bb.6: # in Loop: Header=BB2_4 Depth=2
cmpq %r13, %r15
je .LBB2_9
# %bb.7: # in Loop: Header=BB2_4 Depth=2
cmpq %rbx, %rbp
je .LBB2_9
# %bb.8: # in Loop: Header=BB2_4 Depth=2
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
jmp .LBB2_9
.LBB2_11: # %._crit_edge35
movq 16(%rsp), %rax # 8-byte Reload
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12create_worldii, .Lfunc_end2-_Z12create_worldii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__next_turnPPiS0_ii # -- Begin function _Z24__device_stub__next_turnPPiS0_ii
.p2align 4, 0x90
.type _Z24__device_stub__next_turnPPiS0_ii,@function
_Z24__device_stub__next_turnPPiS0_ii: # @_Z24__device_stub__next_turnPPiS0_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9next_turnPPiS0_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z24__device_stub__next_turnPPiS0_ii, .Lfunc_end3-_Z24__device_stub__next_turnPPiS0_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
addl $-7, %edi
cmpl $-3, %edi
ja .LBB4_2
# %bb.1:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $60, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $1, %r14d
jmp .LBB4_30
.LBB4_2:
movq 8(%rsi), %rdi
xorl %r14d, %r14d
movq %rsi, %r15
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 32(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %ebp, %r15d
addl $2, %r15d
je .LBB4_6
# %bb.3:
movl %r13d, %esi
addl $2, %esi
je .LBB4_6
# %bb.4:
movl %ebx, %ecx
testq %rcx, %rcx
je .LBB4_6
# %bb.5:
movl %eax, %eax
testq %rax, %rax
je .LBB4_6
# %bb.7:
movl %r15d, %eax
imull %esi, %eax
shll $2, %eax
movl %eax, 36(%rsp) # 4-byte Spill
movl %r15d, %edi
movl %esi, 8(%rsp) # 4-byte Spill
callq _Z12create_worldii
movq %rax, 56(%rsp) # 8-byte Spill
movl %r15d, 12(%rsp) # 4-byte Spill
movslq %r15d, %rdi
shlq $3, %rdi
cmpl $-2, %ebp
movq $-1, %r14
cmovlq %r14, %rdi
callq _Znam
movq %rax, %r12
movq %rbp, 48(%rsp) # 8-byte Spill
cmpl $-1, %ebp
jl .LBB4_12
# %bb.8: # %.lr.ph17.i
movl 8(%rsp), %eax # 4-byte Reload
movslq %eax, %rbx
shlq $2, %rbx
cmpl $-2, %r13d
cmovlq %r14, %rbx
movl %eax, %r15d
shlq $2, %r15
movl 12(%rsp), %ebp # 4-byte Reload
xorl %r14d, %r14d
jmp .LBB4_9
.p2align 4, 0x90
.LBB4_11: # %._crit_edge.i
# in Loop: Header=BB4_9 Depth=1
incq %r14
cmpq %r14, %rbp
je .LBB4_12
.LBB4_9: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
callq _Znam
movq %rax, (%r12,%r14,8)
cmpl $-1, %r13d
jl .LBB4_11
# %bb.10: # %.lr.ph.preheader.i
# in Loop: Header=BB4_9 Depth=1
movq %rax, %rdi
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
jmp .LBB4_11
.LBB4_6:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_30
.LBB4_12: # %_Z18create_empty_worldii.exit
movq 56(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl 12(%rsp), %ebp # 4-byte Reload
movl %ebp, %esi
movl 8(%rsp), %edx # 4-byte Reload
callq _Z12print_matrixPPiii
movslq 36(%rsp), %r13 # 4-byte Folded Reload
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
cmpq $0, 24(%rsp)
jne .LBB4_18
# %bb.13:
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_31
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB4_16
# %bb.15:
movzbl 67(%rbx), %eax
jmp .LBB4_17
.LBB4_16:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_18:
cmpq $0, 16(%rsp)
movq 48(%rsp), %r14 # 8-byte Reload
jne .LBB4_24
# %bb.19:
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_31
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i54
cmpb $0, 56(%rbx)
je .LBB4_22
# %bb.21:
movzbl 67(%rbx), %eax
jmp .LBB4_23
.LBB4_22:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit57
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_24:
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_26
# %bb.25:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl %ebp, 44(%rsp)
movl 8(%rsp), %eax # 4-byte Reload
movl %eax, 40(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9next_turnPPiS0_ii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_26:
movq 16(%rsp), %rsi
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r12, %rdi
movl %ebp, %esi
movl 8(%rsp), %edx # 4-byte Reload
callq _Z12print_matrixPPiii
cmpl $-1, %r14d
jl .LBB4_29
# %bb.27: # %.lr.ph.preheader
cmpl $2, %ebp
movl $1, %ebx
cmovgel %ebp, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_28: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%r15,%r14,8), %rdi
callq free
movq (%r12,%r14,8), %rdi
callq free
incq %r14
cmpq %r14, %rbx
jne .LBB4_28
.LBB4_29: # %._crit_edge
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %r14d, %r14d
.LBB4_30:
movl %r14d, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_31:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9next_turnPPiS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "| "
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "|\n"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n"
.size .L.str.3, 2
.type _Z9next_turnPPiS0_ii,@object # @_Z9next_turnPPiS0_ii
.section .rodata,"a",@progbits
.globl _Z9next_turnPPiS0_ii
.p2align 3, 0x0
_Z9next_turnPPiS0_ii:
.quad _Z24__device_stub__next_turnPPiS0_ii
.size _Z9next_turnPPiS0_ii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Usage: ./gol [width] [height] [iterations] [number of tests]"
.size .L.str.4, 61
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "must enter INT values"
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "not able to alloc memory on device"
.size .L.str.6, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9next_turnPPiS0_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__next_turnPPiS0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z9next_turnPPiS0_ii
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9next_turnPPiS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff027624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GT.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fc80003f04270 */
/*0060*/ ISETP.EQ.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fc80000702670 */
/*0070*/ ISETP.LT.OR P0, PT, R2, 0x3, P0 ; /* 0x000000030200780c */
/* 0x000fda0000701670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ ISETP.NE.AND P0, PT, R2.reuse, 0x3, PT ; /* 0x000000030200780c */
/* 0x040fe20003f05270 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R0, R2, -0x2, RZ ; /* 0xfffffffe02007810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*00d0*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fe200078e0205 */
/*00e0*/ LOP3.LUT R6, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100067812 */
/* 0x000fc600078ec0ff */
/*00f0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0100*/ ISETP.NE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f45270 */
/*0110*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe400078e0205 */
/*0120*/ @!P0 BRA 0x5f0 ; /* 0x000004c000008947 */
/* 0x000ff40003800000 */
/*0130*/ IADD3 R6, -R6, c[0x0][0x174], RZ ; /* 0x00005d0006067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0150*/ UMOV UR5, 0x8 ; /* 0x0000000800057882 */
/* 0x000fe40000000000 */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0170*/ LDG.E.64 R12, [R2.64+-0x8] ; /* 0xfffff806020c7981 */
/* 0x000ea8000c1e1b00 */
/*0180*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x001ee8000c1e1b00 */
/*0190*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000806020a7981 */
/* 0x000f22000c1e1b00 */
/*01a0*/ IADD3 R12, P0, R12, UR5, RZ ; /* 0x000000050c0c7c10 */
/* 0x004fc4000ff1e0ff */
/*01b0*/ IADD3 R8, P1, R8, UR5, RZ ; /* 0x0000000508087c10 */
/* 0x008fe4000ff3e0ff */
/*01c0*/ IADD3.X R13, R13, UR4, RZ, P0, !PT ; /* 0x000000040d0d7c10 */
/* 0x000fe400087fe4ff */
/*01d0*/ IADD3 R14, P3, R10, UR5, RZ ; /* 0x000000050a0e7c10 */
/* 0x010fe4000ff7e0ff */
/*01e0*/ IADD3.X R9, R9, UR4, RZ, P1, !PT ; /* 0x0000000409097c10 */
/* 0x000fe20008ffe4ff */
/*01f0*/ LDG.E R7, [R12.64+-0x4] ; /* 0xfffffc060c077981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3.X R15, R11, UR4, RZ, P3, !PT ; /* 0x000000040b0f7c10 */
/* 0x000fc60009ffe4ff */
/*0210*/ LDG.E R16, [R12.64+-0x8] ; /* 0xfffff8060c107981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R17, [R12.64] ; /* 0x000000060c117981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R18, [R8.64] ; /* 0x0000000608127981 */
/* 0x000ee8000c1e1900 */
/*0240*/ LDG.E R19, [R14.64+-0x8] ; /* 0xfffff8060e137981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R20, [R14.64+-0x4] ; /* 0xfffffc060e147981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R21, [R14.64] ; /* 0x000000060e157981 */
/* 0x000f28000c1e1900 */
/*0270*/ LDG.E R22, [R8.64+-0x8] ; /* 0xfffff80608167981 */
/* 0x000f68000c1e1900 */
/*0280*/ LDG.E R23, [R8.64+-0x4] ; /* 0xfffffc0608177981 */
/* 0x000f68000c1e1900 */
/*0290*/ LDG.E.64 R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000f62000c1e1b00 */
/*02a0*/ IADD3 R7, R17, R7, R16 ; /* 0x0000000711077210 */
/* 0x004fc80007ffe010 */
/*02b0*/ IADD3 R7, R19, R7, R18 ; /* 0x0000000713077210 */
/* 0x008fc80007ffe012 */
/*02c0*/ IADD3 R7, R21, R7, R20 ; /* 0x0000000715077210 */
/* 0x010fca0007ffe014 */
/*02d0*/ IMAD.IADD R7, R7, 0x1, R22 ; /* 0x0000000107077824 */
/* 0x020fca00078e0216 */
/*02e0*/ LOP3.LUT R12, R7.reuse, 0x1, RZ, 0xfc, !PT ; /* 0x00000001070c7812 */
/* 0x040fe400078efcff */
/*02f0*/ ISETP.NE.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe40003f05270 */
/*0300*/ ISETP.NE.AND P1, PT, R12, 0x3, PT ; /* 0x000000030c00780c */
/* 0x000fe40003f25270 */
/*0310*/ ISETP.EQ.AND P0, PT, R23.reuse, RZ, !P0 ; /* 0x000000ff1700720c */
/* 0x040fe40004702270 */
/*0320*/ ISETP.EQ.AND P1, PT, R23, 0x1, !P1 ; /* 0x000000011700780c */
/* 0x000fe40004f22270 */
/*0330*/ IADD3 R16, P3, R10, UR5, RZ ; /* 0x000000050a107c10 */
/* 0x000fc4000ff7e0ff */
/*0340*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0350*/ IADD3.X R17, R11, UR4, RZ, P3, !PT ; /* 0x000000040b117c10 */
/* 0x000fe40009ffe4ff */
/*0360*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fca0004000000 */
/*0370*/ STG.E [R16.64+-0x4], R7 ; /* 0xfffffc0710007986 */
/* 0x0001e8000c101906 */
/*0380*/ LDG.E.64 R8, [R2.64+-0x8] ; /* 0xfffff80602087981 */
/* 0x000ea8000c1e1b00 */
/*0390*/ LDG.E.64 R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ee8000c1e1b00 */
/*03a0*/ LDG.E.64 R14, [R2.64+0x8] ; /* 0x00000806020e7981 */
/* 0x000f22000c1e1b00 */
/*03b0*/ IADD3 R12, P0, R8, UR5, RZ ; /* 0x00000005080c7c10 */
/* 0x004fc4000ff1e0ff */
/*03c0*/ IADD3 R8, P1, R10, UR5, RZ ; /* 0x000000050a087c10 */
/* 0x008fe4000ff3e0ff */
/*03d0*/ IADD3.X R13, R9, UR4, RZ, P0, !PT ; /* 0x00000004090d7c10 */
/* 0x000fe400087fe4ff */
/*03e0*/ IADD3 R14, P3, R14, UR5, RZ ; /* 0x000000050e0e7c10 */
/* 0x010fe4000ff7e0ff */
/*03f0*/ IADD3.X R9, R11, UR4, RZ, P1, !PT ; /* 0x000000040b097c10 */
/* 0x000fe20008ffe4ff */
/*0400*/ LDG.E R18, [R12.64] ; /* 0x000000060c127981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IADD3.X R15, R15, UR4, RZ, P3, !PT ; /* 0x000000040f0f7c10 */
/* 0x000fc60009ffe4ff */
/*0420*/ LDG.E R7, [R12.64+-0x4] ; /* 0xfffffc060c077981 */
/* 0x001ea8000c1e1900 */
/*0430*/ LDG.E R16, [R12.64+0x4] ; /* 0x000004060c107981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R20, [R8.64+0x4] ; /* 0x0000040608147981 */
/* 0x000ee8000c1e1900 */
/*0450*/ LDG.E R17, [R14.64+-0x4] ; /* 0xfffffc060e117981 */
/* 0x000ee8000c1e1900 */
/*0460*/ LDG.E R22, [R14.64] ; /* 0x000000060e167981 */
/* 0x000f28000c1e1900 */
/*0470*/ LDG.E R19, [R14.64+0x4] ; /* 0x000004060e137981 */
/* 0x000f28000c1e1900 */
/*0480*/ LDG.E R24, [R8.64+-0x4] ; /* 0xfffffc0608187981 */
/* 0x000f68000c1e1900 */
/*0490*/ LDG.E R21, [R8.64] ; /* 0x0000000608157981 */
/* 0x000f68000c1e1900 */
/*04a0*/ LDG.E.64 R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000f62000c1e1b00 */
/*04b0*/ IADD3 R6, R6, -0x2, RZ ; /* 0xfffffffe06067810 */
/* 0x000fc40007ffe0ff */
/*04c0*/ IADD3 R0, R0, 0x2, RZ ; /* 0x0000000200007810 */
/* 0x000fe40007ffe0ff */
/*04d0*/ IADD3 R7, R16, R18, R7 ; /* 0x0000001210077210 */
/* 0x004fc80007ffe007 */
/*04e0*/ IADD3 R7, R17, R7, R20 ; /* 0x0000000711077210 */
/* 0x008fc80007ffe014 */
/*04f0*/ IADD3 R7, R19, R7, R22 ; /* 0x0000000713077210 */
/* 0x010fca0007ffe016 */
/*0500*/ IMAD.IADD R7, R7, 0x1, R24 ; /* 0x0000000107077824 */
/* 0x020fca00078e0218 */
/*0510*/ LOP3.LUT R12, R7.reuse, 0x1, RZ, 0xfc, !PT ; /* 0x00000001070c7812 */
/* 0x040fe400078efcff */
/*0520*/ ISETP.NE.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe40003f05270 */
/*0530*/ ISETP.NE.AND P1, PT, R12, 0x3, PT ; /* 0x000000030c00780c */
/* 0x000fe40003f25270 */
/*0540*/ ISETP.EQ.AND P0, PT, R21.reuse, RZ, !P0 ; /* 0x000000ff1500720c */
/* 0x040fe40004702270 */
/*0550*/ ISETP.EQ.AND P1, PT, R21, 0x1, !P1 ; /* 0x000000011500780c */
/* 0x000fc80004f22270 */
/*0560*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80000703570 */
/*0570*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fe40004000000 */
/*0580*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fe40003f05270 */
/*0590*/ IADD3 R8, P3, R10, UR5, RZ ; /* 0x000000050a087c10 */
/* 0x000fe2000ff7e0ff */
/*05a0*/ UIADD3 UR5, UP0, UR5, 0x8, URZ ; /* 0x0000000805057890 */
/* 0x000fc6000ff1e03f */
/*05b0*/ IADD3.X R9, R11, UR4, RZ, P3, !PT ; /* 0x000000040b097c10 */
/* 0x000fe20009ffe4ff */
/*05c0*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fc800087fe43f */
/*05d0*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x0001e4000c101906 */
/*05e0*/ @P0 BRA 0x170 ; /* 0xfffffb8000000947 */
/* 0x000fea000383ffff */
/*05f0*/ @!P2 EXIT ; /* 0x000000000000a94d */
/* 0x000fea0003800000 */
/*0600*/ LDG.E.64 R6, [R2.64+-0x8] ; /* 0xfffff80602067981 */
/* 0x001ea8000c1e1b00 */
/*0610*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x000ee8000c1e1b00 */
/*0620*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000806020a7981 */
/* 0x000f28000c1e1b00 */
/*0630*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000f62000c1e1b00 */
/*0640*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x004fc800078e0206 */
/*0650*/ IMAD.WIDE R8, R0.reuse, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x048fe200078e0208 */
/*0660*/ LDG.E R12, [R6.64] ; /* 0x00000006060c7981 */
/* 0x000ea6000c1e1900 */
/*0670*/ IMAD.WIDE R10, R0.reuse, 0x4, R10 ; /* 0x00000004000a7825 */
/* 0x050fe200078e020a */
/*0680*/ LDG.E R13, [R6.64+-0x4] ; /* 0xfffffc06060d7981 */
/* 0x000ea8000c1e1900 */
/*0690*/ LDG.E R14, [R6.64+0x4] ; /* 0x00000406060e7981 */
/* 0x000ea8000c1e1900 */
/*06a0*/ LDG.E R15, [R8.64+0x4] ; /* 0x00000406080f7981 */
/* 0x000ee8000c1e1900 */
/*06b0*/ LDG.E R16, [R10.64+-0x4] ; /* 0xfffffc060a107981 */
/* 0x000ee8000c1e1900 */
/*06c0*/ LDG.E R17, [R10.64] ; /* 0x000000060a117981 */
/* 0x000f28000c1e1900 */
/*06d0*/ LDG.E R18, [R10.64+0x4] ; /* 0x000004060a127981 */
/* 0x000f28000c1e1900 */
/*06e0*/ LDG.E R3, [R8.64+-0x4] ; /* 0xfffffc0608037981 */
/* 0x000f28000c1e1900 */
/*06f0*/ LDG.E R2, [R8.64] ; /* 0x0000000608027981 */
/* 0x000f22000c1e1900 */
/*0700*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x020fe200078e0204 */
/*0710*/ IADD3 R12, R14, R12, R13 ; /* 0x0000000c0e0c7210 */
/* 0x004fc80007ffe00d */
/*0720*/ IADD3 R12, R16, R12, R15 ; /* 0x0000000c100c7210 */
/* 0x008fc80007ffe00f */
/*0730*/ IADD3 R12, R18, R12, R17 ; /* 0x0000000c120c7210 */
/* 0x010fca0007ffe011 */
/*0740*/ IMAD.IADD R3, R12, 0x1, R3 ; /* 0x000000010c037824 */
/* 0x000fca00078e0203 */
/*0750*/ LOP3.LUT R6, R3.reuse, 0x1, RZ, 0xfc, !PT ; /* 0x0000000103067812 */
/* 0x040fe400078efcff */
/*0760*/ ISETP.NE.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f25270 */
/*0770*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f05270 */
/*0780*/ ISETP.EQ.AND P1, PT, R2.reuse, RZ, !P1 ; /* 0x000000ff0200720c */
/* 0x040fe40004f22270 */
/*0790*/ ISETP.EQ.AND P0, PT, R2, 0x1, !P0 ; /* 0x000000010200780c */
/* 0x000fc80004702270 */
/*07a0*/ PLOP3.LUT P0, PT, P1, P0, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80000f01570 */
/*07b0*/ SEL R3, RZ, 0x1, !P0 ; /* 0x00000001ff037807 */
/* 0x000fca0004000000 */
/*07c0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101906 */
/*07d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07e0*/ BRA 0x7e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9next_turnPPiS0_ii
.globl _Z9next_turnPPiS0_ii
.p2align 8
.type _Z9next_turnPPiS0_ii,@function
_Z9next_turnPPiS0_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_ge_i32_e32 vcc_lo, s2, v1
v_cmp_ne_u32_e64 s2, 0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_cmp_gt_i32 s3, 2
s_cselect_b32 s4, -1, 0
s_and_b32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_7
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s1, s3, -2
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[4:5], v[2:3], off
s_clause 0x1
global_load_b64 v[7:8], v[0:1], off offset:-8
global_load_b128 v[0:3], v[0:1], off
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v5, vcc_lo
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_add_co_u32 v5, vcc_lo, v9, s2
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v10, vcc_lo
s_add_i32 s1, s1, -1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s1, 0
flat_store_b32 v[5:6], v4
s_cbranch_scc0 .LBB0_7
.LBB0_3:
s_waitcnt vmcnt(1)
v_add_co_u32 v4, vcc_lo, v7, s2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v8, vcc_lo
flat_load_b96 v[11:13], v[4:5]
s_waitcnt vmcnt(1)
v_add_co_u32 v4, vcc_lo, v0, s2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v14, vcc_lo, v2, s2
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v3, vcc_lo
flat_load_b96 v[4:6], v[4:5]
flat_load_b96 v[14:16], v[14:15]
s_waitcnt vmcnt(2) lgkmcnt(2)
v_add_nc_u32_e32 v11, v12, v11
s_waitcnt vmcnt(1) lgkmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add3_u32 v6, v11, v13, v6
v_cmp_ne_u32_e32 vcc_lo, 1, v5
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add3_u32 v6, v6, v14, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v4, v6, v16, v4
v_and_b32_e32 v6, -2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 2, v6
s_or_b32 s6, vcc_lo, s0
s_mov_b32 s0, -1
s_and_saveexec_b32 s4, s6
v_cmp_eq_u32_e32 vcc_lo, 0, v5
v_cmp_eq_u32_e64 s0, 3, v4
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_or_not1_b32 s0, s0, exec_lo
s_or_b32 exec_lo, exec_lo, s4
v_mov_b32_e32 v4, s5
s_and_saveexec_b32 s4, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v4, 1
s_branch .LBB0_2
.LBB0_7:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9next_turnPPiS0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9next_turnPPiS0_ii, .Lfunc_end0-_Z9next_turnPPiS0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9next_turnPPiS0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9next_turnPPiS0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e68b1_00000000-6_game_of_life_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "| "
.LC1:
.string " "
.LC2:
.string "|\n"
.LC3:
.string "\n"
.text
.globl _Z12print_matrixPPiii
.type _Z12print_matrixPPiii, @function
_Z12print_matrixPPiii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
testl %esi, %esi
jle .L4
movl %edx, %r15d
movq %rdi, %rbp
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %rax
movq %rax, 8(%rsp)
movslq %edx, %r13
salq $2, %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %r14
.L7:
movl $2, %edx
leaq .LC0(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
testl %r15d, %r15d
jle .L5
movl $0, %ebx
.L6:
movq 0(%rbp), %rax
movl (%rax,%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L6
.L5:
movl $2, %edx
leaq .LC2(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, %rbp
cmpq %rbp, 8(%rsp)
jne .L7
.L4:
movl $1, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z12print_matrixPPiii, .-_Z12print_matrixPPiii
.globl _Z18create_empty_worldii
.type _Z18create_empty_worldii, @function
_Z18create_empty_worldii:
.LFB3670:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movslq %edi, %rax
movq %rax, %rcx
shrq $60, %rcx
jne .L12
movl %edi, %ebx
movl %esi, %r13d
leaq 0(,%rax,8), %r12
movq %r12, %rdi
call _Znam@PLT
movq %rax, %r14
testl %ebx, %ebx
jle .L11
movslq %r13d, %rbp
movabsq $2305843009213693950, %rax
cmpq %rbp, %rax
jb .L25
salq $2, %rbp
movq %r14, %rbx
addq %r14, %r12
.L19:
movq %rbp, %rdi
call _Znam@PLT
movq %rax, (%rbx)
movq %rax, %rdx
addq %rbp, %rax
testl %r13d, %r13d
jle .L17
.L18:
movl $0, (%rdx)
addq $4, %rdx
cmpq %rax, %rdx
jne .L18
.L17:
addq $8, %rbx
cmpq %r12, %rbx
jne .L19
.L11:
movq %r14, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.L25:
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE3670:
.size _Z18create_empty_worldii, .-_Z18create_empty_worldii
.globl _Z12create_worldii
.type _Z12create_worldii, @function
_Z12create_worldii:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %edi, 12(%rsp)
movslq %edi, %rax
movq %rax, %rdi
shrq $60, %rdi
jne .L27
movl %esi, %r15d
leaq 0(,%rax,8), %rdi
call _Znam@PLT
movq %rax, 24(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebx, %ebx
jle .L26
movslq %r15d, %r13
movabsq $2305843009213693950, %rax
cmpq %r13, %rax
jb .L43
leaq 0(,%r13,4), %rax
movq %rax, 16(%rsp)
movq 24(%rsp), %rax
movq %rax, (%rsp)
movl $0, %ebp
movl 12(%rsp), %eax
leal -2(%rax), %r14d
jmp .L36
.L27:
call __cxa_throw_bad_array_new_length@PLT
.L43:
call __cxa_throw_bad_array_new_length@PLT
.L33:
movq (%r12), %rax
movl $0, (%rax,%rbx,4)
.L35:
addq $1, %rbx
cmpq %r13, %rbx
je .L32
.L31:
testl %ebp, %ebp
je .L33
testl %ebx, %ebx
je .L33
cmpl %ebp, %r14d
je .L33
leal -2(%r15), %edx
cmpl %ebx, %edx
je .L33
call rand@PLT
movq (%r12), %rcx
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, (%rcx,%rbx,4)
jmp .L35
.L32:
addl $1, %ebp
addq $8, (%rsp)
cmpl %ebp, 12(%rsp)
je .L26
.L36:
movq 16(%rsp), %rdi
call _Znam@PLT
movq (%rsp), %rsi
movq %rsi, %r12
movq %rax, (%rsi)
movl $0, %ebx
testl %r15d, %r15d
jg .L31
jmp .L32
.L26:
movq 24(%rsp), %rax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z12create_worldii, .-_Z12create_worldii
.globl _Z34__device_stub__Z9next_turnPPiS0_iiPPiS0_ii
.type _Z34__device_stub__Z9next_turnPPiS0_iiPPiS0_ii, @function
_Z34__device_stub__Z9next_turnPPiS0_iiPPiS0_ii:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9next_turnPPiS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z34__device_stub__Z9next_turnPPiS0_iiPPiS0_ii, .-_Z34__device_stub__Z9next_turnPPiS0_iiPPiS0_ii
.globl _Z9next_turnPPiS0_ii
.type _Z9next_turnPPiS0_ii, @function
_Z9next_turnPPiS0_ii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9next_turnPPiS0_iiPPiS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z9next_turnPPiS0_ii, .-_Z9next_turnPPiS0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Usage: ./gol [width] [height] [iterations] [number of tests]"
.section .rodata.str1.1
.LC5:
.string "must enter INT values"
.section .rodata.str1.8
.align 8
.LC6:
.string "not able to alloc memory on device"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
subl $5, %edi
cmpl $1, %edi
ja .L66
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
leal 2(%rax), %r14d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
leal 2(%rax), %ebp
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
testl %r14d, %r14d
je .L55
testl %ebp, %ebp
je .L55
testl %r12d, %r12d
je .L55
testl %eax, %eax
je .L55
movl %ebp, %esi
movl %r14d, %edi
call _Z12create_worldii
movq %rax, %r13
movl %ebp, %esi
movl %r14d, %edi
call _Z18create_empty_worldii
movq %rax, %r12
movl %ebp, %edx
movl %r14d, %esi
movq %r13, %rdi
call _Z12print_matrixPPiii
movl %r14d, %ebx
imull %ebp, %ebx
sall $2, %ebx
movslq %ebx, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
cmpq $0, (%rsp)
je .L67
.L58:
cmpq $0, 8(%rsp)
je .L68
.L59:
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L60:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %ebp, %edx
movl %r14d, %esi
movq %r12, %rdi
call _Z12print_matrixPPiii
testl %r14d, %r14d
jle .L61
leal 1(%r15), %ebp
movl $0, %ebx
.L62:
movq 0(%r13,%rbx,8), %rdi
call free@PLT
movq (%r12,%rbx,8), %rdi
call free@PLT
movq %rbx, %rax
addq $1, %rbx
cmpq %rbp, %rax
jne .L62
.L61:
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L52
.L66:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %eax
.L52:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L70
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %eax
jmp .L52
.L67:
leaq .LC6(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L58
.L68:
leaq .LC6(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L59
.L69:
movl %ebp, %ecx
movl %r14d, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z9next_turnPPiS0_iiPPiS0_ii
jmp .L60
.L70:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z9next_turnPPiS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9next_turnPPiS0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "game_of_life_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z12print_matrixPPiii # -- Begin function _Z12print_matrixPPiii
.p2align 4, 0x90
.type _Z12print_matrixPPiii,@function
_Z12print_matrixPPiii: # @_Z12print_matrixPPiii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_7
# %bb.1: # %.lr.ph12
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rdi, %r14
movl %esi, %r15d
movl %edx, %r12d
xorl %r13d, %r13d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r13
cmpq %r15, %r13
je .LBB0_6
.LBB0_2: # =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebx, %ebx
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r14,%r13,8), %rax
movl (%rax,%rbp,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbp
cmpq %rbp, %r12
jne .LBB0_4
jmp .LBB0_5
.LBB0_6:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_7: # %._crit_edge13
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $1, %edx
jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.Lfunc_end0:
.size _Z12print_matrixPPiii, .Lfunc_end0-_Z12print_matrixPPiii
.cfi_endproc
# -- End function
.globl _Z18create_empty_worldii # -- Begin function _Z18create_empty_worldii
.p2align 4, 0x90
.type _Z18create_empty_worldii,@function
_Z18create_empty_worldii: # @_Z18create_empty_worldii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movslq %edi, %r15
leaq (,%r15,8), %rdi
testl %r15d, %r15d
movq $-1, %r12
cmovsq %r12, %rdi
callq _Znam
movq %rax, %r14
testl %r15d, %r15d
jle .LBB1_5
# %bb.1: # %.lr.ph17
movslq %ebx, %rax
leaq (,%rax,4), %r15
testl %eax, %eax
cmovsq %r12, %r15
movl %eax, %r12d
shlq $2, %r12
movl %ebp, %r13d
xorl %ebp, %ebp
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rbp
cmpq %rbp, %r13
je .LBB1_5
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
callq _Znam
movq %rax, (%r14,%rbp,8)
testl %ebx, %ebx
jle .LBB1_4
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
movq %rax, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
jmp .LBB1_4
.LBB1_5: # %._crit_edge18
movq %r14, %rax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18create_empty_worldii, .Lfunc_end1-_Z18create_empty_worldii
.cfi_endproc
# -- End function
.globl _Z12create_worldii # -- Begin function _Z12create_worldii
.p2align 4, 0x90
.type _Z12create_worldii,@function
_Z12create_worldii: # @_Z12create_worldii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, 12(%rsp) # 4-byte Spill
movl %edi, %r12d
movslq %edi, %r14
leaq (,%r14,8), %rdi
testl %r14d, %r14d
movq $-1, %rbx
cmovsq %rbx, %rdi
callq _Znam
movq %rax, 16(%rsp) # 8-byte Spill
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r14d, %r14d
jle .LBB2_11
# %bb.1: # %.lr.ph34
movslq 12(%rsp), %rax # 4-byte Folded Reload
leaq (,%rax,4), %rcx
testl %eax, %eax
cmovsq %rbx, %rcx
movq %rcx, 32(%rsp) # 8-byte Spill
leal -2(%r12), %r13d
leal -2(%rax), %ebp
movl %r12d, %ecx
movq %rcx, 24(%rsp) # 8-byte Spill
movl %eax, %r14d
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_10: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r15
cmpq 24(%rsp), %r15 # 8-byte Folded Reload
je .LBB2_11
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
movq 32(%rsp), %rdi # 8-byte Reload
callq _Znam
movq %rax, %r12
movq 16(%rsp), %rax # 8-byte Reload
movq %r12, (%rax,%r15,8)
cmpl $0, 12(%rsp) # 4-byte Folded Reload
jle .LBB2_10
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
xorl %ebx, %ebx
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_4 Depth=2
movl %eax, (%r12,%rbx,4)
incq %rbx
cmpq %rbx, %r14
je .LBB2_10
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
xorl %eax, %eax
testq %r15, %r15
je .LBB2_9
# %bb.5: # in Loop: Header=BB2_4 Depth=2
testq %rbx, %rbx
je .LBB2_9
# %bb.6: # in Loop: Header=BB2_4 Depth=2
cmpq %r13, %r15
je .LBB2_9
# %bb.7: # in Loop: Header=BB2_4 Depth=2
cmpq %rbx, %rbp
je .LBB2_9
# %bb.8: # in Loop: Header=BB2_4 Depth=2
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
jmp .LBB2_9
.LBB2_11: # %._crit_edge35
movq 16(%rsp), %rax # 8-byte Reload
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12create_worldii, .Lfunc_end2-_Z12create_worldii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__next_turnPPiS0_ii # -- Begin function _Z24__device_stub__next_turnPPiS0_ii
.p2align 4, 0x90
.type _Z24__device_stub__next_turnPPiS0_ii,@function
_Z24__device_stub__next_turnPPiS0_ii: # @_Z24__device_stub__next_turnPPiS0_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9next_turnPPiS0_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z24__device_stub__next_turnPPiS0_ii, .Lfunc_end3-_Z24__device_stub__next_turnPPiS0_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
addl $-7, %edi
cmpl $-3, %edi
ja .LBB4_2
# %bb.1:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $60, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $1, %r14d
jmp .LBB4_30
.LBB4_2:
movq 8(%rsi), %rdi
xorl %r14d, %r14d
movq %rsi, %r15
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 32(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %ebp, %r15d
addl $2, %r15d
je .LBB4_6
# %bb.3:
movl %r13d, %esi
addl $2, %esi
je .LBB4_6
# %bb.4:
movl %ebx, %ecx
testq %rcx, %rcx
je .LBB4_6
# %bb.5:
movl %eax, %eax
testq %rax, %rax
je .LBB4_6
# %bb.7:
movl %r15d, %eax
imull %esi, %eax
shll $2, %eax
movl %eax, 36(%rsp) # 4-byte Spill
movl %r15d, %edi
movl %esi, 8(%rsp) # 4-byte Spill
callq _Z12create_worldii
movq %rax, 56(%rsp) # 8-byte Spill
movl %r15d, 12(%rsp) # 4-byte Spill
movslq %r15d, %rdi
shlq $3, %rdi
cmpl $-2, %ebp
movq $-1, %r14
cmovlq %r14, %rdi
callq _Znam
movq %rax, %r12
movq %rbp, 48(%rsp) # 8-byte Spill
cmpl $-1, %ebp
jl .LBB4_12
# %bb.8: # %.lr.ph17.i
movl 8(%rsp), %eax # 4-byte Reload
movslq %eax, %rbx
shlq $2, %rbx
cmpl $-2, %r13d
cmovlq %r14, %rbx
movl %eax, %r15d
shlq $2, %r15
movl 12(%rsp), %ebp # 4-byte Reload
xorl %r14d, %r14d
jmp .LBB4_9
.p2align 4, 0x90
.LBB4_11: # %._crit_edge.i
# in Loop: Header=BB4_9 Depth=1
incq %r14
cmpq %r14, %rbp
je .LBB4_12
.LBB4_9: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
callq _Znam
movq %rax, (%r12,%r14,8)
cmpl $-1, %r13d
jl .LBB4_11
# %bb.10: # %.lr.ph.preheader.i
# in Loop: Header=BB4_9 Depth=1
movq %rax, %rdi
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
jmp .LBB4_11
.LBB4_6:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_30
.LBB4_12: # %_Z18create_empty_worldii.exit
movq 56(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl 12(%rsp), %ebp # 4-byte Reload
movl %ebp, %esi
movl 8(%rsp), %edx # 4-byte Reload
callq _Z12print_matrixPPiii
movslq 36(%rsp), %r13 # 4-byte Folded Reload
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
cmpq $0, 24(%rsp)
jne .LBB4_18
# %bb.13:
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_31
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB4_16
# %bb.15:
movzbl 67(%rbx), %eax
jmp .LBB4_17
.LBB4_16:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_18:
cmpq $0, 16(%rsp)
movq 48(%rsp), %r14 # 8-byte Reload
jne .LBB4_24
# %bb.19:
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_31
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i54
cmpb $0, 56(%rbx)
je .LBB4_22
# %bb.21:
movzbl 67(%rbx), %eax
jmp .LBB4_23
.LBB4_22:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit57
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_24:
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_26
# %bb.25:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl %ebp, 44(%rsp)
movl 8(%rsp), %eax # 4-byte Reload
movl %eax, 40(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9next_turnPPiS0_ii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_26:
movq 16(%rsp), %rsi
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r12, %rdi
movl %ebp, %esi
movl 8(%rsp), %edx # 4-byte Reload
callq _Z12print_matrixPPiii
cmpl $-1, %r14d
jl .LBB4_29
# %bb.27: # %.lr.ph.preheader
cmpl $2, %ebp
movl $1, %ebx
cmovgel %ebp, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_28: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%r15,%r14,8), %rdi
callq free
movq (%r12,%r14,8), %rdi
callq free
incq %r14
cmpq %r14, %rbx
jne .LBB4_28
.LBB4_29: # %._crit_edge
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %r14d, %r14d
.LBB4_30:
movl %r14d, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_31:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9next_turnPPiS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "| "
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "|\n"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n"
.size .L.str.3, 2
.type _Z9next_turnPPiS0_ii,@object # @_Z9next_turnPPiS0_ii
.section .rodata,"a",@progbits
.globl _Z9next_turnPPiS0_ii
.p2align 3, 0x0
_Z9next_turnPPiS0_ii:
.quad _Z24__device_stub__next_turnPPiS0_ii
.size _Z9next_turnPPiS0_ii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Usage: ./gol [width] [height] [iterations] [number of tests]"
.size .L.str.4, 61
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "must enter INT values"
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "not able to alloc memory on device"
.size .L.str.6, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9next_turnPPiS0_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__next_turnPPiS0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z9next_turnPPiS0_ii
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ __forceinline__ size_t gpu_fieldn_index(unsigned int x, unsigned int y, unsigned int z, unsigned int d)
{
return (NX*(NY*(NZ*(d-1)+z)+y)+x);
}
__global__ void gpu_stream(double *f0, double *f1, double *f2, double *h0, double *h1, double *h2, double *temp0, double *temp1, double *temp2)
{
unsigned int y = blockIdx.y;
unsigned int z = blockIdx.z;
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
// streaming step
unsigned int xp1 = (x + 1) % NX;
unsigned int yp1 = (y + 1) % NY;
unsigned int zp1 = (z + 1) % NZ;
unsigned int xm1 = (NX + x - 1) % NX;
unsigned int ym1 = (NY + y - 1) % NY;
unsigned int zm1 = (NZ + z - 1) % NZ;
// direction numbering scheme
// 6 2 5
// 3 0 1
// 7 4 8
// load populations from adjacent nodes (ft is post-streaming population of f1)
// flows
f1[gpu_fieldn_index(x, y, z, 1)] = f2[gpu_fieldn_index(xm1, y, z, 1)];
f1[gpu_fieldn_index(x, y, z, 2)] = f2[gpu_fieldn_index(xp1, y, z, 2)];
f1[gpu_fieldn_index(x, y, z, 3)] = f2[gpu_fieldn_index(x, ym1, z, 3)];
f1[gpu_fieldn_index(x, y, z, 4)] = f2[gpu_fieldn_index(x, yp1, z, 4)];
f1[gpu_fieldn_index(x, y, z, 5)] = f2[gpu_fieldn_index(x, y, zm1, 5)];
f1[gpu_fieldn_index(x, y, z, 6)] = f2[gpu_fieldn_index(x, y, zp1, 6)];
f1[gpu_fieldn_index(x, y, z, 7)] = f2[gpu_fieldn_index(xm1, ym1, z, 7)];
f1[gpu_fieldn_index(x, y, z, 8)] = f2[gpu_fieldn_index(xp1, yp1, z, 8)];
f1[gpu_fieldn_index(x, y, z, 9)] = f2[gpu_fieldn_index(xm1, y, zm1, 9)];
f1[gpu_fieldn_index(x, y, z, 10)] = f2[gpu_fieldn_index(xp1, y, zp1, 10)];
f1[gpu_fieldn_index(x, y, z, 11)] = f2[gpu_fieldn_index(x, ym1, zm1, 11)];
f1[gpu_fieldn_index(x, y, z, 12)] = f2[gpu_fieldn_index(x, yp1, zp1, 12)];
f1[gpu_fieldn_index(x, y, z, 13)] = f2[gpu_fieldn_index(xm1, yp1, z, 13)];
f1[gpu_fieldn_index(x, y, z, 14)] = f2[gpu_fieldn_index(xp1, ym1, z, 14)];
f1[gpu_fieldn_index(x, y, z, 15)] = f2[gpu_fieldn_index(xm1, y, zp1, 15)];
f1[gpu_fieldn_index(x, y, z, 16)] = f2[gpu_fieldn_index(xp1, y, zm1, 16)];
f1[gpu_fieldn_index(x, y, z, 17)] = f2[gpu_fieldn_index(x, ym1, zp1, 17)];
f1[gpu_fieldn_index(x, y, z, 18)] = f2[gpu_fieldn_index(x, yp1, zm1, 18)];
f1[gpu_fieldn_index(x, y, z, 19)] = f2[gpu_fieldn_index(xm1, ym1, zm1, 19)];
f1[gpu_fieldn_index(x, y, z, 20)] = f2[gpu_fieldn_index(xp1, yp1, zp1, 20)];
f1[gpu_fieldn_index(x, y, z, 21)] = f2[gpu_fieldn_index(xm1, ym1, zp1, 21)];
f1[gpu_fieldn_index(x, y, z, 22)] = f2[gpu_fieldn_index(xp1, yp1, zm1, 22)];
f1[gpu_fieldn_index(x, y, z, 23)] = f2[gpu_fieldn_index(xm1, yp1, zm1, 23)];
f1[gpu_fieldn_index(x, y, z, 24)] = f2[gpu_fieldn_index(xp1, ym1, zp1, 24)];
f1[gpu_fieldn_index(x, y, z, 25)] = f2[gpu_fieldn_index(xp1, ym1, zm1, 25)];
f1[gpu_fieldn_index(x, y, z, 26)] = f2[gpu_fieldn_index(xm1, yp1, zp1, 26)];
// charges
h1[gpu_fieldn_index(x, y, z, 1)] = h2[gpu_fieldn_index(xm1, y, z, 1)];
h1[gpu_fieldn_index(x, y, z, 2)] = h2[gpu_fieldn_index(xp1, y, z, 2)];
h1[gpu_fieldn_index(x, y, z, 3)] = h2[gpu_fieldn_index(x, ym1, z, 3)];
h1[gpu_fieldn_index(x, y, z, 4)] = h2[gpu_fieldn_index(x, yp1, z, 4)];
h1[gpu_fieldn_index(x, y, z, 5)] = h2[gpu_fieldn_index(x, y, zm1, 5)];
h1[gpu_fieldn_index(x, y, z, 6)] = h2[gpu_fieldn_index(x, y, zp1, 6)];
h1[gpu_fieldn_index(x, y, z, 7)] = h2[gpu_fieldn_index(xm1, ym1, z, 7)];
h1[gpu_fieldn_index(x, y, z, 8)] = h2[gpu_fieldn_index(xp1, yp1, z, 8)];
h1[gpu_fieldn_index(x, y, z, 9)] = h2[gpu_fieldn_index(xm1, y, zm1, 9)];
h1[gpu_fieldn_index(x, y, z, 10)] = h2[gpu_fieldn_index(xp1, y, zp1, 10)];
h1[gpu_fieldn_index(x, y, z, 11)] = h2[gpu_fieldn_index(x, ym1, zm1, 11)];
h1[gpu_fieldn_index(x, y, z, 12)] = h2[gpu_fieldn_index(x, yp1, zp1, 12)];
h1[gpu_fieldn_index(x, y, z, 13)] = h2[gpu_fieldn_index(xm1, yp1, z, 13)];
h1[gpu_fieldn_index(x, y, z, 14)] = h2[gpu_fieldn_index(xp1, ym1, z, 14)];
h1[gpu_fieldn_index(x, y, z, 15)] = h2[gpu_fieldn_index(xm1, y, zp1, 15)];
h1[gpu_fieldn_index(x, y, z, 16)] = h2[gpu_fieldn_index(xp1, y, zm1, 16)];
h1[gpu_fieldn_index(x, y, z, 17)] = h2[gpu_fieldn_index(x, ym1, zp1, 17)];
h1[gpu_fieldn_index(x, y, z, 18)] = h2[gpu_fieldn_index(x, yp1, zm1, 18)];
h1[gpu_fieldn_index(x, y, z, 19)] = h2[gpu_fieldn_index(xm1, ym1, zm1, 19)];
h1[gpu_fieldn_index(x, y, z, 20)] = h2[gpu_fieldn_index(xp1, yp1, zp1, 20)];
h1[gpu_fieldn_index(x, y, z, 21)] = h2[gpu_fieldn_index(xm1, ym1, zp1, 21)];
h1[gpu_fieldn_index(x, y, z, 22)] = h2[gpu_fieldn_index(xp1, yp1, zm1, 22)];
h1[gpu_fieldn_index(x, y, z, 23)] = h2[gpu_fieldn_index(xm1, yp1, zm1, 23)];
h1[gpu_fieldn_index(x, y, z, 24)] = h2[gpu_fieldn_index(xp1, ym1, zp1, 24)];
h1[gpu_fieldn_index(x, y, z, 25)] = h2[gpu_fieldn_index(xp1, ym1, zm1, 25)];
h1[gpu_fieldn_index(x, y, z, 26)] = h2[gpu_fieldn_index(xm1, yp1, zp1, 26)];
// temperature
temp1[gpu_fieldn_index(x, y, z, 1)] = temp2[gpu_fieldn_index(xm1, y, z, 1)];
temp1[gpu_fieldn_index(x, y, z, 2)] = temp2[gpu_fieldn_index(xp1, y, z, 2)];
temp1[gpu_fieldn_index(x, y, z, 3)] = temp2[gpu_fieldn_index(x, ym1, z, 3)];
temp1[gpu_fieldn_index(x, y, z, 4)] = temp2[gpu_fieldn_index(x, yp1, z, 4)];
temp1[gpu_fieldn_index(x, y, z, 5)] = temp2[gpu_fieldn_index(x, y, zm1, 5)];
temp1[gpu_fieldn_index(x, y, z, 6)] = temp2[gpu_fieldn_index(x, y, zp1, 6)];
temp1[gpu_fieldn_index(x, y, z, 7)] = temp2[gpu_fieldn_index(xm1, ym1, z, 7)];
temp1[gpu_fieldn_index(x, y, z, 8)] = temp2[gpu_fieldn_index(xp1, yp1, z, 8)];
temp1[gpu_fieldn_index(x, y, z, 9)] = temp2[gpu_fieldn_index(xm1, y, zm1, 9)];
temp1[gpu_fieldn_index(x, y, z, 10)] = temp2[gpu_fieldn_index(xp1, y, zp1, 10)];
temp1[gpu_fieldn_index(x, y, z, 11)] = temp2[gpu_fieldn_index(x, ym1, zm1, 11)];
temp1[gpu_fieldn_index(x, y, z, 12)] = temp2[gpu_fieldn_index(x, yp1, zp1, 12)];
temp1[gpu_fieldn_index(x, y, z, 13)] = temp2[gpu_fieldn_index(xm1, yp1, z, 13)];
temp1[gpu_fieldn_index(x, y, z, 14)] = temp2[gpu_fieldn_index(xp1, ym1, z, 14)];
temp1[gpu_fieldn_index(x, y, z, 15)] = temp2[gpu_fieldn_index(xm1, y, zp1, 15)];
temp1[gpu_fieldn_index(x, y, z, 16)] = temp2[gpu_fieldn_index(xp1, y, zm1, 16)];
temp1[gpu_fieldn_index(x, y, z, 17)] = temp2[gpu_fieldn_index(x, ym1, zp1, 17)];
temp1[gpu_fieldn_index(x, y, z, 18)] = temp2[gpu_fieldn_index(x, yp1, zm1, 18)];
temp1[gpu_fieldn_index(x, y, z, 19)] = temp2[gpu_fieldn_index(xm1, ym1, zm1, 19)];
temp1[gpu_fieldn_index(x, y, z, 20)] = temp2[gpu_fieldn_index(xp1, yp1, zp1, 20)];
temp1[gpu_fieldn_index(x, y, z, 21)] = temp2[gpu_fieldn_index(xm1, ym1, zp1, 21)];
temp1[gpu_fieldn_index(x, y, z, 22)] = temp2[gpu_fieldn_index(xp1, yp1, zm1, 22)];
temp1[gpu_fieldn_index(x, y, z, 23)] = temp2[gpu_fieldn_index(xm1, yp1, zm1, 23)];
temp1[gpu_fieldn_index(x, y, z, 24)] = temp2[gpu_fieldn_index(xp1, ym1, zp1, 24)];
temp1[gpu_fieldn_index(x, y, z, 25)] = temp2[gpu_fieldn_index(xp1, ym1, zm1, 25)];
temp1[gpu_fieldn_index(x, y, z, 26)] = temp2[gpu_fieldn_index(xm1, yp1, zp1, 26)];
} | .file "tmpxft_00090441_00000000-6_gpu_stream.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z10gpu_streamPdS_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_
.type _Z46__device_stub__Z10gpu_streamPdS_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_, @function
_Z46__device_stub__Z10gpu_streamPdS_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 248
pushq 88(%rsp)
.cfi_def_cfa_offset 256
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z10gpu_streamPdS_S_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z46__device_stub__Z10gpu_streamPdS_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_, .-_Z46__device_stub__Z10gpu_streamPdS_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_
.globl _Z10gpu_streamPdS_S_S_S_S_S_S_S_
.type _Z10gpu_streamPdS_S_S_S_S_S_S_S_, @function
_Z10gpu_streamPdS_S_S_S_S_S_S_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z46__device_stub__Z10gpu_streamPdS_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10gpu_streamPdS_S_S_S_S_S_S_S_, .-_Z10gpu_streamPdS_S_S_S_S_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10gpu_streamPdS_S_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10gpu_streamPdS_S_S_S_S_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ __forceinline__ size_t gpu_fieldn_index(unsigned int x, unsigned int y, unsigned int z, unsigned int d)
{
return (NX*(NY*(NZ*(d-1)+z)+y)+x);
}
__global__ void gpu_stream(double *f0, double *f1, double *f2, double *h0, double *h1, double *h2, double *temp0, double *temp1, double *temp2)
{
unsigned int y = blockIdx.y;
unsigned int z = blockIdx.z;
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
// streaming step
unsigned int xp1 = (x + 1) % NX;
unsigned int yp1 = (y + 1) % NY;
unsigned int zp1 = (z + 1) % NZ;
unsigned int xm1 = (NX + x - 1) % NX;
unsigned int ym1 = (NY + y - 1) % NY;
unsigned int zm1 = (NZ + z - 1) % NZ;
// direction numbering scheme
// 6 2 5
// 3 0 1
// 7 4 8
// load populations from adjacent nodes (ft is post-streaming population of f1)
// flows
f1[gpu_fieldn_index(x, y, z, 1)] = f2[gpu_fieldn_index(xm1, y, z, 1)];
f1[gpu_fieldn_index(x, y, z, 2)] = f2[gpu_fieldn_index(xp1, y, z, 2)];
f1[gpu_fieldn_index(x, y, z, 3)] = f2[gpu_fieldn_index(x, ym1, z, 3)];
f1[gpu_fieldn_index(x, y, z, 4)] = f2[gpu_fieldn_index(x, yp1, z, 4)];
f1[gpu_fieldn_index(x, y, z, 5)] = f2[gpu_fieldn_index(x, y, zm1, 5)];
f1[gpu_fieldn_index(x, y, z, 6)] = f2[gpu_fieldn_index(x, y, zp1, 6)];
f1[gpu_fieldn_index(x, y, z, 7)] = f2[gpu_fieldn_index(xm1, ym1, z, 7)];
f1[gpu_fieldn_index(x, y, z, 8)] = f2[gpu_fieldn_index(xp1, yp1, z, 8)];
f1[gpu_fieldn_index(x, y, z, 9)] = f2[gpu_fieldn_index(xm1, y, zm1, 9)];
f1[gpu_fieldn_index(x, y, z, 10)] = f2[gpu_fieldn_index(xp1, y, zp1, 10)];
f1[gpu_fieldn_index(x, y, z, 11)] = f2[gpu_fieldn_index(x, ym1, zm1, 11)];
f1[gpu_fieldn_index(x, y, z, 12)] = f2[gpu_fieldn_index(x, yp1, zp1, 12)];
f1[gpu_fieldn_index(x, y, z, 13)] = f2[gpu_fieldn_index(xm1, yp1, z, 13)];
f1[gpu_fieldn_index(x, y, z, 14)] = f2[gpu_fieldn_index(xp1, ym1, z, 14)];
f1[gpu_fieldn_index(x, y, z, 15)] = f2[gpu_fieldn_index(xm1, y, zp1, 15)];
f1[gpu_fieldn_index(x, y, z, 16)] = f2[gpu_fieldn_index(xp1, y, zm1, 16)];
f1[gpu_fieldn_index(x, y, z, 17)] = f2[gpu_fieldn_index(x, ym1, zp1, 17)];
f1[gpu_fieldn_index(x, y, z, 18)] = f2[gpu_fieldn_index(x, yp1, zm1, 18)];
f1[gpu_fieldn_index(x, y, z, 19)] = f2[gpu_fieldn_index(xm1, ym1, zm1, 19)];
f1[gpu_fieldn_index(x, y, z, 20)] = f2[gpu_fieldn_index(xp1, yp1, zp1, 20)];
f1[gpu_fieldn_index(x, y, z, 21)] = f2[gpu_fieldn_index(xm1, ym1, zp1, 21)];
f1[gpu_fieldn_index(x, y, z, 22)] = f2[gpu_fieldn_index(xp1, yp1, zm1, 22)];
f1[gpu_fieldn_index(x, y, z, 23)] = f2[gpu_fieldn_index(xm1, yp1, zm1, 23)];
f1[gpu_fieldn_index(x, y, z, 24)] = f2[gpu_fieldn_index(xp1, ym1, zp1, 24)];
f1[gpu_fieldn_index(x, y, z, 25)] = f2[gpu_fieldn_index(xp1, ym1, zm1, 25)];
f1[gpu_fieldn_index(x, y, z, 26)] = f2[gpu_fieldn_index(xm1, yp1, zp1, 26)];
// charges
h1[gpu_fieldn_index(x, y, z, 1)] = h2[gpu_fieldn_index(xm1, y, z, 1)];
h1[gpu_fieldn_index(x, y, z, 2)] = h2[gpu_fieldn_index(xp1, y, z, 2)];
h1[gpu_fieldn_index(x, y, z, 3)] = h2[gpu_fieldn_index(x, ym1, z, 3)];
h1[gpu_fieldn_index(x, y, z, 4)] = h2[gpu_fieldn_index(x, yp1, z, 4)];
h1[gpu_fieldn_index(x, y, z, 5)] = h2[gpu_fieldn_index(x, y, zm1, 5)];
h1[gpu_fieldn_index(x, y, z, 6)] = h2[gpu_fieldn_index(x, y, zp1, 6)];
h1[gpu_fieldn_index(x, y, z, 7)] = h2[gpu_fieldn_index(xm1, ym1, z, 7)];
h1[gpu_fieldn_index(x, y, z, 8)] = h2[gpu_fieldn_index(xp1, yp1, z, 8)];
h1[gpu_fieldn_index(x, y, z, 9)] = h2[gpu_fieldn_index(xm1, y, zm1, 9)];
h1[gpu_fieldn_index(x, y, z, 10)] = h2[gpu_fieldn_index(xp1, y, zp1, 10)];
h1[gpu_fieldn_index(x, y, z, 11)] = h2[gpu_fieldn_index(x, ym1, zm1, 11)];
h1[gpu_fieldn_index(x, y, z, 12)] = h2[gpu_fieldn_index(x, yp1, zp1, 12)];
h1[gpu_fieldn_index(x, y, z, 13)] = h2[gpu_fieldn_index(xm1, yp1, z, 13)];
h1[gpu_fieldn_index(x, y, z, 14)] = h2[gpu_fieldn_index(xp1, ym1, z, 14)];
h1[gpu_fieldn_index(x, y, z, 15)] = h2[gpu_fieldn_index(xm1, y, zp1, 15)];
h1[gpu_fieldn_index(x, y, z, 16)] = h2[gpu_fieldn_index(xp1, y, zm1, 16)];
h1[gpu_fieldn_index(x, y, z, 17)] = h2[gpu_fieldn_index(x, ym1, zp1, 17)];
h1[gpu_fieldn_index(x, y, z, 18)] = h2[gpu_fieldn_index(x, yp1, zm1, 18)];
h1[gpu_fieldn_index(x, y, z, 19)] = h2[gpu_fieldn_index(xm1, ym1, zm1, 19)];
h1[gpu_fieldn_index(x, y, z, 20)] = h2[gpu_fieldn_index(xp1, yp1, zp1, 20)];
h1[gpu_fieldn_index(x, y, z, 21)] = h2[gpu_fieldn_index(xm1, ym1, zp1, 21)];
h1[gpu_fieldn_index(x, y, z, 22)] = h2[gpu_fieldn_index(xp1, yp1, zm1, 22)];
h1[gpu_fieldn_index(x, y, z, 23)] = h2[gpu_fieldn_index(xm1, yp1, zm1, 23)];
h1[gpu_fieldn_index(x, y, z, 24)] = h2[gpu_fieldn_index(xp1, ym1, zp1, 24)];
h1[gpu_fieldn_index(x, y, z, 25)] = h2[gpu_fieldn_index(xp1, ym1, zm1, 25)];
h1[gpu_fieldn_index(x, y, z, 26)] = h2[gpu_fieldn_index(xm1, yp1, zp1, 26)];
// temperature
temp1[gpu_fieldn_index(x, y, z, 1)] = temp2[gpu_fieldn_index(xm1, y, z, 1)];
temp1[gpu_fieldn_index(x, y, z, 2)] = temp2[gpu_fieldn_index(xp1, y, z, 2)];
temp1[gpu_fieldn_index(x, y, z, 3)] = temp2[gpu_fieldn_index(x, ym1, z, 3)];
temp1[gpu_fieldn_index(x, y, z, 4)] = temp2[gpu_fieldn_index(x, yp1, z, 4)];
temp1[gpu_fieldn_index(x, y, z, 5)] = temp2[gpu_fieldn_index(x, y, zm1, 5)];
temp1[gpu_fieldn_index(x, y, z, 6)] = temp2[gpu_fieldn_index(x, y, zp1, 6)];
temp1[gpu_fieldn_index(x, y, z, 7)] = temp2[gpu_fieldn_index(xm1, ym1, z, 7)];
temp1[gpu_fieldn_index(x, y, z, 8)] = temp2[gpu_fieldn_index(xp1, yp1, z, 8)];
temp1[gpu_fieldn_index(x, y, z, 9)] = temp2[gpu_fieldn_index(xm1, y, zm1, 9)];
temp1[gpu_fieldn_index(x, y, z, 10)] = temp2[gpu_fieldn_index(xp1, y, zp1, 10)];
temp1[gpu_fieldn_index(x, y, z, 11)] = temp2[gpu_fieldn_index(x, ym1, zm1, 11)];
temp1[gpu_fieldn_index(x, y, z, 12)] = temp2[gpu_fieldn_index(x, yp1, zp1, 12)];
temp1[gpu_fieldn_index(x, y, z, 13)] = temp2[gpu_fieldn_index(xm1, yp1, z, 13)];
temp1[gpu_fieldn_index(x, y, z, 14)] = temp2[gpu_fieldn_index(xp1, ym1, z, 14)];
temp1[gpu_fieldn_index(x, y, z, 15)] = temp2[gpu_fieldn_index(xm1, y, zp1, 15)];
temp1[gpu_fieldn_index(x, y, z, 16)] = temp2[gpu_fieldn_index(xp1, y, zm1, 16)];
temp1[gpu_fieldn_index(x, y, z, 17)] = temp2[gpu_fieldn_index(x, ym1, zp1, 17)];
temp1[gpu_fieldn_index(x, y, z, 18)] = temp2[gpu_fieldn_index(x, yp1, zm1, 18)];
temp1[gpu_fieldn_index(x, y, z, 19)] = temp2[gpu_fieldn_index(xm1, ym1, zm1, 19)];
temp1[gpu_fieldn_index(x, y, z, 20)] = temp2[gpu_fieldn_index(xp1, yp1, zp1, 20)];
temp1[gpu_fieldn_index(x, y, z, 21)] = temp2[gpu_fieldn_index(xm1, ym1, zp1, 21)];
temp1[gpu_fieldn_index(x, y, z, 22)] = temp2[gpu_fieldn_index(xp1, yp1, zm1, 22)];
temp1[gpu_fieldn_index(x, y, z, 23)] = temp2[gpu_fieldn_index(xm1, yp1, zm1, 23)];
temp1[gpu_fieldn_index(x, y, z, 24)] = temp2[gpu_fieldn_index(xp1, ym1, zp1, 24)];
temp1[gpu_fieldn_index(x, y, z, 25)] = temp2[gpu_fieldn_index(xp1, ym1, zm1, 25)];
temp1[gpu_fieldn_index(x, y, z, 26)] = temp2[gpu_fieldn_index(xm1, yp1, zp1, 26)];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ __forceinline__ size_t gpu_fieldn_index(unsigned int x, unsigned int y, unsigned int z, unsigned int d)
{
return (NX*(NY*(NZ*(d-1)+z)+y)+x);
}
__global__ void gpu_stream(double *f0, double *f1, double *f2, double *h0, double *h1, double *h2, double *temp0, double *temp1, double *temp2)
{
unsigned int y = blockIdx.y;
unsigned int z = blockIdx.z;
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
// streaming step
unsigned int xp1 = (x + 1) % NX;
unsigned int yp1 = (y + 1) % NY;
unsigned int zp1 = (z + 1) % NZ;
unsigned int xm1 = (NX + x - 1) % NX;
unsigned int ym1 = (NY + y - 1) % NY;
unsigned int zm1 = (NZ + z - 1) % NZ;
// direction numbering scheme
// 6 2 5
// 3 0 1
// 7 4 8
// load populations from adjacent nodes (ft is post-streaming population of f1)
// flows
f1[gpu_fieldn_index(x, y, z, 1)] = f2[gpu_fieldn_index(xm1, y, z, 1)];
f1[gpu_fieldn_index(x, y, z, 2)] = f2[gpu_fieldn_index(xp1, y, z, 2)];
f1[gpu_fieldn_index(x, y, z, 3)] = f2[gpu_fieldn_index(x, ym1, z, 3)];
f1[gpu_fieldn_index(x, y, z, 4)] = f2[gpu_fieldn_index(x, yp1, z, 4)];
f1[gpu_fieldn_index(x, y, z, 5)] = f2[gpu_fieldn_index(x, y, zm1, 5)];
f1[gpu_fieldn_index(x, y, z, 6)] = f2[gpu_fieldn_index(x, y, zp1, 6)];
f1[gpu_fieldn_index(x, y, z, 7)] = f2[gpu_fieldn_index(xm1, ym1, z, 7)];
f1[gpu_fieldn_index(x, y, z, 8)] = f2[gpu_fieldn_index(xp1, yp1, z, 8)];
f1[gpu_fieldn_index(x, y, z, 9)] = f2[gpu_fieldn_index(xm1, y, zm1, 9)];
f1[gpu_fieldn_index(x, y, z, 10)] = f2[gpu_fieldn_index(xp1, y, zp1, 10)];
f1[gpu_fieldn_index(x, y, z, 11)] = f2[gpu_fieldn_index(x, ym1, zm1, 11)];
f1[gpu_fieldn_index(x, y, z, 12)] = f2[gpu_fieldn_index(x, yp1, zp1, 12)];
f1[gpu_fieldn_index(x, y, z, 13)] = f2[gpu_fieldn_index(xm1, yp1, z, 13)];
f1[gpu_fieldn_index(x, y, z, 14)] = f2[gpu_fieldn_index(xp1, ym1, z, 14)];
f1[gpu_fieldn_index(x, y, z, 15)] = f2[gpu_fieldn_index(xm1, y, zp1, 15)];
f1[gpu_fieldn_index(x, y, z, 16)] = f2[gpu_fieldn_index(xp1, y, zm1, 16)];
f1[gpu_fieldn_index(x, y, z, 17)] = f2[gpu_fieldn_index(x, ym1, zp1, 17)];
f1[gpu_fieldn_index(x, y, z, 18)] = f2[gpu_fieldn_index(x, yp1, zm1, 18)];
f1[gpu_fieldn_index(x, y, z, 19)] = f2[gpu_fieldn_index(xm1, ym1, zm1, 19)];
f1[gpu_fieldn_index(x, y, z, 20)] = f2[gpu_fieldn_index(xp1, yp1, zp1, 20)];
f1[gpu_fieldn_index(x, y, z, 21)] = f2[gpu_fieldn_index(xm1, ym1, zp1, 21)];
f1[gpu_fieldn_index(x, y, z, 22)] = f2[gpu_fieldn_index(xp1, yp1, zm1, 22)];
f1[gpu_fieldn_index(x, y, z, 23)] = f2[gpu_fieldn_index(xm1, yp1, zm1, 23)];
f1[gpu_fieldn_index(x, y, z, 24)] = f2[gpu_fieldn_index(xp1, ym1, zp1, 24)];
f1[gpu_fieldn_index(x, y, z, 25)] = f2[gpu_fieldn_index(xp1, ym1, zm1, 25)];
f1[gpu_fieldn_index(x, y, z, 26)] = f2[gpu_fieldn_index(xm1, yp1, zp1, 26)];
// charges
h1[gpu_fieldn_index(x, y, z, 1)] = h2[gpu_fieldn_index(xm1, y, z, 1)];
h1[gpu_fieldn_index(x, y, z, 2)] = h2[gpu_fieldn_index(xp1, y, z, 2)];
h1[gpu_fieldn_index(x, y, z, 3)] = h2[gpu_fieldn_index(x, ym1, z, 3)];
h1[gpu_fieldn_index(x, y, z, 4)] = h2[gpu_fieldn_index(x, yp1, z, 4)];
h1[gpu_fieldn_index(x, y, z, 5)] = h2[gpu_fieldn_index(x, y, zm1, 5)];
h1[gpu_fieldn_index(x, y, z, 6)] = h2[gpu_fieldn_index(x, y, zp1, 6)];
h1[gpu_fieldn_index(x, y, z, 7)] = h2[gpu_fieldn_index(xm1, ym1, z, 7)];
h1[gpu_fieldn_index(x, y, z, 8)] = h2[gpu_fieldn_index(xp1, yp1, z, 8)];
h1[gpu_fieldn_index(x, y, z, 9)] = h2[gpu_fieldn_index(xm1, y, zm1, 9)];
h1[gpu_fieldn_index(x, y, z, 10)] = h2[gpu_fieldn_index(xp1, y, zp1, 10)];
h1[gpu_fieldn_index(x, y, z, 11)] = h2[gpu_fieldn_index(x, ym1, zm1, 11)];
h1[gpu_fieldn_index(x, y, z, 12)] = h2[gpu_fieldn_index(x, yp1, zp1, 12)];
h1[gpu_fieldn_index(x, y, z, 13)] = h2[gpu_fieldn_index(xm1, yp1, z, 13)];
h1[gpu_fieldn_index(x, y, z, 14)] = h2[gpu_fieldn_index(xp1, ym1, z, 14)];
h1[gpu_fieldn_index(x, y, z, 15)] = h2[gpu_fieldn_index(xm1, y, zp1, 15)];
h1[gpu_fieldn_index(x, y, z, 16)] = h2[gpu_fieldn_index(xp1, y, zm1, 16)];
h1[gpu_fieldn_index(x, y, z, 17)] = h2[gpu_fieldn_index(x, ym1, zp1, 17)];
h1[gpu_fieldn_index(x, y, z, 18)] = h2[gpu_fieldn_index(x, yp1, zm1, 18)];
h1[gpu_fieldn_index(x, y, z, 19)] = h2[gpu_fieldn_index(xm1, ym1, zm1, 19)];
h1[gpu_fieldn_index(x, y, z, 20)] = h2[gpu_fieldn_index(xp1, yp1, zp1, 20)];
h1[gpu_fieldn_index(x, y, z, 21)] = h2[gpu_fieldn_index(xm1, ym1, zp1, 21)];
h1[gpu_fieldn_index(x, y, z, 22)] = h2[gpu_fieldn_index(xp1, yp1, zm1, 22)];
h1[gpu_fieldn_index(x, y, z, 23)] = h2[gpu_fieldn_index(xm1, yp1, zm1, 23)];
h1[gpu_fieldn_index(x, y, z, 24)] = h2[gpu_fieldn_index(xp1, ym1, zp1, 24)];
h1[gpu_fieldn_index(x, y, z, 25)] = h2[gpu_fieldn_index(xp1, ym1, zm1, 25)];
h1[gpu_fieldn_index(x, y, z, 26)] = h2[gpu_fieldn_index(xm1, yp1, zp1, 26)];
// temperature
temp1[gpu_fieldn_index(x, y, z, 1)] = temp2[gpu_fieldn_index(xm1, y, z, 1)];
temp1[gpu_fieldn_index(x, y, z, 2)] = temp2[gpu_fieldn_index(xp1, y, z, 2)];
temp1[gpu_fieldn_index(x, y, z, 3)] = temp2[gpu_fieldn_index(x, ym1, z, 3)];
temp1[gpu_fieldn_index(x, y, z, 4)] = temp2[gpu_fieldn_index(x, yp1, z, 4)];
temp1[gpu_fieldn_index(x, y, z, 5)] = temp2[gpu_fieldn_index(x, y, zm1, 5)];
temp1[gpu_fieldn_index(x, y, z, 6)] = temp2[gpu_fieldn_index(x, y, zp1, 6)];
temp1[gpu_fieldn_index(x, y, z, 7)] = temp2[gpu_fieldn_index(xm1, ym1, z, 7)];
temp1[gpu_fieldn_index(x, y, z, 8)] = temp2[gpu_fieldn_index(xp1, yp1, z, 8)];
temp1[gpu_fieldn_index(x, y, z, 9)] = temp2[gpu_fieldn_index(xm1, y, zm1, 9)];
temp1[gpu_fieldn_index(x, y, z, 10)] = temp2[gpu_fieldn_index(xp1, y, zp1, 10)];
temp1[gpu_fieldn_index(x, y, z, 11)] = temp2[gpu_fieldn_index(x, ym1, zm1, 11)];
temp1[gpu_fieldn_index(x, y, z, 12)] = temp2[gpu_fieldn_index(x, yp1, zp1, 12)];
temp1[gpu_fieldn_index(x, y, z, 13)] = temp2[gpu_fieldn_index(xm1, yp1, z, 13)];
temp1[gpu_fieldn_index(x, y, z, 14)] = temp2[gpu_fieldn_index(xp1, ym1, z, 14)];
temp1[gpu_fieldn_index(x, y, z, 15)] = temp2[gpu_fieldn_index(xm1, y, zp1, 15)];
temp1[gpu_fieldn_index(x, y, z, 16)] = temp2[gpu_fieldn_index(xp1, y, zm1, 16)];
temp1[gpu_fieldn_index(x, y, z, 17)] = temp2[gpu_fieldn_index(x, ym1, zp1, 17)];
temp1[gpu_fieldn_index(x, y, z, 18)] = temp2[gpu_fieldn_index(x, yp1, zm1, 18)];
temp1[gpu_fieldn_index(x, y, z, 19)] = temp2[gpu_fieldn_index(xm1, ym1, zm1, 19)];
temp1[gpu_fieldn_index(x, y, z, 20)] = temp2[gpu_fieldn_index(xp1, yp1, zp1, 20)];
temp1[gpu_fieldn_index(x, y, z, 21)] = temp2[gpu_fieldn_index(xm1, ym1, zp1, 21)];
temp1[gpu_fieldn_index(x, y, z, 22)] = temp2[gpu_fieldn_index(xp1, yp1, zm1, 22)];
temp1[gpu_fieldn_index(x, y, z, 23)] = temp2[gpu_fieldn_index(xm1, yp1, zm1, 23)];
temp1[gpu_fieldn_index(x, y, z, 24)] = temp2[gpu_fieldn_index(xp1, ym1, zp1, 24)];
temp1[gpu_fieldn_index(x, y, z, 25)] = temp2[gpu_fieldn_index(xp1, ym1, zm1, 25)];
temp1[gpu_fieldn_index(x, y, z, 26)] = temp2[gpu_fieldn_index(xm1, yp1, zp1, 26)];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ __forceinline__ size_t gpu_fieldn_index(unsigned int x, unsigned int y, unsigned int z, unsigned int d)
{
return (NX*(NY*(NZ*(d-1)+z)+y)+x);
}
__global__ void gpu_stream(double *f0, double *f1, double *f2, double *h0, double *h1, double *h2, double *temp0, double *temp1, double *temp2)
{
unsigned int y = blockIdx.y;
unsigned int z = blockIdx.z;
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
// streaming step
unsigned int xp1 = (x + 1) % NX;
unsigned int yp1 = (y + 1) % NY;
unsigned int zp1 = (z + 1) % NZ;
unsigned int xm1 = (NX + x - 1) % NX;
unsigned int ym1 = (NY + y - 1) % NY;
unsigned int zm1 = (NZ + z - 1) % NZ;
// direction numbering scheme
// 6 2 5
// 3 0 1
// 7 4 8
// load populations from adjacent nodes (ft is post-streaming population of f1)
// flows
f1[gpu_fieldn_index(x, y, z, 1)] = f2[gpu_fieldn_index(xm1, y, z, 1)];
f1[gpu_fieldn_index(x, y, z, 2)] = f2[gpu_fieldn_index(xp1, y, z, 2)];
f1[gpu_fieldn_index(x, y, z, 3)] = f2[gpu_fieldn_index(x, ym1, z, 3)];
f1[gpu_fieldn_index(x, y, z, 4)] = f2[gpu_fieldn_index(x, yp1, z, 4)];
f1[gpu_fieldn_index(x, y, z, 5)] = f2[gpu_fieldn_index(x, y, zm1, 5)];
f1[gpu_fieldn_index(x, y, z, 6)] = f2[gpu_fieldn_index(x, y, zp1, 6)];
f1[gpu_fieldn_index(x, y, z, 7)] = f2[gpu_fieldn_index(xm1, ym1, z, 7)];
f1[gpu_fieldn_index(x, y, z, 8)] = f2[gpu_fieldn_index(xp1, yp1, z, 8)];
f1[gpu_fieldn_index(x, y, z, 9)] = f2[gpu_fieldn_index(xm1, y, zm1, 9)];
f1[gpu_fieldn_index(x, y, z, 10)] = f2[gpu_fieldn_index(xp1, y, zp1, 10)];
f1[gpu_fieldn_index(x, y, z, 11)] = f2[gpu_fieldn_index(x, ym1, zm1, 11)];
f1[gpu_fieldn_index(x, y, z, 12)] = f2[gpu_fieldn_index(x, yp1, zp1, 12)];
f1[gpu_fieldn_index(x, y, z, 13)] = f2[gpu_fieldn_index(xm1, yp1, z, 13)];
f1[gpu_fieldn_index(x, y, z, 14)] = f2[gpu_fieldn_index(xp1, ym1, z, 14)];
f1[gpu_fieldn_index(x, y, z, 15)] = f2[gpu_fieldn_index(xm1, y, zp1, 15)];
f1[gpu_fieldn_index(x, y, z, 16)] = f2[gpu_fieldn_index(xp1, y, zm1, 16)];
f1[gpu_fieldn_index(x, y, z, 17)] = f2[gpu_fieldn_index(x, ym1, zp1, 17)];
f1[gpu_fieldn_index(x, y, z, 18)] = f2[gpu_fieldn_index(x, yp1, zm1, 18)];
f1[gpu_fieldn_index(x, y, z, 19)] = f2[gpu_fieldn_index(xm1, ym1, zm1, 19)];
f1[gpu_fieldn_index(x, y, z, 20)] = f2[gpu_fieldn_index(xp1, yp1, zp1, 20)];
f1[gpu_fieldn_index(x, y, z, 21)] = f2[gpu_fieldn_index(xm1, ym1, zp1, 21)];
f1[gpu_fieldn_index(x, y, z, 22)] = f2[gpu_fieldn_index(xp1, yp1, zm1, 22)];
f1[gpu_fieldn_index(x, y, z, 23)] = f2[gpu_fieldn_index(xm1, yp1, zm1, 23)];
f1[gpu_fieldn_index(x, y, z, 24)] = f2[gpu_fieldn_index(xp1, ym1, zp1, 24)];
f1[gpu_fieldn_index(x, y, z, 25)] = f2[gpu_fieldn_index(xp1, ym1, zm1, 25)];
f1[gpu_fieldn_index(x, y, z, 26)] = f2[gpu_fieldn_index(xm1, yp1, zp1, 26)];
// charges
h1[gpu_fieldn_index(x, y, z, 1)] = h2[gpu_fieldn_index(xm1, y, z, 1)];
h1[gpu_fieldn_index(x, y, z, 2)] = h2[gpu_fieldn_index(xp1, y, z, 2)];
h1[gpu_fieldn_index(x, y, z, 3)] = h2[gpu_fieldn_index(x, ym1, z, 3)];
h1[gpu_fieldn_index(x, y, z, 4)] = h2[gpu_fieldn_index(x, yp1, z, 4)];
h1[gpu_fieldn_index(x, y, z, 5)] = h2[gpu_fieldn_index(x, y, zm1, 5)];
h1[gpu_fieldn_index(x, y, z, 6)] = h2[gpu_fieldn_index(x, y, zp1, 6)];
h1[gpu_fieldn_index(x, y, z, 7)] = h2[gpu_fieldn_index(xm1, ym1, z, 7)];
h1[gpu_fieldn_index(x, y, z, 8)] = h2[gpu_fieldn_index(xp1, yp1, z, 8)];
h1[gpu_fieldn_index(x, y, z, 9)] = h2[gpu_fieldn_index(xm1, y, zm1, 9)];
h1[gpu_fieldn_index(x, y, z, 10)] = h2[gpu_fieldn_index(xp1, y, zp1, 10)];
h1[gpu_fieldn_index(x, y, z, 11)] = h2[gpu_fieldn_index(x, ym1, zm1, 11)];
h1[gpu_fieldn_index(x, y, z, 12)] = h2[gpu_fieldn_index(x, yp1, zp1, 12)];
h1[gpu_fieldn_index(x, y, z, 13)] = h2[gpu_fieldn_index(xm1, yp1, z, 13)];
h1[gpu_fieldn_index(x, y, z, 14)] = h2[gpu_fieldn_index(xp1, ym1, z, 14)];
h1[gpu_fieldn_index(x, y, z, 15)] = h2[gpu_fieldn_index(xm1, y, zp1, 15)];
h1[gpu_fieldn_index(x, y, z, 16)] = h2[gpu_fieldn_index(xp1, y, zm1, 16)];
h1[gpu_fieldn_index(x, y, z, 17)] = h2[gpu_fieldn_index(x, ym1, zp1, 17)];
h1[gpu_fieldn_index(x, y, z, 18)] = h2[gpu_fieldn_index(x, yp1, zm1, 18)];
h1[gpu_fieldn_index(x, y, z, 19)] = h2[gpu_fieldn_index(xm1, ym1, zm1, 19)];
h1[gpu_fieldn_index(x, y, z, 20)] = h2[gpu_fieldn_index(xp1, yp1, zp1, 20)];
h1[gpu_fieldn_index(x, y, z, 21)] = h2[gpu_fieldn_index(xm1, ym1, zp1, 21)];
h1[gpu_fieldn_index(x, y, z, 22)] = h2[gpu_fieldn_index(xp1, yp1, zm1, 22)];
h1[gpu_fieldn_index(x, y, z, 23)] = h2[gpu_fieldn_index(xm1, yp1, zm1, 23)];
h1[gpu_fieldn_index(x, y, z, 24)] = h2[gpu_fieldn_index(xp1, ym1, zp1, 24)];
h1[gpu_fieldn_index(x, y, z, 25)] = h2[gpu_fieldn_index(xp1, ym1, zm1, 25)];
h1[gpu_fieldn_index(x, y, z, 26)] = h2[gpu_fieldn_index(xm1, yp1, zp1, 26)];
// temperature
temp1[gpu_fieldn_index(x, y, z, 1)] = temp2[gpu_fieldn_index(xm1, y, z, 1)];
temp1[gpu_fieldn_index(x, y, z, 2)] = temp2[gpu_fieldn_index(xp1, y, z, 2)];
temp1[gpu_fieldn_index(x, y, z, 3)] = temp2[gpu_fieldn_index(x, ym1, z, 3)];
temp1[gpu_fieldn_index(x, y, z, 4)] = temp2[gpu_fieldn_index(x, yp1, z, 4)];
temp1[gpu_fieldn_index(x, y, z, 5)] = temp2[gpu_fieldn_index(x, y, zm1, 5)];
temp1[gpu_fieldn_index(x, y, z, 6)] = temp2[gpu_fieldn_index(x, y, zp1, 6)];
temp1[gpu_fieldn_index(x, y, z, 7)] = temp2[gpu_fieldn_index(xm1, ym1, z, 7)];
temp1[gpu_fieldn_index(x, y, z, 8)] = temp2[gpu_fieldn_index(xp1, yp1, z, 8)];
temp1[gpu_fieldn_index(x, y, z, 9)] = temp2[gpu_fieldn_index(xm1, y, zm1, 9)];
temp1[gpu_fieldn_index(x, y, z, 10)] = temp2[gpu_fieldn_index(xp1, y, zp1, 10)];
temp1[gpu_fieldn_index(x, y, z, 11)] = temp2[gpu_fieldn_index(x, ym1, zm1, 11)];
temp1[gpu_fieldn_index(x, y, z, 12)] = temp2[gpu_fieldn_index(x, yp1, zp1, 12)];
temp1[gpu_fieldn_index(x, y, z, 13)] = temp2[gpu_fieldn_index(xm1, yp1, z, 13)];
temp1[gpu_fieldn_index(x, y, z, 14)] = temp2[gpu_fieldn_index(xp1, ym1, z, 14)];
temp1[gpu_fieldn_index(x, y, z, 15)] = temp2[gpu_fieldn_index(xm1, y, zp1, 15)];
temp1[gpu_fieldn_index(x, y, z, 16)] = temp2[gpu_fieldn_index(xp1, y, zm1, 16)];
temp1[gpu_fieldn_index(x, y, z, 17)] = temp2[gpu_fieldn_index(x, ym1, zp1, 17)];
temp1[gpu_fieldn_index(x, y, z, 18)] = temp2[gpu_fieldn_index(x, yp1, zm1, 18)];
temp1[gpu_fieldn_index(x, y, z, 19)] = temp2[gpu_fieldn_index(xm1, ym1, zm1, 19)];
temp1[gpu_fieldn_index(x, y, z, 20)] = temp2[gpu_fieldn_index(xp1, yp1, zp1, 20)];
temp1[gpu_fieldn_index(x, y, z, 21)] = temp2[gpu_fieldn_index(xm1, ym1, zp1, 21)];
temp1[gpu_fieldn_index(x, y, z, 22)] = temp2[gpu_fieldn_index(xp1, yp1, zm1, 22)];
temp1[gpu_fieldn_index(x, y, z, 23)] = temp2[gpu_fieldn_index(xm1, yp1, zm1, 23)];
temp1[gpu_fieldn_index(x, y, z, 24)] = temp2[gpu_fieldn_index(xp1, ym1, zp1, 24)];
temp1[gpu_fieldn_index(x, y, z, 25)] = temp2[gpu_fieldn_index(xp1, ym1, zm1, 25)];
temp1[gpu_fieldn_index(x, y, z, 26)] = temp2[gpu_fieldn_index(xm1, yp1, zp1, 26)];
} | .text
.file "gpu_stream.hip"
.globl _Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_ # -- Begin function _Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_,@function
_Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_: # @_Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10gpu_streamPdS_S_S_S_S_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10gpu_streamPdS_S_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10gpu_streamPdS_S_S_S_S_S_S_S_,@object # @_Z10gpu_streamPdS_S_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z10gpu_streamPdS_S_S_S_S_S_S_S_
.p2align 3, 0x0
_Z10gpu_streamPdS_S_S_S_S_S_S_S_:
.quad _Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_
.size _Z10gpu_streamPdS_S_S_S_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10gpu_streamPdS_S_S_S_S_S_S_S_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10gpu_streamPdS_S_S_S_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00090441_00000000-6_gpu_stream.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z10gpu_streamPdS_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_
.type _Z46__device_stub__Z10gpu_streamPdS_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_, @function
_Z46__device_stub__Z10gpu_streamPdS_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 248
pushq 88(%rsp)
.cfi_def_cfa_offset 256
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z10gpu_streamPdS_S_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z46__device_stub__Z10gpu_streamPdS_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_, .-_Z46__device_stub__Z10gpu_streamPdS_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_
.globl _Z10gpu_streamPdS_S_S_S_S_S_S_S_
.type _Z10gpu_streamPdS_S_S_S_S_S_S_S_, @function
_Z10gpu_streamPdS_S_S_S_S_S_S_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z46__device_stub__Z10gpu_streamPdS_S_S_S_S_S_S_S_PdS_S_S_S_S_S_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10gpu_streamPdS_S_S_S_S_S_S_S_, .-_Z10gpu_streamPdS_S_S_S_S_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10gpu_streamPdS_S_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10gpu_streamPdS_S_S_S_S_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_stream.hip"
.globl _Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_ # -- Begin function _Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_,@function
_Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_: # @_Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10gpu_streamPdS_S_S_S_S_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10gpu_streamPdS_S_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10gpu_streamPdS_S_S_S_S_S_S_S_,@object # @_Z10gpu_streamPdS_S_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z10gpu_streamPdS_S_S_S_S_S_S_S_
.p2align 3, 0x0
_Z10gpu_streamPdS_S_S_S_S_S_S_S_:
.quad _Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_
.size _Z10gpu_streamPdS_S_S_S_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10gpu_streamPdS_S_S_S_S_S_S_S_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__gpu_streamPdS_S_S_S_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10gpu_streamPdS_S_S_S_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void mul(int * A, int * B, int * C){
int i = blockIdx.x;
int j = threadIdx.x;
C[i * N + j] = 0;
for (int k = 0; k < N; k++){
C[i * N + j] += A[i * N + k] * B[k * N + j];
}
} | code for sm_80
Function : _Z3mulPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ IMAD.SHL.U32 R5, R5, 0x800000, RZ ; /* 0x0080000005057824 */
/* 0x001fc800078e00ff */
/*0070*/ IMAD.IADD R2, R5, 0x1, R0 ; /* 0x0000000105027824 */
/* 0x002fe400078e0200 */
/*0080*/ IMAD.WIDE R8, R0, R7, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R2, R7, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0207 */
/*00a0*/ IMAD.WIDE R6, R5, R7, c[0x0][0x160] ; /* 0x0000580005067625 */
/* 0x000fe200078e0207 */
/*00b0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101906 */
/*00c0*/ LDG.E R4, [R8.64] ; /* 0x0000000608047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R13, [R6.64] ; /* 0x00000006060d7981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IADD3 R10, P0, R8, 0x2000000, RZ ; /* 0x02000000080a7810 */
/* 0x000fc80007f1e0ff */
/*00f0*/ IADD3.X R11, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff0b7210 */
/* 0x000fe200007fe4ff */
/*0100*/ IMAD R17, R4, R13, RZ ; /* 0x0000000d04117224 */
/* 0x004fca00078e02ff */
/*0110*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e8000c101906 */
/*0120*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R4, [R6.64+0x4] ; /* 0x0000040606047981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IADD3 R12, P0, R8, 0x4000000, RZ ; /* 0x04000000080c7810 */
/* 0x000fca0007f1e0ff */
/*0150*/ IMAD.X R13, RZ, RZ, R9, P0 ; /* 0x000000ffff0d7224 */
/* 0x000fe400000e0609 */
/*0160*/ IMAD R19, R10, R4, R17 ; /* 0x000000040a137224 */
/* 0x004fca00078e0211 */
/*0170*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101906 */
/*0180*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000e28000c1e1900 */
/*0190*/ LDG.E R4, [R6.64+0x8] ; /* 0x0000080606047981 */
/* 0x000e22000c1e1900 */
/*01a0*/ IADD3 R14, P0, R8, 0x6000000, RZ ; /* 0x06000000080e7810 */
/* 0x000fc80007f1e0ff */
/*01b0*/ IADD3.X R15, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff0f7210 */
/* 0x000fe200007fe4ff */
/*01c0*/ IMAD R17, R12, R4, R19 ; /* 0x000000040c117224 */
/* 0x001fca00078e0213 */
/*01d0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e8000c101906 */
/*01e0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000e68000c1e1900 */
/*01f0*/ LDG.E R4, [R6.64+0xc] ; /* 0x00000c0606047981 */
/* 0x000e62000c1e1900 */
/*0200*/ IADD3 R10, P0, R8, 0x8000000, RZ ; /* 0x08000000080a7810 */
/* 0x000fca0007f1e0ff */
/*0210*/ IMAD.X R11, RZ, RZ, R9, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe400000e0609 */
/*0220*/ IMAD R19, R14, R4, R17 ; /* 0x000000040e137224 */
/* 0x002fca00078e0211 */
/*0230*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101906 */
/*0240*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000e28000c1e1900 */
/*0250*/ LDG.E R4, [R6.64+0x10] ; /* 0x0000100606047981 */
/* 0x000e22000c1e1900 */
/*0260*/ IADD3 R12, P0, R8, 0xa000000, RZ ; /* 0x0a000000080c7810 */
/* 0x000fc80007f1e0ff */
/*0270*/ IADD3.X R13, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff0d7210 */
/* 0x000fe200007fe4ff */
/*0280*/ IMAD R17, R10, R4, R19 ; /* 0x000000040a117224 */
/* 0x001fca00078e0213 */
/*0290*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e8000c101906 */
/*02a0*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000e68000c1e1900 */
/*02b0*/ LDG.E R4, [R6.64+0x14] ; /* 0x0000140606047981 */
/* 0x000e62000c1e1900 */
/*02c0*/ IADD3 R14, P0, R8, 0xc000000, RZ ; /* 0x0c000000080e7810 */
/* 0x000fca0007f1e0ff */
/*02d0*/ IMAD.X R15, RZ, RZ, R9, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400000e0609 */
/*02e0*/ IMAD R19, R12, R4, R17 ; /* 0x000000040c137224 */
/* 0x002fca00078e0211 */
/*02f0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe8000c101906 */
/*0300*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea8000c1e1900 */
/*0310*/ LDG.E R4, [R6.64+0x18] ; /* 0x0000180606047981 */
/* 0x000ea2000c1e1900 */
/*0320*/ IADD3 R8, P0, R8, 0xe000000, RZ ; /* 0x0e00000008087810 */
/* 0x000fc80007f1e0ff */
/*0330*/ IADD3.X R9, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff097210 */
/* 0x000fe200007fe4ff */
/*0340*/ IMAD R11, R14, R4, R19 ; /* 0x000000040e0b7224 */
/* 0x004fca00078e0213 */
/*0350*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101906 */
/*0360*/ LDG.E R17, [R6.64+0x1c] ; /* 0x00001c0606117981 */
/* 0x001ea8000c1e1900 */
/*0370*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0a7624 */
/* 0x000fe200078e00ff */
/*0390*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x000fe200000001ff */
/*03a0*/ UIADD3 UR4, UP0, UR4, 0x10000000, URZ ; /* 0x1000000004047890 */
/* 0x000fc6000ff1e03f */
/*03b0*/ IADD3 R10, P0, R10, 0x20, RZ ; /* 0x000000200a0a7810 */
/* 0x000fe20007f1e0ff */
/*03c0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*03d0*/ IMAD R17, R8, R17, R11 ; /* 0x0000001108117224 */
/* 0x004fc600078e020b */
/*03e0*/ IMAD.X R11, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0b7624 */
/* 0x002fe400000e06ff */
/*03f0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e8000c101906 */
/*0400*/ MOV R8, UR4 ; /* 0x0000000400087c02 */
/* 0x000fe20008000f00 */
/*0410*/ IMAD.U32 R9, RZ, RZ, UR5 ; /* 0x00000005ff097e24 */
/* 0x000fe4000f8e00ff */
/*0420*/ IMAD.WIDE R6, R5, 0x4, R10 ; /* 0x0000000405067825 */
/* 0x000fc800078e020a */
/*0430*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x000fe200078e0208 */
/*0440*/ LDG.E R15, [R6.64] ; /* 0x00000006060f7981 */
/* 0x000ea8000c1e1900 */
/*0450*/ LDG.E R14, [R8.64] ; /* 0x00000006080e7981 */
/* 0x000ea2000c1e1900 */
/*0460*/ IADD3 R12, P0, R8, 0x2000000, RZ ; /* 0x02000000080c7810 */
/* 0x000fc80007f1e0ff */
/*0470*/ IADD3.X R13, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff0d7210 */
/* 0x000fe200007fe4ff */
/*0480*/ IMAD R19, R14, R15, R17 ; /* 0x0000000f0e137224 */
/* 0x005fca00078e0211 */
/*0490*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101906 */
/*04a0*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R16, [R6.64+0x4] ; /* 0x0000040606107981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ IADD3 R14, P0, R8, 0x4000000, RZ ; /* 0x04000000080e7810 */
/* 0x000fca0007f1e0ff */
/*04d0*/ IMAD.X R15, RZ, RZ, R9, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400000e0609 */
/*04e0*/ IMAD R21, R12, R16, R19 ; /* 0x000000100c157224 */
/* 0x004fca00078e0213 */
/*04f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101906 */
/*0500*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000e68000c1e1900 */
/*0510*/ LDG.E R18, [R6.64+0x8] ; /* 0x0000080606127981 */
/* 0x000e62000c1e1900 */
/*0520*/ IADD3 R16, P0, R8, 0x6000000, RZ ; /* 0x0600000008107810 */
/* 0x000fc80007f1e0ff */
/*0530*/ IADD3.X R17, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff117210 */
/* 0x001fe200007fe4ff */
/*0540*/ IMAD R19, R14, R18, R21 ; /* 0x000000120e137224 */
/* 0x002fca00078e0215 */
/*0550*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0560*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R18, [R6.64+0xc] ; /* 0x00000c0606127981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IADD3 R12, P0, R8, 0x8000000, RZ ; /* 0x08000000080c7810 */
/* 0x000fca0007f1e0ff */
/*0590*/ IMAD.X R13, RZ, RZ, R9, P0 ; /* 0x000000ffff0d7224 */
/* 0x000fe400000e0609 */
/*05a0*/ IMAD R21, R16, R18, R19 ; /* 0x0000001210157224 */
/* 0x004fca00078e0213 */
/*05b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101906 */
/*05c0*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000e28000c1e1900 */
/*05d0*/ LDG.E R18, [R6.64+0x10] ; /* 0x0000100606127981 */
/* 0x000e22000c1e1900 */
/*05e0*/ IADD3 R14, P0, R8, 0xa000000, RZ ; /* 0x0a000000080e7810 */
/* 0x000fc80007f1e0ff */
/*05f0*/ IADD3.X R15, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff0f7210 */
/* 0x000fe200007fe4ff */
/*0600*/ IMAD R19, R12, R18, R21 ; /* 0x000000120c137224 */
/* 0x001fca00078e0215 */
/*0610*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0620*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000e68000c1e1900 */
/*0630*/ LDG.E R18, [R6.64+0x14] ; /* 0x0000140606127981 */
/* 0x000e62000c1e1900 */
/*0640*/ IADD3 R16, P0, R8, 0xc000000, RZ ; /* 0x0c00000008107810 */
/* 0x000fca0007f1e0ff */
/*0650*/ IMAD.X R17, RZ, RZ, R9, P0 ; /* 0x000000ffff117224 */
/* 0x000fe400000e0609 */
/*0660*/ IMAD R21, R14, R18, R19 ; /* 0x000000120e157224 */
/* 0x002fca00078e0213 */
/*0670*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101906 */
/*0680*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000e28000c1e1900 */
/*0690*/ LDG.E R18, [R6.64+0x18] ; /* 0x0000180606127981 */
/* 0x000e22000c1e1900 */
/*06a0*/ IADD3 R12, P0, R8, 0xe000000, RZ ; /* 0x0e000000080c7810 */
/* 0x000fc80007f1e0ff */
/*06b0*/ IADD3.X R13, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff0d7210 */
/* 0x000fe200007fe4ff */
/*06c0*/ IMAD R19, R16, R18, R21 ; /* 0x0000001210137224 */
/* 0x001fca00078e0215 */
/*06d0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*06e0*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000e68000c1e1900 */
/*06f0*/ LDG.E R18, [R6.64+0x1c] ; /* 0x00001c0606127981 */
/* 0x000e62000c1e1900 */
/*0700*/ IADD3 R14, P0, R8, 0x10000000, RZ ; /* 0x10000000080e7810 */
/* 0x000fca0007f1e0ff */
/*0710*/ IMAD.X R15, RZ, RZ, R9, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400000e0609 */
/*0720*/ IMAD R21, R12, R18, R19 ; /* 0x000000120c157224 */
/* 0x002fca00078e0213 */
/*0730*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101906 */
/*0740*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000e28000c1e1900 */
/*0750*/ LDG.E R18, [R6.64+0x20] ; /* 0x0000200606127981 */
/* 0x000e22000c1e1900 */
/*0760*/ IADD3 R16, P0, R8, 0x12000000, RZ ; /* 0x1200000008107810 */
/* 0x000fc80007f1e0ff */
/*0770*/ IADD3.X R17, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff117210 */
/* 0x000fe200007fe4ff */
/*0780*/ IMAD R19, R14, R18, R21 ; /* 0x000000120e137224 */
/* 0x001fca00078e0215 */
/*0790*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*07a0*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000e68000c1e1900 */
/*07b0*/ LDG.E R18, [R6.64+0x24] ; /* 0x0000240606127981 */
/* 0x000e62000c1e1900 */
/*07c0*/ IADD3 R12, P0, R8, 0x14000000, RZ ; /* 0x14000000080c7810 */
/* 0x000fca0007f1e0ff */
/*07d0*/ IMAD.X R13, RZ, RZ, R9, P0 ; /* 0x000000ffff0d7224 */
/* 0x000fe400000e0609 */
/*07e0*/ IMAD R21, R16, R18, R19 ; /* 0x0000001210157224 */
/* 0x002fca00078e0213 */
/*07f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101906 */
/*0800*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000e28000c1e1900 */
/*0810*/ LDG.E R18, [R6.64+0x28] ; /* 0x0000280606127981 */
/* 0x000e22000c1e1900 */
/*0820*/ IADD3 R14, P0, R8, 0x16000000, RZ ; /* 0x16000000080e7810 */
/* 0x000fc80007f1e0ff */
/*0830*/ IADD3.X R15, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff0f7210 */
/* 0x000fe200007fe4ff */
/*0840*/ IMAD R19, R12, R18, R21 ; /* 0x000000120c137224 */
/* 0x001fca00078e0215 */
/*0850*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0860*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000e68000c1e1900 */
/*0870*/ LDG.E R18, [R6.64+0x2c] ; /* 0x00002c0606127981 */
/* 0x000e62000c1e1900 */
/*0880*/ IADD3 R16, P0, R8, 0x18000000, RZ ; /* 0x1800000008107810 */
/* 0x000fca0007f1e0ff */
/*0890*/ IMAD.X R17, RZ, RZ, R9, P0 ; /* 0x000000ffff117224 */
/* 0x000fe400000e0609 */
/*08a0*/ IMAD R21, R14, R18, R19 ; /* 0x000000120e157224 */
/* 0x002fca00078e0213 */
/*08b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101906 */
/*08c0*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000e28000c1e1900 */
/*08d0*/ LDG.E R18, [R6.64+0x30] ; /* 0x0000300606127981 */
/* 0x000e22000c1e1900 */
/*08e0*/ IADD3 R12, P0, R8, 0x1a000000, RZ ; /* 0x1a000000080c7810 */
/* 0x000fc80007f1e0ff */
/*08f0*/ IADD3.X R13, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff0d7210 */
/* 0x000fe200007fe4ff */
/*0900*/ IMAD R19, R16, R18, R21 ; /* 0x0000001210137224 */
/* 0x001fca00078e0215 */
/*0910*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0920*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000e68000c1e1900 */
/*0930*/ LDG.E R18, [R6.64+0x34] ; /* 0x0000340606127981 */
/* 0x000e62000c1e1900 */
/*0940*/ IADD3 R14, P0, R8, 0x1c000000, RZ ; /* 0x1c000000080e7810 */
/* 0x000fca0007f1e0ff */
/*0950*/ IMAD.X R15, RZ, RZ, R9, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400000e0609 */
/*0960*/ IMAD R21, R12, R18, R19 ; /* 0x000000120c157224 */
/* 0x002fca00078e0213 */
/*0970*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101906 */
/*0980*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000e28000c1e1900 */
/*0990*/ LDG.E R18, [R6.64+0x38] ; /* 0x0000380606127981 */
/* 0x000e22000c1e1900 */
/*09a0*/ IADD3 R16, P0, R8, 0x1e000000, RZ ; /* 0x1e00000008107810 */
/* 0x000fc80007f1e0ff */
/*09b0*/ IADD3.X R17, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff117210 */
/* 0x000fe200007fe4ff */
/*09c0*/ IMAD R19, R14, R18, R21 ; /* 0x000000120e137224 */
/* 0x001fca00078e0215 */
/*09d0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*09e0*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000e68000c1e1900 */
/*09f0*/ LDG.E R18, [R6.64+0x3c] ; /* 0x00003c0606127981 */
/* 0x000e62000c1e1900 */
/*0a00*/ IADD3 R12, P0, R8, 0x20000000, RZ ; /* 0x20000000080c7810 */
/* 0x000fca0007f1e0ff */
/*0a10*/ IMAD.X R13, RZ, RZ, R9, P0 ; /* 0x000000ffff0d7224 */
/* 0x000fe400000e0609 */
/*0a20*/ IMAD R21, R16, R18, R19 ; /* 0x0000001210157224 */
/* 0x002fca00078e0213 */
/*0a30*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101906 */
/*0a40*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000e28000c1e1900 */
/*0a50*/ LDG.E R18, [R6.64+0x40] ; /* 0x0000400606127981 */
/* 0x000e22000c1e1900 */
/*0a60*/ IADD3 R14, P0, R8, 0x22000000, RZ ; /* 0x22000000080e7810 */
/* 0x000fc80007f1e0ff */
/*0a70*/ IADD3.X R15, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff0f7210 */
/* 0x000fe200007fe4ff */
/*0a80*/ IMAD R19, R12, R18, R21 ; /* 0x000000120c137224 */
/* 0x001fca00078e0215 */
/*0a90*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0aa0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000e68000c1e1900 */
/*0ab0*/ LDG.E R18, [R6.64+0x44] ; /* 0x0000440606127981 */
/* 0x000e62000c1e1900 */
/*0ac0*/ IADD3 R16, P0, R8, 0x24000000, RZ ; /* 0x2400000008107810 */
/* 0x000fca0007f1e0ff */
/*0ad0*/ IMAD.X R17, RZ, RZ, R9, P0 ; /* 0x000000ffff117224 */
/* 0x000fe400000e0609 */
/*0ae0*/ IMAD R21, R14, R18, R19 ; /* 0x000000120e157224 */
/* 0x002fca00078e0213 */
/*0af0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101906 */
/*0b00*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000e28000c1e1900 */
/*0b10*/ LDG.E R18, [R6.64+0x48] ; /* 0x0000480606127981 */
/* 0x000e22000c1e1900 */
/*0b20*/ IADD3 R12, P0, R8, 0x26000000, RZ ; /* 0x26000000080c7810 */
/* 0x000fc80007f1e0ff */
/*0b30*/ IADD3.X R13, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff0d7210 */
/* 0x000fe200007fe4ff */
/*0b40*/ IMAD R19, R16, R18, R21 ; /* 0x0000001210137224 */
/* 0x001fca00078e0215 */
/*0b50*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0b60*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000e68000c1e1900 */
/*0b70*/ LDG.E R18, [R6.64+0x4c] ; /* 0x00004c0606127981 */
/* 0x000e62000c1e1900 */
/*0b80*/ IADD3 R14, P0, R8, 0x28000000, RZ ; /* 0x28000000080e7810 */
/* 0x000fca0007f1e0ff */
/*0b90*/ IMAD.X R15, RZ, RZ, R9, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400000e0609 */
/*0ba0*/ IMAD R21, R12, R18, R19 ; /* 0x000000120c157224 */
/* 0x002fca00078e0213 */
/*0bb0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101906 */
/*0bc0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000e28000c1e1900 */
/*0bd0*/ LDG.E R18, [R6.64+0x50] ; /* 0x0000500606127981 */
/* 0x000e22000c1e1900 */
/*0be0*/ IADD3 R16, P0, R8, 0x2a000000, RZ ; /* 0x2a00000008107810 */
/* 0x000fc80007f1e0ff */
/*0bf0*/ IADD3.X R17, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff117210 */
/* 0x000fe200007fe4ff */
/*0c00*/ IMAD R19, R14, R18, R21 ; /* 0x000000120e137224 */
/* 0x001fca00078e0215 */
/*0c10*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0c20*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000e68000c1e1900 */
/*0c30*/ LDG.E R18, [R6.64+0x54] ; /* 0x0000540606127981 */
/* 0x000e62000c1e1900 */
/*0c40*/ IADD3 R12, P0, R8, 0x2c000000, RZ ; /* 0x2c000000080c7810 */
/* 0x000fca0007f1e0ff */
/*0c50*/ IMAD.X R13, RZ, RZ, R9, P0 ; /* 0x000000ffff0d7224 */
/* 0x000fe400000e0609 */
/*0c60*/ IMAD R21, R16, R18, R19 ; /* 0x0000001210157224 */
/* 0x002fca00078e0213 */
/*0c70*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101906 */
/*0c80*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000e28000c1e1900 */
/*0c90*/ LDG.E R18, [R6.64+0x58] ; /* 0x0000580606127981 */
/* 0x000e22000c1e1900 */
/*0ca0*/ IADD3 R14, P0, R8, 0x2e000000, RZ ; /* 0x2e000000080e7810 */
/* 0x000fc80007f1e0ff */
/*0cb0*/ IADD3.X R15, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff0f7210 */
/* 0x000fe200007fe4ff */
/*0cc0*/ IMAD R19, R12, R18, R21 ; /* 0x000000120c137224 */
/* 0x001fca00078e0215 */
/*0cd0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0ce0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000e68000c1e1900 */
/*0cf0*/ LDG.E R18, [R6.64+0x5c] ; /* 0x00005c0606127981 */
/* 0x000e62000c1e1900 */
/*0d00*/ IADD3 R16, P0, R8, 0x30000000, RZ ; /* 0x3000000008107810 */
/* 0x000fca0007f1e0ff */
/*0d10*/ IMAD.X R17, RZ, RZ, R9, P0 ; /* 0x000000ffff117224 */
/* 0x000fe400000e0609 */
/*0d20*/ IMAD R21, R14, R18, R19 ; /* 0x000000120e157224 */
/* 0x002fca00078e0213 */
/*0d30*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101906 */
/*0d40*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000e28000c1e1900 */
/*0d50*/ LDG.E R18, [R6.64+0x60] ; /* 0x0000600606127981 */
/* 0x000e22000c1e1900 */
/*0d60*/ IADD3 R12, P0, R8, 0x32000000, RZ ; /* 0x32000000080c7810 */
/* 0x000fc80007f1e0ff */
/*0d70*/ IADD3.X R13, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff0d7210 */
/* 0x000fe200007fe4ff */
/*0d80*/ IMAD R19, R16, R18, R21 ; /* 0x0000001210137224 */
/* 0x001fca00078e0215 */
/*0d90*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0da0*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000e68000c1e1900 */
/*0db0*/ LDG.E R18, [R6.64+0x64] ; /* 0x0000640606127981 */
/* 0x000e62000c1e1900 */
/*0dc0*/ IADD3 R14, P0, R8, 0x34000000, RZ ; /* 0x34000000080e7810 */
/* 0x000fca0007f1e0ff */
/*0dd0*/ IMAD.X R15, RZ, RZ, R9, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400000e0609 */
/*0de0*/ IMAD R21, R12, R18, R19 ; /* 0x000000120c157224 */
/* 0x002fca00078e0213 */
/*0df0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101906 */
/*0e00*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000e28000c1e1900 */
/*0e10*/ LDG.E R18, [R6.64+0x68] ; /* 0x0000680606127981 */
/* 0x000e22000c1e1900 */
/*0e20*/ IADD3 R16, P0, R8, 0x36000000, RZ ; /* 0x3600000008107810 */
/* 0x000fc80007f1e0ff */
/*0e30*/ IADD3.X R17, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff117210 */
/* 0x000fe200007fe4ff */
/*0e40*/ IMAD R19, R14, R18, R21 ; /* 0x000000120e137224 */
/* 0x001fca00078e0215 */
/*0e50*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*0e60*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000e68000c1e1900 */
/*0e70*/ LDG.E R18, [R6.64+0x6c] ; /* 0x00006c0606127981 */
/* 0x000e62000c1e1900 */
/*0e80*/ IADD3 R12, P0, R8, 0x38000000, RZ ; /* 0x38000000080c7810 */
/* 0x000fca0007f1e0ff */
/*0e90*/ IMAD.X R13, RZ, RZ, R9, P0 ; /* 0x000000ffff0d7224 */
/* 0x000fe400000e0609 */
/*0ea0*/ IMAD R21, R16, R18, R19 ; /* 0x0000001210157224 */
/* 0x002fca00078e0213 */
/*0eb0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101906 */
/*0ec0*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000e28000c1e1900 */
/*0ed0*/ LDG.E R18, [R6.64+0x70] ; /* 0x0000700606127981 */
/* 0x000e22000c1e1900 */
/*0ee0*/ IADD3 R14, P0, R8, 0x3a000000, RZ ; /* 0x3a000000080e7810 */
/* 0x000fc80007f1e0ff */
/*0ef0*/ IADD3.X R15, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff0f7210 */
/* 0x000fe200007fe4ff */
/*0f00*/ IMAD R19, R12, R18, R21 ; /* 0x000000120c137224 */
/* 0x001fca00078e0215 */
/*0f10*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe8000c101906 */
/*0f20*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000e68000c1e1900 */
/*0f30*/ LDG.E R18, [R6.64+0x74] ; /* 0x0000740606127981 */
/* 0x000e62000c1e1900 */
/*0f40*/ IADD3 R16, P0, R8, 0x3c000000, RZ ; /* 0x3c00000008107810 */
/* 0x000fca0007f1e0ff */
/*0f50*/ IMAD.X R17, RZ, RZ, R9, P0 ; /* 0x000000ffff117224 */
/* 0x000fe400000e0609 */
/*0f60*/ IMAD R21, R14, R18, R19 ; /* 0x000000120e157224 */
/* 0x002fca00078e0213 */
/*0f70*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101906 */
/*0f80*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000ea8000c1e1900 */
/*0f90*/ LDG.E R18, [R6.64+0x78] ; /* 0x0000780606127981 */
/* 0x000ea2000c1e1900 */
/*0fa0*/ IADD3 R12, P0, R8, 0x3e000000, RZ ; /* 0x3e000000080c7810 */
/* 0x000fc80007f1e0ff */
/*0fb0*/ IADD3.X R13, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff0d7210 */
/* 0x000fe200007fe4ff */
/*0fc0*/ IMAD R23, R16, R18, R21 ; /* 0x0000001210177224 */
/* 0x004fca00078e0215 */
/*0fd0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe8000c101906 */
/*0fe0*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000e28000c1e1900 */
/*0ff0*/ LDG.E R18, [R6.64+0x7c] ; /* 0x00007c0606127981 */
/* 0x000e22000c1e1900 */
/*1000*/ IADD3 R14, P0, R8, 0x40000000, RZ ; /* 0x40000000080e7810 */
/* 0x000fca0007f1e0ff */
/*1010*/ IMAD.X R15, RZ, RZ, R9, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400000e0609 */
/*1020*/ IMAD R21, R12, R18, R23 ; /* 0x000000120c157224 */
/* 0x001fca00078e0217 */
/*1030*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101906 */
/*1040*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea8000c1e1900 */
/*1050*/ LDG.E R19, [R6.64+0x80] ; /* 0x0000800606137981 */
/* 0x000ea2000c1e1900 */
/*1060*/ IADD3 R16, P0, R8, 0x42000000, RZ ; /* 0x4200000008107810 */
/* 0x000fc80007f1e0ff */
/*1070*/ IADD3.X R17, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff117210 */
/* 0x000fe200007fe4ff */
/*1080*/ IMAD R19, R14, R19, R21 ; /* 0x000000130e137224 */
/* 0x004fca00078e0215 */
/*1090*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101906 */
/*10a0*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000e28000c1e1900 */
/*10b0*/ LDG.E R18, [R6.64+0x84] ; /* 0x0000840606127981 */
/* 0x000e22000c1e1900 */
/*10c0*/ IADD3 R12, P0, R8, 0x44000000, RZ ; /* 0x44000000080c7810 */
/* 0x000fc80007f1e0ff */
/*10d0*/ IADD3.X R13, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff0d7210 */
/* 0x000fe200007fe4ff */
/*10e0*/ IMAD R21, R16, R18, R19 ; /* 0x0000001210157224 */
/* 0x001fca00078e0213 */
/*10f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101906 */
/*1100*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000e68000c1e1900 */
/*1110*/ LDG.E R18, [R6.64+0x88] ; /* 0x0000880606127981 */
/* 0x000e62000c1e1900 */
/*1120*/ IADD3 R14, P0, R8, 0x46000000, RZ ; /* 0x46000000080e7810 */
/* 0x000fca0007f1e0ff */
/*1130*/ IMAD.X R15, RZ, RZ, R9, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400000e0609 */
/*1140*/ IMAD R19, R12, R18, R21 ; /* 0x000000120c137224 */
/* 0x002fca00078e0215 */
/*1150*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101906 */
/*1160*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000e28000c1e1900 */
/*1170*/ LDG.E R18, [R6.64+0x8c] ; /* 0x00008c0606127981 */
/* 0x000e22000c1e1900 */
/*1180*/ IADD3 R16, P0, R8, 0x48000000, RZ ; /* 0x4800000008107810 */
/* 0x000fc80007f1e0ff */
/*1190*/ IADD3.X R17, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff117210 */
/* 0x000fe200007fe4ff */
/*11a0*/ IMAD R21, R14, R18, R19 ; /* 0x000000120e157224 */
/* 0x001fca00078e0213 */
/*11b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101906 */
/*11c0*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000e68000c1e1900 */
/*11d0*/ LDG.E R18, [R6.64+0x90] ; /* 0x0000900606127981 */
/* 0x000e62000c1e1900 */
/*11e0*/ IADD3 R12, P0, R8, 0x4a000000, RZ ; /* 0x4a000000080c7810 */
/* 0x000fc80007f1e0ff */
/*11f0*/ IADD3.X R13, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff0d7210 */
/* 0x000fe200007fe4ff */
/*1200*/ IMAD R19, R16, R18, R21 ; /* 0x0000001210137224 */
/* 0x002fca00078e0215 */
/*1210*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101906 */
/*1220*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000e28000c1e1900 */
/*1230*/ LDG.E R18, [R6.64+0x94] ; /* 0x0000940606127981 */
/* 0x000e22000c1e1900 */
/*1240*/ IADD3 R14, P0, R8, 0x4c000000, RZ ; /* 0x4c000000080e7810 */
/* 0x000fca0007f1e0ff */
/*1250*/ IMAD.X R15, RZ, RZ, R9, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400000e0609 */
/*1260*/ IMAD R21, R12, R18, R19 ; /* 0x000000120c157224 */
/* 0x001fca00078e0213 */
/*1270*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101906 */
/*1280*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000e68000c1e1900 */
/*1290*/ LDG.E R16, [R6.64+0x98] ; /* 0x0000980606107981 */
/* 0x000e62000c1e1900 */
/*12a0*/ IADD3 R8, P0, R8, 0x4e000000, RZ ; /* 0x4e00000008087810 */
/* 0x000fc80007f1e0ff */
/*12b0*/ IADD3.X R9, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff097210 */
/* 0x000fe200007fe4ff */
/*12c0*/ IMAD R19, R14, R16, R21 ; /* 0x000000100e137224 */
/* 0x002fca00078e0215 */
/*12d0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101906 */
/*12e0*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea8000c1e1900 */
/*12f0*/ LDG.E R17, [R6.64+0x9c] ; /* 0x00009c0606117981 */
/* 0x000ea2000c1e1900 */
/*1300*/ IADD3 R4, R4, 0x28, RZ ; /* 0x0000002804047810 */
/* 0x000fe20007ffe0ff */
/*1310*/ UIADD3 UR4, UP0, UR4, 0x50000000, URZ ; /* 0x5000000004047890 */
/* 0x000fe2000ff1e03f */
/*1320*/ IADD3 R10, P1, R10, 0xa0, RZ ; /* 0x000000a00a0a7810 */
/* 0x000fc40007f3e0ff */
/*1330*/ ISETP.NE.AND P0, PT, R4, 0x800000, PT ; /* 0x008000000400780c */
/* 0x000fe20003f05270 */
/*1340*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*1350*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe20000ffe4ff */
/*1360*/ IMAD R17, R8, R17, R19 ; /* 0x0000001108117224 */
/* 0x004fca00078e0213 */
/*1370*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001ea000c101906 */
/*1380*/ @P0 BRA 0x400 ; /* 0xfffff07000000947 */
/* 0x000fea000383ffff */
/*1390*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*13a0*/ BRA 0x13a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*13b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void mul(int * A, int * B, int * C){
int i = blockIdx.x;
int j = threadIdx.x;
C[i * N + j] = 0;
for (int k = 0; k < N; k++){
C[i * N + j] += A[i * N + k] * B[k * N + j];
}
} | .file "tmpxft_000eeb3b_00000000-6_mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3mulPiS_S_PiS_S_
.type _Z26__device_stub__Z3mulPiS_S_PiS_S_, @function
_Z26__device_stub__Z3mulPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3mulPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3mulPiS_S_PiS_S_, .-_Z26__device_stub__Z3mulPiS_S_PiS_S_
.globl _Z3mulPiS_S_
.type _Z3mulPiS_S_, @function
_Z3mulPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3mulPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3mulPiS_S_, .-_Z3mulPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3mulPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mulPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void mul(int * A, int * B, int * C){
int i = blockIdx.x;
int j = threadIdx.x;
C[i * N + j] = 0;
for (int k = 0; k < N; k++){
C[i * N + j] += A[i * N + k] * B[k * N + j];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mul(int * A, int * B, int * C){
int i = blockIdx.x;
int j = threadIdx.x;
C[i * N + j] = 0;
for (int k = 0; k < N; k++){
C[i * N + j] += A[i * N + k] * B[k * N + j];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mul(int * A, int * B, int * C){
int i = blockIdx.x;
int j = threadIdx.x;
C[i * N + j] = 0;
for (int k = 0; k < N; k++){
C[i * N + j] += A[i * N + k] * B[k * N + j];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3mulPiS_S_
.globl _Z3mulPiS_S_
.p2align 8
.type _Z3mulPiS_S_,@function
_Z3mulPiS_S_:
s_load_b64 s[4:5], s[0:1], 0x10
s_lshl_b32 s6, s15, 23
s_load_b128 s[0:3], s[0:1], 0x0
v_or_b32_e32 v1, s6, v0
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mov_b32_e32 v4, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_lshl_b64 s[4:5], s[6:7], 2
s_add_u32 s4, s0, s4
s_addc_u32 s5, s1, s5
s_mov_b64 s[0:1], 0
global_store_b32 v[2:3], v1, off
.p2align 6
.LBB0_1:
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_add_u32 s6, s4, s0
s_addc_u32 s7, s5, s1
v_add_nc_u32_e32 v0, 0x800000, v0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_cmp_eq_u32 s0, 0x2000000
global_load_b32 v7, v1, s[6:7]
global_load_b32 v8, v[5:6], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v8, v7, v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v4, v5
global_store_b32 v[2:3], v5, off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mulPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3mulPiS_S_, .Lfunc_end0-_Z3mulPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mulPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3mulPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mul(int * A, int * B, int * C){
int i = blockIdx.x;
int j = threadIdx.x;
C[i * N + j] = 0;
for (int k = 0; k < N; k++){
C[i * N + j] += A[i * N + k] * B[k * N + j];
}
} | .text
.file "mul.hip"
.globl _Z18__device_stub__mulPiS_S_ # -- Begin function _Z18__device_stub__mulPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__mulPiS_S_,@function
_Z18__device_stub__mulPiS_S_: # @_Z18__device_stub__mulPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3mulPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__mulPiS_S_, .Lfunc_end0-_Z18__device_stub__mulPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mulPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3mulPiS_S_,@object # @_Z3mulPiS_S_
.section .rodata,"a",@progbits
.globl _Z3mulPiS_S_
.p2align 3, 0x0
_Z3mulPiS_S_:
.quad _Z18__device_stub__mulPiS_S_
.size _Z3mulPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3mulPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__mulPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3mulPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000eeb3b_00000000-6_mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3mulPiS_S_PiS_S_
.type _Z26__device_stub__Z3mulPiS_S_PiS_S_, @function
_Z26__device_stub__Z3mulPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3mulPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3mulPiS_S_PiS_S_, .-_Z26__device_stub__Z3mulPiS_S_PiS_S_
.globl _Z3mulPiS_S_
.type _Z3mulPiS_S_, @function
_Z3mulPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3mulPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3mulPiS_S_, .-_Z3mulPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3mulPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mulPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mul.hip"
.globl _Z18__device_stub__mulPiS_S_ # -- Begin function _Z18__device_stub__mulPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__mulPiS_S_,@function
_Z18__device_stub__mulPiS_S_: # @_Z18__device_stub__mulPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3mulPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__mulPiS_S_, .Lfunc_end0-_Z18__device_stub__mulPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mulPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3mulPiS_S_,@object # @_Z3mulPiS_S_
.section .rodata,"a",@progbits
.globl _Z3mulPiS_S_
.p2align 3, 0x0
_Z3mulPiS_S_:
.quad _Z18__device_stub__mulPiS_S_
.size _Z3mulPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3mulPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__mulPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3mulPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void group_point_grad_gpu(int b, int n, int c, int m, int nsample, const float *grad_out, const int *idx, float *grad_points) {
for (int i=0;i<b;++i) {
for (int j=0;j<m;++j) {
for (int k=0;k<nsample;++k) {
int ii = idx[j*nsample+k];
for (int l=0;l<c;++l) {
grad_points[ii*c+l] += grad_out[j*nsample*c+k*c+l];
}
}
}
idx+=m*nsample;
grad_out+=m*nsample*c;
grad_points+=n*c;
}
} | code for sm_80
Function : _Z20group_point_grad_gpuiiiiiPKfPKiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff007435 */
/* 0x000fd400000001ff */
/*0020*/ ISETP.LE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f03270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ ISETP.LE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f03270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ ISETP.LE.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f23270 */
/*0080*/ HFMA2.MMA R6, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff067435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff007624 */
/* 0x000fe200078e00ff */
/*00b0*/ ISETP.LT.OR P1, PT, R5.reuse, 0x1, !P1 ; /* 0x000000010500780c */
/* 0x040fe20004f21670 */
/*00c0*/ IMAD R5, R5, c[0x0][0x16c], RZ ; /* 0x00005b0005057a24 */
/* 0x000fe200078e02ff */
/*00d0*/ ULDC UR5, c[0x0][0x164] ; /* 0x0000590000057ab9 */
/* 0x000fe20000000800 */
/*00e0*/ MOV R3, c[0x0][0x184] ; /* 0x0000610000037a02 */
/* 0x000fe20000000f00 */
/*00f0*/ UIMAD UR5, UR4, UR5, URZ ; /* 0x00000005040572a4 */
/* 0x000fe2000f8e023f */
/*0100*/ IMAD R2, R5.reuse, c[0x0][0x168], RZ ; /* 0x00005a0005027a24 */
/* 0x040fe200078e02ff */
/*0110*/ SHF.R.S32.HI R8, RZ, 0x1f, R5 ; /* 0x0000001fff087819 */
/* 0x000fe20000011405 */
/*0120*/ ULOP3.LUT UR7, UR4, 0x3, URZ, 0xc0, !UPT ; /* 0x0000000304077892 */
/* 0x000fe2000f8ec03f */
/*0130*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0c7624 */
/* 0x000fe200078e00ff */
/*0140*/ USHF.R.S32.HI UR6, URZ, 0x1f, UR5 ; /* 0x0000001f3f067899 */
/* 0x000fe20008011405 */
/*0150*/ SHF.R.S32.HI R7, RZ, 0x1f, R2 ; /* 0x0000001fff077819 */
/* 0x000fe20000011402 */
/*0160*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0170*/ MOV R13, c[0x0][0x17c] ; /* 0x00005f00000d7a02 */
/* 0x000fe20000000f00 */
/*0180*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0190*/ IADD3 R6, -R6, c[0x0][0x168], RZ ; /* 0x00005a0006067a10 */
/* 0x000fe20007ffe1ff */
/*01a0*/ UIADD3 UR4, -UR7, UR4, URZ ; /* 0x0000000407047290 */
/* 0x000fe2000fffe13f */
/*01b0*/ SHF.L.U64.HI R8, R5, 0x2, R8 ; /* 0x0000000205087819 */
/* 0x000fe20000010208 */
/*01c0*/ USHF.L.U64.HI UR6, UR5, 0x2, UR6 ; /* 0x0000000205067899 */
/* 0x000fe20008010206 */
/*01d0*/ SHF.L.U64.HI R7, R2, 0x2, R7 ; /* 0x0000000202077819 */
/* 0x000fe20000010207 */
/*01e0*/ ULDC.64 UR10, c[0x0][0x188] ; /* 0x00006200000a7ab9 */
/* 0x000fc40000000a00 */
/*01f0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fc80007ffe0ff */
/*0200*/ ISETP.GE.AND P3, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fe20003f66270 */
/*0210*/ @P1 BRA 0xf20 ; /* 0x00000d0000001947 */
/* 0x003fea0003800000 */
/*0220*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fd400000001ff */
/*0230*/ IMAD.MOV.U32 R10, RZ, RZ, R9 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0009 */
/*0240*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*0250*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe40000000f00 */
/*0260*/ ISETP.GE.AND P4, PT, R9, c[0x0][0x16c], PT ; /* 0x00005b0009007a0c */
/* 0x003fe40003f86270 */
/*0270*/ MOV R15, R3 ; /* 0x00000003000f7202 */
/* 0x001fe20000000f00 */
/*0280*/ IMAD R19, R10, c[0x0][0x170], R11 ; /* 0x00005c000a137a24 */
/* 0x000fe400078e020b */
/*0290*/ IMAD.MOV.U32 R14, RZ, RZ, R0 ; /* 0x000000ffff0e7224 */
/* 0x000fc800078e0000 */
/*02a0*/ IMAD.WIDE R14, R19, 0x4, R14 ; /* 0x00000004130e7825 */
/* 0x000fcc00078e020e */
/*02b0*/ LDG.E R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f06070 */
/*02d0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe200078e00ff */
/*02e0*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD R19, R19, c[0x0][0x168], RZ ; /* 0x00005a0013137a24 */
/* 0x000fc600078e02ff */
/*0300*/ ISETP.GE.AND P2, PT, R11, c[0x0][0x170], PT ; /* 0x00005c000b007a0c */
/* 0x000fe20003f46270 */
/*0310*/ IMAD R21, R14, c[0x0][0x168], RZ ; /* 0x00005a000e157a24 */
/* 0x004fcc00078e02ff */
/*0320*/ @!P0 BRA 0xd60 ; /* 0x00000a3000008947 */
/* 0x002fea0003800000 */
/*0330*/ ISETP.LT.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf01270 */
/*0340*/ IMAD.U32 R23, RZ, RZ, UR10 ; /* 0x0000000aff177e24 */
/* 0x000fe2000f8e00ff */
/*0350*/ MOV R22, UR11 ; /* 0x0000000b00167c02 */
/* 0x000fe20008000f00 */
/*0360*/ IMAD.U32 R18, RZ, RZ, UR4 ; /* 0x00000004ff127e24 */
/* 0x000fe2000f8e00ff */
/*0370*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe200000001ff */
/*0380*/ IMAD.WIDE R14, R19, 0x4, R12 ; /* 0x00000004130e7825 */
/* 0x000fd000078e020c */
/*0390*/ @!P0 BRA 0xba0 ; /* 0x0000080000008947 */
/* 0x000fea0003800000 */
/*03a0*/ ISETP.GT.AND P5, PT, R18, 0xc, PT ; /* 0x0000000c1200780c */
/* 0x000fe40003fa4270 */
/*03b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*03c0*/ @!P5 BRA 0x8a0 ; /* 0x000004d00000d947 */
/* 0x000fea0003800000 */
/*03d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*03e0*/ MOV R16, R23 ; /* 0x0000001700107202 */
/* 0x002fe20000000f00 */
/*03f0*/ IMAD.MOV.U32 R17, RZ, RZ, R22 ; /* 0x000000ffff117224 */
/* 0x000fe200078e0016 */
/*0400*/ LDG.E R25, [R14.64] ; /* 0x000000080e197981 */
/* 0x000ea6000c1e1900 */
/*0410*/ IMAD.WIDE R16, R21, 0x4, R16 ; /* 0x0000000415107825 */
/* 0x000fca00078e0210 */
/*0420*/ LDG.E R24, [R16.64] ; /* 0x0000000810187981 */
/* 0x000ea4000c1e1900 */
/*0430*/ FADD R25, R24, R25 ; /* 0x0000001918197221 */
/* 0x004fe40000000000 */
/*0440*/ LDG.E R24, [R16.64+0x4] ; /* 0x0000040810187981 */
/* 0x000ea8000c1e1900 */
/*0450*/ STG.E [R16.64], R25 ; /* 0x0000001910007986 */
/* 0x0001e8000c101908 */
/*0460*/ LDG.E R27, [R14.64+0x4] ; /* 0x000004080e1b7981 */
/* 0x000ea4000c1e1900 */
/*0470*/ FADD R27, R24, R27 ; /* 0x0000001b181b7221 */
/* 0x004fc40000000000 */
/*0480*/ LDG.E R24, [R16.64+0x8] ; /* 0x0000080810187981 */
/* 0x000ea8000c1e1900 */
/*0490*/ STG.E [R16.64+0x4], R27 ; /* 0x0000041b10007986 */
/* 0x0003e8000c101908 */
/*04a0*/ LDG.E R29, [R14.64+0x8] ; /* 0x000008080e1d7981 */
/* 0x000ea4000c1e1900 */
/*04b0*/ FADD R29, R24, R29 ; /* 0x0000001d181d7221 */
/* 0x004fc40000000000 */
/*04c0*/ LDG.E R24, [R16.64+0xc] ; /* 0x00000c0810187981 */
/* 0x000e28000c1e1900 */
/*04d0*/ STG.E [R16.64+0x8], R29 ; /* 0x0000081d10007986 */
/* 0x0005e8000c101908 */
/*04e0*/ LDG.E R26, [R14.64+0xc] ; /* 0x00000c080e1a7981 */
/* 0x000e24000c1e1900 */
/*04f0*/ FADD R25, R24, R26 ; /* 0x0000001a18197221 */
/* 0x001fc40000000000 */
/*0500*/ LDG.E R24, [R16.64+0x10] ; /* 0x0000100810187981 */
/* 0x000e68000c1e1900 */
/*0510*/ STG.E [R16.64+0xc], R25 ; /* 0x00000c1910007986 */
/* 0x0001e8000c101908 */
/*0520*/ LDG.E R26, [R14.64+0x10] ; /* 0x000010080e1a7981 */
/* 0x000e64000c1e1900 */
/*0530*/ FADD R27, R24, R26 ; /* 0x0000001a181b7221 */
/* 0x002fc40000000000 */
/*0540*/ LDG.E R24, [R16.64+0x14] ; /* 0x0000140810187981 */
/* 0x000ea8000c1e1900 */
/*0550*/ STG.E [R16.64+0x10], R27 ; /* 0x0000101b10007986 */
/* 0x0003e8000c101908 */
/*0560*/ LDG.E R26, [R14.64+0x14] ; /* 0x000014080e1a7981 */
/* 0x000ea4000c1e1900 */
/*0570*/ FADD R29, R24, R26 ; /* 0x0000001a181d7221 */
/* 0x004fc40000000000 */
/*0580*/ LDG.E R24, [R16.64+0x18] ; /* 0x0000180810187981 */
/* 0x000e28000c1e1900 */
/*0590*/ STG.E [R16.64+0x14], R29 ; /* 0x0000141d10007986 */
/* 0x0005e8000c101908 */
/*05a0*/ LDG.E R26, [R14.64+0x18] ; /* 0x000018080e1a7981 */
/* 0x000e24000c1e1900 */
/*05b0*/ FADD R25, R24, R26 ; /* 0x0000001a18197221 */
/* 0x001fc40000000000 */
/*05c0*/ LDG.E R24, [R16.64+0x1c] ; /* 0x00001c0810187981 */
/* 0x000e68000c1e1900 */
/*05d0*/ STG.E [R16.64+0x18], R25 ; /* 0x0000181910007986 */
/* 0x0001e8000c101908 */
/*05e0*/ LDG.E R26, [R14.64+0x1c] ; /* 0x00001c080e1a7981 */
/* 0x000e64000c1e1900 */
/*05f0*/ FADD R27, R24, R26 ; /* 0x0000001a181b7221 */
/* 0x002fc40000000000 */
/*0600*/ LDG.E R24, [R16.64+0x20] ; /* 0x0000200810187981 */
/* 0x000ea8000c1e1900 */
/*0610*/ STG.E [R16.64+0x1c], R27 ; /* 0x00001c1b10007986 */
/* 0x0003e8000c101908 */
/*0620*/ LDG.E R26, [R14.64+0x20] ; /* 0x000020080e1a7981 */
/* 0x000ea4000c1e1900 */
/*0630*/ FADD R29, R24, R26 ; /* 0x0000001a181d7221 */
/* 0x004fc40000000000 */
/*0640*/ LDG.E R24, [R16.64+0x24] ; /* 0x0000240810187981 */
/* 0x000e28000c1e1900 */
/*0650*/ STG.E [R16.64+0x20], R29 ; /* 0x0000201d10007986 */
/* 0x0005e8000c101908 */
/*0660*/ LDG.E R26, [R14.64+0x24] ; /* 0x000024080e1a7981 */
/* 0x000e24000c1e1900 */
/*0670*/ FADD R25, R24, R26 ; /* 0x0000001a18197221 */
/* 0x001fc40000000000 */
/*0680*/ LDG.E R24, [R16.64+0x28] ; /* 0x0000280810187981 */
/* 0x000e68000c1e1900 */
/*0690*/ STG.E [R16.64+0x24], R25 ; /* 0x0000241910007986 */
/* 0x0001e8000c101908 */
/*06a0*/ LDG.E R26, [R14.64+0x28] ; /* 0x000028080e1a7981 */
/* 0x000e64000c1e1900 */
/*06b0*/ FADD R27, R24, R26 ; /* 0x0000001a181b7221 */
/* 0x002fc40000000000 */
/*06c0*/ LDG.E R24, [R16.64+0x2c] ; /* 0x00002c0810187981 */
/* 0x000ea8000c1e1900 */
/*06d0*/ STG.E [R16.64+0x28], R27 ; /* 0x0000281b10007986 */
/* 0x0003e8000c101908 */
/*06e0*/ LDG.E R26, [R14.64+0x2c] ; /* 0x00002c080e1a7981 */
/* 0x000ea4000c1e1900 */
/*06f0*/ FADD R29, R24, R26 ; /* 0x0000001a181d7221 */
/* 0x004fc40000000000 */
/*0700*/ LDG.E R24, [R16.64+0x30] ; /* 0x0000300810187981 */
/* 0x000e28000c1e1900 */
/*0710*/ STG.E [R16.64+0x2c], R29 ; /* 0x00002c1d10007986 */
/* 0x0005e8000c101908 */
/*0720*/ LDG.E R26, [R14.64+0x30] ; /* 0x000030080e1a7981 */
/* 0x000e24000c1e1900 */
/*0730*/ FADD R25, R24, R26 ; /* 0x0000001a18197221 */
/* 0x001fc40000000000 */
/*0740*/ LDG.E R24, [R16.64+0x34] ; /* 0x0000340810187981 */
/* 0x000e68000c1e1900 */
/*0750*/ STG.E [R16.64+0x30], R25 ; /* 0x0000301910007986 */
/* 0x0001e8000c101908 */
/*0760*/ LDG.E R26, [R14.64+0x34] ; /* 0x000034080e1a7981 */
/* 0x000e64000c1e1900 */
/*0770*/ FADD R27, R24, R26 ; /* 0x0000001a181b7221 */
/* 0x002fc40000000000 */
/*0780*/ LDG.E R24, [R16.64+0x38] ; /* 0x0000380810187981 */
/* 0x000ea8000c1e1900 */
/*0790*/ STG.E [R16.64+0x34], R27 ; /* 0x0000341b10007986 */
/* 0x0003e8000c101908 */
/*07a0*/ LDG.E R26, [R14.64+0x38] ; /* 0x000038080e1a7981 */
/* 0x000ea2000c1e1900 */
/*07b0*/ IADD3 R23, P6, R23, 0x40, RZ ; /* 0x0000004017177810 */
/* 0x000fe40007fde0ff */
/*07c0*/ IADD3 R18, R18, -0x10, RZ ; /* 0xfffffff012127810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ FADD R29, R24, R26 ; /* 0x0000001a181d7221 */
/* 0x004fc40000000000 */
/*07e0*/ LDG.E R24, [R16.64+0x3c] ; /* 0x00003c0810187981 */
/* 0x000e28000c1e1900 */
/*07f0*/ STG.E [R16.64+0x38], R29 ; /* 0x0000381d10007986 */
/* 0x0003e8000c101908 */
/*0800*/ LDG.E R26, [R14.64+0x3c] ; /* 0x00003c080e1a7981 */
/* 0x000e22000c1e1900 */
/*0810*/ IADD3.X R22, RZ, R22, RZ, P6, !PT ; /* 0x00000016ff167210 */
/* 0x000fe400037fe4ff */
/*0820*/ ISETP.GT.AND P6, PT, R18, 0xc, PT ; /* 0x0000000c1200780c */
/* 0x000fc40003fc4270 */
/*0830*/ IADD3 R20, R20, 0x10, RZ ; /* 0x0000001014147810 */
/* 0x000fe20007ffe0ff */
/*0840*/ FADD R25, R24, R26 ; /* 0x0000001a18197221 */
/* 0x001fe20000000000 */
/*0850*/ IADD3 R24, P5, R14, 0x40, RZ ; /* 0x000000400e187810 */
/* 0x000fc80007fbe0ff */
/*0860*/ STG.E [R16.64+0x3c], R25 ; /* 0x00003c1910007986 */
/* 0x0003e2000c101908 */
/*0870*/ IMAD.X R15, RZ, RZ, R15, P5 ; /* 0x000000ffff0f7224 */
/* 0x000fe200028e060f */
/*0880*/ MOV R14, R24 ; /* 0x00000018000e7202 */
/* 0x000fc60000000f00 */
/*0890*/ @P6 BRA 0x3e0 ; /* 0xfffffb4000006947 */
/* 0x000fea000383ffff */
/*08a0*/ ISETP.GT.AND P5, PT, R18, 0x4, PT ; /* 0x000000041200780c */
/* 0x000fda0003fa4270 */
/*08b0*/ @!P5 BRA 0xb80 ; /* 0x000002c00000d947 */
/* 0x000fea0003800000 */
/*08c0*/ MOV R17, R22 ; /* 0x0000001600117202 */
/* 0x002fe20000000f00 */
/*08d0*/ IMAD.MOV.U32 R16, RZ, RZ, R23 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0017 */
/*08e0*/ LDG.E R25, [R14.64] ; /* 0x000000080e197981 */
/* 0x000ea6000c1e1900 */
/*08f0*/ IMAD.WIDE R16, R21, 0x4, R16 ; /* 0x0000000415107825 */
/* 0x000fca00078e0210 */
/*0900*/ LDG.E R24, [R16.64] ; /* 0x0000000810187981 */
/* 0x000ea4000c1e1900 */
/*0910*/ FADD R25, R24, R25 ; /* 0x0000001918197221 */
/* 0x004fe40000000000 */
/*0920*/ LDG.E R24, [R16.64+0x4] ; /* 0x0000040810187981 */
/* 0x000ea8000c1e1900 */
/*0930*/ STG.E [R16.64], R25 ; /* 0x0000001910007986 */
/* 0x0001e8000c101908 */
/*0940*/ LDG.E R27, [R14.64+0x4] ; /* 0x000004080e1b7981 */
/* 0x000ea4000c1e1900 */
/*0950*/ FADD R27, R24, R27 ; /* 0x0000001b181b7221 */
/* 0x004fc40000000000 */
/*0960*/ LDG.E R24, [R16.64+0x8] ; /* 0x0000080810187981 */
/* 0x000ea8000c1e1900 */
/*0970*/ STG.E [R16.64+0x4], R27 ; /* 0x0000041b10007986 */
/* 0x0003e8000c101908 */
/*0980*/ LDG.E R29, [R14.64+0x8] ; /* 0x000008080e1d7981 */
/* 0x000ea4000c1e1900 */
/*0990*/ FADD R29, R24, R29 ; /* 0x0000001d181d7221 */
/* 0x004fc40000000000 */
/*09a0*/ LDG.E R24, [R16.64+0xc] ; /* 0x00000c0810187981 */
/* 0x000e28000c1e1900 */
/*09b0*/ STG.E [R16.64+0x8], R29 ; /* 0x0000081d10007986 */
/* 0x0005e8000c101908 */
/*09c0*/ LDG.E R26, [R14.64+0xc] ; /* 0x00000c080e1a7981 */
/* 0x000e24000c1e1900 */
/*09d0*/ FADD R25, R24, R26 ; /* 0x0000001a18197221 */
/* 0x001fc40000000000 */
/*09e0*/ LDG.E R24, [R16.64+0x10] ; /* 0x0000100810187981 */
/* 0x000e68000c1e1900 */
/*09f0*/ STG.E [R16.64+0xc], R25 ; /* 0x00000c1910007986 */
/* 0x0001e8000c101908 */
/*0a00*/ LDG.E R26, [R14.64+0x10] ; /* 0x000010080e1a7981 */
/* 0x000e64000c1e1900 */
/*0a10*/ FADD R27, R24, R26 ; /* 0x0000001a181b7221 */
/* 0x002fc40000000000 */
/*0a20*/ LDG.E R24, [R16.64+0x14] ; /* 0x0000140810187981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ STG.E [R16.64+0x10], R27 ; /* 0x0000101b10007986 */
/* 0x0003e8000c101908 */
/*0a40*/ LDG.E R26, [R14.64+0x14] ; /* 0x000014080e1a7981 */
/* 0x000ea4000c1e1900 */
/*0a50*/ FADD R29, R24, R26 ; /* 0x0000001a181d7221 */
/* 0x004fc40000000000 */
/*0a60*/ LDG.E R24, [R16.64+0x18] ; /* 0x0000180810187981 */
/* 0x000e28000c1e1900 */
/*0a70*/ STG.E [R16.64+0x14], R29 ; /* 0x0000141d10007986 */
/* 0x0005e8000c101908 */
/*0a80*/ LDG.E R26, [R14.64+0x18] ; /* 0x000018080e1a7981 */
/* 0x000e24000c1e1900 */
/*0a90*/ FADD R25, R24, R26 ; /* 0x0000001a18197221 */
/* 0x001fc40000000000 */
/*0aa0*/ LDG.E R24, [R16.64+0x1c] ; /* 0x00001c0810187981 */
/* 0x000e68000c1e1900 */
/*0ab0*/ STG.E [R16.64+0x18], R25 ; /* 0x0000181910007986 */
/* 0x0001e8000c101908 */
/*0ac0*/ LDG.E R26, [R14.64+0x1c] ; /* 0x00001c080e1a7981 */
/* 0x000e62000c1e1900 */
/*0ad0*/ IADD3 R23, P5, R23, 0x20, RZ ; /* 0x0000002017177810 */
/* 0x000fe40007fbe0ff */
/*0ae0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0af0*/ IADD3 R20, R20, 0x8, RZ ; /* 0x0000000814147810 */
/* 0x000fe40007ffe0ff */
/*0b00*/ IADD3 R18, R18, -0x8, RZ ; /* 0xfffffff812127810 */
/* 0x000fe40007ffe0ff */
/*0b10*/ IADD3.X R22, RZ, R22, RZ, P5, !PT ; /* 0x00000016ff167210 */
/* 0x000fe20002ffe4ff */
/*0b20*/ FADD R27, R24, R26 ; /* 0x0000001a181b7221 */
/* 0x002fca0000000000 */
/*0b30*/ STG.E [R16.64+0x1c], R27 ; /* 0x00001c1b10007986 */
/* 0x0001e2000c101908 */
/*0b40*/ IADD3 R24, P6, R14, 0x20, RZ ; /* 0x000000200e187810 */
/* 0x000fca0007fde0ff */
/*0b50*/ IMAD.X R29, RZ, RZ, R15, P6 ; /* 0x000000ffff1d7224 */
/* 0x004fe400030e060f */
/*0b60*/ IMAD.MOV.U32 R14, RZ, RZ, R24 ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e0018 */
/*0b70*/ MOV R15, R29 ; /* 0x0000001d000f7202 */
/* 0x000fe40000000f00 */
/*0b80*/ ISETP.NE.OR P0, PT, R18, RZ, P0 ; /* 0x000000ff1200720c */
/* 0x000fda0000705670 */
/*0b90*/ @!P0 BRA 0xd60 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0ba0*/ MOV R17, R22 ; /* 0x0000001600117202 */
/* 0x003fe20000000f00 */
/*0bb0*/ IMAD.MOV.U32 R16, RZ, RZ, R23 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0017 */
/*0bc0*/ LDG.E R25, [R14.64] ; /* 0x000000080e197981 */
/* 0x000ea6000c1e1900 */
/*0bd0*/ IMAD.WIDE R16, R21, 0x4, R16 ; /* 0x0000000415107825 */
/* 0x000fca00078e0210 */
/*0be0*/ LDG.E R24, [R16.64] ; /* 0x0000000810187981 */
/* 0x000ea4000c1e1900 */
/*0bf0*/ FADD R25, R24, R25 ; /* 0x0000001918197221 */
/* 0x004fe40000000000 */
/*0c00*/ LDG.E R24, [R16.64+0x4] ; /* 0x0000040810187981 */
/* 0x000ea8000c1e1900 */
/*0c10*/ STG.E [R16.64], R25 ; /* 0x0000001910007986 */
/* 0x0001e8000c101908 */
/*0c20*/ LDG.E R27, [R14.64+0x4] ; /* 0x000004080e1b7981 */
/* 0x000ea4000c1e1900 */
/*0c30*/ FADD R27, R24, R27 ; /* 0x0000001b181b7221 */
/* 0x004fc40000000000 */
/*0c40*/ LDG.E R24, [R16.64+0x8] ; /* 0x0000080810187981 */
/* 0x000ea8000c1e1900 */
/*0c50*/ STG.E [R16.64+0x4], R27 ; /* 0x0000041b10007986 */
/* 0x0003e8000c101908 */
/*0c60*/ LDG.E R29, [R14.64+0x8] ; /* 0x000008080e1d7981 */
/* 0x000ea2000c1e1900 */
/*0c70*/ IADD3 R18, R18, -0x4, RZ ; /* 0xfffffffc12127810 */
/* 0x000fe20007ffe0ff */
/*0c80*/ FADD R29, R24, R29 ; /* 0x0000001d181d7221 */
/* 0x004fc40000000000 */
/*0c90*/ LDG.E R24, [R16.64+0xc] ; /* 0x00000c0810187981 */
/* 0x000e28000c1e1900 */
/*0ca0*/ STG.E [R16.64+0x8], R29 ; /* 0x0000081d10007986 */
/* 0x0003e8000c101908 */
/*0cb0*/ LDG.E R26, [R14.64+0xc] ; /* 0x00000c080e1a7981 */
/* 0x000e22000c1e1900 */
/*0cc0*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe40003f05270 */
/*0cd0*/ IADD3 R23, P5, R23, 0x10, RZ ; /* 0x0000001017177810 */
/* 0x000fc40007fbe0ff */
/*0ce0*/ IADD3 R20, R20, 0x4, RZ ; /* 0x0000000414147810 */
/* 0x000fe40007ffe0ff */
/*0cf0*/ IADD3.X R22, RZ, R22, RZ, P5, !PT ; /* 0x00000016ff167210 */
/* 0x000fe20002ffe4ff */
/*0d00*/ FADD R25, R24, R26 ; /* 0x0000001a18197221 */
/* 0x001fe20000000000 */
/*0d10*/ IADD3 R24, P6, R14, 0x10, RZ ; /* 0x000000100e187810 */
/* 0x000fc80007fde0ff */
/*0d20*/ STG.E [R16.64+0xc], R25 ; /* 0x00000c1910007986 */
/* 0x0003e2000c101908 */
/*0d30*/ IMAD.X R15, RZ, RZ, R15, P6 ; /* 0x000000ffff0f7224 */
/* 0x000fe400030e060f */
/*0d40*/ IMAD.MOV.U32 R14, RZ, RZ, R24 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0018 */
/*0d50*/ @P0 BRA 0xba0 ; /* 0xfffffe4000000947 */
/* 0x002fea000383ffff */
/*0d60*/ ISETP.NE.AND P0, PT, RZ, UR7, PT ; /* 0x00000007ff007c0c */
/* 0x000fda000bf05270 */
/*0d70*/ @!P0 BRA 0xf00 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0d80*/ MOV R14, UR10 ; /* 0x0000000a000e7c02 */
/* 0x000fe20008000f00 */
/*0d90*/ IMAD.U32 R15, RZ, RZ, UR11 ; /* 0x0000000bff0f7e24 */
/* 0x000fe2000f8e00ff */
/*0da0*/ IADD3 R17, R19, R20, RZ ; /* 0x0000001413117210 */
/* 0x003fe20007ffe0ff */
/*0db0*/ IMAD.IADD R21, R21, 0x1, R20 ; /* 0x0000000115157824 */
/* 0x000fc800078e0214 */
/*0dc0*/ IMAD.WIDE R16, R17, 0x4, R12 ; /* 0x0000000411107825 */
/* 0x000fc800078e020c */
/*0dd0*/ IMAD.WIDE R14, R21, 0x4, R14 ; /* 0x00000004150e7825 */
/* 0x000fe200078e020e */
/*0de0*/ LDG.E R19, [R16.64] ; /* 0x0000000810137981 */
/* 0x000ea8000c1e1900 */
/*0df0*/ LDG.E R18, [R14.64] ; /* 0x000000080e127981 */
/* 0x000ea2000c1e1900 */
/*0e00*/ UISETP.NE.AND UP0, UPT, UR7, 0x1, UPT ; /* 0x000000010700788c */
/* 0x000fcc000bf05270 */
/*0e10*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f008 */
/*0e20*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x004fca0000000000 */
/*0e30*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0001ee000c101908 */
/*0e40*/ @!P0 BRA 0xf00 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0e50*/ LDG.E R18, [R14.64+0x4] ; /* 0x000004080e127981 */
/* 0x000ea8000c1e1900 */
/*0e60*/ LDG.E R19, [R16.64+0x4] ; /* 0x0000040810137981 */
/* 0x001ea2000c1e1900 */
/*0e70*/ UISETP.NE.AND UP0, UPT, UR7, 0x2, UPT ; /* 0x000000020700788c */
/* 0x000fcc000bf05270 */
/*0e80*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f008 */
/*0e90*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x004fca0000000000 */
/*0ea0*/ STG.E [R14.64+0x4], R19 ; /* 0x000004130e007986 */
/* 0x0001ee000c101908 */
/*0eb0*/ @!P0 BRA 0xf00 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0ec0*/ LDG.E R17, [R16.64+0x8] ; /* 0x0000080810117981 */
/* 0x000ea8000c1e1900 */
/*0ed0*/ LDG.E R18, [R14.64+0x8] ; /* 0x000008080e127981 */
/* 0x000ea4000c1e1900 */
/*0ee0*/ FADD R19, R18, R17 ; /* 0x0000001112137221 */
/* 0x005fca0000000000 */
/*0ef0*/ STG.E [R14.64+0x8], R19 ; /* 0x000008130e007986 */
/* 0x0001e4000c101908 */
/*0f00*/ @!P2 BRA 0x270 ; /* 0xfffff3600000a947 */
/* 0x000fea000383ffff */
/*0f10*/ @!P4 BRA 0x230 ; /* 0xfffff3100000c947 */
/* 0x000fea000383ffff */
/*0f20*/ ULEA UR10, UP0, UR5, UR10, 0x2 ; /* 0x0000000a050a7291 */
/* 0x000fe2000f80103f */
/*0f30*/ LEA R0, P0, R5, R0, 0x2 ; /* 0x0000000005007211 */
/* 0x000fe400078010ff */
/*0f40*/ LEA R12, P2, R2, R12, 0x2 ; /* 0x0000000c020c7211 */
/* 0x000fe200078410ff */
/*0f50*/ UIADD3.X UR11, UR11, UR6, URZ, UP0, !UPT ; /* 0x000000060b0b7290 */
/* 0x000fe400087fe43f */
/*0f60*/ IMAD.X R3, R3, 0x1, R8, P0 ; /* 0x0000000103037824 */
/* 0x000fe200000e0608 */
/*0f70*/ IADD3.X R13, R13, R7, RZ, P2, !PT ; /* 0x000000070d0d7210 */
/* 0x000fe200017fe4ff */
/*0f80*/ @!P3 BRA 0x1f0 ; /* 0xfffff2600000b947 */
/* 0x000fea000383ffff */
/*0f90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fa0*/ BRA 0xfa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void group_point_grad_gpu(int b, int n, int c, int m, int nsample, const float *grad_out, const int *idx, float *grad_points) {
for (int i=0;i<b;++i) {
for (int j=0;j<m;++j) {
for (int k=0;k<nsample;++k) {
int ii = idx[j*nsample+k];
for (int l=0;l<c;++l) {
grad_points[ii*c+l] += grad_out[j*nsample*c+k*c+l];
}
}
}
idx+=m*nsample;
grad_out+=m*nsample*c;
grad_points+=n*c;
}
} | .file "tmpxft_000781ba_00000000-6_group_point_grad_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
.type _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf, @function
_Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq 216(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20group_point_grad_gpuiiiiiPKfPKiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf, .-_Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
.globl _Z20group_point_grad_gpuiiiiiPKfPKiPf
.type _Z20group_point_grad_gpuiiiiiPKfPKiPf, @function
_Z20group_point_grad_gpuiiiiiPKfPKiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20group_point_grad_gpuiiiiiPKfPKiPf, .-_Z20group_point_grad_gpuiiiiiPKfPKiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20group_point_grad_gpuiiiiiPKfPKiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20group_point_grad_gpuiiiiiPKfPKiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void group_point_grad_gpu(int b, int n, int c, int m, int nsample, const float *grad_out, const int *idx, float *grad_points) {
for (int i=0;i<b;++i) {
for (int j=0;j<m;++j) {
for (int k=0;k<nsample;++k) {
int ii = idx[j*nsample+k];
for (int l=0;l<c;++l) {
grad_points[ii*c+l] += grad_out[j*nsample*c+k*c+l];
}
}
}
idx+=m*nsample;
grad_out+=m*nsample*c;
grad_points+=n*c;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void group_point_grad_gpu(int b, int n, int c, int m, int nsample, const float *grad_out, const int *idx, float *grad_points) {
for (int i=0;i<b;++i) {
for (int j=0;j<m;++j) {
for (int k=0;k<nsample;++k) {
int ii = idx[j*nsample+k];
for (int l=0;l<c;++l) {
grad_points[ii*c+l] += grad_out[j*nsample*c+k*c+l];
}
}
}
idx+=m*nsample;
grad_out+=m*nsample*c;
grad_points+=n*c;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void group_point_grad_gpu(int b, int n, int c, int m, int nsample, const float *grad_out, const int *idx, float *grad_points) {
for (int i=0;i<b;++i) {
for (int j=0;j<m;++j) {
for (int k=0;k<nsample;++k) {
int ii = idx[j*nsample+k];
for (int l=0;l<c;++l) {
grad_points[ii*c+l] += grad_out[j*nsample*c+k*c+l];
}
}
}
idx+=m*nsample;
grad_out+=m*nsample*c;
grad_points+=n*c;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20group_point_grad_gpuiiiiiPKfPKiPf
.globl _Z20group_point_grad_gpuiiiiiPKfPKiPf
.p2align 8
.type _Z20group_point_grad_gpuiiiiiPKfPKiPf,@function
_Z20group_point_grad_gpuiiiiiPKfPKiPf:
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_12
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x4
s_load_b128 s[8:11], s[0:1], 0x18
s_load_b64 s[12:13], s[0:1], 0x28
s_mov_b32 s15, 0
s_mov_b32 s28, 0
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s6, 0
s_mul_i32 s20, s7, s6
s_cselect_b32 s0, -1, 0
s_cmp_gt_i32 s7, 0
v_cndmask_b32_e64 v0, 0, 1, s0
s_cselect_b32 s0, -1, 0
s_cmp_gt_i32 s5, 0
v_cndmask_b32_e64 v1, 0, 1, s0
s_cselect_b32 s0, -1, 0
s_mul_i32 s16, s5, s4
v_cndmask_b32_e64 v2, 0, 1, s0
s_mul_i32 s18, s20, s5
v_cmp_ne_u32_e64 s0, 1, v0
v_cmp_ne_u32_e64 s1, 1, v1
v_mov_b32_e32 v0, 0
v_cmp_ne_u32_e64 s2, 1, v2
s_ashr_i32 s21, s20, 31
s_ashr_i32 s19, s18, 31
s_ashr_i32 s17, s16, 31
s_lshl_b64 s[18:19], s[18:19], 2
s_lshl_b64 s[16:17], s[16:17], 2
s_mul_i32 s4, s7, s5
s_lshl_b64 s[20:21], s[20:21], 2
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_add_u32 s10, s10, s20
s_addc_u32 s11, s11, s21
s_add_i32 s28, s28, 1
s_add_u32 s12, s12, s16
s_addc_u32 s13, s13, s17
s_add_u32 s8, s8, s18
s_addc_u32 s9, s9, s19
s_cmp_eq_u32 s28, s3
s_cbranch_scc1 .LBB0_12
.LBB0_3:
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_2
s_mov_b32 s29, 0
s_mov_b32 s30, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_add_i32 s30, s30, 1
s_add_i32 s29, s29, s4
s_cmp_eq_u32 s30, s6
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_and_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_5
s_mul_i32 s31, s30, s7
s_mov_b32 s33, 0
s_mov_b32 s22, s29
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_add_i32 s33, s33, 1
s_add_i32 s22, s22, s5
s_cmp_eq_u32 s33, s7
s_cbranch_scc1 .LBB0_5
.LBB0_9:
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_8
s_ashr_i32 s23, s22, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[24:25], s[22:23], 2
s_add_u32 s24, s8, s24
s_addc_u32 s25, s9, s25
s_add_i32 s14, s33, s31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[26:27], s[14:15], 2
s_add_u32 s26, s10, s26
s_addc_u32 s27, s11, s27
s_load_b32 s14, s[26:27], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s26, s14, s5
s_mov_b32 s14, s5
s_ashr_i32 s27, s26, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[26:27], s[26:27], 2
s_add_u32 s26, s12, s26
s_addc_u32 s27, s13, s27
.LBB0_11:
s_clause 0x1
global_load_b32 v1, v0, s[24:25]
global_load_b32 v2, v0, s[26:27]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[26:27]
s_add_u32 s26, s26, 4
s_addc_u32 s27, s27, 0
s_add_u32 s24, s24, 4
s_addc_u32 s25, s25, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc0 .LBB0_11
s_branch .LBB0_8
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20group_point_grad_gpuiiiiiPKfPKiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 34
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20group_point_grad_gpuiiiiiPKfPKiPf, .Lfunc_end0-_Z20group_point_grad_gpuiiiiiPKfPKiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20group_point_grad_gpuiiiiiPKfPKiPf
.private_segment_fixed_size: 0
.sgpr_count: 36
.sgpr_spill_count: 0
.symbol: _Z20group_point_grad_gpuiiiiiPKfPKiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void group_point_grad_gpu(int b, int n, int c, int m, int nsample, const float *grad_out, const int *idx, float *grad_points) {
for (int i=0;i<b;++i) {
for (int j=0;j<m;++j) {
for (int k=0;k<nsample;++k) {
int ii = idx[j*nsample+k];
for (int l=0;l<c;++l) {
grad_points[ii*c+l] += grad_out[j*nsample*c+k*c+l];
}
}
}
idx+=m*nsample;
grad_out+=m*nsample*c;
grad_points+=n*c;
}
} | .text
.file "group_point_grad_gpu.hip"
.globl _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf # -- Begin function _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.p2align 4, 0x90
.type _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf,@function
_Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf: # @_Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20group_point_grad_gpuiiiiiPKfPKiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf, .Lfunc_end0-_Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20group_point_grad_gpuiiiiiPKfPKiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20group_point_grad_gpuiiiiiPKfPKiPf,@object # @_Z20group_point_grad_gpuiiiiiPKfPKiPf
.section .rodata,"a",@progbits
.globl _Z20group_point_grad_gpuiiiiiPKfPKiPf
.p2align 3, 0x0
_Z20group_point_grad_gpuiiiiiPKfPKiPf:
.quad _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.size _Z20group_point_grad_gpuiiiiiPKfPKiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20group_point_grad_gpuiiiiiPKfPKiPf"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20group_point_grad_gpuiiiiiPKfPKiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20group_point_grad_gpuiiiiiPKfPKiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff007435 */
/* 0x000fd400000001ff */
/*0020*/ ISETP.LE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f03270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ ISETP.LE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f03270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ ISETP.LE.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f23270 */
/*0080*/ HFMA2.MMA R6, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff067435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff007624 */
/* 0x000fe200078e00ff */
/*00b0*/ ISETP.LT.OR P1, PT, R5.reuse, 0x1, !P1 ; /* 0x000000010500780c */
/* 0x040fe20004f21670 */
/*00c0*/ IMAD R5, R5, c[0x0][0x16c], RZ ; /* 0x00005b0005057a24 */
/* 0x000fe200078e02ff */
/*00d0*/ ULDC UR5, c[0x0][0x164] ; /* 0x0000590000057ab9 */
/* 0x000fe20000000800 */
/*00e0*/ MOV R3, c[0x0][0x184] ; /* 0x0000610000037a02 */
/* 0x000fe20000000f00 */
/*00f0*/ UIMAD UR5, UR4, UR5, URZ ; /* 0x00000005040572a4 */
/* 0x000fe2000f8e023f */
/*0100*/ IMAD R2, R5.reuse, c[0x0][0x168], RZ ; /* 0x00005a0005027a24 */
/* 0x040fe200078e02ff */
/*0110*/ SHF.R.S32.HI R8, RZ, 0x1f, R5 ; /* 0x0000001fff087819 */
/* 0x000fe20000011405 */
/*0120*/ ULOP3.LUT UR7, UR4, 0x3, URZ, 0xc0, !UPT ; /* 0x0000000304077892 */
/* 0x000fe2000f8ec03f */
/*0130*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0c7624 */
/* 0x000fe200078e00ff */
/*0140*/ USHF.R.S32.HI UR6, URZ, 0x1f, UR5 ; /* 0x0000001f3f067899 */
/* 0x000fe20008011405 */
/*0150*/ SHF.R.S32.HI R7, RZ, 0x1f, R2 ; /* 0x0000001fff077819 */
/* 0x000fe20000011402 */
/*0160*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0170*/ MOV R13, c[0x0][0x17c] ; /* 0x00005f00000d7a02 */
/* 0x000fe20000000f00 */
/*0180*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0190*/ IADD3 R6, -R6, c[0x0][0x168], RZ ; /* 0x00005a0006067a10 */
/* 0x000fe20007ffe1ff */
/*01a0*/ UIADD3 UR4, -UR7, UR4, URZ ; /* 0x0000000407047290 */
/* 0x000fe2000fffe13f */
/*01b0*/ SHF.L.U64.HI R8, R5, 0x2, R8 ; /* 0x0000000205087819 */
/* 0x000fe20000010208 */
/*01c0*/ USHF.L.U64.HI UR6, UR5, 0x2, UR6 ; /* 0x0000000205067899 */
/* 0x000fe20008010206 */
/*01d0*/ SHF.L.U64.HI R7, R2, 0x2, R7 ; /* 0x0000000202077819 */
/* 0x000fe20000010207 */
/*01e0*/ ULDC.64 UR10, c[0x0][0x188] ; /* 0x00006200000a7ab9 */
/* 0x000fc40000000a00 */
/*01f0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fc80007ffe0ff */
/*0200*/ ISETP.GE.AND P3, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fe20003f66270 */
/*0210*/ @P1 BRA 0xf20 ; /* 0x00000d0000001947 */
/* 0x003fea0003800000 */
/*0220*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fd400000001ff */
/*0230*/ IMAD.MOV.U32 R10, RZ, RZ, R9 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0009 */
/*0240*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*0250*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe40000000f00 */
/*0260*/ ISETP.GE.AND P4, PT, R9, c[0x0][0x16c], PT ; /* 0x00005b0009007a0c */
/* 0x003fe40003f86270 */
/*0270*/ MOV R15, R3 ; /* 0x00000003000f7202 */
/* 0x001fe20000000f00 */
/*0280*/ IMAD R19, R10, c[0x0][0x170], R11 ; /* 0x00005c000a137a24 */
/* 0x000fe400078e020b */
/*0290*/ IMAD.MOV.U32 R14, RZ, RZ, R0 ; /* 0x000000ffff0e7224 */
/* 0x000fc800078e0000 */
/*02a0*/ IMAD.WIDE R14, R19, 0x4, R14 ; /* 0x00000004130e7825 */
/* 0x000fcc00078e020e */
/*02b0*/ LDG.E R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f06070 */
/*02d0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe200078e00ff */
/*02e0*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD R19, R19, c[0x0][0x168], RZ ; /* 0x00005a0013137a24 */
/* 0x000fc600078e02ff */
/*0300*/ ISETP.GE.AND P2, PT, R11, c[0x0][0x170], PT ; /* 0x00005c000b007a0c */
/* 0x000fe20003f46270 */
/*0310*/ IMAD R21, R14, c[0x0][0x168], RZ ; /* 0x00005a000e157a24 */
/* 0x004fcc00078e02ff */
/*0320*/ @!P0 BRA 0xd60 ; /* 0x00000a3000008947 */
/* 0x002fea0003800000 */
/*0330*/ ISETP.LT.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf01270 */
/*0340*/ IMAD.U32 R23, RZ, RZ, UR10 ; /* 0x0000000aff177e24 */
/* 0x000fe2000f8e00ff */
/*0350*/ MOV R22, UR11 ; /* 0x0000000b00167c02 */
/* 0x000fe20008000f00 */
/*0360*/ IMAD.U32 R18, RZ, RZ, UR4 ; /* 0x00000004ff127e24 */
/* 0x000fe2000f8e00ff */
/*0370*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe200000001ff */
/*0380*/ IMAD.WIDE R14, R19, 0x4, R12 ; /* 0x00000004130e7825 */
/* 0x000fd000078e020c */
/*0390*/ @!P0 BRA 0xba0 ; /* 0x0000080000008947 */
/* 0x000fea0003800000 */
/*03a0*/ ISETP.GT.AND P5, PT, R18, 0xc, PT ; /* 0x0000000c1200780c */
/* 0x000fe40003fa4270 */
/*03b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*03c0*/ @!P5 BRA 0x8a0 ; /* 0x000004d00000d947 */
/* 0x000fea0003800000 */
/*03d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*03e0*/ MOV R16, R23 ; /* 0x0000001700107202 */
/* 0x002fe20000000f00 */
/*03f0*/ IMAD.MOV.U32 R17, RZ, RZ, R22 ; /* 0x000000ffff117224 */
/* 0x000fe200078e0016 */
/*0400*/ LDG.E R25, [R14.64] ; /* 0x000000080e197981 */
/* 0x000ea6000c1e1900 */
/*0410*/ IMAD.WIDE R16, R21, 0x4, R16 ; /* 0x0000000415107825 */
/* 0x000fca00078e0210 */
/*0420*/ LDG.E R24, [R16.64] ; /* 0x0000000810187981 */
/* 0x000ea4000c1e1900 */
/*0430*/ FADD R25, R24, R25 ; /* 0x0000001918197221 */
/* 0x004fe40000000000 */
/*0440*/ LDG.E R24, [R16.64+0x4] ; /* 0x0000040810187981 */
/* 0x000ea8000c1e1900 */
/*0450*/ STG.E [R16.64], R25 ; /* 0x0000001910007986 */
/* 0x0001e8000c101908 */
/*0460*/ LDG.E R27, [R14.64+0x4] ; /* 0x000004080e1b7981 */
/* 0x000ea4000c1e1900 */
/*0470*/ FADD R27, R24, R27 ; /* 0x0000001b181b7221 */
/* 0x004fc40000000000 */
/*0480*/ LDG.E R24, [R16.64+0x8] ; /* 0x0000080810187981 */
/* 0x000ea8000c1e1900 */
/*0490*/ STG.E [R16.64+0x4], R27 ; /* 0x0000041b10007986 */
/* 0x0003e8000c101908 */
/*04a0*/ LDG.E R29, [R14.64+0x8] ; /* 0x000008080e1d7981 */
/* 0x000ea4000c1e1900 */
/*04b0*/ FADD R29, R24, R29 ; /* 0x0000001d181d7221 */
/* 0x004fc40000000000 */
/*04c0*/ LDG.E R24, [R16.64+0xc] ; /* 0x00000c0810187981 */
/* 0x000e28000c1e1900 */
/*04d0*/ STG.E [R16.64+0x8], R29 ; /* 0x0000081d10007986 */
/* 0x0005e8000c101908 */
/*04e0*/ LDG.E R26, [R14.64+0xc] ; /* 0x00000c080e1a7981 */
/* 0x000e24000c1e1900 */
/*04f0*/ FADD R25, R24, R26 ; /* 0x0000001a18197221 */
/* 0x001fc40000000000 */
/*0500*/ LDG.E R24, [R16.64+0x10] ; /* 0x0000100810187981 */
/* 0x000e68000c1e1900 */
/*0510*/ STG.E [R16.64+0xc], R25 ; /* 0x00000c1910007986 */
/* 0x0001e8000c101908 */
/*0520*/ LDG.E R26, [R14.64+0x10] ; /* 0x000010080e1a7981 */
/* 0x000e64000c1e1900 */
/*0530*/ FADD R27, R24, R26 ; /* 0x0000001a181b7221 */
/* 0x002fc40000000000 */
/*0540*/ LDG.E R24, [R16.64+0x14] ; /* 0x0000140810187981 */
/* 0x000ea8000c1e1900 */
/*0550*/ STG.E [R16.64+0x10], R27 ; /* 0x0000101b10007986 */
/* 0x0003e8000c101908 */
/*0560*/ LDG.E R26, [R14.64+0x14] ; /* 0x000014080e1a7981 */
/* 0x000ea4000c1e1900 */
/*0570*/ FADD R29, R24, R26 ; /* 0x0000001a181d7221 */
/* 0x004fc40000000000 */
/*0580*/ LDG.E R24, [R16.64+0x18] ; /* 0x0000180810187981 */
/* 0x000e28000c1e1900 */
/*0590*/ STG.E [R16.64+0x14], R29 ; /* 0x0000141d10007986 */
/* 0x0005e8000c101908 */
/*05a0*/ LDG.E R26, [R14.64+0x18] ; /* 0x000018080e1a7981 */
/* 0x000e24000c1e1900 */
/*05b0*/ FADD R25, R24, R26 ; /* 0x0000001a18197221 */
/* 0x001fc40000000000 */
/*05c0*/ LDG.E R24, [R16.64+0x1c] ; /* 0x00001c0810187981 */
/* 0x000e68000c1e1900 */
/*05d0*/ STG.E [R16.64+0x18], R25 ; /* 0x0000181910007986 */
/* 0x0001e8000c101908 */
/*05e0*/ LDG.E R26, [R14.64+0x1c] ; /* 0x00001c080e1a7981 */
/* 0x000e64000c1e1900 */
/*05f0*/ FADD R27, R24, R26 ; /* 0x0000001a181b7221 */
/* 0x002fc40000000000 */
/*0600*/ LDG.E R24, [R16.64+0x20] ; /* 0x0000200810187981 */
/* 0x000ea8000c1e1900 */
/*0610*/ STG.E [R16.64+0x1c], R27 ; /* 0x00001c1b10007986 */
/* 0x0003e8000c101908 */
/*0620*/ LDG.E R26, [R14.64+0x20] ; /* 0x000020080e1a7981 */
/* 0x000ea4000c1e1900 */
/*0630*/ FADD R29, R24, R26 ; /* 0x0000001a181d7221 */
/* 0x004fc40000000000 */
/*0640*/ LDG.E R24, [R16.64+0x24] ; /* 0x0000240810187981 */
/* 0x000e28000c1e1900 */
/*0650*/ STG.E [R16.64+0x20], R29 ; /* 0x0000201d10007986 */
/* 0x0005e8000c101908 */
/*0660*/ LDG.E R26, [R14.64+0x24] ; /* 0x000024080e1a7981 */
/* 0x000e24000c1e1900 */
/*0670*/ FADD R25, R24, R26 ; /* 0x0000001a18197221 */
/* 0x001fc40000000000 */
/*0680*/ LDG.E R24, [R16.64+0x28] ; /* 0x0000280810187981 */
/* 0x000e68000c1e1900 */
/*0690*/ STG.E [R16.64+0x24], R25 ; /* 0x0000241910007986 */
/* 0x0001e8000c101908 */
/*06a0*/ LDG.E R26, [R14.64+0x28] ; /* 0x000028080e1a7981 */
/* 0x000e64000c1e1900 */
/*06b0*/ FADD R27, R24, R26 ; /* 0x0000001a181b7221 */
/* 0x002fc40000000000 */
/*06c0*/ LDG.E R24, [R16.64+0x2c] ; /* 0x00002c0810187981 */
/* 0x000ea8000c1e1900 */
/*06d0*/ STG.E [R16.64+0x28], R27 ; /* 0x0000281b10007986 */
/* 0x0003e8000c101908 */
/*06e0*/ LDG.E R26, [R14.64+0x2c] ; /* 0x00002c080e1a7981 */
/* 0x000ea4000c1e1900 */
/*06f0*/ FADD R29, R24, R26 ; /* 0x0000001a181d7221 */
/* 0x004fc40000000000 */
/*0700*/ LDG.E R24, [R16.64+0x30] ; /* 0x0000300810187981 */
/* 0x000e28000c1e1900 */
/*0710*/ STG.E [R16.64+0x2c], R29 ; /* 0x00002c1d10007986 */
/* 0x0005e8000c101908 */
/*0720*/ LDG.E R26, [R14.64+0x30] ; /* 0x000030080e1a7981 */
/* 0x000e24000c1e1900 */
/*0730*/ FADD R25, R24, R26 ; /* 0x0000001a18197221 */
/* 0x001fc40000000000 */
/*0740*/ LDG.E R24, [R16.64+0x34] ; /* 0x0000340810187981 */
/* 0x000e68000c1e1900 */
/*0750*/ STG.E [R16.64+0x30], R25 ; /* 0x0000301910007986 */
/* 0x0001e8000c101908 */
/*0760*/ LDG.E R26, [R14.64+0x34] ; /* 0x000034080e1a7981 */
/* 0x000e64000c1e1900 */
/*0770*/ FADD R27, R24, R26 ; /* 0x0000001a181b7221 */
/* 0x002fc40000000000 */
/*0780*/ LDG.E R24, [R16.64+0x38] ; /* 0x0000380810187981 */
/* 0x000ea8000c1e1900 */
/*0790*/ STG.E [R16.64+0x34], R27 ; /* 0x0000341b10007986 */
/* 0x0003e8000c101908 */
/*07a0*/ LDG.E R26, [R14.64+0x38] ; /* 0x000038080e1a7981 */
/* 0x000ea2000c1e1900 */
/*07b0*/ IADD3 R23, P6, R23, 0x40, RZ ; /* 0x0000004017177810 */
/* 0x000fe40007fde0ff */
/*07c0*/ IADD3 R18, R18, -0x10, RZ ; /* 0xfffffff012127810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ FADD R29, R24, R26 ; /* 0x0000001a181d7221 */
/* 0x004fc40000000000 */
/*07e0*/ LDG.E R24, [R16.64+0x3c] ; /* 0x00003c0810187981 */
/* 0x000e28000c1e1900 */
/*07f0*/ STG.E [R16.64+0x38], R29 ; /* 0x0000381d10007986 */
/* 0x0003e8000c101908 */
/*0800*/ LDG.E R26, [R14.64+0x3c] ; /* 0x00003c080e1a7981 */
/* 0x000e22000c1e1900 */
/*0810*/ IADD3.X R22, RZ, R22, RZ, P6, !PT ; /* 0x00000016ff167210 */
/* 0x000fe400037fe4ff */
/*0820*/ ISETP.GT.AND P6, PT, R18, 0xc, PT ; /* 0x0000000c1200780c */
/* 0x000fc40003fc4270 */
/*0830*/ IADD3 R20, R20, 0x10, RZ ; /* 0x0000001014147810 */
/* 0x000fe20007ffe0ff */
/*0840*/ FADD R25, R24, R26 ; /* 0x0000001a18197221 */
/* 0x001fe20000000000 */
/*0850*/ IADD3 R24, P5, R14, 0x40, RZ ; /* 0x000000400e187810 */
/* 0x000fc80007fbe0ff */
/*0860*/ STG.E [R16.64+0x3c], R25 ; /* 0x00003c1910007986 */
/* 0x0003e2000c101908 */
/*0870*/ IMAD.X R15, RZ, RZ, R15, P5 ; /* 0x000000ffff0f7224 */
/* 0x000fe200028e060f */
/*0880*/ MOV R14, R24 ; /* 0x00000018000e7202 */
/* 0x000fc60000000f00 */
/*0890*/ @P6 BRA 0x3e0 ; /* 0xfffffb4000006947 */
/* 0x000fea000383ffff */
/*08a0*/ ISETP.GT.AND P5, PT, R18, 0x4, PT ; /* 0x000000041200780c */
/* 0x000fda0003fa4270 */
/*08b0*/ @!P5 BRA 0xb80 ; /* 0x000002c00000d947 */
/* 0x000fea0003800000 */
/*08c0*/ MOV R17, R22 ; /* 0x0000001600117202 */
/* 0x002fe20000000f00 */
/*08d0*/ IMAD.MOV.U32 R16, RZ, RZ, R23 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0017 */
/*08e0*/ LDG.E R25, [R14.64] ; /* 0x000000080e197981 */
/* 0x000ea6000c1e1900 */
/*08f0*/ IMAD.WIDE R16, R21, 0x4, R16 ; /* 0x0000000415107825 */
/* 0x000fca00078e0210 */
/*0900*/ LDG.E R24, [R16.64] ; /* 0x0000000810187981 */
/* 0x000ea4000c1e1900 */
/*0910*/ FADD R25, R24, R25 ; /* 0x0000001918197221 */
/* 0x004fe40000000000 */
/*0920*/ LDG.E R24, [R16.64+0x4] ; /* 0x0000040810187981 */
/* 0x000ea8000c1e1900 */
/*0930*/ STG.E [R16.64], R25 ; /* 0x0000001910007986 */
/* 0x0001e8000c101908 */
/*0940*/ LDG.E R27, [R14.64+0x4] ; /* 0x000004080e1b7981 */
/* 0x000ea4000c1e1900 */
/*0950*/ FADD R27, R24, R27 ; /* 0x0000001b181b7221 */
/* 0x004fc40000000000 */
/*0960*/ LDG.E R24, [R16.64+0x8] ; /* 0x0000080810187981 */
/* 0x000ea8000c1e1900 */
/*0970*/ STG.E [R16.64+0x4], R27 ; /* 0x0000041b10007986 */
/* 0x0003e8000c101908 */
/*0980*/ LDG.E R29, [R14.64+0x8] ; /* 0x000008080e1d7981 */
/* 0x000ea4000c1e1900 */
/*0990*/ FADD R29, R24, R29 ; /* 0x0000001d181d7221 */
/* 0x004fc40000000000 */
/*09a0*/ LDG.E R24, [R16.64+0xc] ; /* 0x00000c0810187981 */
/* 0x000e28000c1e1900 */
/*09b0*/ STG.E [R16.64+0x8], R29 ; /* 0x0000081d10007986 */
/* 0x0005e8000c101908 */
/*09c0*/ LDG.E R26, [R14.64+0xc] ; /* 0x00000c080e1a7981 */
/* 0x000e24000c1e1900 */
/*09d0*/ FADD R25, R24, R26 ; /* 0x0000001a18197221 */
/* 0x001fc40000000000 */
/*09e0*/ LDG.E R24, [R16.64+0x10] ; /* 0x0000100810187981 */
/* 0x000e68000c1e1900 */
/*09f0*/ STG.E [R16.64+0xc], R25 ; /* 0x00000c1910007986 */
/* 0x0001e8000c101908 */
/*0a00*/ LDG.E R26, [R14.64+0x10] ; /* 0x000010080e1a7981 */
/* 0x000e64000c1e1900 */
/*0a10*/ FADD R27, R24, R26 ; /* 0x0000001a181b7221 */
/* 0x002fc40000000000 */
/*0a20*/ LDG.E R24, [R16.64+0x14] ; /* 0x0000140810187981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ STG.E [R16.64+0x10], R27 ; /* 0x0000101b10007986 */
/* 0x0003e8000c101908 */
/*0a40*/ LDG.E R26, [R14.64+0x14] ; /* 0x000014080e1a7981 */
/* 0x000ea4000c1e1900 */
/*0a50*/ FADD R29, R24, R26 ; /* 0x0000001a181d7221 */
/* 0x004fc40000000000 */
/*0a60*/ LDG.E R24, [R16.64+0x18] ; /* 0x0000180810187981 */
/* 0x000e28000c1e1900 */
/*0a70*/ STG.E [R16.64+0x14], R29 ; /* 0x0000141d10007986 */
/* 0x0005e8000c101908 */
/*0a80*/ LDG.E R26, [R14.64+0x18] ; /* 0x000018080e1a7981 */
/* 0x000e24000c1e1900 */
/*0a90*/ FADD R25, R24, R26 ; /* 0x0000001a18197221 */
/* 0x001fc40000000000 */
/*0aa0*/ LDG.E R24, [R16.64+0x1c] ; /* 0x00001c0810187981 */
/* 0x000e68000c1e1900 */
/*0ab0*/ STG.E [R16.64+0x18], R25 ; /* 0x0000181910007986 */
/* 0x0001e8000c101908 */
/*0ac0*/ LDG.E R26, [R14.64+0x1c] ; /* 0x00001c080e1a7981 */
/* 0x000e62000c1e1900 */
/*0ad0*/ IADD3 R23, P5, R23, 0x20, RZ ; /* 0x0000002017177810 */
/* 0x000fe40007fbe0ff */
/*0ae0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0af0*/ IADD3 R20, R20, 0x8, RZ ; /* 0x0000000814147810 */
/* 0x000fe40007ffe0ff */
/*0b00*/ IADD3 R18, R18, -0x8, RZ ; /* 0xfffffff812127810 */
/* 0x000fe40007ffe0ff */
/*0b10*/ IADD3.X R22, RZ, R22, RZ, P5, !PT ; /* 0x00000016ff167210 */
/* 0x000fe20002ffe4ff */
/*0b20*/ FADD R27, R24, R26 ; /* 0x0000001a181b7221 */
/* 0x002fca0000000000 */
/*0b30*/ STG.E [R16.64+0x1c], R27 ; /* 0x00001c1b10007986 */
/* 0x0001e2000c101908 */
/*0b40*/ IADD3 R24, P6, R14, 0x20, RZ ; /* 0x000000200e187810 */
/* 0x000fca0007fde0ff */
/*0b50*/ IMAD.X R29, RZ, RZ, R15, P6 ; /* 0x000000ffff1d7224 */
/* 0x004fe400030e060f */
/*0b60*/ IMAD.MOV.U32 R14, RZ, RZ, R24 ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e0018 */
/*0b70*/ MOV R15, R29 ; /* 0x0000001d000f7202 */
/* 0x000fe40000000f00 */
/*0b80*/ ISETP.NE.OR P0, PT, R18, RZ, P0 ; /* 0x000000ff1200720c */
/* 0x000fda0000705670 */
/*0b90*/ @!P0 BRA 0xd60 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0ba0*/ MOV R17, R22 ; /* 0x0000001600117202 */
/* 0x003fe20000000f00 */
/*0bb0*/ IMAD.MOV.U32 R16, RZ, RZ, R23 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0017 */
/*0bc0*/ LDG.E R25, [R14.64] ; /* 0x000000080e197981 */
/* 0x000ea6000c1e1900 */
/*0bd0*/ IMAD.WIDE R16, R21, 0x4, R16 ; /* 0x0000000415107825 */
/* 0x000fca00078e0210 */
/*0be0*/ LDG.E R24, [R16.64] ; /* 0x0000000810187981 */
/* 0x000ea4000c1e1900 */
/*0bf0*/ FADD R25, R24, R25 ; /* 0x0000001918197221 */
/* 0x004fe40000000000 */
/*0c00*/ LDG.E R24, [R16.64+0x4] ; /* 0x0000040810187981 */
/* 0x000ea8000c1e1900 */
/*0c10*/ STG.E [R16.64], R25 ; /* 0x0000001910007986 */
/* 0x0001e8000c101908 */
/*0c20*/ LDG.E R27, [R14.64+0x4] ; /* 0x000004080e1b7981 */
/* 0x000ea4000c1e1900 */
/*0c30*/ FADD R27, R24, R27 ; /* 0x0000001b181b7221 */
/* 0x004fc40000000000 */
/*0c40*/ LDG.E R24, [R16.64+0x8] ; /* 0x0000080810187981 */
/* 0x000ea8000c1e1900 */
/*0c50*/ STG.E [R16.64+0x4], R27 ; /* 0x0000041b10007986 */
/* 0x0003e8000c101908 */
/*0c60*/ LDG.E R29, [R14.64+0x8] ; /* 0x000008080e1d7981 */
/* 0x000ea2000c1e1900 */
/*0c70*/ IADD3 R18, R18, -0x4, RZ ; /* 0xfffffffc12127810 */
/* 0x000fe20007ffe0ff */
/*0c80*/ FADD R29, R24, R29 ; /* 0x0000001d181d7221 */
/* 0x004fc40000000000 */
/*0c90*/ LDG.E R24, [R16.64+0xc] ; /* 0x00000c0810187981 */
/* 0x000e28000c1e1900 */
/*0ca0*/ STG.E [R16.64+0x8], R29 ; /* 0x0000081d10007986 */
/* 0x0003e8000c101908 */
/*0cb0*/ LDG.E R26, [R14.64+0xc] ; /* 0x00000c080e1a7981 */
/* 0x000e22000c1e1900 */
/*0cc0*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe40003f05270 */
/*0cd0*/ IADD3 R23, P5, R23, 0x10, RZ ; /* 0x0000001017177810 */
/* 0x000fc40007fbe0ff */
/*0ce0*/ IADD3 R20, R20, 0x4, RZ ; /* 0x0000000414147810 */
/* 0x000fe40007ffe0ff */
/*0cf0*/ IADD3.X R22, RZ, R22, RZ, P5, !PT ; /* 0x00000016ff167210 */
/* 0x000fe20002ffe4ff */
/*0d00*/ FADD R25, R24, R26 ; /* 0x0000001a18197221 */
/* 0x001fe20000000000 */
/*0d10*/ IADD3 R24, P6, R14, 0x10, RZ ; /* 0x000000100e187810 */
/* 0x000fc80007fde0ff */
/*0d20*/ STG.E [R16.64+0xc], R25 ; /* 0x00000c1910007986 */
/* 0x0003e2000c101908 */
/*0d30*/ IMAD.X R15, RZ, RZ, R15, P6 ; /* 0x000000ffff0f7224 */
/* 0x000fe400030e060f */
/*0d40*/ IMAD.MOV.U32 R14, RZ, RZ, R24 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0018 */
/*0d50*/ @P0 BRA 0xba0 ; /* 0xfffffe4000000947 */
/* 0x002fea000383ffff */
/*0d60*/ ISETP.NE.AND P0, PT, RZ, UR7, PT ; /* 0x00000007ff007c0c */
/* 0x000fda000bf05270 */
/*0d70*/ @!P0 BRA 0xf00 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0d80*/ MOV R14, UR10 ; /* 0x0000000a000e7c02 */
/* 0x000fe20008000f00 */
/*0d90*/ IMAD.U32 R15, RZ, RZ, UR11 ; /* 0x0000000bff0f7e24 */
/* 0x000fe2000f8e00ff */
/*0da0*/ IADD3 R17, R19, R20, RZ ; /* 0x0000001413117210 */
/* 0x003fe20007ffe0ff */
/*0db0*/ IMAD.IADD R21, R21, 0x1, R20 ; /* 0x0000000115157824 */
/* 0x000fc800078e0214 */
/*0dc0*/ IMAD.WIDE R16, R17, 0x4, R12 ; /* 0x0000000411107825 */
/* 0x000fc800078e020c */
/*0dd0*/ IMAD.WIDE R14, R21, 0x4, R14 ; /* 0x00000004150e7825 */
/* 0x000fe200078e020e */
/*0de0*/ LDG.E R19, [R16.64] ; /* 0x0000000810137981 */
/* 0x000ea8000c1e1900 */
/*0df0*/ LDG.E R18, [R14.64] ; /* 0x000000080e127981 */
/* 0x000ea2000c1e1900 */
/*0e00*/ UISETP.NE.AND UP0, UPT, UR7, 0x1, UPT ; /* 0x000000010700788c */
/* 0x000fcc000bf05270 */
/*0e10*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f008 */
/*0e20*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x004fca0000000000 */
/*0e30*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0001ee000c101908 */
/*0e40*/ @!P0 BRA 0xf00 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0e50*/ LDG.E R18, [R14.64+0x4] ; /* 0x000004080e127981 */
/* 0x000ea8000c1e1900 */
/*0e60*/ LDG.E R19, [R16.64+0x4] ; /* 0x0000040810137981 */
/* 0x001ea2000c1e1900 */
/*0e70*/ UISETP.NE.AND UP0, UPT, UR7, 0x2, UPT ; /* 0x000000020700788c */
/* 0x000fcc000bf05270 */
/*0e80*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f008 */
/*0e90*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x004fca0000000000 */
/*0ea0*/ STG.E [R14.64+0x4], R19 ; /* 0x000004130e007986 */
/* 0x0001ee000c101908 */
/*0eb0*/ @!P0 BRA 0xf00 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0ec0*/ LDG.E R17, [R16.64+0x8] ; /* 0x0000080810117981 */
/* 0x000ea8000c1e1900 */
/*0ed0*/ LDG.E R18, [R14.64+0x8] ; /* 0x000008080e127981 */
/* 0x000ea4000c1e1900 */
/*0ee0*/ FADD R19, R18, R17 ; /* 0x0000001112137221 */
/* 0x005fca0000000000 */
/*0ef0*/ STG.E [R14.64+0x8], R19 ; /* 0x000008130e007986 */
/* 0x0001e4000c101908 */
/*0f00*/ @!P2 BRA 0x270 ; /* 0xfffff3600000a947 */
/* 0x000fea000383ffff */
/*0f10*/ @!P4 BRA 0x230 ; /* 0xfffff3100000c947 */
/* 0x000fea000383ffff */
/*0f20*/ ULEA UR10, UP0, UR5, UR10, 0x2 ; /* 0x0000000a050a7291 */
/* 0x000fe2000f80103f */
/*0f30*/ LEA R0, P0, R5, R0, 0x2 ; /* 0x0000000005007211 */
/* 0x000fe400078010ff */
/*0f40*/ LEA R12, P2, R2, R12, 0x2 ; /* 0x0000000c020c7211 */
/* 0x000fe200078410ff */
/*0f50*/ UIADD3.X UR11, UR11, UR6, URZ, UP0, !UPT ; /* 0x000000060b0b7290 */
/* 0x000fe400087fe43f */
/*0f60*/ IMAD.X R3, R3, 0x1, R8, P0 ; /* 0x0000000103037824 */
/* 0x000fe200000e0608 */
/*0f70*/ IADD3.X R13, R13, R7, RZ, P2, !PT ; /* 0x000000070d0d7210 */
/* 0x000fe200017fe4ff */
/*0f80*/ @!P3 BRA 0x1f0 ; /* 0xfffff2600000b947 */
/* 0x000fea000383ffff */
/*0f90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fa0*/ BRA 0xfa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20group_point_grad_gpuiiiiiPKfPKiPf
.globl _Z20group_point_grad_gpuiiiiiPKfPKiPf
.p2align 8
.type _Z20group_point_grad_gpuiiiiiPKfPKiPf,@function
_Z20group_point_grad_gpuiiiiiPKfPKiPf:
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_12
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x4
s_load_b128 s[8:11], s[0:1], 0x18
s_load_b64 s[12:13], s[0:1], 0x28
s_mov_b32 s15, 0
s_mov_b32 s28, 0
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s6, 0
s_mul_i32 s20, s7, s6
s_cselect_b32 s0, -1, 0
s_cmp_gt_i32 s7, 0
v_cndmask_b32_e64 v0, 0, 1, s0
s_cselect_b32 s0, -1, 0
s_cmp_gt_i32 s5, 0
v_cndmask_b32_e64 v1, 0, 1, s0
s_cselect_b32 s0, -1, 0
s_mul_i32 s16, s5, s4
v_cndmask_b32_e64 v2, 0, 1, s0
s_mul_i32 s18, s20, s5
v_cmp_ne_u32_e64 s0, 1, v0
v_cmp_ne_u32_e64 s1, 1, v1
v_mov_b32_e32 v0, 0
v_cmp_ne_u32_e64 s2, 1, v2
s_ashr_i32 s21, s20, 31
s_ashr_i32 s19, s18, 31
s_ashr_i32 s17, s16, 31
s_lshl_b64 s[18:19], s[18:19], 2
s_lshl_b64 s[16:17], s[16:17], 2
s_mul_i32 s4, s7, s5
s_lshl_b64 s[20:21], s[20:21], 2
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_add_u32 s10, s10, s20
s_addc_u32 s11, s11, s21
s_add_i32 s28, s28, 1
s_add_u32 s12, s12, s16
s_addc_u32 s13, s13, s17
s_add_u32 s8, s8, s18
s_addc_u32 s9, s9, s19
s_cmp_eq_u32 s28, s3
s_cbranch_scc1 .LBB0_12
.LBB0_3:
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_2
s_mov_b32 s29, 0
s_mov_b32 s30, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_add_i32 s30, s30, 1
s_add_i32 s29, s29, s4
s_cmp_eq_u32 s30, s6
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_and_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_5
s_mul_i32 s31, s30, s7
s_mov_b32 s33, 0
s_mov_b32 s22, s29
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_add_i32 s33, s33, 1
s_add_i32 s22, s22, s5
s_cmp_eq_u32 s33, s7
s_cbranch_scc1 .LBB0_5
.LBB0_9:
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_8
s_ashr_i32 s23, s22, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[24:25], s[22:23], 2
s_add_u32 s24, s8, s24
s_addc_u32 s25, s9, s25
s_add_i32 s14, s33, s31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[26:27], s[14:15], 2
s_add_u32 s26, s10, s26
s_addc_u32 s27, s11, s27
s_load_b32 s14, s[26:27], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s26, s14, s5
s_mov_b32 s14, s5
s_ashr_i32 s27, s26, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[26:27], s[26:27], 2
s_add_u32 s26, s12, s26
s_addc_u32 s27, s13, s27
.LBB0_11:
s_clause 0x1
global_load_b32 v1, v0, s[24:25]
global_load_b32 v2, v0, s[26:27]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[26:27]
s_add_u32 s26, s26, 4
s_addc_u32 s27, s27, 0
s_add_u32 s24, s24, 4
s_addc_u32 s25, s25, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc0 .LBB0_11
s_branch .LBB0_8
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20group_point_grad_gpuiiiiiPKfPKiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 34
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20group_point_grad_gpuiiiiiPKfPKiPf, .Lfunc_end0-_Z20group_point_grad_gpuiiiiiPKfPKiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20group_point_grad_gpuiiiiiPKfPKiPf
.private_segment_fixed_size: 0
.sgpr_count: 36
.sgpr_spill_count: 0
.symbol: _Z20group_point_grad_gpuiiiiiPKfPKiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000781ba_00000000-6_group_point_grad_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
.type _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf, @function
_Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq 216(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20group_point_grad_gpuiiiiiPKfPKiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf, .-_Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
.globl _Z20group_point_grad_gpuiiiiiPKfPKiPf
.type _Z20group_point_grad_gpuiiiiiPKfPKiPf, @function
_Z20group_point_grad_gpuiiiiiPKfPKiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20group_point_grad_gpuiiiiiPKfPKiPf, .-_Z20group_point_grad_gpuiiiiiPKfPKiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20group_point_grad_gpuiiiiiPKfPKiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20group_point_grad_gpuiiiiiPKfPKiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "group_point_grad_gpu.hip"
.globl _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf # -- Begin function _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.p2align 4, 0x90
.type _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf,@function
_Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf: # @_Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20group_point_grad_gpuiiiiiPKfPKiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf, .Lfunc_end0-_Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20group_point_grad_gpuiiiiiPKfPKiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20group_point_grad_gpuiiiiiPKfPKiPf,@object # @_Z20group_point_grad_gpuiiiiiPKfPKiPf
.section .rodata,"a",@progbits
.globl _Z20group_point_grad_gpuiiiiiPKfPKiPf
.p2align 3, 0x0
_Z20group_point_grad_gpuiiiiiPKfPKiPf:
.quad _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.size _Z20group_point_grad_gpuiiiiiPKfPKiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20group_point_grad_gpuiiiiiPKfPKiPf"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20group_point_grad_gpuiiiiiPKfPKiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h> // needed for the function sqrtf()
#define TILE_SIZE 64 // NB // Block SIZE
/*
* Function to perform rank-k update
* half of the threads working
*/
__device__ void ssyrk_tile(float* rA1, float* rA2)
{
// int row = blockIdx.y * TILE_SIZE + threadIdx.y;
// int column = blockIdx.x * TILE_SIZE + threadIdx.x;
int row = threadIdx.y;
int column = threadIdx.x;
if(column <= row)
{
float updatedValue = rA2[row * TILE_SIZE + column];
for(int k=0; k<TILE_SIZE; k++)
{
updatedValue -= rA1[row * TILE_SIZE + k] * rA1[column * TILE_SIZE + k];
}
rA2[row * TILE_SIZE + column] = updatedValue;
}
}
/*
* Function to perform general matrix multiplication
* DOUBT: I think calculation is given wrong in paper it should be rA2[k][n]
*/
__device__ void sgemm_tile(const float* rA1, const float* rA2, float* rA3)
{
// int row = blockIdx.y * TILE_SIZE + threadIdx.y;
// int column = blockIdx.x * TILE_SIZE + threadIdx.x;
int row = threadIdx.y;
int column = threadIdx.x;
float updatedValue = rA3[row * TILE_SIZE + column];
for(int i=0; i<TILE_SIZE; i++)
{
updatedValue -= rA1[row * TILE_SIZE + i] * rA2[i * TILE_SIZE + column];
}
rA3[row * TILE_SIZE + column] = updatedValue;
}
/*
* Function to store full tile from shared memory to global memory
*/
__device__ void store_full(const float* s_data, float* g_data)
{
int g_row = blockIdx.y * TILE_SIZE + threadIdx.y;
int g_column = blockIdx.x * TILE_SIZE + threadIdx.x;
int l_row = threadIdx.y;
int l_column = threadIdx.x;
g_data[g_row * TILE_SIZE + g_column] = s_data[l_row * TILE_SIZE + l_column];
__syncthreads();
}
/*
* Function to store lower triangular tile from shared memory to global memory
*/
__device__ void store_lower(const float* s_data, float* g_data)
{
int g_row = blockIdx.y * TILE_SIZE + threadIdx.y;
int g_column = blockIdx.x * TILE_SIZE + threadIdx.x;
int l_row = threadIdx.y;
int l_column = threadIdx.x;
if(l_column <= l_row)
g_data[g_row * TILE_SIZE + g_column] = s_data[l_row * TILE_SIZE + l_column];
else
g_data[g_row * TILE_SIZE + g_column] = 0;
__syncthreads();
}
/*
* Function to perform Choleshky Factorization for a tile
*/
__device__ void spotrf_tile(float* t_A)
{
// int ty = blockIdx.x*blockDim.x + threadIdx.x; // col
// int tx = blockIdx.y*blockDim.y + threadIdx.y; // row
int ty = threadIdx.x; // col
int tx = threadIdx.y; // row
for(int k{0};k<TILE_SIZE;k++){
// square root of diagonal elements
if(tx==0 && ty==0)
t_A[k*TILE_SIZE + k] = sqrtf(t_A[k*TILE_SIZE + k]);
__syncthreads();
// division step done parallaly
if(ty<=tx && tx<TILE_SIZE - 1 && ty<TILE_SIZE - 1 && ty == k)
{
t_A[(tx+1)*TILE_SIZE + k]/= t_A[k*TILE_SIZE + k];
}
__syncthreads();
if(ty<=tx && tx<TILE_SIZE - 1 && ty<TILE_SIZE - 1 && ty >= k)
{
t_A[(tx+1)*TILE_SIZE + (ty+1)]-= t_A[(tx+1)*TILE_SIZE + k]*t_A[(ty+1)*TILE_SIZE + k];
}
__syncthreads();
}
}
/*
* Function to perform triangular solve for a tile
*/
__device__ void strsm_tile(float *t_A1, float *t_A2)
{
// t_A2 is current unkonown
// int ty = blockIdx.x*TILE_SIZE + threadIdx.x;
// int tx = blockIdx.y*TILE_SIZE + threadIdx.y;
int ty = threadIdx.x;
int tx = threadIdx.y;
for(int i{0};i<TILE_SIZE;i++){
if(ty==0){
t_A2[tx*TILE_SIZE + i]/= t_A1[i*TILE_SIZE + i];
}
__syncthreads();
if(ty>i && i<TILE_SIZE-1)
{
t_A2[tx*TILE_SIZE+ty]-= t_A2[tx*TILE_SIZE + i]*t_A1[ty*TILE_SIZE + i];
}
__syncthreads();
}
}
/*
* Function to load a full tile from global memory to shared memory
*/
__device__ void load_full(float *t_A,float * S_A)
{
// assigning a 2-D array in shared memory
int g_ty = blockIdx.x*blockDim.x + threadIdx.x; // col
int g_tx = blockIdx.y*blockDim.y + threadIdx.y; // row
int l_tx = threadIdx.x;
int l_ty = threadIdx.y;
if(l_tx<TILE_SIZE && l_ty<TILE_SIZE)
S_A[l_tx * TILE_SIZE + l_ty] = t_A[g_tx*TILE_SIZE + g_ty];
__syncthreads();
}
/*
* Left looking kernel code (without loop unrolling)
*/
__global__ void left_looking_kernel(float *g_in, int N)
{
// ((N / NB) + 2) * sizeof(TILE) amount of shared memory
extern __shared__ float s_current_panel[];
int l_tid = threadIdx.y * (blockDim.x) + threadIdx.x; // local thread id
int tx = threadIdx.x;
int ty = threadIdx.y;
// i: current panel
for(int i=0; i<(N / TILE_SIZE); i++)
{
// loading current panel in shared memory
for(int j=0; j<(N / TILE_SIZE); j++)
{
int access_row = j * blockDim.y + threadIdx.y;
s_current_panel[j * TILE_SIZE * TILE_SIZE + l_tid] = g_in[access_row * N + i * TILE_SIZE + tx];
}
__syncthreads();
// UPDATE CURRENT PANEL using preceding panels
// j: preceding panel no.
for(int j=0; j<i; j++)
{
int row = i * TILE_SIZE + ty;
// Loading data for rank-k update in shared memory
s_current_panel[N * TILE_SIZE + l_tid] = g_in[row * N + j * TILE_SIZE + tx];
__syncthreads();
// Rank-k update
float *rA1 = &s_current_panel[N*TILE_SIZE + 0];
float *rA2 = &s_current_panel[i * TILE_SIZE * TILE_SIZE];
ssyrk_tile(rA1, rA2);
__syncthreads();
// Applying SGEMM
for(int k=i+1; k<(N / TILE_SIZE); k++)
{
// Loading data for sgemm in shared memory
int access_row = (k) * TILE_SIZE + ty;
s_current_panel[(N + 1) * TILE_SIZE + l_tid] = g_in[access_row * N + j * TILE_SIZE + tx];
__syncthreads();
// sgemm
float *rA1 = &s_current_panel[N * TILE_SIZE];
float *rA2 = &s_current_panel[(N + 1) * TILE_SIZE];
float *rA3 = &s_current_panel[k * TILE_SIZE * TILE_SIZE];
sgemm_tile(rA1, rA2, rA3);
__syncthreads();
}
}
// FACTORIZE CURRENT PANEL
// applying spotrf on the tile (i, i)
float *rA1 = &s_current_panel[i * TILE_SIZE * TILE_SIZE];
spotrf_tile(rA1);
__syncthreads();
// Applying TRSM
for(int k=i+1; k<(N / TILE_SIZE); k++)
{
// trsm
float *rA2 = &s_current_panel[k * TILE_SIZE * TILE_SIZE];
strsm_tile(rA1, rA2);
__syncthreads();
}
// STORING the current panel back in the global memory
for (int k=0; k<(N / TILE_SIZE); k++)
{
// store zero for tiles above the tile (i, i)
if(k<i)
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = 0.0;
}
else
{
// store lower for tile (i, i)
if(k == i)
{
if(tx <= ty)
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = s_current_panel[k * TILE_SIZE * TILE_SIZE + ty * TILE_SIZE + tx];
}
else
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = 0.0;
}
}
else // store full for tiles below the tile (i, i)
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = s_current_panel[k * TILE_SIZE * TILE_SIZE + ty * TILE_SIZE + tx];
}
}
}
__syncthreads();
}
} | .file "tmpxft_0011ccdf_00000000-6_left_looking.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10ssyrk_tilePfS_
.type _Z10ssyrk_tilePfS_, @function
_Z10ssyrk_tilePfS_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10ssyrk_tilePfS_, .-_Z10ssyrk_tilePfS_
.globl _Z10sgemm_tilePKfS0_Pf
.type _Z10sgemm_tilePKfS0_Pf, @function
_Z10sgemm_tilePKfS0_Pf:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10sgemm_tilePKfS0_Pf, .-_Z10sgemm_tilePKfS0_Pf
.globl _Z10store_fullPKfPf
.type _Z10store_fullPKfPf, @function
_Z10store_fullPKfPf:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10store_fullPKfPf, .-_Z10store_fullPKfPf
.globl _Z11store_lowerPKfPf
.type _Z11store_lowerPKfPf, @function
_Z11store_lowerPKfPf:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z11store_lowerPKfPf, .-_Z11store_lowerPKfPf
.globl _Z11spotrf_tilePf
.type _Z11spotrf_tilePf, @function
_Z11spotrf_tilePf:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z11spotrf_tilePf, .-_Z11spotrf_tilePf
.globl _Z10strsm_tilePfS_
.type _Z10strsm_tilePfS_, @function
_Z10strsm_tilePfS_:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z10strsm_tilePfS_, .-_Z10strsm_tilePfS_
.globl _Z9load_fullPfS_
.type _Z9load_fullPfS_, @function
_Z9load_fullPfS_:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z9load_fullPfS_, .-_Z9load_fullPfS_
.globl _Z40__device_stub__Z19left_looking_kernelPfiPfi
.type _Z40__device_stub__Z19left_looking_kernelPfiPfi, @function
_Z40__device_stub__Z19left_looking_kernelPfiPfi:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19left_looking_kernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z40__device_stub__Z19left_looking_kernelPfiPfi, .-_Z40__device_stub__Z19left_looking_kernelPfiPfi
.globl _Z19left_looking_kernelPfi
.type _Z19left_looking_kernelPfi, @function
_Z19left_looking_kernelPfi:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z19left_looking_kernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z19left_looking_kernelPfi, .-_Z19left_looking_kernelPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19left_looking_kernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19left_looking_kernelPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h> // needed for the function sqrtf()
#define TILE_SIZE 64 // NB // Block SIZE
/*
* Function to perform rank-k update
* half of the threads working
*/
__device__ void ssyrk_tile(float* rA1, float* rA2)
{
// int row = blockIdx.y * TILE_SIZE + threadIdx.y;
// int column = blockIdx.x * TILE_SIZE + threadIdx.x;
int row = threadIdx.y;
int column = threadIdx.x;
if(column <= row)
{
float updatedValue = rA2[row * TILE_SIZE + column];
for(int k=0; k<TILE_SIZE; k++)
{
updatedValue -= rA1[row * TILE_SIZE + k] * rA1[column * TILE_SIZE + k];
}
rA2[row * TILE_SIZE + column] = updatedValue;
}
}
/*
* Function to perform general matrix multiplication
* DOUBT: I think calculation is given wrong in paper it should be rA2[k][n]
*/
__device__ void sgemm_tile(const float* rA1, const float* rA2, float* rA3)
{
// int row = blockIdx.y * TILE_SIZE + threadIdx.y;
// int column = blockIdx.x * TILE_SIZE + threadIdx.x;
int row = threadIdx.y;
int column = threadIdx.x;
float updatedValue = rA3[row * TILE_SIZE + column];
for(int i=0; i<TILE_SIZE; i++)
{
updatedValue -= rA1[row * TILE_SIZE + i] * rA2[i * TILE_SIZE + column];
}
rA3[row * TILE_SIZE + column] = updatedValue;
}
/*
* Function to store full tile from shared memory to global memory
*/
__device__ void store_full(const float* s_data, float* g_data)
{
int g_row = blockIdx.y * TILE_SIZE + threadIdx.y;
int g_column = blockIdx.x * TILE_SIZE + threadIdx.x;
int l_row = threadIdx.y;
int l_column = threadIdx.x;
g_data[g_row * TILE_SIZE + g_column] = s_data[l_row * TILE_SIZE + l_column];
__syncthreads();
}
/*
* Function to store lower triangular tile from shared memory to global memory
*/
__device__ void store_lower(const float* s_data, float* g_data)
{
int g_row = blockIdx.y * TILE_SIZE + threadIdx.y;
int g_column = blockIdx.x * TILE_SIZE + threadIdx.x;
int l_row = threadIdx.y;
int l_column = threadIdx.x;
if(l_column <= l_row)
g_data[g_row * TILE_SIZE + g_column] = s_data[l_row * TILE_SIZE + l_column];
else
g_data[g_row * TILE_SIZE + g_column] = 0;
__syncthreads();
}
/*
* Function to perform Choleshky Factorization for a tile
*/
__device__ void spotrf_tile(float* t_A)
{
// int ty = blockIdx.x*blockDim.x + threadIdx.x; // col
// int tx = blockIdx.y*blockDim.y + threadIdx.y; // row
int ty = threadIdx.x; // col
int tx = threadIdx.y; // row
for(int k{0};k<TILE_SIZE;k++){
// square root of diagonal elements
if(tx==0 && ty==0)
t_A[k*TILE_SIZE + k] = sqrtf(t_A[k*TILE_SIZE + k]);
__syncthreads();
// division step done parallaly
if(ty<=tx && tx<TILE_SIZE - 1 && ty<TILE_SIZE - 1 && ty == k)
{
t_A[(tx+1)*TILE_SIZE + k]/= t_A[k*TILE_SIZE + k];
}
__syncthreads();
if(ty<=tx && tx<TILE_SIZE - 1 && ty<TILE_SIZE - 1 && ty >= k)
{
t_A[(tx+1)*TILE_SIZE + (ty+1)]-= t_A[(tx+1)*TILE_SIZE + k]*t_A[(ty+1)*TILE_SIZE + k];
}
__syncthreads();
}
}
/*
* Function to perform triangular solve for a tile
*/
__device__ void strsm_tile(float *t_A1, float *t_A2)
{
// t_A2 is current unkonown
// int ty = blockIdx.x*TILE_SIZE + threadIdx.x;
// int tx = blockIdx.y*TILE_SIZE + threadIdx.y;
int ty = threadIdx.x;
int tx = threadIdx.y;
for(int i{0};i<TILE_SIZE;i++){
if(ty==0){
t_A2[tx*TILE_SIZE + i]/= t_A1[i*TILE_SIZE + i];
}
__syncthreads();
if(ty>i && i<TILE_SIZE-1)
{
t_A2[tx*TILE_SIZE+ty]-= t_A2[tx*TILE_SIZE + i]*t_A1[ty*TILE_SIZE + i];
}
__syncthreads();
}
}
/*
* Function to load a full tile from global memory to shared memory
*/
__device__ void load_full(float *t_A,float * S_A)
{
// assigning a 2-D array in shared memory
int g_ty = blockIdx.x*blockDim.x + threadIdx.x; // col
int g_tx = blockIdx.y*blockDim.y + threadIdx.y; // row
int l_tx = threadIdx.x;
int l_ty = threadIdx.y;
if(l_tx<TILE_SIZE && l_ty<TILE_SIZE)
S_A[l_tx * TILE_SIZE + l_ty] = t_A[g_tx*TILE_SIZE + g_ty];
__syncthreads();
}
/*
* Left looking kernel code (without loop unrolling)
*/
__global__ void left_looking_kernel(float *g_in, int N)
{
// ((N / NB) + 2) * sizeof(TILE) amount of shared memory
extern __shared__ float s_current_panel[];
int l_tid = threadIdx.y * (blockDim.x) + threadIdx.x; // local thread id
int tx = threadIdx.x;
int ty = threadIdx.y;
// i: current panel
for(int i=0; i<(N / TILE_SIZE); i++)
{
// loading current panel in shared memory
for(int j=0; j<(N / TILE_SIZE); j++)
{
int access_row = j * blockDim.y + threadIdx.y;
s_current_panel[j * TILE_SIZE * TILE_SIZE + l_tid] = g_in[access_row * N + i * TILE_SIZE + tx];
}
__syncthreads();
// UPDATE CURRENT PANEL using preceding panels
// j: preceding panel no.
for(int j=0; j<i; j++)
{
int row = i * TILE_SIZE + ty;
// Loading data for rank-k update in shared memory
s_current_panel[N * TILE_SIZE + l_tid] = g_in[row * N + j * TILE_SIZE + tx];
__syncthreads();
// Rank-k update
float *rA1 = &s_current_panel[N*TILE_SIZE + 0];
float *rA2 = &s_current_panel[i * TILE_SIZE * TILE_SIZE];
ssyrk_tile(rA1, rA2);
__syncthreads();
// Applying SGEMM
for(int k=i+1; k<(N / TILE_SIZE); k++)
{
// Loading data for sgemm in shared memory
int access_row = (k) * TILE_SIZE + ty;
s_current_panel[(N + 1) * TILE_SIZE + l_tid] = g_in[access_row * N + j * TILE_SIZE + tx];
__syncthreads();
// sgemm
float *rA1 = &s_current_panel[N * TILE_SIZE];
float *rA2 = &s_current_panel[(N + 1) * TILE_SIZE];
float *rA3 = &s_current_panel[k * TILE_SIZE * TILE_SIZE];
sgemm_tile(rA1, rA2, rA3);
__syncthreads();
}
}
// FACTORIZE CURRENT PANEL
// applying spotrf on the tile (i, i)
float *rA1 = &s_current_panel[i * TILE_SIZE * TILE_SIZE];
spotrf_tile(rA1);
__syncthreads();
// Applying TRSM
for(int k=i+1; k<(N / TILE_SIZE); k++)
{
// trsm
float *rA2 = &s_current_panel[k * TILE_SIZE * TILE_SIZE];
strsm_tile(rA1, rA2);
__syncthreads();
}
// STORING the current panel back in the global memory
for (int k=0; k<(N / TILE_SIZE); k++)
{
// store zero for tiles above the tile (i, i)
if(k<i)
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = 0.0;
}
else
{
// store lower for tile (i, i)
if(k == i)
{
if(tx <= ty)
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = s_current_panel[k * TILE_SIZE * TILE_SIZE + ty * TILE_SIZE + tx];
}
else
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = 0.0;
}
}
else // store full for tiles below the tile (i, i)
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = s_current_panel[k * TILE_SIZE * TILE_SIZE + ty * TILE_SIZE + tx];
}
}
}
__syncthreads();
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h> // needed for the function sqrtf()
#define TILE_SIZE 64 // NB // Block SIZE
/*
* Function to perform rank-k update
* half of the threads working
*/
__device__ void ssyrk_tile(float* rA1, float* rA2)
{
// int row = blockIdx.y * TILE_SIZE + threadIdx.y;
// int column = blockIdx.x * TILE_SIZE + threadIdx.x;
int row = threadIdx.y;
int column = threadIdx.x;
if(column <= row)
{
float updatedValue = rA2[row * TILE_SIZE + column];
for(int k=0; k<TILE_SIZE; k++)
{
updatedValue -= rA1[row * TILE_SIZE + k] * rA1[column * TILE_SIZE + k];
}
rA2[row * TILE_SIZE + column] = updatedValue;
}
}
/*
* Function to perform general matrix multiplication
* DOUBT: I think calculation is given wrong in paper it should be rA2[k][n]
*/
__device__ void sgemm_tile(const float* rA1, const float* rA2, float* rA3)
{
// int row = blockIdx.y * TILE_SIZE + threadIdx.y;
// int column = blockIdx.x * TILE_SIZE + threadIdx.x;
int row = threadIdx.y;
int column = threadIdx.x;
float updatedValue = rA3[row * TILE_SIZE + column];
for(int i=0; i<TILE_SIZE; i++)
{
updatedValue -= rA1[row * TILE_SIZE + i] * rA2[i * TILE_SIZE + column];
}
rA3[row * TILE_SIZE + column] = updatedValue;
}
/*
* Function to store full tile from shared memory to global memory
*/
__device__ void store_full(const float* s_data, float* g_data)
{
int g_row = blockIdx.y * TILE_SIZE + threadIdx.y;
int g_column = blockIdx.x * TILE_SIZE + threadIdx.x;
int l_row = threadIdx.y;
int l_column = threadIdx.x;
g_data[g_row * TILE_SIZE + g_column] = s_data[l_row * TILE_SIZE + l_column];
__syncthreads();
}
/*
* Function to store lower triangular tile from shared memory to global memory
*/
__device__ void store_lower(const float* s_data, float* g_data)
{
int g_row = blockIdx.y * TILE_SIZE + threadIdx.y;
int g_column = blockIdx.x * TILE_SIZE + threadIdx.x;
int l_row = threadIdx.y;
int l_column = threadIdx.x;
if(l_column <= l_row)
g_data[g_row * TILE_SIZE + g_column] = s_data[l_row * TILE_SIZE + l_column];
else
g_data[g_row * TILE_SIZE + g_column] = 0;
__syncthreads();
}
/*
* Function to perform Choleshky Factorization for a tile
*/
__device__ void spotrf_tile(float* t_A)
{
// int ty = blockIdx.x*blockDim.x + threadIdx.x; // col
// int tx = blockIdx.y*blockDim.y + threadIdx.y; // row
int ty = threadIdx.x; // col
int tx = threadIdx.y; // row
for(int k{0};k<TILE_SIZE;k++){
// square root of diagonal elements
if(tx==0 && ty==0)
t_A[k*TILE_SIZE + k] = sqrtf(t_A[k*TILE_SIZE + k]);
__syncthreads();
// division step done parallaly
if(ty<=tx && tx<TILE_SIZE - 1 && ty<TILE_SIZE - 1 && ty == k)
{
t_A[(tx+1)*TILE_SIZE + k]/= t_A[k*TILE_SIZE + k];
}
__syncthreads();
if(ty<=tx && tx<TILE_SIZE - 1 && ty<TILE_SIZE - 1 && ty >= k)
{
t_A[(tx+1)*TILE_SIZE + (ty+1)]-= t_A[(tx+1)*TILE_SIZE + k]*t_A[(ty+1)*TILE_SIZE + k];
}
__syncthreads();
}
}
/*
* Function to perform triangular solve for a tile
*/
__device__ void strsm_tile(float *t_A1, float *t_A2)
{
// t_A2 is current unkonown
// int ty = blockIdx.x*TILE_SIZE + threadIdx.x;
// int tx = blockIdx.y*TILE_SIZE + threadIdx.y;
int ty = threadIdx.x;
int tx = threadIdx.y;
for(int i{0};i<TILE_SIZE;i++){
if(ty==0){
t_A2[tx*TILE_SIZE + i]/= t_A1[i*TILE_SIZE + i];
}
__syncthreads();
if(ty>i && i<TILE_SIZE-1)
{
t_A2[tx*TILE_SIZE+ty]-= t_A2[tx*TILE_SIZE + i]*t_A1[ty*TILE_SIZE + i];
}
__syncthreads();
}
}
/*
* Function to load a full tile from global memory to shared memory
*/
__device__ void load_full(float *t_A,float * S_A)
{
// assigning a 2-D array in shared memory
int g_ty = blockIdx.x*blockDim.x + threadIdx.x; // col
int g_tx = blockIdx.y*blockDim.y + threadIdx.y; // row
int l_tx = threadIdx.x;
int l_ty = threadIdx.y;
if(l_tx<TILE_SIZE && l_ty<TILE_SIZE)
S_A[l_tx * TILE_SIZE + l_ty] = t_A[g_tx*TILE_SIZE + g_ty];
__syncthreads();
}
/*
* Left looking kernel code (without loop unrolling)
*/
__global__ void left_looking_kernel(float *g_in, int N)
{
// ((N / NB) + 2) * sizeof(TILE) amount of shared memory
extern __shared__ float s_current_panel[];
int l_tid = threadIdx.y * (blockDim.x) + threadIdx.x; // local thread id
int tx = threadIdx.x;
int ty = threadIdx.y;
// i: current panel
for(int i=0; i<(N / TILE_SIZE); i++)
{
// loading current panel in shared memory
for(int j=0; j<(N / TILE_SIZE); j++)
{
int access_row = j * blockDim.y + threadIdx.y;
s_current_panel[j * TILE_SIZE * TILE_SIZE + l_tid] = g_in[access_row * N + i * TILE_SIZE + tx];
}
__syncthreads();
// UPDATE CURRENT PANEL using preceding panels
// j: preceding panel no.
for(int j=0; j<i; j++)
{
int row = i * TILE_SIZE + ty;
// Loading data for rank-k update in shared memory
s_current_panel[N * TILE_SIZE + l_tid] = g_in[row * N + j * TILE_SIZE + tx];
__syncthreads();
// Rank-k update
float *rA1 = &s_current_panel[N*TILE_SIZE + 0];
float *rA2 = &s_current_panel[i * TILE_SIZE * TILE_SIZE];
ssyrk_tile(rA1, rA2);
__syncthreads();
// Applying SGEMM
for(int k=i+1; k<(N / TILE_SIZE); k++)
{
// Loading data for sgemm in shared memory
int access_row = (k) * TILE_SIZE + ty;
s_current_panel[(N + 1) * TILE_SIZE + l_tid] = g_in[access_row * N + j * TILE_SIZE + tx];
__syncthreads();
// sgemm
float *rA1 = &s_current_panel[N * TILE_SIZE];
float *rA2 = &s_current_panel[(N + 1) * TILE_SIZE];
float *rA3 = &s_current_panel[k * TILE_SIZE * TILE_SIZE];
sgemm_tile(rA1, rA2, rA3);
__syncthreads();
}
}
// FACTORIZE CURRENT PANEL
// applying spotrf on the tile (i, i)
float *rA1 = &s_current_panel[i * TILE_SIZE * TILE_SIZE];
spotrf_tile(rA1);
__syncthreads();
// Applying TRSM
for(int k=i+1; k<(N / TILE_SIZE); k++)
{
// trsm
float *rA2 = &s_current_panel[k * TILE_SIZE * TILE_SIZE];
strsm_tile(rA1, rA2);
__syncthreads();
}
// STORING the current panel back in the global memory
for (int k=0; k<(N / TILE_SIZE); k++)
{
// store zero for tiles above the tile (i, i)
if(k<i)
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = 0.0;
}
else
{
// store lower for tile (i, i)
if(k == i)
{
if(tx <= ty)
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = s_current_panel[k * TILE_SIZE * TILE_SIZE + ty * TILE_SIZE + tx];
}
else
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = 0.0;
}
}
else // store full for tiles below the tile (i, i)
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = s_current_panel[k * TILE_SIZE * TILE_SIZE + ty * TILE_SIZE + tx];
}
}
}
__syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h> // needed for the function sqrtf()
#define TILE_SIZE 64 // NB // Block SIZE
/*
* Function to perform rank-k update
* half of the threads working
*/
__device__ void ssyrk_tile(float* rA1, float* rA2)
{
// int row = blockIdx.y * TILE_SIZE + threadIdx.y;
// int column = blockIdx.x * TILE_SIZE + threadIdx.x;
int row = threadIdx.y;
int column = threadIdx.x;
if(column <= row)
{
float updatedValue = rA2[row * TILE_SIZE + column];
for(int k=0; k<TILE_SIZE; k++)
{
updatedValue -= rA1[row * TILE_SIZE + k] * rA1[column * TILE_SIZE + k];
}
rA2[row * TILE_SIZE + column] = updatedValue;
}
}
/*
* Function to perform general matrix multiplication
* DOUBT: I think calculation is given wrong in paper it should be rA2[k][n]
*/
__device__ void sgemm_tile(const float* rA1, const float* rA2, float* rA3)
{
// int row = blockIdx.y * TILE_SIZE + threadIdx.y;
// int column = blockIdx.x * TILE_SIZE + threadIdx.x;
int row = threadIdx.y;
int column = threadIdx.x;
float updatedValue = rA3[row * TILE_SIZE + column];
for(int i=0; i<TILE_SIZE; i++)
{
updatedValue -= rA1[row * TILE_SIZE + i] * rA2[i * TILE_SIZE + column];
}
rA3[row * TILE_SIZE + column] = updatedValue;
}
/*
* Function to store full tile from shared memory to global memory
*/
__device__ void store_full(const float* s_data, float* g_data)
{
int g_row = blockIdx.y * TILE_SIZE + threadIdx.y;
int g_column = blockIdx.x * TILE_SIZE + threadIdx.x;
int l_row = threadIdx.y;
int l_column = threadIdx.x;
g_data[g_row * TILE_SIZE + g_column] = s_data[l_row * TILE_SIZE + l_column];
__syncthreads();
}
/*
* Function to store lower triangular tile from shared memory to global memory
*/
__device__ void store_lower(const float* s_data, float* g_data)
{
int g_row = blockIdx.y * TILE_SIZE + threadIdx.y;
int g_column = blockIdx.x * TILE_SIZE + threadIdx.x;
int l_row = threadIdx.y;
int l_column = threadIdx.x;
if(l_column <= l_row)
g_data[g_row * TILE_SIZE + g_column] = s_data[l_row * TILE_SIZE + l_column];
else
g_data[g_row * TILE_SIZE + g_column] = 0;
__syncthreads();
}
/*
* Function to perform Choleshky Factorization for a tile
*/
__device__ void spotrf_tile(float* t_A)
{
// int ty = blockIdx.x*blockDim.x + threadIdx.x; // col
// int tx = blockIdx.y*blockDim.y + threadIdx.y; // row
int ty = threadIdx.x; // col
int tx = threadIdx.y; // row
for(int k{0};k<TILE_SIZE;k++){
// square root of diagonal elements
if(tx==0 && ty==0)
t_A[k*TILE_SIZE + k] = sqrtf(t_A[k*TILE_SIZE + k]);
__syncthreads();
// division step done parallaly
if(ty<=tx && tx<TILE_SIZE - 1 && ty<TILE_SIZE - 1 && ty == k)
{
t_A[(tx+1)*TILE_SIZE + k]/= t_A[k*TILE_SIZE + k];
}
__syncthreads();
if(ty<=tx && tx<TILE_SIZE - 1 && ty<TILE_SIZE - 1 && ty >= k)
{
t_A[(tx+1)*TILE_SIZE + (ty+1)]-= t_A[(tx+1)*TILE_SIZE + k]*t_A[(ty+1)*TILE_SIZE + k];
}
__syncthreads();
}
}
/*
* Function to perform triangular solve for a tile
*/
__device__ void strsm_tile(float *t_A1, float *t_A2)
{
// t_A2 is current unkonown
// int ty = blockIdx.x*TILE_SIZE + threadIdx.x;
// int tx = blockIdx.y*TILE_SIZE + threadIdx.y;
int ty = threadIdx.x;
int tx = threadIdx.y;
for(int i{0};i<TILE_SIZE;i++){
if(ty==0){
t_A2[tx*TILE_SIZE + i]/= t_A1[i*TILE_SIZE + i];
}
__syncthreads();
if(ty>i && i<TILE_SIZE-1)
{
t_A2[tx*TILE_SIZE+ty]-= t_A2[tx*TILE_SIZE + i]*t_A1[ty*TILE_SIZE + i];
}
__syncthreads();
}
}
/*
* Function to load a full tile from global memory to shared memory
*/
__device__ void load_full(float *t_A,float * S_A)
{
// assigning a 2-D array in shared memory
int g_ty = blockIdx.x*blockDim.x + threadIdx.x; // col
int g_tx = blockIdx.y*blockDim.y + threadIdx.y; // row
int l_tx = threadIdx.x;
int l_ty = threadIdx.y;
if(l_tx<TILE_SIZE && l_ty<TILE_SIZE)
S_A[l_tx * TILE_SIZE + l_ty] = t_A[g_tx*TILE_SIZE + g_ty];
__syncthreads();
}
/*
* Left looking kernel code (without loop unrolling)
*/
__global__ void left_looking_kernel(float *g_in, int N)
{
// ((N / NB) + 2) * sizeof(TILE) amount of shared memory
extern __shared__ float s_current_panel[];
int l_tid = threadIdx.y * (blockDim.x) + threadIdx.x; // local thread id
int tx = threadIdx.x;
int ty = threadIdx.y;
// i: current panel
for(int i=0; i<(N / TILE_SIZE); i++)
{
// loading current panel in shared memory
for(int j=0; j<(N / TILE_SIZE); j++)
{
int access_row = j * blockDim.y + threadIdx.y;
s_current_panel[j * TILE_SIZE * TILE_SIZE + l_tid] = g_in[access_row * N + i * TILE_SIZE + tx];
}
__syncthreads();
// UPDATE CURRENT PANEL using preceding panels
// j: preceding panel no.
for(int j=0; j<i; j++)
{
int row = i * TILE_SIZE + ty;
// Loading data for rank-k update in shared memory
s_current_panel[N * TILE_SIZE + l_tid] = g_in[row * N + j * TILE_SIZE + tx];
__syncthreads();
// Rank-k update
float *rA1 = &s_current_panel[N*TILE_SIZE + 0];
float *rA2 = &s_current_panel[i * TILE_SIZE * TILE_SIZE];
ssyrk_tile(rA1, rA2);
__syncthreads();
// Applying SGEMM
for(int k=i+1; k<(N / TILE_SIZE); k++)
{
// Loading data for sgemm in shared memory
int access_row = (k) * TILE_SIZE + ty;
s_current_panel[(N + 1) * TILE_SIZE + l_tid] = g_in[access_row * N + j * TILE_SIZE + tx];
__syncthreads();
// sgemm
float *rA1 = &s_current_panel[N * TILE_SIZE];
float *rA2 = &s_current_panel[(N + 1) * TILE_SIZE];
float *rA3 = &s_current_panel[k * TILE_SIZE * TILE_SIZE];
sgemm_tile(rA1, rA2, rA3);
__syncthreads();
}
}
// FACTORIZE CURRENT PANEL
// applying spotrf on the tile (i, i)
float *rA1 = &s_current_panel[i * TILE_SIZE * TILE_SIZE];
spotrf_tile(rA1);
__syncthreads();
// Applying TRSM
for(int k=i+1; k<(N / TILE_SIZE); k++)
{
// trsm
float *rA2 = &s_current_panel[k * TILE_SIZE * TILE_SIZE];
strsm_tile(rA1, rA2);
__syncthreads();
}
// STORING the current panel back in the global memory
for (int k=0; k<(N / TILE_SIZE); k++)
{
// store zero for tiles above the tile (i, i)
if(k<i)
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = 0.0;
}
else
{
// store lower for tile (i, i)
if(k == i)
{
if(tx <= ty)
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = s_current_panel[k * TILE_SIZE * TILE_SIZE + ty * TILE_SIZE + tx];
}
else
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = 0.0;
}
}
else // store full for tiles below the tile (i, i)
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = s_current_panel[k * TILE_SIZE * TILE_SIZE + ty * TILE_SIZE + tx];
}
}
}
__syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19left_looking_kernelPfi
.globl _Z19left_looking_kernelPfi
.p2align 8
.type _Z19left_looking_kernelPfi,@function
_Z19left_looking_kernelPfi:
s_load_b32 s6, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 64
s_cbranch_scc1 .LBB0_43
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
v_bfe_u32 v4, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_ashr_i32 s0, s6, 31
s_lshl_b32 s8, s6, 6
s_lshr_b32 s0, s0, 26
v_lshlrev_b32_e32 v3, 6, v4
s_add_i32 s1, s6, s0
v_lshlrev_b32_e32 v5, 2, v0
s_ashr_i32 s9, s1, 6
v_lshlrev_b32_e32 v1, 8, v4
v_lshlrev_b32_e32 v2, 8, v0
v_max_u32_e32 v8, v4, v0
v_add_nc_u32_e32 v9, 0, v5
s_add_i32 s2, s8, 64
s_lshl_b32 s10, s6, 8
v_or_b32_e32 v7, v4, v0
v_add_nc_u32_e32 v17, 0, v1
v_add_nc_u32_e32 v18, 64, v3
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s3, 0xffff
v_add_nc_u32_e32 v19, 1, v0
v_mad_u32_u24 v13, v4, s1, v0
v_add_nc_u32_e32 v12, 0, v2
v_add3_u32 v6, 0, s10, v2
v_cmp_gt_u32_e32 vcc_lo, 63, v8
v_add_nc_u32_e32 v8, v9, v1
v_add_nc_u32_e32 v10, s8, v13
v_add_nc_u32_e32 v11, s2, v13
v_mad_u64_u32 v[1:2], null, v4, s6, v[0:1]
v_cmp_le_u32_e64 s0, v0, v4
v_cmp_eq_u32_e64 s1, 0, v7
v_add_nc_u32_e32 v7, v17, v5
v_lshl_add_u32 v9, s2, 2, v9
v_lshl_add_u32 v10, v10, 2, 0
v_lshl_add_u32 v11, v11, 2, 0
v_cmp_eq_u32_e64 s2, 0, v0
v_lshl_add_u32 v13, v13, 2, 0
v_add_nc_u32_e32 v14, s10, v17
v_add_nc_u32_e32 v15, 0x100, v12
v_add_nc_u32_e32 v16, 0x100, v17
v_add_nc_u32_e32 v17, 0x4000, v17
v_lshlrev_b32_e32 v18, 2, v18
v_lshlrev_b32_e32 v19, 2, v19
v_lshlrev_b32_e32 v20, 2, v3
s_lshr_b32 s3, s3, 16
s_mov_b32 s7, 0
s_and_b32 s10, vcc_lo, s0
s_mul_i32 s11, s6, s3
s_mov_b32 s12, 0
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v1, 64, v1
v_add_nc_u32_e32 v15, 0x4000, v15
v_add_nc_u32_e32 v16, 0x4000, v16
v_add_nc_u32_e32 v12, 0x4000, v12
v_add_nc_u32_e32 v17, 0x4000, v17
s_addk_i32 s7, 0x4000
s_cmp_eq_u32 s3, s9
s_mov_b32 s12, s3
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_43
.LBB0_3:
v_mov_b32_e32 v2, v1
v_mov_b32_e32 v21, v13
s_mov_b32 s3, s9
.LBB0_4:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[22:23], 2, v[2:3]
v_add_nc_u32_e32 v2, s11, v2
v_add_co_u32 v22, vcc_lo, s4, v22
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v23, vcc_lo, s5, v23, vcc_lo
global_load_b32 v3, v[22:23], off
s_waitcnt vmcnt(0)
ds_store_b32 v21, v3
v_add_nc_u32_e32 v21, 0x4000, v21
s_cbranch_scc0 .LBB0_4
s_cmp_eq_u32 s12, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_17
v_lshl_add_u32 v2, s12, 6, v4
s_add_i32 s3, s12, 1
v_lshl_add_u32 v21, s12, 14, v7
s_cmp_lt_i32 s3, s9
s_mov_b32 s14, 0
v_mul_lo_u32 v3, v2, s6
s_cselect_b32 s13, -1, 0
s_branch .LBB0_8
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s14, s12
s_cbranch_scc1 .LBB0_17
.LBB0_8:
s_lshl_b32 s15, s14, 6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v22, s15, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v23, 31, v22
v_lshlrev_b64 v[22:23], 2, v[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v22, vcc_lo, s4, v22
v_add_co_ci_u32_e32 v23, vcc_lo, s5, v23, vcc_lo
global_load_b32 v2, v[22:23], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s16, s0
s_cbranch_execz .LBB0_12
ds_load_b32 v2, v21
s_mov_b32 s17, 0
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v22, s17, v14
v_add_nc_u32_e32 v23, s17, v6
s_add_i32 s17, s17, 4
ds_load_b32 v22, v22
ds_load_b32 v23, v23
s_cmpk_eq_i32 s17, 0x100
s_waitcnt lgkmcnt(0)
v_fma_f32 v2, -v22, v23, v2
s_cbranch_scc0 .LBB0_10
ds_store_b32 v21, v2
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s13
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_7
v_add_nc_u32_e32 v2, s15, v0
s_mov_b32 s15, s3
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_14:
v_lshl_add_u32 v24, s15, 6, v4
s_mov_b32 s16, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[22:23], null, v24, s6, v[2:3]
v_mov_b32_e32 v24, v9
v_ashrrev_i32_e32 v23, 31, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[22:23], 2, v[22:23]
v_add_co_u32 v22, vcc_lo, s4, v22
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v23, vcc_lo, s5, v23, vcc_lo
global_load_b32 v23, v[22:23], off
v_lshl_add_u32 v22, s15, 14, v8
s_waitcnt vmcnt(0)
ds_store_b32 v11, v23
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v23, v22
.LBB0_15:
v_add_nc_u32_e32 v25, s16, v14
s_add_i32 s16, s16, 4
ds_load_b32 v26, v24
ds_load_b32 v25, v25
v_add_nc_u32_e32 v24, 0x100, v24
s_cmpk_lg_i32 s16, 0x100
s_waitcnt lgkmcnt(0)
v_fma_f32 v23, -v25, v26, v23
s_cbranch_scc1 .LBB0_15
s_add_i32 s15, s15, 1
ds_store_b32 v22, v23
s_cmp_ge_i32 s15, s9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_14
s_branch .LBB0_7
.LBB0_17:
s_lshl_b32 s3, s12, 14
s_mov_b32 s13, 0
s_add_i32 s3, s3, 0
s_mov_b32 s14, s7
v_add3_u32 v2, s3, v18, v19
s_mov_b32 s15, 0
s_branch .LBB0_19
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s13, s13, 4
s_add_i32 s15, s15, 1
s_addk_i32 s14, 0x104
s_cmpk_lg_i32 s13, 0x100
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_25
.LBB0_19:
s_and_saveexec_b32 s16, s1
s_cbranch_execz .LBB0_21
v_mov_b32_e32 v3, s14
ds_load_b32 v21, v3
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v22, 0x4f800000, v21
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v21, v21, v22, vcc_lo
v_sqrt_f32_e32 v22, v21
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v23, -1, v22
v_add_nc_u32_e32 v24, 1, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v25, -v23, v22, v21
v_fma_f32 v26, -v24, v22, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s3, 0, v25
v_cndmask_b32_e64 v22, v22, v23, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s3, 0, v26
v_cndmask_b32_e64 v22, v22, v24, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v23, 0x37800000, v22
v_cndmask_b32_e32 v22, v22, v23, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v21, 0x260
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v21, v22, v21, vcc_lo
ds_store_b32 v3, v21
.LBB0_21:
s_or_b32 exec_lo, exec_lo, s16
v_cmp_eq_u32_e32 vcc_lo, s13, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s16, s10, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s16
s_cbranch_execz .LBB0_23
v_mov_b32_e32 v3, s14
v_add_nc_u32_e32 v21, s13, v16
ds_load_b32 v3, v3
ds_load_b32 v22, v21
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v23, null, v3, v3, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v24, v23
s_waitcnt_depctr 0xfff
v_fma_f32 v25, -v23, v24, 1.0
v_fmac_f32_e32 v24, v25, v24
v_div_scale_f32 v25, vcc_lo, v22, v3, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v26, v25, v24
v_fma_f32 v27, -v23, v26, v25
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v26, v27, v24
v_fma_f32 v23, -v23, v26, v25
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v23, v23, v24, v26
v_div_fixup_f32 v3, v23, v3, v22
ds_store_b32 v21, v3
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_le_u32_e32 vcc_lo, s15, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s16, s10, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s16
s_cbranch_execz .LBB0_18
v_add_nc_u32_e32 v3, s13, v16
v_add_nc_u32_e32 v21, s13, v15
ds_load_b32 v3, v3
ds_load_b32 v21, v21
ds_load_b32 v22, v2
s_waitcnt lgkmcnt(0)
v_fma_f32 v3, -v3, v21, v22
ds_store_b32 v2, v3
s_branch .LBB0_18
.LBB0_25:
s_add_i32 s3, s12, 1
v_mov_b32_e32 v2, v17
s_barrier
s_cmp_ge_i32 s3, s9
s_mov_b32 s13, s3
s_branch .LBB0_27
.LBB0_26:
v_add_nc_u32_e32 v2, 0x4000, v2
s_add_i32 s13, s13, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s13, s9
s_barrier
.LBB0_27:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_34
s_lshl_b32 s14, s13, 14
s_movk_i32 s15, 0xff00
s_add_i32 s14, s14, 0
s_mov_b32 s16, s7
v_add3_u32 v3, s14, v20, v5
s_mov_b32 s14, 0
s_branch .LBB0_30
.LBB0_29:
s_or_b32 exec_lo, exec_lo, s17
s_add_i32 s15, s15, 4
s_add_i32 s14, s14, 1
s_addk_i32 s16, 0x104
s_cmp_lg_u32 s15, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_26
.LBB0_30:
s_and_saveexec_b32 s17, s2
s_cbranch_execz .LBB0_32
v_dual_mov_b32 v21, s16 :: v_dual_add_nc_u32 v22, s15, v2
ds_load_b32 v21, v21
ds_load_b32 v23, v22 offset:256
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v24, null, v21, v21, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v25, v24
s_waitcnt_depctr 0xfff
v_fma_f32 v26, -v24, v25, 1.0
v_fmac_f32_e32 v25, v26, v25
v_div_scale_f32 v26, vcc_lo, v23, v21, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v27, v26, v25
v_fma_f32 v28, -v24, v27, v26
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v27, v28, v25
v_fma_f32 v24, -v24, v27, v26
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v24, v24, v25, v27
v_div_fixup_f32 v21, v24, v21, v23
ds_store_b32 v22, v21 offset:256
.LBB0_32:
s_or_b32 exec_lo, exec_lo, s17
v_cmp_lt_u32_e32 vcc_lo, s14, v0
s_cmp_lg_u32 s15, -4
s_waitcnt lgkmcnt(0)
s_cselect_b32 s17, -1, 0
s_barrier
s_and_b32 s18, vcc_lo, s17
buffer_gl0_inv
s_and_saveexec_b32 s17, s18
s_cbranch_execz .LBB0_29
v_add_nc_u32_e32 v21, s15, v2
v_add_nc_u32_e32 v22, s15, v12
ds_load_b32 v21, v21 offset:256
ds_load_b32 v22, v22 offset:256
ds_load_b32 v23, v3
s_waitcnt lgkmcnt(0)
v_fma_f32 v21, -v21, v22, v23
ds_store_b32 v3, v21
s_branch .LBB0_29
.LBB0_34:
v_dual_mov_b32 v21, v8 :: v_dual_mov_b32 v2, v1
s_mov_b32 s13, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_37
.p2align 6
.LBB0_35:
s_or_b32 exec_lo, exec_lo, s14
.LBB0_36:
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v21, 0x4000, v21
s_add_i32 s13, s13, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s9, s13
v_lshlrev_b64 v[23:24], 2, v[2:3]
v_add_nc_u32_e32 v2, s8, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v23, vcc_lo, s4, v23
v_add_co_ci_u32_e32 v24, vcc_lo, s5, v24, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[23:24], v22, off
s_cbranch_scc1 .LBB0_2
.LBB0_37:
v_mov_b32_e32 v22, 0
s_cmp_lt_u32 s13, s12
s_cbranch_scc1 .LBB0_36
s_cmp_lg_u32 s12, s13
s_cbranch_scc0 .LBB0_40
ds_load_b32 v22, v21
s_cbranch_execnz .LBB0_36
s_branch .LBB0_41
.p2align 6
.LBB0_40:
.LBB0_41:
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v22, 0
s_and_saveexec_b32 s14, s0
s_cbranch_execz .LBB0_35
ds_load_b32 v22, v21
s_branch .LBB0_35
.LBB0_43:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19left_looking_kernelPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 29
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19left_looking_kernelPfi, .Lfunc_end0-_Z19left_looking_kernelPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19left_looking_kernelPfi
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z19left_looking_kernelPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 29
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h> // needed for the function sqrtf()
#define TILE_SIZE 64 // NB // Block SIZE
/*
* Function to perform rank-k update
* half of the threads working
*/
__device__ void ssyrk_tile(float* rA1, float* rA2)
{
// int row = blockIdx.y * TILE_SIZE + threadIdx.y;
// int column = blockIdx.x * TILE_SIZE + threadIdx.x;
int row = threadIdx.y;
int column = threadIdx.x;
if(column <= row)
{
float updatedValue = rA2[row * TILE_SIZE + column];
for(int k=0; k<TILE_SIZE; k++)
{
updatedValue -= rA1[row * TILE_SIZE + k] * rA1[column * TILE_SIZE + k];
}
rA2[row * TILE_SIZE + column] = updatedValue;
}
}
/*
* Function to perform general matrix multiplication
* DOUBT: I think calculation is given wrong in paper it should be rA2[k][n]
*/
__device__ void sgemm_tile(const float* rA1, const float* rA2, float* rA3)
{
// int row = blockIdx.y * TILE_SIZE + threadIdx.y;
// int column = blockIdx.x * TILE_SIZE + threadIdx.x;
int row = threadIdx.y;
int column = threadIdx.x;
float updatedValue = rA3[row * TILE_SIZE + column];
for(int i=0; i<TILE_SIZE; i++)
{
updatedValue -= rA1[row * TILE_SIZE + i] * rA2[i * TILE_SIZE + column];
}
rA3[row * TILE_SIZE + column] = updatedValue;
}
/*
* Function to store full tile from shared memory to global memory
*/
__device__ void store_full(const float* s_data, float* g_data)
{
int g_row = blockIdx.y * TILE_SIZE + threadIdx.y;
int g_column = blockIdx.x * TILE_SIZE + threadIdx.x;
int l_row = threadIdx.y;
int l_column = threadIdx.x;
g_data[g_row * TILE_SIZE + g_column] = s_data[l_row * TILE_SIZE + l_column];
__syncthreads();
}
/*
* Function to store lower triangular tile from shared memory to global memory
*/
__device__ void store_lower(const float* s_data, float* g_data)
{
int g_row = blockIdx.y * TILE_SIZE + threadIdx.y;
int g_column = blockIdx.x * TILE_SIZE + threadIdx.x;
int l_row = threadIdx.y;
int l_column = threadIdx.x;
if(l_column <= l_row)
g_data[g_row * TILE_SIZE + g_column] = s_data[l_row * TILE_SIZE + l_column];
else
g_data[g_row * TILE_SIZE + g_column] = 0;
__syncthreads();
}
/*
* Function to perform Choleshky Factorization for a tile
*/
__device__ void spotrf_tile(float* t_A)
{
// int ty = blockIdx.x*blockDim.x + threadIdx.x; // col
// int tx = blockIdx.y*blockDim.y + threadIdx.y; // row
int ty = threadIdx.x; // col
int tx = threadIdx.y; // row
for(int k{0};k<TILE_SIZE;k++){
// square root of diagonal elements
if(tx==0 && ty==0)
t_A[k*TILE_SIZE + k] = sqrtf(t_A[k*TILE_SIZE + k]);
__syncthreads();
// division step done parallaly
if(ty<=tx && tx<TILE_SIZE - 1 && ty<TILE_SIZE - 1 && ty == k)
{
t_A[(tx+1)*TILE_SIZE + k]/= t_A[k*TILE_SIZE + k];
}
__syncthreads();
if(ty<=tx && tx<TILE_SIZE - 1 && ty<TILE_SIZE - 1 && ty >= k)
{
t_A[(tx+1)*TILE_SIZE + (ty+1)]-= t_A[(tx+1)*TILE_SIZE + k]*t_A[(ty+1)*TILE_SIZE + k];
}
__syncthreads();
}
}
/*
* Function to perform triangular solve for a tile
*/
__device__ void strsm_tile(float *t_A1, float *t_A2)
{
// t_A2 is current unkonown
// int ty = blockIdx.x*TILE_SIZE + threadIdx.x;
// int tx = blockIdx.y*TILE_SIZE + threadIdx.y;
int ty = threadIdx.x;
int tx = threadIdx.y;
for(int i{0};i<TILE_SIZE;i++){
if(ty==0){
t_A2[tx*TILE_SIZE + i]/= t_A1[i*TILE_SIZE + i];
}
__syncthreads();
if(ty>i && i<TILE_SIZE-1)
{
t_A2[tx*TILE_SIZE+ty]-= t_A2[tx*TILE_SIZE + i]*t_A1[ty*TILE_SIZE + i];
}
__syncthreads();
}
}
/*
* Function to load a full tile from global memory to shared memory
*/
__device__ void load_full(float *t_A,float * S_A)
{
// assigning a 2-D array in shared memory
int g_ty = blockIdx.x*blockDim.x + threadIdx.x; // col
int g_tx = blockIdx.y*blockDim.y + threadIdx.y; // row
int l_tx = threadIdx.x;
int l_ty = threadIdx.y;
if(l_tx<TILE_SIZE && l_ty<TILE_SIZE)
S_A[l_tx * TILE_SIZE + l_ty] = t_A[g_tx*TILE_SIZE + g_ty];
__syncthreads();
}
/*
* Left looking kernel code (without loop unrolling)
*/
__global__ void left_looking_kernel(float *g_in, int N)
{
// ((N / NB) + 2) * sizeof(TILE) amount of shared memory
extern __shared__ float s_current_panel[];
int l_tid = threadIdx.y * (blockDim.x) + threadIdx.x; // local thread id
int tx = threadIdx.x;
int ty = threadIdx.y;
// i: current panel
for(int i=0; i<(N / TILE_SIZE); i++)
{
// loading current panel in shared memory
for(int j=0; j<(N / TILE_SIZE); j++)
{
int access_row = j * blockDim.y + threadIdx.y;
s_current_panel[j * TILE_SIZE * TILE_SIZE + l_tid] = g_in[access_row * N + i * TILE_SIZE + tx];
}
__syncthreads();
// UPDATE CURRENT PANEL using preceding panels
// j: preceding panel no.
for(int j=0; j<i; j++)
{
int row = i * TILE_SIZE + ty;
// Loading data for rank-k update in shared memory
s_current_panel[N * TILE_SIZE + l_tid] = g_in[row * N + j * TILE_SIZE + tx];
__syncthreads();
// Rank-k update
float *rA1 = &s_current_panel[N*TILE_SIZE + 0];
float *rA2 = &s_current_panel[i * TILE_SIZE * TILE_SIZE];
ssyrk_tile(rA1, rA2);
__syncthreads();
// Applying SGEMM
for(int k=i+1; k<(N / TILE_SIZE); k++)
{
// Loading data for sgemm in shared memory
int access_row = (k) * TILE_SIZE + ty;
s_current_panel[(N + 1) * TILE_SIZE + l_tid] = g_in[access_row * N + j * TILE_SIZE + tx];
__syncthreads();
// sgemm
float *rA1 = &s_current_panel[N * TILE_SIZE];
float *rA2 = &s_current_panel[(N + 1) * TILE_SIZE];
float *rA3 = &s_current_panel[k * TILE_SIZE * TILE_SIZE];
sgemm_tile(rA1, rA2, rA3);
__syncthreads();
}
}
// FACTORIZE CURRENT PANEL
// applying spotrf on the tile (i, i)
float *rA1 = &s_current_panel[i * TILE_SIZE * TILE_SIZE];
spotrf_tile(rA1);
__syncthreads();
// Applying TRSM
for(int k=i+1; k<(N / TILE_SIZE); k++)
{
// trsm
float *rA2 = &s_current_panel[k * TILE_SIZE * TILE_SIZE];
strsm_tile(rA1, rA2);
__syncthreads();
}
// STORING the current panel back in the global memory
for (int k=0; k<(N / TILE_SIZE); k++)
{
// store zero for tiles above the tile (i, i)
if(k<i)
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = 0.0;
}
else
{
// store lower for tile (i, i)
if(k == i)
{
if(tx <= ty)
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = s_current_panel[k * TILE_SIZE * TILE_SIZE + ty * TILE_SIZE + tx];
}
else
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = 0.0;
}
}
else // store full for tiles below the tile (i, i)
{
g_in[(k * TILE_SIZE + ty) * N + (i * TILE_SIZE) + tx] = s_current_panel[k * TILE_SIZE * TILE_SIZE + ty * TILE_SIZE + tx];
}
}
}
__syncthreads();
}
} | .text
.file "left_looking.hip"
.globl _Z34__device_stub__left_looking_kernelPfi # -- Begin function _Z34__device_stub__left_looking_kernelPfi
.p2align 4, 0x90
.type _Z34__device_stub__left_looking_kernelPfi,@function
_Z34__device_stub__left_looking_kernelPfi: # @_Z34__device_stub__left_looking_kernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19left_looking_kernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z34__device_stub__left_looking_kernelPfi, .Lfunc_end0-_Z34__device_stub__left_looking_kernelPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19left_looking_kernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19left_looking_kernelPfi,@object # @_Z19left_looking_kernelPfi
.section .rodata,"a",@progbits
.globl _Z19left_looking_kernelPfi
.p2align 3, 0x0
_Z19left_looking_kernelPfi:
.quad _Z34__device_stub__left_looking_kernelPfi
.size _Z19left_looking_kernelPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19left_looking_kernelPfi"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__left_looking_kernelPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19left_looking_kernelPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011ccdf_00000000-6_left_looking.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10ssyrk_tilePfS_
.type _Z10ssyrk_tilePfS_, @function
_Z10ssyrk_tilePfS_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10ssyrk_tilePfS_, .-_Z10ssyrk_tilePfS_
.globl _Z10sgemm_tilePKfS0_Pf
.type _Z10sgemm_tilePKfS0_Pf, @function
_Z10sgemm_tilePKfS0_Pf:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10sgemm_tilePKfS0_Pf, .-_Z10sgemm_tilePKfS0_Pf
.globl _Z10store_fullPKfPf
.type _Z10store_fullPKfPf, @function
_Z10store_fullPKfPf:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10store_fullPKfPf, .-_Z10store_fullPKfPf
.globl _Z11store_lowerPKfPf
.type _Z11store_lowerPKfPf, @function
_Z11store_lowerPKfPf:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z11store_lowerPKfPf, .-_Z11store_lowerPKfPf
.globl _Z11spotrf_tilePf
.type _Z11spotrf_tilePf, @function
_Z11spotrf_tilePf:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z11spotrf_tilePf, .-_Z11spotrf_tilePf
.globl _Z10strsm_tilePfS_
.type _Z10strsm_tilePfS_, @function
_Z10strsm_tilePfS_:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z10strsm_tilePfS_, .-_Z10strsm_tilePfS_
.globl _Z9load_fullPfS_
.type _Z9load_fullPfS_, @function
_Z9load_fullPfS_:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z9load_fullPfS_, .-_Z9load_fullPfS_
.globl _Z40__device_stub__Z19left_looking_kernelPfiPfi
.type _Z40__device_stub__Z19left_looking_kernelPfiPfi, @function
_Z40__device_stub__Z19left_looking_kernelPfiPfi:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19left_looking_kernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z40__device_stub__Z19left_looking_kernelPfiPfi, .-_Z40__device_stub__Z19left_looking_kernelPfiPfi
.globl _Z19left_looking_kernelPfi
.type _Z19left_looking_kernelPfi, @function
_Z19left_looking_kernelPfi:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z19left_looking_kernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z19left_looking_kernelPfi, .-_Z19left_looking_kernelPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19left_looking_kernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19left_looking_kernelPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "left_looking.hip"
.globl _Z34__device_stub__left_looking_kernelPfi # -- Begin function _Z34__device_stub__left_looking_kernelPfi
.p2align 4, 0x90
.type _Z34__device_stub__left_looking_kernelPfi,@function
_Z34__device_stub__left_looking_kernelPfi: # @_Z34__device_stub__left_looking_kernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19left_looking_kernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z34__device_stub__left_looking_kernelPfi, .Lfunc_end0-_Z34__device_stub__left_looking_kernelPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19left_looking_kernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19left_looking_kernelPfi,@object # @_Z19left_looking_kernelPfi
.section .rodata,"a",@progbits
.globl _Z19left_looking_kernelPfi
.p2align 3, 0x0
_Z19left_looking_kernelPfi:
.quad _Z34__device_stub__left_looking_kernelPfi
.size _Z19left_looking_kernelPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19left_looking_kernelPfi"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__left_looking_kernelPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19left_looking_kernelPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
void f(double *res, double *vec1, double *vec2, int n) {
int i = 0;
for(i = 0; i < n; i++)
res[i] = vec1[i] + vec2[i];
}
int main() {
int i, n;
scanf("%d", &n);
double *res = (double *)malloc(sizeof(double) * n);
double *vec1 = (double *)malloc(sizeof(double) * n);
double *vec2 = (double *)malloc(sizeof(double) * n);
for(i = 0; i < n; i++)
scanf("%lf", &vec1[i]);
for(i = 0; i < n; i++)
scanf("%lf", &vec2[i]);
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
f(res, vec1, vec2, n);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
fprintf(stderr, "time = %f\n", time);
cudaEventDestroy(stop);
cudaEventDestroy(start);
// for(i = 0; i < n; i++)
// printf("%f ", res[i]);
// printf("\n");
free(res);
free(vec1);
free(vec2);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
void f(double *res, double *vec1, double *vec2, int n) {
int i = 0;
for(i = 0; i < n; i++)
res[i] = vec1[i] + vec2[i];
}
int main() {
int i, n;
scanf("%d", &n);
double *res = (double *)malloc(sizeof(double) * n);
double *vec1 = (double *)malloc(sizeof(double) * n);
double *vec2 = (double *)malloc(sizeof(double) * n);
for(i = 0; i < n; i++)
scanf("%lf", &vec1[i]);
for(i = 0; i < n; i++)
scanf("%lf", &vec2[i]);
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
f(res, vec1, vec2, n);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
fprintf(stderr, "time = %f\n", time);
cudaEventDestroy(stop);
cudaEventDestroy(start);
// for(i = 0; i < n; i++)
// printf("%f ", res[i]);
// printf("\n");
free(res);
free(vec1);
free(vec2);
return 0;
} | .file "tmpxft_00061cb6_00000000-6_cpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1fPdS_S_i
.type _Z1fPdS_S_i, @function
_Z1fPdS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
salq $3, %rcx
movl $0, %eax
.L5:
movsd (%rsi,%rax), %xmm0
addsd (%rdx,%rax), %xmm0
movsd %xmm0, (%rdi,%rax)
addq $8, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z1fPdS_S_i, .-_Z1fPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "%lf"
.LC2:
.string "time = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
movl (%rsp), %ebp
movslq %ebp, %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
testl %ebp, %ebp
jle .L8
movq %r13, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r15
.L9:
movq %rbp, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl (%rsp), %eax
addq $8, %rbp
cmpl %ebx, %eax
jg .L9
testl %eax, %eax
jle .L8
movq %r12, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r15
.L10:
movq %rbp, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $8, %rbp
cmpl %ebx, (%rsp)
jg .L10
.L8:
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl (%rsp), %ecx
movq %r12, %rdx
movq %r13, %rsi
movq %r14, %rdi
call _Z1fPdS_S_i
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L15
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
void f(double *res, double *vec1, double *vec2, int n) {
int i = 0;
for(i = 0; i < n; i++)
res[i] = vec1[i] + vec2[i];
}
int main() {
int i, n;
scanf("%d", &n);
double *res = (double *)malloc(sizeof(double) * n);
double *vec1 = (double *)malloc(sizeof(double) * n);
double *vec2 = (double *)malloc(sizeof(double) * n);
for(i = 0; i < n; i++)
scanf("%lf", &vec1[i]);
for(i = 0; i < n; i++)
scanf("%lf", &vec2[i]);
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
f(res, vec1, vec2, n);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
fprintf(stderr, "time = %f\n", time);
cudaEventDestroy(stop);
cudaEventDestroy(start);
// for(i = 0; i < n; i++)
// printf("%f ", res[i]);
// printf("\n");
free(res);
free(vec1);
free(vec2);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
void f(double *res, double *vec1, double *vec2, int n) {
int i = 0;
for(i = 0; i < n; i++)
res[i] = vec1[i] + vec2[i];
}
int main() {
int i, n;
scanf("%d", &n);
double *res = (double *)malloc(sizeof(double) * n);
double *vec1 = (double *)malloc(sizeof(double) * n);
double *vec2 = (double *)malloc(sizeof(double) * n);
for(i = 0; i < n; i++)
scanf("%lf", &vec1[i]);
for(i = 0; i < n; i++)
scanf("%lf", &vec2[i]);
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
f(res, vec1, vec2, n);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
fprintf(stderr, "time = %f\n", time);
hipEventDestroy(stop);
hipEventDestroy(start);
// for(i = 0; i < n; i++)
// printf("%f ", res[i]);
// printf("\n");
free(res);
free(vec1);
free(vec2);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
void f(double *res, double *vec1, double *vec2, int n) {
int i = 0;
for(i = 0; i < n; i++)
res[i] = vec1[i] + vec2[i];
}
int main() {
int i, n;
scanf("%d", &n);
double *res = (double *)malloc(sizeof(double) * n);
double *vec1 = (double *)malloc(sizeof(double) * n);
double *vec2 = (double *)malloc(sizeof(double) * n);
for(i = 0; i < n; i++)
scanf("%lf", &vec1[i]);
for(i = 0; i < n; i++)
scanf("%lf", &vec2[i]);
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
f(res, vec1, vec2, n);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
fprintf(stderr, "time = %f\n", time);
hipEventDestroy(stop);
hipEventDestroy(start);
// for(i = 0; i < n; i++)
// printf("%f ", res[i]);
// printf("\n");
free(res);
free(vec1);
free(vec2);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
void f(double *res, double *vec1, double *vec2, int n) {
int i = 0;
for(i = 0; i < n; i++)
res[i] = vec1[i] + vec2[i];
}
int main() {
int i, n;
scanf("%d", &n);
double *res = (double *)malloc(sizeof(double) * n);
double *vec1 = (double *)malloc(sizeof(double) * n);
double *vec2 = (double *)malloc(sizeof(double) * n);
for(i = 0; i < n; i++)
scanf("%lf", &vec1[i]);
for(i = 0; i < n; i++)
scanf("%lf", &vec2[i]);
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
f(res, vec1, vec2, n);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
fprintf(stderr, "time = %f\n", time);
hipEventDestroy(stop);
hipEventDestroy(start);
// for(i = 0; i < n; i++)
// printf("%f ", res[i]);
// printf("\n");
free(res);
free(vec1);
free(vec2);
return 0;
} | .text
.file "cpu.hip"
.globl _Z1fPdS_S_i # -- Begin function _Z1fPdS_S_i
.p2align 4, 0x90
.type _Z1fPdS_S_i,@function
_Z1fPdS_S_i: # @_Z1fPdS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rsi,%rcx,8), %xmm0 # xmm0 = mem[0],zero
addsd (%rdx,%rcx,8), %xmm0
movsd %xmm0, (%rdi,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z1fPdS_S_i, .Lfunc_end0-_Z1fPdS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $40, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 12(%rsp), %r15
leaq (,%r15,8), %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %r14
testq %r15, %r15
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r12
movslq 12(%rsp), %rax
addq $8, %r15
cmpq %rax, %r12
jl .LBB1_2
.LBB1_3: # %.preheader
cmpl $0, 12(%rsp)
jle .LBB1_6
# %bb.4: # %.lr.ph15.preheader
movq %r14, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph15
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r12
movslq 12(%rsp), %rax
addq $8, %r15
cmpq %rax, %r12
jl .LBB1_5
.LBB1_6: # %._crit_edge
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 36(%rsp), %rdi
callq hipEventElapsedTime
movq stderr(%rip), %rdi
movss 36(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movb $1, %al
callq fprintf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%lf"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "time = %f\n"
.size .L.str.2, 11
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00061cb6_00000000-6_cpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1fPdS_S_i
.type _Z1fPdS_S_i, @function
_Z1fPdS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
salq $3, %rcx
movl $0, %eax
.L5:
movsd (%rsi,%rax), %xmm0
addsd (%rdx,%rax), %xmm0
movsd %xmm0, (%rdi,%rax)
addq $8, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z1fPdS_S_i, .-_Z1fPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "%lf"
.LC2:
.string "time = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
movl (%rsp), %ebp
movslq %ebp, %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
testl %ebp, %ebp
jle .L8
movq %r13, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r15
.L9:
movq %rbp, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl (%rsp), %eax
addq $8, %rbp
cmpl %ebx, %eax
jg .L9
testl %eax, %eax
jle .L8
movq %r12, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r15
.L10:
movq %rbp, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $8, %rbp
cmpl %ebx, (%rsp)
jg .L10
.L8:
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl (%rsp), %ecx
movq %r12, %rdx
movq %r13, %rsi
movq %r14, %rdi
call _Z1fPdS_S_i
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L15
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cpu.hip"
.globl _Z1fPdS_S_i # -- Begin function _Z1fPdS_S_i
.p2align 4, 0x90
.type _Z1fPdS_S_i,@function
_Z1fPdS_S_i: # @_Z1fPdS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rsi,%rcx,8), %xmm0 # xmm0 = mem[0],zero
addsd (%rdx,%rcx,8), %xmm0
movsd %xmm0, (%rdi,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z1fPdS_S_i, .Lfunc_end0-_Z1fPdS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $40, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 12(%rsp), %r15
leaq (,%r15,8), %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %r14
testq %r15, %r15
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r12
movslq 12(%rsp), %rax
addq $8, %r15
cmpq %rax, %r12
jl .LBB1_2
.LBB1_3: # %.preheader
cmpl $0, 12(%rsp)
jle .LBB1_6
# %bb.4: # %.lr.ph15.preheader
movq %r14, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph15
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r12
movslq 12(%rsp), %rax
addq $8, %r15
cmpq %rax, %r12
jl .LBB1_5
.LBB1_6: # %._crit_edge
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 36(%rsp), %rdi
callq hipEventElapsedTime
movq stderr(%rip), %rdi
movss 36(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movb $1, %al
callq fprintf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%lf"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "time = %f\n"
.size .L.str.2, 11
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
We consider 1024 map, which are initially constructed with (at most)size = 1024 key, value pairs, for which keys are integers and values are float point numbers.
Then each of them processes 262,144 operations.
The operations include:
'i': insert a key-value pair, or modify the original value. (if the map is full, do nothing)
'r': remove a key.
'g': get the value for a key. If that key dose not exist, return 0
*/
#include <bits/stdc++.h>
#include <cassert>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#include <thrust/sequence.h>
#include <thrust/find.h>
#include <thrust/execution_policy.h>
#define to_ptr(x) thrust::raw_pointer_cast(&x[0])
#define gpu_copy(x, y) thrust::copy((x).begin(), (x).end(), (y).begin())
#define gpu_copy_to(x, y, pos) thrust::copy((x).begin(), (x).end(), (y).begin() + (pos))
#define gpu_seq(x) thrust::sequence((x).begin(), (x).end())
#define host_find(x, n, key) thrust::find((x), (x)+n, key);
#define device_find(x, n, key) thrust::find(thrust::device, (x), (x)+n, key)
#define def_dvec(t) thrust::device_vector<t>
using namespace std;
const int BLOCK_SIZE = 512;
const int NUM_INSTANCE = 1024;
const int NUM_OPERATION = 262144;
const int MOD = 10000;
const int MAX_SIZE = 31;
__device__ int gpuIndex(int size, int *keys, int key){
return (int)(device_find(keys, size, key) - keys);
}
__global__ void procKernel(int n_ins, int *sizes, int *keys, float *values,
int n_ops, char *ops, int *input_keys, float *input_values, float *ans){
int b_id = blockIdx.x, b_sz = blockDim.x, t_id = threadIdx.x;
int global_idx = b_id*b_sz + t_id;
int sz = sizes[global_idx];
int start = global_idx*MAX_SIZE;
for(int i=global_idx*n_ops; i<(global_idx+1)*n_ops; ++i){
int key = input_keys[i];
char op = ops[i];
float value = input_values[i];
int idx = gpuIndex(sz, keys + start, key);
if(op == 'g'){
ans[i] = (idx == sz? 0.:values[start+idx]);
}
else if(op == 'r'){
sz -= (idx != sz);
keys[start+idx] = keys[start+sz];
values[start+idx] = values[start+sz];
}
else{
keys[start + idx] = key;
keys[start + idx] = value;
sz += (idx==sz && sz < MAX_SIZE);
}
}
sizes[global_idx] = sz;
}
class GPUMapTest{
int N_ins, N_ops;
def_dvec(int) dkeys, dinkeys, dsizes;
def_dvec(float) dvalues, dinvalues;
def_dvec(char) dops;
public:
GPUMapTest(int num_ins): N_ins(num_ins){
dkeys.resize(num_ins * MAX_SIZE);
dvalues.resize(num_ins * MAX_SIZE);
dsizes.assign(num_ins, 0);
}
void loadOps(const vector<char> &ops, const vector<int> &inkeys,const vector<float> &invals, int n_ops){
N_ops = n_ops;
assert((int)ops.size() == N_ops * N_ins);
dinkeys.resize(N_ops * N_ins);
dinvalues.resize(N_ops * N_ins);
dops.resize(N_ops * N_ins);
gpu_copy(ops, dops);
gpu_copy(inkeys, dinkeys);
gpu_copy(invals, dinvalues);
}
void procOps(vector<float> &ans){
ans.resize(N_ins * N_ops);
def_dvec(float) dans(N_ins * N_ops);
int n_block = (N_ins+BLOCK_SIZE-1)/BLOCK_SIZE;
procKernel<<<n_block, BLOCK_SIZE>>>(N_ins, to_ptr(dsizes), to_ptr(dkeys), to_ptr(dvalues), N_ops,
to_ptr(dops), to_ptr(dinkeys), to_ptr(dinvalues), to_ptr(dans));
gpu_copy(dans, ans);
return ;
}
};
int main(int argc, char *argv[]){
srand(0);
int num_ins = NUM_INSTANCE, num_ops = NUM_OPERATION;
if(argc > 1) num_ins = stoi(argv[1]);
if(argc > 2) num_ops = stoi(argv[2]);
/* using cudaEvent to evaluate time */
cudaEvent_t start, stop;
float cuda_time;
cudaEventCreate(&start); // creating the event 1
cudaEventCreate(&stop); // creating the event 2
/* Generating data*/
cudaEventRecord(start, 0);
string ref;
ref += string(1500, 'g') + string(300, 'i') + string(200, 'r');
vector<char> ops(num_ins * num_ops);
vector<int> input_keys(num_ins * num_ops);
vector<float> input_values(num_ins * num_ops);
generate(input_keys.begin(), input_keys.end(), [](){return rand()%MOD;});
generate(input_values.begin(), input_values.end(), [](){return float(rand())/RAND_MAX;});
generate(ops.begin(), ops.end(), [&ref](){return ref[rand()%(int)ref.size()];});
cudaEventRecord(stop, 0); // Stop time measuring
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for generating random data is: "<<cuda_time/1000<<"s"<<endl;
cudaEventRecord(start, 0);
GPUMapTest gpu_test(num_ins);
gpu_test.loadOps(ops, input_keys, input_values, num_ops);
cudaEventRecord(stop, 0); // Stop time measuring
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for preparing maps is: "<<cuda_time/1000<<"s"<<endl;
cudaEventRecord(start, 0);
vector<float> ans;
gpu_test.procOps(ans);
cudaEventRecord(stop, 0); // Stop time measuring
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for processing operations is: "<<cuda_time/1000<<"s"<<endl;
cout<<"Showing GPU code answers:"<<endl;
for(int i=0;i<num_ins*num_ops ; i+=num_ins*num_ops/25 + 1) cout<<ans[i]<<' ';
cout << endl;
cout<<"DONE!"<<endl;
return 0;
} | /*
We consider 1024 map, which are initially constructed with (at most)size = 1024 key, value pairs, for which keys are integers and values are float point numbers.
Then each of them processes 262,144 operations.
The operations include:
'i': insert a key-value pair, or modify the original value. (if the map is full, do nothing)
'r': remove a key.
'g': get the value for a key. If that key dose not exist, return 0
*/
#include <hip/hip_runtime.h>
#include <bits/stdc++.h>
#include <cassert>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#include <thrust/sequence.h>
#include <thrust/find.h>
#include <thrust/execution_policy.h>
#define to_ptr(x) thrust::raw_pointer_cast(&x[0])
#define gpu_copy(x, y) thrust::copy((x).begin(), (x).end(), (y).begin())
#define gpu_copy_to(x, y, pos) thrust::copy((x).begin(), (x).end(), (y).begin() + (pos))
#define gpu_seq(x) thrust::sequence((x).begin(), (x).end())
#define host_find(x, n, key) thrust::find((x), (x)+n, key);
#define device_find(x, n, key) thrust::find(thrust::device, (x), (x)+n, key)
#define def_dvec(t) thrust::device_vector<t>
using namespace std;
const int BLOCK_SIZE = 512;
const int NUM_INSTANCE = 1024;
const int NUM_OPERATION = 262144;
const int MOD = 10000;
const int MAX_SIZE = 31;
__device__ int gpuIndex(int size, int *keys, int key){
return (int)(device_find(keys, size, key) - keys);
}
__global__ void procKernel(int n_ins, int *sizes, int *keys, float *values,
int n_ops, char *ops, int *input_keys, float *input_values, float *ans){
int b_id = blockIdx.x, b_sz = blockDim.x, t_id = threadIdx.x;
int global_idx = b_id*b_sz + t_id;
int sz = sizes[global_idx];
int start = global_idx*MAX_SIZE;
for(int i=global_idx*n_ops; i<(global_idx+1)*n_ops; ++i){
int key = input_keys[i];
char op = ops[i];
float value = input_values[i];
int idx = gpuIndex(sz, keys + start, key);
if(op == 'g'){
ans[i] = (idx == sz? 0.:values[start+idx]);
}
else if(op == 'r'){
sz -= (idx != sz);
keys[start+idx] = keys[start+sz];
values[start+idx] = values[start+sz];
}
else{
keys[start + idx] = key;
keys[start + idx] = value;
sz += (idx==sz && sz < MAX_SIZE);
}
}
sizes[global_idx] = sz;
}
class GPUMapTest{
int N_ins, N_ops;
def_dvec(int) dkeys, dinkeys, dsizes;
def_dvec(float) dvalues, dinvalues;
def_dvec(char) dops;
public:
GPUMapTest(int num_ins): N_ins(num_ins){
dkeys.resize(num_ins * MAX_SIZE);
dvalues.resize(num_ins * MAX_SIZE);
dsizes.assign(num_ins, 0);
}
void loadOps(const vector<char> &ops, const vector<int> &inkeys,const vector<float> &invals, int n_ops){
N_ops = n_ops;
assert((int)ops.size() == N_ops * N_ins);
dinkeys.resize(N_ops * N_ins);
dinvalues.resize(N_ops * N_ins);
dops.resize(N_ops * N_ins);
gpu_copy(ops, dops);
gpu_copy(inkeys, dinkeys);
gpu_copy(invals, dinvalues);
}
void procOps(vector<float> &ans){
ans.resize(N_ins * N_ops);
def_dvec(float) dans(N_ins * N_ops);
int n_block = (N_ins+BLOCK_SIZE-1)/BLOCK_SIZE;
procKernel<<<n_block, BLOCK_SIZE>>>(N_ins, to_ptr(dsizes), to_ptr(dkeys), to_ptr(dvalues), N_ops,
to_ptr(dops), to_ptr(dinkeys), to_ptr(dinvalues), to_ptr(dans));
gpu_copy(dans, ans);
return ;
}
};
int main(int argc, char *argv[]){
srand(0);
int num_ins = NUM_INSTANCE, num_ops = NUM_OPERATION;
if(argc > 1) num_ins = stoi(argv[1]);
if(argc > 2) num_ops = stoi(argv[2]);
/* using cudaEvent to evaluate time */
hipEvent_t start, stop;
float cuda_time;
hipEventCreate(&start); // creating the event 1
hipEventCreate(&stop); // creating the event 2
/* Generating data*/
hipEventRecord(start, 0);
string ref;
ref += string(1500, 'g') + string(300, 'i') + string(200, 'r');
vector<char> ops(num_ins * num_ops);
vector<int> input_keys(num_ins * num_ops);
vector<float> input_values(num_ins * num_ops);
generate(input_keys.begin(), input_keys.end(), [](){return rand()%MOD;});
generate(input_values.begin(), input_values.end(), [](){return float(rand())/RAND_MAX;});
generate(ops.begin(), ops.end(), [&ref](){return ref[rand()%(int)ref.size()];});
hipEventRecord(stop, 0); // Stop time measuring
hipEventSynchronize(stop);
hipEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for generating random data is: "<<cuda_time/1000<<"s"<<endl;
hipEventRecord(start, 0);
GPUMapTest gpu_test(num_ins);
gpu_test.loadOps(ops, input_keys, input_values, num_ops);
hipEventRecord(stop, 0); // Stop time measuring
hipEventSynchronize(stop);
hipEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for preparing maps is: "<<cuda_time/1000<<"s"<<endl;
hipEventRecord(start, 0);
vector<float> ans;
gpu_test.procOps(ans);
hipEventRecord(stop, 0); // Stop time measuring
hipEventSynchronize(stop);
hipEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for processing operations is: "<<cuda_time/1000<<"s"<<endl;
cout<<"Showing GPU code answers:"<<endl;
for(int i=0;i<num_ins*num_ops ; i+=num_ins*num_ops/25 + 1) cout<<ans[i]<<' ';
cout << endl;
cout<<"DONE!"<<endl;
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
//#include "bmp.h"
extern "C" void write_bmp(unsigned char* data, int width, int height);
extern "C" unsigned char* read_bmp(char* filename);
//#include "host_blur.h"
extern "C" void host_blur(unsigned char* inputImage, unsigned char* outputImage, int size);
void print_properties(){
int deviceCount = 0;
cudaGetDeviceCount(&deviceCount);
printf("Device count: %d\n", deviceCount);
cudaDeviceProp p;
cudaSetDevice(0);
cudaGetDeviceProperties (&p, 0);
printf("Compute capability: %d.%d\n", p.major, p.minor);
printf("Name: %s\n" , p.name);
printf("\n\n");
}
__global__ void device_blur(unsigned char* input, unsigned char* output) {
uint i = (blockIdx.x * blockDim.x) + threadIdx.x;
uint j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i != 0 && j != 0 && i != 512 && j != 512) {
output[i*512 + j] = 0;
for(int k = -1; k < 2; k++){
for(int l = -1; l < 2; l++){
output[i * 512 + j] += (input[(i + k)*512 + (j + l)] / 9.0);
}
}
}
}
int main(int argc,char **argv) {
//Prints some device properties, also to make sure the GPU works etc.
print_properties();
unsigned char* A = read_bmp("peppers.bmp");
unsigned char* B = (unsigned char*)malloc(sizeof(unsigned char) * 512 * 512);
//Allocate buffers for the input image and the output image on the device
unsigned char* A_device;
cudaMalloc((void**)&A_device, sizeof(unsigned char)*512*512);
unsigned char* B_device;
cudaMalloc((void**)&B_device, sizeof(unsigned char)*512*512);
//Transfer the input image from the host to the device
cudaMemcpy(A_device, A, sizeof(unsigned char)*512*512, cudaMemcpyHostToDevice);
cudaMemcpy(B_device, B, sizeof(unsigned char)*512*512, cudaMemcpyHostToDevice);
//Launch the kernel which does the bluring
//The grid consists of 4096 blocks, 64 threads per block
dim3 grid(64, 64);
dim3 block(8, 8);
device_blur<<<grid, block>>>(A_device, B_device);
//Transfer the result back to the host.
cudaMemcpy(B, B_device, sizeof(unsigned char)*512*512, cudaMemcpyDeviceToHost);
write_bmp(B, 512, 512);
free(A);
free(B);
return 0;
} | .file "tmpxft_0007750b_00000000-6_blur_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device count: %d\n"
.LC1:
.string "Compute capability: %d.%d\n"
.LC2:
.string "Name: %s\n"
.LC3:
.string "\n\n"
.text
.globl _Z16print_propertiesv
.type _Z16print_propertiesv, @function
_Z16print_propertiesv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1056, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
leaq 16(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z16print_propertiesv, .-_Z16print_propertiesv
.globl _Z33__device_stub__Z11device_blurPhS_PhS_
.type _Z33__device_stub__Z11device_blurPhS_PhS_, @function
_Z33__device_stub__Z11device_blurPhS_PhS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11device_blurPhS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z11device_blurPhS_PhS_, .-_Z33__device_stub__Z11device_blurPhS_PhS_
.globl _Z11device_blurPhS_
.type _Z11device_blurPhS_, @function
_Z11device_blurPhS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11device_blurPhS_PhS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z11device_blurPhS_, .-_Z11device_blurPhS_
.section .rodata.str1.1
.LC4:
.string "peppers.bmp"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call _Z16print_propertiesv
leaq .LC4(%rip), %rdi
call read_bmp@PLT
movq %rax, %rbp
movl $262144, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $262144, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $262144, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 16(%rsp)
movl $64, 20(%rsp)
movl $8, 28(%rsp)
movl $8, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movl $2, %ecx
movl $262144, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $512, %edx
movl $512, %esi
movq %rbx, %rdi
call write_bmp@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z33__device_stub__Z11device_blurPhS_PhS_
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z11device_blurPhS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z11device_blurPhS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
//#include "bmp.h"
extern "C" void write_bmp(unsigned char* data, int width, int height);
extern "C" unsigned char* read_bmp(char* filename);
//#include "host_blur.h"
extern "C" void host_blur(unsigned char* inputImage, unsigned char* outputImage, int size);
void print_properties(){
int deviceCount = 0;
cudaGetDeviceCount(&deviceCount);
printf("Device count: %d\n", deviceCount);
cudaDeviceProp p;
cudaSetDevice(0);
cudaGetDeviceProperties (&p, 0);
printf("Compute capability: %d.%d\n", p.major, p.minor);
printf("Name: %s\n" , p.name);
printf("\n\n");
}
__global__ void device_blur(unsigned char* input, unsigned char* output) {
uint i = (blockIdx.x * blockDim.x) + threadIdx.x;
uint j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i != 0 && j != 0 && i != 512 && j != 512) {
output[i*512 + j] = 0;
for(int k = -1; k < 2; k++){
for(int l = -1; l < 2; l++){
output[i * 512 + j] += (input[(i + k)*512 + (j + l)] / 9.0);
}
}
}
}
int main(int argc,char **argv) {
//Prints some device properties, also to make sure the GPU works etc.
print_properties();
unsigned char* A = read_bmp("peppers.bmp");
unsigned char* B = (unsigned char*)malloc(sizeof(unsigned char) * 512 * 512);
//Allocate buffers for the input image and the output image on the device
unsigned char* A_device;
cudaMalloc((void**)&A_device, sizeof(unsigned char)*512*512);
unsigned char* B_device;
cudaMalloc((void**)&B_device, sizeof(unsigned char)*512*512);
//Transfer the input image from the host to the device
cudaMemcpy(A_device, A, sizeof(unsigned char)*512*512, cudaMemcpyHostToDevice);
cudaMemcpy(B_device, B, sizeof(unsigned char)*512*512, cudaMemcpyHostToDevice);
//Launch the kernel which does the bluring
//The grid consists of 4096 blocks, 64 threads per block
dim3 grid(64, 64);
dim3 block(8, 8);
device_blur<<<grid, block>>>(A_device, B_device);
//Transfer the result back to the host.
cudaMemcpy(B, B_device, sizeof(unsigned char)*512*512, cudaMemcpyDeviceToHost);
write_bmp(B, 512, 512);
free(A);
free(B);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
//#include "bmp.h"
extern "C" void write_bmp(unsigned char* data, int width, int height);
extern "C" unsigned char* read_bmp(char* filename);
//#include "host_blur.h"
extern "C" void host_blur(unsigned char* inputImage, unsigned char* outputImage, int size);
void print_properties(){
int deviceCount = 0;
hipGetDeviceCount(&deviceCount);
printf("Device count: %d\n", deviceCount);
hipDeviceProp_t p;
hipSetDevice(0);
hipGetDeviceProperties (&p, 0);
printf("Compute capability: %d.%d\n", p.major, p.minor);
printf("Name: %s\n" , p.name);
printf("\n\n");
}
__global__ void device_blur(unsigned char* input, unsigned char* output) {
uint i = (blockIdx.x * blockDim.x) + threadIdx.x;
uint j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i != 0 && j != 0 && i != 512 && j != 512) {
output[i*512 + j] = 0;
for(int k = -1; k < 2; k++){
for(int l = -1; l < 2; l++){
output[i * 512 + j] += (input[(i + k)*512 + (j + l)] / 9.0);
}
}
}
}
int main(int argc,char **argv) {
//Prints some device properties, also to make sure the GPU works etc.
print_properties();
unsigned char* A = read_bmp("peppers.bmp");
unsigned char* B = (unsigned char*)malloc(sizeof(unsigned char) * 512 * 512);
//Allocate buffers for the input image and the output image on the device
unsigned char* A_device;
hipMalloc((void**)&A_device, sizeof(unsigned char)*512*512);
unsigned char* B_device;
hipMalloc((void**)&B_device, sizeof(unsigned char)*512*512);
//Transfer the input image from the host to the device
hipMemcpy(A_device, A, sizeof(unsigned char)*512*512, hipMemcpyHostToDevice);
hipMemcpy(B_device, B, sizeof(unsigned char)*512*512, hipMemcpyHostToDevice);
//Launch the kernel which does the bluring
//The grid consists of 4096 blocks, 64 threads per block
dim3 grid(64, 64);
dim3 block(8, 8);
device_blur<<<grid, block>>>(A_device, B_device);
//Transfer the result back to the host.
hipMemcpy(B, B_device, sizeof(unsigned char)*512*512, hipMemcpyDeviceToHost);
write_bmp(B, 512, 512);
free(A);
free(B);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
//#include "bmp.h"
extern "C" void write_bmp(unsigned char* data, int width, int height);
extern "C" unsigned char* read_bmp(char* filename);
//#include "host_blur.h"
extern "C" void host_blur(unsigned char* inputImage, unsigned char* outputImage, int size);
void print_properties(){
int deviceCount = 0;
hipGetDeviceCount(&deviceCount);
printf("Device count: %d\n", deviceCount);
hipDeviceProp_t p;
hipSetDevice(0);
hipGetDeviceProperties (&p, 0);
printf("Compute capability: %d.%d\n", p.major, p.minor);
printf("Name: %s\n" , p.name);
printf("\n\n");
}
__global__ void device_blur(unsigned char* input, unsigned char* output) {
uint i = (blockIdx.x * blockDim.x) + threadIdx.x;
uint j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i != 0 && j != 0 && i != 512 && j != 512) {
output[i*512 + j] = 0;
for(int k = -1; k < 2; k++){
for(int l = -1; l < 2; l++){
output[i * 512 + j] += (input[(i + k)*512 + (j + l)] / 9.0);
}
}
}
}
int main(int argc,char **argv) {
//Prints some device properties, also to make sure the GPU works etc.
print_properties();
unsigned char* A = read_bmp("peppers.bmp");
unsigned char* B = (unsigned char*)malloc(sizeof(unsigned char) * 512 * 512);
//Allocate buffers for the input image and the output image on the device
unsigned char* A_device;
hipMalloc((void**)&A_device, sizeof(unsigned char)*512*512);
unsigned char* B_device;
hipMalloc((void**)&B_device, sizeof(unsigned char)*512*512);
//Transfer the input image from the host to the device
hipMemcpy(A_device, A, sizeof(unsigned char)*512*512, hipMemcpyHostToDevice);
hipMemcpy(B_device, B, sizeof(unsigned char)*512*512, hipMemcpyHostToDevice);
//Launch the kernel which does the bluring
//The grid consists of 4096 blocks, 64 threads per block
dim3 grid(64, 64);
dim3 block(8, 8);
device_blur<<<grid, block>>>(A_device, B_device);
//Transfer the result back to the host.
hipMemcpy(B, B_device, sizeof(unsigned char)*512*512, hipMemcpyDeviceToHost);
write_bmp(B, 512, 512);
free(A);
free(B);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11device_blurPhS_
.globl _Z11device_blurPhS_
.p2align 8
.type _Z11device_blurPhS_,@function
_Z11device_blurPhS_:
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
s_mul_i32 s15, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, s15, v0
v_and_b32_e32 v4, 0xfffffdff, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v5, 0xfffffdff, v3
v_cmp_ne_u32_e32 vcc_lo, 0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s2, 0, v5
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
s_load_b128 s[0:3], s[0:1], 0x0
s_mul_i32 s14, s14, s4
v_lshl_add_u32 v4, v2, 9, v3
s_lshl_b32 s4, s14, 9
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 9, v1
v_add3_u32 v5, s15, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add3_u32 v3, v5, v3, 0xfffffdff
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s4, s2, v4
v_add_co_ci_u32_e64 v1, null, s3, 0, s4
s_mov_b32 s4, -1
global_store_b8 v4, v2, s[2:3]
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_mov_b32 s2, 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v4, s2, v3
v_and_b32_e32 v2, 0xff, v2
s_add_i32 s2, s2, 1
s_cmp_eq_u32 s2, 3
global_load_u8 v4, v4, s[0:1]
v_and_b32_e32 v2, 0xffff, v2
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[4:5], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[6:7], null, 0x40220000, 0x40220000, v[4:5]
v_div_scale_f64 v[12:13], vcc_lo, v[4:5], 0x40220000, v[4:5]
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_mul_f64 v[10:11], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
v_cvt_f64_u32_e32 v[8:9], v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[4:5], v[6:7], 0x40220000, v[4:5]
v_add_f64 v[4:5], v[4:5], v[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f64_e32 v2, v[4:5]
global_store_b8 v[0:1], v2, off
s_cbranch_scc0 .LBB0_3
v_add_nc_u32_e32 v3, 0x200, v3
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 2
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11device_blurPhS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11device_blurPhS_, .Lfunc_end0-_Z11device_blurPhS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11device_blurPhS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11device_blurPhS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
//#include "bmp.h"
extern "C" void write_bmp(unsigned char* data, int width, int height);
extern "C" unsigned char* read_bmp(char* filename);
//#include "host_blur.h"
extern "C" void host_blur(unsigned char* inputImage, unsigned char* outputImage, int size);
void print_properties(){
int deviceCount = 0;
hipGetDeviceCount(&deviceCount);
printf("Device count: %d\n", deviceCount);
hipDeviceProp_t p;
hipSetDevice(0);
hipGetDeviceProperties (&p, 0);
printf("Compute capability: %d.%d\n", p.major, p.minor);
printf("Name: %s\n" , p.name);
printf("\n\n");
}
__global__ void device_blur(unsigned char* input, unsigned char* output) {
uint i = (blockIdx.x * blockDim.x) + threadIdx.x;
uint j = (blockIdx.y * blockDim.y) + threadIdx.y;
if (i != 0 && j != 0 && i != 512 && j != 512) {
output[i*512 + j] = 0;
for(int k = -1; k < 2; k++){
for(int l = -1; l < 2; l++){
output[i * 512 + j] += (input[(i + k)*512 + (j + l)] / 9.0);
}
}
}
}
int main(int argc,char **argv) {
//Prints some device properties, also to make sure the GPU works etc.
print_properties();
unsigned char* A = read_bmp("peppers.bmp");
unsigned char* B = (unsigned char*)malloc(sizeof(unsigned char) * 512 * 512);
//Allocate buffers for the input image and the output image on the device
unsigned char* A_device;
hipMalloc((void**)&A_device, sizeof(unsigned char)*512*512);
unsigned char* B_device;
hipMalloc((void**)&B_device, sizeof(unsigned char)*512*512);
//Transfer the input image from the host to the device
hipMemcpy(A_device, A, sizeof(unsigned char)*512*512, hipMemcpyHostToDevice);
hipMemcpy(B_device, B, sizeof(unsigned char)*512*512, hipMemcpyHostToDevice);
//Launch the kernel which does the bluring
//The grid consists of 4096 blocks, 64 threads per block
dim3 grid(64, 64);
dim3 block(8, 8);
device_blur<<<grid, block>>>(A_device, B_device);
//Transfer the result back to the host.
hipMemcpy(B, B_device, sizeof(unsigned char)*512*512, hipMemcpyDeviceToHost);
write_bmp(B, 512, 512);
free(A);
free(B);
return 0;
} | .text
.file "blur_cuda.hip"
.globl _Z16print_propertiesv # -- Begin function _Z16print_propertiesv
.p2align 4, 0x90
.type _Z16print_propertiesv,@function
_Z16print_propertiesv: # @_Z16print_propertiesv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl 12(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
leaq 16(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 376(%rsp), %esi
movl 380(%rsp), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z16print_propertiesv, .Lfunc_end0-_Z16print_propertiesv
.cfi_endproc
# -- End function
.globl _Z26__device_stub__device_blurPhS_ # -- Begin function _Z26__device_stub__device_blurPhS_
.p2align 4, 0x90
.type _Z26__device_stub__device_blurPhS_,@function
_Z26__device_stub__device_blurPhS_: # @_Z26__device_stub__device_blurPhS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11device_blurPhS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z26__device_stub__device_blurPhS_, .Lfunc_end1-_Z26__device_stub__device_blurPhS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1560, %rsp # imm = 0x618
.cfi_def_cfa_offset 1584
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $0, 8(%rsp)
leaq 8(%rsp), %rdi
callq hipGetDeviceCount
movl 8(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
leaq 80(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 440(%rsp), %esi
movl 444(%rsp), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.4, %edi
callq read_bmp
movq %rax, %rbx
movl $262144, %edi # imm = 0x40000
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
movq %rsp, %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
movq 24(%rsp), %rdi
movl $262144, %edx # imm = 0x40000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $262144, %edx # imm = 0x40000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 24(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11device_blurPhS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq (%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $512, %esi # imm = 0x200
movl $512, %edx # imm = 0x200
callq write_bmp
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $1560, %rsp # imm = 0x618
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11device_blurPhS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device count: %d\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Compute capability: %d.%d\n"
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Name: %s\n"
.size .L.str.2, 10
.type _Z11device_blurPhS_,@object # @_Z11device_blurPhS_
.section .rodata,"a",@progbits
.globl _Z11device_blurPhS_
.p2align 3, 0x0
_Z11device_blurPhS_:
.quad _Z26__device_stub__device_blurPhS_
.size _Z11device_blurPhS_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "peppers.bmp"
.size .L.str.4, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11device_blurPhS_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__device_blurPhS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11device_blurPhS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007750b_00000000-6_blur_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device count: %d\n"
.LC1:
.string "Compute capability: %d.%d\n"
.LC2:
.string "Name: %s\n"
.LC3:
.string "\n\n"
.text
.globl _Z16print_propertiesv
.type _Z16print_propertiesv, @function
_Z16print_propertiesv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1056, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
leaq 16(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z16print_propertiesv, .-_Z16print_propertiesv
.globl _Z33__device_stub__Z11device_blurPhS_PhS_
.type _Z33__device_stub__Z11device_blurPhS_PhS_, @function
_Z33__device_stub__Z11device_blurPhS_PhS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11device_blurPhS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z11device_blurPhS_PhS_, .-_Z33__device_stub__Z11device_blurPhS_PhS_
.globl _Z11device_blurPhS_
.type _Z11device_blurPhS_, @function
_Z11device_blurPhS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11device_blurPhS_PhS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z11device_blurPhS_, .-_Z11device_blurPhS_
.section .rodata.str1.1
.LC4:
.string "peppers.bmp"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call _Z16print_propertiesv
leaq .LC4(%rip), %rdi
call read_bmp@PLT
movq %rax, %rbp
movl $262144, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $262144, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $262144, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 16(%rsp)
movl $64, 20(%rsp)
movl $8, 28(%rsp)
movl $8, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movl $2, %ecx
movl $262144, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $512, %edx
movl $512, %esi
movq %rbx, %rdi
call write_bmp@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z33__device_stub__Z11device_blurPhS_PhS_
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z11device_blurPhS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z11device_blurPhS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "blur_cuda.hip"
.globl _Z16print_propertiesv # -- Begin function _Z16print_propertiesv
.p2align 4, 0x90
.type _Z16print_propertiesv,@function
_Z16print_propertiesv: # @_Z16print_propertiesv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl 12(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
leaq 16(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 376(%rsp), %esi
movl 380(%rsp), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z16print_propertiesv, .Lfunc_end0-_Z16print_propertiesv
.cfi_endproc
# -- End function
.globl _Z26__device_stub__device_blurPhS_ # -- Begin function _Z26__device_stub__device_blurPhS_
.p2align 4, 0x90
.type _Z26__device_stub__device_blurPhS_,@function
_Z26__device_stub__device_blurPhS_: # @_Z26__device_stub__device_blurPhS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11device_blurPhS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z26__device_stub__device_blurPhS_, .Lfunc_end1-_Z26__device_stub__device_blurPhS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1560, %rsp # imm = 0x618
.cfi_def_cfa_offset 1584
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $0, 8(%rsp)
leaq 8(%rsp), %rdi
callq hipGetDeviceCount
movl 8(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
leaq 80(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 440(%rsp), %esi
movl 444(%rsp), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.4, %edi
callq read_bmp
movq %rax, %rbx
movl $262144, %edi # imm = 0x40000
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
movq %rsp, %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
movq 24(%rsp), %rdi
movl $262144, %edx # imm = 0x40000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $262144, %edx # imm = 0x40000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 24(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11device_blurPhS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq (%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $512, %esi # imm = 0x200
movl $512, %edx # imm = 0x200
callq write_bmp
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $1560, %rsp # imm = 0x618
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11device_blurPhS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device count: %d\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Compute capability: %d.%d\n"
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Name: %s\n"
.size .L.str.2, 10
.type _Z11device_blurPhS_,@object # @_Z11device_blurPhS_
.section .rodata,"a",@progbits
.globl _Z11device_blurPhS_
.p2align 3, 0x0
_Z11device_blurPhS_:
.quad _Z26__device_stub__device_blurPhS_
.size _Z11device_blurPhS_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "peppers.bmp"
.size .L.str.4, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11device_blurPhS_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__device_blurPhS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11device_blurPhS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* CSCI 563 Programming Assignment 2
Clayton Kramp
*/
#include <iostream>
#include <fstream>
using namespace std;
// Main Device Function to be used to count number of ones
__global__ void countOnes(int* A, int* count, int row, int col) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= row || j >= col) return;
if (A[i * col + j] == 1) {
// Atomic addition for race conditions
atomicAdd(count, 1);
}
}
int main(int argc, char* argv[]) {
if (argc != 2) {
cerr << "Arguments error" << endl;
return -1;
}
ifstream file(argv[1]);
if (!file.good()) {
cerr << "Bad input" << endl;
return -1;
}
int row, col;
file >> col >> row;
int** A = new int*[row];
A[0] = new int[row*col];
for (int i = 1; i < row; i++) A[i] = A[i-1] + col;
// Fill in Host Array A
for (int i = 0; i < row; i++) {
for (int j = 0; j < col; j++) {
int element;
file >> element;
A[i][j] = element;
}
}
file.close();
int* count = new int;
*count = 0;
// Copy memory to device array deviceA
int* deviceA;
int bytes = row * col * sizeof(int);
cudaMalloc(&deviceA, bytes);
cudaMemcpy(deviceA, A[0], bytes, cudaMemcpyHostToDevice);
// Copy deviceCount
int* deviceCount;
cudaMalloc(&deviceCount, 4);
cudaMemcpy(deviceCount, count, 4, cudaMemcpyHostToDevice);
dim3 threadsPerBlock(8, 8, 1);
dim3 numBlocks((col + threadsPerBlock.x-1) / threadsPerBlock.x,
(row + threadsPerBlock.y-1) / threadsPerBlock.y, 1);
// Launch the program
countOnes<<<numBlocks, threadsPerBlock>>>(deviceA, deviceCount, row, col);
//cudaDeviceSynchronize();
// Copy back from device the deviceCount
cudaMemcpy(count, deviceCount, 4, cudaMemcpyDeviceToHost);
cout << *count << endl;
delete A[0];
delete A;
cudaFree(deviceA);
cudaFree(deviceCount);
return 0;
} | code for sm_80
Function : _Z9countOnesPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R3, c[0x0][0x174], R0 ; /* 0x00005d0003037a24 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0202 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0120*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0130*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0140*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0150*/ POPC R5, UR6 ; /* 0x0000000600057d09 */
/* 0x000e620008000000 */
/*0160*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fc80000000f00 */
/*0170*/ ISETP.EQ.U32.AND P0, PT, R0, UR7, PT ; /* 0x0000000700007c0c */
/* 0x001fda000bf02070 */
/*0180*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x002fe2000c10e184 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* CSCI 563 Programming Assignment 2
Clayton Kramp
*/
#include <iostream>
#include <fstream>
using namespace std;
// Main Device Function to be used to count number of ones
__global__ void countOnes(int* A, int* count, int row, int col) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= row || j >= col) return;
if (A[i * col + j] == 1) {
// Atomic addition for race conditions
atomicAdd(count, 1);
}
}
int main(int argc, char* argv[]) {
if (argc != 2) {
cerr << "Arguments error" << endl;
return -1;
}
ifstream file(argv[1]);
if (!file.good()) {
cerr << "Bad input" << endl;
return -1;
}
int row, col;
file >> col >> row;
int** A = new int*[row];
A[0] = new int[row*col];
for (int i = 1; i < row; i++) A[i] = A[i-1] + col;
// Fill in Host Array A
for (int i = 0; i < row; i++) {
for (int j = 0; j < col; j++) {
int element;
file >> element;
A[i][j] = element;
}
}
file.close();
int* count = new int;
*count = 0;
// Copy memory to device array deviceA
int* deviceA;
int bytes = row * col * sizeof(int);
cudaMalloc(&deviceA, bytes);
cudaMemcpy(deviceA, A[0], bytes, cudaMemcpyHostToDevice);
// Copy deviceCount
int* deviceCount;
cudaMalloc(&deviceCount, 4);
cudaMemcpy(deviceCount, count, 4, cudaMemcpyHostToDevice);
dim3 threadsPerBlock(8, 8, 1);
dim3 numBlocks((col + threadsPerBlock.x-1) / threadsPerBlock.x,
(row + threadsPerBlock.y-1) / threadsPerBlock.y, 1);
// Launch the program
countOnes<<<numBlocks, threadsPerBlock>>>(deviceA, deviceCount, row, col);
//cudaDeviceSynchronize();
// Copy back from device the deviceCount
cudaMemcpy(count, deviceCount, 4, cudaMemcpyDeviceToHost);
cout << *count << endl;
delete A[0];
delete A;
cudaFree(deviceA);
cudaFree(deviceCount);
return 0;
} | .file "tmpxft_000556f3_00000000-6_Homework2_1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9countOnesPiS_iiPiS_ii
.type _Z32__device_stub__Z9countOnesPiS_iiPiS_ii, @function
_Z32__device_stub__Z9countOnesPiS_iiPiS_ii:
.LFB3825:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9countOnesPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3825:
.size _Z32__device_stub__Z9countOnesPiS_iiPiS_ii, .-_Z32__device_stub__Z9countOnesPiS_iiPiS_ii
.globl _Z9countOnesPiS_ii
.type _Z9countOnesPiS_ii, @function
_Z9countOnesPiS_ii:
.LFB3826:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9countOnesPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3826:
.size _Z9countOnesPiS_ii, .-_Z9countOnesPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9countOnesPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3828:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9countOnesPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3828:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC1:
.string "Arguments error"
.LC2:
.string "Bad input"
.text
.globl main
.type main, @function
main:
.LFB3800:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3800
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $584, %rsp
.cfi_def_cfa_offset 640
movq %fs:40, %rax
movq %rax, 568(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L46
movq 8(%rsi), %rsi
leaq 48(%rsp), %rdi
movl $8, %edx
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
movl 336(%rsp), %r15d
testl %r15d, %r15d
jne .L47
leaq 4(%rsp), %rsi
leaq 48(%rsp), %rdi
.LEHB1:
call _ZNSirsERi@PLT
.LEHE1:
jmp .L48
.L46:
leaq .LC1(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
.LEHB2:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE2:
movl $-1, %r15d
jmp .L13
.L47:
leaq .LC2(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
.LEHB3:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L49
.L48:
movq %rax, %rdi
movq %rsp, %rsi
call _ZNSirsERi@PLT
movslq (%rsp), %rax
movabsq $1152921504606846975, %rdx
cmpq %rax, %rdx
jb .L18
leaq 0(,%rax,8), %rdi
call _Znam@PLT
movq %rax, %r14
movl (%rsp), %eax
imull 4(%rsp), %eax
cltq
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L50
leaq 0(,%rax,4), %rdi
call _Znam@PLT
jmp .L51
.L18:
movq 568(%rsp), %rax
subq %fs:40, %rax
je .L20
call __stack_chk_fail@PLT
.L20:
call __cxa_throw_bad_array_new_length@PLT
.L38:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 568(%rsp), %rax
subq %fs:40, %rax
je .L34
call __stack_chk_fail@PLT
.L51:
movq %rax, (%r14)
movl (%rsp), %edx
cmpl $1, %edx
jle .L52
movslq 4(%rsp), %rcx
salq $2, %rcx
movq %r14, %rax
leal -1(%rdx), %edx
leaq (%r14,%rdx,8), %rsi
.L25:
movq %rcx, %rdx
addq (%rax), %rdx
movq %rdx, 8(%rax)
addq $8, %rax
cmpq %rsi, %rax
jne .L25
.L26:
movq %r14, %rbp
movl %r15d, %r13d
leaq 36(%rsp), %r12
jmp .L28
.L50:
movq 568(%rsp), %rax
subq %fs:40, %rax
je .L23
call __stack_chk_fail@PLT
.L23:
call __cxa_throw_bad_array_new_length@PLT
.L52:
testl %edx, %edx
jg .L26
.L27:
leaq 48(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
jmp .L53
.L54:
movq 0(%rbp), %rax
movl 36(%rsp), %edx
movl %edx, (%rax,%rbx,4)
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jle .L30
.L29:
leaq 48(%rsp), %rdi
movq %r12, %rsi
call _ZNSirsERi@PLT
jmp .L54
.L30:
addl $1, %r13d
addq $8, %rbp
cmpl %r13d, (%rsp)
jle .L27
.L28:
movl $0, %ebx
cmpl $0, 4(%rsp)
jg .L29
jmp .L30
.L53:
movl $4, %edi
call _Znwm@PLT
movq %rax, %rbp
movl $0, (%rax)
movl (%rsp), %ebx
imull 4(%rsp), %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq (%r14), %r12
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl (%rsp), %eax
addl $7, %eax
shrl $3, %eax
movl 4(%rsp), %ecx
leal 7(%rcx), %edx
shrl $3, %edx
movl %edx, 36(%rsp)
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $8, 24(%rsp)
movl $8, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L31
movl 4(%rsp), %ecx
movl (%rsp), %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z9countOnesPiS_iiPiS_ii
.L31:
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl 0(%rbp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
testq %r12, %r12
je .L32
movl $4, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
.L32:
movl $8, %esi
movq %r14, %rdi
call _ZdlPvm@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
.LEHE3:
jmp .L17
.L49:
movl $-1, %r15d
.L17:
leaq 48(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L13:
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl %r15d, %eax
addq $584, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3800:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3800-.LLSDACSB3800
.LLSDACSB3800:
.uleb128 .LEHB0-.LFB3800
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3800
.uleb128 .LEHE1-.LEHB1
.uleb128 .L38-.LFB3800
.uleb128 0
.uleb128 .LEHB2-.LFB3800
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3800
.uleb128 .LEHE3-.LEHB3
.uleb128 .L38-.LFB3800
.uleb128 0
.uleb128 .LEHB4-.LFB3800
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE3800:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* CSCI 563 Programming Assignment 2
Clayton Kramp
*/
#include <iostream>
#include <fstream>
using namespace std;
// Main Device Function to be used to count number of ones
__global__ void countOnes(int* A, int* count, int row, int col) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= row || j >= col) return;
if (A[i * col + j] == 1) {
// Atomic addition for race conditions
atomicAdd(count, 1);
}
}
int main(int argc, char* argv[]) {
if (argc != 2) {
cerr << "Arguments error" << endl;
return -1;
}
ifstream file(argv[1]);
if (!file.good()) {
cerr << "Bad input" << endl;
return -1;
}
int row, col;
file >> col >> row;
int** A = new int*[row];
A[0] = new int[row*col];
for (int i = 1; i < row; i++) A[i] = A[i-1] + col;
// Fill in Host Array A
for (int i = 0; i < row; i++) {
for (int j = 0; j < col; j++) {
int element;
file >> element;
A[i][j] = element;
}
}
file.close();
int* count = new int;
*count = 0;
// Copy memory to device array deviceA
int* deviceA;
int bytes = row * col * sizeof(int);
cudaMalloc(&deviceA, bytes);
cudaMemcpy(deviceA, A[0], bytes, cudaMemcpyHostToDevice);
// Copy deviceCount
int* deviceCount;
cudaMalloc(&deviceCount, 4);
cudaMemcpy(deviceCount, count, 4, cudaMemcpyHostToDevice);
dim3 threadsPerBlock(8, 8, 1);
dim3 numBlocks((col + threadsPerBlock.x-1) / threadsPerBlock.x,
(row + threadsPerBlock.y-1) / threadsPerBlock.y, 1);
// Launch the program
countOnes<<<numBlocks, threadsPerBlock>>>(deviceA, deviceCount, row, col);
//cudaDeviceSynchronize();
// Copy back from device the deviceCount
cudaMemcpy(count, deviceCount, 4, cudaMemcpyDeviceToHost);
cout << *count << endl;
delete A[0];
delete A;
cudaFree(deviceA);
cudaFree(deviceCount);
return 0;
} | /* CSCI 563 Programming Assignment 2
Clayton Kramp
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
using namespace std;
// Main Device Function to be used to count number of ones
__global__ void countOnes(int* A, int* count, int row, int col) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= row || j >= col) return;
if (A[i * col + j] == 1) {
// Atomic addition for race conditions
atomicAdd(count, 1);
}
}
int main(int argc, char* argv[]) {
if (argc != 2) {
cerr << "Arguments error" << endl;
return -1;
}
ifstream file(argv[1]);
if (!file.good()) {
cerr << "Bad input" << endl;
return -1;
}
int row, col;
file >> col >> row;
int** A = new int*[row];
A[0] = new int[row*col];
for (int i = 1; i < row; i++) A[i] = A[i-1] + col;
// Fill in Host Array A
for (int i = 0; i < row; i++) {
for (int j = 0; j < col; j++) {
int element;
file >> element;
A[i][j] = element;
}
}
file.close();
int* count = new int;
*count = 0;
// Copy memory to device array deviceA
int* deviceA;
int bytes = row * col * sizeof(int);
hipMalloc(&deviceA, bytes);
hipMemcpy(deviceA, A[0], bytes, hipMemcpyHostToDevice);
// Copy deviceCount
int* deviceCount;
hipMalloc(&deviceCount, 4);
hipMemcpy(deviceCount, count, 4, hipMemcpyHostToDevice);
dim3 threadsPerBlock(8, 8, 1);
dim3 numBlocks((col + threadsPerBlock.x-1) / threadsPerBlock.x,
(row + threadsPerBlock.y-1) / threadsPerBlock.y, 1);
// Launch the program
countOnes<<<numBlocks, threadsPerBlock>>>(deviceA, deviceCount, row, col);
//cudaDeviceSynchronize();
// Copy back from device the deviceCount
hipMemcpy(count, deviceCount, 4, hipMemcpyDeviceToHost);
cout << *count << endl;
delete A[0];
delete A;
hipFree(deviceA);
hipFree(deviceCount);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* CSCI 563 Programming Assignment 2
Clayton Kramp
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
using namespace std;
// Main Device Function to be used to count number of ones
__global__ void countOnes(int* A, int* count, int row, int col) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= row || j >= col) return;
if (A[i * col + j] == 1) {
// Atomic addition for race conditions
atomicAdd(count, 1);
}
}
int main(int argc, char* argv[]) {
if (argc != 2) {
cerr << "Arguments error" << endl;
return -1;
}
ifstream file(argv[1]);
if (!file.good()) {
cerr << "Bad input" << endl;
return -1;
}
int row, col;
file >> col >> row;
int** A = new int*[row];
A[0] = new int[row*col];
for (int i = 1; i < row; i++) A[i] = A[i-1] + col;
// Fill in Host Array A
for (int i = 0; i < row; i++) {
for (int j = 0; j < col; j++) {
int element;
file >> element;
A[i][j] = element;
}
}
file.close();
int* count = new int;
*count = 0;
// Copy memory to device array deviceA
int* deviceA;
int bytes = row * col * sizeof(int);
hipMalloc(&deviceA, bytes);
hipMemcpy(deviceA, A[0], bytes, hipMemcpyHostToDevice);
// Copy deviceCount
int* deviceCount;
hipMalloc(&deviceCount, 4);
hipMemcpy(deviceCount, count, 4, hipMemcpyHostToDevice);
dim3 threadsPerBlock(8, 8, 1);
dim3 numBlocks((col + threadsPerBlock.x-1) / threadsPerBlock.x,
(row + threadsPerBlock.y-1) / threadsPerBlock.y, 1);
// Launch the program
countOnes<<<numBlocks, threadsPerBlock>>>(deviceA, deviceCount, row, col);
//cudaDeviceSynchronize();
// Copy back from device the deviceCount
hipMemcpy(count, deviceCount, 4, hipMemcpyDeviceToHost);
cout << *count << endl;
delete A[0];
delete A;
hipFree(deviceA);
hipFree(deviceCount);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9countOnesPiS_ii
.globl _Z9countOnesPiS_ii
.p2align 8
.type _Z9countOnesPiS_ii,@function
_Z9countOnesPiS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_4
s_load_b64 s[4:5], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x8
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9countOnesPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9countOnesPiS_ii, .Lfunc_end0-_Z9countOnesPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9countOnesPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9countOnesPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* CSCI 563 Programming Assignment 2
Clayton Kramp
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
using namespace std;
// Main Device Function to be used to count number of ones
__global__ void countOnes(int* A, int* count, int row, int col) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
if (i >= row || j >= col) return;
if (A[i * col + j] == 1) {
// Atomic addition for race conditions
atomicAdd(count, 1);
}
}
int main(int argc, char* argv[]) {
if (argc != 2) {
cerr << "Arguments error" << endl;
return -1;
}
ifstream file(argv[1]);
if (!file.good()) {
cerr << "Bad input" << endl;
return -1;
}
int row, col;
file >> col >> row;
int** A = new int*[row];
A[0] = new int[row*col];
for (int i = 1; i < row; i++) A[i] = A[i-1] + col;
// Fill in Host Array A
for (int i = 0; i < row; i++) {
for (int j = 0; j < col; j++) {
int element;
file >> element;
A[i][j] = element;
}
}
file.close();
int* count = new int;
*count = 0;
// Copy memory to device array deviceA
int* deviceA;
int bytes = row * col * sizeof(int);
hipMalloc(&deviceA, bytes);
hipMemcpy(deviceA, A[0], bytes, hipMemcpyHostToDevice);
// Copy deviceCount
int* deviceCount;
hipMalloc(&deviceCount, 4);
hipMemcpy(deviceCount, count, 4, hipMemcpyHostToDevice);
dim3 threadsPerBlock(8, 8, 1);
dim3 numBlocks((col + threadsPerBlock.x-1) / threadsPerBlock.x,
(row + threadsPerBlock.y-1) / threadsPerBlock.y, 1);
// Launch the program
countOnes<<<numBlocks, threadsPerBlock>>>(deviceA, deviceCount, row, col);
//cudaDeviceSynchronize();
// Copy back from device the deviceCount
hipMemcpy(count, deviceCount, 4, hipMemcpyDeviceToHost);
cout << *count << endl;
delete A[0];
delete A;
hipFree(deviceA);
hipFree(deviceCount);
return 0;
} | .text
.file "Homework2_1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__countOnesPiS_ii # -- Begin function _Z24__device_stub__countOnesPiS_ii
.p2align 4, 0x90
.type _Z24__device_stub__countOnesPiS_ii,@function
_Z24__device_stub__countOnesPiS_ii: # @_Z24__device_stub__countOnesPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9countOnesPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__countOnesPiS_ii, .Lfunc_end0-_Z24__device_stub__countOnesPiS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $656, %rsp # imm = 0x290
.cfi_def_cfa_offset 704
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $2, %edi
jne .LBB1_1
# %bb.7:
movq 8(%rsi), %rsi
.cfi_escape 0x2e, 0x00
leaq 136(%rsp), %rdi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
movq 136(%rsp), %rax
movq -24(%rax), %rax
cmpl $0, 168(%rsp,%rax)
je .LBB1_18
# %bb.8:
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp1:
# %bb.9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_10
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i62
cmpb $0, 56(%rbx)
je .LBB1_14
# %bb.13:
movzbl 67(%rbx), %eax
jmp .LBB1_16
.LBB1_1:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_69
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB1_5
.LBB1_18:
.Ltmp13:
.cfi_escape 0x2e, 0x00
leaq 136(%rsp), %rdi
movq %rsp, %rsi
callq _ZNSirsERi
.Ltmp14:
# %bb.19:
.Ltmp15:
.cfi_escape 0x2e, 0x00
leaq 4(%rsp), %rsi
movq %rax, %rdi
callq _ZNSirsERi
.Ltmp16:
# %bb.20:
movslq 4(%rsp), %r14
leaq (,%r14,8), %rdi
testq %r14, %r14
movq $-1, %r12
cmovsq %r12, %rdi
.Ltmp18:
.cfi_escape 0x2e, 0x00
callq _Znam
.Ltmp19:
# %bb.21:
movq %rax, %rbx
movl %r14d, %r14d
movslq (%rsp), %r15
movslq %r14d, %rax
imulq %r15, %rax
movq %rax, %rdi
shlq $2, %rdi
testl %eax, %eax
cmovsq %r12, %rdi
.Ltmp20:
.cfi_escape 0x2e, 0x00
callq _Znam
.Ltmp21:
# %bb.22:
movq %rax, (%rbx)
cmpl $2, %r14d
jl .LBB1_25
# %bb.23: # %.lr.ph
shlq $2, %r15
movq (%rbx), %rax
addq %r15, %rax
movl $1, %ecx
.p2align 4, 0x90
.LBB1_24: # =>This Inner Loop Header: Depth=1
movq %rax, (%rbx,%rcx,8)
incq %rcx
addq %r15, %rax
cmpq %rcx, %r14
jne .LBB1_24
.LBB1_25: # %.preheader84
cmpl $0, 4(%rsp)
jle .LBB1_32
# %bb.26: # %.preheader.preheader
xorl %r12d, %r12d
leaq 136(%rsp), %r14
leaq 96(%rsp), %r15
jmp .LBB1_27
.p2align 4, 0x90
.LBB1_31: # %._crit_edge
# in Loop: Header=BB1_27 Depth=1
incq %r12
movslq 4(%rsp), %rax
cmpq %rax, %r12
jge .LBB1_32
.LBB1_27: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_29 Depth 2
cmpl $0, (%rsp)
jle .LBB1_31
# %bb.28: # %.lr.ph87
# in Loop: Header=BB1_27 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_29: # Parent Loop BB1_27 Depth=1
# => This Inner Loop Header: Depth=2
.Ltmp22:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movq %r15, %rsi
callq _ZNSirsERi
.Ltmp23:
# %bb.30: # in Loop: Header=BB1_29 Depth=2
movl 96(%rsp), %eax
movq (%rbx,%r12,8), %rcx
movl %eax, (%rcx,%r13,4)
incq %r13
movslq (%rsp), %rax
cmpq %rax, %r13
jl .LBB1_29
jmp .LBB1_31
.LBB1_4:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movl $-1, %ebx
jmp .LBB1_6
.LBB1_32: # %._crit_edge89
leaq 152(%rsp), %rdi
.Ltmp25:
.cfi_escape 0x2e, 0x00
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp26:
# %bb.33: # %.noexc
testq %rax, %rax
jne .LBB1_35
# %bb.34:
movq 136(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $136, %rdi
movl 168(%rsp,%rax), %esi
orl $4, %esi
.Ltmp27:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp28:
.LBB1_35: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
.Ltmp30:
.cfi_escape 0x2e, 0x00
movl $4, %edi
callq _Znwm
.Ltmp31:
# %bb.36:
movq %rax, %r14
movl $0, (%rax)
movl 4(%rsp), %eax
imull (%rsp), %eax
shll $2, %eax
movslq %eax, %r15
.Ltmp33:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
.Ltmp34:
# %bb.37: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
movq 16(%rsp), %rdi
movq (%rbx), %rsi
.Ltmp35:
.cfi_escape 0x2e, 0x00
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp36:
# %bb.38:
.Ltmp38:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
.Ltmp39:
# %bb.39: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit56
movq 8(%rsp), %rdi
.Ltmp40:
.cfi_escape 0x2e, 0x00
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp41:
# %bb.40:
movl (%rsp), %eax
addl $7, %eax
shrl $3, %eax
movl 4(%rsp), %edi
addl $7, %edi
shrl $3, %edi
shlq $32, %rdi
orq %rax, %rdi
.Ltmp43:
.cfi_escape 0x2e, 0x00
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp44:
# %bb.41:
testl %eax, %eax
jne .LBB1_44
# %bb.42:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl 4(%rsp), %edx
movl (%rsp), %esi
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 28(%rsp)
movl %esi, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
.Ltmp45:
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp46:
# %bb.43: # %.noexc57
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
.Ltmp47:
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z9countOnesPiS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp48:
.LBB1_44:
movq 8(%rsp), %rsi
.Ltmp49:
.cfi_escape 0x2e, 0x00
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp50:
# %bb.45:
movl (%r14), %esi
.Ltmp51:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp52:
# %bb.46:
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_47
# %bb.55: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i72
cmpb $0, 56(%r15)
je .LBB1_57
# %bb.56:
movzbl 67(%r15), %eax
jmp .LBB1_59
.LBB1_14:
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp3:
# %bb.15: # %.noexc66
movq (%rbx), %rax
.Ltmp4:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp5:
.LBB1_16: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp6:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
.Ltmp7:
# %bb.17: # %.noexc68
movl $-1, %ebx
.Ltmp8:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp9:
jmp .LBB1_66
.LBB1_57:
.Ltmp53:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp54:
# %bb.58: # %.noexc77
movq (%r15), %rax
.Ltmp55:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp56:
.LBB1_59: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i74
.Ltmp57:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp58:
# %bb.60: # %.noexc79
.Ltmp59:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp60:
# %bb.61: # %_ZNSolsEPFRSoS_E.exit60
movq (%rbx), %rdi
testq %rdi, %rdi
je .LBB1_63
# %bb.62:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_63:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
movq 16(%rsp), %rdi
.Ltmp61:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp62:
# %bb.64:
movq 8(%rsp), %rdi
.Ltmp63:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp64:
# %bb.65:
xorl %ebx, %ebx
.LBB1_66: # %_ZNSolsEPFRSoS_E.exit
.cfi_escape 0x2e, 0x00
leaq 136(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 392(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.LBB1_6:
movl %ebx, %eax
addq $656, %rsp # imm = 0x290
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_69:
.cfi_def_cfa_offset 704
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_10:
.Ltmp10:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp11:
# %bb.11: # %.noexc65
.LBB1_47:
.Ltmp65:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp66:
# %bb.54: # %.noexc76
.LBB1_50:
.Ltmp32:
jmp .LBB1_68
.LBB1_52:
.Ltmp42:
jmp .LBB1_68
.LBB1_51:
.Ltmp37:
jmp .LBB1_68
.LBB1_48:
.Ltmp17:
jmp .LBB1_68
.LBB1_49:
.Ltmp29:
jmp .LBB1_68
.LBB1_67:
.Ltmp12:
jmp .LBB1_68
.LBB1_53:
.Ltmp67:
jmp .LBB1_68
.LBB1_70:
.Ltmp24:
.LBB1_68:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 136(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 392(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp13-.Ltmp1 # Call between .Ltmp1 and .Ltmp13
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp16-.Ltmp13 # Call between .Ltmp13 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp21-.Ltmp18 # Call between .Ltmp18 and .Ltmp21
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp23-.Ltmp22 # Call between .Ltmp22 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp25-.Ltmp23 # Call between .Ltmp23 and .Ltmp25
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp28-.Ltmp25 # Call between .Ltmp25 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp31-.Ltmp30 # Call between .Ltmp30 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp36-.Ltmp33 # Call between .Ltmp33 and .Ltmp36
.uleb128 .Ltmp37-.Lfunc_begin0 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp41-.Ltmp38 # Call between .Ltmp38 and .Ltmp41
.uleb128 .Ltmp42-.Lfunc_begin0 # jumps to .Ltmp42
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp52-.Ltmp43 # Call between .Ltmp43 and .Ltmp52
.uleb128 .Ltmp67-.Lfunc_begin0 # jumps to .Ltmp67
.byte 0 # On action: cleanup
.uleb128 .Ltmp2-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp9-.Ltmp2 # Call between .Ltmp2 and .Ltmp9
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp53-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp64-.Ltmp53 # Call between .Ltmp53 and .Ltmp64
.uleb128 .Ltmp67-.Lfunc_begin0 # jumps to .Ltmp67
.byte 0 # On action: cleanup
.uleb128 .Ltmp64-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp10-.Ltmp64 # Call between .Ltmp64 and .Ltmp10
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp65-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp66-.Ltmp65 # Call between .Ltmp65 and .Ltmp66
.uleb128 .Ltmp67-.Lfunc_begin0 # jumps to .Ltmp67
.byte 0 # On action: cleanup
.uleb128 .Ltmp66-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Lfunc_end1-.Ltmp66 # Call between .Ltmp66 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9countOnesPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9countOnesPiS_ii,@object # @_Z9countOnesPiS_ii
.section .rodata,"a",@progbits
.globl _Z9countOnesPiS_ii
.p2align 3, 0x0
_Z9countOnesPiS_ii:
.quad _Z24__device_stub__countOnesPiS_ii
.size _Z9countOnesPiS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Arguments error"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Bad input"
.size .L.str.1, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9countOnesPiS_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__countOnesPiS_ii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z9countOnesPiS_ii
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9countOnesPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R3, c[0x0][0x174], R0 ; /* 0x00005d0003037a24 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0202 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0120*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0130*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0140*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0150*/ POPC R5, UR6 ; /* 0x0000000600057d09 */
/* 0x000e620008000000 */
/*0160*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fc80000000f00 */
/*0170*/ ISETP.EQ.U32.AND P0, PT, R0, UR7, PT ; /* 0x0000000700007c0c */
/* 0x001fda000bf02070 */
/*0180*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x002fe2000c10e184 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9countOnesPiS_ii
.globl _Z9countOnesPiS_ii
.p2align 8
.type _Z9countOnesPiS_ii,@function
_Z9countOnesPiS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_4
s_load_b64 s[4:5], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x8
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9countOnesPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9countOnesPiS_ii, .Lfunc_end0-_Z9countOnesPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9countOnesPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9countOnesPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000556f3_00000000-6_Homework2_1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9countOnesPiS_iiPiS_ii
.type _Z32__device_stub__Z9countOnesPiS_iiPiS_ii, @function
_Z32__device_stub__Z9countOnesPiS_iiPiS_ii:
.LFB3825:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9countOnesPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3825:
.size _Z32__device_stub__Z9countOnesPiS_iiPiS_ii, .-_Z32__device_stub__Z9countOnesPiS_iiPiS_ii
.globl _Z9countOnesPiS_ii
.type _Z9countOnesPiS_ii, @function
_Z9countOnesPiS_ii:
.LFB3826:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9countOnesPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3826:
.size _Z9countOnesPiS_ii, .-_Z9countOnesPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9countOnesPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3828:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9countOnesPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3828:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC1:
.string "Arguments error"
.LC2:
.string "Bad input"
.text
.globl main
.type main, @function
main:
.LFB3800:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3800
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $584, %rsp
.cfi_def_cfa_offset 640
movq %fs:40, %rax
movq %rax, 568(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L46
movq 8(%rsi), %rsi
leaq 48(%rsp), %rdi
movl $8, %edx
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
movl 336(%rsp), %r15d
testl %r15d, %r15d
jne .L47
leaq 4(%rsp), %rsi
leaq 48(%rsp), %rdi
.LEHB1:
call _ZNSirsERi@PLT
.LEHE1:
jmp .L48
.L46:
leaq .LC1(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
.LEHB2:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE2:
movl $-1, %r15d
jmp .L13
.L47:
leaq .LC2(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
.LEHB3:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L49
.L48:
movq %rax, %rdi
movq %rsp, %rsi
call _ZNSirsERi@PLT
movslq (%rsp), %rax
movabsq $1152921504606846975, %rdx
cmpq %rax, %rdx
jb .L18
leaq 0(,%rax,8), %rdi
call _Znam@PLT
movq %rax, %r14
movl (%rsp), %eax
imull 4(%rsp), %eax
cltq
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L50
leaq 0(,%rax,4), %rdi
call _Znam@PLT
jmp .L51
.L18:
movq 568(%rsp), %rax
subq %fs:40, %rax
je .L20
call __stack_chk_fail@PLT
.L20:
call __cxa_throw_bad_array_new_length@PLT
.L38:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 568(%rsp), %rax
subq %fs:40, %rax
je .L34
call __stack_chk_fail@PLT
.L51:
movq %rax, (%r14)
movl (%rsp), %edx
cmpl $1, %edx
jle .L52
movslq 4(%rsp), %rcx
salq $2, %rcx
movq %r14, %rax
leal -1(%rdx), %edx
leaq (%r14,%rdx,8), %rsi
.L25:
movq %rcx, %rdx
addq (%rax), %rdx
movq %rdx, 8(%rax)
addq $8, %rax
cmpq %rsi, %rax
jne .L25
.L26:
movq %r14, %rbp
movl %r15d, %r13d
leaq 36(%rsp), %r12
jmp .L28
.L50:
movq 568(%rsp), %rax
subq %fs:40, %rax
je .L23
call __stack_chk_fail@PLT
.L23:
call __cxa_throw_bad_array_new_length@PLT
.L52:
testl %edx, %edx
jg .L26
.L27:
leaq 48(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
jmp .L53
.L54:
movq 0(%rbp), %rax
movl 36(%rsp), %edx
movl %edx, (%rax,%rbx,4)
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jle .L30
.L29:
leaq 48(%rsp), %rdi
movq %r12, %rsi
call _ZNSirsERi@PLT
jmp .L54
.L30:
addl $1, %r13d
addq $8, %rbp
cmpl %r13d, (%rsp)
jle .L27
.L28:
movl $0, %ebx
cmpl $0, 4(%rsp)
jg .L29
jmp .L30
.L53:
movl $4, %edi
call _Znwm@PLT
movq %rax, %rbp
movl $0, (%rax)
movl (%rsp), %ebx
imull 4(%rsp), %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq (%r14), %r12
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl (%rsp), %eax
addl $7, %eax
shrl $3, %eax
movl 4(%rsp), %ecx
leal 7(%rcx), %edx
shrl $3, %edx
movl %edx, 36(%rsp)
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $8, 24(%rsp)
movl $8, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L31
movl 4(%rsp), %ecx
movl (%rsp), %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z9countOnesPiS_iiPiS_ii
.L31:
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl 0(%rbp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
testq %r12, %r12
je .L32
movl $4, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
.L32:
movl $8, %esi
movq %r14, %rdi
call _ZdlPvm@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
.LEHE3:
jmp .L17
.L49:
movl $-1, %r15d
.L17:
leaq 48(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L13:
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl %r15d, %eax
addq $584, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3800:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3800-.LLSDACSB3800
.LLSDACSB3800:
.uleb128 .LEHB0-.LFB3800
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3800
.uleb128 .LEHE1-.LEHB1
.uleb128 .L38-.LFB3800
.uleb128 0
.uleb128 .LEHB2-.LFB3800
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3800
.uleb128 .LEHE3-.LEHB3
.uleb128 .L38-.LFB3800
.uleb128 0
.uleb128 .LEHB4-.LFB3800
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE3800:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Homework2_1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__countOnesPiS_ii # -- Begin function _Z24__device_stub__countOnesPiS_ii
.p2align 4, 0x90
.type _Z24__device_stub__countOnesPiS_ii,@function
_Z24__device_stub__countOnesPiS_ii: # @_Z24__device_stub__countOnesPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9countOnesPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__countOnesPiS_ii, .Lfunc_end0-_Z24__device_stub__countOnesPiS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $656, %rsp # imm = 0x290
.cfi_def_cfa_offset 704
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $2, %edi
jne .LBB1_1
# %bb.7:
movq 8(%rsi), %rsi
.cfi_escape 0x2e, 0x00
leaq 136(%rsp), %rdi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
movq 136(%rsp), %rax
movq -24(%rax), %rax
cmpl $0, 168(%rsp,%rax)
je .LBB1_18
# %bb.8:
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp1:
# %bb.9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_10
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i62
cmpb $0, 56(%rbx)
je .LBB1_14
# %bb.13:
movzbl 67(%rbx), %eax
jmp .LBB1_16
.LBB1_1:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_69
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB1_5
.LBB1_18:
.Ltmp13:
.cfi_escape 0x2e, 0x00
leaq 136(%rsp), %rdi
movq %rsp, %rsi
callq _ZNSirsERi
.Ltmp14:
# %bb.19:
.Ltmp15:
.cfi_escape 0x2e, 0x00
leaq 4(%rsp), %rsi
movq %rax, %rdi
callq _ZNSirsERi
.Ltmp16:
# %bb.20:
movslq 4(%rsp), %r14
leaq (,%r14,8), %rdi
testq %r14, %r14
movq $-1, %r12
cmovsq %r12, %rdi
.Ltmp18:
.cfi_escape 0x2e, 0x00
callq _Znam
.Ltmp19:
# %bb.21:
movq %rax, %rbx
movl %r14d, %r14d
movslq (%rsp), %r15
movslq %r14d, %rax
imulq %r15, %rax
movq %rax, %rdi
shlq $2, %rdi
testl %eax, %eax
cmovsq %r12, %rdi
.Ltmp20:
.cfi_escape 0x2e, 0x00
callq _Znam
.Ltmp21:
# %bb.22:
movq %rax, (%rbx)
cmpl $2, %r14d
jl .LBB1_25
# %bb.23: # %.lr.ph
shlq $2, %r15
movq (%rbx), %rax
addq %r15, %rax
movl $1, %ecx
.p2align 4, 0x90
.LBB1_24: # =>This Inner Loop Header: Depth=1
movq %rax, (%rbx,%rcx,8)
incq %rcx
addq %r15, %rax
cmpq %rcx, %r14
jne .LBB1_24
.LBB1_25: # %.preheader84
cmpl $0, 4(%rsp)
jle .LBB1_32
# %bb.26: # %.preheader.preheader
xorl %r12d, %r12d
leaq 136(%rsp), %r14
leaq 96(%rsp), %r15
jmp .LBB1_27
.p2align 4, 0x90
.LBB1_31: # %._crit_edge
# in Loop: Header=BB1_27 Depth=1
incq %r12
movslq 4(%rsp), %rax
cmpq %rax, %r12
jge .LBB1_32
.LBB1_27: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_29 Depth 2
cmpl $0, (%rsp)
jle .LBB1_31
# %bb.28: # %.lr.ph87
# in Loop: Header=BB1_27 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_29: # Parent Loop BB1_27 Depth=1
# => This Inner Loop Header: Depth=2
.Ltmp22:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movq %r15, %rsi
callq _ZNSirsERi
.Ltmp23:
# %bb.30: # in Loop: Header=BB1_29 Depth=2
movl 96(%rsp), %eax
movq (%rbx,%r12,8), %rcx
movl %eax, (%rcx,%r13,4)
incq %r13
movslq (%rsp), %rax
cmpq %rax, %r13
jl .LBB1_29
jmp .LBB1_31
.LBB1_4:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movl $-1, %ebx
jmp .LBB1_6
.LBB1_32: # %._crit_edge89
leaq 152(%rsp), %rdi
.Ltmp25:
.cfi_escape 0x2e, 0x00
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp26:
# %bb.33: # %.noexc
testq %rax, %rax
jne .LBB1_35
# %bb.34:
movq 136(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $136, %rdi
movl 168(%rsp,%rax), %esi
orl $4, %esi
.Ltmp27:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp28:
.LBB1_35: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
.Ltmp30:
.cfi_escape 0x2e, 0x00
movl $4, %edi
callq _Znwm
.Ltmp31:
# %bb.36:
movq %rax, %r14
movl $0, (%rax)
movl 4(%rsp), %eax
imull (%rsp), %eax
shll $2, %eax
movslq %eax, %r15
.Ltmp33:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
.Ltmp34:
# %bb.37: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
movq 16(%rsp), %rdi
movq (%rbx), %rsi
.Ltmp35:
.cfi_escape 0x2e, 0x00
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp36:
# %bb.38:
.Ltmp38:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
.Ltmp39:
# %bb.39: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit56
movq 8(%rsp), %rdi
.Ltmp40:
.cfi_escape 0x2e, 0x00
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp41:
# %bb.40:
movl (%rsp), %eax
addl $7, %eax
shrl $3, %eax
movl 4(%rsp), %edi
addl $7, %edi
shrl $3, %edi
shlq $32, %rdi
orq %rax, %rdi
.Ltmp43:
.cfi_escape 0x2e, 0x00
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp44:
# %bb.41:
testl %eax, %eax
jne .LBB1_44
# %bb.42:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl 4(%rsp), %edx
movl (%rsp), %esi
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 28(%rsp)
movl %esi, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
.Ltmp45:
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp46:
# %bb.43: # %.noexc57
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
.Ltmp47:
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z9countOnesPiS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp48:
.LBB1_44:
movq 8(%rsp), %rsi
.Ltmp49:
.cfi_escape 0x2e, 0x00
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp50:
# %bb.45:
movl (%r14), %esi
.Ltmp51:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp52:
# %bb.46:
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_47
# %bb.55: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i72
cmpb $0, 56(%r15)
je .LBB1_57
# %bb.56:
movzbl 67(%r15), %eax
jmp .LBB1_59
.LBB1_14:
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp3:
# %bb.15: # %.noexc66
movq (%rbx), %rax
.Ltmp4:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp5:
.LBB1_16: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp6:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
.Ltmp7:
# %bb.17: # %.noexc68
movl $-1, %ebx
.Ltmp8:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp9:
jmp .LBB1_66
.LBB1_57:
.Ltmp53:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp54:
# %bb.58: # %.noexc77
movq (%r15), %rax
.Ltmp55:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp56:
.LBB1_59: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i74
.Ltmp57:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp58:
# %bb.60: # %.noexc79
.Ltmp59:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp60:
# %bb.61: # %_ZNSolsEPFRSoS_E.exit60
movq (%rbx), %rdi
testq %rdi, %rdi
je .LBB1_63
# %bb.62:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_63:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
movq 16(%rsp), %rdi
.Ltmp61:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp62:
# %bb.64:
movq 8(%rsp), %rdi
.Ltmp63:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp64:
# %bb.65:
xorl %ebx, %ebx
.LBB1_66: # %_ZNSolsEPFRSoS_E.exit
.cfi_escape 0x2e, 0x00
leaq 136(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 392(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.LBB1_6:
movl %ebx, %eax
addq $656, %rsp # imm = 0x290
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_69:
.cfi_def_cfa_offset 704
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_10:
.Ltmp10:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp11:
# %bb.11: # %.noexc65
.LBB1_47:
.Ltmp65:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp66:
# %bb.54: # %.noexc76
.LBB1_50:
.Ltmp32:
jmp .LBB1_68
.LBB1_52:
.Ltmp42:
jmp .LBB1_68
.LBB1_51:
.Ltmp37:
jmp .LBB1_68
.LBB1_48:
.Ltmp17:
jmp .LBB1_68
.LBB1_49:
.Ltmp29:
jmp .LBB1_68
.LBB1_67:
.Ltmp12:
jmp .LBB1_68
.LBB1_53:
.Ltmp67:
jmp .LBB1_68
.LBB1_70:
.Ltmp24:
.LBB1_68:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 136(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 392(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp13-.Ltmp1 # Call between .Ltmp1 and .Ltmp13
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp16-.Ltmp13 # Call between .Ltmp13 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp21-.Ltmp18 # Call between .Ltmp18 and .Ltmp21
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp23-.Ltmp22 # Call between .Ltmp22 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp25-.Ltmp23 # Call between .Ltmp23 and .Ltmp25
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp28-.Ltmp25 # Call between .Ltmp25 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp31-.Ltmp30 # Call between .Ltmp30 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp36-.Ltmp33 # Call between .Ltmp33 and .Ltmp36
.uleb128 .Ltmp37-.Lfunc_begin0 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp41-.Ltmp38 # Call between .Ltmp38 and .Ltmp41
.uleb128 .Ltmp42-.Lfunc_begin0 # jumps to .Ltmp42
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp52-.Ltmp43 # Call between .Ltmp43 and .Ltmp52
.uleb128 .Ltmp67-.Lfunc_begin0 # jumps to .Ltmp67
.byte 0 # On action: cleanup
.uleb128 .Ltmp2-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp9-.Ltmp2 # Call between .Ltmp2 and .Ltmp9
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp53-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp64-.Ltmp53 # Call between .Ltmp53 and .Ltmp64
.uleb128 .Ltmp67-.Lfunc_begin0 # jumps to .Ltmp67
.byte 0 # On action: cleanup
.uleb128 .Ltmp64-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp10-.Ltmp64 # Call between .Ltmp64 and .Ltmp10
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp65-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp66-.Ltmp65 # Call between .Ltmp65 and .Ltmp66
.uleb128 .Ltmp67-.Lfunc_begin0 # jumps to .Ltmp67
.byte 0 # On action: cleanup
.uleb128 .Ltmp66-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Lfunc_end1-.Ltmp66 # Call between .Ltmp66 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9countOnesPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9countOnesPiS_ii,@object # @_Z9countOnesPiS_ii
.section .rodata,"a",@progbits
.globl _Z9countOnesPiS_ii
.p2align 3, 0x0
_Z9countOnesPiS_ii:
.quad _Z24__device_stub__countOnesPiS_ii
.size _Z9countOnesPiS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Arguments error"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Bad input"
.size .L.str.1, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9countOnesPiS_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__countOnesPiS_ii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z9countOnesPiS_ii
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
//*************inclución de librerias***************
//************variables globales***************
int N=93, dimx=1920, dimy=2560, tam_imag=1920*2560;
//**********KERNEL**************
float *leerMatrizVarianza(int d);
//*****************función main**********************
__global__ void kernel (float *max, float *var, int *top, int k){
int idx=threadIdx.x + blockIdx.x*blockDim.x;
int tam_imag=1920*2560;
if(idx<tam_imag){
if(var[idx]>max[idx]){
top[idx]=k;
max[idx]=var[idx];
}
}
} | code for sm_80
Function : _Z6kernelPfS_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x4affff, PT ; /* 0x004affff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe200078e0205 */
/*00a0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FSETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720b */
/* 0x004fda0003f04000 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fe20000011400 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff097624 */
/* 0x000fe200078e00ff */
/*0100*/ LEA R6, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000067a11 */
/* 0x000fc800078010ff */
/*0110*/ LEA.HI.X R7, R0, c[0x0][0x174], R7, 0x2, P0 ; /* 0x00005d0000077a11 */
/* 0x000fca00000f1407 */
/*0120*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe8000c101904 */
/*0130*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0140*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
//*************inclución de librerias***************
//************variables globales***************
int N=93, dimx=1920, dimy=2560, tam_imag=1920*2560;
//**********KERNEL**************
float *leerMatrizVarianza(int d);
//*****************función main**********************
__global__ void kernel (float *max, float *var, int *top, int k){
int idx=threadIdx.x + blockIdx.x*blockDim.x;
int tam_imag=1920*2560;
if(idx<tam_imag){
if(var[idx]>max[idx]){
top[idx]=k;
max[idx]=var[idx];
}
}
} | .file "tmpxft_000b82d0_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6kernelPfS_PiiPfS_Pii
.type _Z30__device_stub__Z6kernelPfS_PiiPfS_Pii, @function
_Z30__device_stub__Z6kernelPfS_PiiPfS_Pii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPfS_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6kernelPfS_PiiPfS_Pii, .-_Z30__device_stub__Z6kernelPfS_PiiPfS_Pii
.globl _Z6kernelPfS_Pii
.type _Z6kernelPfS_Pii, @function
_Z6kernelPfS_Pii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6kernelPfS_PiiPfS_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPfS_Pii, .-_Z6kernelPfS_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPfS_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl tam_imag
.data
.align 4
.type tam_imag, @object
.size tam_imag, 4
tam_imag:
.long 4915200
.globl dimy
.align 4
.type dimy, @object
.size dimy, 4
dimy:
.long 2560
.globl dimx
.align 4
.type dimx, @object
.size dimx, 4
dimx:
.long 1920
.globl N
.align 4
.type N, @object
.size N, 4
N:
.long 93
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
//*************inclución de librerias***************
//************variables globales***************
int N=93, dimx=1920, dimy=2560, tam_imag=1920*2560;
//**********KERNEL**************
float *leerMatrizVarianza(int d);
//*****************función main**********************
__global__ void kernel (float *max, float *var, int *top, int k){
int idx=threadIdx.x + blockIdx.x*blockDim.x;
int tam_imag=1920*2560;
if(idx<tam_imag){
if(var[idx]>max[idx]){
top[idx]=k;
max[idx]=var[idx];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
//*************inclución de librerias***************
//************variables globales***************
int N=93, dimx=1920, dimy=2560, tam_imag=1920*2560;
//**********KERNEL**************
float *leerMatrizVarianza(int d);
//*****************función main**********************
__global__ void kernel (float *max, float *var, int *top, int k){
int idx=threadIdx.x + blockIdx.x*blockDim.x;
int tam_imag=1920*2560;
if(idx<tam_imag){
if(var[idx]>max[idx]){
top[idx]=k;
max[idx]=var[idx];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//*************inclución de librerias***************
//************variables globales***************
int N=93, dimx=1920, dimy=2560, tam_imag=1920*2560;
//**********KERNEL**************
float *leerMatrizVarianza(int d);
//*****************función main**********************
__global__ void kernel (float *max, float *var, int *top, int k){
int idx=threadIdx.x + blockIdx.x*blockDim.x;
int tam_imag=1920*2560;
if(idx<tam_imag){
if(var[idx]>max[idx]){
top[idx]=k;
max[idx]=var[idx];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfS_Pii
.globl _Z6kernelPfS_Pii
.p2align 8
.type _Z6kernelPfS_Pii,@function
_Z6kernelPfS_Pii:
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x4b0000, v1
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v4, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v5, s0
global_store_b32 v[0:1], v5, off
global_store_b32 v[2:3], v4, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfS_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfS_Pii, .Lfunc_end0-_Z6kernelPfS_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfS_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfS_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//*************inclución de librerias***************
//************variables globales***************
int N=93, dimx=1920, dimy=2560, tam_imag=1920*2560;
//**********KERNEL**************
float *leerMatrizVarianza(int d);
//*****************función main**********************
__global__ void kernel (float *max, float *var, int *top, int k){
int idx=threadIdx.x + blockIdx.x*blockDim.x;
int tam_imag=1920*2560;
if(idx<tam_imag){
if(var[idx]>max[idx]){
top[idx]=k;
max[idx]=var[idx];
}
}
} | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPfS_Pii # -- Begin function _Z21__device_stub__kernelPfS_Pii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_Pii,@function
_Z21__device_stub__kernelPfS_Pii: # @_Z21__device_stub__kernelPfS_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPfS_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_Pii, .Lfunc_end0-_Z21__device_stub__kernelPfS_Pii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type N,@object # @N
.data
.globl N
.p2align 2, 0x0
N:
.long 93 # 0x5d
.size N, 4
.type dimx,@object # @dimx
.globl dimx
.p2align 2, 0x0
dimx:
.long 1920 # 0x780
.size dimx, 4
.type dimy,@object # @dimy
.globl dimy
.p2align 2, 0x0
dimy:
.long 2560 # 0xa00
.size dimy, 4
.type tam_imag,@object # @tam_imag
.globl tam_imag
.p2align 2, 0x0
tam_imag:
.long 4915200 # 0x4b0000
.size tam_imag, 4
.type _Z6kernelPfS_Pii,@object # @_Z6kernelPfS_Pii
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_Pii
.p2align 3, 0x0
_Z6kernelPfS_Pii:
.quad _Z21__device_stub__kernelPfS_Pii
.size _Z6kernelPfS_Pii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPfS_Pii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfS_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPfS_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x4affff, PT ; /* 0x004affff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe200078e0205 */
/*00a0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FSETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720b */
/* 0x004fda0003f04000 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fe20000011400 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff097624 */
/* 0x000fe200078e00ff */
/*0100*/ LEA R6, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000067a11 */
/* 0x000fc800078010ff */
/*0110*/ LEA.HI.X R7, R0, c[0x0][0x174], R7, 0x2, P0 ; /* 0x00005d0000077a11 */
/* 0x000fca00000f1407 */
/*0120*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe8000c101904 */
/*0130*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0140*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfS_Pii
.globl _Z6kernelPfS_Pii
.p2align 8
.type _Z6kernelPfS_Pii,@function
_Z6kernelPfS_Pii:
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x4b0000, v1
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v4, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v5, s0
global_store_b32 v[0:1], v5, off
global_store_b32 v[2:3], v4, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfS_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfS_Pii, .Lfunc_end0-_Z6kernelPfS_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfS_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfS_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b82d0_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6kernelPfS_PiiPfS_Pii
.type _Z30__device_stub__Z6kernelPfS_PiiPfS_Pii, @function
_Z30__device_stub__Z6kernelPfS_PiiPfS_Pii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPfS_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6kernelPfS_PiiPfS_Pii, .-_Z30__device_stub__Z6kernelPfS_PiiPfS_Pii
.globl _Z6kernelPfS_Pii
.type _Z6kernelPfS_Pii, @function
_Z6kernelPfS_Pii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6kernelPfS_PiiPfS_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPfS_Pii, .-_Z6kernelPfS_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPfS_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl tam_imag
.data
.align 4
.type tam_imag, @object
.size tam_imag, 4
tam_imag:
.long 4915200
.globl dimy
.align 4
.type dimy, @object
.size dimy, 4
dimy:
.long 2560
.globl dimx
.align 4
.type dimx, @object
.size dimx, 4
dimx:
.long 1920
.globl N
.align 4
.type N, @object
.size N, 4
N:
.long 93
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPfS_Pii # -- Begin function _Z21__device_stub__kernelPfS_Pii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_Pii,@function
_Z21__device_stub__kernelPfS_Pii: # @_Z21__device_stub__kernelPfS_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPfS_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_Pii, .Lfunc_end0-_Z21__device_stub__kernelPfS_Pii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type N,@object # @N
.data
.globl N
.p2align 2, 0x0
N:
.long 93 # 0x5d
.size N, 4
.type dimx,@object # @dimx
.globl dimx
.p2align 2, 0x0
dimx:
.long 1920 # 0x780
.size dimx, 4
.type dimy,@object # @dimy
.globl dimy
.p2align 2, 0x0
dimy:
.long 2560 # 0xa00
.size dimy, 4
.type tam_imag,@object # @tam_imag
.globl tam_imag
.p2align 2, 0x0
tam_imag:
.long 4915200 # 0x4b0000
.size tam_imag, 4
.type _Z6kernelPfS_Pii,@object # @_Z6kernelPfS_Pii
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_Pii
.p2align 3, 0x0
_Z6kernelPfS_Pii:
.quad _Z21__device_stub__kernelPfS_Pii
.size _Z6kernelPfS_Pii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPfS_Pii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfS_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define dx 0.01
#define dy 0.01
#define rho 8800
#define C 381
#define lambda 384.0
#define tau 0.01
#define BLOCK_SIZE 16
__global__ void __laplas__(float *T,float *T_old, const int n, const int height)
{
double at = lambda / (rho * C);
int iA = n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x;
if(blockDim.y * blockIdx.y + threadIdx.y>0 && blockDim.x * blockIdx.x + threadIdx.x>0 && blockDim.y * blockIdx.y + threadIdx.y < height && blockDim.x * blockIdx.x + threadIdx.x < n)
T[iA] = T_old[iA] + (tau / (dx * dx)) * at * (T_old[n * (blockDim.y * blockIdx.y + threadIdx.y-1) + blockDim.x * blockIdx.x + threadIdx.x] - 2 * T_old[iA] + T_old[n * (blockDim.y * blockIdx.y + threadIdx.y+1) + blockDim.x * blockIdx.x + threadIdx.x]) + (tau / (dy * dy)) * at * (T_old[n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x-1] - 2 * T_old[iA] + T_old[n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x+1]);
}
extern "C" void gpu(int index, int numDev, int n, int height, float *T, float *T_old)
{
cudaSetDevice(numDev);
if (index == 0)
{
int count;
unsigned int flag;
int device;
cudaGetDevice(&device);
cudaGetDeviceCount(&count);
cudaGetDeviceFlags(&flag);
printf("set device %d\n", numDev);
printf("device %d\n", device);
printf("device flag %d\n", flag);
printf("device count %d\n", count);
}
size_t size = (height+1) * (n+1) * sizeof(float);
float *dev_T = NULL;
cudaMalloc((void **)&dev_T, size);
float *dev_T_old = NULL;
cudaMalloc((void **)&dev_T_old, size);
cudaMemcpy( dev_T, T, size, cudaMemcpyHostToDevice );
cudaMemcpy( dev_T_old, T_old, size, cudaMemcpyHostToDevice );
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE, 1);
dim3 dimGrid(n/BLOCK_SIZE, height/BLOCK_SIZE, 1);
__laplas__<<<dimGrid, dimBlock>>>(dev_T,dev_T_old, n, height);
cudaDeviceSynchronize();
cudaMemcpy(T, dev_T, size, cudaMemcpyDeviceToHost);
cudaFree(dev_T);
cudaFree(dev_T_old);
} | code for sm_80
Function : _Z10__laplas__PfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.Y ; /* 0x00000000000479c3 */
/* 0x000e220000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0030*/ ULDC.64 UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fc60000000a00 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000ea60000002100 */
/*0050*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000ee20000002500 */
/*0060*/ UIMAD UR4, UR4, UR7, URZ ; /* 0x00000007040472a4 */
/* 0x001fe2000f8e023f */
/*0070*/ IADD3 R0, -R3, RZ, RZ ; /* 0x000000ff03007210 */
/* 0x002fe40007ffe1ff */
/*0080*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x004fc60007ffe1ff */
/*0090*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf05270 */
/*00a0*/ UIMAD UR5, UR5, UR6, URZ ; /* 0x00000006050572a4 */
/* 0x008fe2000f8e023f */
/*00b0*/ IADD3 R3, R3, UR4, RZ ; /* 0x0000000403037c10 */
/* 0x000fca000fffe0ff */
/*00c0*/ ISETP.EQ.OR P0, PT, R4, UR5, !P0 ; /* 0x0000000504007c0c */
/* 0x000fe4000c702670 */
/*00d0*/ IADD3 R2, R2, UR5, RZ ; /* 0x0000000502027c10 */
/* 0x000fe4000fffe0ff */
/*00e0*/ ISETP.GE.U32.OR P0, PT, R3, c[0x0][0x174], P0 ; /* 0x00005d0003007a0c */
/* 0x000fc80000706470 */
/*00f0*/ ISETP.GE.U32.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */
/* 0x000fda0000706470 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fe20000000f00 */
/*0120*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0130*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0140*/ IMAD R5, R3.reuse, R8, -c[0x0][0x170] ; /* 0x80005c0003057624 */
/* 0x040fe400078e0208 */
/*0150*/ IMAD R3, R3, c[0x0][0x170], R2 ; /* 0x00005c0003037a24 */
/* 0x000fc600078e0202 */
/*0160*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD.WIDE R4, R3, R0, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0200 */
/*0180*/ IMAD.WIDE.U32 R6, R9, R0, c[0x0][0x168] ; /* 0x00005a0009067625 */
/* 0x000fe200078e0000 */
/*0190*/ LEA R9, R8, R9, 0x1 ; /* 0x0000000908097211 */
/* 0x000fe200078e08ff */
/*01a0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IADD3 R11, R3, -0x1, RZ ; /* 0xffffffff030b7810 */
/* 0x000fc60007ffe0ff */
/*01c0*/ IMAD.WIDE.U32 R8, R9, R0.reuse, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x080fe200078e0000 */
/*01d0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee2000c1e1900 */
/*01e0*/ IADD3 R13, R3, 0x1, RZ ; /* 0x00000001030d7810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ IMAD.WIDE.U32 R10, R11, R0.reuse, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x080fe400078e0000 */
/*0200*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f24000c1e1900 */
/*0210*/ IMAD.WIDE.U32 R12, R13, R0, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x000fe400078e0000 */
/*0220*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000f62000c1e1900 */
/*0240*/ FADD R2, R14, R14 ; /* 0x0000000e0e027221 */
/* 0x004fe20000000000 */
/*0250*/ F2F.F64.F32 R4, R14 ; /* 0x0000000e00047310 */
/* 0x000fe60000201800 */
/*0260*/ FADD R15, -R2, R7 ; /* 0x00000007020f7221 */
/* 0x008fc80000000100 */
/*0270*/ FADD R6, R15, R8 ; /* 0x000000080f067221 */
/* 0x010fe40000000000 */
/*0280*/ FADD R2, -R2, R11 ; /* 0x0000000b02027221 */
/* 0x020fc80000000100 */
/*0290*/ F2F.F64.F32 R6, R6 ; /* 0x0000000600067310 */
/* 0x000e220000201800 */
/*02a0*/ FADD R15, R2, R13 ; /* 0x0000000d020f7221 */
/* 0x000fe40000000000 */
/*02b0*/ IMAD.WIDE R2, R3, R0, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0200 */
/*02c0*/ F2F.F64.F32 R8, R15 ; /* 0x0000000f00087310 */
/* 0x000e620000201800 */
/*02d0*/ DFMA R4, R6, c[0x2][0x0], R4 ; /* 0x0080000006047a2b */
/* 0x001e4c0000000004 */
/*02e0*/ DFMA R4, R8, c[0x2][0x0], R4 ; /* 0x0080000008047a2b */
/* 0x002e140000000004 */
/*02f0*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x001e240000301000 */
/*0300*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define dx 0.01
#define dy 0.01
#define rho 8800
#define C 381
#define lambda 384.0
#define tau 0.01
#define BLOCK_SIZE 16
__global__ void __laplas__(float *T,float *T_old, const int n, const int height)
{
double at = lambda / (rho * C);
int iA = n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x;
if(blockDim.y * blockIdx.y + threadIdx.y>0 && blockDim.x * blockIdx.x + threadIdx.x>0 && blockDim.y * blockIdx.y + threadIdx.y < height && blockDim.x * blockIdx.x + threadIdx.x < n)
T[iA] = T_old[iA] + (tau / (dx * dx)) * at * (T_old[n * (blockDim.y * blockIdx.y + threadIdx.y-1) + blockDim.x * blockIdx.x + threadIdx.x] - 2 * T_old[iA] + T_old[n * (blockDim.y * blockIdx.y + threadIdx.y+1) + blockDim.x * blockIdx.x + threadIdx.x]) + (tau / (dy * dy)) * at * (T_old[n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x-1] - 2 * T_old[iA] + T_old[n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x+1]);
}
extern "C" void gpu(int index, int numDev, int n, int height, float *T, float *T_old)
{
cudaSetDevice(numDev);
if (index == 0)
{
int count;
unsigned int flag;
int device;
cudaGetDevice(&device);
cudaGetDeviceCount(&count);
cudaGetDeviceFlags(&flag);
printf("set device %d\n", numDev);
printf("device %d\n", device);
printf("device flag %d\n", flag);
printf("device count %d\n", count);
}
size_t size = (height+1) * (n+1) * sizeof(float);
float *dev_T = NULL;
cudaMalloc((void **)&dev_T, size);
float *dev_T_old = NULL;
cudaMalloc((void **)&dev_T_old, size);
cudaMemcpy( dev_T, T, size, cudaMemcpyHostToDevice );
cudaMemcpy( dev_T_old, T_old, size, cudaMemcpyHostToDevice );
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE, 1);
dim3 dimGrid(n/BLOCK_SIZE, height/BLOCK_SIZE, 1);
__laplas__<<<dimGrid, dimBlock>>>(dev_T,dev_T_old, n, height);
cudaDeviceSynchronize();
cudaMemcpy(T, dev_T, size, cudaMemcpyDeviceToHost);
cudaFree(dev_T);
cudaFree(dev_T_old);
} | .file "tmpxft_000d87ba_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10__laplas__PfS_iiPfS_ii
.type _Z34__device_stub__Z10__laplas__PfS_iiPfS_ii, @function
_Z34__device_stub__Z10__laplas__PfS_iiPfS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10__laplas__PfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10__laplas__PfS_iiPfS_ii, .-_Z34__device_stub__Z10__laplas__PfS_iiPfS_ii
.globl _Z10__laplas__PfS_ii
.type _Z10__laplas__PfS_ii, @function
_Z10__laplas__PfS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10__laplas__PfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10__laplas__PfS_ii, .-_Z10__laplas__PfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "set device %d\n"
.LC1:
.string "device %d\n"
.LC2:
.string "device flag %d\n"
.LC3:
.string "device count %d\n"
.text
.globl gpu
.type gpu, @function
gpu:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %r15d
movl %esi, %ebx
movl %edx, %ebp
movl %ecx, %r12d
movq %r8, %r13
movq %r9, %r14
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %esi, %edi
call cudaSetDevice@PLT
testl %r15d, %r15d
je .L16
.L12:
leal 1(%r12), %ebx
leal 1(%rbp), %eax
imull %eax, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq $0, (%rsp)
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 16(%rsp)
movl $16, 20(%rsp)
movl $1, 24(%rsp)
leal 15(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $4, %eax
movl %eax, 28(%rsp)
leal 15(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $4, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
leaq 28(%rsp), %rdi
call cudaGetDevice@PLT
leaq 8(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq 16(%rsp), %rdi
call cudaGetDeviceFlags@PLT
movl %ebx, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 28(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L17:
movl %r12d, %ecx
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z10__laplas__PfS_iiPfS_ii
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size gpu, .-gpu
.section .rodata.str1.1
.LC4:
.string "_Z10__laplas__PfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10__laplas__PfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define dx 0.01
#define dy 0.01
#define rho 8800
#define C 381
#define lambda 384.0
#define tau 0.01
#define BLOCK_SIZE 16
__global__ void __laplas__(float *T,float *T_old, const int n, const int height)
{
double at = lambda / (rho * C);
int iA = n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x;
if(blockDim.y * blockIdx.y + threadIdx.y>0 && blockDim.x * blockIdx.x + threadIdx.x>0 && blockDim.y * blockIdx.y + threadIdx.y < height && blockDim.x * blockIdx.x + threadIdx.x < n)
T[iA] = T_old[iA] + (tau / (dx * dx)) * at * (T_old[n * (blockDim.y * blockIdx.y + threadIdx.y-1) + blockDim.x * blockIdx.x + threadIdx.x] - 2 * T_old[iA] + T_old[n * (blockDim.y * blockIdx.y + threadIdx.y+1) + blockDim.x * blockIdx.x + threadIdx.x]) + (tau / (dy * dy)) * at * (T_old[n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x-1] - 2 * T_old[iA] + T_old[n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x+1]);
}
extern "C" void gpu(int index, int numDev, int n, int height, float *T, float *T_old)
{
cudaSetDevice(numDev);
if (index == 0)
{
int count;
unsigned int flag;
int device;
cudaGetDevice(&device);
cudaGetDeviceCount(&count);
cudaGetDeviceFlags(&flag);
printf("set device %d\n", numDev);
printf("device %d\n", device);
printf("device flag %d\n", flag);
printf("device count %d\n", count);
}
size_t size = (height+1) * (n+1) * sizeof(float);
float *dev_T = NULL;
cudaMalloc((void **)&dev_T, size);
float *dev_T_old = NULL;
cudaMalloc((void **)&dev_T_old, size);
cudaMemcpy( dev_T, T, size, cudaMemcpyHostToDevice );
cudaMemcpy( dev_T_old, T_old, size, cudaMemcpyHostToDevice );
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE, 1);
dim3 dimGrid(n/BLOCK_SIZE, height/BLOCK_SIZE, 1);
__laplas__<<<dimGrid, dimBlock>>>(dev_T,dev_T_old, n, height);
cudaDeviceSynchronize();
cudaMemcpy(T, dev_T, size, cudaMemcpyDeviceToHost);
cudaFree(dev_T);
cudaFree(dev_T_old);
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define dx 0.01
#define dy 0.01
#define rho 8800
#define C 381
#define lambda 384.0
#define tau 0.01
#define BLOCK_SIZE 16
__global__ void __laplas__(float *T,float *T_old, const int n, const int height)
{
double at = lambda / (rho * C);
int iA = n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x;
if(blockDim.y * blockIdx.y + threadIdx.y>0 && blockDim.x * blockIdx.x + threadIdx.x>0 && blockDim.y * blockIdx.y + threadIdx.y < height && blockDim.x * blockIdx.x + threadIdx.x < n)
T[iA] = T_old[iA] + (tau / (dx * dx)) * at * (T_old[n * (blockDim.y * blockIdx.y + threadIdx.y-1) + blockDim.x * blockIdx.x + threadIdx.x] - 2 * T_old[iA] + T_old[n * (blockDim.y * blockIdx.y + threadIdx.y+1) + blockDim.x * blockIdx.x + threadIdx.x]) + (tau / (dy * dy)) * at * (T_old[n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x-1] - 2 * T_old[iA] + T_old[n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x+1]);
}
extern "C" void gpu(int index, int numDev, int n, int height, float *T, float *T_old)
{
hipSetDevice(numDev);
if (index == 0)
{
int count;
unsigned int flag;
int device;
hipGetDevice(&device);
hipGetDeviceCount(&count);
hipGetDeviceFlags(&flag);
printf("set device %d\n", numDev);
printf("device %d\n", device);
printf("device flag %d\n", flag);
printf("device count %d\n", count);
}
size_t size = (height+1) * (n+1) * sizeof(float);
float *dev_T = NULL;
hipMalloc((void **)&dev_T, size);
float *dev_T_old = NULL;
hipMalloc((void **)&dev_T_old, size);
hipMemcpy( dev_T, T, size, hipMemcpyHostToDevice );
hipMemcpy( dev_T_old, T_old, size, hipMemcpyHostToDevice );
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE, 1);
dim3 dimGrid(n/BLOCK_SIZE, height/BLOCK_SIZE, 1);
__laplas__<<<dimGrid, dimBlock>>>(dev_T,dev_T_old, n, height);
hipDeviceSynchronize();
hipMemcpy(T, dev_T, size, hipMemcpyDeviceToHost);
hipFree(dev_T);
hipFree(dev_T_old);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define dx 0.01
#define dy 0.01
#define rho 8800
#define C 381
#define lambda 384.0
#define tau 0.01
#define BLOCK_SIZE 16
__global__ void __laplas__(float *T,float *T_old, const int n, const int height)
{
double at = lambda / (rho * C);
int iA = n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x;
if(blockDim.y * blockIdx.y + threadIdx.y>0 && blockDim.x * blockIdx.x + threadIdx.x>0 && blockDim.y * blockIdx.y + threadIdx.y < height && blockDim.x * blockIdx.x + threadIdx.x < n)
T[iA] = T_old[iA] + (tau / (dx * dx)) * at * (T_old[n * (blockDim.y * blockIdx.y + threadIdx.y-1) + blockDim.x * blockIdx.x + threadIdx.x] - 2 * T_old[iA] + T_old[n * (blockDim.y * blockIdx.y + threadIdx.y+1) + blockDim.x * blockIdx.x + threadIdx.x]) + (tau / (dy * dy)) * at * (T_old[n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x-1] - 2 * T_old[iA] + T_old[n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x+1]);
}
extern "C" void gpu(int index, int numDev, int n, int height, float *T, float *T_old)
{
hipSetDevice(numDev);
if (index == 0)
{
int count;
unsigned int flag;
int device;
hipGetDevice(&device);
hipGetDeviceCount(&count);
hipGetDeviceFlags(&flag);
printf("set device %d\n", numDev);
printf("device %d\n", device);
printf("device flag %d\n", flag);
printf("device count %d\n", count);
}
size_t size = (height+1) * (n+1) * sizeof(float);
float *dev_T = NULL;
hipMalloc((void **)&dev_T, size);
float *dev_T_old = NULL;
hipMalloc((void **)&dev_T_old, size);
hipMemcpy( dev_T, T, size, hipMemcpyHostToDevice );
hipMemcpy( dev_T_old, T_old, size, hipMemcpyHostToDevice );
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE, 1);
dim3 dimGrid(n/BLOCK_SIZE, height/BLOCK_SIZE, 1);
__laplas__<<<dimGrid, dimBlock>>>(dev_T,dev_T_old, n, height);
hipDeviceSynchronize();
hipMemcpy(T, dev_T, size, hipMemcpyDeviceToHost);
hipFree(dev_T);
hipFree(dev_T_old);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10__laplas__PfS_ii
.globl _Z10__laplas__PfS_ii
.p2align 8
.type _Z10__laplas__PfS_ii,@function
_Z10__laplas__PfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, 0, v1
v_sub_nc_u32_e32 v3, 0, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_mul_i32 s14, s14, s2
v_add_nc_u32_e32 v1, s15, v1
v_add_nc_u32_e32 v0, s14, v0
v_cmp_ne_u32_e32 vcc_lo, s15, v2
v_cmp_ne_u32_e64 s2, s14, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_gt_u32_e64 s3, s7, v1
v_cmp_gt_u32_e64 s4, s6, v0
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v7, v1, s6
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v3, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[1:2], null, v3, s6, v[0:1]
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v3, v0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add3_u32 v1, v7, s6, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v9, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x2
global_load_b32 v6, v[9:10], off
global_load_b32 v9, v[4:5], off
global_load_b32 v10, v[0:1], off
v_add_nc_u32_e32 v1, -1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, 1, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b32 v4, v[2:3], off
global_load_b32 v5, v[0:1], off
s_mov_b32 s3, 0x3f8774ba
s_mov_b32 s2, 0xea317a3b
s_waitcnt vmcnt(4)
v_cvt_f64_f32_e32 v[0:1], v6
s_waitcnt vmcnt(3)
v_fmac_f32_e32 v9, -2.0, v6
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v9, v10
v_cvt_f64_f32_e32 v[2:3], v2
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v4, -2.0, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v4, v4, v5
v_fma_f64 v[0:1], v[2:3], s[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v4
v_fma_f64 v[0:1], v[2:3], s[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v8, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10__laplas__PfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10__laplas__PfS_ii, .Lfunc_end0-_Z10__laplas__PfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10__laplas__PfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10__laplas__PfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define dx 0.01
#define dy 0.01
#define rho 8800
#define C 381
#define lambda 384.0
#define tau 0.01
#define BLOCK_SIZE 16
__global__ void __laplas__(float *T,float *T_old, const int n, const int height)
{
double at = lambda / (rho * C);
int iA = n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x;
if(blockDim.y * blockIdx.y + threadIdx.y>0 && blockDim.x * blockIdx.x + threadIdx.x>0 && blockDim.y * blockIdx.y + threadIdx.y < height && blockDim.x * blockIdx.x + threadIdx.x < n)
T[iA] = T_old[iA] + (tau / (dx * dx)) * at * (T_old[n * (blockDim.y * blockIdx.y + threadIdx.y-1) + blockDim.x * blockIdx.x + threadIdx.x] - 2 * T_old[iA] + T_old[n * (blockDim.y * blockIdx.y + threadIdx.y+1) + blockDim.x * blockIdx.x + threadIdx.x]) + (tau / (dy * dy)) * at * (T_old[n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x-1] - 2 * T_old[iA] + T_old[n * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x+1]);
}
extern "C" void gpu(int index, int numDev, int n, int height, float *T, float *T_old)
{
hipSetDevice(numDev);
if (index == 0)
{
int count;
unsigned int flag;
int device;
hipGetDevice(&device);
hipGetDeviceCount(&count);
hipGetDeviceFlags(&flag);
printf("set device %d\n", numDev);
printf("device %d\n", device);
printf("device flag %d\n", flag);
printf("device count %d\n", count);
}
size_t size = (height+1) * (n+1) * sizeof(float);
float *dev_T = NULL;
hipMalloc((void **)&dev_T, size);
float *dev_T_old = NULL;
hipMalloc((void **)&dev_T_old, size);
hipMemcpy( dev_T, T, size, hipMemcpyHostToDevice );
hipMemcpy( dev_T_old, T_old, size, hipMemcpyHostToDevice );
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE, 1);
dim3 dimGrid(n/BLOCK_SIZE, height/BLOCK_SIZE, 1);
__laplas__<<<dimGrid, dimBlock>>>(dev_T,dev_T_old, n, height);
hipDeviceSynchronize();
hipMemcpy(T, dev_T, size, hipMemcpyDeviceToHost);
hipFree(dev_T);
hipFree(dev_T_old);
} | .text
.file "kernel.hip"
.globl _Z25__device_stub____laplas__PfS_ii # -- Begin function _Z25__device_stub____laplas__PfS_ii
.p2align 4, 0x90
.type _Z25__device_stub____laplas__PfS_ii,@function
_Z25__device_stub____laplas__PfS_ii: # @_Z25__device_stub____laplas__PfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10__laplas__PfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub____laplas__PfS_ii, .Lfunc_end0-_Z25__device_stub____laplas__PfS_ii
.cfi_endproc
# -- End function
.globl gpu # -- Begin function gpu
.p2align 4, 0x90
.type gpu,@function
gpu: # @gpu
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %r13
movq %r8, %rbx
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %ebp
movl %edi, %r12d
movl %esi, %edi
callq hipSetDevice
testl %r12d, %r12d
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
callq hipGetDevice
leaq 96(%rsp), %rdi
callq hipGetDeviceCount
leaq 48(%rsp), %rdi
callq hipGetDeviceFlags
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl 32(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 48(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 96(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
.LBB1_2:
leal 1(%r14), %eax
leal 1(%r15), %ecx
imull %eax, %ecx
movslq %ecx, %r12
shlq $2, %r12
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r15), %eax
testl %r15d, %r15d
cmovnsl %r15d, %eax
sarl $4, %eax
leal 15(%r14), %edi
testl %r14d, %r14d
cmovnsl %r14d, %edi
sarl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 28(%rsp)
movl %r14d, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10__laplas__PfS_ii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size gpu, .Lfunc_end1-gpu
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10__laplas__PfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10__laplas__PfS_ii,@object # @_Z10__laplas__PfS_ii
.section .rodata,"a",@progbits
.globl _Z10__laplas__PfS_ii
.p2align 3, 0x0
_Z10__laplas__PfS_ii:
.quad _Z25__device_stub____laplas__PfS_ii
.size _Z10__laplas__PfS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "set device %d\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "device %d\n"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "device flag %d\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "device count %d\n"
.size .L.str.3, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10__laplas__PfS_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub____laplas__PfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10__laplas__PfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10__laplas__PfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.Y ; /* 0x00000000000479c3 */
/* 0x000e220000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0030*/ ULDC.64 UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fc60000000a00 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000ea60000002100 */
/*0050*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000ee20000002500 */
/*0060*/ UIMAD UR4, UR4, UR7, URZ ; /* 0x00000007040472a4 */
/* 0x001fe2000f8e023f */
/*0070*/ IADD3 R0, -R3, RZ, RZ ; /* 0x000000ff03007210 */
/* 0x002fe40007ffe1ff */
/*0080*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x004fc60007ffe1ff */
/*0090*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf05270 */
/*00a0*/ UIMAD UR5, UR5, UR6, URZ ; /* 0x00000006050572a4 */
/* 0x008fe2000f8e023f */
/*00b0*/ IADD3 R3, R3, UR4, RZ ; /* 0x0000000403037c10 */
/* 0x000fca000fffe0ff */
/*00c0*/ ISETP.EQ.OR P0, PT, R4, UR5, !P0 ; /* 0x0000000504007c0c */
/* 0x000fe4000c702670 */
/*00d0*/ IADD3 R2, R2, UR5, RZ ; /* 0x0000000502027c10 */
/* 0x000fe4000fffe0ff */
/*00e0*/ ISETP.GE.U32.OR P0, PT, R3, c[0x0][0x174], P0 ; /* 0x00005d0003007a0c */
/* 0x000fc80000706470 */
/*00f0*/ ISETP.GE.U32.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */
/* 0x000fda0000706470 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fe20000000f00 */
/*0120*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0130*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0140*/ IMAD R5, R3.reuse, R8, -c[0x0][0x170] ; /* 0x80005c0003057624 */
/* 0x040fe400078e0208 */
/*0150*/ IMAD R3, R3, c[0x0][0x170], R2 ; /* 0x00005c0003037a24 */
/* 0x000fc600078e0202 */
/*0160*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD.WIDE R4, R3, R0, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0200 */
/*0180*/ IMAD.WIDE.U32 R6, R9, R0, c[0x0][0x168] ; /* 0x00005a0009067625 */
/* 0x000fe200078e0000 */
/*0190*/ LEA R9, R8, R9, 0x1 ; /* 0x0000000908097211 */
/* 0x000fe200078e08ff */
/*01a0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IADD3 R11, R3, -0x1, RZ ; /* 0xffffffff030b7810 */
/* 0x000fc60007ffe0ff */
/*01c0*/ IMAD.WIDE.U32 R8, R9, R0.reuse, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x080fe200078e0000 */
/*01d0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee2000c1e1900 */
/*01e0*/ IADD3 R13, R3, 0x1, RZ ; /* 0x00000001030d7810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ IMAD.WIDE.U32 R10, R11, R0.reuse, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x080fe400078e0000 */
/*0200*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f24000c1e1900 */
/*0210*/ IMAD.WIDE.U32 R12, R13, R0, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x000fe400078e0000 */
/*0220*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000f62000c1e1900 */
/*0240*/ FADD R2, R14, R14 ; /* 0x0000000e0e027221 */
/* 0x004fe20000000000 */
/*0250*/ F2F.F64.F32 R4, R14 ; /* 0x0000000e00047310 */
/* 0x000fe60000201800 */
/*0260*/ FADD R15, -R2, R7 ; /* 0x00000007020f7221 */
/* 0x008fc80000000100 */
/*0270*/ FADD R6, R15, R8 ; /* 0x000000080f067221 */
/* 0x010fe40000000000 */
/*0280*/ FADD R2, -R2, R11 ; /* 0x0000000b02027221 */
/* 0x020fc80000000100 */
/*0290*/ F2F.F64.F32 R6, R6 ; /* 0x0000000600067310 */
/* 0x000e220000201800 */
/*02a0*/ FADD R15, R2, R13 ; /* 0x0000000d020f7221 */
/* 0x000fe40000000000 */
/*02b0*/ IMAD.WIDE R2, R3, R0, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0200 */
/*02c0*/ F2F.F64.F32 R8, R15 ; /* 0x0000000f00087310 */
/* 0x000e620000201800 */
/*02d0*/ DFMA R4, R6, c[0x2][0x0], R4 ; /* 0x0080000006047a2b */
/* 0x001e4c0000000004 */
/*02e0*/ DFMA R4, R8, c[0x2][0x0], R4 ; /* 0x0080000008047a2b */
/* 0x002e140000000004 */
/*02f0*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x001e240000301000 */
/*0300*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10__laplas__PfS_ii
.globl _Z10__laplas__PfS_ii
.p2align 8
.type _Z10__laplas__PfS_ii,@function
_Z10__laplas__PfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, 0, v1
v_sub_nc_u32_e32 v3, 0, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_mul_i32 s14, s14, s2
v_add_nc_u32_e32 v1, s15, v1
v_add_nc_u32_e32 v0, s14, v0
v_cmp_ne_u32_e32 vcc_lo, s15, v2
v_cmp_ne_u32_e64 s2, s14, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_gt_u32_e64 s3, s7, v1
v_cmp_gt_u32_e64 s4, s6, v0
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v7, v1, s6
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v3, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[1:2], null, v3, s6, v[0:1]
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v3, v0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add3_u32 v1, v7, s6, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v9, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x2
global_load_b32 v6, v[9:10], off
global_load_b32 v9, v[4:5], off
global_load_b32 v10, v[0:1], off
v_add_nc_u32_e32 v1, -1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, 1, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b32 v4, v[2:3], off
global_load_b32 v5, v[0:1], off
s_mov_b32 s3, 0x3f8774ba
s_mov_b32 s2, 0xea317a3b
s_waitcnt vmcnt(4)
v_cvt_f64_f32_e32 v[0:1], v6
s_waitcnt vmcnt(3)
v_fmac_f32_e32 v9, -2.0, v6
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v9, v10
v_cvt_f64_f32_e32 v[2:3], v2
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v4, -2.0, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v4, v4, v5
v_fma_f64 v[0:1], v[2:3], s[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v4
v_fma_f64 v[0:1], v[2:3], s[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v8, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10__laplas__PfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10__laplas__PfS_ii, .Lfunc_end0-_Z10__laplas__PfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10__laplas__PfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10__laplas__PfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d87ba_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10__laplas__PfS_iiPfS_ii
.type _Z34__device_stub__Z10__laplas__PfS_iiPfS_ii, @function
_Z34__device_stub__Z10__laplas__PfS_iiPfS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10__laplas__PfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10__laplas__PfS_iiPfS_ii, .-_Z34__device_stub__Z10__laplas__PfS_iiPfS_ii
.globl _Z10__laplas__PfS_ii
.type _Z10__laplas__PfS_ii, @function
_Z10__laplas__PfS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10__laplas__PfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10__laplas__PfS_ii, .-_Z10__laplas__PfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "set device %d\n"
.LC1:
.string "device %d\n"
.LC2:
.string "device flag %d\n"
.LC3:
.string "device count %d\n"
.text
.globl gpu
.type gpu, @function
gpu:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %r15d
movl %esi, %ebx
movl %edx, %ebp
movl %ecx, %r12d
movq %r8, %r13
movq %r9, %r14
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %esi, %edi
call cudaSetDevice@PLT
testl %r15d, %r15d
je .L16
.L12:
leal 1(%r12), %ebx
leal 1(%rbp), %eax
imull %eax, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq $0, (%rsp)
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 16(%rsp)
movl $16, 20(%rsp)
movl $1, 24(%rsp)
leal 15(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $4, %eax
movl %eax, 28(%rsp)
leal 15(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $4, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
leaq 28(%rsp), %rdi
call cudaGetDevice@PLT
leaq 8(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq 16(%rsp), %rdi
call cudaGetDeviceFlags@PLT
movl %ebx, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 28(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L17:
movl %r12d, %ecx
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z10__laplas__PfS_iiPfS_ii
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size gpu, .-gpu
.section .rodata.str1.1
.LC4:
.string "_Z10__laplas__PfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10__laplas__PfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z25__device_stub____laplas__PfS_ii # -- Begin function _Z25__device_stub____laplas__PfS_ii
.p2align 4, 0x90
.type _Z25__device_stub____laplas__PfS_ii,@function
_Z25__device_stub____laplas__PfS_ii: # @_Z25__device_stub____laplas__PfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10__laplas__PfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub____laplas__PfS_ii, .Lfunc_end0-_Z25__device_stub____laplas__PfS_ii
.cfi_endproc
# -- End function
.globl gpu # -- Begin function gpu
.p2align 4, 0x90
.type gpu,@function
gpu: # @gpu
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %r13
movq %r8, %rbx
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %ebp
movl %edi, %r12d
movl %esi, %edi
callq hipSetDevice
testl %r12d, %r12d
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
callq hipGetDevice
leaq 96(%rsp), %rdi
callq hipGetDeviceCount
leaq 48(%rsp), %rdi
callq hipGetDeviceFlags
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl 32(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 48(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 96(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
.LBB1_2:
leal 1(%r14), %eax
leal 1(%r15), %ecx
imull %eax, %ecx
movslq %ecx, %r12
shlq $2, %r12
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r15), %eax
testl %r15d, %r15d
cmovnsl %r15d, %eax
sarl $4, %eax
leal 15(%r14), %edi
testl %r14d, %r14d
cmovnsl %r14d, %edi
sarl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 28(%rsp)
movl %r14d, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10__laplas__PfS_ii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size gpu, .Lfunc_end1-gpu
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10__laplas__PfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10__laplas__PfS_ii,@object # @_Z10__laplas__PfS_ii
.section .rodata,"a",@progbits
.globl _Z10__laplas__PfS_ii
.p2align 3, 0x0
_Z10__laplas__PfS_ii:
.quad _Z25__device_stub____laplas__PfS_ii
.size _Z10__laplas__PfS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "set device %d\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "device %d\n"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "device flag %d\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "device count %d\n"
.size .L.str.3, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10__laplas__PfS_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub____laplas__PfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10__laplas__PfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
cudaEvent_t start, stop;
__global__ void cudaComputeYGradient(int* y_gradient, unsigned char* channel, int image_width, int image_height) {
int y_kernel[3][3] = { { 1, 2, 1 }, { 0, 0, 0 }, { -1, -2, -1 } };
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index == 0) {
return;
}
y_gradient[index] =
y_kernel[0][0] * channel[index - 1] +
y_kernel[1][0] * channel[index] +
y_kernel[2][0] * channel[index + 1] +
y_kernel[0][1] * channel[index + image_width - 1] +
y_kernel[1][1] * channel[index + image_width] +
y_kernel[2][1] * channel[index + image_width + 1] +
y_kernel[0][2] * channel[index + 2 * image_width - 1] +
y_kernel[1][2] * channel[index + 2 * image_width] +
y_kernel[2][2] * channel[index + 2 * image_width + 1];
return;
} | code for sm_80
Function : _Z20cudaComputeYGradientPiPhii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R0, R8.reuse, c[0x0][0x170], RZ ; /* 0x00005c0008007a10 */
/* 0x040fe20007ffe0ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fe40007ffe0ff */
/*0090*/ IADD3 R3, R0, c[0x0][0x170], RZ ; /* 0x00005c0000037a10 */
/* 0x000fe40007ffe0ff */
/*00a0*/ IADD3 R2, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004027a10 */
/* 0x000fe40007f1e0ff */
/*00b0*/ IADD3 R5, R3, -0x1, RZ ; /* 0xffffffff03057810 */
/* 0x000fe40007ffe0ff */
/*00c0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc40007ffe0ff */
/*00d0*/ IADD3 R6, P1, R5.reuse, c[0x0][0x168], RZ ; /* 0x00005a0005067a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ LEA.HI.X.SX32 R3, R4, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0004037a11 */
/* 0x000fe400000f0eff */
/*00f0*/ IADD3 R4, P0, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x040fe40007f1e0ff */
/*0100*/ LEA.HI.X.SX32 R7, R5, c[0x0][0x16c], 0x1, P1 ; /* 0x00005b0005077a11 */
/* 0x000fe200008f0eff */
/*0110*/ LDG.E.U8 R9, [R2.64+0x2] ; /* 0x0000020402097981 */
/* 0x000ea2000c1e1100 */
/*0120*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000057a11 */
/* 0x000fc600000f0eff */
/*0130*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1100 */
/*0140*/ LDG.E.U8 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea8000c1e1100 */
/*0150*/ LDG.E.U8 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ee8000c1e1100 */
/*0160*/ LDG.E.U8 R11, [R4.64+0x2] ; /* 0x00000204040b7981 */
/* 0x000ee8000c1e1100 */
/*0170*/ LDG.E.U8 R13, [R6.64+0x2] ; /* 0x00000204060d7981 */
/* 0x000f22000c1e1100 */
/*0180*/ IADD3 R0, R12, R0, -R9 ; /* 0x000000000c007210 */
/* 0x004fe20007ffe809 */
/*0190*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc400078e00ff */
/*01a0*/ IMAD.IADD R10, R10, 0x1, -R11 ; /* 0x000000010a0a7824 */
/* 0x008fe400078e0a0b */
/*01b0*/ IMAD.IADD R13, R0, 0x1, -R13 ; /* 0x00000001000d7824 */
/* 0x010fe400078e0a0d */
/*01c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc800078e0209 */
/*01d0*/ IMAD R13, R10, 0x2, R13 ; /* 0x000000020a0d7824 */
/* 0x000fca00078e020d */
/*01e0*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
cudaEvent_t start, stop;
__global__ void cudaComputeYGradient(int* y_gradient, unsigned char* channel, int image_width, int image_height) {
int y_kernel[3][3] = { { 1, 2, 1 }, { 0, 0, 0 }, { -1, -2, -1 } };
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index == 0) {
return;
}
y_gradient[index] =
y_kernel[0][0] * channel[index - 1] +
y_kernel[1][0] * channel[index] +
y_kernel[2][0] * channel[index + 1] +
y_kernel[0][1] * channel[index + image_width - 1] +
y_kernel[1][1] * channel[index + image_width] +
y_kernel[2][1] * channel[index + image_width + 1] +
y_kernel[0][2] * channel[index + 2 * image_width - 1] +
y_kernel[1][2] * channel[index + 2 * image_width] +
y_kernel[2][2] * channel[index + 2 * image_width + 1];
return;
} | .file "tmpxft_000101ca_00000000-6_cudaComputeYGradient.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z20cudaComputeYGradientPiPhiiPiPhii
.type _Z44__device_stub__Z20cudaComputeYGradientPiPhiiPiPhii, @function
_Z44__device_stub__Z20cudaComputeYGradientPiPhiiPiPhii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20cudaComputeYGradientPiPhii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z20cudaComputeYGradientPiPhiiPiPhii, .-_Z44__device_stub__Z20cudaComputeYGradientPiPhiiPiPhii
.globl _Z20cudaComputeYGradientPiPhii
.type _Z20cudaComputeYGradientPiPhii, @function
_Z20cudaComputeYGradientPiPhii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20cudaComputeYGradientPiPhiiPiPhii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20cudaComputeYGradientPiPhii, .-_Z20cudaComputeYGradientPiPhii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20cudaComputeYGradientPiPhii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20cudaComputeYGradientPiPhii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl stop
.bss
.align 8
.type stop, @object
.size stop, 8
stop:
.zero 8
.globl start
.align 8
.type start, @object
.size start, 8
start:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
cudaEvent_t start, stop;
__global__ void cudaComputeYGradient(int* y_gradient, unsigned char* channel, int image_width, int image_height) {
int y_kernel[3][3] = { { 1, 2, 1 }, { 0, 0, 0 }, { -1, -2, -1 } };
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index == 0) {
return;
}
y_gradient[index] =
y_kernel[0][0] * channel[index - 1] +
y_kernel[1][0] * channel[index] +
y_kernel[2][0] * channel[index + 1] +
y_kernel[0][1] * channel[index + image_width - 1] +
y_kernel[1][1] * channel[index + image_width] +
y_kernel[2][1] * channel[index + image_width + 1] +
y_kernel[0][2] * channel[index + 2 * image_width - 1] +
y_kernel[1][2] * channel[index + 2 * image_width] +
y_kernel[2][2] * channel[index + 2 * image_width + 1];
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
hipEvent_t start, stop;
__global__ void cudaComputeYGradient(int* y_gradient, unsigned char* channel, int image_width, int image_height) {
int y_kernel[3][3] = { { 1, 2, 1 }, { 0, 0, 0 }, { -1, -2, -1 } };
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index == 0) {
return;
}
y_gradient[index] =
y_kernel[0][0] * channel[index - 1] +
y_kernel[1][0] * channel[index] +
y_kernel[2][0] * channel[index + 1] +
y_kernel[0][1] * channel[index + image_width - 1] +
y_kernel[1][1] * channel[index + image_width] +
y_kernel[2][1] * channel[index + image_width + 1] +
y_kernel[0][2] * channel[index + 2 * image_width - 1] +
y_kernel[1][2] * channel[index + 2 * image_width] +
y_kernel[2][2] * channel[index + 2 * image_width + 1];
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
hipEvent_t start, stop;
__global__ void cudaComputeYGradient(int* y_gradient, unsigned char* channel, int image_width, int image_height) {
int y_kernel[3][3] = { { 1, 2, 1 }, { 0, 0, 0 }, { -1, -2, -1 } };
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index == 0) {
return;
}
y_gradient[index] =
y_kernel[0][0] * channel[index - 1] +
y_kernel[1][0] * channel[index] +
y_kernel[2][0] * channel[index + 1] +
y_kernel[0][1] * channel[index + image_width - 1] +
y_kernel[1][1] * channel[index + image_width] +
y_kernel[2][1] * channel[index + image_width + 1] +
y_kernel[0][2] * channel[index + 2 * image_width - 1] +
y_kernel[1][2] * channel[index + 2 * image_width] +
y_kernel[2][2] * channel[index + 2 * image_width + 1];
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20cudaComputeYGradientPiPhii
.globl _Z20cudaComputeYGradientPiPhii
.p2align 8
.type _Z20cudaComputeYGradientPiPhii,@function
_Z20cudaComputeYGradientPiPhii:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_lshl_add_u32 v5, s4, 1, v1
v_add_nc_u32_e32 v0, s4, v1
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v5, vcc_lo, s2, v5
v_ashrrev_i32_e32 v8, 31, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
s_clause 0x5
global_load_u8 v0, v[5:6], off offset:-1
global_load_u8 v5, v[5:6], off offset:1
global_load_u8 v6, v[3:4], off offset:-1
global_load_u8 v3, v[3:4], off offset:1
global_load_u8 v4, v[7:8], off offset:-1
global_load_u8 v7, v[7:8], off offset:1
s_waitcnt vmcnt(3)
v_add_nc_u32_e32 v0, v6, v0
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v3, v3, v5
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v0, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshl_add_u32 v2, v4, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20cudaComputeYGradientPiPhii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20cudaComputeYGradientPiPhii, .Lfunc_end0-_Z20cudaComputeYGradientPiPhii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20cudaComputeYGradientPiPhii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20cudaComputeYGradientPiPhii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
hipEvent_t start, stop;
__global__ void cudaComputeYGradient(int* y_gradient, unsigned char* channel, int image_width, int image_height) {
int y_kernel[3][3] = { { 1, 2, 1 }, { 0, 0, 0 }, { -1, -2, -1 } };
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index == 0) {
return;
}
y_gradient[index] =
y_kernel[0][0] * channel[index - 1] +
y_kernel[1][0] * channel[index] +
y_kernel[2][0] * channel[index + 1] +
y_kernel[0][1] * channel[index + image_width - 1] +
y_kernel[1][1] * channel[index + image_width] +
y_kernel[2][1] * channel[index + image_width + 1] +
y_kernel[0][2] * channel[index + 2 * image_width - 1] +
y_kernel[1][2] * channel[index + 2 * image_width] +
y_kernel[2][2] * channel[index + 2 * image_width + 1];
return;
} | .text
.file "cudaComputeYGradient.hip"
.globl _Z35__device_stub__cudaComputeYGradientPiPhii # -- Begin function _Z35__device_stub__cudaComputeYGradientPiPhii
.p2align 4, 0x90
.type _Z35__device_stub__cudaComputeYGradientPiPhii,@function
_Z35__device_stub__cudaComputeYGradientPiPhii: # @_Z35__device_stub__cudaComputeYGradientPiPhii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20cudaComputeYGradientPiPhii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__cudaComputeYGradientPiPhii, .Lfunc_end0-_Z35__device_stub__cudaComputeYGradientPiPhii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20cudaComputeYGradientPiPhii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type start,@object # @start
.bss
.globl start
.p2align 3, 0x0
start:
.quad 0
.size start, 8
.type stop,@object # @stop
.globl stop
.p2align 3, 0x0
stop:
.quad 0
.size stop, 8
.type _Z20cudaComputeYGradientPiPhii,@object # @_Z20cudaComputeYGradientPiPhii
.section .rodata,"a",@progbits
.globl _Z20cudaComputeYGradientPiPhii
.p2align 3, 0x0
_Z20cudaComputeYGradientPiPhii:
.quad _Z35__device_stub__cudaComputeYGradientPiPhii
.size _Z20cudaComputeYGradientPiPhii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20cudaComputeYGradientPiPhii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__cudaComputeYGradientPiPhii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20cudaComputeYGradientPiPhii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20cudaComputeYGradientPiPhii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R0, R8.reuse, c[0x0][0x170], RZ ; /* 0x00005c0008007a10 */
/* 0x040fe20007ffe0ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fe40007ffe0ff */
/*0090*/ IADD3 R3, R0, c[0x0][0x170], RZ ; /* 0x00005c0000037a10 */
/* 0x000fe40007ffe0ff */
/*00a0*/ IADD3 R2, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004027a10 */
/* 0x000fe40007f1e0ff */
/*00b0*/ IADD3 R5, R3, -0x1, RZ ; /* 0xffffffff03057810 */
/* 0x000fe40007ffe0ff */
/*00c0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc40007ffe0ff */
/*00d0*/ IADD3 R6, P1, R5.reuse, c[0x0][0x168], RZ ; /* 0x00005a0005067a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ LEA.HI.X.SX32 R3, R4, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0004037a11 */
/* 0x000fe400000f0eff */
/*00f0*/ IADD3 R4, P0, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x040fe40007f1e0ff */
/*0100*/ LEA.HI.X.SX32 R7, R5, c[0x0][0x16c], 0x1, P1 ; /* 0x00005b0005077a11 */
/* 0x000fe200008f0eff */
/*0110*/ LDG.E.U8 R9, [R2.64+0x2] ; /* 0x0000020402097981 */
/* 0x000ea2000c1e1100 */
/*0120*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000057a11 */
/* 0x000fc600000f0eff */
/*0130*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1100 */
/*0140*/ LDG.E.U8 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea8000c1e1100 */
/*0150*/ LDG.E.U8 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ee8000c1e1100 */
/*0160*/ LDG.E.U8 R11, [R4.64+0x2] ; /* 0x00000204040b7981 */
/* 0x000ee8000c1e1100 */
/*0170*/ LDG.E.U8 R13, [R6.64+0x2] ; /* 0x00000204060d7981 */
/* 0x000f22000c1e1100 */
/*0180*/ IADD3 R0, R12, R0, -R9 ; /* 0x000000000c007210 */
/* 0x004fe20007ffe809 */
/*0190*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc400078e00ff */
/*01a0*/ IMAD.IADD R10, R10, 0x1, -R11 ; /* 0x000000010a0a7824 */
/* 0x008fe400078e0a0b */
/*01b0*/ IMAD.IADD R13, R0, 0x1, -R13 ; /* 0x00000001000d7824 */
/* 0x010fe400078e0a0d */
/*01c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc800078e0209 */
/*01d0*/ IMAD R13, R10, 0x2, R13 ; /* 0x000000020a0d7824 */
/* 0x000fca00078e020d */
/*01e0*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20cudaComputeYGradientPiPhii
.globl _Z20cudaComputeYGradientPiPhii
.p2align 8
.type _Z20cudaComputeYGradientPiPhii,@function
_Z20cudaComputeYGradientPiPhii:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_lshl_add_u32 v5, s4, 1, v1
v_add_nc_u32_e32 v0, s4, v1
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v5, vcc_lo, s2, v5
v_ashrrev_i32_e32 v8, 31, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
s_clause 0x5
global_load_u8 v0, v[5:6], off offset:-1
global_load_u8 v5, v[5:6], off offset:1
global_load_u8 v6, v[3:4], off offset:-1
global_load_u8 v3, v[3:4], off offset:1
global_load_u8 v4, v[7:8], off offset:-1
global_load_u8 v7, v[7:8], off offset:1
s_waitcnt vmcnt(3)
v_add_nc_u32_e32 v0, v6, v0
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v3, v3, v5
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v0, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshl_add_u32 v2, v4, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20cudaComputeYGradientPiPhii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20cudaComputeYGradientPiPhii, .Lfunc_end0-_Z20cudaComputeYGradientPiPhii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20cudaComputeYGradientPiPhii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20cudaComputeYGradientPiPhii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000101ca_00000000-6_cudaComputeYGradient.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z20cudaComputeYGradientPiPhiiPiPhii
.type _Z44__device_stub__Z20cudaComputeYGradientPiPhiiPiPhii, @function
_Z44__device_stub__Z20cudaComputeYGradientPiPhiiPiPhii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20cudaComputeYGradientPiPhii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z20cudaComputeYGradientPiPhiiPiPhii, .-_Z44__device_stub__Z20cudaComputeYGradientPiPhiiPiPhii
.globl _Z20cudaComputeYGradientPiPhii
.type _Z20cudaComputeYGradientPiPhii, @function
_Z20cudaComputeYGradientPiPhii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20cudaComputeYGradientPiPhiiPiPhii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20cudaComputeYGradientPiPhii, .-_Z20cudaComputeYGradientPiPhii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20cudaComputeYGradientPiPhii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20cudaComputeYGradientPiPhii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl stop
.bss
.align 8
.type stop, @object
.size stop, 8
stop:
.zero 8
.globl start
.align 8
.type start, @object
.size start, 8
start:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaComputeYGradient.hip"
.globl _Z35__device_stub__cudaComputeYGradientPiPhii # -- Begin function _Z35__device_stub__cudaComputeYGradientPiPhii
.p2align 4, 0x90
.type _Z35__device_stub__cudaComputeYGradientPiPhii,@function
_Z35__device_stub__cudaComputeYGradientPiPhii: # @_Z35__device_stub__cudaComputeYGradientPiPhii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20cudaComputeYGradientPiPhii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__cudaComputeYGradientPiPhii, .Lfunc_end0-_Z35__device_stub__cudaComputeYGradientPiPhii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20cudaComputeYGradientPiPhii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type start,@object # @start
.bss
.globl start
.p2align 3, 0x0
start:
.quad 0
.size start, 8
.type stop,@object # @stop
.globl stop
.p2align 3, 0x0
stop:
.quad 0
.size stop, 8
.type _Z20cudaComputeYGradientPiPhii,@object # @_Z20cudaComputeYGradientPiPhii
.section .rodata,"a",@progbits
.globl _Z20cudaComputeYGradientPiPhii
.p2align 3, 0x0
_Z20cudaComputeYGradientPiPhii:
.quad _Z35__device_stub__cudaComputeYGradientPiPhii
.size _Z20cudaComputeYGradientPiPhii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20cudaComputeYGradientPiPhii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__cudaComputeYGradientPiPhii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20cudaComputeYGradientPiPhii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
__global__
void saxpy2(float a, float *x, float *y, float* r, unsigned int n)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x;
i < n;
i += blockDim.x * gridDim.x)
{
r[i] = a * x[i] + y[i];
}
} | code for sm_80
Function : saxpy2
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06070 */
/*0100*/ FFMA R9, R2, c[0x0][0x160], R5 ; /* 0x0000580002097a23 */
/* 0x004fca0000000005 */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__
void saxpy2(float a, float *x, float *y, float* r, unsigned int n)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x;
i < n;
i += blockDim.x * gridDim.x)
{
r[i] = a * x[i] + y[i];
}
} | .file "tmpxft_0018f25a_00000000-6_saxpy2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6saxpy2fPfS_S_jfPfS_S_j
.type _Z31__device_stub__Z6saxpy2fPfS_S_jfPfS_S_j, @function
_Z31__device_stub__Z6saxpy2fPfS_S_jfPfS_S_j:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq saxpy2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z6saxpy2fPfS_S_jfPfS_S_j, .-_Z31__device_stub__Z6saxpy2fPfS_S_jfPfS_S_j
.globl saxpy2
.type saxpy2, @function
saxpy2:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6saxpy2fPfS_S_jfPfS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size saxpy2, .-saxpy2
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "saxpy2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq saxpy2(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__
void saxpy2(float a, float *x, float *y, float* r, unsigned int n)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x;
i < n;
i += blockDim.x * gridDim.x)
{
r[i] = a * x[i] + y[i];
}
} | #include <hip/hip_runtime.h>
extern "C"
__global__
void saxpy2(float a, float *x, float *y, float* r, unsigned int n)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x;
i < n;
i += blockDim.x * gridDim.x)
{
r[i] = a * x[i] + y[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__
void saxpy2(float a, float *x, float *y, float* r, unsigned int n)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x;
i < n;
i += blockDim.x * gridDim.x)
{
r[i] = a * x[i] + y[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected saxpy2
.globl saxpy2
.p2align 8
.type saxpy2,@function
saxpy2:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x20
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s11, s[2:3], 0x0
s_clause 0x2
s_load_b32 s9, s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s11, s10
s_mov_b32 s10, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, s0, s2, v2
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s1, v1
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, s9, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s8, v1
global_store_b32 v[2:3], v4, off
s_or_b32 s10, vcc_lo, s10
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel saxpy2
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size saxpy2, .Lfunc_end0-saxpy2
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: saxpy2
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: saxpy2.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__
void saxpy2(float a, float *x, float *y, float* r, unsigned int n)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x;
i < n;
i += blockDim.x * gridDim.x)
{
r[i] = a * x[i] + y[i];
}
} | .text
.file "saxpy2.hip"
.globl __device_stub__saxpy2 # -- Begin function __device_stub__saxpy2
.p2align 4, 0x90
.type __device_stub__saxpy2,@function
__device_stub__saxpy2: # @__device_stub__saxpy2
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 4(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $saxpy2, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__saxpy2, .Lfunc_end0-__device_stub__saxpy2
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $saxpy2, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type saxpy2,@object # @saxpy2
.section .rodata,"a",@progbits
.globl saxpy2
.p2align 3, 0x0
saxpy2:
.quad __device_stub__saxpy2
.size saxpy2, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "saxpy2"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__saxpy2
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym saxpy2
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : saxpy2
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06070 */
/*0100*/ FFMA R9, R2, c[0x0][0x160], R5 ; /* 0x0000580002097a23 */
/* 0x004fca0000000005 */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected saxpy2
.globl saxpy2
.p2align 8
.type saxpy2,@function
saxpy2:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x20
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s11, s[2:3], 0x0
s_clause 0x2
s_load_b32 s9, s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s11, s10
s_mov_b32 s10, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, s0, s2, v2
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s1, v1
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, s9, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s8, v1
global_store_b32 v[2:3], v4, off
s_or_b32 s10, vcc_lo, s10
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel saxpy2
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size saxpy2, .Lfunc_end0-saxpy2
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: saxpy2
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: saxpy2.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018f25a_00000000-6_saxpy2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6saxpy2fPfS_S_jfPfS_S_j
.type _Z31__device_stub__Z6saxpy2fPfS_S_jfPfS_S_j, @function
_Z31__device_stub__Z6saxpy2fPfS_S_jfPfS_S_j:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq saxpy2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z6saxpy2fPfS_S_jfPfS_S_j, .-_Z31__device_stub__Z6saxpy2fPfS_S_jfPfS_S_j
.globl saxpy2
.type saxpy2, @function
saxpy2:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6saxpy2fPfS_S_jfPfS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size saxpy2, .-saxpy2
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "saxpy2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq saxpy2(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "saxpy2.hip"
.globl __device_stub__saxpy2 # -- Begin function __device_stub__saxpy2
.p2align 4, 0x90
.type __device_stub__saxpy2,@function
__device_stub__saxpy2: # @__device_stub__saxpy2
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 4(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $saxpy2, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__saxpy2, .Lfunc_end0-__device_stub__saxpy2
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $saxpy2, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type saxpy2,@object # @saxpy2
.section .rodata,"a",@progbits
.globl saxpy2
.p2align 3, 0x0
saxpy2:
.quad __device_stub__saxpy2
.size saxpy2, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "saxpy2"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__saxpy2
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym saxpy2
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void simple_corner_turn_kernel(float *d_input, float *d_output, int primary_size, int secondary_size){
size_t primary = blockIdx.x * blockDim.x + threadIdx.x;
size_t secondary = blockIdx.y * blockDim.y + threadIdx.y;
d_output[(size_t)primary*secondary_size + secondary] = (float) __ldg(&d_input[(size_t)secondary*primary_size + primary]);
} | code for sm_80
Function : _Z25simple_corner_turn_kernelPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR4 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011404 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0060*/ S2R R8, SR_CTAID.Y ; /* 0x0000000000087919 */
/* 0x000e680000002600 */
/*0070*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fe200078e0205 */
/*0090*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*00a0*/ IMAD R8, R8, c[0x0][0x4], R9 ; /* 0x0000010008087a24 */
/* 0x002fc800078e0209 */
/*00b0*/ IMAD R7, R8, UR4, RZ ; /* 0x0000000408077c24 */
/* 0x000fca000f8e02ff */
/*00c0*/ IMAD.WIDE.U32 R2, R8, c[0x0][0x170], R4 ; /* 0x00005c0008027a25 */
/* 0x000fca00078e0004 */
/*00d0*/ IADD3 R3, R3, R7, RZ ; /* 0x0000000703037210 */
/* 0x000fe40007ffe0ff */
/*00e0*/ LEA R6, P0, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002067a11 */
/* 0x000fc800078010ff */
/*00f0*/ LEA.HI.X R7, R2, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590002077a11 */
/* 0x000fcc00000f1403 */
/*0100*/ LDG.E.CONSTANT R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e9900 */
/*0110*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0120*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR5 ; /* 0x0000001f3f047899 */
/* 0x000fcc0008011405 */
/*0130*/ IMAD R3, R4, UR4, RZ ; /* 0x0000000404037c24 */
/* 0x000fc6000f8e02ff */
/*0140*/ IMAD.WIDE.U32 R4, R4, c[0x0][0x174], R8 ; /* 0x00005d0004047a25 */
/* 0x000fca00078e0008 */
/*0150*/ IADD3 R3, R5, R3, RZ ; /* 0x0000000305037210 */
/* 0x000fe40007ffe0ff */
/*0160*/ LEA R2, P0, R4, c[0x0][0x168], 0x2 ; /* 0x00005a0004027a11 */
/* 0x000fc800078010ff */
/*0170*/ LEA.HI.X R3, R4, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0004037a11 */
/* 0x000fca00000f1403 */
/*0180*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x004fe2000c101906 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void simple_corner_turn_kernel(float *d_input, float *d_output, int primary_size, int secondary_size){
size_t primary = blockIdx.x * blockDim.x + threadIdx.x;
size_t secondary = blockIdx.y * blockDim.y + threadIdx.y;
d_output[(size_t)primary*secondary_size + secondary] = (float) __ldg(&d_input[(size_t)secondary*primary_size + primary]);
} | .file "tmpxft_000de0d8_00000000-6_simple_corner_turn_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z25simple_corner_turn_kernelPfS_iiPfS_ii
.type _Z49__device_stub__Z25simple_corner_turn_kernelPfS_iiPfS_ii, @function
_Z49__device_stub__Z25simple_corner_turn_kernelPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25simple_corner_turn_kernelPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z25simple_corner_turn_kernelPfS_iiPfS_ii, .-_Z49__device_stub__Z25simple_corner_turn_kernelPfS_iiPfS_ii
.globl _Z25simple_corner_turn_kernelPfS_ii
.type _Z25simple_corner_turn_kernelPfS_ii, @function
_Z25simple_corner_turn_kernelPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z25simple_corner_turn_kernelPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25simple_corner_turn_kernelPfS_ii, .-_Z25simple_corner_turn_kernelPfS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25simple_corner_turn_kernelPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25simple_corner_turn_kernelPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void simple_corner_turn_kernel(float *d_input, float *d_output, int primary_size, int secondary_size){
size_t primary = blockIdx.x * blockDim.x + threadIdx.x;
size_t secondary = blockIdx.y * blockDim.y + threadIdx.y;
d_output[(size_t)primary*secondary_size + secondary] = (float) __ldg(&d_input[(size_t)secondary*primary_size + primary]);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void simple_corner_turn_kernel(float *d_input, float *d_output, int primary_size, int secondary_size){
size_t primary = blockIdx.x * blockDim.x + threadIdx.x;
size_t secondary = blockIdx.y * blockDim.y + threadIdx.y;
d_output[(size_t)primary*secondary_size + secondary] = (float) __ldg(&d_input[(size_t)secondary*primary_size + primary]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void simple_corner_turn_kernel(float *d_input, float *d_output, int primary_size, int secondary_size){
size_t primary = blockIdx.x * blockDim.x + threadIdx.x;
size_t secondary = blockIdx.y * blockDim.y + threadIdx.y;
d_output[(size_t)primary*secondary_size + secondary] = (float) __ldg(&d_input[(size_t)secondary*primary_size + primary]);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25simple_corner_turn_kernelPfS_ii
.globl _Z25simple_corner_turn_kernelPfS_ii
.p2align 8
.type _Z25simple_corner_turn_kernelPfS_ii,@function
_Z25simple_corner_turn_kernelPfS_ii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s6, 16
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s4, 0
s_ashr_i32 s4, s4, 31
v_mov_b32_e32 v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[4:5], null, v2, s4, v[1:2]
s_and_b32 s4, s6, 0xffff
v_mad_u64_u32 v[5:6], null, s14, s4, v[0:1]
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_lshlrev_b64 v[3:4], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_ashr_i32 s0, s5, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v3
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
global_load_b32 v7, v[0:1], off
v_mad_u64_u32 v[0:1], null, v5, s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v5, s0, v[1:2]
v_mov_b32_e32 v1, v3
v_mov_b32_e32 v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v7, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25simple_corner_turn_kernelPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25simple_corner_turn_kernelPfS_ii, .Lfunc_end0-_Z25simple_corner_turn_kernelPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25simple_corner_turn_kernelPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25simple_corner_turn_kernelPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void simple_corner_turn_kernel(float *d_input, float *d_output, int primary_size, int secondary_size){
size_t primary = blockIdx.x * blockDim.x + threadIdx.x;
size_t secondary = blockIdx.y * blockDim.y + threadIdx.y;
d_output[(size_t)primary*secondary_size + secondary] = (float) __ldg(&d_input[(size_t)secondary*primary_size + primary]);
} | .text
.file "simple_corner_turn_kernel.hip"
.globl _Z40__device_stub__simple_corner_turn_kernelPfS_ii # -- Begin function _Z40__device_stub__simple_corner_turn_kernelPfS_ii
.p2align 4, 0x90
.type _Z40__device_stub__simple_corner_turn_kernelPfS_ii,@function
_Z40__device_stub__simple_corner_turn_kernelPfS_ii: # @_Z40__device_stub__simple_corner_turn_kernelPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25simple_corner_turn_kernelPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__simple_corner_turn_kernelPfS_ii, .Lfunc_end0-_Z40__device_stub__simple_corner_turn_kernelPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25simple_corner_turn_kernelPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25simple_corner_turn_kernelPfS_ii,@object # @_Z25simple_corner_turn_kernelPfS_ii
.section .rodata,"a",@progbits
.globl _Z25simple_corner_turn_kernelPfS_ii
.p2align 3, 0x0
_Z25simple_corner_turn_kernelPfS_ii:
.quad _Z40__device_stub__simple_corner_turn_kernelPfS_ii
.size _Z25simple_corner_turn_kernelPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25simple_corner_turn_kernelPfS_ii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__simple_corner_turn_kernelPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25simple_corner_turn_kernelPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25simple_corner_turn_kernelPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR4 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011404 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0060*/ S2R R8, SR_CTAID.Y ; /* 0x0000000000087919 */
/* 0x000e680000002600 */
/*0070*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fe200078e0205 */
/*0090*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*00a0*/ IMAD R8, R8, c[0x0][0x4], R9 ; /* 0x0000010008087a24 */
/* 0x002fc800078e0209 */
/*00b0*/ IMAD R7, R8, UR4, RZ ; /* 0x0000000408077c24 */
/* 0x000fca000f8e02ff */
/*00c0*/ IMAD.WIDE.U32 R2, R8, c[0x0][0x170], R4 ; /* 0x00005c0008027a25 */
/* 0x000fca00078e0004 */
/*00d0*/ IADD3 R3, R3, R7, RZ ; /* 0x0000000703037210 */
/* 0x000fe40007ffe0ff */
/*00e0*/ LEA R6, P0, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002067a11 */
/* 0x000fc800078010ff */
/*00f0*/ LEA.HI.X R7, R2, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590002077a11 */
/* 0x000fcc00000f1403 */
/*0100*/ LDG.E.CONSTANT R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e9900 */
/*0110*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0120*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR5 ; /* 0x0000001f3f047899 */
/* 0x000fcc0008011405 */
/*0130*/ IMAD R3, R4, UR4, RZ ; /* 0x0000000404037c24 */
/* 0x000fc6000f8e02ff */
/*0140*/ IMAD.WIDE.U32 R4, R4, c[0x0][0x174], R8 ; /* 0x00005d0004047a25 */
/* 0x000fca00078e0008 */
/*0150*/ IADD3 R3, R5, R3, RZ ; /* 0x0000000305037210 */
/* 0x000fe40007ffe0ff */
/*0160*/ LEA R2, P0, R4, c[0x0][0x168], 0x2 ; /* 0x00005a0004027a11 */
/* 0x000fc800078010ff */
/*0170*/ LEA.HI.X R3, R4, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0004037a11 */
/* 0x000fca00000f1403 */
/*0180*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x004fe2000c101906 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25simple_corner_turn_kernelPfS_ii
.globl _Z25simple_corner_turn_kernelPfS_ii
.p2align 8
.type _Z25simple_corner_turn_kernelPfS_ii,@function
_Z25simple_corner_turn_kernelPfS_ii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s6, 16
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s4, 0
s_ashr_i32 s4, s4, 31
v_mov_b32_e32 v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[4:5], null, v2, s4, v[1:2]
s_and_b32 s4, s6, 0xffff
v_mad_u64_u32 v[5:6], null, s14, s4, v[0:1]
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_lshlrev_b64 v[3:4], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_ashr_i32 s0, s5, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v3
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
global_load_b32 v7, v[0:1], off
v_mad_u64_u32 v[0:1], null, v5, s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v5, s0, v[1:2]
v_mov_b32_e32 v1, v3
v_mov_b32_e32 v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v7, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25simple_corner_turn_kernelPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25simple_corner_turn_kernelPfS_ii, .Lfunc_end0-_Z25simple_corner_turn_kernelPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25simple_corner_turn_kernelPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25simple_corner_turn_kernelPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000de0d8_00000000-6_simple_corner_turn_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z25simple_corner_turn_kernelPfS_iiPfS_ii
.type _Z49__device_stub__Z25simple_corner_turn_kernelPfS_iiPfS_ii, @function
_Z49__device_stub__Z25simple_corner_turn_kernelPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25simple_corner_turn_kernelPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z25simple_corner_turn_kernelPfS_iiPfS_ii, .-_Z49__device_stub__Z25simple_corner_turn_kernelPfS_iiPfS_ii
.globl _Z25simple_corner_turn_kernelPfS_ii
.type _Z25simple_corner_turn_kernelPfS_ii, @function
_Z25simple_corner_turn_kernelPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z25simple_corner_turn_kernelPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25simple_corner_turn_kernelPfS_ii, .-_Z25simple_corner_turn_kernelPfS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25simple_corner_turn_kernelPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25simple_corner_turn_kernelPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simple_corner_turn_kernel.hip"
.globl _Z40__device_stub__simple_corner_turn_kernelPfS_ii # -- Begin function _Z40__device_stub__simple_corner_turn_kernelPfS_ii
.p2align 4, 0x90
.type _Z40__device_stub__simple_corner_turn_kernelPfS_ii,@function
_Z40__device_stub__simple_corner_turn_kernelPfS_ii: # @_Z40__device_stub__simple_corner_turn_kernelPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25simple_corner_turn_kernelPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__simple_corner_turn_kernelPfS_ii, .Lfunc_end0-_Z40__device_stub__simple_corner_turn_kernelPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25simple_corner_turn_kernelPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25simple_corner_turn_kernelPfS_ii,@object # @_Z25simple_corner_turn_kernelPfS_ii
.section .rodata,"a",@progbits
.globl _Z25simple_corner_turn_kernelPfS_ii
.p2align 3, 0x0
_Z25simple_corner_turn_kernelPfS_ii:
.quad _Z40__device_stub__simple_corner_turn_kernelPfS_ii
.size _Z25simple_corner_turn_kernelPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25simple_corner_turn_kernelPfS_ii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__simple_corner_turn_kernelPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25simple_corner_turn_kernelPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void memcpy( float *dst, float *src )
{
int index = threadIdx.x + 4 * blockIdx.x * blockDim.x;
float a[4];//allocated in registers
for(int i=0;i<4;i++) a[i]=src[index+i*blockDim.x];
for(int i=0;i<4;i++) dst[index+i*blockDim.x]=a[i];
} | code for sm_80
Function : _Z6memcpyPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ SHF.L.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007819 */
/* 0x001fca00000006ff */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fc800078e0203 */
/*0070*/ IMAD.WIDE.U32 R2, R0.reuse, R17, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x040fe200078e0011 */
/*0080*/ IADD3 R12, R0, c[0x0][0x0], RZ ; /* 0x00000000000c7a10 */
/* 0x000fc80007ffe0ff */
/*0090*/ IADD3 R14, R12.reuse, c[0x0][0x0], RZ ; /* 0x000000000c0e7a10 */
/* 0x040fe20007ffe0ff */
/*00a0*/ IMAD.WIDE.U32 R4, R12, R17.reuse, c[0x0][0x168] ; /* 0x00005a000c047625 */
/* 0x080fe200078e0011 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IADD3 R16, R14.reuse, c[0x0][0x0], RZ ; /* 0x000000000e107a10 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD.WIDE.U32 R6, R14, R17.reuse, c[0x0][0x168] ; /* 0x00005a000e067625 */
/* 0x080fe400078e0011 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ee4000c1e1900 */
/*00f0*/ IMAD.WIDE.U32 R8, R16, R17.reuse, c[0x0][0x168] ; /* 0x00005a0010087625 */
/* 0x080fe400078e0011 */
/*0100*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000f28000c1e1900 */
/*0110*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000f62000c1e1900 */
/*0120*/ IMAD.WIDE.U32 R10, R0, R17, c[0x0][0x160] ; /* 0x00005800000a7625 */
/* 0x000fc800078e0011 */
/*0130*/ IMAD.WIDE.U32 R12, R12, R17, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fc800078e0011 */
/*0140*/ IMAD.WIDE.U32 R14, R14, R17, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc800078e0011 */
/*0150*/ IMAD.WIDE.U32 R16, R16, R17, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x000fe200078e0011 */
/*0160*/ STG.E [R10.64], R3 ; /* 0x000000030a007986 */
/* 0x004fe8000c101904 */
/*0170*/ STG.E [R12.64], R5 ; /* 0x000000050c007986 */
/* 0x008fe8000c101904 */
/*0180*/ STG.E [R14.64], R7 ; /* 0x000000070e007986 */
/* 0x010fe8000c101904 */
/*0190*/ STG.E [R16.64], R9 ; /* 0x0000000910007986 */
/* 0x020fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void memcpy( float *dst, float *src )
{
int index = threadIdx.x + 4 * blockIdx.x * blockDim.x;
float a[4];//allocated in registers
for(int i=0;i<4;i++) a[i]=src[index+i*blockDim.x];
for(int i=0;i<4;i++) dst[index+i*blockDim.x]=a[i];
} | .file "tmpxft_00179782_00000000-6_memcpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6memcpyPfS_PfS_
.type _Z27__device_stub__Z6memcpyPfS_PfS_, @function
_Z27__device_stub__Z6memcpyPfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6memcpyPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z6memcpyPfS_PfS_, .-_Z27__device_stub__Z6memcpyPfS_PfS_
.globl _Z6memcpyPfS_
.type _Z6memcpyPfS_, @function
_Z6memcpyPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6memcpyPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6memcpyPfS_, .-_Z6memcpyPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6memcpyPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6memcpyPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void memcpy( float *dst, float *src )
{
int index = threadIdx.x + 4 * blockIdx.x * blockDim.x;
float a[4];//allocated in registers
for(int i=0;i<4;i++) a[i]=src[index+i*blockDim.x];
for(int i=0;i<4;i++) dst[index+i*blockDim.x]=a[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void memcpy( float *dst, float *src )
{
int index = threadIdx.x + 4 * blockIdx.x * blockDim.x;
float a[4];//allocated in registers
for(int i=0;i<4;i++) a[i]=src[index+i*blockDim.x];
for(int i=0;i<4;i++) dst[index+i*blockDim.x]=a[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void memcpy( float *dst, float *src )
{
int index = threadIdx.x + 4 * blockIdx.x * blockDim.x;
float a[4];//allocated in registers
for(int i=0;i<4;i++) a[i]=src[index+i*blockDim.x];
for(int i=0;i<4;i++) dst[index+i*blockDim.x]=a[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6memcpyPfS_
.globl _Z6memcpyPfS_
.p2align 8
.type _Z6memcpyPfS_,@function
_Z6memcpyPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[6:7], s[0:1], 0x8
s_mov_b64 s[8:9], 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s5
v_lshl_add_u32 v0, s15, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, v0
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[1:2]
s_cmp_eq_u32 s8, 3
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s8, 2
s_cselect_b32 s2, -1, 0
global_load_b32 v7, v[7:8], off
s_cmp_eq_u32 s8, 1
v_add_nc_u32_e32 v1, s5, v1
s_cselect_b32 s3, -1, 0
s_cmp_eq_u32 s8, 0
s_cselect_b32 s4, -1, 0
s_add_u32 s8, s8, 1
s_addc_u32 s9, s9, 0
s_cmp_lg_u32 s8, 4
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_cndmask_b32_e64 v5, v5, v7, s2
v_cndmask_b32_e64 v4, v4, v7, s3
v_cndmask_b32_e64 v3, v3, v7, s4
s_cbranch_scc1 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_mov_b64 s[2:3], 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 1
v_lshlrev_b64 v[7:8], 2, v[0:1]
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s2, 2
v_cndmask_b32_e32 v2, v3, v4, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s2, 3
v_add_nc_u32_e32 v0, s5, v0
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s2, s2, 1
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 4
global_store_b32 v[7:8], v2, off
s_cbranch_scc0 .LBB0_3
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6memcpyPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6memcpyPfS_, .Lfunc_end0-_Z6memcpyPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6memcpyPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6memcpyPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void memcpy( float *dst, float *src )
{
int index = threadIdx.x + 4 * blockIdx.x * blockDim.x;
float a[4];//allocated in registers
for(int i=0;i<4;i++) a[i]=src[index+i*blockDim.x];
for(int i=0;i<4;i++) dst[index+i*blockDim.x]=a[i];
} | .text
.file "memcpy.hip"
.globl _Z21__device_stub__memcpyPfS_ # -- Begin function _Z21__device_stub__memcpyPfS_
.p2align 4, 0x90
.type _Z21__device_stub__memcpyPfS_,@function
_Z21__device_stub__memcpyPfS_: # @_Z21__device_stub__memcpyPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6memcpyPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__memcpyPfS_, .Lfunc_end0-_Z21__device_stub__memcpyPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6memcpyPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6memcpyPfS_,@object # @_Z6memcpyPfS_
.section .rodata,"a",@progbits
.globl _Z6memcpyPfS_
.p2align 3, 0x0
_Z6memcpyPfS_:
.quad _Z21__device_stub__memcpyPfS_
.size _Z6memcpyPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6memcpyPfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__memcpyPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6memcpyPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6memcpyPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ SHF.L.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007819 */
/* 0x001fca00000006ff */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fc800078e0203 */
/*0070*/ IMAD.WIDE.U32 R2, R0.reuse, R17, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x040fe200078e0011 */
/*0080*/ IADD3 R12, R0, c[0x0][0x0], RZ ; /* 0x00000000000c7a10 */
/* 0x000fc80007ffe0ff */
/*0090*/ IADD3 R14, R12.reuse, c[0x0][0x0], RZ ; /* 0x000000000c0e7a10 */
/* 0x040fe20007ffe0ff */
/*00a0*/ IMAD.WIDE.U32 R4, R12, R17.reuse, c[0x0][0x168] ; /* 0x00005a000c047625 */
/* 0x080fe200078e0011 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IADD3 R16, R14.reuse, c[0x0][0x0], RZ ; /* 0x000000000e107a10 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD.WIDE.U32 R6, R14, R17.reuse, c[0x0][0x168] ; /* 0x00005a000e067625 */
/* 0x080fe400078e0011 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ee4000c1e1900 */
/*00f0*/ IMAD.WIDE.U32 R8, R16, R17.reuse, c[0x0][0x168] ; /* 0x00005a0010087625 */
/* 0x080fe400078e0011 */
/*0100*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000f28000c1e1900 */
/*0110*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000f62000c1e1900 */
/*0120*/ IMAD.WIDE.U32 R10, R0, R17, c[0x0][0x160] ; /* 0x00005800000a7625 */
/* 0x000fc800078e0011 */
/*0130*/ IMAD.WIDE.U32 R12, R12, R17, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fc800078e0011 */
/*0140*/ IMAD.WIDE.U32 R14, R14, R17, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc800078e0011 */
/*0150*/ IMAD.WIDE.U32 R16, R16, R17, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x000fe200078e0011 */
/*0160*/ STG.E [R10.64], R3 ; /* 0x000000030a007986 */
/* 0x004fe8000c101904 */
/*0170*/ STG.E [R12.64], R5 ; /* 0x000000050c007986 */
/* 0x008fe8000c101904 */
/*0180*/ STG.E [R14.64], R7 ; /* 0x000000070e007986 */
/* 0x010fe8000c101904 */
/*0190*/ STG.E [R16.64], R9 ; /* 0x0000000910007986 */
/* 0x020fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6memcpyPfS_
.globl _Z6memcpyPfS_
.p2align 8
.type _Z6memcpyPfS_,@function
_Z6memcpyPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[6:7], s[0:1], 0x8
s_mov_b64 s[8:9], 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s5
v_lshl_add_u32 v0, s15, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, v0
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[1:2]
s_cmp_eq_u32 s8, 3
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s8, 2
s_cselect_b32 s2, -1, 0
global_load_b32 v7, v[7:8], off
s_cmp_eq_u32 s8, 1
v_add_nc_u32_e32 v1, s5, v1
s_cselect_b32 s3, -1, 0
s_cmp_eq_u32 s8, 0
s_cselect_b32 s4, -1, 0
s_add_u32 s8, s8, 1
s_addc_u32 s9, s9, 0
s_cmp_lg_u32 s8, 4
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_cndmask_b32_e64 v5, v5, v7, s2
v_cndmask_b32_e64 v4, v4, v7, s3
v_cndmask_b32_e64 v3, v3, v7, s4
s_cbranch_scc1 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_mov_b64 s[2:3], 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 1
v_lshlrev_b64 v[7:8], 2, v[0:1]
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s2, 2
v_cndmask_b32_e32 v2, v3, v4, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s2, 3
v_add_nc_u32_e32 v0, s5, v0
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s2, s2, 1
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 4
global_store_b32 v[7:8], v2, off
s_cbranch_scc0 .LBB0_3
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6memcpyPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6memcpyPfS_, .Lfunc_end0-_Z6memcpyPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6memcpyPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6memcpyPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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