system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
using T = double;
constexpr T range_min = 2.0;
constexpr T range_max = 4.0;
constexpr T range = range_max - range_min;
constexpr auto all_threads = 4096;
constexpr auto block_size = 16;
constexpr auto thread_size = all_threads / block_size;
constexpr auto warmup = 300;
constexpr auto loops = 1000;
__device__ T get_a() {
return // 2 * log2(2 + range / thread_size * threadIdx.x);
range_min +
// ((T)thread_size) / ((T)threadIdx.x) * range
range / (thread_size * block_size) *
(blockIdx.x * thread_size + threadIdx.x);
}
__global__ void logistic() {
const auto a = get_a();
T x = 0.8;
for(int index = 0; index < warmup; index++) {
x = a * x * (1 - x);
}
for(int index = warmup; index < loops; index++) {
printf("%1.8lf %1.8lf\n", a, x);
x = a * x * (1 - x);
}
}
int main() {
// size_t nBytes = loops * (thread_size + 1) * sizeof(T);
// T *x;
// cudaMalloc((void **)&x, nBytes);
logistic<<<block_size, thread_size>>>();
// cudaFree(x);
cudaDeviceReset();
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
using T = double;
constexpr T range_min = 2.0;
constexpr T range_max = 4.0;
constexpr T range = range_max - range_min;
constexpr auto all_threads = 4096;
constexpr auto block_size = 16;
constexpr auto thread_size = all_threads / block_size;
constexpr auto warmup = 300;
constexpr auto loops = 1000;
__device__ T get_a() {
return // 2 * log2(2 + range / thread_size * threadIdx.x);
range_min +
// ((T)thread_size) / ((T)threadIdx.x) * range
range / (thread_size * block_size) *
(blockIdx.x * thread_size + threadIdx.x);
}
__global__ void logistic() {
const auto a = get_a();
T x = 0.8;
for(int index = 0; index < warmup; index++) {
x = a * x * (1 - x);
}
for(int index = warmup; index < loops; index++) {
printf("%1.8lf %1.8lf\n", a, x);
x = a * x * (1 - x);
}
}
int main() {
// size_t nBytes = loops * (thread_size + 1) * sizeof(T);
// T *x;
// cudaMalloc((void **)&x, nBytes);
logistic<<<block_size, thread_size>>>();
// cudaFree(x);
hipDeviceReset();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
using T = double;
constexpr T range_min = 2.0;
constexpr T range_max = 4.0;
constexpr T range = range_max - range_min;
constexpr auto all_threads = 4096;
constexpr auto block_size = 16;
constexpr auto thread_size = all_threads / block_size;
constexpr auto warmup = 300;
constexpr auto loops = 1000;
__device__ T get_a() {
return // 2 * log2(2 + range / thread_size * threadIdx.x);
range_min +
// ((T)thread_size) / ((T)threadIdx.x) * range
range / (thread_size * block_size) *
(blockIdx.x * thread_size + threadIdx.x);
}
__global__ void logistic() {
const auto a = get_a();
T x = 0.8;
for(int index = 0; index < warmup; index++) {
x = a * x * (1 - x);
}
for(int index = warmup; index < loops; index++) {
printf("%1.8lf %1.8lf\n", a, x);
x = a * x * (1 - x);
}
}
int main() {
// size_t nBytes = loops * (thread_size + 1) * sizeof(T);
// T *x;
// cudaMalloc((void **)&x, nBytes);
logistic<<<block_size, thread_size>>>();
// cudaFree(x);
hipDeviceReset();
} | .text
.file "logistic.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__logisticv # -- Begin function _Z23__device_stub__logisticv
.p2align 4, 0x90
.type _Z23__device_stub__logisticv,@function
_Z23__device_stub__logisticv: # @_Z23__device_stub__logisticv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8logisticv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__logisticv, .Lfunc_end0-_Z23__device_stub__logisticv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 240(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8logisticv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8logisticv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8logisticv,@object # @_Z8logisticv
.section .rodata,"a",@progbits
.globl _Z8logisticv
.p2align 3, 0x0
_Z8logisticv:
.quad _Z23__device_stub__logisticv
.size _Z8logisticv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8logisticv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__logisticv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8logisticv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001069b4_00000000-6_logistic.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5get_av
.type _Z5get_av, @function
_Z5get_av:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z5get_av, .-_Z5get_av
.globl _Z26__device_stub__Z8logisticvv
.type _Z26__device_stub__Z8logisticvv, @function
_Z26__device_stub__Z8logisticvv:
.LFB3695:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8logisticv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z26__device_stub__Z8logisticvv, .-_Z26__device_stub__Z8logisticvv
.globl _Z8logisticv
.type _Z8logisticv, @function
_Z8logisticv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8logisticvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z8logisticv, .-_Z8logisticv
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $16, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L14:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call _Z26__device_stub__Z8logisticvv
jmp .L14
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8logisticv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8logisticv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "logistic.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__logisticv # -- Begin function _Z23__device_stub__logisticv
.p2align 4, 0x90
.type _Z23__device_stub__logisticv,@function
_Z23__device_stub__logisticv: # @_Z23__device_stub__logisticv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8logisticv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__logisticv, .Lfunc_end0-_Z23__device_stub__logisticv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 240(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8logisticv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8logisticv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8logisticv,@object # @_Z8logisticv
.section .rodata,"a",@progbits
.globl _Z8logisticv
.p2align 3, 0x0
_Z8logisticv:
.quad _Z23__device_stub__logisticv
.size _Z8logisticv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8logisticv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__logisticv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8logisticv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
#define initTimer struct timeval tv1, tv2; struct timezone tz
#define startTimer gettimeofday(&tv1, &tz)
#define stopTimer gettimeofday(&tv2, &tz)
#define tpsCalcul (tv2.tv_sec-tv1.tv_sec)*1000000L + (tv2.tv_usec-tv1.tv_usec)
#define MAX_DIM_GRID 65535
#define MAX_DIM_BLOCK 1024
#define MAX_CHAINE 100
#define MIN(a, b) (a < b ? a : b)
#define MAX(a, b) (a > b ? a : b)
#define CALLOC(ptr, nr, type) if (!(ptr = (type *) calloc((size_t)(nr), sizeof(type)))) { \
printf("Erreur lors de l'allocation memoire \n") ; \
exit (-1); \
}
#define FOPEN(fich,fichier,sens) if ((fich=fopen(fichier,sens)) == NULL) { \
printf("Probleme d'ouverture du fichier %s\n",fichier); \
exit(-1); \
}
#define MAX_VALEUR 255
#define MIN_VALEUR 0
#define NBPOINTSPARLIGNES 15
#define false 0
#define true 1
#define boolean int
long tailleVecteur ;
/* KERNEL CUDA */
__global__ void rehaussement_contraste_gpu(int *vec, int *res, int min, float coef ,long N) {
long i = (long)blockIdx.x * (long)blockDim.x + (long)threadIdx.x;
res[i] = (vec[i] - min) * coef;
}
void rehaussement_contraste_cpu(int *vec, int *res, int min, float coef ,long N)
{
long i ;
for (i=0 ; i < N ; i ++) {
res[i] = (vec[i] - min) * coef;
}
}
int main(int argc, char *argv[]) {
if (argc < 2) {
printf("Erreur, manque un argument\n");
exit(0);
}
/*========================================================================*/
/* Declaration de variables et allocation memoire */
/*========================================================================*/
int i, j, n;
int LE_MIN = MAX_VALEUR;
int LE_MAX = MIN_VALEUR;
float ETALEMENT = 0.0;
int **image;
int **resultat;
int X, Y, x, y;
int P;
FILE *Src, *Dst;
char SrcFile[MAX_CHAINE];
char DstFile[MAX_CHAINE];
char ligne[MAX_CHAINE];
boolean inverse = false;
char *Chemin;
/*========================================================================*/
/* Recuperation des parametres */
/*========================================================================*/
sscanf(argv[1],"%s", SrcFile);
sprintf(DstFile,"%s.new",SrcFile);
/*========================================================================*/
/* Recuperation de l'endroit ou l'on travail */
/*========================================================================*/
CALLOC(Chemin, MAX_CHAINE, char);
Chemin = getenv("PWD");
printf("Repertoire de travail : %s \n\n",Chemin);
/*========================================================================*/
/* Ouverture des fichiers */
/*========================================================================*/
printf("Operations sur les fichiers\n");
FOPEN(Src, SrcFile, "r");
printf("\t Fichier source ouvert (%s) \n",SrcFile);
FOPEN(Dst, DstFile, "w");
printf("\t Fichier destination ouvert (%s) \n",DstFile);
/*========================================================================*/
/* On effectue la lecture du fichier source */
/*========================================================================*/
printf("\t Lecture entete du fichier source ");
for (i = 0 ; i < 2 ; i++) {
fgets(ligne, MAX_CHAINE, Src);
fprintf(Dst,"%s", ligne);
}
fscanf(Src," %d %d\n",&X, &Y);
fprintf(Dst," %d %d\n", X, Y);
fgets(ligne, MAX_CHAINE, Src); /* Lecture du 255 */
fprintf(Dst,"%s", ligne);
printf(": OK \n");
/*========================================================================*/
/* Allocation memoire pour l'image source et l'image resultat */
/*========================================================================*/
CALLOC(image, Y+1, int *);
CALLOC(resultat, Y+1, int *);
for (i=0;i<Y;i++) {
CALLOC(image[i], X+1, int);
CALLOC(resultat[i], X+1, int);
for (j=0;j<X;j++) {
image[i][j] = 0;
resultat[i][j] = 0;
}
}
printf("\t\t Initialisation de l'image [%d ; %d] : Ok \n", X, Y);
tailleVecteur = X * Y;
x = 0;
y = 0;
/*========================================================================*/
/* Lecture du fichier pour remplir l'image source */
/*========================================================================*/
while (! feof(Src)) {
n = fscanf(Src,"%d",&P);
image[y][x] = P;
LE_MIN = MIN(LE_MIN, P);
LE_MAX = MAX(LE_MAX, P);
x ++;
if (n == EOF || (x == X && y == Y-1)) {
break;
}
if (x == X) {
x = 0 ;
y++;
}
}
fclose(Src);
printf("\t Lecture du fichier image : Ok \n\n");
/*========================================================================*/
/* Calcul du facteur d'etalement */
/*========================================================================*/
if (inverse) {
ETALEMENT = 0.2;
} else {
ETALEMENT = (float)(MAX_VALEUR - MIN_VALEUR) / (float)(LE_MAX - LE_MIN);
}
/*========================================================================*/
/* Code CUDA --> Calcul de chaque nouvelle valeur de pixel */
/*========================================================================*/
long blocksize = 1;
// GPUmode, if 1 -> use cuda & gpu else use cpu
int gpumode = 1;
int *vecteur;
int *resultatContraste;
int *cudaVec;
int *cudaRes;
initTimer;
long size = sizeof(int)*tailleVecteur;
vecteur = (int *)malloc(size);
resultatContraste = (int *)malloc(size);
if (vecteur == NULL) {
printf("Allocation memoire qui pose probleme (vecteur) \n");
}
if (resultatContraste == NULL) {
printf("Allocation memoire qui pose probleme (resultatContraste) \n");
}
// DONE: init vec and res
long i_vec = 0 ;
for (i = 0 ; i < Y ; i++) {
for (j = 0 ; j < X ; j++) {
vecteur[i_vec] = image[i][j];
resultatContraste[i_vec] = 0;
i_vec++;
}
}
if (gpumode==1){
printf("Using gpu\n");
if (cudaMalloc((void **)&cudaVec, size) == cudaErrorMemoryAllocation) {
printf("Allocation memoire qui pose probleme (cudaVec) \n");
}
if (cudaMalloc((void **)&cudaRes, size) == cudaErrorMemoryAllocation) {
printf("Allocation memoire qui pose probleme (cudaRes) \n");
}
long dimBlock = blocksize;
long dimGrid = tailleVecteur/blocksize;
if ((tailleVecteur % blocksize) != 0) {
dimGrid++;
}
int res = cudaMemcpy(&cudaVec[0], &vecteur[0], size, cudaMemcpyHostToDevice);
// printf("Copy CPU -> GPU %d \n",res);
startTimer;
rehaussement_contraste_gpu<<<dimGrid, dimBlock>>>(cudaVec, cudaRes, LE_MIN, ETALEMENT, tailleVecteur);
// DONE: Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
stopTimer;
cudaMemcpy(&resultatContraste[0], &cudaRes[0], size, cudaMemcpyDeviceToHost);
/* Test bon fonctionnement */
bool ok = true;
int indice = -1;
int valtest = -1;
for (i_vec= 0 ; i_vec < tailleVecteur ; i_vec++) {
valtest = (vecteur[i_vec] - LE_MIN) * ETALEMENT;
if (resultatContraste[i_vec] != valtest) {
// printf("Resultat GPU %d Resultat CPU %d \n", resultatContraste[i_vec], valtest);
ok = false;
if (indice ==-1) {
indice = i_vec;
}
}
}
printf("------ ");
printf("dimGrid %ld dimBlock %ld ",dimGrid, dimBlock);
if (ok) {
printf("Resultat ok\n");
} else {
printf("resultatContraste NON ok (%d)\n", indice);
}
cudaFree(cudaVec);
cudaFree(cudaRes);
/*========================================================================*/
/* Fin Code CUDA */
/*========================================================================*/
}
else
{
printf("Using cpu\n");
startTimer;
rehaussement_contraste_cpu(vecteur, resultatContraste, LE_MIN, ETALEMENT, tailleVecteur);
stopTimer;
}
printf("chrono %ld \n", tpsCalcul);
/*========================================================================*/
/* Sauvegarde de l'image dans le fichier resultat */
/*========================================================================*/
n = 0;
long cpt;
for (cpt = 0 ; cpt < tailleVecteur ; cpt++) {
// printf("%d \n", resultatContraste[cpt]);
fprintf(Dst,"%3d ",resultatContraste[cpt]);
n++;
if (n == NBPOINTSPARLIGNES) {
n = 0;
fprintf(Dst, "\n");
}
}
fprintf(Dst,"\n");
fclose(Dst);
/*========================================================================*/
/* Fin du programme principal */
/*========================================================================*/
exit(0);
} | code for sm_80
Function : _Z26rehaussement_contraste_gpuPiS_ifl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e240000002500 */
/*0050*/ IMAD.WIDE.U32 R2, R5, c[0x0][0x0], R2 ; /* 0x0000000005027a25 */
/* 0x001fc800078e0002 */
/*0060*/ IMAD.SHL.U32 R4, R2.reuse, 0x4, RZ ; /* 0x0000000402047824 */
/* 0x040fe200078e00ff */
/*0070*/ SHF.L.U64.HI R5, R2, 0x2, R3 ; /* 0x0000000202057819 */
/* 0x000fc80000010203 */
/*0080*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*0090*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590005037a10 */
/* 0x000fca00007fe4ff */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R5, R5, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0005057a10 */
/* 0x000fe400007fe4ff */
/*00d0*/ IADD3 R0, R2, -c[0x0][0x170], RZ ; /* 0x80005c0002007a10 */
/* 0x004fcc0007ffe0ff */
/*00e0*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x000e240000201400 */
/*00f0*/ FMUL R6, R0, c[0x0][0x174] ; /* 0x00005d0000067a20 */
/* 0x001fcc0000400000 */
/*0100*/ F2I.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000e24000020f100 */
/*0110*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
#define initTimer struct timeval tv1, tv2; struct timezone tz
#define startTimer gettimeofday(&tv1, &tz)
#define stopTimer gettimeofday(&tv2, &tz)
#define tpsCalcul (tv2.tv_sec-tv1.tv_sec)*1000000L + (tv2.tv_usec-tv1.tv_usec)
#define MAX_DIM_GRID 65535
#define MAX_DIM_BLOCK 1024
#define MAX_CHAINE 100
#define MIN(a, b) (a < b ? a : b)
#define MAX(a, b) (a > b ? a : b)
#define CALLOC(ptr, nr, type) if (!(ptr = (type *) calloc((size_t)(nr), sizeof(type)))) { \
printf("Erreur lors de l'allocation memoire \n") ; \
exit (-1); \
}
#define FOPEN(fich,fichier,sens) if ((fich=fopen(fichier,sens)) == NULL) { \
printf("Probleme d'ouverture du fichier %s\n",fichier); \
exit(-1); \
}
#define MAX_VALEUR 255
#define MIN_VALEUR 0
#define NBPOINTSPARLIGNES 15
#define false 0
#define true 1
#define boolean int
long tailleVecteur ;
/* KERNEL CUDA */
__global__ void rehaussement_contraste_gpu(int *vec, int *res, int min, float coef ,long N) {
long i = (long)blockIdx.x * (long)blockDim.x + (long)threadIdx.x;
res[i] = (vec[i] - min) * coef;
}
void rehaussement_contraste_cpu(int *vec, int *res, int min, float coef ,long N)
{
long i ;
for (i=0 ; i < N ; i ++) {
res[i] = (vec[i] - min) * coef;
}
}
int main(int argc, char *argv[]) {
if (argc < 2) {
printf("Erreur, manque un argument\n");
exit(0);
}
/*========================================================================*/
/* Declaration de variables et allocation memoire */
/*========================================================================*/
int i, j, n;
int LE_MIN = MAX_VALEUR;
int LE_MAX = MIN_VALEUR;
float ETALEMENT = 0.0;
int **image;
int **resultat;
int X, Y, x, y;
int P;
FILE *Src, *Dst;
char SrcFile[MAX_CHAINE];
char DstFile[MAX_CHAINE];
char ligne[MAX_CHAINE];
boolean inverse = false;
char *Chemin;
/*========================================================================*/
/* Recuperation des parametres */
/*========================================================================*/
sscanf(argv[1],"%s", SrcFile);
sprintf(DstFile,"%s.new",SrcFile);
/*========================================================================*/
/* Recuperation de l'endroit ou l'on travail */
/*========================================================================*/
CALLOC(Chemin, MAX_CHAINE, char);
Chemin = getenv("PWD");
printf("Repertoire de travail : %s \n\n",Chemin);
/*========================================================================*/
/* Ouverture des fichiers */
/*========================================================================*/
printf("Operations sur les fichiers\n");
FOPEN(Src, SrcFile, "r");
printf("\t Fichier source ouvert (%s) \n",SrcFile);
FOPEN(Dst, DstFile, "w");
printf("\t Fichier destination ouvert (%s) \n",DstFile);
/*========================================================================*/
/* On effectue la lecture du fichier source */
/*========================================================================*/
printf("\t Lecture entete du fichier source ");
for (i = 0 ; i < 2 ; i++) {
fgets(ligne, MAX_CHAINE, Src);
fprintf(Dst,"%s", ligne);
}
fscanf(Src," %d %d\n",&X, &Y);
fprintf(Dst," %d %d\n", X, Y);
fgets(ligne, MAX_CHAINE, Src); /* Lecture du 255 */
fprintf(Dst,"%s", ligne);
printf(": OK \n");
/*========================================================================*/
/* Allocation memoire pour l'image source et l'image resultat */
/*========================================================================*/
CALLOC(image, Y+1, int *);
CALLOC(resultat, Y+1, int *);
for (i=0;i<Y;i++) {
CALLOC(image[i], X+1, int);
CALLOC(resultat[i], X+1, int);
for (j=0;j<X;j++) {
image[i][j] = 0;
resultat[i][j] = 0;
}
}
printf("\t\t Initialisation de l'image [%d ; %d] : Ok \n", X, Y);
tailleVecteur = X * Y;
x = 0;
y = 0;
/*========================================================================*/
/* Lecture du fichier pour remplir l'image source */
/*========================================================================*/
while (! feof(Src)) {
n = fscanf(Src,"%d",&P);
image[y][x] = P;
LE_MIN = MIN(LE_MIN, P);
LE_MAX = MAX(LE_MAX, P);
x ++;
if (n == EOF || (x == X && y == Y-1)) {
break;
}
if (x == X) {
x = 0 ;
y++;
}
}
fclose(Src);
printf("\t Lecture du fichier image : Ok \n\n");
/*========================================================================*/
/* Calcul du facteur d'etalement */
/*========================================================================*/
if (inverse) {
ETALEMENT = 0.2;
} else {
ETALEMENT = (float)(MAX_VALEUR - MIN_VALEUR) / (float)(LE_MAX - LE_MIN);
}
/*========================================================================*/
/* Code CUDA --> Calcul de chaque nouvelle valeur de pixel */
/*========================================================================*/
long blocksize = 1;
// GPUmode, if 1 -> use cuda & gpu else use cpu
int gpumode = 1;
int *vecteur;
int *resultatContraste;
int *cudaVec;
int *cudaRes;
initTimer;
long size = sizeof(int)*tailleVecteur;
vecteur = (int *)malloc(size);
resultatContraste = (int *)malloc(size);
if (vecteur == NULL) {
printf("Allocation memoire qui pose probleme (vecteur) \n");
}
if (resultatContraste == NULL) {
printf("Allocation memoire qui pose probleme (resultatContraste) \n");
}
// DONE: init vec and res
long i_vec = 0 ;
for (i = 0 ; i < Y ; i++) {
for (j = 0 ; j < X ; j++) {
vecteur[i_vec] = image[i][j];
resultatContraste[i_vec] = 0;
i_vec++;
}
}
if (gpumode==1){
printf("Using gpu\n");
if (cudaMalloc((void **)&cudaVec, size) == cudaErrorMemoryAllocation) {
printf("Allocation memoire qui pose probleme (cudaVec) \n");
}
if (cudaMalloc((void **)&cudaRes, size) == cudaErrorMemoryAllocation) {
printf("Allocation memoire qui pose probleme (cudaRes) \n");
}
long dimBlock = blocksize;
long dimGrid = tailleVecteur/blocksize;
if ((tailleVecteur % blocksize) != 0) {
dimGrid++;
}
int res = cudaMemcpy(&cudaVec[0], &vecteur[0], size, cudaMemcpyHostToDevice);
// printf("Copy CPU -> GPU %d \n",res);
startTimer;
rehaussement_contraste_gpu<<<dimGrid, dimBlock>>>(cudaVec, cudaRes, LE_MIN, ETALEMENT, tailleVecteur);
// DONE: Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
stopTimer;
cudaMemcpy(&resultatContraste[0], &cudaRes[0], size, cudaMemcpyDeviceToHost);
/* Test bon fonctionnement */
bool ok = true;
int indice = -1;
int valtest = -1;
for (i_vec= 0 ; i_vec < tailleVecteur ; i_vec++) {
valtest = (vecteur[i_vec] - LE_MIN) * ETALEMENT;
if (resultatContraste[i_vec] != valtest) {
// printf("Resultat GPU %d Resultat CPU %d \n", resultatContraste[i_vec], valtest);
ok = false;
if (indice ==-1) {
indice = i_vec;
}
}
}
printf("------ ");
printf("dimGrid %ld dimBlock %ld ",dimGrid, dimBlock);
if (ok) {
printf("Resultat ok\n");
} else {
printf("resultatContraste NON ok (%d)\n", indice);
}
cudaFree(cudaVec);
cudaFree(cudaRes);
/*========================================================================*/
/* Fin Code CUDA */
/*========================================================================*/
}
else
{
printf("Using cpu\n");
startTimer;
rehaussement_contraste_cpu(vecteur, resultatContraste, LE_MIN, ETALEMENT, tailleVecteur);
stopTimer;
}
printf("chrono %ld \n", tpsCalcul);
/*========================================================================*/
/* Sauvegarde de l'image dans le fichier resultat */
/*========================================================================*/
n = 0;
long cpt;
for (cpt = 0 ; cpt < tailleVecteur ; cpt++) {
// printf("%d \n", resultatContraste[cpt]);
fprintf(Dst,"%3d ",resultatContraste[cpt]);
n++;
if (n == NBPOINTSPARLIGNES) {
n = 0;
fprintf(Dst, "\n");
}
}
fprintf(Dst,"\n");
fclose(Dst);
/*========================================================================*/
/* Fin du programme principal */
/*========================================================================*/
exit(0);
} | .file "tmpxft_0018c3e7_00000000-6_CodeCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26rehaussement_contraste_cpuPiS_ifl
.type _Z26rehaussement_contraste_cpuPiS_ifl, @function
_Z26rehaussement_contraste_cpuPiS_ifl:
.LFB2057:
.cfi_startproc
endbr64
testq %rcx, %rcx
jle .L3
movl $0, %eax
.L5:
movl (%rdi,%rax,4), %r8d
subl %edx, %r8d
pxor %xmm1, %xmm1
cvtsi2ssl %r8d, %xmm1
mulss %xmm0, %xmm1
cvttss2sil %xmm1, %r8d
movl %r8d, (%rsi,%rax,4)
addq $1, %rax
cmpq %rax, %rcx
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z26rehaussement_contraste_cpuPiS_ifl, .-_Z26rehaussement_contraste_cpuPiS_ifl
.globl _Z51__device_stub__Z26rehaussement_contraste_gpuPiS_iflPiS_ifl
.type _Z51__device_stub__Z26rehaussement_contraste_gpuPiS_iflPiS_ifl, @function
_Z51__device_stub__Z26rehaussement_contraste_gpuPiS_iflPiS_ifl:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26rehaussement_contraste_gpuPiS_ifl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z51__device_stub__Z26rehaussement_contraste_gpuPiS_iflPiS_ifl, .-_Z51__device_stub__Z26rehaussement_contraste_gpuPiS_iflPiS_ifl
.globl _Z26rehaussement_contraste_gpuPiS_ifl
.type _Z26rehaussement_contraste_gpuPiS_ifl, @function
_Z26rehaussement_contraste_gpuPiS_ifl:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z26rehaussement_contraste_gpuPiS_iflPiS_ifl
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z26rehaussement_contraste_gpuPiS_ifl, .-_Z26rehaussement_contraste_gpuPiS_ifl
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Erreur, manque un argument\n"
.LC1:
.string "%s"
.LC2:
.string "%s.new"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Erreur lors de l'allocation memoire \n"
.section .rodata.str1.1
.LC4:
.string "PWD"
.LC5:
.string "Repertoire de travail : %s \n\n"
.LC6:
.string "Operations sur les fichiers\n"
.LC7:
.string "r"
.section .rodata.str1.8
.align 8
.LC8:
.string "Probleme d'ouverture du fichier %s\n"
.align 8
.LC9:
.string "\t Fichier source ouvert (%s) \n"
.section .rodata.str1.1
.LC10:
.string "w"
.section .rodata.str1.8
.align 8
.LC11:
.string "\t Fichier destination ouvert (%s) \n"
.align 8
.LC12:
.string "\t Lecture entete du fichier source "
.section .rodata.str1.1
.LC13:
.string " %d %d\n"
.LC14:
.string ": OK \n"
.section .rodata.str1.8
.align 8
.LC15:
.string "\t\t Initialisation de l'image [%d ; %d] : Ok \n"
.section .rodata.str1.1
.LC16:
.string "%d"
.section .rodata.str1.8
.align 8
.LC17:
.string "\t Lecture du fichier image : Ok \n\n"
.align 8
.LC19:
.string "Allocation memoire qui pose probleme (vecteur) \n"
.align 8
.LC20:
.string "Allocation memoire qui pose probleme (resultatContraste) \n"
.section .rodata.str1.1
.LC21:
.string "Using gpu\n"
.section .rodata.str1.8
.align 8
.LC22:
.string "Allocation memoire qui pose probleme (cudaVec) \n"
.align 8
.LC23:
.string "Allocation memoire qui pose probleme (cudaRes) \n"
.section .rodata.str1.1
.LC24:
.string "------ "
.LC25:
.string "dimGrid %ld dimBlock %ld "
.LC26:
.string "Resultat ok\n"
.section .rodata.str1.8
.align 8
.LC27:
.string "resultatContraste NON ok (%d)\n"
.section .rodata.str1.1
.LC28:
.string "chrono %ld \n"
.LC29:
.string "%3d "
.LC30:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $472, %rsp
.cfi_def_cfa_offset 528
movq %fs:40, %rax
movq %rax, 456(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L62
leaq 128(%rsp), %rbx
movq 8(%rsi), %rdi
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 240(%rsp), %rdi
movq %rbx, %r8
leaq .LC2(%rip), %rcx
movl $100, %edx
movl $2, %esi
movl $0, %eax
call __sprintf_chk@PLT
movl $1, %esi
movl $100, %edi
call calloc@PLT
testq %rax, %rax
je .L63
leaq .LC4(%rip), %rdi
call getenv@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 128(%rsp), %rdi
leaq .LC7(%rip), %rsi
call fopen@PLT
movq %rax, %r15
testq %rax, %rax
je .L64
leaq 128(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 240(%rsp), %rdi
leaq .LC10(%rip), %rsi
call fopen@PLT
movq %rax, 16(%rsp)
testq %rax, %rax
je .L65
leaq 240(%rsp), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 352(%rsp), %rbx
movq %r15, %rcx
movl $100, %edx
movl $100, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %rbx, %rcx
leaq .LC1(%rip), %rbp
movq %rbp, %rdx
movl $2, %esi
movq 16(%rsp), %r14
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r15, %rcx
movl $100, %edx
movl $100, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %rbx, %rcx
movq %rbp, %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq 48(%rsp), %rcx
leaq 44(%rsp), %rdx
leaq .LC13(%rip), %r12
movq %r12, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 48(%rsp), %r8d
movl 44(%rsp), %ecx
movq %r12, %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r15, %rcx
movl $100, %edx
movl $100, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %rbx, %rcx
movq %rbp, %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 48(%rsp), %eax
movl %eax, 28(%rsp)
leal 1(%rax), %ebx
movslq %ebx, %rbx
movl $8, %esi
movq %rbx, %rdi
call calloc@PLT
movq %rax, 8(%rsp)
testq %rax, %rax
je .L66
movl $8, %esi
movq %rbx, %rdi
call calloc@PLT
movq %rax, %r14
testq %rax, %rax
je .L21
cmpl $0, 28(%rsp)
jle .L23
movq 8(%rsp), %rdi
movq %rdi, %r12
movslq 28(%rsp), %rax
leaq (%rdi,%rax,8), %rax
movq %rax, (%rsp)
jmp .L29
.L62:
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L63:
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L64:
leaq 128(%rsp), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L65:
leaq 240(%rsp), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L66:
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L21:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L67:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L25:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L27:
addq $8, %r12
addq $8, %r14
movq (%rsp), %rax
cmpq %rax, %r12
je .L23
.L29:
movl 44(%rsp), %r13d
leal 1(%r13), %ebp
movslq %ebp, %rbp
movl $4, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, %rbx
movq %rax, (%r12)
testq %rax, %rax
je .L67
movl $4, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, (%r14)
testq %rax, %rax
je .L25
movslq %r13d, %rcx
salq $2, %rcx
movl $0, %edx
testl %r13d, %r13d
jle .L27
.L28:
movl $0, (%rbx,%rdx)
movl $0, (%rax,%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L28
jmp .L27
.L23:
movl 28(%rsp), %ecx
movl 44(%rsp), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 44(%rsp), %eax
imull 48(%rsp), %eax
cltq
movq %rax, tailleVecteur(%rip)
movl $0, %r14d
movl $0, %ebp
movl $0, %r13d
movl $255, %r12d
jmp .L30
.L68:
addl $1, %r14d
movl %ebx, %ebp
.L30:
movq %r15, %rdi
call feof@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L31
leaq 52(%rsp), %rdx
leaq .LC16(%rip), %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl %eax, %ecx
movl 52(%rsp), %eax
movslq %r14d, %rdx
movslq %ebp, %rsi
movq 8(%rsp), %rdi
movq (%rdi,%rdx,8), %rdx
movl %eax, (%rdx,%rsi,4)
cmpl %eax, %r12d
cmovg %eax, %r12d
cmpl %eax, %r13d
cmovl %eax, %r13d
addl $1, %ebp
cmpl $-1, %ecx
je .L31
cmpl %ebp, 44(%rsp)
jne .L30
movl 48(%rsp), %eax
subl $1, %eax
cmpl %r14d, %eax
jne .L68
.L31:
movq %r15, %rdi
call fclose@PLT
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subl %r12d, %r13d
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
movss .LC18(%rip), %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%rsp)
movq tailleVecteur(%rip), %rax
leaq 0(,%rax,4), %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
testq %rbp, %rbp
je .L69
.L34:
testq %rbx, %rbx
je .L70
.L35:
movl 48(%rsp), %eax
testl %eax, %eax
jle .L36
movl 44(%rsp), %r9d
movq 8(%rsp), %rdi
movq %rdi, %r8
cltq
leaq (%rdi,%rax,8), %r10
movl $0, %edi
movslq %r9d, %r14
leal -1(%r9), %r11d
jmp .L37
.L69:
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L34
.L70:
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L35
.L39:
leaq (%r14,%rdi), %rsi
movq %rdi, %rdx
negq %rdx
movq (%r8), %rax
leaq (%rax,%rdx,4), %rcx
movq %rdi, %rax
.L38:
movl (%rcx,%rax,4), %edx
movl %edx, 0(%rbp,%rax,4)
movl $0, (%rbx,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L38
leaq 1(%rdi,%r11), %rdi
.L40:
addq $8, %r8
cmpq %r10, %r8
je .L36
.L37:
testl %r9d, %r9d
jg .L39
jmp .L40
.L36:
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
cmpl $2, %eax
je .L71
.L41:
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
cmpl $2, %eax
je .L72
.L42:
movq tailleVecteur(%rip), %r14
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq 76(%rsp), %rsi
leaq 96(%rsp), %rdi
call gettimeofday@PLT
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl %r14d, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 112(%rsp), %rdx
movl $1, %ecx
movq 84(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L43:
call cudaDeviceSynchronize@PLT
leaq 76(%rsp), %rsi
leaq 112(%rsp), %rdi
call gettimeofday@PLT
movl $2, %ecx
movq %r13, %rdx
movq 64(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq tailleVecteur(%rip), %rcx
testq %rcx, %rcx
jle .L44
movl $-1, %r13d
movl $1, %r15d
movl $0, %eax
jmp .L46
.L71:
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L41
.L72:
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L42
.L73:
movq tailleVecteur(%rip), %rcx
movss (%rsp), %xmm0
movl %r12d, %edx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z51__device_stub__Z26rehaussement_contraste_gpuPiS_iflPiS_ifl
jmp .L43
.L45:
addq $1, %rax
cmpq %rcx, %rax
je .L74
.L46:
movl 0(%rbp,%rax,4), %edx
subl %r12d, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
mulss (%rsp), %xmm0
cvttss2sil %xmm0, %edx
cmpl %edx, (%rbx,%rax,4)
je .L45
cmpl $-1, %r13d
cmove %eax, %r13d
movl $0, %r15d
jmp .L45
.L74:
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %r14, %rdx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb %r15b, %r15b
jne .L52
movl %r13d, %edx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L48
.L50:
addq $1, %rbp
cmpq %rbp, tailleVecteur(%rip)
jle .L49
.L51:
movl (%rbx,%rbp,4), %ecx
movq %r13, %rdx
movl $2, %esi
movq 16(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r12d
cmpl $15, %r12d
jne .L50
movq %r14, %rdx
movl $2, %esi
movq 16(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %r12d
jmp .L50
.L49:
leaq .LC30(%rip), %rdx
movl $2, %esi
movq 16(%rsp), %rbx
movq %rbx, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbx, %rdi
call fclose@PLT
movl $0, %edi
call exit@PLT
.L44:
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %r14, %rdx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L52:
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L48:
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdx
subq 96(%rsp), %rdx
imulq $1000000, %rdx, %rdx
addq 120(%rsp), %rdx
subq 104(%rsp), %rdx
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpq $0, tailleVecteur(%rip)
jle .L49
movl $0, %ebp
movl $0, %r12d
leaq .LC29(%rip), %r13
leaq .LC30(%rip), %r14
jmp .L51
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC31:
.string "_Z26rehaussement_contraste_gpuPiS_ifl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _Z26rehaussement_contraste_gpuPiS_ifl(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl tailleVecteur
.bss
.align 8
.type tailleVecteur, @object
.size tailleVecteur, 8
tailleVecteur:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC18:
.long 1132396544
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
#define initTimer struct timeval tv1, tv2; struct timezone tz
#define startTimer gettimeofday(&tv1, &tz)
#define stopTimer gettimeofday(&tv2, &tz)
#define tpsCalcul (tv2.tv_sec-tv1.tv_sec)*1000000L + (tv2.tv_usec-tv1.tv_usec)
#define MAX_DIM_GRID 65535
#define MAX_DIM_BLOCK 1024
#define MAX_CHAINE 100
#define MIN(a, b) (a < b ? a : b)
#define MAX(a, b) (a > b ? a : b)
#define CALLOC(ptr, nr, type) if (!(ptr = (type *) calloc((size_t)(nr), sizeof(type)))) { \
printf("Erreur lors de l'allocation memoire \n") ; \
exit (-1); \
}
#define FOPEN(fich,fichier,sens) if ((fich=fopen(fichier,sens)) == NULL) { \
printf("Probleme d'ouverture du fichier %s\n",fichier); \
exit(-1); \
}
#define MAX_VALEUR 255
#define MIN_VALEUR 0
#define NBPOINTSPARLIGNES 15
#define false 0
#define true 1
#define boolean int
long tailleVecteur ;
/* KERNEL CUDA */
__global__ void rehaussement_contraste_gpu(int *vec, int *res, int min, float coef ,long N) {
long i = (long)blockIdx.x * (long)blockDim.x + (long)threadIdx.x;
res[i] = (vec[i] - min) * coef;
}
void rehaussement_contraste_cpu(int *vec, int *res, int min, float coef ,long N)
{
long i ;
for (i=0 ; i < N ; i ++) {
res[i] = (vec[i] - min) * coef;
}
}
int main(int argc, char *argv[]) {
if (argc < 2) {
printf("Erreur, manque un argument\n");
exit(0);
}
/*========================================================================*/
/* Declaration de variables et allocation memoire */
/*========================================================================*/
int i, j, n;
int LE_MIN = MAX_VALEUR;
int LE_MAX = MIN_VALEUR;
float ETALEMENT = 0.0;
int **image;
int **resultat;
int X, Y, x, y;
int P;
FILE *Src, *Dst;
char SrcFile[MAX_CHAINE];
char DstFile[MAX_CHAINE];
char ligne[MAX_CHAINE];
boolean inverse = false;
char *Chemin;
/*========================================================================*/
/* Recuperation des parametres */
/*========================================================================*/
sscanf(argv[1],"%s", SrcFile);
sprintf(DstFile,"%s.new",SrcFile);
/*========================================================================*/
/* Recuperation de l'endroit ou l'on travail */
/*========================================================================*/
CALLOC(Chemin, MAX_CHAINE, char);
Chemin = getenv("PWD");
printf("Repertoire de travail : %s \n\n",Chemin);
/*========================================================================*/
/* Ouverture des fichiers */
/*========================================================================*/
printf("Operations sur les fichiers\n");
FOPEN(Src, SrcFile, "r");
printf("\t Fichier source ouvert (%s) \n",SrcFile);
FOPEN(Dst, DstFile, "w");
printf("\t Fichier destination ouvert (%s) \n",DstFile);
/*========================================================================*/
/* On effectue la lecture du fichier source */
/*========================================================================*/
printf("\t Lecture entete du fichier source ");
for (i = 0 ; i < 2 ; i++) {
fgets(ligne, MAX_CHAINE, Src);
fprintf(Dst,"%s", ligne);
}
fscanf(Src," %d %d\n",&X, &Y);
fprintf(Dst," %d %d\n", X, Y);
fgets(ligne, MAX_CHAINE, Src); /* Lecture du 255 */
fprintf(Dst,"%s", ligne);
printf(": OK \n");
/*========================================================================*/
/* Allocation memoire pour l'image source et l'image resultat */
/*========================================================================*/
CALLOC(image, Y+1, int *);
CALLOC(resultat, Y+1, int *);
for (i=0;i<Y;i++) {
CALLOC(image[i], X+1, int);
CALLOC(resultat[i], X+1, int);
for (j=0;j<X;j++) {
image[i][j] = 0;
resultat[i][j] = 0;
}
}
printf("\t\t Initialisation de l'image [%d ; %d] : Ok \n", X, Y);
tailleVecteur = X * Y;
x = 0;
y = 0;
/*========================================================================*/
/* Lecture du fichier pour remplir l'image source */
/*========================================================================*/
while (! feof(Src)) {
n = fscanf(Src,"%d",&P);
image[y][x] = P;
LE_MIN = MIN(LE_MIN, P);
LE_MAX = MAX(LE_MAX, P);
x ++;
if (n == EOF || (x == X && y == Y-1)) {
break;
}
if (x == X) {
x = 0 ;
y++;
}
}
fclose(Src);
printf("\t Lecture du fichier image : Ok \n\n");
/*========================================================================*/
/* Calcul du facteur d'etalement */
/*========================================================================*/
if (inverse) {
ETALEMENT = 0.2;
} else {
ETALEMENT = (float)(MAX_VALEUR - MIN_VALEUR) / (float)(LE_MAX - LE_MIN);
}
/*========================================================================*/
/* Code CUDA --> Calcul de chaque nouvelle valeur de pixel */
/*========================================================================*/
long blocksize = 1;
// GPUmode, if 1 -> use cuda & gpu else use cpu
int gpumode = 1;
int *vecteur;
int *resultatContraste;
int *cudaVec;
int *cudaRes;
initTimer;
long size = sizeof(int)*tailleVecteur;
vecteur = (int *)malloc(size);
resultatContraste = (int *)malloc(size);
if (vecteur == NULL) {
printf("Allocation memoire qui pose probleme (vecteur) \n");
}
if (resultatContraste == NULL) {
printf("Allocation memoire qui pose probleme (resultatContraste) \n");
}
// DONE: init vec and res
long i_vec = 0 ;
for (i = 0 ; i < Y ; i++) {
for (j = 0 ; j < X ; j++) {
vecteur[i_vec] = image[i][j];
resultatContraste[i_vec] = 0;
i_vec++;
}
}
if (gpumode==1){
printf("Using gpu\n");
if (cudaMalloc((void **)&cudaVec, size) == cudaErrorMemoryAllocation) {
printf("Allocation memoire qui pose probleme (cudaVec) \n");
}
if (cudaMalloc((void **)&cudaRes, size) == cudaErrorMemoryAllocation) {
printf("Allocation memoire qui pose probleme (cudaRes) \n");
}
long dimBlock = blocksize;
long dimGrid = tailleVecteur/blocksize;
if ((tailleVecteur % blocksize) != 0) {
dimGrid++;
}
int res = cudaMemcpy(&cudaVec[0], &vecteur[0], size, cudaMemcpyHostToDevice);
// printf("Copy CPU -> GPU %d \n",res);
startTimer;
rehaussement_contraste_gpu<<<dimGrid, dimBlock>>>(cudaVec, cudaRes, LE_MIN, ETALEMENT, tailleVecteur);
// DONE: Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
stopTimer;
cudaMemcpy(&resultatContraste[0], &cudaRes[0], size, cudaMemcpyDeviceToHost);
/* Test bon fonctionnement */
bool ok = true;
int indice = -1;
int valtest = -1;
for (i_vec= 0 ; i_vec < tailleVecteur ; i_vec++) {
valtest = (vecteur[i_vec] - LE_MIN) * ETALEMENT;
if (resultatContraste[i_vec] != valtest) {
// printf("Resultat GPU %d Resultat CPU %d \n", resultatContraste[i_vec], valtest);
ok = false;
if (indice ==-1) {
indice = i_vec;
}
}
}
printf("------ ");
printf("dimGrid %ld dimBlock %ld ",dimGrid, dimBlock);
if (ok) {
printf("Resultat ok\n");
} else {
printf("resultatContraste NON ok (%d)\n", indice);
}
cudaFree(cudaVec);
cudaFree(cudaRes);
/*========================================================================*/
/* Fin Code CUDA */
/*========================================================================*/
}
else
{
printf("Using cpu\n");
startTimer;
rehaussement_contraste_cpu(vecteur, resultatContraste, LE_MIN, ETALEMENT, tailleVecteur);
stopTimer;
}
printf("chrono %ld \n", tpsCalcul);
/*========================================================================*/
/* Sauvegarde de l'image dans le fichier resultat */
/*========================================================================*/
n = 0;
long cpt;
for (cpt = 0 ; cpt < tailleVecteur ; cpt++) {
// printf("%d \n", resultatContraste[cpt]);
fprintf(Dst,"%3d ",resultatContraste[cpt]);
n++;
if (n == NBPOINTSPARLIGNES) {
n = 0;
fprintf(Dst, "\n");
}
}
fprintf(Dst,"\n");
fclose(Dst);
/*========================================================================*/
/* Fin du programme principal */
/*========================================================================*/
exit(0);
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
#define initTimer struct timeval tv1, tv2; struct timezone tz
#define startTimer gettimeofday(&tv1, &tz)
#define stopTimer gettimeofday(&tv2, &tz)
#define tpsCalcul (tv2.tv_sec-tv1.tv_sec)*1000000L + (tv2.tv_usec-tv1.tv_usec)
#define MAX_DIM_GRID 65535
#define MAX_DIM_BLOCK 1024
#define MAX_CHAINE 100
#define MIN(a, b) (a < b ? a : b)
#define MAX(a, b) (a > b ? a : b)
#define CALLOC(ptr, nr, type) if (!(ptr = (type *) calloc((size_t)(nr), sizeof(type)))) { \
printf("Erreur lors de l'allocation memoire \n") ; \
exit (-1); \
}
#define FOPEN(fich,fichier,sens) if ((fich=fopen(fichier,sens)) == NULL) { \
printf("Probleme d'ouverture du fichier %s\n",fichier); \
exit(-1); \
}
#define MAX_VALEUR 255
#define MIN_VALEUR 0
#define NBPOINTSPARLIGNES 15
#define false 0
#define true 1
#define boolean int
long tailleVecteur ;
/* KERNEL CUDA */
__global__ void rehaussement_contraste_gpu(int *vec, int *res, int min, float coef ,long N) {
long i = (long)blockIdx.x * (long)blockDim.x + (long)threadIdx.x;
res[i] = (vec[i] - min) * coef;
}
void rehaussement_contraste_cpu(int *vec, int *res, int min, float coef ,long N)
{
long i ;
for (i=0 ; i < N ; i ++) {
res[i] = (vec[i] - min) * coef;
}
}
int main(int argc, char *argv[]) {
if (argc < 2) {
printf("Erreur, manque un argument\n");
exit(0);
}
/*========================================================================*/
/* Declaration de variables et allocation memoire */
/*========================================================================*/
int i, j, n;
int LE_MIN = MAX_VALEUR;
int LE_MAX = MIN_VALEUR;
float ETALEMENT = 0.0;
int **image;
int **resultat;
int X, Y, x, y;
int P;
FILE *Src, *Dst;
char SrcFile[MAX_CHAINE];
char DstFile[MAX_CHAINE];
char ligne[MAX_CHAINE];
boolean inverse = false;
char *Chemin;
/*========================================================================*/
/* Recuperation des parametres */
/*========================================================================*/
sscanf(argv[1],"%s", SrcFile);
sprintf(DstFile,"%s.new",SrcFile);
/*========================================================================*/
/* Recuperation de l'endroit ou l'on travail */
/*========================================================================*/
CALLOC(Chemin, MAX_CHAINE, char);
Chemin = getenv("PWD");
printf("Repertoire de travail : %s \n\n",Chemin);
/*========================================================================*/
/* Ouverture des fichiers */
/*========================================================================*/
printf("Operations sur les fichiers\n");
FOPEN(Src, SrcFile, "r");
printf("\t Fichier source ouvert (%s) \n",SrcFile);
FOPEN(Dst, DstFile, "w");
printf("\t Fichier destination ouvert (%s) \n",DstFile);
/*========================================================================*/
/* On effectue la lecture du fichier source */
/*========================================================================*/
printf("\t Lecture entete du fichier source ");
for (i = 0 ; i < 2 ; i++) {
fgets(ligne, MAX_CHAINE, Src);
fprintf(Dst,"%s", ligne);
}
fscanf(Src," %d %d\n",&X, &Y);
fprintf(Dst," %d %d\n", X, Y);
fgets(ligne, MAX_CHAINE, Src); /* Lecture du 255 */
fprintf(Dst,"%s", ligne);
printf(": OK \n");
/*========================================================================*/
/* Allocation memoire pour l'image source et l'image resultat */
/*========================================================================*/
CALLOC(image, Y+1, int *);
CALLOC(resultat, Y+1, int *);
for (i=0;i<Y;i++) {
CALLOC(image[i], X+1, int);
CALLOC(resultat[i], X+1, int);
for (j=0;j<X;j++) {
image[i][j] = 0;
resultat[i][j] = 0;
}
}
printf("\t\t Initialisation de l'image [%d ; %d] : Ok \n", X, Y);
tailleVecteur = X * Y;
x = 0;
y = 0;
/*========================================================================*/
/* Lecture du fichier pour remplir l'image source */
/*========================================================================*/
while (! feof(Src)) {
n = fscanf(Src,"%d",&P);
image[y][x] = P;
LE_MIN = MIN(LE_MIN, P);
LE_MAX = MAX(LE_MAX, P);
x ++;
if (n == EOF || (x == X && y == Y-1)) {
break;
}
if (x == X) {
x = 0 ;
y++;
}
}
fclose(Src);
printf("\t Lecture du fichier image : Ok \n\n");
/*========================================================================*/
/* Calcul du facteur d'etalement */
/*========================================================================*/
if (inverse) {
ETALEMENT = 0.2;
} else {
ETALEMENT = (float)(MAX_VALEUR - MIN_VALEUR) / (float)(LE_MAX - LE_MIN);
}
/*========================================================================*/
/* Code CUDA --> Calcul de chaque nouvelle valeur de pixel */
/*========================================================================*/
long blocksize = 1;
// GPUmode, if 1 -> use cuda & gpu else use cpu
int gpumode = 1;
int *vecteur;
int *resultatContraste;
int *cudaVec;
int *cudaRes;
initTimer;
long size = sizeof(int)*tailleVecteur;
vecteur = (int *)malloc(size);
resultatContraste = (int *)malloc(size);
if (vecteur == NULL) {
printf("Allocation memoire qui pose probleme (vecteur) \n");
}
if (resultatContraste == NULL) {
printf("Allocation memoire qui pose probleme (resultatContraste) \n");
}
// DONE: init vec and res
long i_vec = 0 ;
for (i = 0 ; i < Y ; i++) {
for (j = 0 ; j < X ; j++) {
vecteur[i_vec] = image[i][j];
resultatContraste[i_vec] = 0;
i_vec++;
}
}
if (gpumode==1){
printf("Using gpu\n");
if (hipMalloc((void **)&cudaVec, size) == hipErrorOutOfMemory) {
printf("Allocation memoire qui pose probleme (cudaVec) \n");
}
if (hipMalloc((void **)&cudaRes, size) == hipErrorOutOfMemory) {
printf("Allocation memoire qui pose probleme (cudaRes) \n");
}
long dimBlock = blocksize;
long dimGrid = tailleVecteur/blocksize;
if ((tailleVecteur % blocksize) != 0) {
dimGrid++;
}
int res = hipMemcpy(&cudaVec[0], &vecteur[0], size, hipMemcpyHostToDevice);
// printf("Copy CPU -> GPU %d \n",res);
startTimer;
rehaussement_contraste_gpu<<<dimGrid, dimBlock>>>(cudaVec, cudaRes, LE_MIN, ETALEMENT, tailleVecteur);
// DONE: Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
stopTimer;
hipMemcpy(&resultatContraste[0], &cudaRes[0], size, hipMemcpyDeviceToHost);
/* Test bon fonctionnement */
bool ok = true;
int indice = -1;
int valtest = -1;
for (i_vec= 0 ; i_vec < tailleVecteur ; i_vec++) {
valtest = (vecteur[i_vec] - LE_MIN) * ETALEMENT;
if (resultatContraste[i_vec] != valtest) {
// printf("Resultat GPU %d Resultat CPU %d \n", resultatContraste[i_vec], valtest);
ok = false;
if (indice ==-1) {
indice = i_vec;
}
}
}
printf("------ ");
printf("dimGrid %ld dimBlock %ld ",dimGrid, dimBlock);
if (ok) {
printf("Resultat ok\n");
} else {
printf("resultatContraste NON ok (%d)\n", indice);
}
hipFree(cudaVec);
hipFree(cudaRes);
/*========================================================================*/
/* Fin Code CUDA */
/*========================================================================*/
}
else
{
printf("Using cpu\n");
startTimer;
rehaussement_contraste_cpu(vecteur, resultatContraste, LE_MIN, ETALEMENT, tailleVecteur);
stopTimer;
}
printf("chrono %ld \n", tpsCalcul);
/*========================================================================*/
/* Sauvegarde de l'image dans le fichier resultat */
/*========================================================================*/
n = 0;
long cpt;
for (cpt = 0 ; cpt < tailleVecteur ; cpt++) {
// printf("%d \n", resultatContraste[cpt]);
fprintf(Dst,"%3d ",resultatContraste[cpt]);
n++;
if (n == NBPOINTSPARLIGNES) {
n = 0;
fprintf(Dst, "\n");
}
}
fprintf(Dst,"\n");
fclose(Dst);
/*========================================================================*/
/* Fin du programme principal */
/*========================================================================*/
exit(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
#define initTimer struct timeval tv1, tv2; struct timezone tz
#define startTimer gettimeofday(&tv1, &tz)
#define stopTimer gettimeofday(&tv2, &tz)
#define tpsCalcul (tv2.tv_sec-tv1.tv_sec)*1000000L + (tv2.tv_usec-tv1.tv_usec)
#define MAX_DIM_GRID 65535
#define MAX_DIM_BLOCK 1024
#define MAX_CHAINE 100
#define MIN(a, b) (a < b ? a : b)
#define MAX(a, b) (a > b ? a : b)
#define CALLOC(ptr, nr, type) if (!(ptr = (type *) calloc((size_t)(nr), sizeof(type)))) { \
printf("Erreur lors de l'allocation memoire \n") ; \
exit (-1); \
}
#define FOPEN(fich,fichier,sens) if ((fich=fopen(fichier,sens)) == NULL) { \
printf("Probleme d'ouverture du fichier %s\n",fichier); \
exit(-1); \
}
#define MAX_VALEUR 255
#define MIN_VALEUR 0
#define NBPOINTSPARLIGNES 15
#define false 0
#define true 1
#define boolean int
long tailleVecteur ;
/* KERNEL CUDA */
__global__ void rehaussement_contraste_gpu(int *vec, int *res, int min, float coef ,long N) {
long i = (long)blockIdx.x * (long)blockDim.x + (long)threadIdx.x;
res[i] = (vec[i] - min) * coef;
}
void rehaussement_contraste_cpu(int *vec, int *res, int min, float coef ,long N)
{
long i ;
for (i=0 ; i < N ; i ++) {
res[i] = (vec[i] - min) * coef;
}
}
int main(int argc, char *argv[]) {
if (argc < 2) {
printf("Erreur, manque un argument\n");
exit(0);
}
/*========================================================================*/
/* Declaration de variables et allocation memoire */
/*========================================================================*/
int i, j, n;
int LE_MIN = MAX_VALEUR;
int LE_MAX = MIN_VALEUR;
float ETALEMENT = 0.0;
int **image;
int **resultat;
int X, Y, x, y;
int P;
FILE *Src, *Dst;
char SrcFile[MAX_CHAINE];
char DstFile[MAX_CHAINE];
char ligne[MAX_CHAINE];
boolean inverse = false;
char *Chemin;
/*========================================================================*/
/* Recuperation des parametres */
/*========================================================================*/
sscanf(argv[1],"%s", SrcFile);
sprintf(DstFile,"%s.new",SrcFile);
/*========================================================================*/
/* Recuperation de l'endroit ou l'on travail */
/*========================================================================*/
CALLOC(Chemin, MAX_CHAINE, char);
Chemin = getenv("PWD");
printf("Repertoire de travail : %s \n\n",Chemin);
/*========================================================================*/
/* Ouverture des fichiers */
/*========================================================================*/
printf("Operations sur les fichiers\n");
FOPEN(Src, SrcFile, "r");
printf("\t Fichier source ouvert (%s) \n",SrcFile);
FOPEN(Dst, DstFile, "w");
printf("\t Fichier destination ouvert (%s) \n",DstFile);
/*========================================================================*/
/* On effectue la lecture du fichier source */
/*========================================================================*/
printf("\t Lecture entete du fichier source ");
for (i = 0 ; i < 2 ; i++) {
fgets(ligne, MAX_CHAINE, Src);
fprintf(Dst,"%s", ligne);
}
fscanf(Src," %d %d\n",&X, &Y);
fprintf(Dst," %d %d\n", X, Y);
fgets(ligne, MAX_CHAINE, Src); /* Lecture du 255 */
fprintf(Dst,"%s", ligne);
printf(": OK \n");
/*========================================================================*/
/* Allocation memoire pour l'image source et l'image resultat */
/*========================================================================*/
CALLOC(image, Y+1, int *);
CALLOC(resultat, Y+1, int *);
for (i=0;i<Y;i++) {
CALLOC(image[i], X+1, int);
CALLOC(resultat[i], X+1, int);
for (j=0;j<X;j++) {
image[i][j] = 0;
resultat[i][j] = 0;
}
}
printf("\t\t Initialisation de l'image [%d ; %d] : Ok \n", X, Y);
tailleVecteur = X * Y;
x = 0;
y = 0;
/*========================================================================*/
/* Lecture du fichier pour remplir l'image source */
/*========================================================================*/
while (! feof(Src)) {
n = fscanf(Src,"%d",&P);
image[y][x] = P;
LE_MIN = MIN(LE_MIN, P);
LE_MAX = MAX(LE_MAX, P);
x ++;
if (n == EOF || (x == X && y == Y-1)) {
break;
}
if (x == X) {
x = 0 ;
y++;
}
}
fclose(Src);
printf("\t Lecture du fichier image : Ok \n\n");
/*========================================================================*/
/* Calcul du facteur d'etalement */
/*========================================================================*/
if (inverse) {
ETALEMENT = 0.2;
} else {
ETALEMENT = (float)(MAX_VALEUR - MIN_VALEUR) / (float)(LE_MAX - LE_MIN);
}
/*========================================================================*/
/* Code CUDA --> Calcul de chaque nouvelle valeur de pixel */
/*========================================================================*/
long blocksize = 1;
// GPUmode, if 1 -> use cuda & gpu else use cpu
int gpumode = 1;
int *vecteur;
int *resultatContraste;
int *cudaVec;
int *cudaRes;
initTimer;
long size = sizeof(int)*tailleVecteur;
vecteur = (int *)malloc(size);
resultatContraste = (int *)malloc(size);
if (vecteur == NULL) {
printf("Allocation memoire qui pose probleme (vecteur) \n");
}
if (resultatContraste == NULL) {
printf("Allocation memoire qui pose probleme (resultatContraste) \n");
}
// DONE: init vec and res
long i_vec = 0 ;
for (i = 0 ; i < Y ; i++) {
for (j = 0 ; j < X ; j++) {
vecteur[i_vec] = image[i][j];
resultatContraste[i_vec] = 0;
i_vec++;
}
}
if (gpumode==1){
printf("Using gpu\n");
if (hipMalloc((void **)&cudaVec, size) == hipErrorOutOfMemory) {
printf("Allocation memoire qui pose probleme (cudaVec) \n");
}
if (hipMalloc((void **)&cudaRes, size) == hipErrorOutOfMemory) {
printf("Allocation memoire qui pose probleme (cudaRes) \n");
}
long dimBlock = blocksize;
long dimGrid = tailleVecteur/blocksize;
if ((tailleVecteur % blocksize) != 0) {
dimGrid++;
}
int res = hipMemcpy(&cudaVec[0], &vecteur[0], size, hipMemcpyHostToDevice);
// printf("Copy CPU -> GPU %d \n",res);
startTimer;
rehaussement_contraste_gpu<<<dimGrid, dimBlock>>>(cudaVec, cudaRes, LE_MIN, ETALEMENT, tailleVecteur);
// DONE: Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
stopTimer;
hipMemcpy(&resultatContraste[0], &cudaRes[0], size, hipMemcpyDeviceToHost);
/* Test bon fonctionnement */
bool ok = true;
int indice = -1;
int valtest = -1;
for (i_vec= 0 ; i_vec < tailleVecteur ; i_vec++) {
valtest = (vecteur[i_vec] - LE_MIN) * ETALEMENT;
if (resultatContraste[i_vec] != valtest) {
// printf("Resultat GPU %d Resultat CPU %d \n", resultatContraste[i_vec], valtest);
ok = false;
if (indice ==-1) {
indice = i_vec;
}
}
}
printf("------ ");
printf("dimGrid %ld dimBlock %ld ",dimGrid, dimBlock);
if (ok) {
printf("Resultat ok\n");
} else {
printf("resultatContraste NON ok (%d)\n", indice);
}
hipFree(cudaVec);
hipFree(cudaRes);
/*========================================================================*/
/* Fin Code CUDA */
/*========================================================================*/
}
else
{
printf("Using cpu\n");
startTimer;
rehaussement_contraste_cpu(vecteur, resultatContraste, LE_MIN, ETALEMENT, tailleVecteur);
stopTimer;
}
printf("chrono %ld \n", tpsCalcul);
/*========================================================================*/
/* Sauvegarde de l'image dans le fichier resultat */
/*========================================================================*/
n = 0;
long cpt;
for (cpt = 0 ; cpt < tailleVecteur ; cpt++) {
// printf("%d \n", resultatContraste[cpt]);
fprintf(Dst,"%3d ",resultatContraste[cpt]);
n++;
if (n == NBPOINTSPARLIGNES) {
n = 0;
fprintf(Dst, "\n");
}
}
fprintf(Dst,"\n");
fclose(Dst);
/*========================================================================*/
/* Fin du programme principal */
/*========================================================================*/
exit(0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26rehaussement_contraste_gpuPiS_ifl
.globl _Z26rehaussement_contraste_gpuPiS_ifl
.p2align 8
.type _Z26rehaussement_contraste_gpuPiS_ifl,@function
_Z26rehaussement_contraste_gpuPiS_ifl:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s15, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_subrev_nc_u32_e32 v2, s0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v2, v2
v_mul_f32_e32 v2, s1, v2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26rehaussement_contraste_gpuPiS_ifl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26rehaussement_contraste_gpuPiS_ifl, .Lfunc_end0-_Z26rehaussement_contraste_gpuPiS_ifl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26rehaussement_contraste_gpuPiS_ifl
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26rehaussement_contraste_gpuPiS_ifl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>
#define initTimer struct timeval tv1, tv2; struct timezone tz
#define startTimer gettimeofday(&tv1, &tz)
#define stopTimer gettimeofday(&tv2, &tz)
#define tpsCalcul (tv2.tv_sec-tv1.tv_sec)*1000000L + (tv2.tv_usec-tv1.tv_usec)
#define MAX_DIM_GRID 65535
#define MAX_DIM_BLOCK 1024
#define MAX_CHAINE 100
#define MIN(a, b) (a < b ? a : b)
#define MAX(a, b) (a > b ? a : b)
#define CALLOC(ptr, nr, type) if (!(ptr = (type *) calloc((size_t)(nr), sizeof(type)))) { \
printf("Erreur lors de l'allocation memoire \n") ; \
exit (-1); \
}
#define FOPEN(fich,fichier,sens) if ((fich=fopen(fichier,sens)) == NULL) { \
printf("Probleme d'ouverture du fichier %s\n",fichier); \
exit(-1); \
}
#define MAX_VALEUR 255
#define MIN_VALEUR 0
#define NBPOINTSPARLIGNES 15
#define false 0
#define true 1
#define boolean int
long tailleVecteur ;
/* KERNEL CUDA */
__global__ void rehaussement_contraste_gpu(int *vec, int *res, int min, float coef ,long N) {
long i = (long)blockIdx.x * (long)blockDim.x + (long)threadIdx.x;
res[i] = (vec[i] - min) * coef;
}
void rehaussement_contraste_cpu(int *vec, int *res, int min, float coef ,long N)
{
long i ;
for (i=0 ; i < N ; i ++) {
res[i] = (vec[i] - min) * coef;
}
}
int main(int argc, char *argv[]) {
if (argc < 2) {
printf("Erreur, manque un argument\n");
exit(0);
}
/*========================================================================*/
/* Declaration de variables et allocation memoire */
/*========================================================================*/
int i, j, n;
int LE_MIN = MAX_VALEUR;
int LE_MAX = MIN_VALEUR;
float ETALEMENT = 0.0;
int **image;
int **resultat;
int X, Y, x, y;
int P;
FILE *Src, *Dst;
char SrcFile[MAX_CHAINE];
char DstFile[MAX_CHAINE];
char ligne[MAX_CHAINE];
boolean inverse = false;
char *Chemin;
/*========================================================================*/
/* Recuperation des parametres */
/*========================================================================*/
sscanf(argv[1],"%s", SrcFile);
sprintf(DstFile,"%s.new",SrcFile);
/*========================================================================*/
/* Recuperation de l'endroit ou l'on travail */
/*========================================================================*/
CALLOC(Chemin, MAX_CHAINE, char);
Chemin = getenv("PWD");
printf("Repertoire de travail : %s \n\n",Chemin);
/*========================================================================*/
/* Ouverture des fichiers */
/*========================================================================*/
printf("Operations sur les fichiers\n");
FOPEN(Src, SrcFile, "r");
printf("\t Fichier source ouvert (%s) \n",SrcFile);
FOPEN(Dst, DstFile, "w");
printf("\t Fichier destination ouvert (%s) \n",DstFile);
/*========================================================================*/
/* On effectue la lecture du fichier source */
/*========================================================================*/
printf("\t Lecture entete du fichier source ");
for (i = 0 ; i < 2 ; i++) {
fgets(ligne, MAX_CHAINE, Src);
fprintf(Dst,"%s", ligne);
}
fscanf(Src," %d %d\n",&X, &Y);
fprintf(Dst," %d %d\n", X, Y);
fgets(ligne, MAX_CHAINE, Src); /* Lecture du 255 */
fprintf(Dst,"%s", ligne);
printf(": OK \n");
/*========================================================================*/
/* Allocation memoire pour l'image source et l'image resultat */
/*========================================================================*/
CALLOC(image, Y+1, int *);
CALLOC(resultat, Y+1, int *);
for (i=0;i<Y;i++) {
CALLOC(image[i], X+1, int);
CALLOC(resultat[i], X+1, int);
for (j=0;j<X;j++) {
image[i][j] = 0;
resultat[i][j] = 0;
}
}
printf("\t\t Initialisation de l'image [%d ; %d] : Ok \n", X, Y);
tailleVecteur = X * Y;
x = 0;
y = 0;
/*========================================================================*/
/* Lecture du fichier pour remplir l'image source */
/*========================================================================*/
while (! feof(Src)) {
n = fscanf(Src,"%d",&P);
image[y][x] = P;
LE_MIN = MIN(LE_MIN, P);
LE_MAX = MAX(LE_MAX, P);
x ++;
if (n == EOF || (x == X && y == Y-1)) {
break;
}
if (x == X) {
x = 0 ;
y++;
}
}
fclose(Src);
printf("\t Lecture du fichier image : Ok \n\n");
/*========================================================================*/
/* Calcul du facteur d'etalement */
/*========================================================================*/
if (inverse) {
ETALEMENT = 0.2;
} else {
ETALEMENT = (float)(MAX_VALEUR - MIN_VALEUR) / (float)(LE_MAX - LE_MIN);
}
/*========================================================================*/
/* Code CUDA --> Calcul de chaque nouvelle valeur de pixel */
/*========================================================================*/
long blocksize = 1;
// GPUmode, if 1 -> use cuda & gpu else use cpu
int gpumode = 1;
int *vecteur;
int *resultatContraste;
int *cudaVec;
int *cudaRes;
initTimer;
long size = sizeof(int)*tailleVecteur;
vecteur = (int *)malloc(size);
resultatContraste = (int *)malloc(size);
if (vecteur == NULL) {
printf("Allocation memoire qui pose probleme (vecteur) \n");
}
if (resultatContraste == NULL) {
printf("Allocation memoire qui pose probleme (resultatContraste) \n");
}
// DONE: init vec and res
long i_vec = 0 ;
for (i = 0 ; i < Y ; i++) {
for (j = 0 ; j < X ; j++) {
vecteur[i_vec] = image[i][j];
resultatContraste[i_vec] = 0;
i_vec++;
}
}
if (gpumode==1){
printf("Using gpu\n");
if (hipMalloc((void **)&cudaVec, size) == hipErrorOutOfMemory) {
printf("Allocation memoire qui pose probleme (cudaVec) \n");
}
if (hipMalloc((void **)&cudaRes, size) == hipErrorOutOfMemory) {
printf("Allocation memoire qui pose probleme (cudaRes) \n");
}
long dimBlock = blocksize;
long dimGrid = tailleVecteur/blocksize;
if ((tailleVecteur % blocksize) != 0) {
dimGrid++;
}
int res = hipMemcpy(&cudaVec[0], &vecteur[0], size, hipMemcpyHostToDevice);
// printf("Copy CPU -> GPU %d \n",res);
startTimer;
rehaussement_contraste_gpu<<<dimGrid, dimBlock>>>(cudaVec, cudaRes, LE_MIN, ETALEMENT, tailleVecteur);
// DONE: Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
stopTimer;
hipMemcpy(&resultatContraste[0], &cudaRes[0], size, hipMemcpyDeviceToHost);
/* Test bon fonctionnement */
bool ok = true;
int indice = -1;
int valtest = -1;
for (i_vec= 0 ; i_vec < tailleVecteur ; i_vec++) {
valtest = (vecteur[i_vec] - LE_MIN) * ETALEMENT;
if (resultatContraste[i_vec] != valtest) {
// printf("Resultat GPU %d Resultat CPU %d \n", resultatContraste[i_vec], valtest);
ok = false;
if (indice ==-1) {
indice = i_vec;
}
}
}
printf("------ ");
printf("dimGrid %ld dimBlock %ld ",dimGrid, dimBlock);
if (ok) {
printf("Resultat ok\n");
} else {
printf("resultatContraste NON ok (%d)\n", indice);
}
hipFree(cudaVec);
hipFree(cudaRes);
/*========================================================================*/
/* Fin Code CUDA */
/*========================================================================*/
}
else
{
printf("Using cpu\n");
startTimer;
rehaussement_contraste_cpu(vecteur, resultatContraste, LE_MIN, ETALEMENT, tailleVecteur);
stopTimer;
}
printf("chrono %ld \n", tpsCalcul);
/*========================================================================*/
/* Sauvegarde de l'image dans le fichier resultat */
/*========================================================================*/
n = 0;
long cpt;
for (cpt = 0 ; cpt < tailleVecteur ; cpt++) {
// printf("%d \n", resultatContraste[cpt]);
fprintf(Dst,"%3d ",resultatContraste[cpt]);
n++;
if (n == NBPOINTSPARLIGNES) {
n = 0;
fprintf(Dst, "\n");
}
}
fprintf(Dst,"\n");
fclose(Dst);
/*========================================================================*/
/* Fin du programme principal */
/*========================================================================*/
exit(0);
} | .text
.file "CodeCuda.hip"
.globl _Z41__device_stub__rehaussement_contraste_gpuPiS_ifl # -- Begin function _Z41__device_stub__rehaussement_contraste_gpuPiS_ifl
.p2align 4, 0x90
.type _Z41__device_stub__rehaussement_contraste_gpuPiS_ifl,@function
_Z41__device_stub__rehaussement_contraste_gpuPiS_ifl: # @_Z41__device_stub__rehaussement_contraste_gpuPiS_ifl
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movss %xmm0, (%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26rehaussement_contraste_gpuPiS_ifl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z41__device_stub__rehaussement_contraste_gpuPiS_ifl, .Lfunc_end0-_Z41__device_stub__rehaussement_contraste_gpuPiS_ifl
.cfi_endproc
# -- End function
.globl _Z26rehaussement_contraste_cpuPiS_ifl # -- Begin function _Z26rehaussement_contraste_cpuPiS_ifl
.p2align 4, 0x90
.type _Z26rehaussement_contraste_cpuPiS_ifl,@function
_Z26rehaussement_contraste_cpuPiS_ifl: # @_Z26rehaussement_contraste_cpuPiS_ifl
.cfi_startproc
# %bb.0:
testq %rcx, %rcx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdi,%rax,4), %r8d
subl %edx, %r8d
xorps %xmm1, %xmm1
cvtsi2ss %r8d, %xmm1
mulss %xmm0, %xmm1
cvttss2si %xmm1, %r8d
movl %r8d, (%rsi,%rax,4)
incq %rax
cmpq %rax, %rcx
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z26rehaussement_contraste_cpuPiS_ifl, .Lfunc_end1-_Z26rehaussement_contraste_cpuPiS_ifl
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x437f0000 # float 255
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $424, %rsp # imm = 0x1A8
.cfi_def_cfa_offset 480
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $1, %edi
jg .LBB2_1
# %bb.52:
movl $.Lstr.13, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.LBB2_1:
movq 8(%rsi), %rdi
leaq 208(%rsp), %rbx
movl $.L.str.1, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_sscanf
leaq 96(%rsp), %rdi
movl $.L.str.2, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq sprintf
movl $.L.str.4, %edi
callq getenv
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.7, %esi
movq %rbx, %rdi
callq fopen
testq %rax, %rax
jne .LBB2_4
# %bb.2:
leaq 208(%rsp), %rsi
jmp .LBB2_3
.LBB2_4:
movq %rax, %r14
leaq 208(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
leaq 96(%rsp), %rdi
movl $.L.str.10, %esi
callq fopen
testq %rax, %rax
jne .LBB2_6
# %bb.5:
leaq 96(%rsp), %rsi
.LBB2_3:
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.LBB2_6:
movq %rax, %r12
leaq 96(%rsp), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl $1, %ebx
leaq 320(%rsp), %r15
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $100, %esi
movq %r14, %rdx
callq fgets
movq %r15, %rdi
movq %r12, %rsi
callq fputs@PLT
decl %ebx
je .LBB2_7
# %bb.8:
leaq 4(%rsp), %rdx
movq %rsp, %rcx
movl $.L.str.13, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 4(%rsp), %edx
movl (%rsp), %ecx
movl $.L.str.13, %esi
movq %r12, %rdi
xorl %eax, %eax
callq fprintf
leaq 320(%rsp), %r15
movq %r15, %rdi
movl $100, %esi
movq %r14, %rdx
callq fgets
movq %r15, %rdi
movq %r12, %rsi
callq fputs@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movslq (%rsp), %rdi
incq %rdi
movl $8, %esi
callq calloc
testq %rax, %rax
jne .LBB2_9
.LBB2_53:
movl $.Lstr.11, %edi
callq puts@PLT
movl $-1, %edi
callq exit
.LBB2_9: # %.preheader162
movq %rax, %rbx
movq %r12, 48(%rsp) # 8-byte Spill
movl (%rsp), %r12d
testl %r12d, %r12d
jle .LBB2_15
# %bb.10: # %.lr.ph167
movl 4(%rsp), %r15d
movslq %r15d, %r13
incq %r13
movq %r15, %rax
shlq $2, %rax
movq %rax, 8(%rsp) # 8-byte Spill
xorl %ebp, %ebp
jmp .LBB2_11
.p2align 4, 0x90
.LBB2_14: # %._crit_edge
# in Loop: Header=BB2_11 Depth=1
incq %rbp
cmpq %rbp, %r12
je .LBB2_15
.LBB2_11: # =>This Inner Loop Header: Depth=1
movl $4, %esi
movq %r13, %rdi
callq calloc
movq %rax, (%rbx,%rbp,8)
testq %rax, %rax
je .LBB2_53
# %bb.12: # %.preheader161
# in Loop: Header=BB2_11 Depth=1
testl %r15d, %r15d
jle .LBB2_14
# %bb.13: # %.lr.ph.preheader
# in Loop: Header=BB2_11 Depth=1
movq %rax, %rdi
xorl %esi, %esi
movq 8(%rsp), %rdx # 8-byte Reload
callq memset@PLT
jmp .LBB2_14
.LBB2_15: # %._crit_edge168
movq %rbx, 8(%rsp) # 8-byte Spill
movl 4(%rsp), %esi
xorl %r13d, %r13d
movl $.L.str.15, %edi
movl %r12d, %edx
xorl %eax, %eax
callq printf
movslq 4(%rsp), %rax
movslq (%rsp), %rcx
imulq %rax, %rcx
movq %rcx, tailleVecteur(%rip)
movq %r14, %rdi
callq feof
movl $255, %ebp
testl %eax, %eax
jne .LBB2_21
# %bb.16: # %.lr.ph175.preheader
xorl %r13d, %r13d
xorl %r15d, %r15d
xorl %r12d, %r12d
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_20: # in Loop: Header=BB2_17 Depth=1
xorl %ecx, %ecx
cmpl %eax, %r15d
sete %cl
addl %ecx, %r12d
movq %r14, %rdi
callq feof
movl %ebx, %r15d
testl %eax, %eax
jne .LBB2_21
.LBB2_17: # %.lr.ph175
# =>This Inner Loop Header: Depth=1
movl %r13d, %ebx
movl $.L.str.16, %esi
movq %r14, %rdi
leaq 20(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 20(%rsp), %ecx
movl %r12d, %edx
movq 8(%rsp), %rsi # 8-byte Reload
movq (%rsi,%rdx,8), %rdx
movslq %r15d, %rsi
movl %ecx, (%rdx,%rsi,4)
movl 20(%rsp), %r13d
cmpl %r13d, %ebp
cmovgel %r13d, %ebp
cmpl %r13d, %ebx
cmovgl %ebx, %r13d
cmpl $-1, %eax
je .LBB2_21
# %bb.18: # in Loop: Header=BB2_17 Depth=1
incl %r15d
movl 4(%rsp), %eax
movl %r15d, %ebx
cmpl %eax, %r15d
jne .LBB2_20
# %bb.19: # in Loop: Header=BB2_17 Depth=1
movl (%rsp), %ecx
decl %ecx
xorl %ebx, %ebx
cmpl %ecx, %r12d
jne .LBB2_20
.LBB2_21: # %._crit_edge176
movq %r14, %rdi
callq fclose
movl $.Lstr.4, %edi
callq puts@PLT
movq tailleVecteur(%rip), %r15
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq %r15, %rdi
callq malloc
movq %rax, %r14
testq %r12, %r12
jne .LBB2_23
# %bb.22:
movl $.Lstr.5, %edi
callq puts@PLT
.LBB2_23:
testq %r14, %r14
movq 8(%rsp), %rbx # 8-byte Reload
jne .LBB2_25
# %bb.24:
movl $.Lstr.6, %edi
callq puts@PLT
.LBB2_25:
movl (%rsp), %eax
testl %eax, %eax
jle .LBB2_32
# %bb.26: # %.preheader.lr.ph
movl 4(%rsp), %ecx
xorl %edx, %edx
xorl %esi, %esi
jmp .LBB2_27
.p2align 4, 0x90
.LBB2_30: # %._crit_edge188.loopexit
# in Loop: Header=BB2_27 Depth=1
addq %r9, %rsi
.LBB2_31: # %._crit_edge188
# in Loop: Header=BB2_27 Depth=1
incq %rdx
cmpq %rax, %rdx
je .LBB2_32
.LBB2_27: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_29 Depth 2
testl %ecx, %ecx
jle .LBB2_31
# %bb.28: # %.lr.ph187
# in Loop: Header=BB2_27 Depth=1
movq (%rbx,%rdx,8), %rdi
leaq (%r12,%rsi,4), %r8
leaq (%r14,%rsi,4), %r10
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_29: # Parent Loop BB2_27 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rdi,%r9,4), %r11d
movl %r11d, (%r8,%r9,4)
movl $0, (%r10,%r9,4)
incq %r9
cmpq %r9, %rcx
jne .LBB2_29
jmp .LBB2_30
.LBB2_32: # %._crit_edge192
subl %ebp, %r13d
movl $.Lstr.7, %edi
callq puts@PLT
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
cmpl $2, %eax
jne .LBB2_34
# %bb.33:
movl $.Lstr.8, %edi
callq puts@PLT
.LBB2_34:
cvtsi2ss %r13d, %xmm0
movss %xmm0, 44(%rsp) # 4-byte Spill
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 8(%rsp) # 4-byte Spill
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
cmpl $2, %eax
jne .LBB2_36
# %bb.35:
movl $.Lstr.9, %edi
callq puts@PLT
.LBB2_36:
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss 44(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 8(%rsp) # 4-byte Spill
movq tailleVecteur(%rip), %rbx
movq 32(%rsp), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 80(%rsp), %rdi
leaq 56(%rsp), %rsi
callq gettimeofday
movl %ebx, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_38
# %bb.37:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movq tailleVecteur(%rip), %rcx
movl %ebp, %edx
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq _Z41__device_stub__rehaussement_contraste_gpuPiS_ifl
.LBB2_38:
callq hipDeviceSynchronize
leaq 64(%rsp), %rdi
leaq 56(%rsp), %rsi
callq gettimeofday
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq tailleVecteur(%rip), %rax
xorl %r15d, %r15d
testq %rax, %rax
jle .LBB2_39
# %bb.40: # %.lr.ph197.preheader
movb $1, %cl
movl $-1, %r13d
xorl %edx, %edx
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_41: # %.lr.ph197
# =>This Inner Loop Header: Depth=1
movl %r13d, %esi
movl (%r12,%rdx,4), %edi
subl %ebp, %edi
xorps %xmm0, %xmm0
cvtsi2ss %edi, %xmm0
mulss %xmm1, %xmm0
cvttss2si %xmm0, %edi
cmpl $-1, %r13d
movl %edx, %r13d
cmovnel %esi, %r13d
cmpl %edi, (%r14,%rdx,4)
movzbl %cl, %ecx
cmovnel %r15d, %ecx
cmovel %esi, %r13d
incq %rdx
cmpq %rdx, %rax
jne .LBB2_41
# %bb.42: # %._crit_edge198.loopexit
testb $1, %cl
sete %r15b
jmp .LBB2_43
.LBB2_39:
movl $-1, %r13d
.LBB2_43: # %._crit_edge198
movl $.L.str.23, %edi
xorl %eax, %eax
callq printf
movl $.L.str.24, %edi
movl $1, %edx
movq %rbx, %rsi
xorl %eax, %eax
callq printf
testb %r15b, %r15b
movq 48(%rsp), %rbx # 8-byte Reload
je .LBB2_44
# %bb.45:
movl $.L.str.26, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
jmp .LBB2_46
.LBB2_44:
movl $.Lstr.10, %edi
callq puts@PLT
.LBB2_46:
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rax
movq 72(%rsp), %rsi
subq 80(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 88(%rsp), %rsi
addq %rax, %rsi
movl $.L.str.28, %edi
xorl %eax, %eax
callq printf
cmpq $0, tailleVecteur(%rip)
jle .LBB2_51
# %bb.47: # %.lr.ph204.preheader
xorl %r15d, %r15d
xorl %ebp, %ebp
jmp .LBB2_48
.p2align 4, 0x90
.LBB2_50: # in Loop: Header=BB2_48 Depth=1
incq %r15
cmpq tailleVecteur(%rip), %r15
jge .LBB2_51
.LBB2_48: # %.lr.ph204
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %edx
movl $.L.str.29, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
incl %ebp
cmpl $15, %ebp
jne .LBB2_50
# %bb.49: # in Loop: Header=BB2_48 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
xorl %ebp, %ebp
jmp .LBB2_50
.LBB2_51: # %._crit_edge205
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
movq %rbx, %rdi
callq fclose
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26rehaussement_contraste_gpuPiS_ifl, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type tailleVecteur,@object # @tailleVecteur
.bss
.globl tailleVecteur
.p2align 3, 0x0
tailleVecteur:
.quad 0 # 0x0
.size tailleVecteur, 8
.type _Z26rehaussement_contraste_gpuPiS_ifl,@object # @_Z26rehaussement_contraste_gpuPiS_ifl
.section .rodata,"a",@progbits
.globl _Z26rehaussement_contraste_gpuPiS_ifl
.p2align 3, 0x0
_Z26rehaussement_contraste_gpuPiS_ifl:
.quad _Z41__device_stub__rehaussement_contraste_gpuPiS_ifl
.size _Z26rehaussement_contraste_gpuPiS_ifl, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%s"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s.new"
.size .L.str.2, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "PWD"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Repertoire de travail : %s \n\n"
.size .L.str.5, 30
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "r"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Probleme d'ouverture du fichier %s\n"
.size .L.str.8, 36
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\t Fichier source ouvert (%s) \n"
.size .L.str.9, 31
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "w"
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\t Fichier destination ouvert (%s) \n"
.size .L.str.11, 36
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\t Lecture entete du fichier source "
.size .L.str.12, 36
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " %d %d\n"
.size .L.str.13, 8
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "\t\t Initialisation de l'image [%d
.size .L.str.15, 46
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "%d"
.size .L.str.16, 3
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "------ "
.size .L.str.23, 8
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "dimGrid %ld dimBlock %ld "
.size .L.str.24, 26
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "resultatContraste NON ok (%d)\n"
.size .L.str.26, 31
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "chrono %ld \n"
.size .L.str.28, 13
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz "%3d "
.size .L.str.29, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z26rehaussement_contraste_gpuPiS_ifl"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Operations sur les fichiers"
.size .Lstr, 28
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz ": OK "
.size .Lstr.1, 6
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\t Lecture du fichier image : Ok \n"
.size .Lstr.4, 34
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Allocation memoire qui pose probleme (vecteur) "
.size .Lstr.5, 48
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Allocation memoire qui pose probleme (resultatContraste) "
.size .Lstr.6, 58
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "Using gpu"
.size .Lstr.7, 10
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "Allocation memoire qui pose probleme (cudaVec) "
.size .Lstr.8, 48
.type .Lstr.9,@object # @str.9
.Lstr.9:
.asciz "Allocation memoire qui pose probleme (cudaRes) "
.size .Lstr.9, 48
.type .Lstr.10,@object # @str.10
.Lstr.10:
.asciz "Resultat ok"
.size .Lstr.10, 12
.type .Lstr.11,@object # @str.11
.Lstr.11:
.asciz "Erreur lors de l'allocation memoire "
.size .Lstr.11, 37
.type .Lstr.13,@object # @str.13
.Lstr.13:
.asciz "Erreur, manque un argument"
.size .Lstr.13, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__rehaussement_contraste_gpuPiS_ifl
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26rehaussement_contraste_gpuPiS_ifl
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26rehaussement_contraste_gpuPiS_ifl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e240000002500 */
/*0050*/ IMAD.WIDE.U32 R2, R5, c[0x0][0x0], R2 ; /* 0x0000000005027a25 */
/* 0x001fc800078e0002 */
/*0060*/ IMAD.SHL.U32 R4, R2.reuse, 0x4, RZ ; /* 0x0000000402047824 */
/* 0x040fe200078e00ff */
/*0070*/ SHF.L.U64.HI R5, R2, 0x2, R3 ; /* 0x0000000202057819 */
/* 0x000fc80000010203 */
/*0080*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*0090*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590005037a10 */
/* 0x000fca00007fe4ff */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R5, R5, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0005057a10 */
/* 0x000fe400007fe4ff */
/*00d0*/ IADD3 R0, R2, -c[0x0][0x170], RZ ; /* 0x80005c0002007a10 */
/* 0x004fcc0007ffe0ff */
/*00e0*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x000e240000201400 */
/*00f0*/ FMUL R6, R0, c[0x0][0x174] ; /* 0x00005d0000067a20 */
/* 0x001fcc0000400000 */
/*0100*/ F2I.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000e24000020f100 */
/*0110*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26rehaussement_contraste_gpuPiS_ifl
.globl _Z26rehaussement_contraste_gpuPiS_ifl
.p2align 8
.type _Z26rehaussement_contraste_gpuPiS_ifl,@function
_Z26rehaussement_contraste_gpuPiS_ifl:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s15, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_subrev_nc_u32_e32 v2, s0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v2, v2
v_mul_f32_e32 v2, s1, v2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26rehaussement_contraste_gpuPiS_ifl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26rehaussement_contraste_gpuPiS_ifl, .Lfunc_end0-_Z26rehaussement_contraste_gpuPiS_ifl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26rehaussement_contraste_gpuPiS_ifl
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26rehaussement_contraste_gpuPiS_ifl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018c3e7_00000000-6_CodeCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26rehaussement_contraste_cpuPiS_ifl
.type _Z26rehaussement_contraste_cpuPiS_ifl, @function
_Z26rehaussement_contraste_cpuPiS_ifl:
.LFB2057:
.cfi_startproc
endbr64
testq %rcx, %rcx
jle .L3
movl $0, %eax
.L5:
movl (%rdi,%rax,4), %r8d
subl %edx, %r8d
pxor %xmm1, %xmm1
cvtsi2ssl %r8d, %xmm1
mulss %xmm0, %xmm1
cvttss2sil %xmm1, %r8d
movl %r8d, (%rsi,%rax,4)
addq $1, %rax
cmpq %rax, %rcx
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z26rehaussement_contraste_cpuPiS_ifl, .-_Z26rehaussement_contraste_cpuPiS_ifl
.globl _Z51__device_stub__Z26rehaussement_contraste_gpuPiS_iflPiS_ifl
.type _Z51__device_stub__Z26rehaussement_contraste_gpuPiS_iflPiS_ifl, @function
_Z51__device_stub__Z26rehaussement_contraste_gpuPiS_iflPiS_ifl:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26rehaussement_contraste_gpuPiS_ifl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z51__device_stub__Z26rehaussement_contraste_gpuPiS_iflPiS_ifl, .-_Z51__device_stub__Z26rehaussement_contraste_gpuPiS_iflPiS_ifl
.globl _Z26rehaussement_contraste_gpuPiS_ifl
.type _Z26rehaussement_contraste_gpuPiS_ifl, @function
_Z26rehaussement_contraste_gpuPiS_ifl:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z26rehaussement_contraste_gpuPiS_iflPiS_ifl
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z26rehaussement_contraste_gpuPiS_ifl, .-_Z26rehaussement_contraste_gpuPiS_ifl
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Erreur, manque un argument\n"
.LC1:
.string "%s"
.LC2:
.string "%s.new"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Erreur lors de l'allocation memoire \n"
.section .rodata.str1.1
.LC4:
.string "PWD"
.LC5:
.string "Repertoire de travail : %s \n\n"
.LC6:
.string "Operations sur les fichiers\n"
.LC7:
.string "r"
.section .rodata.str1.8
.align 8
.LC8:
.string "Probleme d'ouverture du fichier %s\n"
.align 8
.LC9:
.string "\t Fichier source ouvert (%s) \n"
.section .rodata.str1.1
.LC10:
.string "w"
.section .rodata.str1.8
.align 8
.LC11:
.string "\t Fichier destination ouvert (%s) \n"
.align 8
.LC12:
.string "\t Lecture entete du fichier source "
.section .rodata.str1.1
.LC13:
.string " %d %d\n"
.LC14:
.string ": OK \n"
.section .rodata.str1.8
.align 8
.LC15:
.string "\t\t Initialisation de l'image [%d ; %d] : Ok \n"
.section .rodata.str1.1
.LC16:
.string "%d"
.section .rodata.str1.8
.align 8
.LC17:
.string "\t Lecture du fichier image : Ok \n\n"
.align 8
.LC19:
.string "Allocation memoire qui pose probleme (vecteur) \n"
.align 8
.LC20:
.string "Allocation memoire qui pose probleme (resultatContraste) \n"
.section .rodata.str1.1
.LC21:
.string "Using gpu\n"
.section .rodata.str1.8
.align 8
.LC22:
.string "Allocation memoire qui pose probleme (cudaVec) \n"
.align 8
.LC23:
.string "Allocation memoire qui pose probleme (cudaRes) \n"
.section .rodata.str1.1
.LC24:
.string "------ "
.LC25:
.string "dimGrid %ld dimBlock %ld "
.LC26:
.string "Resultat ok\n"
.section .rodata.str1.8
.align 8
.LC27:
.string "resultatContraste NON ok (%d)\n"
.section .rodata.str1.1
.LC28:
.string "chrono %ld \n"
.LC29:
.string "%3d "
.LC30:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $472, %rsp
.cfi_def_cfa_offset 528
movq %fs:40, %rax
movq %rax, 456(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L62
leaq 128(%rsp), %rbx
movq 8(%rsi), %rdi
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 240(%rsp), %rdi
movq %rbx, %r8
leaq .LC2(%rip), %rcx
movl $100, %edx
movl $2, %esi
movl $0, %eax
call __sprintf_chk@PLT
movl $1, %esi
movl $100, %edi
call calloc@PLT
testq %rax, %rax
je .L63
leaq .LC4(%rip), %rdi
call getenv@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 128(%rsp), %rdi
leaq .LC7(%rip), %rsi
call fopen@PLT
movq %rax, %r15
testq %rax, %rax
je .L64
leaq 128(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 240(%rsp), %rdi
leaq .LC10(%rip), %rsi
call fopen@PLT
movq %rax, 16(%rsp)
testq %rax, %rax
je .L65
leaq 240(%rsp), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 352(%rsp), %rbx
movq %r15, %rcx
movl $100, %edx
movl $100, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %rbx, %rcx
leaq .LC1(%rip), %rbp
movq %rbp, %rdx
movl $2, %esi
movq 16(%rsp), %r14
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r15, %rcx
movl $100, %edx
movl $100, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %rbx, %rcx
movq %rbp, %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq 48(%rsp), %rcx
leaq 44(%rsp), %rdx
leaq .LC13(%rip), %r12
movq %r12, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 48(%rsp), %r8d
movl 44(%rsp), %ecx
movq %r12, %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r15, %rcx
movl $100, %edx
movl $100, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %rbx, %rcx
movq %rbp, %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 48(%rsp), %eax
movl %eax, 28(%rsp)
leal 1(%rax), %ebx
movslq %ebx, %rbx
movl $8, %esi
movq %rbx, %rdi
call calloc@PLT
movq %rax, 8(%rsp)
testq %rax, %rax
je .L66
movl $8, %esi
movq %rbx, %rdi
call calloc@PLT
movq %rax, %r14
testq %rax, %rax
je .L21
cmpl $0, 28(%rsp)
jle .L23
movq 8(%rsp), %rdi
movq %rdi, %r12
movslq 28(%rsp), %rax
leaq (%rdi,%rax,8), %rax
movq %rax, (%rsp)
jmp .L29
.L62:
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L63:
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L64:
leaq 128(%rsp), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L65:
leaq 240(%rsp), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L66:
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L21:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L67:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L25:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L27:
addq $8, %r12
addq $8, %r14
movq (%rsp), %rax
cmpq %rax, %r12
je .L23
.L29:
movl 44(%rsp), %r13d
leal 1(%r13), %ebp
movslq %ebp, %rbp
movl $4, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, %rbx
movq %rax, (%r12)
testq %rax, %rax
je .L67
movl $4, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, (%r14)
testq %rax, %rax
je .L25
movslq %r13d, %rcx
salq $2, %rcx
movl $0, %edx
testl %r13d, %r13d
jle .L27
.L28:
movl $0, (%rbx,%rdx)
movl $0, (%rax,%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L28
jmp .L27
.L23:
movl 28(%rsp), %ecx
movl 44(%rsp), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 44(%rsp), %eax
imull 48(%rsp), %eax
cltq
movq %rax, tailleVecteur(%rip)
movl $0, %r14d
movl $0, %ebp
movl $0, %r13d
movl $255, %r12d
jmp .L30
.L68:
addl $1, %r14d
movl %ebx, %ebp
.L30:
movq %r15, %rdi
call feof@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L31
leaq 52(%rsp), %rdx
leaq .LC16(%rip), %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl %eax, %ecx
movl 52(%rsp), %eax
movslq %r14d, %rdx
movslq %ebp, %rsi
movq 8(%rsp), %rdi
movq (%rdi,%rdx,8), %rdx
movl %eax, (%rdx,%rsi,4)
cmpl %eax, %r12d
cmovg %eax, %r12d
cmpl %eax, %r13d
cmovl %eax, %r13d
addl $1, %ebp
cmpl $-1, %ecx
je .L31
cmpl %ebp, 44(%rsp)
jne .L30
movl 48(%rsp), %eax
subl $1, %eax
cmpl %r14d, %eax
jne .L68
.L31:
movq %r15, %rdi
call fclose@PLT
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subl %r12d, %r13d
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
movss .LC18(%rip), %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%rsp)
movq tailleVecteur(%rip), %rax
leaq 0(,%rax,4), %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
testq %rbp, %rbp
je .L69
.L34:
testq %rbx, %rbx
je .L70
.L35:
movl 48(%rsp), %eax
testl %eax, %eax
jle .L36
movl 44(%rsp), %r9d
movq 8(%rsp), %rdi
movq %rdi, %r8
cltq
leaq (%rdi,%rax,8), %r10
movl $0, %edi
movslq %r9d, %r14
leal -1(%r9), %r11d
jmp .L37
.L69:
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L34
.L70:
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L35
.L39:
leaq (%r14,%rdi), %rsi
movq %rdi, %rdx
negq %rdx
movq (%r8), %rax
leaq (%rax,%rdx,4), %rcx
movq %rdi, %rax
.L38:
movl (%rcx,%rax,4), %edx
movl %edx, 0(%rbp,%rax,4)
movl $0, (%rbx,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L38
leaq 1(%rdi,%r11), %rdi
.L40:
addq $8, %r8
cmpq %r10, %r8
je .L36
.L37:
testl %r9d, %r9d
jg .L39
jmp .L40
.L36:
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
cmpl $2, %eax
je .L71
.L41:
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
cmpl $2, %eax
je .L72
.L42:
movq tailleVecteur(%rip), %r14
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq 76(%rsp), %rsi
leaq 96(%rsp), %rdi
call gettimeofday@PLT
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl %r14d, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 112(%rsp), %rdx
movl $1, %ecx
movq 84(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L43:
call cudaDeviceSynchronize@PLT
leaq 76(%rsp), %rsi
leaq 112(%rsp), %rdi
call gettimeofday@PLT
movl $2, %ecx
movq %r13, %rdx
movq 64(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq tailleVecteur(%rip), %rcx
testq %rcx, %rcx
jle .L44
movl $-1, %r13d
movl $1, %r15d
movl $0, %eax
jmp .L46
.L71:
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L41
.L72:
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L42
.L73:
movq tailleVecteur(%rip), %rcx
movss (%rsp), %xmm0
movl %r12d, %edx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z51__device_stub__Z26rehaussement_contraste_gpuPiS_iflPiS_ifl
jmp .L43
.L45:
addq $1, %rax
cmpq %rcx, %rax
je .L74
.L46:
movl 0(%rbp,%rax,4), %edx
subl %r12d, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
mulss (%rsp), %xmm0
cvttss2sil %xmm0, %edx
cmpl %edx, (%rbx,%rax,4)
je .L45
cmpl $-1, %r13d
cmove %eax, %r13d
movl $0, %r15d
jmp .L45
.L74:
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %r14, %rdx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb %r15b, %r15b
jne .L52
movl %r13d, %edx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L48
.L50:
addq $1, %rbp
cmpq %rbp, tailleVecteur(%rip)
jle .L49
.L51:
movl (%rbx,%rbp,4), %ecx
movq %r13, %rdx
movl $2, %esi
movq 16(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r12d
cmpl $15, %r12d
jne .L50
movq %r14, %rdx
movl $2, %esi
movq 16(%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %r12d
jmp .L50
.L49:
leaq .LC30(%rip), %rdx
movl $2, %esi
movq 16(%rsp), %rbx
movq %rbx, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbx, %rdi
call fclose@PLT
movl $0, %edi
call exit@PLT
.L44:
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %r14, %rdx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L52:
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L48:
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdx
subq 96(%rsp), %rdx
imulq $1000000, %rdx, %rdx
addq 120(%rsp), %rdx
subq 104(%rsp), %rdx
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpq $0, tailleVecteur(%rip)
jle .L49
movl $0, %ebp
movl $0, %r12d
leaq .LC29(%rip), %r13
leaq .LC30(%rip), %r14
jmp .L51
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC31:
.string "_Z26rehaussement_contraste_gpuPiS_ifl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _Z26rehaussement_contraste_gpuPiS_ifl(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl tailleVecteur
.bss
.align 8
.type tailleVecteur, @object
.size tailleVecteur, 8
tailleVecteur:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC18:
.long 1132396544
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CodeCuda.hip"
.globl _Z41__device_stub__rehaussement_contraste_gpuPiS_ifl # -- Begin function _Z41__device_stub__rehaussement_contraste_gpuPiS_ifl
.p2align 4, 0x90
.type _Z41__device_stub__rehaussement_contraste_gpuPiS_ifl,@function
_Z41__device_stub__rehaussement_contraste_gpuPiS_ifl: # @_Z41__device_stub__rehaussement_contraste_gpuPiS_ifl
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movss %xmm0, (%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26rehaussement_contraste_gpuPiS_ifl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z41__device_stub__rehaussement_contraste_gpuPiS_ifl, .Lfunc_end0-_Z41__device_stub__rehaussement_contraste_gpuPiS_ifl
.cfi_endproc
# -- End function
.globl _Z26rehaussement_contraste_cpuPiS_ifl # -- Begin function _Z26rehaussement_contraste_cpuPiS_ifl
.p2align 4, 0x90
.type _Z26rehaussement_contraste_cpuPiS_ifl,@function
_Z26rehaussement_contraste_cpuPiS_ifl: # @_Z26rehaussement_contraste_cpuPiS_ifl
.cfi_startproc
# %bb.0:
testq %rcx, %rcx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdi,%rax,4), %r8d
subl %edx, %r8d
xorps %xmm1, %xmm1
cvtsi2ss %r8d, %xmm1
mulss %xmm0, %xmm1
cvttss2si %xmm1, %r8d
movl %r8d, (%rsi,%rax,4)
incq %rax
cmpq %rax, %rcx
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z26rehaussement_contraste_cpuPiS_ifl, .Lfunc_end1-_Z26rehaussement_contraste_cpuPiS_ifl
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x437f0000 # float 255
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $424, %rsp # imm = 0x1A8
.cfi_def_cfa_offset 480
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $1, %edi
jg .LBB2_1
# %bb.52:
movl $.Lstr.13, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.LBB2_1:
movq 8(%rsi), %rdi
leaq 208(%rsp), %rbx
movl $.L.str.1, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_sscanf
leaq 96(%rsp), %rdi
movl $.L.str.2, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq sprintf
movl $.L.str.4, %edi
callq getenv
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.7, %esi
movq %rbx, %rdi
callq fopen
testq %rax, %rax
jne .LBB2_4
# %bb.2:
leaq 208(%rsp), %rsi
jmp .LBB2_3
.LBB2_4:
movq %rax, %r14
leaq 208(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
leaq 96(%rsp), %rdi
movl $.L.str.10, %esi
callq fopen
testq %rax, %rax
jne .LBB2_6
# %bb.5:
leaq 96(%rsp), %rsi
.LBB2_3:
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.LBB2_6:
movq %rax, %r12
leaq 96(%rsp), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl $1, %ebx
leaq 320(%rsp), %r15
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $100, %esi
movq %r14, %rdx
callq fgets
movq %r15, %rdi
movq %r12, %rsi
callq fputs@PLT
decl %ebx
je .LBB2_7
# %bb.8:
leaq 4(%rsp), %rdx
movq %rsp, %rcx
movl $.L.str.13, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 4(%rsp), %edx
movl (%rsp), %ecx
movl $.L.str.13, %esi
movq %r12, %rdi
xorl %eax, %eax
callq fprintf
leaq 320(%rsp), %r15
movq %r15, %rdi
movl $100, %esi
movq %r14, %rdx
callq fgets
movq %r15, %rdi
movq %r12, %rsi
callq fputs@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movslq (%rsp), %rdi
incq %rdi
movl $8, %esi
callq calloc
testq %rax, %rax
jne .LBB2_9
.LBB2_53:
movl $.Lstr.11, %edi
callq puts@PLT
movl $-1, %edi
callq exit
.LBB2_9: # %.preheader162
movq %rax, %rbx
movq %r12, 48(%rsp) # 8-byte Spill
movl (%rsp), %r12d
testl %r12d, %r12d
jle .LBB2_15
# %bb.10: # %.lr.ph167
movl 4(%rsp), %r15d
movslq %r15d, %r13
incq %r13
movq %r15, %rax
shlq $2, %rax
movq %rax, 8(%rsp) # 8-byte Spill
xorl %ebp, %ebp
jmp .LBB2_11
.p2align 4, 0x90
.LBB2_14: # %._crit_edge
# in Loop: Header=BB2_11 Depth=1
incq %rbp
cmpq %rbp, %r12
je .LBB2_15
.LBB2_11: # =>This Inner Loop Header: Depth=1
movl $4, %esi
movq %r13, %rdi
callq calloc
movq %rax, (%rbx,%rbp,8)
testq %rax, %rax
je .LBB2_53
# %bb.12: # %.preheader161
# in Loop: Header=BB2_11 Depth=1
testl %r15d, %r15d
jle .LBB2_14
# %bb.13: # %.lr.ph.preheader
# in Loop: Header=BB2_11 Depth=1
movq %rax, %rdi
xorl %esi, %esi
movq 8(%rsp), %rdx # 8-byte Reload
callq memset@PLT
jmp .LBB2_14
.LBB2_15: # %._crit_edge168
movq %rbx, 8(%rsp) # 8-byte Spill
movl 4(%rsp), %esi
xorl %r13d, %r13d
movl $.L.str.15, %edi
movl %r12d, %edx
xorl %eax, %eax
callq printf
movslq 4(%rsp), %rax
movslq (%rsp), %rcx
imulq %rax, %rcx
movq %rcx, tailleVecteur(%rip)
movq %r14, %rdi
callq feof
movl $255, %ebp
testl %eax, %eax
jne .LBB2_21
# %bb.16: # %.lr.ph175.preheader
xorl %r13d, %r13d
xorl %r15d, %r15d
xorl %r12d, %r12d
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_20: # in Loop: Header=BB2_17 Depth=1
xorl %ecx, %ecx
cmpl %eax, %r15d
sete %cl
addl %ecx, %r12d
movq %r14, %rdi
callq feof
movl %ebx, %r15d
testl %eax, %eax
jne .LBB2_21
.LBB2_17: # %.lr.ph175
# =>This Inner Loop Header: Depth=1
movl %r13d, %ebx
movl $.L.str.16, %esi
movq %r14, %rdi
leaq 20(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 20(%rsp), %ecx
movl %r12d, %edx
movq 8(%rsp), %rsi # 8-byte Reload
movq (%rsi,%rdx,8), %rdx
movslq %r15d, %rsi
movl %ecx, (%rdx,%rsi,4)
movl 20(%rsp), %r13d
cmpl %r13d, %ebp
cmovgel %r13d, %ebp
cmpl %r13d, %ebx
cmovgl %ebx, %r13d
cmpl $-1, %eax
je .LBB2_21
# %bb.18: # in Loop: Header=BB2_17 Depth=1
incl %r15d
movl 4(%rsp), %eax
movl %r15d, %ebx
cmpl %eax, %r15d
jne .LBB2_20
# %bb.19: # in Loop: Header=BB2_17 Depth=1
movl (%rsp), %ecx
decl %ecx
xorl %ebx, %ebx
cmpl %ecx, %r12d
jne .LBB2_20
.LBB2_21: # %._crit_edge176
movq %r14, %rdi
callq fclose
movl $.Lstr.4, %edi
callq puts@PLT
movq tailleVecteur(%rip), %r15
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq %r15, %rdi
callq malloc
movq %rax, %r14
testq %r12, %r12
jne .LBB2_23
# %bb.22:
movl $.Lstr.5, %edi
callq puts@PLT
.LBB2_23:
testq %r14, %r14
movq 8(%rsp), %rbx # 8-byte Reload
jne .LBB2_25
# %bb.24:
movl $.Lstr.6, %edi
callq puts@PLT
.LBB2_25:
movl (%rsp), %eax
testl %eax, %eax
jle .LBB2_32
# %bb.26: # %.preheader.lr.ph
movl 4(%rsp), %ecx
xorl %edx, %edx
xorl %esi, %esi
jmp .LBB2_27
.p2align 4, 0x90
.LBB2_30: # %._crit_edge188.loopexit
# in Loop: Header=BB2_27 Depth=1
addq %r9, %rsi
.LBB2_31: # %._crit_edge188
# in Loop: Header=BB2_27 Depth=1
incq %rdx
cmpq %rax, %rdx
je .LBB2_32
.LBB2_27: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_29 Depth 2
testl %ecx, %ecx
jle .LBB2_31
# %bb.28: # %.lr.ph187
# in Loop: Header=BB2_27 Depth=1
movq (%rbx,%rdx,8), %rdi
leaq (%r12,%rsi,4), %r8
leaq (%r14,%rsi,4), %r10
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_29: # Parent Loop BB2_27 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rdi,%r9,4), %r11d
movl %r11d, (%r8,%r9,4)
movl $0, (%r10,%r9,4)
incq %r9
cmpq %r9, %rcx
jne .LBB2_29
jmp .LBB2_30
.LBB2_32: # %._crit_edge192
subl %ebp, %r13d
movl $.Lstr.7, %edi
callq puts@PLT
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
cmpl $2, %eax
jne .LBB2_34
# %bb.33:
movl $.Lstr.8, %edi
callq puts@PLT
.LBB2_34:
cvtsi2ss %r13d, %xmm0
movss %xmm0, 44(%rsp) # 4-byte Spill
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 8(%rsp) # 4-byte Spill
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
cmpl $2, %eax
jne .LBB2_36
# %bb.35:
movl $.Lstr.9, %edi
callq puts@PLT
.LBB2_36:
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss 44(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 8(%rsp) # 4-byte Spill
movq tailleVecteur(%rip), %rbx
movq 32(%rsp), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 80(%rsp), %rdi
leaq 56(%rsp), %rsi
callq gettimeofday
movl %ebx, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_38
# %bb.37:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movq tailleVecteur(%rip), %rcx
movl %ebp, %edx
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq _Z41__device_stub__rehaussement_contraste_gpuPiS_ifl
.LBB2_38:
callq hipDeviceSynchronize
leaq 64(%rsp), %rdi
leaq 56(%rsp), %rsi
callq gettimeofday
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq tailleVecteur(%rip), %rax
xorl %r15d, %r15d
testq %rax, %rax
jle .LBB2_39
# %bb.40: # %.lr.ph197.preheader
movb $1, %cl
movl $-1, %r13d
xorl %edx, %edx
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_41: # %.lr.ph197
# =>This Inner Loop Header: Depth=1
movl %r13d, %esi
movl (%r12,%rdx,4), %edi
subl %ebp, %edi
xorps %xmm0, %xmm0
cvtsi2ss %edi, %xmm0
mulss %xmm1, %xmm0
cvttss2si %xmm0, %edi
cmpl $-1, %r13d
movl %edx, %r13d
cmovnel %esi, %r13d
cmpl %edi, (%r14,%rdx,4)
movzbl %cl, %ecx
cmovnel %r15d, %ecx
cmovel %esi, %r13d
incq %rdx
cmpq %rdx, %rax
jne .LBB2_41
# %bb.42: # %._crit_edge198.loopexit
testb $1, %cl
sete %r15b
jmp .LBB2_43
.LBB2_39:
movl $-1, %r13d
.LBB2_43: # %._crit_edge198
movl $.L.str.23, %edi
xorl %eax, %eax
callq printf
movl $.L.str.24, %edi
movl $1, %edx
movq %rbx, %rsi
xorl %eax, %eax
callq printf
testb %r15b, %r15b
movq 48(%rsp), %rbx # 8-byte Reload
je .LBB2_44
# %bb.45:
movl $.L.str.26, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
jmp .LBB2_46
.LBB2_44:
movl $.Lstr.10, %edi
callq puts@PLT
.LBB2_46:
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rax
movq 72(%rsp), %rsi
subq 80(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 88(%rsp), %rsi
addq %rax, %rsi
movl $.L.str.28, %edi
xorl %eax, %eax
callq printf
cmpq $0, tailleVecteur(%rip)
jle .LBB2_51
# %bb.47: # %.lr.ph204.preheader
xorl %r15d, %r15d
xorl %ebp, %ebp
jmp .LBB2_48
.p2align 4, 0x90
.LBB2_50: # in Loop: Header=BB2_48 Depth=1
incq %r15
cmpq tailleVecteur(%rip), %r15
jge .LBB2_51
.LBB2_48: # %.lr.ph204
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %edx
movl $.L.str.29, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
incl %ebp
cmpl $15, %ebp
jne .LBB2_50
# %bb.49: # in Loop: Header=BB2_48 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
xorl %ebp, %ebp
jmp .LBB2_50
.LBB2_51: # %._crit_edge205
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
movq %rbx, %rdi
callq fclose
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26rehaussement_contraste_gpuPiS_ifl, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type tailleVecteur,@object # @tailleVecteur
.bss
.globl tailleVecteur
.p2align 3, 0x0
tailleVecteur:
.quad 0 # 0x0
.size tailleVecteur, 8
.type _Z26rehaussement_contraste_gpuPiS_ifl,@object # @_Z26rehaussement_contraste_gpuPiS_ifl
.section .rodata,"a",@progbits
.globl _Z26rehaussement_contraste_gpuPiS_ifl
.p2align 3, 0x0
_Z26rehaussement_contraste_gpuPiS_ifl:
.quad _Z41__device_stub__rehaussement_contraste_gpuPiS_ifl
.size _Z26rehaussement_contraste_gpuPiS_ifl, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%s"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s.new"
.size .L.str.2, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "PWD"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Repertoire de travail : %s \n\n"
.size .L.str.5, 30
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "r"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Probleme d'ouverture du fichier %s\n"
.size .L.str.8, 36
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\t Fichier source ouvert (%s) \n"
.size .L.str.9, 31
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "w"
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\t Fichier destination ouvert (%s) \n"
.size .L.str.11, 36
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\t Lecture entete du fichier source "
.size .L.str.12, 36
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " %d %d\n"
.size .L.str.13, 8
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "\t\t Initialisation de l'image [%d
.size .L.str.15, 46
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "%d"
.size .L.str.16, 3
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "------ "
.size .L.str.23, 8
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "dimGrid %ld dimBlock %ld "
.size .L.str.24, 26
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "resultatContraste NON ok (%d)\n"
.size .L.str.26, 31
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "chrono %ld \n"
.size .L.str.28, 13
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz "%3d "
.size .L.str.29, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z26rehaussement_contraste_gpuPiS_ifl"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Operations sur les fichiers"
.size .Lstr, 28
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz ": OK "
.size .Lstr.1, 6
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\t Lecture du fichier image : Ok \n"
.size .Lstr.4, 34
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Allocation memoire qui pose probleme (vecteur) "
.size .Lstr.5, 48
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Allocation memoire qui pose probleme (resultatContraste) "
.size .Lstr.6, 58
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "Using gpu"
.size .Lstr.7, 10
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "Allocation memoire qui pose probleme (cudaVec) "
.size .Lstr.8, 48
.type .Lstr.9,@object # @str.9
.Lstr.9:
.asciz "Allocation memoire qui pose probleme (cudaRes) "
.size .Lstr.9, 48
.type .Lstr.10,@object # @str.10
.Lstr.10:
.asciz "Resultat ok"
.size .Lstr.10, 12
.type .Lstr.11,@object # @str.11
.Lstr.11:
.asciz "Erreur lors de l'allocation memoire "
.size .Lstr.11, 37
.type .Lstr.13,@object # @str.13
.Lstr.13:
.asciz "Erreur, manque un argument"
.size .Lstr.13, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__rehaussement_contraste_gpuPiS_ifl
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26rehaussement_contraste_gpuPiS_ifl
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define UMUL(a, b) ( (a) * (b) )
#define UMAD(a, b, c) ( UMUL((a), (b)) + (c) )
typedef unsigned int uint;
typedef unsigned short ushort;
typedef unsigned char uchar;
#define SHARED_MEMORY_SIZE 49152
#define MERGE_THREADBLOCK_SIZE 128
static uint *d_PartialHistograms;
/*
* Function that maps value to bin in range 0 inclusive to binCOunt exclusive
*/
__global__ void clearHistogram(uint *d_Histogram, uint binCount)
{
//clear histogram
for (uint bin = UMAD(blockIdx.x, blockDim.x, threadIdx.x); bin < binCount; bin += UMUL(blockDim.x, gridDim.x))
d_Histogram[bin] = 0;
} | code for sm_80
Function : _Z14clearHistogramPjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0005 */
/*00a0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fe200078e0200 */
/*00b0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e8000c101904 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*00d0*/ @!P0 BRA 0x90 ; /* 0xffffffb000008947 */
/* 0x001fea000383ffff */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define UMUL(a, b) ( (a) * (b) )
#define UMAD(a, b, c) ( UMUL((a), (b)) + (c) )
typedef unsigned int uint;
typedef unsigned short ushort;
typedef unsigned char uchar;
#define SHARED_MEMORY_SIZE 49152
#define MERGE_THREADBLOCK_SIZE 128
static uint *d_PartialHistograms;
/*
* Function that maps value to bin in range 0 inclusive to binCOunt exclusive
*/
__global__ void clearHistogram(uint *d_Histogram, uint binCount)
{
//clear histogram
for (uint bin = UMAD(blockIdx.x, blockDim.x, threadIdx.x); bin < binCount; bin += UMUL(blockDim.x, gridDim.x))
d_Histogram[bin] = 0;
} | .file "tmpxft_00059cc0_00000000-6_clearHistogram.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z14clearHistogramPjjPjj
.type _Z35__device_stub__Z14clearHistogramPjjPjj, @function
_Z35__device_stub__Z14clearHistogramPjjPjj:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14clearHistogramPjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z14clearHistogramPjjPjj, .-_Z35__device_stub__Z14clearHistogramPjjPjj
.globl _Z14clearHistogramPjj
.type _Z14clearHistogramPjj, @function
_Z14clearHistogramPjj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14clearHistogramPjjPjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14clearHistogramPjj, .-_Z14clearHistogramPjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14clearHistogramPjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14clearHistogramPjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define UMUL(a, b) ( (a) * (b) )
#define UMAD(a, b, c) ( UMUL((a), (b)) + (c) )
typedef unsigned int uint;
typedef unsigned short ushort;
typedef unsigned char uchar;
#define SHARED_MEMORY_SIZE 49152
#define MERGE_THREADBLOCK_SIZE 128
static uint *d_PartialHistograms;
/*
* Function that maps value to bin in range 0 inclusive to binCOunt exclusive
*/
__global__ void clearHistogram(uint *d_Histogram, uint binCount)
{
//clear histogram
for (uint bin = UMAD(blockIdx.x, blockDim.x, threadIdx.x); bin < binCount; bin += UMUL(blockDim.x, gridDim.x))
d_Histogram[bin] = 0;
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define UMUL(a, b) ( (a) * (b) )
#define UMAD(a, b, c) ( UMUL((a), (b)) + (c) )
typedef unsigned int uint;
typedef unsigned short ushort;
typedef unsigned char uchar;
#define SHARED_MEMORY_SIZE 49152
#define MERGE_THREADBLOCK_SIZE 128
static uint *d_PartialHistograms;
/*
* Function that maps value to bin in range 0 inclusive to binCOunt exclusive
*/
__global__ void clearHistogram(uint *d_Histogram, uint binCount)
{
//clear histogram
for (uint bin = UMAD(blockIdx.x, blockDim.x, threadIdx.x); bin < binCount; bin += UMUL(blockDim.x, gridDim.x))
d_Histogram[bin] = 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define UMUL(a, b) ( (a) * (b) )
#define UMAD(a, b, c) ( UMUL((a), (b)) + (c) )
typedef unsigned int uint;
typedef unsigned short ushort;
typedef unsigned char uchar;
#define SHARED_MEMORY_SIZE 49152
#define MERGE_THREADBLOCK_SIZE 128
static uint *d_PartialHistograms;
/*
* Function that maps value to bin in range 0 inclusive to binCOunt exclusive
*/
__global__ void clearHistogram(uint *d_Histogram, uint binCount)
{
//clear histogram
for (uint bin = UMAD(blockIdx.x, blockDim.x, threadIdx.x); bin < binCount; bin += UMUL(blockDim.x, gridDim.x))
d_Histogram[bin] = 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14clearHistogramPjj
.globl _Z14clearHistogramPjj
.p2align 8
.type _Z14clearHistogramPjj,@function
_Z14clearHistogramPjj:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s6, s5
s_mov_b32 s5, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s0, s2, v3
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
s_or_b32 s5, vcc_lo, s5
global_store_b32 v[3:4], v2, off
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14clearHistogramPjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14clearHistogramPjj, .Lfunc_end0-_Z14clearHistogramPjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14clearHistogramPjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14clearHistogramPjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define UMUL(a, b) ( (a) * (b) )
#define UMAD(a, b, c) ( UMUL((a), (b)) + (c) )
typedef unsigned int uint;
typedef unsigned short ushort;
typedef unsigned char uchar;
#define SHARED_MEMORY_SIZE 49152
#define MERGE_THREADBLOCK_SIZE 128
static uint *d_PartialHistograms;
/*
* Function that maps value to bin in range 0 inclusive to binCOunt exclusive
*/
__global__ void clearHistogram(uint *d_Histogram, uint binCount)
{
//clear histogram
for (uint bin = UMAD(blockIdx.x, blockDim.x, threadIdx.x); bin < binCount; bin += UMUL(blockDim.x, gridDim.x))
d_Histogram[bin] = 0;
} | .text
.file "clearHistogram.hip"
.globl _Z29__device_stub__clearHistogramPjj # -- Begin function _Z29__device_stub__clearHistogramPjj
.p2align 4, 0x90
.type _Z29__device_stub__clearHistogramPjj,@function
_Z29__device_stub__clearHistogramPjj: # @_Z29__device_stub__clearHistogramPjj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14clearHistogramPjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__clearHistogramPjj, .Lfunc_end0-_Z29__device_stub__clearHistogramPjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14clearHistogramPjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14clearHistogramPjj,@object # @_Z14clearHistogramPjj
.section .rodata,"a",@progbits
.globl _Z14clearHistogramPjj
.p2align 3, 0x0
_Z14clearHistogramPjj:
.quad _Z29__device_stub__clearHistogramPjj
.size _Z14clearHistogramPjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14clearHistogramPjj"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__clearHistogramPjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14clearHistogramPjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14clearHistogramPjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0005 */
/*00a0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fe200078e0200 */
/*00b0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e8000c101904 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*00d0*/ @!P0 BRA 0x90 ; /* 0xffffffb000008947 */
/* 0x001fea000383ffff */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14clearHistogramPjj
.globl _Z14clearHistogramPjj
.p2align 8
.type _Z14clearHistogramPjj,@function
_Z14clearHistogramPjj:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s6, s5
s_mov_b32 s5, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s0, s2, v3
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
s_or_b32 s5, vcc_lo, s5
global_store_b32 v[3:4], v2, off
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14clearHistogramPjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14clearHistogramPjj, .Lfunc_end0-_Z14clearHistogramPjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14clearHistogramPjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14clearHistogramPjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00059cc0_00000000-6_clearHistogram.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z14clearHistogramPjjPjj
.type _Z35__device_stub__Z14clearHistogramPjjPjj, @function
_Z35__device_stub__Z14clearHistogramPjjPjj:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14clearHistogramPjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z14clearHistogramPjjPjj, .-_Z35__device_stub__Z14clearHistogramPjjPjj
.globl _Z14clearHistogramPjj
.type _Z14clearHistogramPjj, @function
_Z14clearHistogramPjj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14clearHistogramPjjPjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14clearHistogramPjj, .-_Z14clearHistogramPjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14clearHistogramPjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14clearHistogramPjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "clearHistogram.hip"
.globl _Z29__device_stub__clearHistogramPjj # -- Begin function _Z29__device_stub__clearHistogramPjj
.p2align 4, 0x90
.type _Z29__device_stub__clearHistogramPjj,@function
_Z29__device_stub__clearHistogramPjj: # @_Z29__device_stub__clearHistogramPjj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14clearHistogramPjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__clearHistogramPjj, .Lfunc_end0-_Z29__device_stub__clearHistogramPjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14clearHistogramPjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14clearHistogramPjj,@object # @_Z14clearHistogramPjj
.section .rodata,"a",@progbits
.globl _Z14clearHistogramPjj
.p2align 3, 0x0
_Z14clearHistogramPjj:
.quad _Z29__device_stub__clearHistogramPjj
.size _Z14clearHistogramPjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14clearHistogramPjj"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__clearHistogramPjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14clearHistogramPjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void lots_of_double_compute(double *inputs, int N, size_t niters, double *outputs)
{
size_t tid = blockIdx.x * blockDim.x + threadIdx.x;
size_t nthreads = gridDim.x * blockDim.x;
for ( ; tid < N; tid += nthreads)
{
size_t iter;
double val = inputs[tid];
for (iter = 0; iter < niters; iter++)
{
val = (val + 5.0) - 101.0;
val = (val / 3.0) + 102.0;
val = (val + 1.07) - 103.0;
val = (val / 1.037) + 104.0;
val = (val + 3.00) - 105.0;
val = (val / 0.22) + 106.0;
}
outputs[tid] = val;
}
} | .file "tmpxft_0004032f_00000000-6_lots_of_double_compute.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z22lots_of_double_computePdimS_PdimS_
.type _Z46__device_stub__Z22lots_of_double_computePdimS_PdimS_, @function
_Z46__device_stub__Z22lots_of_double_computePdimS_PdimS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22lots_of_double_computePdimS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z22lots_of_double_computePdimS_PdimS_, .-_Z46__device_stub__Z22lots_of_double_computePdimS_PdimS_
.globl _Z22lots_of_double_computePdimS_
.type _Z22lots_of_double_computePdimS_, @function
_Z22lots_of_double_computePdimS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z22lots_of_double_computePdimS_PdimS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22lots_of_double_computePdimS_, .-_Z22lots_of_double_computePdimS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22lots_of_double_computePdimS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22lots_of_double_computePdimS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void lots_of_double_compute(double *inputs, int N, size_t niters, double *outputs)
{
size_t tid = blockIdx.x * blockDim.x + threadIdx.x;
size_t nthreads = gridDim.x * blockDim.x;
for ( ; tid < N; tid += nthreads)
{
size_t iter;
double val = inputs[tid];
for (iter = 0; iter < niters; iter++)
{
val = (val + 5.0) - 101.0;
val = (val / 3.0) + 102.0;
val = (val + 1.07) - 103.0;
val = (val / 1.037) + 104.0;
val = (val + 3.00) - 105.0;
val = (val / 0.22) + 106.0;
}
outputs[tid] = val;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void lots_of_double_compute(double *inputs, int N, size_t niters, double *outputs)
{
size_t tid = blockIdx.x * blockDim.x + threadIdx.x;
size_t nthreads = gridDim.x * blockDim.x;
for ( ; tid < N; tid += nthreads)
{
size_t iter;
double val = inputs[tid];
for (iter = 0; iter < niters; iter++)
{
val = (val + 5.0) - 101.0;
val = (val / 3.0) + 102.0;
val = (val + 1.07) - 103.0;
val = (val / 1.037) + 104.0;
val = (val + 3.00) - 105.0;
val = (val / 0.22) + 106.0;
}
outputs[tid] = val;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void lots_of_double_compute(double *inputs, int N, size_t niters, double *outputs)
{
size_t tid = blockIdx.x * blockDim.x + threadIdx.x;
size_t nthreads = gridDim.x * blockDim.x;
for ( ; tid < N; tid += nthreads)
{
size_t iter;
double val = inputs[tid];
for (iter = 0; iter < niters; iter++)
{
val = (val + 5.0) - 101.0;
val = (val / 3.0) + 102.0;
val = (val + 1.07) - 103.0;
val = (val / 1.037) + 104.0;
val = (val + 3.00) - 105.0;
val = (val / 0.22) + 106.0;
}
outputs[tid] = val;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22lots_of_double_computePdimS_
.globl _Z22lots_of_double_computePdimS_
.p2align 8
.type _Z22lots_of_double_computePdimS_,@function
_Z22lots_of_double_computePdimS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
s_add_u32 s8, s0, 32
s_addc_u32 s9, s1, 0
s_and_b32 s12, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b32 s14, s[8:9], 0x0
s_load_b64 s[8:9], s[0:1], 0x0
s_mov_b32 s16, 0
s_mov_b32 s11, 0x3ff11eb8
s_mov_b32 s10, 0x51eb851f
s_mov_b32 s13, 0x3ff0978d
s_mov_b32 s15, 0x3fcc28f5
s_mov_b32 s19, s16
s_waitcnt lgkmcnt(0)
s_cmp_lg_u64 s[4:5], 0
s_mul_i32 s17, s14, s12
s_cselect_b32 s18, -1, 0
s_mov_b32 s12, 0x4fdf3b64
s_mov_b32 s14, 0xc28f5c29
s_branch .LBB0_3
.LBB0_2:
v_add_co_u32 v1, vcc_lo, v1, s17
v_add_co_ci_u32_e32 v2, vcc_lo, s16, v2, vcc_lo
v_add_co_u32 v3, s0, s6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_waitcnt vmcnt(0)
global_store_b64 v[3:4], v[5:6], off
s_or_b32 s19, vcc_lo, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s19
s_cbranch_execz .LBB0_5
.LBB0_3:
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_mov_b64 s[0:1], s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s18
global_load_b64 v[5:6], v[5:6], off
s_cbranch_vccnz .LBB0_2
.LBB0_4:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_f64 v[5:6], v[5:6], 0x40140000
s_add_u32 s0, s0, -1
s_addc_u32 s1, s1, -1
s_cmp_lg_u64 s[0:1], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], 0xc0594000
v_div_scale_f64 v[7:8], null, 0x40080000, 0x40080000, v[5:6]
v_div_scale_f64 v[13:14], vcc_lo, v[5:6], 0x40080000, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[11:12], v[13:14], v[9:10]
v_fma_f64 v[7:8], -v[7:8], v[11:12], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[11:12]
v_div_fixup_f64 v[5:6], v[7:8], 0x40080000, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], 0x40598000
v_add_f64 v[5:6], v[5:6], s[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], 0xc059c000
v_div_scale_f64 v[7:8], null, s[12:13], s[12:13], v[5:6]
v_div_scale_f64 v[13:14], vcc_lo, v[5:6], s[12:13], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[11:12], v[13:14], v[9:10]
v_fma_f64 v[7:8], -v[7:8], v[11:12], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[11:12]
v_div_fixup_f64 v[5:6], v[7:8], s[12:13], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], 0x405a0000
v_add_f64 v[5:6], v[5:6], 0x40080000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], 0xc05a4000
v_div_scale_f64 v[7:8], null, s[14:15], s[14:15], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_div_scale_f64 v[11:12], vcc_lo, v[5:6], s[14:15], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[13:14], v[11:12], v[9:10]
v_fma_f64 v[7:8], -v[7:8], v[13:14], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[13:14]
v_div_fixup_f64 v[5:6], v[7:8], s[14:15], v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], 0x405a8000
s_cbranch_scc1 .LBB0_4
s_branch .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22lots_of_double_computePdimS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22lots_of_double_computePdimS_, .Lfunc_end0-_Z22lots_of_double_computePdimS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22lots_of_double_computePdimS_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z22lots_of_double_computePdimS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void lots_of_double_compute(double *inputs, int N, size_t niters, double *outputs)
{
size_t tid = blockIdx.x * blockDim.x + threadIdx.x;
size_t nthreads = gridDim.x * blockDim.x;
for ( ; tid < N; tid += nthreads)
{
size_t iter;
double val = inputs[tid];
for (iter = 0; iter < niters; iter++)
{
val = (val + 5.0) - 101.0;
val = (val / 3.0) + 102.0;
val = (val + 1.07) - 103.0;
val = (val / 1.037) + 104.0;
val = (val + 3.00) - 105.0;
val = (val / 0.22) + 106.0;
}
outputs[tid] = val;
}
} | .text
.file "lots_of_double_compute.hip"
.globl _Z37__device_stub__lots_of_double_computePdimS_ # -- Begin function _Z37__device_stub__lots_of_double_computePdimS_
.p2align 4, 0x90
.type _Z37__device_stub__lots_of_double_computePdimS_,@function
_Z37__device_stub__lots_of_double_computePdimS_: # @_Z37__device_stub__lots_of_double_computePdimS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22lots_of_double_computePdimS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__lots_of_double_computePdimS_, .Lfunc_end0-_Z37__device_stub__lots_of_double_computePdimS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22lots_of_double_computePdimS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22lots_of_double_computePdimS_,@object # @_Z22lots_of_double_computePdimS_
.section .rodata,"a",@progbits
.globl _Z22lots_of_double_computePdimS_
.p2align 3, 0x0
_Z22lots_of_double_computePdimS_:
.quad _Z37__device_stub__lots_of_double_computePdimS_
.size _Z22lots_of_double_computePdimS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22lots_of_double_computePdimS_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__lots_of_double_computePdimS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22lots_of_double_computePdimS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004032f_00000000-6_lots_of_double_compute.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z22lots_of_double_computePdimS_PdimS_
.type _Z46__device_stub__Z22lots_of_double_computePdimS_PdimS_, @function
_Z46__device_stub__Z22lots_of_double_computePdimS_PdimS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22lots_of_double_computePdimS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z22lots_of_double_computePdimS_PdimS_, .-_Z46__device_stub__Z22lots_of_double_computePdimS_PdimS_
.globl _Z22lots_of_double_computePdimS_
.type _Z22lots_of_double_computePdimS_, @function
_Z22lots_of_double_computePdimS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z22lots_of_double_computePdimS_PdimS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22lots_of_double_computePdimS_, .-_Z22lots_of_double_computePdimS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22lots_of_double_computePdimS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22lots_of_double_computePdimS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lots_of_double_compute.hip"
.globl _Z37__device_stub__lots_of_double_computePdimS_ # -- Begin function _Z37__device_stub__lots_of_double_computePdimS_
.p2align 4, 0x90
.type _Z37__device_stub__lots_of_double_computePdimS_,@function
_Z37__device_stub__lots_of_double_computePdimS_: # @_Z37__device_stub__lots_of_double_computePdimS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22lots_of_double_computePdimS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__lots_of_double_computePdimS_, .Lfunc_end0-_Z37__device_stub__lots_of_double_computePdimS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22lots_of_double_computePdimS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22lots_of_double_computePdimS_,@object # @_Z22lots_of_double_computePdimS_
.section .rodata,"a",@progbits
.globl _Z22lots_of_double_computePdimS_
.p2align 3, 0x0
_Z22lots_of_double_computePdimS_:
.quad _Z37__device_stub__lots_of_double_computePdimS_
.size _Z22lots_of_double_computePdimS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22lots_of_double_computePdimS_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__lots_of_double_computePdimS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22lots_of_double_computePdimS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdlib>
#include <ctime>
#include "cuda_runtime.h"
#define VEC_SIZE 20000
#define START 1
#define STOP 100
using namespace std;
__global__ void vect_mul(int *arr_a, int *arr_b, int *arr_c)
{
arr_c[threadIdx.x] = arr_a[threadIdx.x] * arr_b[threadIdx.x];
}
int main()
{
int *arr_a, *arr_b, *arr_c, total_sum = 0, dev_count;
int *d_arr_a, *d_arr_b, *d_arr_c;
int size = sizeof(int) * VEC_SIZE;
float working_time = 0;
cudaEvent_t e_start, e_stop;
cudaError_t cuda_status;
cuda_status = cudaEventCreate(&e_start);
if(cuda_status != cudaSuccess)
{
cout << "Can not create cuda event!" << endl;
}
cuda_status = cudaEventCreate(&e_stop);
if(cuda_status != cudaSuccess)
{
cout << "Can not create cuda event!" << endl;
}
arr_a = new int[VEC_SIZE];
arr_b = new int[VEC_SIZE];
arr_c = new int[VEC_SIZE];
cuda_status = cudaMalloc((void**)&d_arr_a, size);
if(cuda_status != cudaSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
cuda_status = cudaMalloc((void**)&d_arr_b, size);
if(cuda_status != cudaSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
cuda_status = cudaMalloc((void**)&d_arr_c, size);
if(cuda_status != cudaSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
srand(time(NULL));
for (int i = 0; i < VEC_SIZE; i++)
{
arr_a[i] = START + rand() % STOP;
arr_b[i] = START + rand() % STOP;
}
cuda_status = cudaMemcpy(d_arr_a, arr_a, VEC_SIZE, cudaMemcpyHostToDevice);
if(cuda_status != cudaSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
cuda_status = cudaMemcpy(d_arr_b, arr_b, VEC_SIZE, cudaMemcpyHostToDevice);
if(cuda_status != cudaSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
cuda_status = cudaGetDeviceCount(&dev_count);
if(cuda_status != cudaSuccess)
{
cout << "Cuda get device count error!" << endl;
goto cuda_error;
}
cuda_status = cudaEventRecord(e_start);
if(cuda_status != cudaSuccess)
{
cout << "Cuda event error while recording!" << endl;
goto cuda_error;
}
vect_mul<<<VEC_SIZE, 1>>>(d_arr_a, d_arr_b, d_arr_c);
cudaDeviceSynchronize();
cuda_status = cudaGetLastError();
if(cuda_status != cudaSuccess)
{
cout << "Kernel error!" << endl;
goto cuda_error;
}
cuda_status = cudaEventRecord(e_stop);
if(cuda_status != cudaSuccess)
{
cout << "Cuda event error while recording!" << endl;
goto cuda_error;
}
cuda_status = cudaMemcpy(arr_c, d_arr_c, VEC_SIZE, cudaMemcpyDeviceToHost);
if(cuda_status != cudaSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
for(int i = 0; i < VEC_SIZE; i++)
total_sum += arr_c[i];
cuda_status = cudaEventSynchronize(e_stop);
if(cuda_status != cudaSuccess)
{
cout << "Cuda event error while synchronizing!" << endl;
goto cuda_error;
}
cuda_status = cudaEventElapsedTime(&working_time, e_start, e_stop);
if(cuda_status != cudaSuccess)
{
cout << "Cuda event error while elapsing!" << endl;
goto cuda_error;
}
cout << "CUDA devices: " << dev_count << endl;
cout << "Result of vectors multiplication is " << total_sum << endl;
cout << "Working time: " << working_time << " ms"<< endl;
cuda_error:
delete[] arr_a;
delete[] arr_b;
delete[] arr_c;
cudaFree(d_arr_a);
cudaFree(d_arr_b);
cudaFree(d_arr_c);
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z8vect_mulPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*0090*/ IMAD R9, R2, R5, RZ ; /* 0x0000000502097224 */
/* 0x004fca00078e02ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdlib>
#include <ctime>
#include "cuda_runtime.h"
#define VEC_SIZE 20000
#define START 1
#define STOP 100
using namespace std;
__global__ void vect_mul(int *arr_a, int *arr_b, int *arr_c)
{
arr_c[threadIdx.x] = arr_a[threadIdx.x] * arr_b[threadIdx.x];
}
int main()
{
int *arr_a, *arr_b, *arr_c, total_sum = 0, dev_count;
int *d_arr_a, *d_arr_b, *d_arr_c;
int size = sizeof(int) * VEC_SIZE;
float working_time = 0;
cudaEvent_t e_start, e_stop;
cudaError_t cuda_status;
cuda_status = cudaEventCreate(&e_start);
if(cuda_status != cudaSuccess)
{
cout << "Can not create cuda event!" << endl;
}
cuda_status = cudaEventCreate(&e_stop);
if(cuda_status != cudaSuccess)
{
cout << "Can not create cuda event!" << endl;
}
arr_a = new int[VEC_SIZE];
arr_b = new int[VEC_SIZE];
arr_c = new int[VEC_SIZE];
cuda_status = cudaMalloc((void**)&d_arr_a, size);
if(cuda_status != cudaSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
cuda_status = cudaMalloc((void**)&d_arr_b, size);
if(cuda_status != cudaSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
cuda_status = cudaMalloc((void**)&d_arr_c, size);
if(cuda_status != cudaSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
srand(time(NULL));
for (int i = 0; i < VEC_SIZE; i++)
{
arr_a[i] = START + rand() % STOP;
arr_b[i] = START + rand() % STOP;
}
cuda_status = cudaMemcpy(d_arr_a, arr_a, VEC_SIZE, cudaMemcpyHostToDevice);
if(cuda_status != cudaSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
cuda_status = cudaMemcpy(d_arr_b, arr_b, VEC_SIZE, cudaMemcpyHostToDevice);
if(cuda_status != cudaSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
cuda_status = cudaGetDeviceCount(&dev_count);
if(cuda_status != cudaSuccess)
{
cout << "Cuda get device count error!" << endl;
goto cuda_error;
}
cuda_status = cudaEventRecord(e_start);
if(cuda_status != cudaSuccess)
{
cout << "Cuda event error while recording!" << endl;
goto cuda_error;
}
vect_mul<<<VEC_SIZE, 1>>>(d_arr_a, d_arr_b, d_arr_c);
cudaDeviceSynchronize();
cuda_status = cudaGetLastError();
if(cuda_status != cudaSuccess)
{
cout << "Kernel error!" << endl;
goto cuda_error;
}
cuda_status = cudaEventRecord(e_stop);
if(cuda_status != cudaSuccess)
{
cout << "Cuda event error while recording!" << endl;
goto cuda_error;
}
cuda_status = cudaMemcpy(arr_c, d_arr_c, VEC_SIZE, cudaMemcpyDeviceToHost);
if(cuda_status != cudaSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
for(int i = 0; i < VEC_SIZE; i++)
total_sum += arr_c[i];
cuda_status = cudaEventSynchronize(e_stop);
if(cuda_status != cudaSuccess)
{
cout << "Cuda event error while synchronizing!" << endl;
goto cuda_error;
}
cuda_status = cudaEventElapsedTime(&working_time, e_start, e_stop);
if(cuda_status != cudaSuccess)
{
cout << "Cuda event error while elapsing!" << endl;
goto cuda_error;
}
cout << "CUDA devices: " << dev_count << endl;
cout << "Result of vectors multiplication is " << total_sum << endl;
cout << "Working time: " << working_time << " ms"<< endl;
cuda_error:
delete[] arr_a;
delete[] arr_b;
delete[] arr_c;
cudaFree(d_arr_a);
cudaFree(d_arr_b);
cudaFree(d_arr_c);
cudaDeviceReset();
return 0;
} | .file "tmpxft_000ecb74_00000000-6_vec_mul_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8vect_mulPiS_S_PiS_S_
.type _Z31__device_stub__Z8vect_mulPiS_S_PiS_S_, @function
_Z31__device_stub__Z8vect_mulPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8vect_mulPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z31__device_stub__Z8vect_mulPiS_S_PiS_S_, .-_Z31__device_stub__Z8vect_mulPiS_S_PiS_S_
.globl _Z8vect_mulPiS_S_
.type _Z8vect_mulPiS_S_, @function
_Z8vect_mulPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8vect_mulPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8vect_mulPiS_S_, .-_Z8vect_mulPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Can not create cuda event!"
.LC2:
.string "Cuda malloc error!"
.LC3:
.string "Cuda memcpy error!"
.LC4:
.string "Cuda get device count error!"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Cuda event error while recording!"
.section .rodata.str1.1
.LC6:
.string "Kernel error!"
.section .rodata.str1.8
.align 8
.LC7:
.string "Cuda event error while synchronizing!"
.align 8
.LC8:
.string "Cuda event error while elapsing!"
.section .rodata.str1.1
.LC9:
.string "CUDA devices: "
.section .rodata.str1.8
.align 8
.LC10:
.string "Result of vectors multiplication is "
.section .rodata.str1.1
.LC11:
.string "Working time: "
.LC12:
.string " ms"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0x00000000, 4(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L34
.L12:
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L35
.L13:
movl $80000, %edi
call _Znam@PLT
movq %rax, %rbp
movl $80000, %edi
call _Znam@PLT
movq %rax, %r12
movl $80000, %edi
call _Znam@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L36
leaq 16(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L37
leaq 24(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L38
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $0, %ebx
.L18:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, 0(%rbp,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, (%r12,%rbx)
addq $4, %rbx
cmpq $80000, %rbx
jne .L18
movl $1, %ecx
movl $20000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L39
movl $1, %ecx
movl $20000, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L40
movq %rsp, %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L41
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L42
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $20000, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L23:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L44
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L45
movl $2, %ecx
movl $20000, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L46
movq %r13, %rax
leaq 80000(%r13), %rcx
movl $0, %edx
.L27:
movl %edx, %ebx
addl (%rax), %ebx
movl %ebx, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L27
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L47
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L48
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %r14
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC10(%rip), %rsi
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC11(%rip), %rsi
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L34:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L12
.L35:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L13
.L36:
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L15:
movq %rbp, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L38:
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L39:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L40:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L41:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L42:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L43:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z8vect_mulPiS_S_PiS_S_
jmp .L23
.L44:
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L45:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L46:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L47:
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L48:
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z8vect_mulPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8vect_mulPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdlib>
#include <ctime>
#include "cuda_runtime.h"
#define VEC_SIZE 20000
#define START 1
#define STOP 100
using namespace std;
__global__ void vect_mul(int *arr_a, int *arr_b, int *arr_c)
{
arr_c[threadIdx.x] = arr_a[threadIdx.x] * arr_b[threadIdx.x];
}
int main()
{
int *arr_a, *arr_b, *arr_c, total_sum = 0, dev_count;
int *d_arr_a, *d_arr_b, *d_arr_c;
int size = sizeof(int) * VEC_SIZE;
float working_time = 0;
cudaEvent_t e_start, e_stop;
cudaError_t cuda_status;
cuda_status = cudaEventCreate(&e_start);
if(cuda_status != cudaSuccess)
{
cout << "Can not create cuda event!" << endl;
}
cuda_status = cudaEventCreate(&e_stop);
if(cuda_status != cudaSuccess)
{
cout << "Can not create cuda event!" << endl;
}
arr_a = new int[VEC_SIZE];
arr_b = new int[VEC_SIZE];
arr_c = new int[VEC_SIZE];
cuda_status = cudaMalloc((void**)&d_arr_a, size);
if(cuda_status != cudaSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
cuda_status = cudaMalloc((void**)&d_arr_b, size);
if(cuda_status != cudaSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
cuda_status = cudaMalloc((void**)&d_arr_c, size);
if(cuda_status != cudaSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
srand(time(NULL));
for (int i = 0; i < VEC_SIZE; i++)
{
arr_a[i] = START + rand() % STOP;
arr_b[i] = START + rand() % STOP;
}
cuda_status = cudaMemcpy(d_arr_a, arr_a, VEC_SIZE, cudaMemcpyHostToDevice);
if(cuda_status != cudaSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
cuda_status = cudaMemcpy(d_arr_b, arr_b, VEC_SIZE, cudaMemcpyHostToDevice);
if(cuda_status != cudaSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
cuda_status = cudaGetDeviceCount(&dev_count);
if(cuda_status != cudaSuccess)
{
cout << "Cuda get device count error!" << endl;
goto cuda_error;
}
cuda_status = cudaEventRecord(e_start);
if(cuda_status != cudaSuccess)
{
cout << "Cuda event error while recording!" << endl;
goto cuda_error;
}
vect_mul<<<VEC_SIZE, 1>>>(d_arr_a, d_arr_b, d_arr_c);
cudaDeviceSynchronize();
cuda_status = cudaGetLastError();
if(cuda_status != cudaSuccess)
{
cout << "Kernel error!" << endl;
goto cuda_error;
}
cuda_status = cudaEventRecord(e_stop);
if(cuda_status != cudaSuccess)
{
cout << "Cuda event error while recording!" << endl;
goto cuda_error;
}
cuda_status = cudaMemcpy(arr_c, d_arr_c, VEC_SIZE, cudaMemcpyDeviceToHost);
if(cuda_status != cudaSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
for(int i = 0; i < VEC_SIZE; i++)
total_sum += arr_c[i];
cuda_status = cudaEventSynchronize(e_stop);
if(cuda_status != cudaSuccess)
{
cout << "Cuda event error while synchronizing!" << endl;
goto cuda_error;
}
cuda_status = cudaEventElapsedTime(&working_time, e_start, e_stop);
if(cuda_status != cudaSuccess)
{
cout << "Cuda event error while elapsing!" << endl;
goto cuda_error;
}
cout << "CUDA devices: " << dev_count << endl;
cout << "Result of vectors multiplication is " << total_sum << endl;
cout << "Working time: " << working_time << " ms"<< endl;
cuda_error:
delete[] arr_a;
delete[] arr_b;
delete[] arr_c;
cudaFree(d_arr_a);
cudaFree(d_arr_b);
cudaFree(d_arr_c);
cudaDeviceReset();
return 0;
} | #include <iostream>
#include <cstdlib>
#include <ctime>
#include "hip/hip_runtime.h"
#define VEC_SIZE 20000
#define START 1
#define STOP 100
using namespace std;
__global__ void vect_mul(int *arr_a, int *arr_b, int *arr_c)
{
arr_c[threadIdx.x] = arr_a[threadIdx.x] * arr_b[threadIdx.x];
}
int main()
{
int *arr_a, *arr_b, *arr_c, total_sum = 0, dev_count;
int *d_arr_a, *d_arr_b, *d_arr_c;
int size = sizeof(int) * VEC_SIZE;
float working_time = 0;
hipEvent_t e_start, e_stop;
hipError_t cuda_status;
cuda_status = hipEventCreate(&e_start);
if(cuda_status != hipSuccess)
{
cout << "Can not create cuda event!" << endl;
}
cuda_status = hipEventCreate(&e_stop);
if(cuda_status != hipSuccess)
{
cout << "Can not create cuda event!" << endl;
}
arr_a = new int[VEC_SIZE];
arr_b = new int[VEC_SIZE];
arr_c = new int[VEC_SIZE];
cuda_status = hipMalloc((void**)&d_arr_a, size);
if(cuda_status != hipSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
cuda_status = hipMalloc((void**)&d_arr_b, size);
if(cuda_status != hipSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
cuda_status = hipMalloc((void**)&d_arr_c, size);
if(cuda_status != hipSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
srand(time(NULL));
for (int i = 0; i < VEC_SIZE; i++)
{
arr_a[i] = START + rand() % STOP;
arr_b[i] = START + rand() % STOP;
}
cuda_status = hipMemcpy(d_arr_a, arr_a, VEC_SIZE, hipMemcpyHostToDevice);
if(cuda_status != hipSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
cuda_status = hipMemcpy(d_arr_b, arr_b, VEC_SIZE, hipMemcpyHostToDevice);
if(cuda_status != hipSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
cuda_status = hipGetDeviceCount(&dev_count);
if(cuda_status != hipSuccess)
{
cout << "Cuda get device count error!" << endl;
goto cuda_error;
}
cuda_status = hipEventRecord(e_start);
if(cuda_status != hipSuccess)
{
cout << "Cuda event error while recording!" << endl;
goto cuda_error;
}
vect_mul<<<VEC_SIZE, 1>>>(d_arr_a, d_arr_b, d_arr_c);
hipDeviceSynchronize();
cuda_status = hipGetLastError();
if(cuda_status != hipSuccess)
{
cout << "Kernel error!" << endl;
goto cuda_error;
}
cuda_status = hipEventRecord(e_stop);
if(cuda_status != hipSuccess)
{
cout << "Cuda event error while recording!" << endl;
goto cuda_error;
}
cuda_status = hipMemcpy(arr_c, d_arr_c, VEC_SIZE, hipMemcpyDeviceToHost);
if(cuda_status != hipSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
for(int i = 0; i < VEC_SIZE; i++)
total_sum += arr_c[i];
cuda_status = hipEventSynchronize(e_stop);
if(cuda_status != hipSuccess)
{
cout << "Cuda event error while synchronizing!" << endl;
goto cuda_error;
}
cuda_status = hipEventElapsedTime(&working_time, e_start, e_stop);
if(cuda_status != hipSuccess)
{
cout << "Cuda event error while elapsing!" << endl;
goto cuda_error;
}
cout << "CUDA devices: " << dev_count << endl;
cout << "Result of vectors multiplication is " << total_sum << endl;
cout << "Working time: " << working_time << " ms"<< endl;
cuda_error:
delete[] arr_a;
delete[] arr_b;
delete[] arr_c;
hipFree(d_arr_a);
hipFree(d_arr_b);
hipFree(d_arr_c);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <cstdlib>
#include <ctime>
#include "hip/hip_runtime.h"
#define VEC_SIZE 20000
#define START 1
#define STOP 100
using namespace std;
__global__ void vect_mul(int *arr_a, int *arr_b, int *arr_c)
{
arr_c[threadIdx.x] = arr_a[threadIdx.x] * arr_b[threadIdx.x];
}
int main()
{
int *arr_a, *arr_b, *arr_c, total_sum = 0, dev_count;
int *d_arr_a, *d_arr_b, *d_arr_c;
int size = sizeof(int) * VEC_SIZE;
float working_time = 0;
hipEvent_t e_start, e_stop;
hipError_t cuda_status;
cuda_status = hipEventCreate(&e_start);
if(cuda_status != hipSuccess)
{
cout << "Can not create cuda event!" << endl;
}
cuda_status = hipEventCreate(&e_stop);
if(cuda_status != hipSuccess)
{
cout << "Can not create cuda event!" << endl;
}
arr_a = new int[VEC_SIZE];
arr_b = new int[VEC_SIZE];
arr_c = new int[VEC_SIZE];
cuda_status = hipMalloc((void**)&d_arr_a, size);
if(cuda_status != hipSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
cuda_status = hipMalloc((void**)&d_arr_b, size);
if(cuda_status != hipSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
cuda_status = hipMalloc((void**)&d_arr_c, size);
if(cuda_status != hipSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
srand(time(NULL));
for (int i = 0; i < VEC_SIZE; i++)
{
arr_a[i] = START + rand() % STOP;
arr_b[i] = START + rand() % STOP;
}
cuda_status = hipMemcpy(d_arr_a, arr_a, VEC_SIZE, hipMemcpyHostToDevice);
if(cuda_status != hipSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
cuda_status = hipMemcpy(d_arr_b, arr_b, VEC_SIZE, hipMemcpyHostToDevice);
if(cuda_status != hipSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
cuda_status = hipGetDeviceCount(&dev_count);
if(cuda_status != hipSuccess)
{
cout << "Cuda get device count error!" << endl;
goto cuda_error;
}
cuda_status = hipEventRecord(e_start);
if(cuda_status != hipSuccess)
{
cout << "Cuda event error while recording!" << endl;
goto cuda_error;
}
vect_mul<<<VEC_SIZE, 1>>>(d_arr_a, d_arr_b, d_arr_c);
hipDeviceSynchronize();
cuda_status = hipGetLastError();
if(cuda_status != hipSuccess)
{
cout << "Kernel error!" << endl;
goto cuda_error;
}
cuda_status = hipEventRecord(e_stop);
if(cuda_status != hipSuccess)
{
cout << "Cuda event error while recording!" << endl;
goto cuda_error;
}
cuda_status = hipMemcpy(arr_c, d_arr_c, VEC_SIZE, hipMemcpyDeviceToHost);
if(cuda_status != hipSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
for(int i = 0; i < VEC_SIZE; i++)
total_sum += arr_c[i];
cuda_status = hipEventSynchronize(e_stop);
if(cuda_status != hipSuccess)
{
cout << "Cuda event error while synchronizing!" << endl;
goto cuda_error;
}
cuda_status = hipEventElapsedTime(&working_time, e_start, e_stop);
if(cuda_status != hipSuccess)
{
cout << "Cuda event error while elapsing!" << endl;
goto cuda_error;
}
cout << "CUDA devices: " << dev_count << endl;
cout << "Result of vectors multiplication is " << total_sum << endl;
cout << "Working time: " << working_time << " ms"<< endl;
cuda_error:
delete[] arr_a;
delete[] arr_b;
delete[] arr_c;
hipFree(d_arr_a);
hipFree(d_arr_b);
hipFree(d_arr_c);
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8vect_mulPiS_S_
.globl _Z8vect_mulPiS_S_
.p2align 8
.type _Z8vect_mulPiS_S_,@function
_Z8vect_mulPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8vect_mulPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8vect_mulPiS_S_, .Lfunc_end0-_Z8vect_mulPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8vect_mulPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z8vect_mulPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <cstdlib>
#include <ctime>
#include "hip/hip_runtime.h"
#define VEC_SIZE 20000
#define START 1
#define STOP 100
using namespace std;
__global__ void vect_mul(int *arr_a, int *arr_b, int *arr_c)
{
arr_c[threadIdx.x] = arr_a[threadIdx.x] * arr_b[threadIdx.x];
}
int main()
{
int *arr_a, *arr_b, *arr_c, total_sum = 0, dev_count;
int *d_arr_a, *d_arr_b, *d_arr_c;
int size = sizeof(int) * VEC_SIZE;
float working_time = 0;
hipEvent_t e_start, e_stop;
hipError_t cuda_status;
cuda_status = hipEventCreate(&e_start);
if(cuda_status != hipSuccess)
{
cout << "Can not create cuda event!" << endl;
}
cuda_status = hipEventCreate(&e_stop);
if(cuda_status != hipSuccess)
{
cout << "Can not create cuda event!" << endl;
}
arr_a = new int[VEC_SIZE];
arr_b = new int[VEC_SIZE];
arr_c = new int[VEC_SIZE];
cuda_status = hipMalloc((void**)&d_arr_a, size);
if(cuda_status != hipSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
cuda_status = hipMalloc((void**)&d_arr_b, size);
if(cuda_status != hipSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
cuda_status = hipMalloc((void**)&d_arr_c, size);
if(cuda_status != hipSuccess)
{
cout << "Cuda malloc error!" << endl;
goto cuda_error;
}
srand(time(NULL));
for (int i = 0; i < VEC_SIZE; i++)
{
arr_a[i] = START + rand() % STOP;
arr_b[i] = START + rand() % STOP;
}
cuda_status = hipMemcpy(d_arr_a, arr_a, VEC_SIZE, hipMemcpyHostToDevice);
if(cuda_status != hipSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
cuda_status = hipMemcpy(d_arr_b, arr_b, VEC_SIZE, hipMemcpyHostToDevice);
if(cuda_status != hipSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
cuda_status = hipGetDeviceCount(&dev_count);
if(cuda_status != hipSuccess)
{
cout << "Cuda get device count error!" << endl;
goto cuda_error;
}
cuda_status = hipEventRecord(e_start);
if(cuda_status != hipSuccess)
{
cout << "Cuda event error while recording!" << endl;
goto cuda_error;
}
vect_mul<<<VEC_SIZE, 1>>>(d_arr_a, d_arr_b, d_arr_c);
hipDeviceSynchronize();
cuda_status = hipGetLastError();
if(cuda_status != hipSuccess)
{
cout << "Kernel error!" << endl;
goto cuda_error;
}
cuda_status = hipEventRecord(e_stop);
if(cuda_status != hipSuccess)
{
cout << "Cuda event error while recording!" << endl;
goto cuda_error;
}
cuda_status = hipMemcpy(arr_c, d_arr_c, VEC_SIZE, hipMemcpyDeviceToHost);
if(cuda_status != hipSuccess)
{
cout << "Cuda memcpy error!" << endl;
goto cuda_error;
}
for(int i = 0; i < VEC_SIZE; i++)
total_sum += arr_c[i];
cuda_status = hipEventSynchronize(e_stop);
if(cuda_status != hipSuccess)
{
cout << "Cuda event error while synchronizing!" << endl;
goto cuda_error;
}
cuda_status = hipEventElapsedTime(&working_time, e_start, e_stop);
if(cuda_status != hipSuccess)
{
cout << "Cuda event error while elapsing!" << endl;
goto cuda_error;
}
cout << "CUDA devices: " << dev_count << endl;
cout << "Result of vectors multiplication is " << total_sum << endl;
cout << "Working time: " << working_time << " ms"<< endl;
cuda_error:
delete[] arr_a;
delete[] arr_b;
delete[] arr_c;
hipFree(d_arr_a);
hipFree(d_arr_b);
hipFree(d_arr_c);
hipDeviceReset();
return 0;
} | .text
.file "vec_mul_gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__vect_mulPiS_S_ # -- Begin function _Z23__device_stub__vect_mulPiS_S_
.p2align 4, 0x90
.type _Z23__device_stub__vect_mulPiS_S_,@function
_Z23__device_stub__vect_mulPiS_S_: # @_Z23__device_stub__vect_mulPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8vect_mulPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__vect_mulPiS_S_, .Lfunc_end0-_Z23__device_stub__vect_mulPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 12(%rsp)
leaq 56(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
je .LBB1_6
# %bb.1:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB1_5
.LBB1_4:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_6:
leaq 16(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
je .LBB1_12
# %bb.7:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i53
cmpb $0, 56(%rbx)
je .LBB1_10
# %bb.9:
movzbl 67(%rbx), %eax
jmp .LBB1_11
.LBB1_10:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit56
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_12:
movl $80000, %edi # imm = 0x13880
callq _Znam
movq %rax, %rbx
movl $80000, %edi # imm = 0x13880
callq _Znam
movq %rax, %r14
movl $80000, %edi # imm = 0x13880
callq _Znam
movq %rax, %r15
leaq 40(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.17:
leaq 32(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.20:
leaq 24(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
testl %eax, %eax
je .LBB1_22
.LBB1_13:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
.LBB1_14:
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i58
cmpb $0, 56(%r12)
je .LBB1_26
# %bb.16:
movzbl 67(%r12), %eax
jmp .LBB1_27
.LBB1_26:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_27: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit61
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_28:
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
callq hipDeviceReset
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 112
xorl %r12d, %r12d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_23: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%rbx,%r12,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq $20000, %r12 # imm = 0x4E20
jne .LBB1_23
# %bb.24:
movq 40(%rsp), %rdi
movl $20000, %edx # imm = 0x4E20
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_29
# %bb.25:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
jmp .LBB1_14
.LBB1_29:
movq 32(%rsp), %rdi
movl $20000, %edx # imm = 0x4E20
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_31
.LBB1_30:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $18, %edx
jmp .LBB1_39
.LBB1_31:
leaq 52(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
je .LBB1_33
# %bb.32:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $28, %edx
jmp .LBB1_39
.LBB1_33:
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
je .LBB1_35
.LBB1_34:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $33, %edx
jmp .LBB1_39
.LBB1_35:
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 19999(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_37
# %bb.36:
movq 40(%rsp), %rdi
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
callq _Z23__device_stub__vect_mulPiS_S_
.LBB1_37:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB1_41
# %bb.38:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $13, %edx
.LBB1_39:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
.LBB1_40:
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
jmp .LBB1_28
.LBB1_41:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_34
# %bb.42:
movq 24(%rsp), %rsi
movl $20000, %edx # imm = 0x4E20
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_30
# %bb.43: # %.preheader.preheader
xorl %eax, %eax
xorl %ebp, %ebp
.LBB1_44: # %.preheader
# =>This Inner Loop Header: Depth=1
addl (%r15,%rax,4), %ebp
incq %rax
cmpq $20000, %rax # imm = 0x4E20
jne .LBB1_44
# %bb.45:
movq 16(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
je .LBB1_47
# %bb.46:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $37, %edx
jmp .LBB1_39
.LBB1_47:
movq 56(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
testl %eax, %eax
je .LBB1_49
# %bb.48:
movl $.L.str.7, %esi
movl $32, %edx
jmp .LBB1_39
.LBB1_49:
movl $.L.str.8, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 52(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $36, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.11, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r12, %rdi
jmp .LBB1_40
.LBB1_19:
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8vect_mulPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8vect_mulPiS_S_,@object # @_Z8vect_mulPiS_S_
.section .rodata,"a",@progbits
.globl _Z8vect_mulPiS_S_
.p2align 3, 0x0
_Z8vect_mulPiS_S_:
.quad _Z23__device_stub__vect_mulPiS_S_
.size _Z8vect_mulPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Can not create cuda event!"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cuda malloc error!"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Cuda memcpy error!"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cuda get device count error!"
.size .L.str.3, 29
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Cuda event error while recording!"
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Kernel error!"
.size .L.str.5, 14
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Cuda event error while synchronizing!"
.size .L.str.6, 38
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Cuda event error while elapsing!"
.size .L.str.7, 33
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "CUDA devices: "
.size .L.str.8, 16
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Result of vectors multiplication is "
.size .L.str.9, 37
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Working time: "
.size .L.str.10, 15
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " ms"
.size .L.str.11, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8vect_mulPiS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__vect_mulPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8vect_mulPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8vect_mulPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*0090*/ IMAD R9, R2, R5, RZ ; /* 0x0000000502097224 */
/* 0x004fca00078e02ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8vect_mulPiS_S_
.globl _Z8vect_mulPiS_S_
.p2align 8
.type _Z8vect_mulPiS_S_,@function
_Z8vect_mulPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8vect_mulPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8vect_mulPiS_S_, .Lfunc_end0-_Z8vect_mulPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8vect_mulPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z8vect_mulPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ecb74_00000000-6_vec_mul_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8vect_mulPiS_S_PiS_S_
.type _Z31__device_stub__Z8vect_mulPiS_S_PiS_S_, @function
_Z31__device_stub__Z8vect_mulPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8vect_mulPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z31__device_stub__Z8vect_mulPiS_S_PiS_S_, .-_Z31__device_stub__Z8vect_mulPiS_S_PiS_S_
.globl _Z8vect_mulPiS_S_
.type _Z8vect_mulPiS_S_, @function
_Z8vect_mulPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8vect_mulPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8vect_mulPiS_S_, .-_Z8vect_mulPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Can not create cuda event!"
.LC2:
.string "Cuda malloc error!"
.LC3:
.string "Cuda memcpy error!"
.LC4:
.string "Cuda get device count error!"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Cuda event error while recording!"
.section .rodata.str1.1
.LC6:
.string "Kernel error!"
.section .rodata.str1.8
.align 8
.LC7:
.string "Cuda event error while synchronizing!"
.align 8
.LC8:
.string "Cuda event error while elapsing!"
.section .rodata.str1.1
.LC9:
.string "CUDA devices: "
.section .rodata.str1.8
.align 8
.LC10:
.string "Result of vectors multiplication is "
.section .rodata.str1.1
.LC11:
.string "Working time: "
.LC12:
.string " ms"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0x00000000, 4(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L34
.L12:
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L35
.L13:
movl $80000, %edi
call _Znam@PLT
movq %rax, %rbp
movl $80000, %edi
call _Znam@PLT
movq %rax, %r12
movl $80000, %edi
call _Znam@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L36
leaq 16(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L37
leaq 24(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L38
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $0, %ebx
.L18:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, 0(%rbp,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, (%r12,%rbx)
addq $4, %rbx
cmpq $80000, %rbx
jne .L18
movl $1, %ecx
movl $20000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L39
movl $1, %ecx
movl $20000, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L40
movq %rsp, %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L41
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L42
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $20000, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L23:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L44
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L45
movl $2, %ecx
movl $20000, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L46
movq %r13, %rax
leaq 80000(%r13), %rcx
movl $0, %edx
.L27:
movl %edx, %ebx
addl (%rax), %ebx
movl %ebx, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L27
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L47
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L48
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %r14
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC10(%rip), %rsi
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC11(%rip), %rsi
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L34:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L12
.L35:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L13
.L36:
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L15:
movq %rbp, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L38:
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L39:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L40:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L41:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L42:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L43:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z8vect_mulPiS_S_PiS_S_
jmp .L23
.L44:
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L45:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L46:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L47:
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L48:
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z8vect_mulPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8vect_mulPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vec_mul_gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__vect_mulPiS_S_ # -- Begin function _Z23__device_stub__vect_mulPiS_S_
.p2align 4, 0x90
.type _Z23__device_stub__vect_mulPiS_S_,@function
_Z23__device_stub__vect_mulPiS_S_: # @_Z23__device_stub__vect_mulPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8vect_mulPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__vect_mulPiS_S_, .Lfunc_end0-_Z23__device_stub__vect_mulPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 12(%rsp)
leaq 56(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
je .LBB1_6
# %bb.1:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB1_5
.LBB1_4:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_6:
leaq 16(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
je .LBB1_12
# %bb.7:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i53
cmpb $0, 56(%rbx)
je .LBB1_10
# %bb.9:
movzbl 67(%rbx), %eax
jmp .LBB1_11
.LBB1_10:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit56
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_12:
movl $80000, %edi # imm = 0x13880
callq _Znam
movq %rax, %rbx
movl $80000, %edi # imm = 0x13880
callq _Znam
movq %rax, %r14
movl $80000, %edi # imm = 0x13880
callq _Znam
movq %rax, %r15
leaq 40(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.17:
leaq 32(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.20:
leaq 24(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
testl %eax, %eax
je .LBB1_22
.LBB1_13:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
.LBB1_14:
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i58
cmpb $0, 56(%r12)
je .LBB1_26
# %bb.16:
movzbl 67(%r12), %eax
jmp .LBB1_27
.LBB1_26:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_27: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit61
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_28:
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
callq hipDeviceReset
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 112
xorl %r12d, %r12d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_23: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%rbx,%r12,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq $20000, %r12 # imm = 0x4E20
jne .LBB1_23
# %bb.24:
movq 40(%rsp), %rdi
movl $20000, %edx # imm = 0x4E20
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_29
# %bb.25:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
jmp .LBB1_14
.LBB1_29:
movq 32(%rsp), %rdi
movl $20000, %edx # imm = 0x4E20
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_31
.LBB1_30:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $18, %edx
jmp .LBB1_39
.LBB1_31:
leaq 52(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
je .LBB1_33
# %bb.32:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $28, %edx
jmp .LBB1_39
.LBB1_33:
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
je .LBB1_35
.LBB1_34:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $33, %edx
jmp .LBB1_39
.LBB1_35:
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 19999(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_37
# %bb.36:
movq 40(%rsp), %rdi
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
callq _Z23__device_stub__vect_mulPiS_S_
.LBB1_37:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB1_41
# %bb.38:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $13, %edx
.LBB1_39:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
.LBB1_40:
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
jmp .LBB1_28
.LBB1_41:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_34
# %bb.42:
movq 24(%rsp), %rsi
movl $20000, %edx # imm = 0x4E20
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_30
# %bb.43: # %.preheader.preheader
xorl %eax, %eax
xorl %ebp, %ebp
.LBB1_44: # %.preheader
# =>This Inner Loop Header: Depth=1
addl (%r15,%rax,4), %ebp
incq %rax
cmpq $20000, %rax # imm = 0x4E20
jne .LBB1_44
# %bb.45:
movq 16(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
je .LBB1_47
# %bb.46:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $37, %edx
jmp .LBB1_39
.LBB1_47:
movq 56(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
testl %eax, %eax
je .LBB1_49
# %bb.48:
movl $.L.str.7, %esi
movl $32, %edx
jmp .LBB1_39
.LBB1_49:
movl $.L.str.8, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 52(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $36, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.11, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r12, %rdi
jmp .LBB1_40
.LBB1_19:
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8vect_mulPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8vect_mulPiS_S_,@object # @_Z8vect_mulPiS_S_
.section .rodata,"a",@progbits
.globl _Z8vect_mulPiS_S_
.p2align 3, 0x0
_Z8vect_mulPiS_S_:
.quad _Z23__device_stub__vect_mulPiS_S_
.size _Z8vect_mulPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Can not create cuda event!"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cuda malloc error!"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Cuda memcpy error!"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cuda get device count error!"
.size .L.str.3, 29
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Cuda event error while recording!"
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Kernel error!"
.size .L.str.5, 14
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Cuda event error while synchronizing!"
.size .L.str.6, 38
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Cuda event error while elapsing!"
.size .L.str.7, 33
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "CUDA devices: "
.size .L.str.8, 16
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Result of vectors multiplication is "
.size .L.str.9, 37
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Working time: "
.size .L.str.10, 15
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " ms"
.size .L.str.11, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8vect_mulPiS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__vect_mulPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8vect_mulPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<cuda_runtime.h>
#include<device_launch_parameters.h>
__global__ void add(float *a,float *b){
int id = blockIdx.x*blockDim.x+threadIdx.x;
b[id] = sinf(a[id]);
}
int main(){
int n;
float a[10],b[10];
printf("Enter n:");
scanf("%d",&n);
printf("Enter A:\n");
for(int i=0;i<n;i++)
scanf("%f",&a[i]);
float *d_a,*d_b;
int size = sizeof(float)*n;
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_b,size);
cudaMemcpy(d_a,&a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,&b,size,cudaMemcpyHostToDevice);
add<<<n,1>>>(d_a,d_b);
cudaMemcpy(&b,d_b,size,cudaMemcpyDeviceToHost);
for(int i=0;i<n;i++)
printf("%f ",b[i]);
printf("\n");
cudaFree(d_a);
cudaFree(d_b);
} | code for sm_80
Function : _Z3addPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ BSSY B0, 0x7e0 ; /* 0x0000075000007945 */
/* 0x000fe20003800000 */
/*0090*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*00a0*/ FMUL R6, R2.reuse, 0.63661974668502807617 ; /* 0x3f22f98302067820 */
/* 0x044fe20000400000 */
/*00b0*/ FSETP.GE.AND P0, PT, |R2|, 105615, PT ; /* 0x47ce47800200780b */
/* 0x000fc60003f06200 */
/*00c0*/ F2I.NTZ R10, R6 ; /* 0x00000006000a7305 */
/* 0x000e300000203100 */
/*00d0*/ I2F R7, R10 ; /* 0x0000000a00077306 */
/* 0x001e240000201400 */
/*00e0*/ FFMA R8, R7, -1.5707962512969970703, R2 ; /* 0xbfc90fda07087823 */
/* 0x001fc80000000002 */
/*00f0*/ FFMA R8, R7, -7.5497894158615963534e-08, R8 ; /* 0xb3a2216807087823 */
/* 0x000fc80000000008 */
/*0100*/ FFMA R11, R7, -5.3903029534742383927e-15, R8 ; /* 0xa7c234c5070b7823 */
/* 0x000fe20000000008 */
/*0110*/ @!P0 BRA 0x7d0 ; /* 0x000006b000008947 */
/* 0x000fea0003800000 */
/*0120*/ FSETP.NEU.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f0d200 */
/*0130*/ @!P0 BRA 0x7b0 ; /* 0x0000067000008947 */
/* 0x000fea0003800000 */
/*0140*/ SHF.R.U32.HI R4, RZ, 0x17, R2 ; /* 0x00000017ff047819 */
/* 0x000fe20000011602 */
/*0150*/ IMAD.SHL.U32 R6, R2, 0x100, RZ ; /* 0x0000010002067824 */
/* 0x000fe200078e00ff */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0170*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0180*/ LOP3.LUT R5, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04057812 */
/* 0x000fe200078ec0ff */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*01a0*/ LOP3.LUT R11, R6, 0x80000000, RZ, 0xfc, !PT ; /* 0x80000000060b7812 */
/* 0x000fe200078efcff */
/*01b0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*01c0*/ IADD3 R5, R5, -0x80, RZ ; /* 0xffffff8005057810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fc60000000a00 */
/*01e0*/ SHF.R.U32.HI R12, RZ, 0x5, R5 ; /* 0x00000005ff0c7819 */
/* 0x000fe40000011605 */
/*01f0*/ IMAD.U32 R6, RZ, RZ, UR8 ; /* 0x00000008ff067e24 */
/* 0x000fe4000f8e00ff */
/*0200*/ IMAD.U32 R7, RZ, RZ, UR9 ; /* 0x00000009ff077e24 */
/* 0x000fca000f8e00ff */
/*0210*/ LDG.E.CONSTANT R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea2000c1e9900 */
/*0220*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe20007ffe0ff */
/*0230*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff1e03f */
/*0240*/ ISETP.EQ.AND P0, PT, R19.reuse, RZ, PT ; /* 0x000000ff1300720c */
/* 0x040fe40003f02270 */
/*0250*/ ISETP.EQ.AND P5, PT, R19.reuse, 0x4, PT ; /* 0x000000041300780c */
/* 0x040fe20003fa2270 */
/*0260*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0270*/ ISETP.EQ.AND P4, PT, R19.reuse, 0x8, PT ; /* 0x000000081300780c */
/* 0x040fe40003f82270 */
/*0280*/ ISETP.EQ.AND P3, PT, R19.reuse, 0xc, PT ; /* 0x0000000c1300780c */
/* 0x040fe40003f62270 */
/*0290*/ ISETP.EQ.AND P2, PT, R19, 0x10, PT ; /* 0x000000101300780c */
/* 0x000fc40003f42270 */
/*02a0*/ ISETP.EQ.AND P1, PT, R19.reuse, 0x14, PT ; /* 0x000000141300780c */
/* 0x040fe40003f22270 */
/*02b0*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.WIDE.U32 R8, R6, R11, RZ ; /* 0x0000000b06087225 */
/* 0x004fca00078e00ff */
/*02d0*/ IADD3 R8, P6, R8, R4, RZ ; /* 0x0000000408087210 */
/* 0x000fc80007fde0ff */
/*02e0*/ IADD3.X R4, R9, UR4, RZ, P6, !PT ; /* 0x0000000409047c10 */
/* 0x000fe2000b7fe4ff */
/*02f0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, R8.reuse ; /* 0x000000ffff0a0224 */
/* 0x100fe200078e0008 */
/*0300*/ ISETP.NE.AND P6, PT, R13, 0x6, PT ; /* 0x000000060d00780c */
/* 0x000fe20003fc5270 */
/*0310*/ @P5 IMAD.MOV.U32 R15, RZ, RZ, R8.reuse ; /* 0x000000ffff0f5224 */
/* 0x100fe400078e0008 */
/*0320*/ @P4 IMAD.MOV.U32 R16, RZ, RZ, R8.reuse ; /* 0x000000ffff104224 */
/* 0x100fe400078e0008 */
/*0330*/ @P3 IMAD.MOV.U32 R17, RZ, RZ, R8.reuse ; /* 0x000000ffff113224 */
/* 0x100fe400078e0008 */
/*0340*/ @P2 IMAD.MOV.U32 R18, RZ, RZ, R8.reuse ; /* 0x000000ffff122224 */
/* 0x100fe400078e0008 */
/*0350*/ @P1 IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e1224 */
/* 0x000fc800078e0008 */
/*0360*/ @P6 BRA 0x1f0 ; /* 0xfffffe8000006947 */
/* 0x000fea000383ffff */
/*0370*/ IADD3 R6, -R12, 0x6, RZ ; /* 0x000000060c067810 */
/* 0x000fe20007ffe1ff */
/*0380*/ BSSY B1, 0x6a0 ; /* 0x0000031000017945 */
/* 0x000fe80003800000 */
/*0390*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x000fca00078e00ff */
/*03a0*/ ISETP.EQ.AND P0, PT, R6.reuse, RZ, PT ; /* 0x000000ff0600720c */
/* 0x040fe40003f02270 */
/*03b0*/ ISETP.EQ.AND P3, PT, R6.reuse, 0x4, PT ; /* 0x000000040600780c */
/* 0x040fe40003f62270 */
/*03c0*/ ISETP.EQ.AND P4, PT, R6.reuse, 0x8, PT ; /* 0x000000080600780c */
/* 0x040fe40003f82270 */
/*03d0*/ ISETP.EQ.AND P2, PT, R6.reuse, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x040fe40003f42270 */
/*03e0*/ ISETP.EQ.AND P1, PT, R6, 0x10, PT ; /* 0x000000100600780c */
/* 0x000fca0003f22270 */
/*03f0*/ @P0 MOV R7, R10 ; /* 0x0000000a00070202 */
/* 0x000fe40000000f00 */
/*0400*/ @P3 IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff083224 */
/* 0x000fe200078e000a */
/*0410*/ ISETP.EQ.AND P0, PT, R6.reuse, 0x14, PT ; /* 0x000000140600780c */
/* 0x040fe20003f02270 */
/*0420*/ @P3 IMAD.MOV.U32 R7, RZ, RZ, R15.reuse ; /* 0x000000ffff073224 */
/* 0x100fe200078e000f */
/*0430*/ ISETP.EQ.AND P3, PT, R6.reuse, 0x18, PT ; /* 0x000000180600780c */
/* 0x040fe20003f62270 */
/*0440*/ @P4 IMAD.MOV.U32 R8, RZ, RZ, R15 ; /* 0x000000ffff084224 */
/* 0x000fe400078e000f */
/*0450*/ @P4 IMAD.MOV.U32 R7, RZ, RZ, R16.reuse ; /* 0x000000ffff074224 */
/* 0x100fe200078e0010 */
/*0460*/ ISETP.EQ.AND P4, PT, R6, 0x1c, PT ; /* 0x0000001c0600780c */
/* 0x000fe20003f82270 */
/*0470*/ @P2 IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff082224 */
/* 0x000fc400078e0010 */
/*0480*/ @P2 IMAD.MOV.U32 R7, RZ, RZ, R17.reuse ; /* 0x000000ffff072224 */
/* 0x100fe400078e0011 */
/*0490*/ @P1 IMAD.MOV.U32 R8, RZ, RZ, R17 ; /* 0x000000ffff081224 */
/* 0x000fe400078e0011 */
/*04a0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R18 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0012 */
/*04b0*/ LOP3.LUT P1, R6, R5, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f05067812 */
/* 0x000fe2000782c0ff */
/*04c0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R14 ; /* 0x000000ffff070224 */
/* 0x000fe400078e000e */
/*04d0*/ @P3 IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff073224 */
/* 0x000fe400078e0004 */
/*04e0*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, R18 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0012 */
/*04f0*/ @P3 MOV R8, R14 ; /* 0x0000000e00083202 */
/* 0x000fe20000000f00 */
/*0500*/ @P4 IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff084224 */
/* 0x000fc400078e0004 */
/*0510*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0007 */
/*0520*/ @!P1 BRA 0x690 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*0530*/ IADD3 R12, -R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007ffe1ff */
/*0540*/ IADD3 R7, -R6, 0x20, RZ ; /* 0x0000002006077810 */
/* 0x000fe40007ffe1ff */
/*0550*/ SHF.L.U32 R9, R8, R6, RZ ; /* 0x0000000608097219 */
/* 0x000fe200000006ff */
/*0560*/ IMAD.SHL.U32 R12, R12, 0x4, RZ ; /* 0x000000040c0c7824 */
/* 0x000fca00078e00ff */
/*0570*/ ISETP.EQ.AND P1, PT, R12.reuse, 0x4, PT ; /* 0x000000040c00780c */
/* 0x040fe40003f22270 */
/*0580*/ ISETP.EQ.AND P2, PT, R12.reuse, 0x8, PT ; /* 0x000000080c00780c */
/* 0x040fe40003f42270 */
/*0590*/ ISETP.EQ.AND P0, PT, R12.reuse, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x040fe40003f02270 */
/*05a0*/ ISETP.EQ.AND P3, PT, R12.reuse, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x040fe40003f62270 */
/*05b0*/ ISETP.EQ.AND P0, PT, R12, 0x10, PT ; /* 0x000000100c00780c */
/* 0x000fca0003f02270 */
/*05c0*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R15 ; /* 0x000000ffff0a1224 */
/* 0x000fe200078e000f */
/*05d0*/ ISETP.EQ.AND P1, PT, R12.reuse, 0x14, PT ; /* 0x000000140c00780c */
/* 0x040fe20003f22270 */
/*05e0*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R16 ; /* 0x000000ffff0a2224 */
/* 0x000fe200078e0010 */
/*05f0*/ ISETP.EQ.AND P2, PT, R12, 0x18, PT ; /* 0x000000180c00780c */
/* 0x000fc60003f42270 */
/*0600*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R17 ; /* 0x000000ffff0a3224 */
/* 0x000fe400078e0011 */
/*0610*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, R18 ; /* 0x000000ffff0a0224 */
/* 0x000fcc00078e0012 */
/*0620*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a1224 */
/* 0x000fe400078e000e */
/*0630*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a2224 */
/* 0x000fe200078e0004 */
/*0640*/ SHF.L.U32 R4, R5, R6, RZ ; /* 0x0000000605047219 */
/* 0x000fe400000006ff */
/*0650*/ SHF.R.U32.HI R5, RZ, R7.reuse, R8 ; /* 0x00000007ff057219 */
/* 0x080fe40000011608 */
/*0660*/ SHF.R.U32.HI R10, RZ, R7, R10 ; /* 0x00000007ff0a7219 */
/* 0x000fe4000001160a */
/*0670*/ IADD3 R5, R5, R4, RZ ; /* 0x0000000405057210 */
/* 0x000fc60007ffe0ff */
/*0680*/ IMAD.IADD R8, R10, 0x1, R9 ; /* 0x000000010a087824 */
/* 0x000fe400078e0209 */
/*0690*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06a0*/ SHF.L.U32.HI R9, R8.reuse, 0x2, R5 ; /* 0x0000000208097819 */
/* 0x040fe20000010605 */
/*06b0*/ IMAD.SHL.U32 R8, R8, 0x4, RZ ; /* 0x0000000408087824 */
/* 0x000fe200078e00ff */
/*06c0*/ LOP3.LUT P1, R2, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000002027812 */
/* 0x000fe4000782c0ff */
/*06d0*/ SHF.R.U32.HI R10, RZ, 0x1f, R9 ; /* 0x0000001fff0a7819 */
/* 0x000fc80000011609 */
/*06e0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*06f0*/ LEA.HI R10, R5, R10, RZ, 0x2 ; /* 0x0000000a050a7211 */
/* 0x000fd600078f10ff */
/*0700*/ @P0 LOP3.LUT R9, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff090212 */
/* 0x000fe400078e33ff */
/*0710*/ @P0 LOP3.LUT R8, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff080212 */
/* 0x000fe400078e33ff */
/*0720*/ @P0 LOP3.LUT R2, R2, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000002020812 */
/* 0x000fe400078e3cff */
/*0730*/ I2F.F64.S64 R6, R8 ; /* 0x0000000800067312 */
/* 0x000e240000301c00 */
/*0740*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0750*/ IMAD.MOV R2, RZ, RZ, -R10 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a0a */
/*0760*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a1224 */
/* 0x000fe200078e0002 */
/*0770*/ DMUL R6, R6, c[0x2][0x0] ; /* 0x0080000006067a28 */
/* 0x001e140000000000 */
/*0780*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */
/* 0x001e240000301000 */
/*0790*/ FSEL R11, R6, -R6, !P0 ; /* 0x80000006060b7208 */
/* 0x001fe20004000000 */
/*07a0*/ BRA 0x7d0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*07b0*/ FMUL R11, RZ, R2 ; /* 0x00000002ff0b7220 */
/* 0x000fe40000400000 */
/*07c0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*07d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT P1, RZ, R10.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x000000010aff7812 */
/* 0x040fe2000782c0ff */
/*07f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff057424 */
/* 0x000fe200078e00ff */
/*0800*/ LOP3.LUT P0, RZ, R10, 0x2, RZ, 0xc0, !PT ; /* 0x000000020aff7812 */
/* 0x000fe2000780c0ff */
/*0810*/ FMUL R6, R11.reuse, R11 ; /* 0x0000000b0b067220 */
/* 0x040fe20000400000 */
/*0820*/ FSEL R11, R11, 1, !P1 ; /* 0x3f8000000b0b7808 */
/* 0x000fe20004800000 */
/*0830*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff077424 */
/* 0x000fe200078e00ff */
/*0840*/ FSEL R5, R5, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb05057808 */
/* 0x000fe20004800000 */
/*0850*/ IMAD.MOV.U32 R2, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff027424 */
/* 0x000fc600078e00ff */
/*0860*/ FSEL R7, -R7, -0.4999999701976776123, !P1 ; /* 0xbeffffff07077808 */
/* 0x000fc60004800100 */
/*0870*/ @P1 IMAD.MOV.U32 R4, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff041424 */
/* 0x000fc800078e00ff */
/*0880*/ @P1 FFMA R2, R6.reuse, R4, -0.0013887860113754868507 ; /* 0xbab607ed06021423 */
/* 0x040fe40000000004 */
/*0890*/ FFMA R4, R11, R6, RZ ; /* 0x000000060b047223 */
/* 0x000fe400000000ff */
/*08a0*/ FFMA R2, R6, R2, R5 ; /* 0x0000000206027223 */
/* 0x000fc80000000005 */
/*08b0*/ FFMA R7, R6, R2, R7 ; /* 0x0000000206077223 */
/* 0x000fe20000000007 */
/*08c0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc600078210ff */
/*08d0*/ FFMA R7, R7, R4, R11 ; /* 0x0000000407077223 */
/* 0x000fe2000000000b */
/*08e0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fc600008f1403 */
/*08f0*/ @P0 FFMA R7, R7, -1, RZ ; /* 0xbf80000007070823 */
/* 0x000fca00000000ff */
/*0900*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0910*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0920*/ BRA 0x920; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<cuda_runtime.h>
#include<device_launch_parameters.h>
__global__ void add(float *a,float *b){
int id = blockIdx.x*blockDim.x+threadIdx.x;
b[id] = sinf(a[id]);
}
int main(){
int n;
float a[10],b[10];
printf("Enter n:");
scanf("%d",&n);
printf("Enter A:\n");
for(int i=0;i<n;i++)
scanf("%f",&a[i]);
float *d_a,*d_b;
int size = sizeof(float)*n;
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_b,size);
cudaMemcpy(d_a,&a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,&b,size,cudaMemcpyHostToDevice);
add<<<n,1>>>(d_a,d_b);
cudaMemcpy(&b,d_b,size,cudaMemcpyDeviceToHost);
for(int i=0;i<n;i++)
printf("%f ",b[i]);
printf("\n");
cudaFree(d_a);
cudaFree(d_b);
} | .file "tmpxft_000f2cca_00000000-6_q4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addPfS_PfS_
.type _Z24__device_stub__Z3addPfS_PfS_, @function
_Z24__device_stub__Z3addPfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3addPfS_PfS_, .-_Z24__device_stub__Z3addPfS_PfS_
.globl _Z3addPfS_
.type _Z3addPfS_, @function
_Z3addPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPfS_, .-_Z3addPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter n:"
.LC1:
.string "%d"
.LC2:
.string "Enter A:\n"
.LC3:
.string "%f"
.LC4:
.string "%f "
.LC5:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $144, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 4(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %eax
testl %eax, %eax
jle .L12
leaq 48(%rsp), %rbp
movl $0, %ebx
leaq .LC3(%rip), %r12
.L13:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 4(%rsp), %eax
addq $4, %rbp
cmpl %ebx, %eax
jg .L13
.L12:
sall $2, %eax
movslq %eax, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl 4(%rsp), %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
leaq 96(%rsp), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
cmpl $0, 4(%rsp)
jle .L15
movl $0, %ebx
leaq .LC4(%rip), %rbp
.L16:
pxor %xmm0, %xmm0
cvtss2sd 96(%rsp,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jg .L16
.L15:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z24__device_stub__Z3addPfS_PfS_
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<cuda_runtime.h>
#include<device_launch_parameters.h>
__global__ void add(float *a,float *b){
int id = blockIdx.x*blockDim.x+threadIdx.x;
b[id] = sinf(a[id]);
}
int main(){
int n;
float a[10],b[10];
printf("Enter n:");
scanf("%d",&n);
printf("Enter A:\n");
for(int i=0;i<n;i++)
scanf("%f",&a[i]);
float *d_a,*d_b;
int size = sizeof(float)*n;
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_b,size);
cudaMemcpy(d_a,&a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,&b,size,cudaMemcpyHostToDevice);
add<<<n,1>>>(d_a,d_b);
cudaMemcpy(&b,d_b,size,cudaMemcpyDeviceToHost);
for(int i=0;i<n;i++)
printf("%f ",b[i]);
printf("\n");
cudaFree(d_a);
cudaFree(d_b);
} | #include<stdio.h>
#include<hip/hip_runtime.h>
__global__ void add(float *a,float *b){
int id = blockIdx.x*blockDim.x+threadIdx.x;
b[id] = sinf(a[id]);
}
int main(){
int n;
float a[10],b[10];
printf("Enter n:");
scanf("%d",&n);
printf("Enter A:\n");
for(int i=0;i<n;i++)
scanf("%f",&a[i]);
float *d_a,*d_b;
int size = sizeof(float)*n;
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_b,size);
hipMemcpy(d_a,&a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,&b,size,hipMemcpyHostToDevice);
add<<<n,1>>>(d_a,d_b);
hipMemcpy(&b,d_b,size,hipMemcpyDeviceToHost);
for(int i=0;i<n;i++)
printf("%f ",b[i]);
printf("\n");
hipFree(d_a);
hipFree(d_b);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
__global__ void add(float *a,float *b){
int id = blockIdx.x*blockDim.x+threadIdx.x;
b[id] = sinf(a[id]);
}
int main(){
int n;
float a[10],b[10];
printf("Enter n:");
scanf("%d",&n);
printf("Enter A:\n");
for(int i=0;i<n;i++)
scanf("%f",&a[i]);
float *d_a,*d_b;
int size = sizeof(float)*n;
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_b,size);
hipMemcpy(d_a,&a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,&b,size,hipMemcpyHostToDevice);
add<<<n,1>>>(d_a,d_b);
hipMemcpy(&b,d_b,size,hipMemcpyDeviceToHost);
for(int i=0;i<n;i++)
printf("%f ",b[i]);
printf("\n");
hipFree(d_a);
hipFree(d_b);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPfS_
.globl _Z3addPfS_
.p2align 8
.type _Z3addPfS_,@function
_Z3addPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v3, 0x7fffffff, v0
v_cmpx_ngt_f32_e64 0x48000000, |v0|
s_xor_b32 s4, exec_lo, s3
s_cbranch_execz .LBB0_2
s_mov_b32 s2, 0x7fffff
v_mov_b32_e32 v6, 0
v_and_or_b32 v14, v3, s2, 0x800000
v_lshrrev_b32_e32 v11, 23, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, v14, 0xfe5163ab, 0
v_add_nc_u32_e32 v12, 0xffffff88, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v12
v_mad_u64_u32 v[7:8], null, v14, 0x3c439041, v[5:6]
v_cndmask_b32_e64 v13, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v5, v8
v_add_nc_u32_e32 v13, v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v14, 0xdb629599, v[5:6]
v_cmp_lt_u32_e64 s2, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v15, 0, 0xffffffe0, s2
v_dual_mov_b32 v5, v9 :: v_dual_cndmask_b32 v4, v8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v15, v15, v13
v_mad_u64_u32 v[9:10], null, v14, 0xf534ddc0, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v15
v_mov_b32_e32 v5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, v9, v7, vcc_lo
v_mad_u64_u32 v[10:11], null, v14, 0xfc2757d1, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, v7, v4, s2
v_mov_b32_e32 v5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v14, 0x4e441529, v[5:6]
v_mov_b32_e32 v5, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, v14, 0xa2f9836e, v[5:6]
v_cndmask_b32_e64 v5, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v6, v11, v9 :: v_dual_add_nc_u32 v5, v5, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v12, v12, v10 :: v_dual_cndmask_b32 v11, v13, v11
v_cndmask_b32_e32 v10, v10, v8, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v9, v12, v6, s2
v_cndmask_b32_e64 v11, v11, v12, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, v6, v10, s2
v_sub_nc_u32_e32 v12, 32, v5
v_cndmask_b32_e64 v10, v10, v7, s2
v_cndmask_b32_e64 v11, v11, v9, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, v9, v6, s3
v_cndmask_b32_e64 v6, v6, v10, s3
v_cndmask_b32_e64 v4, v10, v4, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v11, v9, v12
v_alignbit_b32 v8, v9, v6, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v5, v13, v11, vcc_lo
v_alignbit_b32 v11, v6, v4, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v7, v8, v9, vcc_lo
v_bfe_u32 v8, v5, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v11, v6, vcc_lo
v_alignbit_b32 v9, v5, v7, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v10, 0, v8
v_alignbit_b32 v7, v7, v6, 30
v_alignbit_b32 v4, v6, v4, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v9, v9, v10
v_xor_b32_e32 v6, v7, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v4, v4, v10
v_clz_i32_u32_e32 v11, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v11, 32, v11
v_sub_nc_u32_e32 v7, 31, v11
v_lshlrev_b32_e32 v13, 23, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v9, v9, v6, v7
v_alignbit_b32 v4, v6, v4, v7
v_lshrrev_b32_e32 v7, 29, v5
v_alignbit_b32 v6, v9, v4, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v7, 31, v7
v_lshrrev_b32_e32 v9, 9, v9
v_clz_i32_u32_e32 v10, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v12, 0.5, v7
v_min_u32_e32 v10, 32, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v12, v12, v13
v_sub_nc_u32_e32 v14, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v4, v6, v4, v14
v_or_b32_e32 v6, v9, v12
v_add_lshl_u32 v9, v10, v11, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v4, 9, v4
v_mul_f32_e32 v10, 0x3fc90fda, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v4, v9
v_fma_f32 v9, v6, 0x3fc90fda, -v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 0x33000000, v4
v_fmamk_f32 v6, v6, 0x33a22168, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v4, v4, v7
v_fmac_f32_e32 v6, 0x3fc90fda, v4
v_lshrrev_b32_e32 v5, 30, v5
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v4, v10, v6 :: v_dual_add_nc_u32 v5, v8, v5
.LBB0_2:
s_and_not1_saveexec_b32 s2, s4
v_mul_f32_e64 v4, 0x3f22f983, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v5, v4
v_fma_f32 v4, v5, 0xbfc90fda, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v5, 0xb3a22168, v4
v_fmamk_f32 v4, v5, 0xa7c234c4, v4
v_cvt_i32_f32_e32 v5, v5
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_mul_f32 v6, v4, v4 :: v_dual_and_b32 v9, 1, v5
s_mov_b32 s2, 0xb94c1982
s_mov_b32 s3, 0x37d75334
s_load_b64 s[0:1], s[0:1], 0x8
v_fmaak_f32 v7, s2, v6, 0x3c0881c4
v_cmp_eq_u32_e32 vcc_lo, 0, v9
v_xor_b32_e32 v3, v3, v0
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b32_e32 v5, 30, v5
v_fmaak_f32 v7, v6, v7, 0xbe2aaa9d
v_fmaak_f32 v8, s3, v6, 0xbab64f3b
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_and_b32_e32 v5, 0x80000000, v5
v_mul_f32_e32 v7, v6, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v8, v6, v8, 0x3d2aabf7
v_fmac_f32_e32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v8, v6, v8, 0xbf000004
v_fma_f32 v6, v6, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v6, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
v_xor3_b32 v3, v3, v5, v4
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPfS_, .Lfunc_end0-_Z3addPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
__global__ void add(float *a,float *b){
int id = blockIdx.x*blockDim.x+threadIdx.x;
b[id] = sinf(a[id]);
}
int main(){
int n;
float a[10],b[10];
printf("Enter n:");
scanf("%d",&n);
printf("Enter A:\n");
for(int i=0;i<n;i++)
scanf("%f",&a[i]);
float *d_a,*d_b;
int size = sizeof(float)*n;
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_b,size);
hipMemcpy(d_a,&a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,&b,size,hipMemcpyHostToDevice);
add<<<n,1>>>(d_a,d_b);
hipMemcpy(&b,d_b,size,hipMemcpyDeviceToHost);
for(int i=0;i<n;i++)
printf("%f ",b[i]);
printf("\n");
hipFree(d_a);
hipFree(d_b);
} | .text
.file "q4.hip"
.globl _Z18__device_stub__addPfS_ # -- Begin function _Z18__device_stub__addPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addPfS_,@function
_Z18__device_stub__addPfS_: # @_Z18__device_stub__addPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addPfS_, .Lfunc_end0-_Z18__device_stub__addPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $200, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr, %edi
callq puts@PLT
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 160(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 12(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
shll $2, %eax
movslq %eax, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 160(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 112(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 16(%rsp), %rsi
leaq 112(%rsp), %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 12(%rsp)
jle .LBB1_8
# %bb.6: # %.lr.ph21.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # %.lr.ph21
# =>This Inner Loop Header: Depth=1
movss 112(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
incq %rbx
movslq 12(%rsp), %rax
cmpq %rax, %rbx
jl .LBB1_7
.LBB1_8: # %._crit_edge22
movl $10, %edi
callq putchar@PLT
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPfS_,@object # @_Z3addPfS_
.section .rodata,"a",@progbits
.globl _Z3addPfS_
.p2align 3, 0x0
_Z3addPfS_:
.quad _Z18__device_stub__addPfS_
.size _Z3addPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter n:"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%f "
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPfS_"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter A:"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ BSSY B0, 0x7e0 ; /* 0x0000075000007945 */
/* 0x000fe20003800000 */
/*0090*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*00a0*/ FMUL R6, R2.reuse, 0.63661974668502807617 ; /* 0x3f22f98302067820 */
/* 0x044fe20000400000 */
/*00b0*/ FSETP.GE.AND P0, PT, |R2|, 105615, PT ; /* 0x47ce47800200780b */
/* 0x000fc60003f06200 */
/*00c0*/ F2I.NTZ R10, R6 ; /* 0x00000006000a7305 */
/* 0x000e300000203100 */
/*00d0*/ I2F R7, R10 ; /* 0x0000000a00077306 */
/* 0x001e240000201400 */
/*00e0*/ FFMA R8, R7, -1.5707962512969970703, R2 ; /* 0xbfc90fda07087823 */
/* 0x001fc80000000002 */
/*00f0*/ FFMA R8, R7, -7.5497894158615963534e-08, R8 ; /* 0xb3a2216807087823 */
/* 0x000fc80000000008 */
/*0100*/ FFMA R11, R7, -5.3903029534742383927e-15, R8 ; /* 0xa7c234c5070b7823 */
/* 0x000fe20000000008 */
/*0110*/ @!P0 BRA 0x7d0 ; /* 0x000006b000008947 */
/* 0x000fea0003800000 */
/*0120*/ FSETP.NEU.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f0d200 */
/*0130*/ @!P0 BRA 0x7b0 ; /* 0x0000067000008947 */
/* 0x000fea0003800000 */
/*0140*/ SHF.R.U32.HI R4, RZ, 0x17, R2 ; /* 0x00000017ff047819 */
/* 0x000fe20000011602 */
/*0150*/ IMAD.SHL.U32 R6, R2, 0x100, RZ ; /* 0x0000010002067824 */
/* 0x000fe200078e00ff */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0170*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0180*/ LOP3.LUT R5, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04057812 */
/* 0x000fe200078ec0ff */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*01a0*/ LOP3.LUT R11, R6, 0x80000000, RZ, 0xfc, !PT ; /* 0x80000000060b7812 */
/* 0x000fe200078efcff */
/*01b0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*01c0*/ IADD3 R5, R5, -0x80, RZ ; /* 0xffffff8005057810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fc60000000a00 */
/*01e0*/ SHF.R.U32.HI R12, RZ, 0x5, R5 ; /* 0x00000005ff0c7819 */
/* 0x000fe40000011605 */
/*01f0*/ IMAD.U32 R6, RZ, RZ, UR8 ; /* 0x00000008ff067e24 */
/* 0x000fe4000f8e00ff */
/*0200*/ IMAD.U32 R7, RZ, RZ, UR9 ; /* 0x00000009ff077e24 */
/* 0x000fca000f8e00ff */
/*0210*/ LDG.E.CONSTANT R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea2000c1e9900 */
/*0220*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe20007ffe0ff */
/*0230*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff1e03f */
/*0240*/ ISETP.EQ.AND P0, PT, R19.reuse, RZ, PT ; /* 0x000000ff1300720c */
/* 0x040fe40003f02270 */
/*0250*/ ISETP.EQ.AND P5, PT, R19.reuse, 0x4, PT ; /* 0x000000041300780c */
/* 0x040fe20003fa2270 */
/*0260*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0270*/ ISETP.EQ.AND P4, PT, R19.reuse, 0x8, PT ; /* 0x000000081300780c */
/* 0x040fe40003f82270 */
/*0280*/ ISETP.EQ.AND P3, PT, R19.reuse, 0xc, PT ; /* 0x0000000c1300780c */
/* 0x040fe40003f62270 */
/*0290*/ ISETP.EQ.AND P2, PT, R19, 0x10, PT ; /* 0x000000101300780c */
/* 0x000fc40003f42270 */
/*02a0*/ ISETP.EQ.AND P1, PT, R19.reuse, 0x14, PT ; /* 0x000000141300780c */
/* 0x040fe40003f22270 */
/*02b0*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.WIDE.U32 R8, R6, R11, RZ ; /* 0x0000000b06087225 */
/* 0x004fca00078e00ff */
/*02d0*/ IADD3 R8, P6, R8, R4, RZ ; /* 0x0000000408087210 */
/* 0x000fc80007fde0ff */
/*02e0*/ IADD3.X R4, R9, UR4, RZ, P6, !PT ; /* 0x0000000409047c10 */
/* 0x000fe2000b7fe4ff */
/*02f0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, R8.reuse ; /* 0x000000ffff0a0224 */
/* 0x100fe200078e0008 */
/*0300*/ ISETP.NE.AND P6, PT, R13, 0x6, PT ; /* 0x000000060d00780c */
/* 0x000fe20003fc5270 */
/*0310*/ @P5 IMAD.MOV.U32 R15, RZ, RZ, R8.reuse ; /* 0x000000ffff0f5224 */
/* 0x100fe400078e0008 */
/*0320*/ @P4 IMAD.MOV.U32 R16, RZ, RZ, R8.reuse ; /* 0x000000ffff104224 */
/* 0x100fe400078e0008 */
/*0330*/ @P3 IMAD.MOV.U32 R17, RZ, RZ, R8.reuse ; /* 0x000000ffff113224 */
/* 0x100fe400078e0008 */
/*0340*/ @P2 IMAD.MOV.U32 R18, RZ, RZ, R8.reuse ; /* 0x000000ffff122224 */
/* 0x100fe400078e0008 */
/*0350*/ @P1 IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e1224 */
/* 0x000fc800078e0008 */
/*0360*/ @P6 BRA 0x1f0 ; /* 0xfffffe8000006947 */
/* 0x000fea000383ffff */
/*0370*/ IADD3 R6, -R12, 0x6, RZ ; /* 0x000000060c067810 */
/* 0x000fe20007ffe1ff */
/*0380*/ BSSY B1, 0x6a0 ; /* 0x0000031000017945 */
/* 0x000fe80003800000 */
/*0390*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x000fca00078e00ff */
/*03a0*/ ISETP.EQ.AND P0, PT, R6.reuse, RZ, PT ; /* 0x000000ff0600720c */
/* 0x040fe40003f02270 */
/*03b0*/ ISETP.EQ.AND P3, PT, R6.reuse, 0x4, PT ; /* 0x000000040600780c */
/* 0x040fe40003f62270 */
/*03c0*/ ISETP.EQ.AND P4, PT, R6.reuse, 0x8, PT ; /* 0x000000080600780c */
/* 0x040fe40003f82270 */
/*03d0*/ ISETP.EQ.AND P2, PT, R6.reuse, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x040fe40003f42270 */
/*03e0*/ ISETP.EQ.AND P1, PT, R6, 0x10, PT ; /* 0x000000100600780c */
/* 0x000fca0003f22270 */
/*03f0*/ @P0 MOV R7, R10 ; /* 0x0000000a00070202 */
/* 0x000fe40000000f00 */
/*0400*/ @P3 IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff083224 */
/* 0x000fe200078e000a */
/*0410*/ ISETP.EQ.AND P0, PT, R6.reuse, 0x14, PT ; /* 0x000000140600780c */
/* 0x040fe20003f02270 */
/*0420*/ @P3 IMAD.MOV.U32 R7, RZ, RZ, R15.reuse ; /* 0x000000ffff073224 */
/* 0x100fe200078e000f */
/*0430*/ ISETP.EQ.AND P3, PT, R6.reuse, 0x18, PT ; /* 0x000000180600780c */
/* 0x040fe20003f62270 */
/*0440*/ @P4 IMAD.MOV.U32 R8, RZ, RZ, R15 ; /* 0x000000ffff084224 */
/* 0x000fe400078e000f */
/*0450*/ @P4 IMAD.MOV.U32 R7, RZ, RZ, R16.reuse ; /* 0x000000ffff074224 */
/* 0x100fe200078e0010 */
/*0460*/ ISETP.EQ.AND P4, PT, R6, 0x1c, PT ; /* 0x0000001c0600780c */
/* 0x000fe20003f82270 */
/*0470*/ @P2 IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff082224 */
/* 0x000fc400078e0010 */
/*0480*/ @P2 IMAD.MOV.U32 R7, RZ, RZ, R17.reuse ; /* 0x000000ffff072224 */
/* 0x100fe400078e0011 */
/*0490*/ @P1 IMAD.MOV.U32 R8, RZ, RZ, R17 ; /* 0x000000ffff081224 */
/* 0x000fe400078e0011 */
/*04a0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R18 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0012 */
/*04b0*/ LOP3.LUT P1, R6, R5, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f05067812 */
/* 0x000fe2000782c0ff */
/*04c0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R14 ; /* 0x000000ffff070224 */
/* 0x000fe400078e000e */
/*04d0*/ @P3 IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff073224 */
/* 0x000fe400078e0004 */
/*04e0*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, R18 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0012 */
/*04f0*/ @P3 MOV R8, R14 ; /* 0x0000000e00083202 */
/* 0x000fe20000000f00 */
/*0500*/ @P4 IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff084224 */
/* 0x000fc400078e0004 */
/*0510*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0007 */
/*0520*/ @!P1 BRA 0x690 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*0530*/ IADD3 R12, -R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007ffe1ff */
/*0540*/ IADD3 R7, -R6, 0x20, RZ ; /* 0x0000002006077810 */
/* 0x000fe40007ffe1ff */
/*0550*/ SHF.L.U32 R9, R8, R6, RZ ; /* 0x0000000608097219 */
/* 0x000fe200000006ff */
/*0560*/ IMAD.SHL.U32 R12, R12, 0x4, RZ ; /* 0x000000040c0c7824 */
/* 0x000fca00078e00ff */
/*0570*/ ISETP.EQ.AND P1, PT, R12.reuse, 0x4, PT ; /* 0x000000040c00780c */
/* 0x040fe40003f22270 */
/*0580*/ ISETP.EQ.AND P2, PT, R12.reuse, 0x8, PT ; /* 0x000000080c00780c */
/* 0x040fe40003f42270 */
/*0590*/ ISETP.EQ.AND P0, PT, R12.reuse, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x040fe40003f02270 */
/*05a0*/ ISETP.EQ.AND P3, PT, R12.reuse, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x040fe40003f62270 */
/*05b0*/ ISETP.EQ.AND P0, PT, R12, 0x10, PT ; /* 0x000000100c00780c */
/* 0x000fca0003f02270 */
/*05c0*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R15 ; /* 0x000000ffff0a1224 */
/* 0x000fe200078e000f */
/*05d0*/ ISETP.EQ.AND P1, PT, R12.reuse, 0x14, PT ; /* 0x000000140c00780c */
/* 0x040fe20003f22270 */
/*05e0*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R16 ; /* 0x000000ffff0a2224 */
/* 0x000fe200078e0010 */
/*05f0*/ ISETP.EQ.AND P2, PT, R12, 0x18, PT ; /* 0x000000180c00780c */
/* 0x000fc60003f42270 */
/*0600*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R17 ; /* 0x000000ffff0a3224 */
/* 0x000fe400078e0011 */
/*0610*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, R18 ; /* 0x000000ffff0a0224 */
/* 0x000fcc00078e0012 */
/*0620*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a1224 */
/* 0x000fe400078e000e */
/*0630*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a2224 */
/* 0x000fe200078e0004 */
/*0640*/ SHF.L.U32 R4, R5, R6, RZ ; /* 0x0000000605047219 */
/* 0x000fe400000006ff */
/*0650*/ SHF.R.U32.HI R5, RZ, R7.reuse, R8 ; /* 0x00000007ff057219 */
/* 0x080fe40000011608 */
/*0660*/ SHF.R.U32.HI R10, RZ, R7, R10 ; /* 0x00000007ff0a7219 */
/* 0x000fe4000001160a */
/*0670*/ IADD3 R5, R5, R4, RZ ; /* 0x0000000405057210 */
/* 0x000fc60007ffe0ff */
/*0680*/ IMAD.IADD R8, R10, 0x1, R9 ; /* 0x000000010a087824 */
/* 0x000fe400078e0209 */
/*0690*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06a0*/ SHF.L.U32.HI R9, R8.reuse, 0x2, R5 ; /* 0x0000000208097819 */
/* 0x040fe20000010605 */
/*06b0*/ IMAD.SHL.U32 R8, R8, 0x4, RZ ; /* 0x0000000408087824 */
/* 0x000fe200078e00ff */
/*06c0*/ LOP3.LUT P1, R2, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000002027812 */
/* 0x000fe4000782c0ff */
/*06d0*/ SHF.R.U32.HI R10, RZ, 0x1f, R9 ; /* 0x0000001fff0a7819 */
/* 0x000fc80000011609 */
/*06e0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*06f0*/ LEA.HI R10, R5, R10, RZ, 0x2 ; /* 0x0000000a050a7211 */
/* 0x000fd600078f10ff */
/*0700*/ @P0 LOP3.LUT R9, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff090212 */
/* 0x000fe400078e33ff */
/*0710*/ @P0 LOP3.LUT R8, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff080212 */
/* 0x000fe400078e33ff */
/*0720*/ @P0 LOP3.LUT R2, R2, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000002020812 */
/* 0x000fe400078e3cff */
/*0730*/ I2F.F64.S64 R6, R8 ; /* 0x0000000800067312 */
/* 0x000e240000301c00 */
/*0740*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0750*/ IMAD.MOV R2, RZ, RZ, -R10 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a0a */
/*0760*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a1224 */
/* 0x000fe200078e0002 */
/*0770*/ DMUL R6, R6, c[0x2][0x0] ; /* 0x0080000006067a28 */
/* 0x001e140000000000 */
/*0780*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */
/* 0x001e240000301000 */
/*0790*/ FSEL R11, R6, -R6, !P0 ; /* 0x80000006060b7208 */
/* 0x001fe20004000000 */
/*07a0*/ BRA 0x7d0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*07b0*/ FMUL R11, RZ, R2 ; /* 0x00000002ff0b7220 */
/* 0x000fe40000400000 */
/*07c0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*07d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT P1, RZ, R10.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x000000010aff7812 */
/* 0x040fe2000782c0ff */
/*07f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff057424 */
/* 0x000fe200078e00ff */
/*0800*/ LOP3.LUT P0, RZ, R10, 0x2, RZ, 0xc0, !PT ; /* 0x000000020aff7812 */
/* 0x000fe2000780c0ff */
/*0810*/ FMUL R6, R11.reuse, R11 ; /* 0x0000000b0b067220 */
/* 0x040fe20000400000 */
/*0820*/ FSEL R11, R11, 1, !P1 ; /* 0x3f8000000b0b7808 */
/* 0x000fe20004800000 */
/*0830*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff077424 */
/* 0x000fe200078e00ff */
/*0840*/ FSEL R5, R5, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb05057808 */
/* 0x000fe20004800000 */
/*0850*/ IMAD.MOV.U32 R2, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff027424 */
/* 0x000fc600078e00ff */
/*0860*/ FSEL R7, -R7, -0.4999999701976776123, !P1 ; /* 0xbeffffff07077808 */
/* 0x000fc60004800100 */
/*0870*/ @P1 IMAD.MOV.U32 R4, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff041424 */
/* 0x000fc800078e00ff */
/*0880*/ @P1 FFMA R2, R6.reuse, R4, -0.0013887860113754868507 ; /* 0xbab607ed06021423 */
/* 0x040fe40000000004 */
/*0890*/ FFMA R4, R11, R6, RZ ; /* 0x000000060b047223 */
/* 0x000fe400000000ff */
/*08a0*/ FFMA R2, R6, R2, R5 ; /* 0x0000000206027223 */
/* 0x000fc80000000005 */
/*08b0*/ FFMA R7, R6, R2, R7 ; /* 0x0000000206077223 */
/* 0x000fe20000000007 */
/*08c0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc600078210ff */
/*08d0*/ FFMA R7, R7, R4, R11 ; /* 0x0000000407077223 */
/* 0x000fe2000000000b */
/*08e0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fc600008f1403 */
/*08f0*/ @P0 FFMA R7, R7, -1, RZ ; /* 0xbf80000007070823 */
/* 0x000fca00000000ff */
/*0900*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0910*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0920*/ BRA 0x920; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPfS_
.globl _Z3addPfS_
.p2align 8
.type _Z3addPfS_,@function
_Z3addPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v3, 0x7fffffff, v0
v_cmpx_ngt_f32_e64 0x48000000, |v0|
s_xor_b32 s4, exec_lo, s3
s_cbranch_execz .LBB0_2
s_mov_b32 s2, 0x7fffff
v_mov_b32_e32 v6, 0
v_and_or_b32 v14, v3, s2, 0x800000
v_lshrrev_b32_e32 v11, 23, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, v14, 0xfe5163ab, 0
v_add_nc_u32_e32 v12, 0xffffff88, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v12
v_mad_u64_u32 v[7:8], null, v14, 0x3c439041, v[5:6]
v_cndmask_b32_e64 v13, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v5, v8
v_add_nc_u32_e32 v13, v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v14, 0xdb629599, v[5:6]
v_cmp_lt_u32_e64 s2, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v15, 0, 0xffffffe0, s2
v_dual_mov_b32 v5, v9 :: v_dual_cndmask_b32 v4, v8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v15, v15, v13
v_mad_u64_u32 v[9:10], null, v14, 0xf534ddc0, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v15
v_mov_b32_e32 v5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, v9, v7, vcc_lo
v_mad_u64_u32 v[10:11], null, v14, 0xfc2757d1, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, v7, v4, s2
v_mov_b32_e32 v5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v14, 0x4e441529, v[5:6]
v_mov_b32_e32 v5, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, v14, 0xa2f9836e, v[5:6]
v_cndmask_b32_e64 v5, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v6, v11, v9 :: v_dual_add_nc_u32 v5, v5, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v12, v12, v10 :: v_dual_cndmask_b32 v11, v13, v11
v_cndmask_b32_e32 v10, v10, v8, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v9, v12, v6, s2
v_cndmask_b32_e64 v11, v11, v12, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, v6, v10, s2
v_sub_nc_u32_e32 v12, 32, v5
v_cndmask_b32_e64 v10, v10, v7, s2
v_cndmask_b32_e64 v11, v11, v9, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, v9, v6, s3
v_cndmask_b32_e64 v6, v6, v10, s3
v_cndmask_b32_e64 v4, v10, v4, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v11, v9, v12
v_alignbit_b32 v8, v9, v6, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v5, v13, v11, vcc_lo
v_alignbit_b32 v11, v6, v4, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v7, v8, v9, vcc_lo
v_bfe_u32 v8, v5, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v11, v6, vcc_lo
v_alignbit_b32 v9, v5, v7, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v10, 0, v8
v_alignbit_b32 v7, v7, v6, 30
v_alignbit_b32 v4, v6, v4, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v9, v9, v10
v_xor_b32_e32 v6, v7, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v4, v4, v10
v_clz_i32_u32_e32 v11, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v11, 32, v11
v_sub_nc_u32_e32 v7, 31, v11
v_lshlrev_b32_e32 v13, 23, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v9, v9, v6, v7
v_alignbit_b32 v4, v6, v4, v7
v_lshrrev_b32_e32 v7, 29, v5
v_alignbit_b32 v6, v9, v4, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v7, 31, v7
v_lshrrev_b32_e32 v9, 9, v9
v_clz_i32_u32_e32 v10, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v12, 0.5, v7
v_min_u32_e32 v10, 32, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v12, v12, v13
v_sub_nc_u32_e32 v14, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v4, v6, v4, v14
v_or_b32_e32 v6, v9, v12
v_add_lshl_u32 v9, v10, v11, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v4, 9, v4
v_mul_f32_e32 v10, 0x3fc90fda, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v4, v9
v_fma_f32 v9, v6, 0x3fc90fda, -v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 0x33000000, v4
v_fmamk_f32 v6, v6, 0x33a22168, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v4, v4, v7
v_fmac_f32_e32 v6, 0x3fc90fda, v4
v_lshrrev_b32_e32 v5, 30, v5
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v4, v10, v6 :: v_dual_add_nc_u32 v5, v8, v5
.LBB0_2:
s_and_not1_saveexec_b32 s2, s4
v_mul_f32_e64 v4, 0x3f22f983, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v5, v4
v_fma_f32 v4, v5, 0xbfc90fda, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v5, 0xb3a22168, v4
v_fmamk_f32 v4, v5, 0xa7c234c4, v4
v_cvt_i32_f32_e32 v5, v5
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_mul_f32 v6, v4, v4 :: v_dual_and_b32 v9, 1, v5
s_mov_b32 s2, 0xb94c1982
s_mov_b32 s3, 0x37d75334
s_load_b64 s[0:1], s[0:1], 0x8
v_fmaak_f32 v7, s2, v6, 0x3c0881c4
v_cmp_eq_u32_e32 vcc_lo, 0, v9
v_xor_b32_e32 v3, v3, v0
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b32_e32 v5, 30, v5
v_fmaak_f32 v7, v6, v7, 0xbe2aaa9d
v_fmaak_f32 v8, s3, v6, 0xbab64f3b
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_and_b32_e32 v5, 0x80000000, v5
v_mul_f32_e32 v7, v6, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v8, v6, v8, 0x3d2aabf7
v_fmac_f32_e32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v8, v6, v8, 0xbf000004
v_fma_f32 v6, v6, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v6, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
v_xor3_b32 v3, v3, v5, v4
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPfS_, .Lfunc_end0-_Z3addPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f2cca_00000000-6_q4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addPfS_PfS_
.type _Z24__device_stub__Z3addPfS_PfS_, @function
_Z24__device_stub__Z3addPfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3addPfS_PfS_, .-_Z24__device_stub__Z3addPfS_PfS_
.globl _Z3addPfS_
.type _Z3addPfS_, @function
_Z3addPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPfS_, .-_Z3addPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter n:"
.LC1:
.string "%d"
.LC2:
.string "Enter A:\n"
.LC3:
.string "%f"
.LC4:
.string "%f "
.LC5:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $144, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 4(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %eax
testl %eax, %eax
jle .L12
leaq 48(%rsp), %rbp
movl $0, %ebx
leaq .LC3(%rip), %r12
.L13:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 4(%rsp), %eax
addq $4, %rbp
cmpl %ebx, %eax
jg .L13
.L12:
sall $2, %eax
movslq %eax, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl 4(%rsp), %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
leaq 96(%rsp), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
cmpl $0, 4(%rsp)
jle .L15
movl $0, %ebx
leaq .LC4(%rip), %rbp
.L16:
pxor %xmm0, %xmm0
cvtss2sd 96(%rsp,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jg .L16
.L15:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z24__device_stub__Z3addPfS_PfS_
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "q4.hip"
.globl _Z18__device_stub__addPfS_ # -- Begin function _Z18__device_stub__addPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addPfS_,@function
_Z18__device_stub__addPfS_: # @_Z18__device_stub__addPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addPfS_, .Lfunc_end0-_Z18__device_stub__addPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $200, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr, %edi
callq puts@PLT
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 160(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 12(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
shll $2, %eax
movslq %eax, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 160(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 112(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 16(%rsp), %rsi
leaq 112(%rsp), %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 12(%rsp)
jle .LBB1_8
# %bb.6: # %.lr.ph21.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # %.lr.ph21
# =>This Inner Loop Header: Depth=1
movss 112(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
incq %rbx
movslq 12(%rsp), %rax
cmpq %rax, %rbx
jl .LBB1_7
.LBB1_8: # %._crit_edge22
movl $10, %edi
callq putchar@PLT
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPfS_,@object # @_Z3addPfS_
.section .rodata,"a",@progbits
.globl _Z3addPfS_
.p2align 3, 0x0
_Z3addPfS_:
.quad _Z18__device_stub__addPfS_
.size _Z3addPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter n:"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%f "
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPfS_"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter A:"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //seqRuntime.cu
#include <iostream>
using namespace std;
#include <thrust/reduce.h>
#include <thrust/sequence.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
__global__ void fillKernel(int *a, int n)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if (tid < n) a[tid] = tid;
}
void fill(int* d_a, int n)
{
int nThreadsPerBlock= 512;
int nBlocks= n/nThreadsPerBlock + ((n%nThreadsPerBlock)?1:0);
fillKernel <<< nBlocks, nThreadsPerBlock >>> (d_a, n);
}
int main()
{
const int N=50000;
// task 1: create the array
thrust::device_vector<int> a(N);
// task 2: fill the array using the runtime
fill(thrust::raw_pointer_cast(&a[0]),N);
// task 3: calculate the sum of the array
int sumA= thrust::reduce(a.begin(),a.end(), 0);
// task 4: calculate the sum of 0 .. N-1
int sumCheck=0;
for(int i=0; i < N; i++) sumCheck += i;
// task 5: check the results agree
if(sumA == sumCheck) cout << "Test Succeeded!" << endl;
else { cerr << "Test FAILED!" << endl; return(1);}
return(0);
} | //seqRuntime.cu
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#include <thrust/reduce.h>
#include <thrust/sequence.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
__global__ void fillKernel(int *a, int n)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if (tid < n) a[tid] = tid;
}
void fill(int* d_a, int n)
{
int nThreadsPerBlock= 512;
int nBlocks= n/nThreadsPerBlock + ((n%nThreadsPerBlock)?1:0);
fillKernel <<< nBlocks, nThreadsPerBlock >>> (d_a, n);
}
int main()
{
const int N=50000;
// task 1: create the array
thrust::device_vector<int> a(N);
// task 2: fill the array using the runtime
fill(thrust::raw_pointer_cast(&a[0]),N);
// task 3: calculate the sum of the array
int sumA= thrust::reduce(a.begin(),a.end(), 0);
// task 4: calculate the sum of 0 .. N-1
int sumCheck=0;
for(int i=0; i < N; i++) sumCheck += i;
// task 5: check the results agree
if(sumA == sumCheck) cout << "Test Succeeded!" << endl;
else { cerr << "Test FAILED!" << endl; return(1);}
return(0);
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ComputeResidualsKernel (double *VthetaRes, double *VMed, int nsec, int nrad, double *Vtheta)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec)
VthetaRes[i*nsec + j] = Vtheta[i*nsec + j]-VMed[i];
} | code for sm_80
Function : _Z22ComputeResidualsKernelPdS_iiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R5, c[0x0][0x170], R0 ; /* 0x00005c0005007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R5, R9, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R9.reuse, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x0c0fe400078e0209 */
/*00f0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0100*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ IMAD.WIDE R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fe200078e0209 */
/*0120*/ DADD R6, -R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000102 */
/*0130*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ComputeResidualsKernel (double *VthetaRes, double *VMed, int nsec, int nrad, double *Vtheta)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec)
VthetaRes[i*nsec + j] = Vtheta[i*nsec + j]-VMed[i];
} | .file "tmpxft_0007a7e5_00000000-6_ComputeResidualsKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z22ComputeResidualsKernelPdS_iiS_PdS_iiS_
.type _Z48__device_stub__Z22ComputeResidualsKernelPdS_iiS_PdS_iiS_, @function
_Z48__device_stub__Z22ComputeResidualsKernelPdS_iiS_PdS_iiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22ComputeResidualsKernelPdS_iiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z22ComputeResidualsKernelPdS_iiS_PdS_iiS_, .-_Z48__device_stub__Z22ComputeResidualsKernelPdS_iiS_PdS_iiS_
.globl _Z22ComputeResidualsKernelPdS_iiS_
.type _Z22ComputeResidualsKernelPdS_iiS_, @function
_Z22ComputeResidualsKernelPdS_iiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z22ComputeResidualsKernelPdS_iiS_PdS_iiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22ComputeResidualsKernelPdS_iiS_, .-_Z22ComputeResidualsKernelPdS_iiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22ComputeResidualsKernelPdS_iiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22ComputeResidualsKernelPdS_iiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ComputeResidualsKernel (double *VthetaRes, double *VMed, int nsec, int nrad, double *Vtheta)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec)
VthetaRes[i*nsec + j] = Vtheta[i*nsec + j]-VMed[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeResidualsKernel (double *VthetaRes, double *VMed, int nsec, int nrad, double *Vtheta)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec)
VthetaRes[i*nsec + j] = Vtheta[i*nsec + j]-VMed[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeResidualsKernel (double *VthetaRes, double *VMed, int nsec, int nrad, double *Vtheta)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec)
VthetaRes[i*nsec + j] = Vtheta[i*nsec + j]-VMed[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22ComputeResidualsKernelPdS_iiS_
.globl _Z22ComputeResidualsKernelPdS_iiS_
.p2align 8
.type _Z22ComputeResidualsKernelPdS_iiS_,@function
_Z22ComputeResidualsKernelPdS_iiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[0:1], v[0:1], off
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[4:5], -v[0:1]
global_store_b64 v[2:3], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22ComputeResidualsKernelPdS_iiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22ComputeResidualsKernelPdS_iiS_, .Lfunc_end0-_Z22ComputeResidualsKernelPdS_iiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22ComputeResidualsKernelPdS_iiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22ComputeResidualsKernelPdS_iiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeResidualsKernel (double *VthetaRes, double *VMed, int nsec, int nrad, double *Vtheta)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec)
VthetaRes[i*nsec + j] = Vtheta[i*nsec + j]-VMed[i];
} | .text
.file "ComputeResidualsKernel.hip"
.globl _Z37__device_stub__ComputeResidualsKernelPdS_iiS_ # -- Begin function _Z37__device_stub__ComputeResidualsKernelPdS_iiS_
.p2align 4, 0x90
.type _Z37__device_stub__ComputeResidualsKernelPdS_iiS_,@function
_Z37__device_stub__ComputeResidualsKernelPdS_iiS_: # @_Z37__device_stub__ComputeResidualsKernelPdS_iiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22ComputeResidualsKernelPdS_iiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__ComputeResidualsKernelPdS_iiS_, .Lfunc_end0-_Z37__device_stub__ComputeResidualsKernelPdS_iiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22ComputeResidualsKernelPdS_iiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22ComputeResidualsKernelPdS_iiS_,@object # @_Z22ComputeResidualsKernelPdS_iiS_
.section .rodata,"a",@progbits
.globl _Z22ComputeResidualsKernelPdS_iiS_
.p2align 3, 0x0
_Z22ComputeResidualsKernelPdS_iiS_:
.quad _Z37__device_stub__ComputeResidualsKernelPdS_iiS_
.size _Z22ComputeResidualsKernelPdS_iiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22ComputeResidualsKernelPdS_iiS_"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__ComputeResidualsKernelPdS_iiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22ComputeResidualsKernelPdS_iiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22ComputeResidualsKernelPdS_iiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R5, c[0x0][0x170], R0 ; /* 0x00005c0005007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R5, R9, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R9.reuse, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x0c0fe400078e0209 */
/*00f0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0100*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ IMAD.WIDE R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fe200078e0209 */
/*0120*/ DADD R6, -R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000102 */
/*0130*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22ComputeResidualsKernelPdS_iiS_
.globl _Z22ComputeResidualsKernelPdS_iiS_
.p2align 8
.type _Z22ComputeResidualsKernelPdS_iiS_,@function
_Z22ComputeResidualsKernelPdS_iiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[0:1], v[0:1], off
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[4:5], -v[0:1]
global_store_b64 v[2:3], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22ComputeResidualsKernelPdS_iiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22ComputeResidualsKernelPdS_iiS_, .Lfunc_end0-_Z22ComputeResidualsKernelPdS_iiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22ComputeResidualsKernelPdS_iiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22ComputeResidualsKernelPdS_iiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007a7e5_00000000-6_ComputeResidualsKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z22ComputeResidualsKernelPdS_iiS_PdS_iiS_
.type _Z48__device_stub__Z22ComputeResidualsKernelPdS_iiS_PdS_iiS_, @function
_Z48__device_stub__Z22ComputeResidualsKernelPdS_iiS_PdS_iiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22ComputeResidualsKernelPdS_iiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z22ComputeResidualsKernelPdS_iiS_PdS_iiS_, .-_Z48__device_stub__Z22ComputeResidualsKernelPdS_iiS_PdS_iiS_
.globl _Z22ComputeResidualsKernelPdS_iiS_
.type _Z22ComputeResidualsKernelPdS_iiS_, @function
_Z22ComputeResidualsKernelPdS_iiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z22ComputeResidualsKernelPdS_iiS_PdS_iiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22ComputeResidualsKernelPdS_iiS_, .-_Z22ComputeResidualsKernelPdS_iiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22ComputeResidualsKernelPdS_iiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22ComputeResidualsKernelPdS_iiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ComputeResidualsKernel.hip"
.globl _Z37__device_stub__ComputeResidualsKernelPdS_iiS_ # -- Begin function _Z37__device_stub__ComputeResidualsKernelPdS_iiS_
.p2align 4, 0x90
.type _Z37__device_stub__ComputeResidualsKernelPdS_iiS_,@function
_Z37__device_stub__ComputeResidualsKernelPdS_iiS_: # @_Z37__device_stub__ComputeResidualsKernelPdS_iiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22ComputeResidualsKernelPdS_iiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__ComputeResidualsKernelPdS_iiS_, .Lfunc_end0-_Z37__device_stub__ComputeResidualsKernelPdS_iiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22ComputeResidualsKernelPdS_iiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22ComputeResidualsKernelPdS_iiS_,@object # @_Z22ComputeResidualsKernelPdS_iiS_
.section .rodata,"a",@progbits
.globl _Z22ComputeResidualsKernelPdS_iiS_
.p2align 3, 0x0
_Z22ComputeResidualsKernelPdS_iiS_:
.quad _Z37__device_stub__ComputeResidualsKernelPdS_iiS_
.size _Z22ComputeResidualsKernelPdS_iiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22ComputeResidualsKernelPdS_iiS_"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__ComputeResidualsKernelPdS_iiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22ComputeResidualsKernelPdS_iiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
using namespace std;
__global__ void minimum(int *input)
{
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0)
{
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
if(input[first] > input[second])
{
input[first] = input[second];
}
}
step_size *= 2;
number_of_threads /=2;
}
}
__global__ void sum(int *input)
{
int step_size = 1;
int number_of_threads = blockDim.x;
int tid = threadIdx.x;
while(number_of_threads > 0)
{
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
input[first] += input[second];
}
step_size *=2;
number_of_threads /= 2;
}
}
int main()
{
int n;
cout<<"Enter no of elements"<<"\n";
cin>>n;
srand(n);
int *arr = new int[n];
for(int i=0;i<n;i++)
{
arr[i] = rand();
}
for(int i=0;i<n;i++)
{
cout<<arr[i]<<" ";
}
cout<<"\n";
int size = n*sizeof(int);
int *arr_d,result1;
cudaMalloc(&arr_d,size);
cudaMemcpy(arr_d,arr,size,cudaMemcpyHostToDevice);
minimum<<<1,n/2>>>(arr_d);
cudaMemcpy(&result1,arr_d,sizeof(int),cudaMemcpyDeviceToHost);
cout<<"Minimum Element = "<<result1;
cudaFree(arr_d);
int *arr_sum,result2;
cudaMalloc(&arr_sum,size);
cudaMemcpy(arr_sum,arr,size,cudaMemcpyHostToDevice);
sum<<<1,n/2>>>(arr_sum);
cudaMemcpy(&result2,arr_sum,size,cudaMemcpyDeviceToHost);
cout<<"Sum = "<<result2;
cudaFree(arr_sum);
return 0;
} | code for sm_80
Function : _Z3sumPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0050*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0060*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.SHL.U32 R6, R8, 0x2, RZ ; /* 0x0000000208067824 */
/* 0x001fe400078e00ff */
/*0090*/ ISETP.GE.AND P0, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fe2000bf06270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*00b0*/ BSSY B0, 0x180 ; /* 0x000000c000007945 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fcc000bf25270 */
/*00d0*/ @P0 BRA 0x170 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R4, R6, UR5, RZ ; /* 0x0000000506047c24 */
/* 0x000fca000f8e02ff */
/*0100*/ IADD3 R2, R4, UR5, RZ ; /* 0x0000000504027c10 */
/* 0x000fc8000fffe0ff */
/*0110*/ IMAD.WIDE R4, R4, R3, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0203 */
/*0120*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*0130*/ LDG.E R0, [R4.64] ; /* 0x0000000604007981 */
/* 0x000eaa000c1e1900 */
/*0140*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea4000c1e1900 */
/*0150*/ IMAD.IADD R7, R0, 0x1, R3 ; /* 0x0000000100077824 */
/* 0x004fca00078e0203 */
/*0160*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e4000c101906 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ USHF.L.U32 UR5, UR5, 0x1, URZ ; /* 0x0000000105057899 */
/* 0x000fe2000800063f */
/*0190*/ @P1 BRA 0x90 ; /* 0xfffffef000001947 */
/* 0x000fea000383ffff */
/*01a0*/ NOP ; /* 0x0000000000007918 */
/* 0x000fc20000000000 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7minimumPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.SHL.U32 R0, R8, 0x2, RZ ; /* 0x0000000208007824 */
/* 0x001fe400078e00ff */
/*0090*/ ISETP.GE.AND P1, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fe2000bf26270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*00b0*/ BSSY B0, 0x170 ; /* 0x000000b000007945 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fcc000bf05270 */
/*00d0*/ @P1 BRA 0x160 ; /* 0x0000008000001947 */
/* 0x001fea0003800000 */
/*00e0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R4, R0, R7, RZ ; /* 0x0000000700047224 */
/* 0x000fd200078e02ff */
/*0100*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0110*/ LDG.E R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R2, R7, 0x4, R4 ; /* 0x0000000407027825 */
/* 0x000fcc00078e0204 */
/*0130*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea4000c1e1900 */
/*0140*/ ISETP.GT.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x004fda0003f24270 */
/*0150*/ @P1 STG.E [R4.64], R3 ; /* 0x0000000304001986 */
/* 0x0001e4000c101906 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ SHF.L.U32 R7, R7, 0x1, RZ ; /* 0x0000000107077819 */
/* 0x000fe200000006ff */
/*0180*/ @P0 BRA 0x90 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
using namespace std;
__global__ void minimum(int *input)
{
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0)
{
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
if(input[first] > input[second])
{
input[first] = input[second];
}
}
step_size *= 2;
number_of_threads /=2;
}
}
__global__ void sum(int *input)
{
int step_size = 1;
int number_of_threads = blockDim.x;
int tid = threadIdx.x;
while(number_of_threads > 0)
{
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
input[first] += input[second];
}
step_size *=2;
number_of_threads /= 2;
}
}
int main()
{
int n;
cout<<"Enter no of elements"<<"\n";
cin>>n;
srand(n);
int *arr = new int[n];
for(int i=0;i<n;i++)
{
arr[i] = rand();
}
for(int i=0;i<n;i++)
{
cout<<arr[i]<<" ";
}
cout<<"\n";
int size = n*sizeof(int);
int *arr_d,result1;
cudaMalloc(&arr_d,size);
cudaMemcpy(arr_d,arr,size,cudaMemcpyHostToDevice);
minimum<<<1,n/2>>>(arr_d);
cudaMemcpy(&result1,arr_d,sizeof(int),cudaMemcpyDeviceToHost);
cout<<"Minimum Element = "<<result1;
cudaFree(arr_d);
int *arr_sum,result2;
cudaMalloc(&arr_sum,size);
cudaMemcpy(arr_sum,arr,size,cudaMemcpyHostToDevice);
sum<<<1,n/2>>>(arr_sum);
cudaMemcpy(&result2,arr_sum,size,cudaMemcpyDeviceToHost);
cout<<"Sum = "<<result2;
cudaFree(arr_sum);
return 0;
} | .file "tmpxft_00000062_00000000-6_parallelreduction.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z7minimumPiPi
.type _Z26__device_stub__Z7minimumPiPi, @function
_Z26__device_stub__Z7minimumPiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7minimumPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z7minimumPiPi, .-_Z26__device_stub__Z7minimumPiPi
.globl _Z7minimumPi
.type _Z7minimumPi, @function
_Z7minimumPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7minimumPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z7minimumPi, .-_Z7minimumPi
.globl _Z22__device_stub__Z3sumPiPi
.type _Z22__device_stub__Z3sumPiPi, @function
_Z22__device_stub__Z3sumPiPi:
.LFB3696:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3sumPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z22__device_stub__Z3sumPiPi, .-_Z22__device_stub__Z3sumPiPi
.globl _Z3sumPi
.type _Z3sumPi, @function
_Z3sumPi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3sumPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z3sumPi, .-_Z3sumPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter no of elements"
.LC1:
.string "\n"
.LC2:
.string " "
.LC3:
.string "Minimum Element = "
.LC4:
.string "Sum = "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 8(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 8(%rsp), %edi
call srand@PLT
movslq 8(%rsp), %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L20
salq $2, %rdi
call _Znam@PLT
movq %rax, %rbp
movl $0, %ebx
cmpl $0, 8(%rsp)
jle .L22
.L21:
call rand@PLT
movl %eax, 0(%rbp,%rbx,4)
movl 8(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jg .L21
testl %eax, %eax
jle .L22
movl $0, %ebx
leaq _ZSt4cout(%rip), %r13
leaq .LC2(%rip), %r12
.L24:
movl 0(%rbp,%rbx,4), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpl %ebx, 8(%rsp)
jg .L24
.L22:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl 8(%rsp), %eax
leal 0(,%rax,4), %ebx
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 8(%rsp), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L25:
leaq 12(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %esi
call _ZNSolsEi@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 8(%rsp), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L26:
leaq 44(%rsp), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 44(%rsp), %esi
call _ZNSolsEi@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L23
call __stack_chk_fail@PLT
.L23:
call __cxa_throw_bad_array_new_length@PLT
.L33:
movq 16(%rsp), %rdi
call _Z26__device_stub__Z7minimumPiPi
jmp .L25
.L34:
movq 24(%rsp), %rdi
call _Z22__device_stub__Z3sumPiPi
jmp .L26
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z3sumPi"
.LC6:
.string "_Z7minimumPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7minimumPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
using namespace std;
__global__ void minimum(int *input)
{
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0)
{
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
if(input[first] > input[second])
{
input[first] = input[second];
}
}
step_size *= 2;
number_of_threads /=2;
}
}
__global__ void sum(int *input)
{
int step_size = 1;
int number_of_threads = blockDim.x;
int tid = threadIdx.x;
while(number_of_threads > 0)
{
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
input[first] += input[second];
}
step_size *=2;
number_of_threads /= 2;
}
}
int main()
{
int n;
cout<<"Enter no of elements"<<"\n";
cin>>n;
srand(n);
int *arr = new int[n];
for(int i=0;i<n;i++)
{
arr[i] = rand();
}
for(int i=0;i<n;i++)
{
cout<<arr[i]<<" ";
}
cout<<"\n";
int size = n*sizeof(int);
int *arr_d,result1;
cudaMalloc(&arr_d,size);
cudaMemcpy(arr_d,arr,size,cudaMemcpyHostToDevice);
minimum<<<1,n/2>>>(arr_d);
cudaMemcpy(&result1,arr_d,sizeof(int),cudaMemcpyDeviceToHost);
cout<<"Minimum Element = "<<result1;
cudaFree(arr_d);
int *arr_sum,result2;
cudaMalloc(&arr_sum,size);
cudaMemcpy(arr_sum,arr,size,cudaMemcpyHostToDevice);
sum<<<1,n/2>>>(arr_sum);
cudaMemcpy(&result2,arr_sum,size,cudaMemcpyDeviceToHost);
cout<<"Sum = "<<result2;
cudaFree(arr_sum);
return 0;
} | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
__global__ void minimum(int *input)
{
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0)
{
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
if(input[first] > input[second])
{
input[first] = input[second];
}
}
step_size *= 2;
number_of_threads /=2;
}
}
__global__ void sum(int *input)
{
int step_size = 1;
int number_of_threads = blockDim.x;
int tid = threadIdx.x;
while(number_of_threads > 0)
{
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
input[first] += input[second];
}
step_size *=2;
number_of_threads /= 2;
}
}
int main()
{
int n;
cout<<"Enter no of elements"<<"\n";
cin>>n;
srand(n);
int *arr = new int[n];
for(int i=0;i<n;i++)
{
arr[i] = rand();
}
for(int i=0;i<n;i++)
{
cout<<arr[i]<<" ";
}
cout<<"\n";
int size = n*sizeof(int);
int *arr_d,result1;
hipMalloc(&arr_d,size);
hipMemcpy(arr_d,arr,size,hipMemcpyHostToDevice);
minimum<<<1,n/2>>>(arr_d);
hipMemcpy(&result1,arr_d,sizeof(int),hipMemcpyDeviceToHost);
cout<<"Minimum Element = "<<result1;
hipFree(arr_d);
int *arr_sum,result2;
hipMalloc(&arr_sum,size);
hipMemcpy(arr_sum,arr,size,hipMemcpyHostToDevice);
sum<<<1,n/2>>>(arr_sum);
hipMemcpy(&result2,arr_sum,size,hipMemcpyDeviceToHost);
cout<<"Sum = "<<result2;
hipFree(arr_sum);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
__global__ void minimum(int *input)
{
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0)
{
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
if(input[first] > input[second])
{
input[first] = input[second];
}
}
step_size *= 2;
number_of_threads /=2;
}
}
__global__ void sum(int *input)
{
int step_size = 1;
int number_of_threads = blockDim.x;
int tid = threadIdx.x;
while(number_of_threads > 0)
{
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
input[first] += input[second];
}
step_size *=2;
number_of_threads /= 2;
}
}
int main()
{
int n;
cout<<"Enter no of elements"<<"\n";
cin>>n;
srand(n);
int *arr = new int[n];
for(int i=0;i<n;i++)
{
arr[i] = rand();
}
for(int i=0;i<n;i++)
{
cout<<arr[i]<<" ";
}
cout<<"\n";
int size = n*sizeof(int);
int *arr_d,result1;
hipMalloc(&arr_d,size);
hipMemcpy(arr_d,arr,size,hipMemcpyHostToDevice);
minimum<<<1,n/2>>>(arr_d);
hipMemcpy(&result1,arr_d,sizeof(int),hipMemcpyDeviceToHost);
cout<<"Minimum Element = "<<result1;
hipFree(arr_d);
int *arr_sum,result2;
hipMalloc(&arr_sum,size);
hipMemcpy(arr_sum,arr,size,hipMemcpyHostToDevice);
sum<<<1,n/2>>>(arr_sum);
hipMemcpy(&result2,arr_sum,size,hipMemcpyDeviceToHost);
cout<<"Sum = "<<result2;
hipFree(arr_sum);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7minimumPi
.globl _Z7minimumPi
.p2align 8
.type _Z7minimumPi,@function
_Z7minimumPi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 1, v0
s_and_b32 s3, 0xffff, s2
s_mov_b32 s2, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_lshl_b32 s2, s2, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_cbranch_scc0 .LBB0_6
.LBB0_3:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v1, v3, s2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v5, v2 :: v_dual_add_nc_u32 v4, s2, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_b32 v6, v[1:2], off
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v6, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
global_store_b32 v[1:2], v4, off
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7minimumPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7minimumPi, .Lfunc_end0-_Z7minimumPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3sumPi
.globl _Z3sumPi
.p2align 8
.type _Z3sumPi,@function
_Z3sumPi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB1_5
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 1, v0
s_and_b32 s3, 0xffff, s2
s_mov_b32 s2, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_lshl_b32 s2, s2, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_cbranch_scc0 .LBB1_5
.LBB1_3:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB1_2
v_mul_lo_u32 v2, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, s2, v2
v_mov_b32_e32 v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
global_store_b32 v[2:3], v4, off
s_branch .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3sumPi, .Lfunc_end1-_Z3sumPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7minimumPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z7minimumPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z3sumPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
__global__ void minimum(int *input)
{
int tid = threadIdx.x;
int step_size = 1;
int number_of_threads = blockDim.x;
while(number_of_threads > 0)
{
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
if(input[first] > input[second])
{
input[first] = input[second];
}
}
step_size *= 2;
number_of_threads /=2;
}
}
__global__ void sum(int *input)
{
int step_size = 1;
int number_of_threads = blockDim.x;
int tid = threadIdx.x;
while(number_of_threads > 0)
{
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
input[first] += input[second];
}
step_size *=2;
number_of_threads /= 2;
}
}
int main()
{
int n;
cout<<"Enter no of elements"<<"\n";
cin>>n;
srand(n);
int *arr = new int[n];
for(int i=0;i<n;i++)
{
arr[i] = rand();
}
for(int i=0;i<n;i++)
{
cout<<arr[i]<<" ";
}
cout<<"\n";
int size = n*sizeof(int);
int *arr_d,result1;
hipMalloc(&arr_d,size);
hipMemcpy(arr_d,arr,size,hipMemcpyHostToDevice);
minimum<<<1,n/2>>>(arr_d);
hipMemcpy(&result1,arr_d,sizeof(int),hipMemcpyDeviceToHost);
cout<<"Minimum Element = "<<result1;
hipFree(arr_d);
int *arr_sum,result2;
hipMalloc(&arr_sum,size);
hipMemcpy(arr_sum,arr,size,hipMemcpyHostToDevice);
sum<<<1,n/2>>>(arr_sum);
hipMemcpy(&result2,arr_sum,size,hipMemcpyDeviceToHost);
cout<<"Sum = "<<result2;
hipFree(arr_sum);
return 0;
} | .text
.file "parallelreduction.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__minimumPi # -- Begin function _Z22__device_stub__minimumPi
.p2align 4, 0x90
.type _Z22__device_stub__minimumPi,@function
_Z22__device_stub__minimumPi: # @_Z22__device_stub__minimumPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7minimumPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z22__device_stub__minimumPi, .Lfunc_end0-_Z22__device_stub__minimumPi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__sumPi # -- Begin function _Z18__device_stub__sumPi
.p2align 4, 0x90
.type _Z18__device_stub__sumPi,@function
_Z18__device_stub__sumPi: # @_Z18__device_stub__sumPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3sumPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z18__device_stub__sumPi, .Lfunc_end1-_Z18__device_stub__sumPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 12(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl 12(%rsp), %edi
callq srand
movslq 12(%rsp), %rbx
leaq (,%rbx,4), %rax
testq %rbx, %rbx
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
movq %rax, %r14
testq %rbx, %rbx
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%r14,%rbx,4)
incq %rbx
movslq 12(%rsp), %rax
cmpq %rax, %rbx
jl .LBB2_2
.LBB2_3: # %.preheader
cmpl $0, 12(%rsp)
jle .LBB2_6
# %bb.4: # %.lr.ph39.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_5: # %.lr.ph39
# =>This Inner Loop Header: Depth=1
movl (%r14,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
movslq 12(%rsp), %rax
cmpq %rax, %rbx
jl .LBB2_5
.LBB2_6: # %._crit_edge
movabsq $4294967296, %r15 # imm = 0x100000000
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 12(%rsp), %eax
shll $2, %eax
movslq %eax, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
movl %eax, %edx
shrl $31, %edx
addl %eax, %edx
sarl %edx
orq %r15, %rdx
leaq 1(%r15), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 40(%rsp), %rax
movq %rax, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 48(%rsp)
leaq 16(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7minimumPi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movq 40(%rsp), %rsi
leaq 108(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 108(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq 40(%rsp), %rdi
callq hipFree
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
movl %eax, %edx
shrl $31, %edx
addl %eax, %edx
sarl %edx
orq %r15, %rdx
incq %r15
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 32(%rsp), %rax
movq %rax, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 48(%rsp)
leaq 16(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3sumPi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq 32(%rsp), %rsi
leaq 16(%rsp), %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 16(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7minimumPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7minimumPi,@object # @_Z7minimumPi
.section .rodata,"a",@progbits
.globl _Z7minimumPi
.p2align 3, 0x0
_Z7minimumPi:
.quad _Z22__device_stub__minimumPi
.size _Z7minimumPi, 8
.type _Z3sumPi,@object # @_Z3sumPi
.globl _Z3sumPi
.p2align 3, 0x0
_Z3sumPi:
.quad _Z18__device_stub__sumPi
.size _Z3sumPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter no of elements"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " "
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Minimum Element = "
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Sum = "
.size .L.str.4, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7minimumPi"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3sumPi"
.size .L__unnamed_2, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__minimumPi
.addrsig_sym _Z18__device_stub__sumPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7minimumPi
.addrsig_sym _Z3sumPi
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3sumPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0050*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0060*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.SHL.U32 R6, R8, 0x2, RZ ; /* 0x0000000208067824 */
/* 0x001fe400078e00ff */
/*0090*/ ISETP.GE.AND P0, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fe2000bf06270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*00b0*/ BSSY B0, 0x180 ; /* 0x000000c000007945 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fcc000bf25270 */
/*00d0*/ @P0 BRA 0x170 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R4, R6, UR5, RZ ; /* 0x0000000506047c24 */
/* 0x000fca000f8e02ff */
/*0100*/ IADD3 R2, R4, UR5, RZ ; /* 0x0000000504027c10 */
/* 0x000fc8000fffe0ff */
/*0110*/ IMAD.WIDE R4, R4, R3, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0203 */
/*0120*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*0130*/ LDG.E R0, [R4.64] ; /* 0x0000000604007981 */
/* 0x000eaa000c1e1900 */
/*0140*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea4000c1e1900 */
/*0150*/ IMAD.IADD R7, R0, 0x1, R3 ; /* 0x0000000100077824 */
/* 0x004fca00078e0203 */
/*0160*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e4000c101906 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ USHF.L.U32 UR5, UR5, 0x1, URZ ; /* 0x0000000105057899 */
/* 0x000fe2000800063f */
/*0190*/ @P1 BRA 0x90 ; /* 0xfffffef000001947 */
/* 0x000fea000383ffff */
/*01a0*/ NOP ; /* 0x0000000000007918 */
/* 0x000fc20000000000 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7minimumPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.SHL.U32 R0, R8, 0x2, RZ ; /* 0x0000000208007824 */
/* 0x001fe400078e00ff */
/*0090*/ ISETP.GE.AND P1, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fe2000bf26270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*00b0*/ BSSY B0, 0x170 ; /* 0x000000b000007945 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fcc000bf05270 */
/*00d0*/ @P1 BRA 0x160 ; /* 0x0000008000001947 */
/* 0x001fea0003800000 */
/*00e0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R4, R0, R7, RZ ; /* 0x0000000700047224 */
/* 0x000fd200078e02ff */
/*0100*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0110*/ LDG.E R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R2, R7, 0x4, R4 ; /* 0x0000000407027825 */
/* 0x000fcc00078e0204 */
/*0130*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea4000c1e1900 */
/*0140*/ ISETP.GT.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x004fda0003f24270 */
/*0150*/ @P1 STG.E [R4.64], R3 ; /* 0x0000000304001986 */
/* 0x0001e4000c101906 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ SHF.L.U32 R7, R7, 0x1, RZ ; /* 0x0000000107077819 */
/* 0x000fe200000006ff */
/*0180*/ @P0 BRA 0x90 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7minimumPi
.globl _Z7minimumPi
.p2align 8
.type _Z7minimumPi,@function
_Z7minimumPi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 1, v0
s_and_b32 s3, 0xffff, s2
s_mov_b32 s2, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_lshl_b32 s2, s2, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_cbranch_scc0 .LBB0_6
.LBB0_3:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v1, v3, s2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v5, v2 :: v_dual_add_nc_u32 v4, s2, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_b32 v6, v[1:2], off
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v6, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
global_store_b32 v[1:2], v4, off
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7minimumPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7minimumPi, .Lfunc_end0-_Z7minimumPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3sumPi
.globl _Z3sumPi
.p2align 8
.type _Z3sumPi,@function
_Z3sumPi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB1_5
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 1, v0
s_and_b32 s3, 0xffff, s2
s_mov_b32 s2, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_lshl_b32 s2, s2, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_cbranch_scc0 .LBB1_5
.LBB1_3:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB1_2
v_mul_lo_u32 v2, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, s2, v2
v_mov_b32_e32 v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
global_store_b32 v[2:3], v4, off
s_branch .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3sumPi, .Lfunc_end1-_Z3sumPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7minimumPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z7minimumPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z3sumPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00000062_00000000-6_parallelreduction.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z7minimumPiPi
.type _Z26__device_stub__Z7minimumPiPi, @function
_Z26__device_stub__Z7minimumPiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7minimumPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z7minimumPiPi, .-_Z26__device_stub__Z7minimumPiPi
.globl _Z7minimumPi
.type _Z7minimumPi, @function
_Z7minimumPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7minimumPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z7minimumPi, .-_Z7minimumPi
.globl _Z22__device_stub__Z3sumPiPi
.type _Z22__device_stub__Z3sumPiPi, @function
_Z22__device_stub__Z3sumPiPi:
.LFB3696:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3sumPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z22__device_stub__Z3sumPiPi, .-_Z22__device_stub__Z3sumPiPi
.globl _Z3sumPi
.type _Z3sumPi, @function
_Z3sumPi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3sumPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z3sumPi, .-_Z3sumPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter no of elements"
.LC1:
.string "\n"
.LC2:
.string " "
.LC3:
.string "Minimum Element = "
.LC4:
.string "Sum = "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 8(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 8(%rsp), %edi
call srand@PLT
movslq 8(%rsp), %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L20
salq $2, %rdi
call _Znam@PLT
movq %rax, %rbp
movl $0, %ebx
cmpl $0, 8(%rsp)
jle .L22
.L21:
call rand@PLT
movl %eax, 0(%rbp,%rbx,4)
movl 8(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jg .L21
testl %eax, %eax
jle .L22
movl $0, %ebx
leaq _ZSt4cout(%rip), %r13
leaq .LC2(%rip), %r12
.L24:
movl 0(%rbp,%rbx,4), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpl %ebx, 8(%rsp)
jg .L24
.L22:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl 8(%rsp), %eax
leal 0(,%rax,4), %ebx
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 8(%rsp), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L25:
leaq 12(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %esi
call _ZNSolsEi@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 8(%rsp), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L26:
leaq 44(%rsp), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 44(%rsp), %esi
call _ZNSolsEi@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L23
call __stack_chk_fail@PLT
.L23:
call __cxa_throw_bad_array_new_length@PLT
.L33:
movq 16(%rsp), %rdi
call _Z26__device_stub__Z7minimumPiPi
jmp .L25
.L34:
movq 24(%rsp), %rdi
call _Z22__device_stub__Z3sumPiPi
jmp .L26
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z3sumPi"
.LC6:
.string "_Z7minimumPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7minimumPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "parallelreduction.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__minimumPi # -- Begin function _Z22__device_stub__minimumPi
.p2align 4, 0x90
.type _Z22__device_stub__minimumPi,@function
_Z22__device_stub__minimumPi: # @_Z22__device_stub__minimumPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7minimumPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z22__device_stub__minimumPi, .Lfunc_end0-_Z22__device_stub__minimumPi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__sumPi # -- Begin function _Z18__device_stub__sumPi
.p2align 4, 0x90
.type _Z18__device_stub__sumPi,@function
_Z18__device_stub__sumPi: # @_Z18__device_stub__sumPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3sumPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z18__device_stub__sumPi, .Lfunc_end1-_Z18__device_stub__sumPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 12(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl 12(%rsp), %edi
callq srand
movslq 12(%rsp), %rbx
leaq (,%rbx,4), %rax
testq %rbx, %rbx
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
movq %rax, %r14
testq %rbx, %rbx
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%r14,%rbx,4)
incq %rbx
movslq 12(%rsp), %rax
cmpq %rax, %rbx
jl .LBB2_2
.LBB2_3: # %.preheader
cmpl $0, 12(%rsp)
jle .LBB2_6
# %bb.4: # %.lr.ph39.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_5: # %.lr.ph39
# =>This Inner Loop Header: Depth=1
movl (%r14,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
movslq 12(%rsp), %rax
cmpq %rax, %rbx
jl .LBB2_5
.LBB2_6: # %._crit_edge
movabsq $4294967296, %r15 # imm = 0x100000000
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 12(%rsp), %eax
shll $2, %eax
movslq %eax, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
movl %eax, %edx
shrl $31, %edx
addl %eax, %edx
sarl %edx
orq %r15, %rdx
leaq 1(%r15), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 40(%rsp), %rax
movq %rax, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 48(%rsp)
leaq 16(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7minimumPi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movq 40(%rsp), %rsi
leaq 108(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 108(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq 40(%rsp), %rdi
callq hipFree
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
movl %eax, %edx
shrl $31, %edx
addl %eax, %edx
sarl %edx
orq %r15, %rdx
incq %r15
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 32(%rsp), %rax
movq %rax, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 48(%rsp)
leaq 16(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3sumPi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq 32(%rsp), %rsi
leaq 16(%rsp), %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 16(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7minimumPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7minimumPi,@object # @_Z7minimumPi
.section .rodata,"a",@progbits
.globl _Z7minimumPi
.p2align 3, 0x0
_Z7minimumPi:
.quad _Z22__device_stub__minimumPi
.size _Z7minimumPi, 8
.type _Z3sumPi,@object # @_Z3sumPi
.globl _Z3sumPi
.p2align 3, 0x0
_Z3sumPi:
.quad _Z18__device_stub__sumPi
.size _Z3sumPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter no of elements"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " "
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Minimum Element = "
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Sum = "
.size .L.str.4, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7minimumPi"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3sumPi"
.size .L__unnamed_2, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__minimumPi
.addrsig_sym _Z18__device_stub__sumPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7minimumPi
.addrsig_sym _Z3sumPi
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* @file HelloWorld.cu
*
* @author btran
*
* @date 2020-05-02
*
* Copyright (c) organization
*
*/
#include <iostream>
__global__ void helloworld1()
{
// compute local thread ID
int tx = threadIdx.x;
int ty = threadIdx.y;
int tz = threadIdx.z;
// compute local block ID
int bx = blockIdx.x;
int by = blockIdx.y;
int bz = blockIdx.z;
printf("Hello from thread (%d, %d, %d) in block (%d, %d, %d) \n", tx, ty,
tz, bx, by, bz);
}
int main(int argc, char *argv[])
{
helloworld1<<<1, 10>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z11helloworld1v
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*0020*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a20000000a00 */
/*0090*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000ee40000002500 */
/*00a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fc400000e06ff */
/*00b0*/ S2R R10, SR_TID.Z ; /* 0x00000000000a7919 */
/* 0x000ee80000002300 */
/*00c0*/ S2R R13, SR_CTAID.Z ; /* 0x00000000000d7919 */
/* 0x000f280000002700 */
/*00d0*/ S2R R12, SR_CTAID.Y ; /* 0x00000000000c7919 */
/* 0x000f280000002600 */
/*00e0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100a00 */
/*00f0*/ STL.64 [R1+0x8], R10 ; /* 0x0000080a01007387 */
/* 0x0083e80000100a00 */
/*0100*/ STL.64 [R1+0x10], R12 ; /* 0x0000100c01007387 */
/* 0x0103e40000100a00 */
/*0110*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x006fe40000000000 */
/*0120*/ MOV R11, 0x190 ; /* 0x00000190000b7802 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R20, 0x110 ; /* 0x0000011000147802 */
/* 0x000fc40000000f00 */
/*0140*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0160*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0170*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0180*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* @file HelloWorld.cu
*
* @author btran
*
* @date 2020-05-02
*
* Copyright (c) organization
*
*/
#include <iostream>
__global__ void helloworld1()
{
// compute local thread ID
int tx = threadIdx.x;
int ty = threadIdx.y;
int tz = threadIdx.z;
// compute local block ID
int bx = blockIdx.x;
int by = blockIdx.y;
int bz = blockIdx.z;
printf("Hello from thread (%d, %d, %d) in block (%d, %d, %d) \n", tx, ty,
tz, bx, by, bz);
}
int main(int argc, char *argv[])
{
helloworld1<<<1, 10>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000b78ec_00000000-6_HelloWorld.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z11helloworld1vv
.type _Z30__device_stub__Z11helloworld1vv, @function
_Z30__device_stub__Z11helloworld1vv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11helloworld1v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z11helloworld1vv, .-_Z30__device_stub__Z11helloworld1vv
.globl _Z11helloworld1v
.type _Z11helloworld1v, @function
_Z11helloworld1v:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11helloworld1vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z11helloworld1v, .-_Z11helloworld1v
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z30__device_stub__Z11helloworld1vv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11helloworld1v"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11helloworld1v(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* @file HelloWorld.cu
*
* @author btran
*
* @date 2020-05-02
*
* Copyright (c) organization
*
*/
#include <iostream>
__global__ void helloworld1()
{
// compute local thread ID
int tx = threadIdx.x;
int ty = threadIdx.y;
int tz = threadIdx.z;
// compute local block ID
int bx = blockIdx.x;
int by = blockIdx.y;
int bz = blockIdx.z;
printf("Hello from thread (%d, %d, %d) in block (%d, %d, %d) \n", tx, ty,
tz, bx, by, bz);
}
int main(int argc, char *argv[])
{
helloworld1<<<1, 10>>>();
cudaDeviceSynchronize();
return 0;
} | /**
* @file HelloWorld.cu
*
* @author btran
*
* @date 2020-05-02
*
* Copyright (c) organization
*
*/
#include <hip/hip_runtime.h>
#include <iostream>
__global__ void helloworld1()
{
// compute local thread ID
int tx = threadIdx.x;
int ty = threadIdx.y;
int tz = threadIdx.z;
// compute local block ID
int bx = blockIdx.x;
int by = blockIdx.y;
int bz = blockIdx.z;
printf("Hello from thread (%d, %d, %d) in block (%d, %d, %d) \n", tx, ty,
tz, bx, by, bz);
}
int main(int argc, char *argv[])
{
helloworld1<<<1, 10>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* @file HelloWorld.cu
*
* @author btran
*
* @date 2020-05-02
*
* Copyright (c) organization
*
*/
#include <hip/hip_runtime.h>
#include <iostream>
__global__ void helloworld1()
{
// compute local thread ID
int tx = threadIdx.x;
int ty = threadIdx.y;
int tz = threadIdx.z;
// compute local block ID
int bx = blockIdx.x;
int by = blockIdx.y;
int bz = blockIdx.z;
printf("Hello from thread (%d, %d, %d) in block (%d, %d, %d) \n", tx, ty,
tz, bx, by, bz);
}
int main(int argc, char *argv[])
{
helloworld1<<<1, 10>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "HelloWorld.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__helloworld1v # -- Begin function _Z26__device_stub__helloworld1v
.p2align 4, 0x90
.type _Z26__device_stub__helloworld1v,@function
_Z26__device_stub__helloworld1v: # @_Z26__device_stub__helloworld1v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11helloworld1v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z26__device_stub__helloworld1v, .Lfunc_end0-_Z26__device_stub__helloworld1v
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11helloworld1v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11helloworld1v, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11helloworld1v,@object # @_Z11helloworld1v
.section .rodata,"a",@progbits
.globl _Z11helloworld1v
.p2align 3, 0x0
_Z11helloworld1v:
.quad _Z26__device_stub__helloworld1v
.size _Z11helloworld1v, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11helloworld1v"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__helloworld1v
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11helloworld1v
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b78ec_00000000-6_HelloWorld.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z11helloworld1vv
.type _Z30__device_stub__Z11helloworld1vv, @function
_Z30__device_stub__Z11helloworld1vv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11helloworld1v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z11helloworld1vv, .-_Z30__device_stub__Z11helloworld1vv
.globl _Z11helloworld1v
.type _Z11helloworld1v, @function
_Z11helloworld1v:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11helloworld1vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z11helloworld1v, .-_Z11helloworld1v
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z30__device_stub__Z11helloworld1vv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11helloworld1v"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11helloworld1v(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "HelloWorld.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__helloworld1v # -- Begin function _Z26__device_stub__helloworld1v
.p2align 4, 0x90
.type _Z26__device_stub__helloworld1v,@function
_Z26__device_stub__helloworld1v: # @_Z26__device_stub__helloworld1v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11helloworld1v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z26__device_stub__helloworld1v, .Lfunc_end0-_Z26__device_stub__helloworld1v
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11helloworld1v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11helloworld1v, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11helloworld1v,@object # @_Z11helloworld1v
.section .rodata,"a",@progbits
.globl _Z11helloworld1v
.p2align 3, 0x0
_Z11helloworld1v:
.quad _Z26__device_stub__helloworld1v
.size _Z11helloworld1v, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11helloworld1v"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__helloworld1v
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11helloworld1v
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
// Error check macro
#define cudaCheckErrors(msg) \
do {\
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, cudaGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
const int DSIZE = 4096; // Size of the vector
const int block_size = 256; // CUDA maximum is 1024
// Add vectors A + B = C
__global__ void vadd(const float *A, const float *B, float *C, int ds) {
int idx = blockDim.x*blockIdx.x + threadIdx.x;
if (idx < ds) { C[idx] = B[idx] + A[idx]; }
}
int main() {
// 1) Initialize vectors host side
float *h_A, *h_B, *h_C, *d_A, *d_B, *d_C;
h_A = new float[DSIZE]; // allocate space for vectors in host memory
h_B = new float[DSIZE];
h_C = new float[DSIZE];
for (int i = 0; i < DSIZE; i++) { // initialize vectors in host memory
h_A[i] = rand()/float(RAND_MAX);
h_B[i] = rand()/float(RAND_MAX);
h_C[i] = 0.;
}
// 2) Initialize vectors device side
cudaMalloc(&d_A, DSIZE*sizeof(float)); // Allocate device space for vector A
cudaMalloc(&d_B, DSIZE*sizeof(float)); // Allocate device space for vector B
cudaMalloc(&d_C, DSIZE*sizeof(float)); // Allocate device space for vector C
// Commonly asked question: why is first argument of cudaMalloc a ptr to ptr?
// Answer: &d_A is a ptr to ptr in device memory; one dereference (*&d_a)
// is the pointer which points to data in device memory; second dereference
// points to the data
cudaCheckErrors("cudaMalloc failure"); // Error checking
// 3) Copy host vectors to device
cudaMemcpy(d_A, h_A, DSIZE*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, DSIZE*sizeof(float), cudaMemcpyHostToDevice);
// Don't need to copy into C, we will do addition on d_C which is already
// initialized in device, then copy back to host
cudaCheckErrors("cudaMemcpy H2d failure");
// 4) Do addition
// Note: number of blocks is size of vector / block size, rounded up
// so if e.g. 401 elements, block size 100, get 5 blocks
vadd<<<(DSIZE+block_size-1)/block_size, block_size>>>(d_A, d_B, d_C, DSIZE);
cudaCheckErrors("kernel launch failure");
// 5) Copy result (vector C) from device to host
//cudaDeviceSynchronize();
cudaMemcpy(h_C, d_C, DSIZE*sizeof(float), cudaMemcpyDeviceToHost);
cudaCheckErrors("kernel execution failures or cudaMemcpy D2H failure");
// Sample
printf("A[0] = %f\n", h_A[0]);
printf("B[0] = %f\n", h_B[0]);
printf("C[0] = %f\n", h_C[0]);
return 0;
} | code for sm_80
Function : _Z4vaddPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
// Error check macro
#define cudaCheckErrors(msg) \
do {\
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, cudaGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
const int DSIZE = 4096; // Size of the vector
const int block_size = 256; // CUDA maximum is 1024
// Add vectors A + B = C
__global__ void vadd(const float *A, const float *B, float *C, int ds) {
int idx = blockDim.x*blockIdx.x + threadIdx.x;
if (idx < ds) { C[idx] = B[idx] + A[idx]; }
}
int main() {
// 1) Initialize vectors host side
float *h_A, *h_B, *h_C, *d_A, *d_B, *d_C;
h_A = new float[DSIZE]; // allocate space for vectors in host memory
h_B = new float[DSIZE];
h_C = new float[DSIZE];
for (int i = 0; i < DSIZE; i++) { // initialize vectors in host memory
h_A[i] = rand()/float(RAND_MAX);
h_B[i] = rand()/float(RAND_MAX);
h_C[i] = 0.;
}
// 2) Initialize vectors device side
cudaMalloc(&d_A, DSIZE*sizeof(float)); // Allocate device space for vector A
cudaMalloc(&d_B, DSIZE*sizeof(float)); // Allocate device space for vector B
cudaMalloc(&d_C, DSIZE*sizeof(float)); // Allocate device space for vector C
// Commonly asked question: why is first argument of cudaMalloc a ptr to ptr?
// Answer: &d_A is a ptr to ptr in device memory; one dereference (*&d_a)
// is the pointer which points to data in device memory; second dereference
// points to the data
cudaCheckErrors("cudaMalloc failure"); // Error checking
// 3) Copy host vectors to device
cudaMemcpy(d_A, h_A, DSIZE*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, DSIZE*sizeof(float), cudaMemcpyHostToDevice);
// Don't need to copy into C, we will do addition on d_C which is already
// initialized in device, then copy back to host
cudaCheckErrors("cudaMemcpy H2d failure");
// 4) Do addition
// Note: number of blocks is size of vector / block size, rounded up
// so if e.g. 401 elements, block size 100, get 5 blocks
vadd<<<(DSIZE+block_size-1)/block_size, block_size>>>(d_A, d_B, d_C, DSIZE);
cudaCheckErrors("kernel launch failure");
// 5) Copy result (vector C) from device to host
//cudaDeviceSynchronize();
cudaMemcpy(h_C, d_C, DSIZE*sizeof(float), cudaMemcpyDeviceToHost);
cudaCheckErrors("kernel execution failures or cudaMemcpy D2H failure");
// Sample
printf("A[0] = %f\n", h_A[0]);
printf("B[0] = %f\n", h_B[0]);
printf("C[0] = %f\n", h_C[0]);
return 0;
} | .file "tmpxft_0004fc74_00000000-6_vector_add_hw.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi
.type _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi, @function
_Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4vaddPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi, .-_Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi
.globl _Z4vaddPKfS0_Pfi
.type _Z4vaddPKfS0_Pfi, @function
_Z4vaddPKfS0_Pfi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4vaddPKfS0_Pfi, .-_Z4vaddPKfS0_Pfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/mrowan137/cuda-training-series/master/exercises/hw1/vector_add_hw.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "cudaMalloc failure"
.section .rodata.str1.8
.align 8
.LC4:
.string "Fatal error: %s (%s at %s:%d)\n"
.section .rodata.str1.1
.LC5:
.string "*** FAILED - ABORTING\n"
.LC6:
.string "cudaMemcpy H2d failure"
.LC7:
.string "kernel launch failure"
.section .rodata.str1.8
.align 8
.LC8:
.string "kernel execution failures or cudaMemcpy D2H failure"
.section .rodata.str1.1
.LC9:
.string "A[0] = %f\n"
.LC10:
.string "B[0] = %f\n"
.LC11:
.string "C[0] = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $16384, %edi
call _Znam@PLT
movq %rax, %r13
movl $16384, %edi
call _Znam@PLT
movq %rax, %r12
movl $16384, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, %ebx
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%r13,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%r12,%rbx)
movl $0x00000000, 0(%rbp,%rbx)
addq $4, %rbx
cmpq $16384, %rbx
jne .L12
leaq 8(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L21
movl $1, %ecx
movl $16384, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16384, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L22
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $16, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L24
movl $2, %ecx
movl $16384, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L25
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $46
.cfi_def_cfa_offset 128
leaq .LC2(%rip), %r9
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $53
.cfi_def_cfa_offset 128
leaq .LC2(%rip), %r9
leaq .LC6(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L23:
movl $4096, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi
jmp .L15
.L24:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $59
.cfi_def_cfa_offset 128
leaq .LC2(%rip), %r9
leaq .LC7(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $64
.cfi_def_cfa_offset 128
leaq .LC2(%rip), %r9
leaq .LC8(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z4vaddPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z4vaddPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
// Error check macro
#define cudaCheckErrors(msg) \
do {\
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, cudaGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
const int DSIZE = 4096; // Size of the vector
const int block_size = 256; // CUDA maximum is 1024
// Add vectors A + B = C
__global__ void vadd(const float *A, const float *B, float *C, int ds) {
int idx = blockDim.x*blockIdx.x + threadIdx.x;
if (idx < ds) { C[idx] = B[idx] + A[idx]; }
}
int main() {
// 1) Initialize vectors host side
float *h_A, *h_B, *h_C, *d_A, *d_B, *d_C;
h_A = new float[DSIZE]; // allocate space for vectors in host memory
h_B = new float[DSIZE];
h_C = new float[DSIZE];
for (int i = 0; i < DSIZE; i++) { // initialize vectors in host memory
h_A[i] = rand()/float(RAND_MAX);
h_B[i] = rand()/float(RAND_MAX);
h_C[i] = 0.;
}
// 2) Initialize vectors device side
cudaMalloc(&d_A, DSIZE*sizeof(float)); // Allocate device space for vector A
cudaMalloc(&d_B, DSIZE*sizeof(float)); // Allocate device space for vector B
cudaMalloc(&d_C, DSIZE*sizeof(float)); // Allocate device space for vector C
// Commonly asked question: why is first argument of cudaMalloc a ptr to ptr?
// Answer: &d_A is a ptr to ptr in device memory; one dereference (*&d_a)
// is the pointer which points to data in device memory; second dereference
// points to the data
cudaCheckErrors("cudaMalloc failure"); // Error checking
// 3) Copy host vectors to device
cudaMemcpy(d_A, h_A, DSIZE*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, DSIZE*sizeof(float), cudaMemcpyHostToDevice);
// Don't need to copy into C, we will do addition on d_C which is already
// initialized in device, then copy back to host
cudaCheckErrors("cudaMemcpy H2d failure");
// 4) Do addition
// Note: number of blocks is size of vector / block size, rounded up
// so if e.g. 401 elements, block size 100, get 5 blocks
vadd<<<(DSIZE+block_size-1)/block_size, block_size>>>(d_A, d_B, d_C, DSIZE);
cudaCheckErrors("kernel launch failure");
// 5) Copy result (vector C) from device to host
//cudaDeviceSynchronize();
cudaMemcpy(h_C, d_C, DSIZE*sizeof(float), cudaMemcpyDeviceToHost);
cudaCheckErrors("kernel execution failures or cudaMemcpy D2H failure");
// Sample
printf("A[0] = %f\n", h_A[0]);
printf("B[0] = %f\n", h_B[0]);
printf("C[0] = %f\n", h_C[0]);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
// Error check macro
#define cudaCheckErrors(msg) \
do {\
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
const int DSIZE = 4096; // Size of the vector
const int block_size = 256; // CUDA maximum is 1024
// Add vectors A + B = C
__global__ void vadd(const float *A, const float *B, float *C, int ds) {
int idx = blockDim.x*blockIdx.x + threadIdx.x;
if (idx < ds) { C[idx] = B[idx] + A[idx]; }
}
int main() {
// 1) Initialize vectors host side
float *h_A, *h_B, *h_C, *d_A, *d_B, *d_C;
h_A = new float[DSIZE]; // allocate space for vectors in host memory
h_B = new float[DSIZE];
h_C = new float[DSIZE];
for (int i = 0; i < DSIZE; i++) { // initialize vectors in host memory
h_A[i] = rand()/float(RAND_MAX);
h_B[i] = rand()/float(RAND_MAX);
h_C[i] = 0.;
}
// 2) Initialize vectors device side
hipMalloc(&d_A, DSIZE*sizeof(float)); // Allocate device space for vector A
hipMalloc(&d_B, DSIZE*sizeof(float)); // Allocate device space for vector B
hipMalloc(&d_C, DSIZE*sizeof(float)); // Allocate device space for vector C
// Commonly asked question: why is first argument of cudaMalloc a ptr to ptr?
// Answer: &d_A is a ptr to ptr in device memory; one dereference (*&d_a)
// is the pointer which points to data in device memory; second dereference
// points to the data
cudaCheckErrors("hipMalloc failure"); // Error checking
// 3) Copy host vectors to device
hipMemcpy(d_A, h_A, DSIZE*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, DSIZE*sizeof(float), hipMemcpyHostToDevice);
// Don't need to copy into C, we will do addition on d_C which is already
// initialized in device, then copy back to host
cudaCheckErrors("hipMemcpy H2d failure");
// 4) Do addition
// Note: number of blocks is size of vector / block size, rounded up
// so if e.g. 401 elements, block size 100, get 5 blocks
vadd<<<(DSIZE+block_size-1)/block_size, block_size>>>(d_A, d_B, d_C, DSIZE);
cudaCheckErrors("kernel launch failure");
// 5) Copy result (vector C) from device to host
//cudaDeviceSynchronize();
hipMemcpy(h_C, d_C, DSIZE*sizeof(float), hipMemcpyDeviceToHost);
cudaCheckErrors("kernel execution failures or hipMemcpy D2H failure");
// Sample
printf("A[0] = %f\n", h_A[0]);
printf("B[0] = %f\n", h_B[0]);
printf("C[0] = %f\n", h_C[0]);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// Error check macro
#define cudaCheckErrors(msg) \
do {\
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
const int DSIZE = 4096; // Size of the vector
const int block_size = 256; // CUDA maximum is 1024
// Add vectors A + B = C
__global__ void vadd(const float *A, const float *B, float *C, int ds) {
int idx = blockDim.x*blockIdx.x + threadIdx.x;
if (idx < ds) { C[idx] = B[idx] + A[idx]; }
}
int main() {
// 1) Initialize vectors host side
float *h_A, *h_B, *h_C, *d_A, *d_B, *d_C;
h_A = new float[DSIZE]; // allocate space for vectors in host memory
h_B = new float[DSIZE];
h_C = new float[DSIZE];
for (int i = 0; i < DSIZE; i++) { // initialize vectors in host memory
h_A[i] = rand()/float(RAND_MAX);
h_B[i] = rand()/float(RAND_MAX);
h_C[i] = 0.;
}
// 2) Initialize vectors device side
hipMalloc(&d_A, DSIZE*sizeof(float)); // Allocate device space for vector A
hipMalloc(&d_B, DSIZE*sizeof(float)); // Allocate device space for vector B
hipMalloc(&d_C, DSIZE*sizeof(float)); // Allocate device space for vector C
// Commonly asked question: why is first argument of cudaMalloc a ptr to ptr?
// Answer: &d_A is a ptr to ptr in device memory; one dereference (*&d_a)
// is the pointer which points to data in device memory; second dereference
// points to the data
cudaCheckErrors("hipMalloc failure"); // Error checking
// 3) Copy host vectors to device
hipMemcpy(d_A, h_A, DSIZE*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, DSIZE*sizeof(float), hipMemcpyHostToDevice);
// Don't need to copy into C, we will do addition on d_C which is already
// initialized in device, then copy back to host
cudaCheckErrors("hipMemcpy H2d failure");
// 4) Do addition
// Note: number of blocks is size of vector / block size, rounded up
// so if e.g. 401 elements, block size 100, get 5 blocks
vadd<<<(DSIZE+block_size-1)/block_size, block_size>>>(d_A, d_B, d_C, DSIZE);
cudaCheckErrors("kernel launch failure");
// 5) Copy result (vector C) from device to host
//cudaDeviceSynchronize();
hipMemcpy(h_C, d_C, DSIZE*sizeof(float), hipMemcpyDeviceToHost);
cudaCheckErrors("kernel execution failures or hipMemcpy D2H failure");
// Sample
printf("A[0] = %f\n", h_A[0]);
printf("B[0] = %f\n", h_B[0]);
printf("C[0] = %f\n", h_C[0]);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4vaddPKfS0_Pfi
.globl _Z4vaddPKfS0_Pfi
.p2align 8
.type _Z4vaddPKfS0_Pfi,@function
_Z4vaddPKfS0_Pfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4vaddPKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4vaddPKfS0_Pfi, .Lfunc_end0-_Z4vaddPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4vaddPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4vaddPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// Error check macro
#define cudaCheckErrors(msg) \
do {\
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
const int DSIZE = 4096; // Size of the vector
const int block_size = 256; // CUDA maximum is 1024
// Add vectors A + B = C
__global__ void vadd(const float *A, const float *B, float *C, int ds) {
int idx = blockDim.x*blockIdx.x + threadIdx.x;
if (idx < ds) { C[idx] = B[idx] + A[idx]; }
}
int main() {
// 1) Initialize vectors host side
float *h_A, *h_B, *h_C, *d_A, *d_B, *d_C;
h_A = new float[DSIZE]; // allocate space for vectors in host memory
h_B = new float[DSIZE];
h_C = new float[DSIZE];
for (int i = 0; i < DSIZE; i++) { // initialize vectors in host memory
h_A[i] = rand()/float(RAND_MAX);
h_B[i] = rand()/float(RAND_MAX);
h_C[i] = 0.;
}
// 2) Initialize vectors device side
hipMalloc(&d_A, DSIZE*sizeof(float)); // Allocate device space for vector A
hipMalloc(&d_B, DSIZE*sizeof(float)); // Allocate device space for vector B
hipMalloc(&d_C, DSIZE*sizeof(float)); // Allocate device space for vector C
// Commonly asked question: why is first argument of cudaMalloc a ptr to ptr?
// Answer: &d_A is a ptr to ptr in device memory; one dereference (*&d_a)
// is the pointer which points to data in device memory; second dereference
// points to the data
cudaCheckErrors("hipMalloc failure"); // Error checking
// 3) Copy host vectors to device
hipMemcpy(d_A, h_A, DSIZE*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, DSIZE*sizeof(float), hipMemcpyHostToDevice);
// Don't need to copy into C, we will do addition on d_C which is already
// initialized in device, then copy back to host
cudaCheckErrors("hipMemcpy H2d failure");
// 4) Do addition
// Note: number of blocks is size of vector / block size, rounded up
// so if e.g. 401 elements, block size 100, get 5 blocks
vadd<<<(DSIZE+block_size-1)/block_size, block_size>>>(d_A, d_B, d_C, DSIZE);
cudaCheckErrors("kernel launch failure");
// 5) Copy result (vector C) from device to host
//cudaDeviceSynchronize();
hipMemcpy(h_C, d_C, DSIZE*sizeof(float), hipMemcpyDeviceToHost);
cudaCheckErrors("kernel execution failures or hipMemcpy D2H failure");
// Sample
printf("A[0] = %f\n", h_A[0]);
printf("B[0] = %f\n", h_B[0]);
printf("C[0] = %f\n", h_C[0]);
return 0;
} | .text
.file "vector_add_hw.hip"
.globl _Z19__device_stub__vaddPKfS0_Pfi # -- Begin function _Z19__device_stub__vaddPKfS0_Pfi
.p2align 4, 0x90
.type _Z19__device_stub__vaddPKfS0_Pfi,@function
_Z19__device_stub__vaddPKfS0_Pfi: # @_Z19__device_stub__vaddPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4vaddPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__vaddPKfS0_Pfi, .Lfunc_end0-_Z19__device_stub__vaddPKfS0_Pfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16384, %edi # imm = 0x4000
callq _Znam
movq %rax, %r15
movl $16384, %edi # imm = 0x4000
callq _Znam
movq %rax, %r14
movl $16384, %edi # imm = 0x4000
callq _Znam
movq %rax, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%r15,%r12,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r14,%r12,4)
movl $0, (%rbx,%r12,4)
incq %r12
cmpq $4096, %r12 # imm = 0x1000
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB1_3
# %bb.5:
movq 32(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 240(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $4096, 12(%rsp) # imm = 0x1000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z4vaddPKfS0_Pfi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_10
# %bb.11:
movq 16(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_12
# %bb.13:
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $48, %r9d
jmp .LBB1_4
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.4, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $55, %r9d
jmp .LBB1_4
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.5, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $61, %r9d
jmp .LBB1_4
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.6, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $66, %r9d
.LBB1_4:
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4vaddPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4vaddPKfS0_Pfi,@object # @_Z4vaddPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z4vaddPKfS0_Pfi
.p2align 3, 0x0
_Z4vaddPKfS0_Pfi:
.quad _Z19__device_stub__vaddPKfS0_Pfi
.size _Z4vaddPKfS0_Pfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Fatal error: %s (%s at %s:%d)\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc failure"
.size .L.str.1, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/mrowan137/cuda-training-series/master/exercises/hw1/vector_add_hw.hip"
.size .L.str.2, 127
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "*** FAILED - ABORTING\n"
.size .L.str.3, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMemcpy H2d failure"
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "kernel launch failure"
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "kernel execution failures or hipMemcpy D2H failure"
.size .L.str.6, 51
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "A[0] = %f\n"
.size .L.str.7, 11
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "B[0] = %f\n"
.size .L.str.8, 11
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "C[0] = %f\n"
.size .L.str.9, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4vaddPKfS0_Pfi"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__vaddPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4vaddPKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4vaddPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4vaddPKfS0_Pfi
.globl _Z4vaddPKfS0_Pfi
.p2align 8
.type _Z4vaddPKfS0_Pfi,@function
_Z4vaddPKfS0_Pfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4vaddPKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4vaddPKfS0_Pfi, .Lfunc_end0-_Z4vaddPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4vaddPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4vaddPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004fc74_00000000-6_vector_add_hw.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi
.type _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi, @function
_Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4vaddPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi, .-_Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi
.globl _Z4vaddPKfS0_Pfi
.type _Z4vaddPKfS0_Pfi, @function
_Z4vaddPKfS0_Pfi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4vaddPKfS0_Pfi, .-_Z4vaddPKfS0_Pfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/mrowan137/cuda-training-series/master/exercises/hw1/vector_add_hw.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "cudaMalloc failure"
.section .rodata.str1.8
.align 8
.LC4:
.string "Fatal error: %s (%s at %s:%d)\n"
.section .rodata.str1.1
.LC5:
.string "*** FAILED - ABORTING\n"
.LC6:
.string "cudaMemcpy H2d failure"
.LC7:
.string "kernel launch failure"
.section .rodata.str1.8
.align 8
.LC8:
.string "kernel execution failures or cudaMemcpy D2H failure"
.section .rodata.str1.1
.LC9:
.string "A[0] = %f\n"
.LC10:
.string "B[0] = %f\n"
.LC11:
.string "C[0] = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $16384, %edi
call _Znam@PLT
movq %rax, %r13
movl $16384, %edi
call _Znam@PLT
movq %rax, %r12
movl $16384, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, %ebx
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%r13,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%r12,%rbx)
movl $0x00000000, 0(%rbp,%rbx)
addq $4, %rbx
cmpq $16384, %rbx
jne .L12
leaq 8(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L21
movl $1, %ecx
movl $16384, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16384, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L22
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $16, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L24
movl $2, %ecx
movl $16384, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L25
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $46
.cfi_def_cfa_offset 128
leaq .LC2(%rip), %r9
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $53
.cfi_def_cfa_offset 128
leaq .LC2(%rip), %r9
leaq .LC6(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L23:
movl $4096, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi
jmp .L15
.L24:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $59
.cfi_def_cfa_offset 128
leaq .LC2(%rip), %r9
leaq .LC7(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $64
.cfi_def_cfa_offset 128
leaq .LC2(%rip), %r9
leaq .LC8(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z4vaddPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z4vaddPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_add_hw.hip"
.globl _Z19__device_stub__vaddPKfS0_Pfi # -- Begin function _Z19__device_stub__vaddPKfS0_Pfi
.p2align 4, 0x90
.type _Z19__device_stub__vaddPKfS0_Pfi,@function
_Z19__device_stub__vaddPKfS0_Pfi: # @_Z19__device_stub__vaddPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4vaddPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__vaddPKfS0_Pfi, .Lfunc_end0-_Z19__device_stub__vaddPKfS0_Pfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16384, %edi # imm = 0x4000
callq _Znam
movq %rax, %r15
movl $16384, %edi # imm = 0x4000
callq _Znam
movq %rax, %r14
movl $16384, %edi # imm = 0x4000
callq _Znam
movq %rax, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%r15,%r12,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r14,%r12,4)
movl $0, (%rbx,%r12,4)
incq %r12
cmpq $4096, %r12 # imm = 0x1000
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB1_3
# %bb.5:
movq 32(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 240(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $4096, 12(%rsp) # imm = 0x1000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z4vaddPKfS0_Pfi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_10
# %bb.11:
movq 16(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_12
# %bb.13:
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $48, %r9d
jmp .LBB1_4
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.4, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $55, %r9d
jmp .LBB1_4
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.5, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $61, %r9d
jmp .LBB1_4
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.6, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $66, %r9d
.LBB1_4:
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4vaddPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4vaddPKfS0_Pfi,@object # @_Z4vaddPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z4vaddPKfS0_Pfi
.p2align 3, 0x0
_Z4vaddPKfS0_Pfi:
.quad _Z19__device_stub__vaddPKfS0_Pfi
.size _Z4vaddPKfS0_Pfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Fatal error: %s (%s at %s:%d)\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc failure"
.size .L.str.1, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/mrowan137/cuda-training-series/master/exercises/hw1/vector_add_hw.hip"
.size .L.str.2, 127
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "*** FAILED - ABORTING\n"
.size .L.str.3, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMemcpy H2d failure"
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "kernel launch failure"
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "kernel execution failures or hipMemcpy D2H failure"
.size .L.str.6, 51
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "A[0] = %f\n"
.size .L.str.7, 11
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "B[0] = %f\n"
.size .L.str.8, 11
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "C[0] = %f\n"
.size .L.str.9, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4vaddPKfS0_Pfi"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__vaddPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4vaddPKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cuda_runtime.h>
#include "kosaraju.cuh"
/* Fill out the adjacency list and the reverse adjacency list as according to
* the routes given. Each route represents a directed edge.
*/
__global__
void cudaAirportAdjacencyKernel(int *dev_routes,
int *dev_adj,
int *dev_radj,
int n_ports,
int n_routes) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
while (i < n_routes) {
int first = dev_routes[2 * i];
int second = dev_routes[2 * i + 1];
dev_adj[first * n_ports + second] = 1;
dev_radj[second * n_ports + first] = 1;
i += blockDim.x * gridDim.x;
}
}
/* Wrapper function to call cudaAirportAdjacencyKernel. */
void cudaCallAirportAdjacencyKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *dev_routes,
int *dev_adj,
int *dev_radj,
int n_ports,
int n_routes) {
cudaAirportAdjacencyKernel<<<blocks, threadsPerBlock>>>
(dev_routes, dev_adj, dev_radj, n_ports, n_routes);
}
/* Remove any vertices with in-degree and out-degree 0, just for optimization. */
__global__
void cudaTrimGraph(int *m,
int *row_sum,
bool *mark,
int n_ports) {
// For i = 0 to n_ports - 1 inclusive, achieve the following:
// row_sum[i] = sum from j = 0 to n_ports - 1 of m[i * n_ports + j] * !mark[j]
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
while (i < n_ports) {
int total = 0;
for (int j = 0; j < n_ports; j++) {
total += m[i * n_ports + j] * !(mark[j]);
}
row_sum[i] = total;
i += blockDim.x * gridDim.x;
}
}
void cudaCallTrimGraph(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *adj,
int *row_sum,
bool *mark,
int n_ports) {
cudaTrimGraph<<<blocks, threadsPerBlock>>>(adj, row_sum, mark, n_ports);
}
__global__
void cudaBFSKernel(int *adj,
bool *frontier,
bool *visited,
int n_ports) {
// Do the BFS search
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
while (tid < n_ports) {
if (frontier[tid]) {
frontier[tid] = false;
visited[tid] = true;
for (int i = 0; i < n_ports; i++) {
if (adj[tid * n_ports + i] && !visited[i]) {
frontier[i] = true;
}
}
}
tid += blockDim.x * gridDim.x;
}
}
/* Returns whether the frontier array contains any true values. */
__global__
void cudaContainsTrueKernel(bool *frontier,
int *dev_flag,
int n_ports) {
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
while (tid < n_ports) {
if (frontier[tid]) {
dev_flag[0] *= 0;
}
tid += blockDim.x * gridDim.x;
}
}
/* Wrapper function to perform BFS. */
void cudaCallBFSKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *adj,
bool *visited,
bool *dev_frontier,
int start_port,
int n_ports,
int *dev_flag) {
int *flag = (int *) malloc(sizeof(int));
while (true) {
for (int i = 0; i < n_ports; i++) {
cudaBFSKernel<<<blocks, threadsPerBlock>>>
(adj, dev_frontier, visited, n_ports);
}
cudaContainsTrueKernel<<<blocks, threadsPerBlock>>>
(dev_frontier, dev_flag, n_ports);
cudaMemcpy(flag, dev_flag, sizeof(int), cudaMemcpyDeviceToHost);
if (flag[0]) {
break;
}
}
free(flag);
}
/* Fill out an array, one value for each airport. If an index i is some
* representative node of an SCC (that is not the starting airport) and we have
* that dev_zeroes[i] = 0 at the end of this kernel, then that means that
* index represents an airport who is a representative node of an SCC that has
* no incoming edges.
*/
__global__
void cudaFindDegreeZeroSCCKernel(int *adj,
int *radj,
int *reps,
int *dev_zeroes,
int start_port,
int n_ports) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
dev_zeroes[start_port] = 1;
while (i < n_ports) {
unsigned int curr_rep = reps[i];
for(int j = 0; j < n_ports; j++) {
if (radj[i * n_ports + j] == 1 && reps[j] != curr_rep) {
dev_zeroes[curr_rep] = 1;
break;
}
}
i += blockDim.x * gridDim.x;
}
}
/* Find number of representative nodes that have in-degree 0 (excluding
* starting airport). This is then the final answer to our algorithm.
*/
__global__
void cudaFindAllZeroesKernel(int *dev_reps,
int *dev_zeroes,
int *dev_total,
int n_ports){
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
while (i < n_ports) {
if(dev_reps[i] == i && dev_zeroes[i] == 0) {
atomicAdd(dev_total, 1);
}
i += blockDim.x * gridDim.x;
}
}
/* Wrapper function to call cudaFindDegreeZeroSCCKernel and
* cudaFindAllZeroesKernel.
*/
void cudaCallFindDegreeZeroSCCKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *dev_adj,
int *dev_radj,
int *dev_reps,
int *dev_zeroes,
int *dev_total,
int start_port,
int n_ports) {
cudaFindDegreeZeroSCCKernel<<<blocks, threadsPerBlock>>>
(dev_adj, dev_radj, dev_reps, dev_zeroes, start_port, n_ports);
cudaFindAllZeroesKernel<<<blocks, threadsPerBlock>>>
(dev_reps, dev_zeroes, dev_total, n_ports);
} | .file "tmpxft_0000065f_00000000-6_kosaraju.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5273:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5273:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z26cudaAirportAdjacencyKernelPiS_S_iiPiS_S_ii
.type _Z52__device_stub__Z26cudaAirportAdjacencyKernelPiS_S_iiPiS_S_ii, @function
_Z52__device_stub__Z26cudaAirportAdjacencyKernelPiS_S_iiPiS_S_ii:
.LFB5295:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26cudaAirportAdjacencyKernelPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5295:
.size _Z52__device_stub__Z26cudaAirportAdjacencyKernelPiS_S_iiPiS_S_ii, .-_Z52__device_stub__Z26cudaAirportAdjacencyKernelPiS_S_iiPiS_S_ii
.globl _Z26cudaAirportAdjacencyKernelPiS_S_ii
.type _Z26cudaAirportAdjacencyKernelPiS_S_ii, @function
_Z26cudaAirportAdjacencyKernelPiS_S_ii:
.LFB5296:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z26cudaAirportAdjacencyKernelPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5296:
.size _Z26cudaAirportAdjacencyKernelPiS_S_ii, .-_Z26cudaAirportAdjacencyKernelPiS_S_ii
.globl _Z30cudaCallAirportAdjacencyKerneljjPiS_S_ii
.type _Z30cudaCallAirportAdjacencyKerneljjPiS_S_ii, @function
_Z30cudaCallAirportAdjacencyKerneljjPiS_S_ii:
.LFB5267:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdx, %rbx
movq %rcx, %rbp
movq %r8, %r12
movl %r9d, %r13d
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl 80(%rsp), %r8d
movl %r13d, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z52__device_stub__Z26cudaAirportAdjacencyKernelPiS_S_iiPiS_S_ii
jmp .L11
.cfi_endproc
.LFE5267:
.size _Z30cudaCallAirportAdjacencyKerneljjPiS_S_ii, .-_Z30cudaCallAirportAdjacencyKerneljjPiS_S_ii
.globl _Z38__device_stub__Z13cudaTrimGraphPiS_PbiPiS_Pbi
.type _Z38__device_stub__Z13cudaTrimGraphPiS_PbiPiS_Pbi, @function
_Z38__device_stub__Z13cudaTrimGraphPiS_PbiPiS_Pbi:
.LFB5297:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13cudaTrimGraphPiS_Pbi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5297:
.size _Z38__device_stub__Z13cudaTrimGraphPiS_PbiPiS_Pbi, .-_Z38__device_stub__Z13cudaTrimGraphPiS_PbiPiS_Pbi
.globl _Z13cudaTrimGraphPiS_Pbi
.type _Z13cudaTrimGraphPiS_Pbi, @function
_Z13cudaTrimGraphPiS_Pbi:
.LFB5298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13cudaTrimGraphPiS_PbiPiS_Pbi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5298:
.size _Z13cudaTrimGraphPiS_Pbi, .-_Z13cudaTrimGraphPiS_Pbi
.globl _Z17cudaCallTrimGraphjjPiS_Pbi
.type _Z17cudaCallTrimGraphjjPiS_Pbi, @function
_Z17cudaCallTrimGraphjjPiS_Pbi:
.LFB5268:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdx, %rbx
movq %rcx, %rbp
movq %r8, %r12
movl %r9d, %r13d
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %r13d, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z38__device_stub__Z13cudaTrimGraphPiS_PbiPiS_Pbi
jmp .L23
.cfi_endproc
.LFE5268:
.size _Z17cudaCallTrimGraphjjPiS_Pbi, .-_Z17cudaCallTrimGraphjjPiS_Pbi
.globl _Z39__device_stub__Z13cudaBFSKernelPiPbS0_iPiPbS0_i
.type _Z39__device_stub__Z13cudaBFSKernelPiPbS0_iPiPbS0_i, @function
_Z39__device_stub__Z13cudaBFSKernelPiPbS0_iPiPbS0_i:
.LFB5299:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13cudaBFSKernelPiPbS0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5299:
.size _Z39__device_stub__Z13cudaBFSKernelPiPbS0_iPiPbS0_i, .-_Z39__device_stub__Z13cudaBFSKernelPiPbS0_iPiPbS0_i
.globl _Z13cudaBFSKernelPiPbS0_i
.type _Z13cudaBFSKernelPiPbS0_i, @function
_Z13cudaBFSKernelPiPbS0_i:
.LFB5300:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13cudaBFSKernelPiPbS0_iPiPbS0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5300:
.size _Z13cudaBFSKernelPiPbS0_i, .-_Z13cudaBFSKernelPiPbS0_i
.globl _Z45__device_stub__Z22cudaContainsTrueKernelPbPiiPbPii
.type _Z45__device_stub__Z22cudaContainsTrueKernelPbPiiPbPii, @function
_Z45__device_stub__Z22cudaContainsTrueKernelPbPiiPbPii:
.LFB5301:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22cudaContainsTrueKernelPbPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5301:
.size _Z45__device_stub__Z22cudaContainsTrueKernelPbPiiPbPii, .-_Z45__device_stub__Z22cudaContainsTrueKernelPbPiiPbPii
.globl _Z22cudaContainsTrueKernelPbPii
.type _Z22cudaContainsTrueKernelPbPii, @function
_Z22cudaContainsTrueKernelPbPii:
.LFB5302:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z22cudaContainsTrueKernelPbPiiPbPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5302:
.size _Z22cudaContainsTrueKernelPbPii, .-_Z22cudaContainsTrueKernelPbPii
.globl _Z17cudaCallBFSKerneljjPiPbS0_iiS_
.type _Z17cudaCallBFSKerneljjPiPbS0_iiS_, @function
_Z17cudaCallBFSKerneljjPiPbS0_iiS_:
.LFB5269:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %r13d
movl %esi, %r12d
movq %rdx, (%rsp)
movq %rcx, 8(%rsp)
movq %r8, %r14
movl 112(%rsp), %ebp
movl $4, %edi
call malloc@PLT
movq %rax, %r15
jmp .L48
.L45:
addl $1, %ebx
cmpl %ebx, %ebp
je .L44
.L46:
movl %r12d, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %r13d, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L45
movl %ebp, %ecx
movq 8(%rsp), %rdx
movq %r14, %rsi
movq (%rsp), %rdi
call _Z39__device_stub__Z13cudaBFSKernelPiPbS0_iPiPbS0_i
jmp .L45
.L44:
movl %r12d, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %r13d, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L47:
movl $2, %ecx
movl $4, %edx
movq 120(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
cmpl $0, (%r15)
jne .L53
.L48:
testl %ebp, %ebp
jle .L44
movl $0, %ebx
jmp .L46
.L52:
movl %ebp, %edx
movq 120(%rsp), %rsi
movq %r14, %rdi
call _Z45__device_stub__Z22cudaContainsTrueKernelPbPiiPbPii
jmp .L47
.L53:
movq %r15, %rdi
call free@PLT
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5269:
.size _Z17cudaCallBFSKerneljjPiPbS0_iiS_, .-_Z17cudaCallBFSKerneljjPiPbS0_iiS_
.globl _Z55__device_stub__Z27cudaFindDegreeZeroSCCKernelPiS_S_S_iiPiS_S_S_ii
.type _Z55__device_stub__Z27cudaFindDegreeZeroSCCKernelPiS_S_S_iiPiS_S_S_ii, @function
_Z55__device_stub__Z27cudaFindDegreeZeroSCCKernelPiS_S_S_iiPiS_S_S_ii:
.LFB5303:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L58
.L54:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L59
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27cudaFindDegreeZeroSCCKernelPiS_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L54
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5303:
.size _Z55__device_stub__Z27cudaFindDegreeZeroSCCKernelPiS_S_S_iiPiS_S_S_ii, .-_Z55__device_stub__Z27cudaFindDegreeZeroSCCKernelPiS_S_S_iiPiS_S_S_ii
.globl _Z27cudaFindDegreeZeroSCCKernelPiS_S_S_ii
.type _Z27cudaFindDegreeZeroSCCKernelPiS_S_S_ii, @function
_Z27cudaFindDegreeZeroSCCKernelPiS_S_S_ii:
.LFB5304:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z27cudaFindDegreeZeroSCCKernelPiS_S_S_iiPiS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5304:
.size _Z27cudaFindDegreeZeroSCCKernelPiS_S_S_ii, .-_Z27cudaFindDegreeZeroSCCKernelPiS_S_S_ii
.globl _Z48__device_stub__Z23cudaFindAllZeroesKernelPiS_S_iPiS_S_i
.type _Z48__device_stub__Z23cudaFindAllZeroesKernelPiS_S_iPiS_S_i, @function
_Z48__device_stub__Z23cudaFindAllZeroesKernelPiS_S_iPiS_S_i:
.LFB5305:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L66
.L62:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L67
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L66:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23cudaFindAllZeroesKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L62
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5305:
.size _Z48__device_stub__Z23cudaFindAllZeroesKernelPiS_S_iPiS_S_i, .-_Z48__device_stub__Z23cudaFindAllZeroesKernelPiS_S_iPiS_S_i
.globl _Z23cudaFindAllZeroesKernelPiS_S_i
.type _Z23cudaFindAllZeroesKernelPiS_S_i, @function
_Z23cudaFindAllZeroesKernelPiS_S_i:
.LFB5306:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z23cudaFindAllZeroesKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5306:
.size _Z23cudaFindAllZeroesKernelPiS_S_i, .-_Z23cudaFindAllZeroesKernelPiS_S_i
.globl _Z31cudaCallFindDegreeZeroSCCKerneljjPiS_S_S_S_ii
.type _Z31cudaCallFindDegreeZeroSCCKerneljjPiS_S_S_S_ii, @function
_Z31cudaCallFindDegreeZeroSCCKerneljjPiS_S_S_S_ii:
.LFB5270:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movq %rdx, %r14
movq %rcx, %r15
movq %r8, %r12
movq %r9, %r13
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L74
.L71:
movl %ebp, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %ebx, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L75
.L70:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L74:
.cfi_restore_state
movl 112(%rsp), %r9d
movl 104(%rsp), %r8d
movq %r13, %rcx
movq %r12, %rdx
movq %r15, %rsi
movq %r14, %rdi
call _Z55__device_stub__Z27cudaFindDegreeZeroSCCKernelPiS_S_S_iiPiS_S_S_ii
jmp .L71
.L75:
movl 112(%rsp), %ecx
movq 96(%rsp), %rdx
movq %r13, %rsi
movq %r12, %rdi
call _Z48__device_stub__Z23cudaFindAllZeroesKernelPiS_S_iPiS_S_i
jmp .L70
.cfi_endproc
.LFE5270:
.size _Z31cudaCallFindDegreeZeroSCCKerneljjPiS_S_S_S_ii, .-_Z31cudaCallFindDegreeZeroSCCKerneljjPiS_S_S_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23cudaFindAllZeroesKernelPiS_S_i"
.align 8
.LC1:
.string "_Z27cudaFindDegreeZeroSCCKernelPiS_S_S_ii"
.align 8
.LC2:
.string "_Z22cudaContainsTrueKernelPbPii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z13cudaBFSKernelPiPbS0_i"
.LC4:
.string "_Z13cudaTrimGraphPiS_Pbi"
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z26cudaAirportAdjacencyKernelPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5308:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23cudaFindAllZeroesKernelPiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z27cudaFindDegreeZeroSCCKernelPiS_S_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z22cudaContainsTrueKernelPbPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cudaBFSKernelPiPbS0_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cudaTrimGraphPiS_Pbi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z26cudaAirportAdjacencyKernelPiS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5308:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cuda_runtime.h>
#include "kosaraju.cuh"
/* Fill out the adjacency list and the reverse adjacency list as according to
* the routes given. Each route represents a directed edge.
*/
__global__
void cudaAirportAdjacencyKernel(int *dev_routes,
int *dev_adj,
int *dev_radj,
int n_ports,
int n_routes) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
while (i < n_routes) {
int first = dev_routes[2 * i];
int second = dev_routes[2 * i + 1];
dev_adj[first * n_ports + second] = 1;
dev_radj[second * n_ports + first] = 1;
i += blockDim.x * gridDim.x;
}
}
/* Wrapper function to call cudaAirportAdjacencyKernel. */
void cudaCallAirportAdjacencyKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *dev_routes,
int *dev_adj,
int *dev_radj,
int n_ports,
int n_routes) {
cudaAirportAdjacencyKernel<<<blocks, threadsPerBlock>>>
(dev_routes, dev_adj, dev_radj, n_ports, n_routes);
}
/* Remove any vertices with in-degree and out-degree 0, just for optimization. */
__global__
void cudaTrimGraph(int *m,
int *row_sum,
bool *mark,
int n_ports) {
// For i = 0 to n_ports - 1 inclusive, achieve the following:
// row_sum[i] = sum from j = 0 to n_ports - 1 of m[i * n_ports + j] * !mark[j]
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
while (i < n_ports) {
int total = 0;
for (int j = 0; j < n_ports; j++) {
total += m[i * n_ports + j] * !(mark[j]);
}
row_sum[i] = total;
i += blockDim.x * gridDim.x;
}
}
void cudaCallTrimGraph(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *adj,
int *row_sum,
bool *mark,
int n_ports) {
cudaTrimGraph<<<blocks, threadsPerBlock>>>(adj, row_sum, mark, n_ports);
}
__global__
void cudaBFSKernel(int *adj,
bool *frontier,
bool *visited,
int n_ports) {
// Do the BFS search
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
while (tid < n_ports) {
if (frontier[tid]) {
frontier[tid] = false;
visited[tid] = true;
for (int i = 0; i < n_ports; i++) {
if (adj[tid * n_ports + i] && !visited[i]) {
frontier[i] = true;
}
}
}
tid += blockDim.x * gridDim.x;
}
}
/* Returns whether the frontier array contains any true values. */
__global__
void cudaContainsTrueKernel(bool *frontier,
int *dev_flag,
int n_ports) {
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
while (tid < n_ports) {
if (frontier[tid]) {
dev_flag[0] *= 0;
}
tid += blockDim.x * gridDim.x;
}
}
/* Wrapper function to perform BFS. */
void cudaCallBFSKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *adj,
bool *visited,
bool *dev_frontier,
int start_port,
int n_ports,
int *dev_flag) {
int *flag = (int *) malloc(sizeof(int));
while (true) {
for (int i = 0; i < n_ports; i++) {
cudaBFSKernel<<<blocks, threadsPerBlock>>>
(adj, dev_frontier, visited, n_ports);
}
cudaContainsTrueKernel<<<blocks, threadsPerBlock>>>
(dev_frontier, dev_flag, n_ports);
cudaMemcpy(flag, dev_flag, sizeof(int), cudaMemcpyDeviceToHost);
if (flag[0]) {
break;
}
}
free(flag);
}
/* Fill out an array, one value for each airport. If an index i is some
* representative node of an SCC (that is not the starting airport) and we have
* that dev_zeroes[i] = 0 at the end of this kernel, then that means that
* index represents an airport who is a representative node of an SCC that has
* no incoming edges.
*/
__global__
void cudaFindDegreeZeroSCCKernel(int *adj,
int *radj,
int *reps,
int *dev_zeroes,
int start_port,
int n_ports) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
dev_zeroes[start_port] = 1;
while (i < n_ports) {
unsigned int curr_rep = reps[i];
for(int j = 0; j < n_ports; j++) {
if (radj[i * n_ports + j] == 1 && reps[j] != curr_rep) {
dev_zeroes[curr_rep] = 1;
break;
}
}
i += blockDim.x * gridDim.x;
}
}
/* Find number of representative nodes that have in-degree 0 (excluding
* starting airport). This is then the final answer to our algorithm.
*/
__global__
void cudaFindAllZeroesKernel(int *dev_reps,
int *dev_zeroes,
int *dev_total,
int n_ports){
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
while (i < n_ports) {
if(dev_reps[i] == i && dev_zeroes[i] == 0) {
atomicAdd(dev_total, 1);
}
i += blockDim.x * gridDim.x;
}
}
/* Wrapper function to call cudaFindDegreeZeroSCCKernel and
* cudaFindAllZeroesKernel.
*/
void cudaCallFindDegreeZeroSCCKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *dev_adj,
int *dev_radj,
int *dev_reps,
int *dev_zeroes,
int *dev_total,
int start_port,
int n_ports) {
cudaFindDegreeZeroSCCKernel<<<blocks, threadsPerBlock>>>
(dev_adj, dev_radj, dev_reps, dev_zeroes, start_port, n_ports);
cudaFindAllZeroesKernel<<<blocks, threadsPerBlock>>>
(dev_reps, dev_zeroes, dev_total, n_ports);
} | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <vector>
#include <map>
#include <unordered_map>
#include <stack>
#include <set>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
/* Copied over from CS 179 set 1 code for GPU Error Checking. */
#define gpuErrchk(ans) { gpu_assert((ans), __FILE__, __LINE__); }
inline void gpu_assert(hipError_t code, const char *file, int line,
bool abort = true) {
if (code != hipSuccess) {
fprintf(stderr, "gpu_assert: %s %s %d\n",
hipGetErrorString(code), file, line);
exit(code);
}
}
/* These are just wrapper functions to call kernels. */
void cudaCallAirportAdjacencyKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *dev_routes,
int *dev_adj,
int *dev_radj,
int n_ports,
int n_routes
);
void cudaCallTrimGraph(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *adj,
int *row_sum,
bool *mark,
int n_ports
);
void cudaCallBFSKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *adj,
bool *visited,
bool *dev_frontier,
int start_port,
int n_ports,
int *dev_flag
);
void cudaCallFindDegreeZeroSCCKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *dev_adj,
int *dev_radj,
int *dev_reps,
int *dev_zeroes,
int *dev_total,
int start_port,
int n_ports
); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <vector>
#include <map>
#include <unordered_map>
#include <stack>
#include <set>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
/* Copied over from CS 179 set 1 code for GPU Error Checking. */
#define gpuErrchk(ans) { gpu_assert((ans), __FILE__, __LINE__); }
inline void gpu_assert(hipError_t code, const char *file, int line,
bool abort = true) {
if (code != hipSuccess) {
fprintf(stderr, "gpu_assert: %s %s %d\n",
hipGetErrorString(code), file, line);
exit(code);
}
}
/* These are just wrapper functions to call kernels. */
void cudaCallAirportAdjacencyKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *dev_routes,
int *dev_adj,
int *dev_radj,
int n_ports,
int n_routes
);
void cudaCallTrimGraph(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *adj,
int *row_sum,
bool *mark,
int n_ports
);
void cudaCallBFSKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *adj,
bool *visited,
bool *dev_frontier,
int start_port,
int n_ports,
int *dev_flag
);
void cudaCallFindDegreeZeroSCCKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *dev_adj,
int *dev_radj,
int *dev_reps,
int *dev_zeroes,
int *dev_total,
int start_port,
int n_ports
); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <vector>
#include <map>
#include <unordered_map>
#include <stack>
#include <set>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
/* Copied over from CS 179 set 1 code for GPU Error Checking. */
#define gpuErrchk(ans) { gpu_assert((ans), __FILE__, __LINE__); }
inline void gpu_assert(hipError_t code, const char *file, int line,
bool abort = true) {
if (code != hipSuccess) {
fprintf(stderr, "gpu_assert: %s %s %d\n",
hipGetErrorString(code), file, line);
exit(code);
}
}
/* These are just wrapper functions to call kernels. */
void cudaCallAirportAdjacencyKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *dev_routes,
int *dev_adj,
int *dev_radj,
int n_ports,
int n_routes
);
void cudaCallTrimGraph(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *adj,
int *row_sum,
bool *mark,
int n_ports
);
void cudaCallBFSKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *adj,
bool *visited,
bool *dev_frontier,
int start_port,
int n_ports,
int *dev_flag
);
void cudaCallFindDegreeZeroSCCKernel(const unsigned int blocks,
const unsigned int threadsPerBlock,
int *dev_adj,
int *dev_radj,
int *dev_reps,
int *dev_zeroes,
int *dev_total,
int start_port,
int n_ports
); | .text
.file "kosaraju.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000065f_00000000-6_kosaraju.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5273:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5273:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z26cudaAirportAdjacencyKernelPiS_S_iiPiS_S_ii
.type _Z52__device_stub__Z26cudaAirportAdjacencyKernelPiS_S_iiPiS_S_ii, @function
_Z52__device_stub__Z26cudaAirportAdjacencyKernelPiS_S_iiPiS_S_ii:
.LFB5295:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26cudaAirportAdjacencyKernelPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5295:
.size _Z52__device_stub__Z26cudaAirportAdjacencyKernelPiS_S_iiPiS_S_ii, .-_Z52__device_stub__Z26cudaAirportAdjacencyKernelPiS_S_iiPiS_S_ii
.globl _Z26cudaAirportAdjacencyKernelPiS_S_ii
.type _Z26cudaAirportAdjacencyKernelPiS_S_ii, @function
_Z26cudaAirportAdjacencyKernelPiS_S_ii:
.LFB5296:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z26cudaAirportAdjacencyKernelPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5296:
.size _Z26cudaAirportAdjacencyKernelPiS_S_ii, .-_Z26cudaAirportAdjacencyKernelPiS_S_ii
.globl _Z30cudaCallAirportAdjacencyKerneljjPiS_S_ii
.type _Z30cudaCallAirportAdjacencyKerneljjPiS_S_ii, @function
_Z30cudaCallAirportAdjacencyKerneljjPiS_S_ii:
.LFB5267:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdx, %rbx
movq %rcx, %rbp
movq %r8, %r12
movl %r9d, %r13d
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl 80(%rsp), %r8d
movl %r13d, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z52__device_stub__Z26cudaAirportAdjacencyKernelPiS_S_iiPiS_S_ii
jmp .L11
.cfi_endproc
.LFE5267:
.size _Z30cudaCallAirportAdjacencyKerneljjPiS_S_ii, .-_Z30cudaCallAirportAdjacencyKerneljjPiS_S_ii
.globl _Z38__device_stub__Z13cudaTrimGraphPiS_PbiPiS_Pbi
.type _Z38__device_stub__Z13cudaTrimGraphPiS_PbiPiS_Pbi, @function
_Z38__device_stub__Z13cudaTrimGraphPiS_PbiPiS_Pbi:
.LFB5297:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13cudaTrimGraphPiS_Pbi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5297:
.size _Z38__device_stub__Z13cudaTrimGraphPiS_PbiPiS_Pbi, .-_Z38__device_stub__Z13cudaTrimGraphPiS_PbiPiS_Pbi
.globl _Z13cudaTrimGraphPiS_Pbi
.type _Z13cudaTrimGraphPiS_Pbi, @function
_Z13cudaTrimGraphPiS_Pbi:
.LFB5298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13cudaTrimGraphPiS_PbiPiS_Pbi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5298:
.size _Z13cudaTrimGraphPiS_Pbi, .-_Z13cudaTrimGraphPiS_Pbi
.globl _Z17cudaCallTrimGraphjjPiS_Pbi
.type _Z17cudaCallTrimGraphjjPiS_Pbi, @function
_Z17cudaCallTrimGraphjjPiS_Pbi:
.LFB5268:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdx, %rbx
movq %rcx, %rbp
movq %r8, %r12
movl %r9d, %r13d
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %r13d, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z38__device_stub__Z13cudaTrimGraphPiS_PbiPiS_Pbi
jmp .L23
.cfi_endproc
.LFE5268:
.size _Z17cudaCallTrimGraphjjPiS_Pbi, .-_Z17cudaCallTrimGraphjjPiS_Pbi
.globl _Z39__device_stub__Z13cudaBFSKernelPiPbS0_iPiPbS0_i
.type _Z39__device_stub__Z13cudaBFSKernelPiPbS0_iPiPbS0_i, @function
_Z39__device_stub__Z13cudaBFSKernelPiPbS0_iPiPbS0_i:
.LFB5299:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13cudaBFSKernelPiPbS0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5299:
.size _Z39__device_stub__Z13cudaBFSKernelPiPbS0_iPiPbS0_i, .-_Z39__device_stub__Z13cudaBFSKernelPiPbS0_iPiPbS0_i
.globl _Z13cudaBFSKernelPiPbS0_i
.type _Z13cudaBFSKernelPiPbS0_i, @function
_Z13cudaBFSKernelPiPbS0_i:
.LFB5300:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13cudaBFSKernelPiPbS0_iPiPbS0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5300:
.size _Z13cudaBFSKernelPiPbS0_i, .-_Z13cudaBFSKernelPiPbS0_i
.globl _Z45__device_stub__Z22cudaContainsTrueKernelPbPiiPbPii
.type _Z45__device_stub__Z22cudaContainsTrueKernelPbPiiPbPii, @function
_Z45__device_stub__Z22cudaContainsTrueKernelPbPiiPbPii:
.LFB5301:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22cudaContainsTrueKernelPbPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5301:
.size _Z45__device_stub__Z22cudaContainsTrueKernelPbPiiPbPii, .-_Z45__device_stub__Z22cudaContainsTrueKernelPbPiiPbPii
.globl _Z22cudaContainsTrueKernelPbPii
.type _Z22cudaContainsTrueKernelPbPii, @function
_Z22cudaContainsTrueKernelPbPii:
.LFB5302:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z22cudaContainsTrueKernelPbPiiPbPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5302:
.size _Z22cudaContainsTrueKernelPbPii, .-_Z22cudaContainsTrueKernelPbPii
.globl _Z17cudaCallBFSKerneljjPiPbS0_iiS_
.type _Z17cudaCallBFSKerneljjPiPbS0_iiS_, @function
_Z17cudaCallBFSKerneljjPiPbS0_iiS_:
.LFB5269:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %r13d
movl %esi, %r12d
movq %rdx, (%rsp)
movq %rcx, 8(%rsp)
movq %r8, %r14
movl 112(%rsp), %ebp
movl $4, %edi
call malloc@PLT
movq %rax, %r15
jmp .L48
.L45:
addl $1, %ebx
cmpl %ebx, %ebp
je .L44
.L46:
movl %r12d, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %r13d, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L45
movl %ebp, %ecx
movq 8(%rsp), %rdx
movq %r14, %rsi
movq (%rsp), %rdi
call _Z39__device_stub__Z13cudaBFSKernelPiPbS0_iPiPbS0_i
jmp .L45
.L44:
movl %r12d, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %r13d, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L47:
movl $2, %ecx
movl $4, %edx
movq 120(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
cmpl $0, (%r15)
jne .L53
.L48:
testl %ebp, %ebp
jle .L44
movl $0, %ebx
jmp .L46
.L52:
movl %ebp, %edx
movq 120(%rsp), %rsi
movq %r14, %rdi
call _Z45__device_stub__Z22cudaContainsTrueKernelPbPiiPbPii
jmp .L47
.L53:
movq %r15, %rdi
call free@PLT
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5269:
.size _Z17cudaCallBFSKerneljjPiPbS0_iiS_, .-_Z17cudaCallBFSKerneljjPiPbS0_iiS_
.globl _Z55__device_stub__Z27cudaFindDegreeZeroSCCKernelPiS_S_S_iiPiS_S_S_ii
.type _Z55__device_stub__Z27cudaFindDegreeZeroSCCKernelPiS_S_S_iiPiS_S_S_ii, @function
_Z55__device_stub__Z27cudaFindDegreeZeroSCCKernelPiS_S_S_iiPiS_S_S_ii:
.LFB5303:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L58
.L54:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L59
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27cudaFindDegreeZeroSCCKernelPiS_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L54
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5303:
.size _Z55__device_stub__Z27cudaFindDegreeZeroSCCKernelPiS_S_S_iiPiS_S_S_ii, .-_Z55__device_stub__Z27cudaFindDegreeZeroSCCKernelPiS_S_S_iiPiS_S_S_ii
.globl _Z27cudaFindDegreeZeroSCCKernelPiS_S_S_ii
.type _Z27cudaFindDegreeZeroSCCKernelPiS_S_S_ii, @function
_Z27cudaFindDegreeZeroSCCKernelPiS_S_S_ii:
.LFB5304:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z27cudaFindDegreeZeroSCCKernelPiS_S_S_iiPiS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5304:
.size _Z27cudaFindDegreeZeroSCCKernelPiS_S_S_ii, .-_Z27cudaFindDegreeZeroSCCKernelPiS_S_S_ii
.globl _Z48__device_stub__Z23cudaFindAllZeroesKernelPiS_S_iPiS_S_i
.type _Z48__device_stub__Z23cudaFindAllZeroesKernelPiS_S_iPiS_S_i, @function
_Z48__device_stub__Z23cudaFindAllZeroesKernelPiS_S_iPiS_S_i:
.LFB5305:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L66
.L62:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L67
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L66:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23cudaFindAllZeroesKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L62
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5305:
.size _Z48__device_stub__Z23cudaFindAllZeroesKernelPiS_S_iPiS_S_i, .-_Z48__device_stub__Z23cudaFindAllZeroesKernelPiS_S_iPiS_S_i
.globl _Z23cudaFindAllZeroesKernelPiS_S_i
.type _Z23cudaFindAllZeroesKernelPiS_S_i, @function
_Z23cudaFindAllZeroesKernelPiS_S_i:
.LFB5306:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z23cudaFindAllZeroesKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5306:
.size _Z23cudaFindAllZeroesKernelPiS_S_i, .-_Z23cudaFindAllZeroesKernelPiS_S_i
.globl _Z31cudaCallFindDegreeZeroSCCKerneljjPiS_S_S_S_ii
.type _Z31cudaCallFindDegreeZeroSCCKerneljjPiS_S_S_S_ii, @function
_Z31cudaCallFindDegreeZeroSCCKerneljjPiS_S_S_S_ii:
.LFB5270:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movq %rdx, %r14
movq %rcx, %r15
movq %r8, %r12
movq %r9, %r13
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L74
.L71:
movl %ebp, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %ebx, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L75
.L70:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L74:
.cfi_restore_state
movl 112(%rsp), %r9d
movl 104(%rsp), %r8d
movq %r13, %rcx
movq %r12, %rdx
movq %r15, %rsi
movq %r14, %rdi
call _Z55__device_stub__Z27cudaFindDegreeZeroSCCKernelPiS_S_S_iiPiS_S_S_ii
jmp .L71
.L75:
movl 112(%rsp), %ecx
movq 96(%rsp), %rdx
movq %r13, %rsi
movq %r12, %rdi
call _Z48__device_stub__Z23cudaFindAllZeroesKernelPiS_S_iPiS_S_i
jmp .L70
.cfi_endproc
.LFE5270:
.size _Z31cudaCallFindDegreeZeroSCCKerneljjPiS_S_S_S_ii, .-_Z31cudaCallFindDegreeZeroSCCKerneljjPiS_S_S_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23cudaFindAllZeroesKernelPiS_S_i"
.align 8
.LC1:
.string "_Z27cudaFindDegreeZeroSCCKernelPiS_S_S_ii"
.align 8
.LC2:
.string "_Z22cudaContainsTrueKernelPbPii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z13cudaBFSKernelPiPbS0_i"
.LC4:
.string "_Z13cudaTrimGraphPiS_Pbi"
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z26cudaAirportAdjacencyKernelPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5308:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23cudaFindAllZeroesKernelPiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z27cudaFindDegreeZeroSCCKernelPiS_S_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z22cudaContainsTrueKernelPbPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cudaBFSKernelPiPbS0_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cudaTrimGraphPiS_Pbi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z26cudaAirportAdjacencyKernelPiS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5308:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kosaraju.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#define N 5
__global__ void add(int* a, int* b, int* c)
{
int tid;
tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void)
{
int a[N],b[N],c[N];
int size=sizeof(int);
int i;
for(i=0;i<N;i++)
{
a[i] = i;
b[i] = 2*i;
}
int *d_a, *d_b, *d_c;
cudaMalloc((void **)&d_a,N*size);
cudaMalloc((void **)&d_b,N*size);
cudaMalloc((void **)&d_c,N*size);
cudaMemcpy(d_a,a,N*size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,N*size,cudaMemcpyHostToDevice);
add<<<1,N>>>(d_a,d_b,d_c);
cudaMemcpy(c,d_c,size*N,cudaMemcpyDeviceToHost);
for(i=0;i<N;i++)
printf("Sum is %d\n",c[i]);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#define N 5
__global__ void add(int* a, int* b, int* c)
{
int tid;
tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void)
{
int a[N],b[N],c[N];
int size=sizeof(int);
int i;
for(i=0;i<N;i++)
{
a[i] = i;
b[i] = 2*i;
}
int *d_a, *d_b, *d_c;
cudaMalloc((void **)&d_a,N*size);
cudaMalloc((void **)&d_b,N*size);
cudaMalloc((void **)&d_c,N*size);
cudaMemcpy(d_a,a,N*size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,N*size,cudaMemcpyHostToDevice);
add<<<1,N>>>(d_a,d_b,d_c);
cudaMemcpy(c,d_c,size*N,cudaMemcpyDeviceToHost);
for(i=0;i<N;i++)
printf("Sum is %d\n",c[i]);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_0008d329_00000000-6_W6P1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Sum is %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $144, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $0, 48(%rsp)
movl $0, 80(%rsp)
movl $1, 52(%rsp)
movl $2, 84(%rsp)
movl $2, 56(%rsp)
movl $4, 88(%rsp)
movl $3, 60(%rsp)
movl $6, 92(%rsp)
movl $4, 64(%rsp)
movl $8, 96(%rsp)
movq %rsp, %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 112(%rsp), %rbx
movl $2, %ecx
movl $20, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 132(%rsp), %r12
leaq .LC0(%rip), %rbp
.L13:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#define N 5
__global__ void add(int* a, int* b, int* c)
{
int tid;
tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void)
{
int a[N],b[N],c[N];
int size=sizeof(int);
int i;
for(i=0;i<N;i++)
{
a[i] = i;
b[i] = 2*i;
}
int *d_a, *d_b, *d_c;
cudaMalloc((void **)&d_a,N*size);
cudaMalloc((void **)&d_b,N*size);
cudaMalloc((void **)&d_c,N*size);
cudaMemcpy(d_a,a,N*size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,N*size,cudaMemcpyHostToDevice);
add<<<1,N>>>(d_a,d_b,d_c);
cudaMemcpy(c,d_c,size*N,cudaMemcpyDeviceToHost);
for(i=0;i<N;i++)
printf("Sum is %d\n",c[i]);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#define N 5
__global__ void add(int* a, int* b, int* c)
{
int tid;
tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void)
{
int a[N],b[N],c[N];
int size=sizeof(int);
int i;
for(i=0;i<N;i++)
{
a[i] = i;
b[i] = 2*i;
}
int *d_a, *d_b, *d_c;
hipMalloc((void **)&d_a,N*size);
hipMalloc((void **)&d_b,N*size);
hipMalloc((void **)&d_c,N*size);
hipMemcpy(d_a,a,N*size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,N*size,hipMemcpyHostToDevice);
add<<<1,N>>>(d_a,d_b,d_c);
hipMemcpy(c,d_c,size*N,hipMemcpyDeviceToHost);
for(i=0;i<N;i++)
printf("Sum is %d\n",c[i]);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#define N 5
__global__ void add(int* a, int* b, int* c)
{
int tid;
tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void)
{
int a[N],b[N],c[N];
int size=sizeof(int);
int i;
for(i=0;i<N;i++)
{
a[i] = i;
b[i] = 2*i;
}
int *d_a, *d_b, *d_c;
hipMalloc((void **)&d_a,N*size);
hipMalloc((void **)&d_b,N*size);
hipMalloc((void **)&d_c,N*size);
hipMemcpy(d_a,a,N*size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,N*size,hipMemcpyHostToDevice);
add<<<1,N>>>(d_a,d_b,d_c);
hipMemcpy(c,d_c,size*N,hipMemcpyDeviceToHost);
for(i=0;i<N;i++)
printf("Sum is %d\n",c[i]);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#define N 5
__global__ void add(int* a, int* b, int* c)
{
int tid;
tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void)
{
int a[N],b[N],c[N];
int size=sizeof(int);
int i;
for(i=0;i<N;i++)
{
a[i] = i;
b[i] = 2*i;
}
int *d_a, *d_b, *d_c;
hipMalloc((void **)&d_a,N*size);
hipMalloc((void **)&d_b,N*size);
hipMalloc((void **)&d_c,N*size);
hipMemcpy(d_a,a,N*size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,N*size,hipMemcpyHostToDevice);
add<<<1,N>>>(d_a,d_b,d_c);
hipMemcpy(c,d_c,size*N,hipMemcpyDeviceToHost);
for(i=0;i<N;i++)
printf("Sum is %d\n",c[i]);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "W6P1.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $192, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -16
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ecx, 160(%rsp,%rcx,4)
movl %eax, 128(%rsp,%rcx,4)
incq %rcx
addl $2, %eax
cmpq $5, %rcx
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $20, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 32(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB1_5
# %bb.6:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Sum is %d\n"
.size .L.str, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008d329_00000000-6_W6P1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Sum is %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $144, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $0, 48(%rsp)
movl $0, 80(%rsp)
movl $1, 52(%rsp)
movl $2, 84(%rsp)
movl $2, 56(%rsp)
movl $4, 88(%rsp)
movl $3, 60(%rsp)
movl $6, 92(%rsp)
movl $4, 64(%rsp)
movl $8, 96(%rsp)
movq %rsp, %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 112(%rsp), %rbx
movl $2, %ecx
movl $20, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 132(%rsp), %r12
leaq .LC0(%rip), %rbp
.L13:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "W6P1.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $192, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -16
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ecx, 160(%rsp,%rcx,4)
movl %eax, 128(%rsp,%rcx,4)
incq %rcx
addl $2, %eax
cmpq $5, %rcx
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $20, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 32(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB1_5
# %bb.6:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Sum is %d\n"
.size .L.str, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<cuda.h>
#include<math.h>
#include<sys/time.h>
__global__
void Matadd(char* A, char*B, int N)
{
}
int main()
{
for(int j=0;j<=25;j++)
{
cudaEvent_t start1,stop1,start2,stop2;
float time1,time2, time3;
int i;
int N = pow(2,j);
size_t size = N;
printf ("\n The value of N is %d",N);
cudaEventCreate(&start1);
cudaEventCreate(&stop1);
cudaEventCreate(&start2);
cudaEventCreate(&stop2);
//allocate input matrices hA, hB, hC,refC in host memory
char* hA; cudaMallocHost(&hA, size);
char* hB; cudaMallocHost(&hB, size);
for(i=0;i<N;i++)
{
hA[i] = rand()%20-10;
}
//allocate memory on the device at location A (GPU)
char* dA;
cudaMalloc((void**) &dA,size);
//allocate memory on the device at location B (GPU)
char* dB;
cudaMalloc((void**) &dB,size);
//timing start for inclusive timing
cudaEventRecord(start1, 0);
//copy vectors from host memory to devie memory
cudaMemcpy(dA, hA, size, cudaMemcpyHostToDevice);
cudaEventRecord(stop1, 0);
cudaEventSynchronize(stop1);
//invoke GPU kernel, with two blocks each having eight threads
int threadsperblock = 16;
int blockspergrid = (N + threadsperblock - 1)/ threadsperblock;
cudaEventRecord(start2, 0);
//timing start for exclusive timing
//cudaEventRecord(start2, 0);
Matadd<<<blockspergrid,threadsperblock>>>(dA,dB,N);
cudaMemcpy(hB, dB, size, cudaMemcpyDeviceToHost);
cudaEventRecord(stop2, 0);
cudaEventSynchronize(stop2);
cudaEventElapsedTime(&time1,start1,stop1);
cudaEventElapsedTime(&time2,start2,stop2);
printf("\n The Host to Device time for location A in microseconds for 2 to power %d is %f respectively \n",j,time1);
printf("\n The Device to Host time for location B in microseconds for 2 to power %d is %f respectively \n",j,time2);
time3 = time1 + time2;
printf("\n The total data transfer time in microseconds for 2 to power %d is %f respectively \n",j,time3);
cudaFree(hA);
cudaFree(hB);
cudaFree(dA);
cudaFree(dB);
}
return 0;
} | code for sm_80
Function : _Z6MataddPcS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<cuda.h>
#include<math.h>
#include<sys/time.h>
__global__
void Matadd(char* A, char*B, int N)
{
}
int main()
{
for(int j=0;j<=25;j++)
{
cudaEvent_t start1,stop1,start2,stop2;
float time1,time2, time3;
int i;
int N = pow(2,j);
size_t size = N;
printf ("\n The value of N is %d",N);
cudaEventCreate(&start1);
cudaEventCreate(&stop1);
cudaEventCreate(&start2);
cudaEventCreate(&stop2);
//allocate input matrices hA, hB, hC,refC in host memory
char* hA; cudaMallocHost(&hA, size);
char* hB; cudaMallocHost(&hB, size);
for(i=0;i<N;i++)
{
hA[i] = rand()%20-10;
}
//allocate memory on the device at location A (GPU)
char* dA;
cudaMalloc((void**) &dA,size);
//allocate memory on the device at location B (GPU)
char* dB;
cudaMalloc((void**) &dB,size);
//timing start for inclusive timing
cudaEventRecord(start1, 0);
//copy vectors from host memory to devie memory
cudaMemcpy(dA, hA, size, cudaMemcpyHostToDevice);
cudaEventRecord(stop1, 0);
cudaEventSynchronize(stop1);
//invoke GPU kernel, with two blocks each having eight threads
int threadsperblock = 16;
int blockspergrid = (N + threadsperblock - 1)/ threadsperblock;
cudaEventRecord(start2, 0);
//timing start for exclusive timing
//cudaEventRecord(start2, 0);
Matadd<<<blockspergrid,threadsperblock>>>(dA,dB,N);
cudaMemcpy(hB, dB, size, cudaMemcpyDeviceToHost);
cudaEventRecord(stop2, 0);
cudaEventSynchronize(stop2);
cudaEventElapsedTime(&time1,start1,stop1);
cudaEventElapsedTime(&time2,start2,stop2);
printf("\n The Host to Device time for location A in microseconds for 2 to power %d is %f respectively \n",j,time1);
printf("\n The Device to Host time for location B in microseconds for 2 to power %d is %f respectively \n",j,time2);
time3 = time1 + time2;
printf("\n The total data transfer time in microseconds for 2 to power %d is %f respectively \n",j,time3);
cudaFree(hA);
cudaFree(hB);
cudaFree(dA);
cudaFree(dB);
}
return 0;
} | .file "tmpxft_001bb4b1_00000000-6_hw7p1_4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6MataddPcS_iPcS_i
.type _Z28__device_stub__Z6MataddPcS_iPcS_i, @function
_Z28__device_stub__Z6MataddPcS_iPcS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6MataddPcS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z6MataddPcS_iPcS_i, .-_Z28__device_stub__Z6MataddPcS_iPcS_i
.globl _Z6MataddPcS_i
.type _Z6MataddPcS_i, @function
_Z6MataddPcS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6MataddPcS_iPcS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6MataddPcS_i, .-_Z6MataddPcS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n The value of N is %d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\n The Host to Device time for location A in microseconds for 2 to power %d is %f respectively \n"
.align 8
.LC3:
.string "\n The Device to Host time for location B in microseconds for 2 to power %d is %f respectively \n"
.align 8
.LC4:
.string "\n The total data transfer time in microseconds for 2 to power %d is %f respectively \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $0, %r13d
leaq .LC1(%rip), %r15
leaq .LC2(%rip), %r14
jmp .L15
.L14:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 64(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 76(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 64(%rsp), %xmm0
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
movl %r13d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 64(%rsp), %xmm0
addss 76(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl %r13d, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
addl $1, %r13d
cmpl $26, %r13d
je .L20
.L15:
pxor %xmm1, %xmm1
cvtsi2sdl %r13d, %xmm1
movsd .LC0(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %r12d
movslq %r12d, %rbp
movl %r12d, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
movl $0, %edx
movq %rbp, %rsi
call cudaHostAlloc@PLT
leaq 40(%rsp), %rdi
movl $0, %edx
movq %rbp, %rsi
call cudaHostAlloc@PLT
testl %r12d, %r12d
jle .L12
movl $0, %ebx
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
subl $10, %eax
movq 32(%rsp), %rdx
movb %al, (%rdx,%rbx)
addq $1, %rbx
cmpq %rbx, %rbp
jne .L13
.L12:
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 32(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leal 30(%r12), %eax
movl %r12d, %edx
addl $15, %edx
cmovns %edx, %eax
sarl $4, %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movl %r12d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z28__device_stub__Z6MataddPcS_iPcS_i
jmp .L14
.L20:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6MataddPcS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MataddPcS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<cuda.h>
#include<math.h>
#include<sys/time.h>
__global__
void Matadd(char* A, char*B, int N)
{
}
int main()
{
for(int j=0;j<=25;j++)
{
cudaEvent_t start1,stop1,start2,stop2;
float time1,time2, time3;
int i;
int N = pow(2,j);
size_t size = N;
printf ("\n The value of N is %d",N);
cudaEventCreate(&start1);
cudaEventCreate(&stop1);
cudaEventCreate(&start2);
cudaEventCreate(&stop2);
//allocate input matrices hA, hB, hC,refC in host memory
char* hA; cudaMallocHost(&hA, size);
char* hB; cudaMallocHost(&hB, size);
for(i=0;i<N;i++)
{
hA[i] = rand()%20-10;
}
//allocate memory on the device at location A (GPU)
char* dA;
cudaMalloc((void**) &dA,size);
//allocate memory on the device at location B (GPU)
char* dB;
cudaMalloc((void**) &dB,size);
//timing start for inclusive timing
cudaEventRecord(start1, 0);
//copy vectors from host memory to devie memory
cudaMemcpy(dA, hA, size, cudaMemcpyHostToDevice);
cudaEventRecord(stop1, 0);
cudaEventSynchronize(stop1);
//invoke GPU kernel, with two blocks each having eight threads
int threadsperblock = 16;
int blockspergrid = (N + threadsperblock - 1)/ threadsperblock;
cudaEventRecord(start2, 0);
//timing start for exclusive timing
//cudaEventRecord(start2, 0);
Matadd<<<blockspergrid,threadsperblock>>>(dA,dB,N);
cudaMemcpy(hB, dB, size, cudaMemcpyDeviceToHost);
cudaEventRecord(stop2, 0);
cudaEventSynchronize(stop2);
cudaEventElapsedTime(&time1,start1,stop1);
cudaEventElapsedTime(&time2,start2,stop2);
printf("\n The Host to Device time for location A in microseconds for 2 to power %d is %f respectively \n",j,time1);
printf("\n The Device to Host time for location B in microseconds for 2 to power %d is %f respectively \n",j,time2);
time3 = time1 + time2;
printf("\n The total data transfer time in microseconds for 2 to power %d is %f respectively \n",j,time3);
cudaFree(hA);
cudaFree(hB);
cudaFree(dA);
cudaFree(dB);
}
return 0;
} | #include<stdio.h>
#include<hip/hip_runtime.h>
#include<math.h>
#include<sys/time.h>
__global__
void Matadd(char* A, char*B, int N)
{
}
int main()
{
for(int j=0;j<=25;j++)
{
hipEvent_t start1,stop1,start2,stop2;
float time1,time2, time3;
int i;
int N = pow(2,j);
size_t size = N;
printf ("\n The value of N is %d",N);
hipEventCreate(&start1);
hipEventCreate(&stop1);
hipEventCreate(&start2);
hipEventCreate(&stop2);
//allocate input matrices hA, hB, hC,refC in host memory
char* hA; hipHostMalloc(&hA, size, hipHostMallocDefault);
char* hB; hipHostMalloc(&hB, size, hipHostMallocDefault);
for(i=0;i<N;i++)
{
hA[i] = rand()%20-10;
}
//allocate memory on the device at location A (GPU)
char* dA;
hipMalloc((void**) &dA,size);
//allocate memory on the device at location B (GPU)
char* dB;
hipMalloc((void**) &dB,size);
//timing start for inclusive timing
hipEventRecord(start1, 0);
//copy vectors from host memory to devie memory
hipMemcpy(dA, hA, size, hipMemcpyHostToDevice);
hipEventRecord(stop1, 0);
hipEventSynchronize(stop1);
//invoke GPU kernel, with two blocks each having eight threads
int threadsperblock = 16;
int blockspergrid = (N + threadsperblock - 1)/ threadsperblock;
hipEventRecord(start2, 0);
//timing start for exclusive timing
//cudaEventRecord(start2, 0);
Matadd<<<blockspergrid,threadsperblock>>>(dA,dB,N);
hipMemcpy(hB, dB, size, hipMemcpyDeviceToHost);
hipEventRecord(stop2, 0);
hipEventSynchronize(stop2);
hipEventElapsedTime(&time1,start1,stop1);
hipEventElapsedTime(&time2,start2,stop2);
printf("\n The Host to Device time for location A in microseconds for 2 to power %d is %f respectively \n",j,time1);
printf("\n The Device to Host time for location B in microseconds for 2 to power %d is %f respectively \n",j,time2);
time3 = time1 + time2;
printf("\n The total data transfer time in microseconds for 2 to power %d is %f respectively \n",j,time3);
hipFree(hA);
hipFree(hB);
hipFree(dA);
hipFree(dB);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
#include<math.h>
#include<sys/time.h>
__global__
void Matadd(char* A, char*B, int N)
{
}
int main()
{
for(int j=0;j<=25;j++)
{
hipEvent_t start1,stop1,start2,stop2;
float time1,time2, time3;
int i;
int N = pow(2,j);
size_t size = N;
printf ("\n The value of N is %d",N);
hipEventCreate(&start1);
hipEventCreate(&stop1);
hipEventCreate(&start2);
hipEventCreate(&stop2);
//allocate input matrices hA, hB, hC,refC in host memory
char* hA; hipHostMalloc(&hA, size, hipHostMallocDefault);
char* hB; hipHostMalloc(&hB, size, hipHostMallocDefault);
for(i=0;i<N;i++)
{
hA[i] = rand()%20-10;
}
//allocate memory on the device at location A (GPU)
char* dA;
hipMalloc((void**) &dA,size);
//allocate memory on the device at location B (GPU)
char* dB;
hipMalloc((void**) &dB,size);
//timing start for inclusive timing
hipEventRecord(start1, 0);
//copy vectors from host memory to devie memory
hipMemcpy(dA, hA, size, hipMemcpyHostToDevice);
hipEventRecord(stop1, 0);
hipEventSynchronize(stop1);
//invoke GPU kernel, with two blocks each having eight threads
int threadsperblock = 16;
int blockspergrid = (N + threadsperblock - 1)/ threadsperblock;
hipEventRecord(start2, 0);
//timing start for exclusive timing
//cudaEventRecord(start2, 0);
Matadd<<<blockspergrid,threadsperblock>>>(dA,dB,N);
hipMemcpy(hB, dB, size, hipMemcpyDeviceToHost);
hipEventRecord(stop2, 0);
hipEventSynchronize(stop2);
hipEventElapsedTime(&time1,start1,stop1);
hipEventElapsedTime(&time2,start2,stop2);
printf("\n The Host to Device time for location A in microseconds for 2 to power %d is %f respectively \n",j,time1);
printf("\n The Device to Host time for location B in microseconds for 2 to power %d is %f respectively \n",j,time2);
time3 = time1 + time2;
printf("\n The total data transfer time in microseconds for 2 to power %d is %f respectively \n",j,time3);
hipFree(hA);
hipFree(hB);
hipFree(dA);
hipFree(dB);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6MataddPcS_i
.globl _Z6MataddPcS_i
.p2align 8
.type _Z6MataddPcS_i,@function
_Z6MataddPcS_i:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6MataddPcS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6MataddPcS_i, .Lfunc_end0-_Z6MataddPcS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6MataddPcS_i
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6MataddPcS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
#include<math.h>
#include<sys/time.h>
__global__
void Matadd(char* A, char*B, int N)
{
}
int main()
{
for(int j=0;j<=25;j++)
{
hipEvent_t start1,stop1,start2,stop2;
float time1,time2, time3;
int i;
int N = pow(2,j);
size_t size = N;
printf ("\n The value of N is %d",N);
hipEventCreate(&start1);
hipEventCreate(&stop1);
hipEventCreate(&start2);
hipEventCreate(&stop2);
//allocate input matrices hA, hB, hC,refC in host memory
char* hA; hipHostMalloc(&hA, size, hipHostMallocDefault);
char* hB; hipHostMalloc(&hB, size, hipHostMallocDefault);
for(i=0;i<N;i++)
{
hA[i] = rand()%20-10;
}
//allocate memory on the device at location A (GPU)
char* dA;
hipMalloc((void**) &dA,size);
//allocate memory on the device at location B (GPU)
char* dB;
hipMalloc((void**) &dB,size);
//timing start for inclusive timing
hipEventRecord(start1, 0);
//copy vectors from host memory to devie memory
hipMemcpy(dA, hA, size, hipMemcpyHostToDevice);
hipEventRecord(stop1, 0);
hipEventSynchronize(stop1);
//invoke GPU kernel, with two blocks each having eight threads
int threadsperblock = 16;
int blockspergrid = (N + threadsperblock - 1)/ threadsperblock;
hipEventRecord(start2, 0);
//timing start for exclusive timing
//cudaEventRecord(start2, 0);
Matadd<<<blockspergrid,threadsperblock>>>(dA,dB,N);
hipMemcpy(hB, dB, size, hipMemcpyDeviceToHost);
hipEventRecord(stop2, 0);
hipEventSynchronize(stop2);
hipEventElapsedTime(&time1,start1,stop1);
hipEventElapsedTime(&time2,start2,stop2);
printf("\n The Host to Device time for location A in microseconds for 2 to power %d is %f respectively \n",j,time1);
printf("\n The Device to Host time for location B in microseconds for 2 to power %d is %f respectively \n",j,time2);
time3 = time1 + time2;
printf("\n The total data transfer time in microseconds for 2 to power %d is %f respectively \n",j,time3);
hipFree(hA);
hipFree(hB);
hipFree(dA);
hipFree(dB);
}
return 0;
} | .text
.file "hw7p1_4.hip"
.globl _Z21__device_stub__MataddPcS_i # -- Begin function _Z21__device_stub__MataddPcS_i
.p2align 4, 0x90
.type _Z21__device_stub__MataddPcS_i,@function
_Z21__device_stub__MataddPcS_i: # @_Z21__device_stub__MataddPcS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6MataddPcS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__MataddPcS_i, .Lfunc_end0-_Z21__device_stub__MataddPcS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %rax # imm = 0x100000000
leaq 16(%rax), %r15
xorl %ebp, %ebp
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_1 Depth=1
movq 56(%rsp), %rdi
movq (%rsp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 80(%rsp), %rdi
callq hipEventElapsedTime
movq 64(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 40(%rsp), %rdi
callq hipEventElapsedTime
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebp, %esi
movb $1, %al
callq printf
movss 40(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movl %ebp, %esi
movb $1, %al
callq printf
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 40(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movl %ebp, %esi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
incl %ebp
cmpl $26, %ebp
je .LBB1_7
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %ebp, %edi
callq ldexp@PLT
cvttsd2si %xmm0, %r12d
movslq %r12d, %rbx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 56(%rsp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
testl %ebx, %ebx
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
# in Loop: Header=BB1_1 Depth=1
movl %r12d, %r14d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
addb $-10, %al
movq 16(%rsp), %rcx
movb %al, (%rcx,%r13)
incq %r13
cmpq %r13, %r14
jne .LBB1_3
.LBB1_4: # %._crit_edge
# in Loop: Header=BB1_1 Depth=1
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
leal 15(%r12), %eax
leal 30(%r12), %r14d
testl %eax, %eax
cmovnsl %eax, %r14d
sarl $4, %r14d
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r14
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl %r12d, 52(%rsp)
leaq 144(%rsp), %rax
movq %rax, 80(%rsp)
leaq 136(%rsp), %rax
movq %rax, 88(%rsp)
leaq 52(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
movl $_Z6MataddPcS_i, %edi
leaq 80(%rsp), %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_6
.LBB1_7:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MataddPcS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6MataddPcS_i,@object # @_Z6MataddPcS_i
.section .rodata,"a",@progbits
.globl _Z6MataddPcS_i
.p2align 3, 0x0
_Z6MataddPcS_i:
.quad _Z21__device_stub__MataddPcS_i
.size _Z6MataddPcS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n The value of N is %d"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n The Host to Device time for location A in microseconds for 2 to power %d is %f respectively \n"
.size .L.str.1, 97
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n The Device to Host time for location B in microseconds for 2 to power %d is %f respectively \n"
.size .L.str.2, 97
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n The total data transfer time in microseconds for 2 to power %d is %f respectively \n"
.size .L.str.3, 87
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6MataddPcS_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__MataddPcS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6MataddPcS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6MataddPcS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6MataddPcS_i
.globl _Z6MataddPcS_i
.p2align 8
.type _Z6MataddPcS_i,@function
_Z6MataddPcS_i:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6MataddPcS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6MataddPcS_i, .Lfunc_end0-_Z6MataddPcS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6MataddPcS_i
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6MataddPcS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001bb4b1_00000000-6_hw7p1_4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6MataddPcS_iPcS_i
.type _Z28__device_stub__Z6MataddPcS_iPcS_i, @function
_Z28__device_stub__Z6MataddPcS_iPcS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6MataddPcS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z6MataddPcS_iPcS_i, .-_Z28__device_stub__Z6MataddPcS_iPcS_i
.globl _Z6MataddPcS_i
.type _Z6MataddPcS_i, @function
_Z6MataddPcS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6MataddPcS_iPcS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6MataddPcS_i, .-_Z6MataddPcS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n The value of N is %d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\n The Host to Device time for location A in microseconds for 2 to power %d is %f respectively \n"
.align 8
.LC3:
.string "\n The Device to Host time for location B in microseconds for 2 to power %d is %f respectively \n"
.align 8
.LC4:
.string "\n The total data transfer time in microseconds for 2 to power %d is %f respectively \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $0, %r13d
leaq .LC1(%rip), %r15
leaq .LC2(%rip), %r14
jmp .L15
.L14:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 64(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 76(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 64(%rsp), %xmm0
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
movl %r13d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 64(%rsp), %xmm0
addss 76(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl %r13d, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
addl $1, %r13d
cmpl $26, %r13d
je .L20
.L15:
pxor %xmm1, %xmm1
cvtsi2sdl %r13d, %xmm1
movsd .LC0(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %r12d
movslq %r12d, %rbp
movl %r12d, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
movl $0, %edx
movq %rbp, %rsi
call cudaHostAlloc@PLT
leaq 40(%rsp), %rdi
movl $0, %edx
movq %rbp, %rsi
call cudaHostAlloc@PLT
testl %r12d, %r12d
jle .L12
movl $0, %ebx
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
subl $10, %eax
movq 32(%rsp), %rdx
movb %al, (%rdx,%rbx)
addq $1, %rbx
cmpq %rbx, %rbp
jne .L13
.L12:
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 32(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leal 30(%r12), %eax
movl %r12d, %edx
addl $15, %edx
cmovns %edx, %eax
sarl $4, %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movl %r12d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z28__device_stub__Z6MataddPcS_iPcS_i
jmp .L14
.L20:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6MataddPcS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MataddPcS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hw7p1_4.hip"
.globl _Z21__device_stub__MataddPcS_i # -- Begin function _Z21__device_stub__MataddPcS_i
.p2align 4, 0x90
.type _Z21__device_stub__MataddPcS_i,@function
_Z21__device_stub__MataddPcS_i: # @_Z21__device_stub__MataddPcS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6MataddPcS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__MataddPcS_i, .Lfunc_end0-_Z21__device_stub__MataddPcS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %rax # imm = 0x100000000
leaq 16(%rax), %r15
xorl %ebp, %ebp
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_1 Depth=1
movq 56(%rsp), %rdi
movq (%rsp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 80(%rsp), %rdi
callq hipEventElapsedTime
movq 64(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 40(%rsp), %rdi
callq hipEventElapsedTime
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebp, %esi
movb $1, %al
callq printf
movss 40(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movl %ebp, %esi
movb $1, %al
callq printf
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 40(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movl %ebp, %esi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
incl %ebp
cmpl $26, %ebp
je .LBB1_7
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %ebp, %edi
callq ldexp@PLT
cvttsd2si %xmm0, %r12d
movslq %r12d, %rbx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 56(%rsp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
testl %ebx, %ebx
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
# in Loop: Header=BB1_1 Depth=1
movl %r12d, %r14d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
addb $-10, %al
movq 16(%rsp), %rcx
movb %al, (%rcx,%r13)
incq %r13
cmpq %r13, %r14
jne .LBB1_3
.LBB1_4: # %._crit_edge
# in Loop: Header=BB1_1 Depth=1
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
leal 15(%r12), %eax
leal 30(%r12), %r14d
testl %eax, %eax
cmovnsl %eax, %r14d
sarl $4, %r14d
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r14
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl %r12d, 52(%rsp)
leaq 144(%rsp), %rax
movq %rax, 80(%rsp)
leaq 136(%rsp), %rax
movq %rax, 88(%rsp)
leaq 52(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
movl $_Z6MataddPcS_i, %edi
leaq 80(%rsp), %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_6
.LBB1_7:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MataddPcS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6MataddPcS_i,@object # @_Z6MataddPcS_i
.section .rodata,"a",@progbits
.globl _Z6MataddPcS_i
.p2align 3, 0x0
_Z6MataddPcS_i:
.quad _Z21__device_stub__MataddPcS_i
.size _Z6MataddPcS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n The value of N is %d"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n The Host to Device time for location A in microseconds for 2 to power %d is %f respectively \n"
.size .L.str.1, 97
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n The Device to Host time for location B in microseconds for 2 to power %d is %f respectively \n"
.size .L.str.2, 97
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n The total data transfer time in microseconds for 2 to power %d is %f respectively \n"
.size .L.str.3, 87
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6MataddPcS_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__MataddPcS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6MataddPcS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
__global__ void normal(int *a, int *b, int *c, int len)
{
int myrow = blockIdx.x;
__shared__ int smem[256];
while(myrow <len)
{
for (int i = 0; i < len; i ++)//which col of right matrix
{
int tid = threadIdx.x;
int res = 0;
while( tid < len ) // vector vector multiplication
{
res += a[myrow*len + tid] * b[tid*len + i];
tid += blockDim.x;
}
smem[threadIdx.x] = res;
__syncthreads();
for (int idx = blockDim.x/2; idx > 0; idx = idx/2)
{
if(threadIdx.x < idx)
{
int temp = smem[threadIdx.x] + smem[threadIdx.x + idx];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
c[myrow*len + i] = smem[0];
}
}
myrow += gridDim.x;
}
__global__ void transpose(int *a, int *b, int *c, int len)
{
int myrow = blockIdx.x;
__shared__ int smem[256];
while(myrow <len)
{
for (int i = 0; i < len; i ++)//which col of right matrix
{
int tid = threadIdx.x;
int res = 0;
while( tid < len ) // vector vector multiplication
{
res += a[myrow*len + tid] * b[i*len + tid];
tid += blockDim.x;
}
smem[threadIdx.x] = res;
__syncthreads();
for (int i = blockDim.x/2; i > 0; i = i/2)
{
if(threadIdx.x < i)
{
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
c[myrow*len + i] = smem[0];
}
myrow += gridDim.x;
}
} | code for sm_80
Function : _Z9transposePiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002100 */
/*0050*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0060*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe40008011604 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.SHL.U32 R6, R13, 0x4, RZ ; /* 0x000000040d067824 */
/* 0x001fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x001fca00078e00ff */
/*00a0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00b0*/ @!P0 BRA 0x390 ; /* 0x000002d000008947 */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R12, R0, c[0x0][0x178], R13 ; /* 0x00005e00000c7a24 */
/* 0x000fe400078e020d */
/*00e0*/ ISETP.GE.AND P0, PT, R13, c[0x0][0x178], PT ; /* 0x00005e000d007a0c */
/* 0x000fe20003f06270 */
/*00f0*/ BSSY B0, 0x220 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd600078e00ff */
/*0110*/ @P0 BRA 0x210 ; /* 0x000000f000000947 */
/* 0x001fea0003800000 */
/*0120*/ IMAD R9, R7, c[0x0][0x178], R13.reuse ; /* 0x00005e0007097a24 */
/* 0x100fe200078e020d */
/*0130*/ MOV R10, R12 ; /* 0x0000000c000a7202 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e000d */
/*0160*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.WIDE R2, R10, R4, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fc800078e0204 */
/*0180*/ IMAD.WIDE R4, R9, R4, c[0x0][0x168] ; /* 0x00005a0009047625 */
/* 0x000fe400078e0204 */
/*0190*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IADD3 R11, R11, c[0x0][0x0], RZ ; /* 0x000000000b0b7a10 */
/* 0x000fe40007ffe0ff */
/*01c0*/ IADD3 R10, R10, c[0x0][0x0], RZ ; /* 0x000000000a0a7a10 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fc40003f06270 */
/*01e0*/ IADD3 R9, R9, c[0x0][0x0], RZ ; /* 0x0000000009097a10 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD R8, R5, R2, R8 ; /* 0x0000000205087224 */
/* 0x004fd400078e0208 */
/*0200*/ @!P0 BRA 0x160 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0230*/ STS [R13.X4], R8 ; /* 0x000000080d007388 */
/* 0x0001e80000004800 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0250*/ @!P0 BRA 0x310 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0260*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x001fc80008000f00 */
/*0270*/ ISETP.GE.U32.AND P0, PT, R13, R3, PT ; /* 0x000000030d00720c */
/* 0x000fda0003f06070 */
/*0280*/ @!P0 IMAD R4, R3, 0x4, R6 ; /* 0x0000000403048824 */
/* 0x000fe200078e0206 */
/*0290*/ @!P0 LDS R2, [R13.X4] ; /* 0x000000000d028984 */
/* 0x000fe20000004800 */
/*02a0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*02b0*/ @!P0 LDS R5, [R4] ; /* 0x0000000004058984 */
/* 0x000e240000000800 */
/*02c0*/ @!P0 IMAD.IADD R2, R2, 0x1, R5 ; /* 0x0000000102028824 */
/* 0x001fca00078e0205 */
/*02d0*/ @!P0 STS [R13.X4], R2 ; /* 0x000000020d008388 */
/* 0x0001e80000004800 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02f0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x001fea000383ffff */
/*0310*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*0320*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0330*/ IMAD R2, R0, c[0x0][0x178], R7 ; /* 0x00005e0000027a24 */
/* 0x000fe200078e0207 */
/*0340*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*0350*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fc80003f06270 */
/*0360*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0370*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0011e8000c101906 */
/*0380*/ @!P0 BRA 0xe0 ; /* 0xfffffd5000008947 */
/* 0x000fea000383ffff */
/*0390*/ IADD3 R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a10 */
/* 0x000fc80007ffe0ff */
/*03a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*03b0*/ @!P0 BRA 0x90 ; /* 0xfffffcd000008947 */
/* 0x000fea000383ffff */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6normalPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R12, SR_CTAID.X ; /* 0x00000000000c7919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R12, c[0x0][0x178], PT ; /* 0x00005e000c007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002100 */
/*0050*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0060*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe40008011604 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.SHL.U32 R0, R13, 0x4, RZ ; /* 0x000000040d007824 */
/* 0x001fe400078e00ff */
/*0090*/ IMAD R6, R12, c[0x0][0x178], R13 ; /* 0x00005e000c067a24 */
/* 0x000fe400078e020d */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x001fca00000001ff */
/*00b0*/ ISETP.GE.AND P0, PT, R13, c[0x0][0x178], PT ; /* 0x00005e000d007a0c */
/* 0x000fe20003f06270 */
/*00c0*/ BSSY B0, 0x200 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*00d0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd600078e00ff */
/*00e0*/ @P0 BRA 0x1f0 ; /* 0x0000010000000947 */
/* 0x001fea0003800000 */
/*00f0*/ IMAD R9, R13, c[0x0][0x178], R7 ; /* 0x00005e000d097a24 */
/* 0x000fe200078e0207 */
/*0100*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*0120*/ MOV R11, R13 ; /* 0x0000000d000b7202 */
/* 0x000fe40000000f00 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.WIDE R2, R10, R4, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fc800078e0204 */
/*0150*/ IMAD.WIDE R4, R9, R4, c[0x0][0x168] ; /* 0x00005a0009047625 */
/* 0x000fe400078e0204 */
/*0160*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IADD3 R11, R11, c[0x0][0x0], RZ ; /* 0x000000000b0b7a10 */
/* 0x000fe40007ffe0ff */
/*0190*/ MOV R14, c[0x0][0x0] ; /* 0x00000000000e7a02 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fc40003f06270 */
/*01b0*/ IADD3 R10, R10, c[0x0][0x0], RZ ; /* 0x000000000a0a7a10 */
/* 0x000fe20007ffe0ff */
/*01c0*/ IMAD R9, R14, c[0x0][0x178], R9 ; /* 0x00005e000e097a24 */
/* 0x000fe400078e0209 */
/*01d0*/ IMAD R8, R5, R2, R8 ; /* 0x0000000205087224 */
/* 0x004fd000078e0208 */
/*01e0*/ @!P0 BRA 0x130 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0210*/ STS [R13.X4], R8 ; /* 0x000000080d007388 */
/* 0x0001e80000004800 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0230*/ @!P0 BRA 0x2f0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0240*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x001fca000f8e00ff */
/*0250*/ ISETP.GE.U32.AND P0, PT, R13, R3, PT ; /* 0x000000030d00720c */
/* 0x000fda0003f06070 */
/*0260*/ @!P0 LEA R4, R3, R0, 0x2 ; /* 0x0000000003048211 */
/* 0x000fe200078e10ff */
/*0270*/ @!P0 LDS R2, [R13.X4] ; /* 0x000000000d028984 */
/* 0x000fe20000004800 */
/*0280*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0290*/ @!P0 LDS R5, [R4] ; /* 0x0000000004058984 */
/* 0x000e240000000800 */
/*02a0*/ @!P0 IMAD.IADD R2, R2, 0x1, R5 ; /* 0x0000000102028824 */
/* 0x001fca00078e0205 */
/*02b0*/ @!P0 STS [R13.X4], R2 ; /* 0x000000020d008388 */
/* 0x0001e80000004800 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02d0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*02e0*/ @P0 BRA 0x250 ; /* 0xffffff6000000947 */
/* 0x001fea000383ffff */
/*02f0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*0300*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0310*/ IMAD R2, R12, c[0x0][0x178], R7 ; /* 0x00005e000c027a24 */
/* 0x000fe200078e0207 */
/*0320*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*0330*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fc80003f06270 */
/*0340*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0350*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0011e8000c101906 */
/*0360*/ @!P0 BRA 0xb0 ; /* 0xfffffd4000008947 */
/* 0x000fea000383ffff */
/*0370*/ BRA 0xa0 ; /* 0xfffffd2000007947 */
/* 0x000fea000383ffff */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
__global__ void normal(int *a, int *b, int *c, int len)
{
int myrow = blockIdx.x;
__shared__ int smem[256];
while(myrow <len)
{
for (int i = 0; i < len; i ++)//which col of right matrix
{
int tid = threadIdx.x;
int res = 0;
while( tid < len ) // vector vector multiplication
{
res += a[myrow*len + tid] * b[tid*len + i];
tid += blockDim.x;
}
smem[threadIdx.x] = res;
__syncthreads();
for (int idx = blockDim.x/2; idx > 0; idx = idx/2)
{
if(threadIdx.x < idx)
{
int temp = smem[threadIdx.x] + smem[threadIdx.x + idx];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
c[myrow*len + i] = smem[0];
}
}
myrow += gridDim.x;
}
__global__ void transpose(int *a, int *b, int *c, int len)
{
int myrow = blockIdx.x;
__shared__ int smem[256];
while(myrow <len)
{
for (int i = 0; i < len; i ++)//which col of right matrix
{
int tid = threadIdx.x;
int res = 0;
while( tid < len ) // vector vector multiplication
{
res += a[myrow*len + tid] * b[i*len + tid];
tid += blockDim.x;
}
smem[threadIdx.x] = res;
__syncthreads();
for (int i = blockDim.x/2; i > 0; i = i/2)
{
if(threadIdx.x < i)
{
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
c[myrow*len + i] = smem[0];
}
myrow += gridDim.x;
}
} | .file "tmpxft_0005685e_00000000-6_mat_mat.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3671:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6normalPiS_S_iPiS_S_i
.type _Z30__device_stub__Z6normalPiS_S_iPiS_S_i, @function
_Z30__device_stub__Z6normalPiS_S_iPiS_S_i:
.LFB3693:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6normalPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3693:
.size _Z30__device_stub__Z6normalPiS_S_iPiS_S_i, .-_Z30__device_stub__Z6normalPiS_S_iPiS_S_i
.globl _Z6normalPiS_S_i
.type _Z6normalPiS_S_i, @function
_Z6normalPiS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6normalPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3694:
.size _Z6normalPiS_S_i, .-_Z6normalPiS_S_i
.globl _Z33__device_stub__Z9transposePiS_S_iPiS_S_i
.type _Z33__device_stub__Z9transposePiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9transposePiS_S_iPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9transposePiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z33__device_stub__Z9transposePiS_S_iPiS_S_i, .-_Z33__device_stub__Z9transposePiS_S_iPiS_S_i
.globl _Z9transposePiS_S_i
.type _Z9transposePiS_S_i, @function
_Z9transposePiS_S_i:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9transposePiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9transposePiS_S_i, .-_Z9transposePiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9transposePiS_S_i"
.LC1:
.string "_Z6normalPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6normalPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
__global__ void normal(int *a, int *b, int *c, int len)
{
int myrow = blockIdx.x;
__shared__ int smem[256];
while(myrow <len)
{
for (int i = 0; i < len; i ++)//which col of right matrix
{
int tid = threadIdx.x;
int res = 0;
while( tid < len ) // vector vector multiplication
{
res += a[myrow*len + tid] * b[tid*len + i];
tid += blockDim.x;
}
smem[threadIdx.x] = res;
__syncthreads();
for (int idx = blockDim.x/2; idx > 0; idx = idx/2)
{
if(threadIdx.x < idx)
{
int temp = smem[threadIdx.x] + smem[threadIdx.x + idx];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
c[myrow*len + i] = smem[0];
}
}
myrow += gridDim.x;
}
__global__ void transpose(int *a, int *b, int *c, int len)
{
int myrow = blockIdx.x;
__shared__ int smem[256];
while(myrow <len)
{
for (int i = 0; i < len; i ++)//which col of right matrix
{
int tid = threadIdx.x;
int res = 0;
while( tid < len ) // vector vector multiplication
{
res += a[myrow*len + tid] * b[i*len + tid];
tid += blockDim.x;
}
smem[threadIdx.x] = res;
__syncthreads();
for (int i = blockDim.x/2; i > 0; i = i/2)
{
if(threadIdx.x < i)
{
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
c[myrow*len + i] = smem[0];
}
myrow += gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void normal(int *a, int *b, int *c, int len)
{
int myrow = blockIdx.x;
__shared__ int smem[256];
while(myrow <len)
{
for (int i = 0; i < len; i ++)//which col of right matrix
{
int tid = threadIdx.x;
int res = 0;
while( tid < len ) // vector vector multiplication
{
res += a[myrow*len + tid] * b[tid*len + i];
tid += blockDim.x;
}
smem[threadIdx.x] = res;
__syncthreads();
for (int idx = blockDim.x/2; idx > 0; idx = idx/2)
{
if(threadIdx.x < idx)
{
int temp = smem[threadIdx.x] + smem[threadIdx.x + idx];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
c[myrow*len + i] = smem[0];
}
}
myrow += gridDim.x;
}
__global__ void transpose(int *a, int *b, int *c, int len)
{
int myrow = blockIdx.x;
__shared__ int smem[256];
while(myrow <len)
{
for (int i = 0; i < len; i ++)//which col of right matrix
{
int tid = threadIdx.x;
int res = 0;
while( tid < len ) // vector vector multiplication
{
res += a[myrow*len + tid] * b[i*len + tid];
tid += blockDim.x;
}
smem[threadIdx.x] = res;
__syncthreads();
for (int i = blockDim.x/2; i > 0; i = i/2)
{
if(threadIdx.x < i)
{
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
c[myrow*len + i] = smem[0];
}
myrow += gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void normal(int *a, int *b, int *c, int len)
{
int myrow = blockIdx.x;
__shared__ int smem[256];
while(myrow <len)
{
for (int i = 0; i < len; i ++)//which col of right matrix
{
int tid = threadIdx.x;
int res = 0;
while( tid < len ) // vector vector multiplication
{
res += a[myrow*len + tid] * b[tid*len + i];
tid += blockDim.x;
}
smem[threadIdx.x] = res;
__syncthreads();
for (int idx = blockDim.x/2; idx > 0; idx = idx/2)
{
if(threadIdx.x < idx)
{
int temp = smem[threadIdx.x] + smem[threadIdx.x + idx];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
c[myrow*len + i] = smem[0];
}
}
myrow += gridDim.x;
}
__global__ void transpose(int *a, int *b, int *c, int len)
{
int myrow = blockIdx.x;
__shared__ int smem[256];
while(myrow <len)
{
for (int i = 0; i < len; i ++)//which col of right matrix
{
int tid = threadIdx.x;
int res = 0;
while( tid < len ) // vector vector multiplication
{
res += a[myrow*len + tid] * b[i*len + tid];
tid += blockDim.x;
}
smem[threadIdx.x] = res;
__syncthreads();
for (int i = blockDim.x/2; i > 0; i = i/2)
{
if(threadIdx.x < i)
{
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
c[myrow*len + i] = smem[0];
}
myrow += gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6normalPiS_S_i
.globl _Z6normalPiS_S_i
.p2align 8
.type _Z6normalPiS_S_i,@function
_Z6normalPiS_S_i:
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cselect_b32 s10, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_14
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_cmp_gt_i32 s3, 0
v_cmp_gt_i32_e64 s2, s3, v0
s_cselect_b32 s11, -1, 0
s_add_u32 s0, s0, 32
v_lshlrev_b32_e32 v4, 2, v0
v_mul_lo_u32 v5, v0, s3
v_mov_b32_e32 v6, 0
s_mul_i32 s15, s15, s3
s_addc_u32 s1, s1, 0
s_branch .LBB0_3
.LBB0_2:
s_and_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_14
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccnz .LBB0_2
s_load_b32 s12, s[0:1], 0xc
v_mov_b32_e32 v7, v5
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s12, 0xffff
s_bfe_u32 s12, s12, 0xf0001
s_cmp_gt_u32 s13, 1
s_cselect_b32 s13, -1, 0
s_branch .LBB0_6
.LBB0_5:
ds_load_b32 v1, v6
s_add_i32 s16, s14, s15
v_add_nc_u32_e32 v7, 1, v7
s_ashr_i32 s17, s16, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[16:17], s[16:17], 2
s_add_u32 s16, s8, s16
s_addc_u32 s17, s9, s17
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s14, s3
s_waitcnt lgkmcnt(0)
global_store_b32 v6, v1, s[16:17]
s_cbranch_scc1 .LBB0_2
.LBB0_6:
v_mov_b32_e32 v1, 0
s_and_saveexec_b32 s16, s2
s_cbranch_execz .LBB0_10
s_load_b32 s17, s[0:1], 0xc
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, v7
v_mov_b32_e32 v8, v0
s_mov_b32 s18, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s17, s17, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s19, s3, s17
.p2align 6
.LBB0_8:
v_add_nc_u32_e32 v9, s15, v8
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[11:12], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v11, vcc_lo, s6, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b32 v3, v[11:12], off
global_load_b32 v11, v[9:10], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[9:10], null, v3, v11, v[1:2]
v_add_nc_u32_e32 v8, s17, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v1, v9 :: v_dual_add_nc_u32 v2, s19, v2
v_cmp_le_i32_e32 vcc_lo, s3, v8
s_or_b32 s18, vcc_lo, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execnz .LBB0_8
s_or_b32 exec_lo, exec_lo, s18
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s16
s_and_not1_b32 vcc_lo, exec_lo, s13
s_mov_b32 s16, s12
ds_store_b32 v4, v1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB0_12
s_branch .LBB0_5
.p2align 6
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s17
s_lshr_b32 s17, s16, 1
s_cmp_lt_u32 s16, 2
s_mov_b32 s16, s17
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_12:
s_mov_b32 s17, exec_lo
v_cmpx_gt_u32_e64 s16, v0
s_cbranch_execz .LBB0_11
v_add_lshl_u32 v1, s16, v0, 2
ds_load_b32 v2, v4
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v1, v2
ds_store_b32 v4, v1
s_branch .LBB0_11
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6normalPiS_S_i
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6normalPiS_S_i, .Lfunc_end0-_Z6normalPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9transposePiS_S_i
.globl _Z9transposePiS_S_i
.p2align 8
.type _Z9transposePiS_S_i,@function
_Z9transposePiS_S_i:
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB1_14
s_clause 0x2
s_load_b32 s10, s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_cmp_gt_i32 s3, 0
v_cmp_gt_i32_e64 s2, s3, v0
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 2, v0
s_cselect_b32 s11, -1, 0
s_add_u32 s0, s0, 32
s_addc_u32 s1, s1, 0
s_mul_i32 s12, s15, s3
s_waitcnt lgkmcnt(0)
s_mul_i32 s13, s10, s3
s_branch .LBB1_3
.LBB1_2:
s_add_i32 s15, s10, s15
s_add_i32 s12, s12, s13
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB1_14
.LBB1_3:
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccnz .LBB1_2
s_load_b32 s14, s[0:1], 0xc
s_mul_i32 s17, s15, s3
s_mov_b32 s18, 0
s_mov_b32 s19, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s16, s14, 0xffff
s_bfe_u32 s14, s14, 0xf0001
s_cmp_gt_u32 s16, 1
s_cselect_b32 s16, -1, 0
s_branch .LBB1_6
.LBB1_5:
ds_load_b32 v1, v3
s_add_i32 s20, s19, s17
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s21, s20, 31
s_lshl_b64 s[20:21], s[20:21], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s20, s8, s20
s_addc_u32 s21, s9, s21
s_add_i32 s19, s19, 1
s_add_i32 s18, s18, s3
s_cmp_eq_u32 s19, s3
s_waitcnt lgkmcnt(0)
global_store_b32 v3, v1, s[20:21]
s_cbranch_scc1 .LBB1_2
.LBB1_6:
v_mov_b32_e32 v1, 0
s_and_saveexec_b32 s20, s2
s_cbranch_execz .LBB1_10
s_load_b32 s21, s[0:1], 0xc
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s22, s21, 0xffff
s_mov_b32 s21, 0
.p2align 6
.LBB1_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, s12, v4
v_add_nc_u32_e32 v7, s18, v4
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v9, v[5:6], off
global_load_b32 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v7, v9, v[1:2]
v_dual_mov_b32 v1, v5 :: v_dual_add_nc_u32 v4, s22, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s3, v4
s_or_b32 s21, vcc_lo, s21
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execnz .LBB1_8
s_or_b32 exec_lo, exec_lo, s21
.LBB1_10:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s20
s_and_not1_b32 vcc_lo, exec_lo, s16
s_mov_b32 s20, s14
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB1_12
s_branch .LBB1_5
.p2align 6
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s21
s_lshr_b32 s21, s20, 1
s_cmp_lt_u32 s20, 2
s_mov_b32 s20, s21
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_5
.LBB1_12:
s_mov_b32 s21, exec_lo
v_cmpx_gt_u32_e64 s20, v0
s_cbranch_execz .LBB1_11
v_add_lshl_u32 v1, s20, v0, 2
ds_load_b32 v4, v2
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v1, v4
ds_store_b32 v2, v1
s_branch .LBB1_11
.LBB1_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePiS_S_i
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9transposePiS_S_i, .Lfunc_end1-_Z9transposePiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6normalPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z6normalPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z9transposePiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void normal(int *a, int *b, int *c, int len)
{
int myrow = blockIdx.x;
__shared__ int smem[256];
while(myrow <len)
{
for (int i = 0; i < len; i ++)//which col of right matrix
{
int tid = threadIdx.x;
int res = 0;
while( tid < len ) // vector vector multiplication
{
res += a[myrow*len + tid] * b[tid*len + i];
tid += blockDim.x;
}
smem[threadIdx.x] = res;
__syncthreads();
for (int idx = blockDim.x/2; idx > 0; idx = idx/2)
{
if(threadIdx.x < idx)
{
int temp = smem[threadIdx.x] + smem[threadIdx.x + idx];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
c[myrow*len + i] = smem[0];
}
}
myrow += gridDim.x;
}
__global__ void transpose(int *a, int *b, int *c, int len)
{
int myrow = blockIdx.x;
__shared__ int smem[256];
while(myrow <len)
{
for (int i = 0; i < len; i ++)//which col of right matrix
{
int tid = threadIdx.x;
int res = 0;
while( tid < len ) // vector vector multiplication
{
res += a[myrow*len + tid] * b[i*len + tid];
tid += blockDim.x;
}
smem[threadIdx.x] = res;
__syncthreads();
for (int i = blockDim.x/2; i > 0; i = i/2)
{
if(threadIdx.x < i)
{
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
c[myrow*len + i] = smem[0];
}
myrow += gridDim.x;
}
} | .text
.file "mat_mat.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__normalPiS_S_i # -- Begin function _Z21__device_stub__normalPiS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__normalPiS_S_i,@function
_Z21__device_stub__normalPiS_S_i: # @_Z21__device_stub__normalPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6normalPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__normalPiS_S_i, .Lfunc_end0-_Z21__device_stub__normalPiS_S_i
.cfi_endproc
# -- End function
.globl _Z24__device_stub__transposePiS_S_i # -- Begin function _Z24__device_stub__transposePiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__transposePiS_S_i,@function
_Z24__device_stub__transposePiS_S_i: # @_Z24__device_stub__transposePiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9transposePiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__transposePiS_S_i, .Lfunc_end1-_Z24__device_stub__transposePiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6normalPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePiS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6normalPiS_S_i,@object # @_Z6normalPiS_S_i
.section .rodata,"a",@progbits
.globl _Z6normalPiS_S_i
.p2align 3, 0x0
_Z6normalPiS_S_i:
.quad _Z21__device_stub__normalPiS_S_i
.size _Z6normalPiS_S_i, 8
.type _Z9transposePiS_S_i,@object # @_Z9transposePiS_S_i
.globl _Z9transposePiS_S_i
.p2align 3, 0x0
_Z9transposePiS_S_i:
.quad _Z24__device_stub__transposePiS_S_i
.size _Z9transposePiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6normalPiS_S_i"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9transposePiS_S_i"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__normalPiS_S_i
.addrsig_sym _Z24__device_stub__transposePiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6normalPiS_S_i
.addrsig_sym _Z9transposePiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9transposePiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002100 */
/*0050*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0060*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe40008011604 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.SHL.U32 R6, R13, 0x4, RZ ; /* 0x000000040d067824 */
/* 0x001fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x001fca00078e00ff */
/*00a0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00b0*/ @!P0 BRA 0x390 ; /* 0x000002d000008947 */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R12, R0, c[0x0][0x178], R13 ; /* 0x00005e00000c7a24 */
/* 0x000fe400078e020d */
/*00e0*/ ISETP.GE.AND P0, PT, R13, c[0x0][0x178], PT ; /* 0x00005e000d007a0c */
/* 0x000fe20003f06270 */
/*00f0*/ BSSY B0, 0x220 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd600078e00ff */
/*0110*/ @P0 BRA 0x210 ; /* 0x000000f000000947 */
/* 0x001fea0003800000 */
/*0120*/ IMAD R9, R7, c[0x0][0x178], R13.reuse ; /* 0x00005e0007097a24 */
/* 0x100fe200078e020d */
/*0130*/ MOV R10, R12 ; /* 0x0000000c000a7202 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e000d */
/*0160*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.WIDE R2, R10, R4, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fc800078e0204 */
/*0180*/ IMAD.WIDE R4, R9, R4, c[0x0][0x168] ; /* 0x00005a0009047625 */
/* 0x000fe400078e0204 */
/*0190*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IADD3 R11, R11, c[0x0][0x0], RZ ; /* 0x000000000b0b7a10 */
/* 0x000fe40007ffe0ff */
/*01c0*/ IADD3 R10, R10, c[0x0][0x0], RZ ; /* 0x000000000a0a7a10 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fc40003f06270 */
/*01e0*/ IADD3 R9, R9, c[0x0][0x0], RZ ; /* 0x0000000009097a10 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD R8, R5, R2, R8 ; /* 0x0000000205087224 */
/* 0x004fd400078e0208 */
/*0200*/ @!P0 BRA 0x160 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0230*/ STS [R13.X4], R8 ; /* 0x000000080d007388 */
/* 0x0001e80000004800 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0250*/ @!P0 BRA 0x310 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0260*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x001fc80008000f00 */
/*0270*/ ISETP.GE.U32.AND P0, PT, R13, R3, PT ; /* 0x000000030d00720c */
/* 0x000fda0003f06070 */
/*0280*/ @!P0 IMAD R4, R3, 0x4, R6 ; /* 0x0000000403048824 */
/* 0x000fe200078e0206 */
/*0290*/ @!P0 LDS R2, [R13.X4] ; /* 0x000000000d028984 */
/* 0x000fe20000004800 */
/*02a0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*02b0*/ @!P0 LDS R5, [R4] ; /* 0x0000000004058984 */
/* 0x000e240000000800 */
/*02c0*/ @!P0 IMAD.IADD R2, R2, 0x1, R5 ; /* 0x0000000102028824 */
/* 0x001fca00078e0205 */
/*02d0*/ @!P0 STS [R13.X4], R2 ; /* 0x000000020d008388 */
/* 0x0001e80000004800 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02f0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x001fea000383ffff */
/*0310*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*0320*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0330*/ IMAD R2, R0, c[0x0][0x178], R7 ; /* 0x00005e0000027a24 */
/* 0x000fe200078e0207 */
/*0340*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*0350*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fc80003f06270 */
/*0360*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0370*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0011e8000c101906 */
/*0380*/ @!P0 BRA 0xe0 ; /* 0xfffffd5000008947 */
/* 0x000fea000383ffff */
/*0390*/ IADD3 R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a10 */
/* 0x000fc80007ffe0ff */
/*03a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*03b0*/ @!P0 BRA 0x90 ; /* 0xfffffcd000008947 */
/* 0x000fea000383ffff */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6normalPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R12, SR_CTAID.X ; /* 0x00000000000c7919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R12, c[0x0][0x178], PT ; /* 0x00005e000c007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002100 */
/*0050*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0060*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe40008011604 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.SHL.U32 R0, R13, 0x4, RZ ; /* 0x000000040d007824 */
/* 0x001fe400078e00ff */
/*0090*/ IMAD R6, R12, c[0x0][0x178], R13 ; /* 0x00005e000c067a24 */
/* 0x000fe400078e020d */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x001fca00000001ff */
/*00b0*/ ISETP.GE.AND P0, PT, R13, c[0x0][0x178], PT ; /* 0x00005e000d007a0c */
/* 0x000fe20003f06270 */
/*00c0*/ BSSY B0, 0x200 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*00d0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd600078e00ff */
/*00e0*/ @P0 BRA 0x1f0 ; /* 0x0000010000000947 */
/* 0x001fea0003800000 */
/*00f0*/ IMAD R9, R13, c[0x0][0x178], R7 ; /* 0x00005e000d097a24 */
/* 0x000fe200078e0207 */
/*0100*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*0120*/ MOV R11, R13 ; /* 0x0000000d000b7202 */
/* 0x000fe40000000f00 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.WIDE R2, R10, R4, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fc800078e0204 */
/*0150*/ IMAD.WIDE R4, R9, R4, c[0x0][0x168] ; /* 0x00005a0009047625 */
/* 0x000fe400078e0204 */
/*0160*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IADD3 R11, R11, c[0x0][0x0], RZ ; /* 0x000000000b0b7a10 */
/* 0x000fe40007ffe0ff */
/*0190*/ MOV R14, c[0x0][0x0] ; /* 0x00000000000e7a02 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fc40003f06270 */
/*01b0*/ IADD3 R10, R10, c[0x0][0x0], RZ ; /* 0x000000000a0a7a10 */
/* 0x000fe20007ffe0ff */
/*01c0*/ IMAD R9, R14, c[0x0][0x178], R9 ; /* 0x00005e000e097a24 */
/* 0x000fe400078e0209 */
/*01d0*/ IMAD R8, R5, R2, R8 ; /* 0x0000000205087224 */
/* 0x004fd000078e0208 */
/*01e0*/ @!P0 BRA 0x130 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0210*/ STS [R13.X4], R8 ; /* 0x000000080d007388 */
/* 0x0001e80000004800 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0230*/ @!P0 BRA 0x2f0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0240*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x001fca000f8e00ff */
/*0250*/ ISETP.GE.U32.AND P0, PT, R13, R3, PT ; /* 0x000000030d00720c */
/* 0x000fda0003f06070 */
/*0260*/ @!P0 LEA R4, R3, R0, 0x2 ; /* 0x0000000003048211 */
/* 0x000fe200078e10ff */
/*0270*/ @!P0 LDS R2, [R13.X4] ; /* 0x000000000d028984 */
/* 0x000fe20000004800 */
/*0280*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0290*/ @!P0 LDS R5, [R4] ; /* 0x0000000004058984 */
/* 0x000e240000000800 */
/*02a0*/ @!P0 IMAD.IADD R2, R2, 0x1, R5 ; /* 0x0000000102028824 */
/* 0x001fca00078e0205 */
/*02b0*/ @!P0 STS [R13.X4], R2 ; /* 0x000000020d008388 */
/* 0x0001e80000004800 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02d0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*02e0*/ @P0 BRA 0x250 ; /* 0xffffff6000000947 */
/* 0x001fea000383ffff */
/*02f0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*0300*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0310*/ IMAD R2, R12, c[0x0][0x178], R7 ; /* 0x00005e000c027a24 */
/* 0x000fe200078e0207 */
/*0320*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*0330*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fc80003f06270 */
/*0340*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0350*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0011e8000c101906 */
/*0360*/ @!P0 BRA 0xb0 ; /* 0xfffffd4000008947 */
/* 0x000fea000383ffff */
/*0370*/ BRA 0xa0 ; /* 0xfffffd2000007947 */
/* 0x000fea000383ffff */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6normalPiS_S_i
.globl _Z6normalPiS_S_i
.p2align 8
.type _Z6normalPiS_S_i,@function
_Z6normalPiS_S_i:
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cselect_b32 s10, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_14
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_cmp_gt_i32 s3, 0
v_cmp_gt_i32_e64 s2, s3, v0
s_cselect_b32 s11, -1, 0
s_add_u32 s0, s0, 32
v_lshlrev_b32_e32 v4, 2, v0
v_mul_lo_u32 v5, v0, s3
v_mov_b32_e32 v6, 0
s_mul_i32 s15, s15, s3
s_addc_u32 s1, s1, 0
s_branch .LBB0_3
.LBB0_2:
s_and_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_14
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccnz .LBB0_2
s_load_b32 s12, s[0:1], 0xc
v_mov_b32_e32 v7, v5
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s12, 0xffff
s_bfe_u32 s12, s12, 0xf0001
s_cmp_gt_u32 s13, 1
s_cselect_b32 s13, -1, 0
s_branch .LBB0_6
.LBB0_5:
ds_load_b32 v1, v6
s_add_i32 s16, s14, s15
v_add_nc_u32_e32 v7, 1, v7
s_ashr_i32 s17, s16, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[16:17], s[16:17], 2
s_add_u32 s16, s8, s16
s_addc_u32 s17, s9, s17
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s14, s3
s_waitcnt lgkmcnt(0)
global_store_b32 v6, v1, s[16:17]
s_cbranch_scc1 .LBB0_2
.LBB0_6:
v_mov_b32_e32 v1, 0
s_and_saveexec_b32 s16, s2
s_cbranch_execz .LBB0_10
s_load_b32 s17, s[0:1], 0xc
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, v7
v_mov_b32_e32 v8, v0
s_mov_b32 s18, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s17, s17, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s19, s3, s17
.p2align 6
.LBB0_8:
v_add_nc_u32_e32 v9, s15, v8
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[11:12], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v11, vcc_lo, s6, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b32 v3, v[11:12], off
global_load_b32 v11, v[9:10], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[9:10], null, v3, v11, v[1:2]
v_add_nc_u32_e32 v8, s17, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v1, v9 :: v_dual_add_nc_u32 v2, s19, v2
v_cmp_le_i32_e32 vcc_lo, s3, v8
s_or_b32 s18, vcc_lo, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execnz .LBB0_8
s_or_b32 exec_lo, exec_lo, s18
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s16
s_and_not1_b32 vcc_lo, exec_lo, s13
s_mov_b32 s16, s12
ds_store_b32 v4, v1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB0_12
s_branch .LBB0_5
.p2align 6
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s17
s_lshr_b32 s17, s16, 1
s_cmp_lt_u32 s16, 2
s_mov_b32 s16, s17
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_12:
s_mov_b32 s17, exec_lo
v_cmpx_gt_u32_e64 s16, v0
s_cbranch_execz .LBB0_11
v_add_lshl_u32 v1, s16, v0, 2
ds_load_b32 v2, v4
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v1, v2
ds_store_b32 v4, v1
s_branch .LBB0_11
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6normalPiS_S_i
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6normalPiS_S_i, .Lfunc_end0-_Z6normalPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9transposePiS_S_i
.globl _Z9transposePiS_S_i
.p2align 8
.type _Z9transposePiS_S_i,@function
_Z9transposePiS_S_i:
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB1_14
s_clause 0x2
s_load_b32 s10, s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_cmp_gt_i32 s3, 0
v_cmp_gt_i32_e64 s2, s3, v0
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 2, v0
s_cselect_b32 s11, -1, 0
s_add_u32 s0, s0, 32
s_addc_u32 s1, s1, 0
s_mul_i32 s12, s15, s3
s_waitcnt lgkmcnt(0)
s_mul_i32 s13, s10, s3
s_branch .LBB1_3
.LBB1_2:
s_add_i32 s15, s10, s15
s_add_i32 s12, s12, s13
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB1_14
.LBB1_3:
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccnz .LBB1_2
s_load_b32 s14, s[0:1], 0xc
s_mul_i32 s17, s15, s3
s_mov_b32 s18, 0
s_mov_b32 s19, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s16, s14, 0xffff
s_bfe_u32 s14, s14, 0xf0001
s_cmp_gt_u32 s16, 1
s_cselect_b32 s16, -1, 0
s_branch .LBB1_6
.LBB1_5:
ds_load_b32 v1, v3
s_add_i32 s20, s19, s17
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s21, s20, 31
s_lshl_b64 s[20:21], s[20:21], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s20, s8, s20
s_addc_u32 s21, s9, s21
s_add_i32 s19, s19, 1
s_add_i32 s18, s18, s3
s_cmp_eq_u32 s19, s3
s_waitcnt lgkmcnt(0)
global_store_b32 v3, v1, s[20:21]
s_cbranch_scc1 .LBB1_2
.LBB1_6:
v_mov_b32_e32 v1, 0
s_and_saveexec_b32 s20, s2
s_cbranch_execz .LBB1_10
s_load_b32 s21, s[0:1], 0xc
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s22, s21, 0xffff
s_mov_b32 s21, 0
.p2align 6
.LBB1_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, s12, v4
v_add_nc_u32_e32 v7, s18, v4
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v9, v[5:6], off
global_load_b32 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v7, v9, v[1:2]
v_dual_mov_b32 v1, v5 :: v_dual_add_nc_u32 v4, s22, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s3, v4
s_or_b32 s21, vcc_lo, s21
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execnz .LBB1_8
s_or_b32 exec_lo, exec_lo, s21
.LBB1_10:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s20
s_and_not1_b32 vcc_lo, exec_lo, s16
s_mov_b32 s20, s14
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB1_12
s_branch .LBB1_5
.p2align 6
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s21
s_lshr_b32 s21, s20, 1
s_cmp_lt_u32 s20, 2
s_mov_b32 s20, s21
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_5
.LBB1_12:
s_mov_b32 s21, exec_lo
v_cmpx_gt_u32_e64 s20, v0
s_cbranch_execz .LBB1_11
v_add_lshl_u32 v1, s20, v0, 2
ds_load_b32 v4, v2
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v1, v4
ds_store_b32 v2, v1
s_branch .LBB1_11
.LBB1_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePiS_S_i
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9transposePiS_S_i, .Lfunc_end1-_Z9transposePiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6normalPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z6normalPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z9transposePiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005685e_00000000-6_mat_mat.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3671:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6normalPiS_S_iPiS_S_i
.type _Z30__device_stub__Z6normalPiS_S_iPiS_S_i, @function
_Z30__device_stub__Z6normalPiS_S_iPiS_S_i:
.LFB3693:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6normalPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3693:
.size _Z30__device_stub__Z6normalPiS_S_iPiS_S_i, .-_Z30__device_stub__Z6normalPiS_S_iPiS_S_i
.globl _Z6normalPiS_S_i
.type _Z6normalPiS_S_i, @function
_Z6normalPiS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6normalPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3694:
.size _Z6normalPiS_S_i, .-_Z6normalPiS_S_i
.globl _Z33__device_stub__Z9transposePiS_S_iPiS_S_i
.type _Z33__device_stub__Z9transposePiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9transposePiS_S_iPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9transposePiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z33__device_stub__Z9transposePiS_S_iPiS_S_i, .-_Z33__device_stub__Z9transposePiS_S_iPiS_S_i
.globl _Z9transposePiS_S_i
.type _Z9transposePiS_S_i, @function
_Z9transposePiS_S_i:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9transposePiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9transposePiS_S_i, .-_Z9transposePiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9transposePiS_S_i"
.LC1:
.string "_Z6normalPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6normalPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mat_mat.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__normalPiS_S_i # -- Begin function _Z21__device_stub__normalPiS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__normalPiS_S_i,@function
_Z21__device_stub__normalPiS_S_i: # @_Z21__device_stub__normalPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6normalPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__normalPiS_S_i, .Lfunc_end0-_Z21__device_stub__normalPiS_S_i
.cfi_endproc
# -- End function
.globl _Z24__device_stub__transposePiS_S_i # -- Begin function _Z24__device_stub__transposePiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__transposePiS_S_i,@function
_Z24__device_stub__transposePiS_S_i: # @_Z24__device_stub__transposePiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9transposePiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__transposePiS_S_i, .Lfunc_end1-_Z24__device_stub__transposePiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6normalPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePiS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6normalPiS_S_i,@object # @_Z6normalPiS_S_i
.section .rodata,"a",@progbits
.globl _Z6normalPiS_S_i
.p2align 3, 0x0
_Z6normalPiS_S_i:
.quad _Z21__device_stub__normalPiS_S_i
.size _Z6normalPiS_S_i, 8
.type _Z9transposePiS_S_i,@object # @_Z9transposePiS_S_i
.globl _Z9transposePiS_S_i
.p2align 3, 0x0
_Z9transposePiS_S_i:
.quad _Z24__device_stub__transposePiS_S_i
.size _Z9transposePiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6normalPiS_S_i"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9transposePiS_S_i"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__normalPiS_S_i
.addrsig_sym _Z24__device_stub__transposePiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6normalPiS_S_i
.addrsig_sym _Z9transposePiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define NTHREADS 512
// Updates the column norms by subtracting the Hadamard-square of the
// Householder vector.
//
// N.B.: Overflow incurred in computing the square should already have
// been detected in the original norm construction.
__global__ void getColNorms(int rows, int cols, float * da, int lda, float * colNorms)
{
int colIndex = threadIdx.x + blockIdx.x * blockDim.x;
float
sum = 0.f, term,
* col;
if(colIndex >= cols)
return;
col = da + colIndex * lda;
// debug printing
// printf("printing column %d\n", colIndex);
// for(int i = 0; i < rows; i++)
// printf("%f, ", col[i]);
// puts("");
// end debug printing
for(int i = 0; i < rows; i++) {
term = col[i];
term *= term;
sum += term;
}
// debug printing
// printf("norm %f\n", norm);
// end debug printing
colNorms[colIndex] = sum;
} | code for sm_80
Function : _Z11getColNormsiiPfiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x164], PT ; /* 0x0000590004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fc600000001ff */
/*0090*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0x800 ; /* 0x0000075000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ IMAD R7, R4, c[0x0][0x170], RZ ; /* 0x00005c0004077a24 */
/* 0x000fe200078e02ff */
/*00d0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fe40000000f00 */
/*0110*/ SHF.R.S32.HI R8, RZ, 0x1f, R7 ; /* 0x0000001fff087819 */
/* 0x000fd20000011407 */
/*0120*/ @!P0 BRA 0x710 ; /* 0x000005e000008947 */
/* 0x000fea0003800000 */
/*0130*/ LEA R2, P0, R7.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0007027a11 */
/* 0x040fe200078010ff */
/*0140*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0150*/ IADD3 R9, -R0, c[0x0][0x160], RZ ; /* 0x0000580000097a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0170*/ LEA.HI.X R3, R7, c[0x0][0x16c], R8, 0x2, P0 ; /* 0x00005b0007037a11 */
/* 0x000fe400000f1408 */
/*0180*/ ISETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f04270 */
/*0190*/ IADD3 R2, P1, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fca0007f3e0ff */
/*01a0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fcc00008e0603 */
/*01b0*/ @!P0 BRA 0x610 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*01c0*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01e0*/ @!P1 BRA 0x460 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0200*/ LDG.E R22, [R2.64+-0x8] ; /* 0xfffff80402167981 */
/* 0x0000a8000c1e1900 */
/*0210*/ LDG.E R24, [R2.64+-0x4] ; /* 0xfffffc0402187981 */
/* 0x0000e8000c1e1900 */
/*0220*/ LDG.E R26, [R2.64] ; /* 0x00000004021a7981 */
/* 0x000128000c1e1900 */
/*0230*/ LDG.E R28, [R2.64+0x4] ; /* 0x00000404021c7981 */
/* 0x000168000c1e1900 */
/*0240*/ LDG.E R21, [R2.64+0x8] ; /* 0x0000080402157981 */
/* 0x000168000c1e1900 */
/*0250*/ LDG.E R20, [R2.64+0xc] ; /* 0x00000c0402147981 */
/* 0x000168000c1e1900 */
/*0260*/ LDG.E R19, [R2.64+0x10] ; /* 0x0000100402137981 */
/* 0x000168000c1e1900 */
/*0270*/ LDG.E R18, [R2.64+0x14] ; /* 0x0000140402127981 */
/* 0x000168000c1e1900 */
/*0280*/ LDG.E R17, [R2.64+0x18] ; /* 0x0000180402117981 */
/* 0x000168000c1e1900 */
/*0290*/ LDG.E R16, [R2.64+0x1c] ; /* 0x00001c0402107981 */
/* 0x000168000c1e1900 */
/*02a0*/ LDG.E R15, [R2.64+0x20] ; /* 0x00002004020f7981 */
/* 0x000168000c1e1900 */
/*02b0*/ LDG.E R14, [R2.64+0x24] ; /* 0x00002404020e7981 */
/* 0x000168000c1e1900 */
/*02c0*/ LDG.E R13, [R2.64+0x28] ; /* 0x00002804020d7981 */
/* 0x000168000c1e1900 */
/*02d0*/ LDG.E R12, [R2.64+0x2c] ; /* 0x00002c04020c7981 */
/* 0x000168000c1e1900 */
/*02e0*/ LDG.E R10, [R2.64+0x30] ; /* 0x00003004020a7981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R11, [R2.64+0x34] ; /* 0x00003404020b7981 */
/* 0x000162000c1e1900 */
/*0300*/ IADD3 R9, R9, -0x10, RZ ; /* 0xfffffff009097810 */
/* 0x000fc40007ffe0ff */
/*0310*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*0320*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*0330*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fc80007f5e0ff */
/*0340*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe200017fe4ff */
/*0350*/ FFMA R5, R22, R22, R5 ; /* 0x0000001616057223 */
/* 0x004fc80000000005 */
/*0360*/ FFMA R5, R24, R24, R5 ; /* 0x0000001818057223 */
/* 0x008fc80000000005 */
/*0370*/ FFMA R5, R26, R26, R5 ; /* 0x0000001a1a057223 */
/* 0x010fc80000000005 */
/*0380*/ FFMA R5, R28, R28, R5 ; /* 0x0000001c1c057223 */
/* 0x020fc80000000005 */
/*0390*/ FFMA R5, R21, R21, R5 ; /* 0x0000001515057223 */
/* 0x000fc80000000005 */
/*03a0*/ FFMA R20, R20, R20, R5 ; /* 0x0000001414147223 */
/* 0x000fc80000000005 */
/*03b0*/ FFMA R19, R19, R19, R20 ; /* 0x0000001313137223 */
/* 0x000fc80000000014 */
/*03c0*/ FFMA R18, R18, R18, R19 ; /* 0x0000001212127223 */
/* 0x000fc80000000013 */
/*03d0*/ FFMA R17, R17, R17, R18 ; /* 0x0000001111117223 */
/* 0x000fc80000000012 */
/*03e0*/ FFMA R16, R16, R16, R17 ; /* 0x0000001010107223 */
/* 0x000fc80000000011 */
/*03f0*/ FFMA R15, R15, R15, R16 ; /* 0x0000000f0f0f7223 */
/* 0x000fc80000000010 */
/*0400*/ FFMA R14, R14, R14, R15 ; /* 0x0000000e0e0e7223 */
/* 0x000fc8000000000f */
/*0410*/ FFMA R13, R13, R13, R14 ; /* 0x0000000d0d0d7223 */
/* 0x000fc8000000000e */
/*0420*/ FFMA R13, R12, R12, R13 ; /* 0x0000000c0c0d7223 */
/* 0x000fc8000000000d */
/*0430*/ FFMA R10, R10, R10, R13 ; /* 0x0000000a0a0a7223 */
/* 0x000fc8000000000d */
/*0440*/ FFMA R5, R11, R11, R10 ; /* 0x0000000b0b057223 */
/* 0x000fe2000000000a */
/*0450*/ @P1 BRA 0x200 ; /* 0xfffffda000001947 */
/* 0x000fea000383ffff */
/*0460*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f24270 */
/*0470*/ @!P1 BRA 0x5f0 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0480*/ LDG.E R10, [R2.64+-0x8] ; /* 0xfffff804020a7981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R12, [R2.64+-0x4] ; /* 0xfffffc04020c7981 */
/* 0x000ee8000c1e1900 */
/*04a0*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000128000c1e1900 */
/*04b0*/ LDG.E R16, [R2.64+0x4] ; /* 0x0000040402107981 */
/* 0x000168000c1e1900 */
/*04c0*/ LDG.E R18, [R2.64+0x8] ; /* 0x0000080402127981 */
/* 0x000168000c1e1900 */
/*04d0*/ LDG.E R20, [R2.64+0xc] ; /* 0x00000c0402147981 */
/* 0x000168000c1e1900 */
/*04e0*/ LDG.E R22, [R2.64+0x10] ; /* 0x0000100402167981 */
/* 0x000168000c1e1900 */
/*04f0*/ LDG.E R24, [R2.64+0x14] ; /* 0x0000140402187981 */
/* 0x000162000c1e1900 */
/*0500*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0510*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*0520*/ IADD3 R9, R9, -0x8, RZ ; /* 0xfffffff809097810 */
/* 0x000fe20007ffe0ff */
/*0530*/ FFMA R5, R10, R10, R5 ; /* 0x0000000a0a057223 */
/* 0x004fe20000000005 */
/*0540*/ IADD3 R10, P1, R2, 0x20, RZ ; /* 0x00000020020a7810 */
/* 0x000fc60007f3e0ff */
/*0550*/ FFMA R5, R12, R12, R5 ; /* 0x0000000c0c057223 */
/* 0x008fe20000000005 */
/*0560*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x001fe20000000f00 */
/*0570*/ IMAD.X R11, RZ, RZ, R3, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe400008e0603 */
/*0580*/ FFMA R5, R14, R14, R5 ; /* 0x0000000e0e057223 */
/* 0x010fe40000000005 */
/*0590*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*05a0*/ FFMA R5, R16, R16, R5 ; /* 0x0000001010057223 */
/* 0x020fc80000000005 */
/*05b0*/ FFMA R5, R18, R18, R5 ; /* 0x0000001212057223 */
/* 0x000fc80000000005 */
/*05c0*/ FFMA R5, R20, R20, R5 ; /* 0x0000001414057223 */
/* 0x000fc80000000005 */
/*05d0*/ FFMA R5, R22, R22, R5 ; /* 0x0000001616057223 */
/* 0x000fc80000000005 */
/*05e0*/ FFMA R5, R24, R24, R5 ; /* 0x0000001818057223 */
/* 0x000fe40000000005 */
/*05f0*/ ISETP.NE.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000705670 */
/*0600*/ @!P0 BRA 0x710 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0610*/ LDG.E R10, [R2.64+-0x8] ; /* 0xfffff804020a7981 */
/* 0x000ea8000c1e1900 */
/*0620*/ LDG.E R12, [R2.64+-0x4] ; /* 0xfffffc04020c7981 */
/* 0x000ee8000c1e1900 */
/*0630*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000128000c1e1900 */
/*0640*/ LDG.E R16, [R2.64+0x4] ; /* 0x0000040402107981 */
/* 0x000162000c1e1900 */
/*0650*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */
/* 0x000fc40007ffe0ff */
/*0660*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007ffe0ff */
/*0670*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*0680*/ FFMA R5, R10, R10, R5 ; /* 0x0000000a0a057223 */
/* 0x004fe20000000005 */
/*0690*/ IADD3 R10, P1, R2, 0x10, RZ ; /* 0x00000010020a7810 */
/* 0x000fc60007f3e0ff */
/*06a0*/ FFMA R5, R12, R12, R5 ; /* 0x0000000c0c057223 */
/* 0x008fe20000000005 */
/*06b0*/ IADD3.X R11, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0b7210 */
/* 0x000fe20000ffe4ff */
/*06c0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x001fe400078e000a */
/*06d0*/ FFMA R5, R14, R14, R5 ; /* 0x0000000e0e057223 */
/* 0x010fe20000000005 */
/*06e0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*06f0*/ FFMA R5, R16, R16, R5 ; /* 0x0000001010057223 */
/* 0x020fe20000000005 */
/*0700*/ @P0 BRA 0x610 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0710*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0720*/ @!P0 BRA 0x800 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0730*/ IADD3 R2, P0, R7, R6, RZ ; /* 0x0000000607027210 */
/* 0x000fc80007f1e0ff */
/*0740*/ LEA R7, P1, R2, c[0x0][0x168], 0x2 ; /* 0x00005a0002077a11 */
/* 0x000fe400078210ff */
/*0750*/ LEA.HI.X.SX32 R3, R6, R8, 0x1, P0 ; /* 0x0000000806037211 */
/* 0x000fc800000f0eff */
/*0760*/ LEA.HI.X R6, R2, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0002067a11 */
/* 0x000fc600008f1403 */
/*0770*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0007 */
/*0780*/ MOV R3, R6 ; /* 0x0000000600037202 */
/* 0x000fca0000000f00 */
/*0790*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*07a0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ IADD3 R7, P1, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007f3e0ff */
/*07c0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*07d0*/ IMAD.X R6, RZ, RZ, R6, P1 ; /* 0x000000ffff067224 */
/* 0x000fe400008e0606 */
/*07e0*/ FFMA R5, R2, R2, R5 ; /* 0x0000000202057223 */
/* 0x004fd00000000005 */
/*07f0*/ @P0 BRA 0x770 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0800*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0810*/ IMAD.WIDE R2, R4, R3, c[0x0][0x178] ; /* 0x00005e0004027625 */
/* 0x000fca00078e0203 */
/*0820*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0830*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0840*/ BRA 0x840; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define NTHREADS 512
// Updates the column norms by subtracting the Hadamard-square of the
// Householder vector.
//
// N.B.: Overflow incurred in computing the square should already have
// been detected in the original norm construction.
__global__ void getColNorms(int rows, int cols, float * da, int lda, float * colNorms)
{
int colIndex = threadIdx.x + blockIdx.x * blockDim.x;
float
sum = 0.f, term,
* col;
if(colIndex >= cols)
return;
col = da + colIndex * lda;
// debug printing
// printf("printing column %d\n", colIndex);
// for(int i = 0; i < rows; i++)
// printf("%f, ", col[i]);
// puts("");
// end debug printing
for(int i = 0; i < rows; i++) {
term = col[i];
term *= term;
sum += term;
}
// debug printing
// printf("norm %f\n", norm);
// end debug printing
colNorms[colIndex] = sum;
} | .file "tmpxft_0002dc36_00000000-6_getColNorms.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11getColNormsiiPfiS_iiPfiS_
.type _Z36__device_stub__Z11getColNormsiiPfiS_iiPfiS_, @function
_Z36__device_stub__Z11getColNormsiiPfiS_iiPfiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11getColNormsiiPfiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11getColNormsiiPfiS_iiPfiS_, .-_Z36__device_stub__Z11getColNormsiiPfiS_iiPfiS_
.globl _Z11getColNormsiiPfiS_
.type _Z11getColNormsiiPfiS_, @function
_Z11getColNormsiiPfiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11getColNormsiiPfiS_iiPfiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11getColNormsiiPfiS_, .-_Z11getColNormsiiPfiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11getColNormsiiPfiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11getColNormsiiPfiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define NTHREADS 512
// Updates the column norms by subtracting the Hadamard-square of the
// Householder vector.
//
// N.B.: Overflow incurred in computing the square should already have
// been detected in the original norm construction.
__global__ void getColNorms(int rows, int cols, float * da, int lda, float * colNorms)
{
int colIndex = threadIdx.x + blockIdx.x * blockDim.x;
float
sum = 0.f, term,
* col;
if(colIndex >= cols)
return;
col = da + colIndex * lda;
// debug printing
// printf("printing column %d\n", colIndex);
// for(int i = 0; i < rows; i++)
// printf("%f, ", col[i]);
// puts("");
// end debug printing
for(int i = 0; i < rows; i++) {
term = col[i];
term *= term;
sum += term;
}
// debug printing
// printf("norm %f\n", norm);
// end debug printing
colNorms[colIndex] = sum;
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define NTHREADS 512
// Updates the column norms by subtracting the Hadamard-square of the
// Householder vector.
//
// N.B.: Overflow incurred in computing the square should already have
// been detected in the original norm construction.
__global__ void getColNorms(int rows, int cols, float * da, int lda, float * colNorms)
{
int colIndex = threadIdx.x + blockIdx.x * blockDim.x;
float
sum = 0.f, term,
* col;
if(colIndex >= cols)
return;
col = da + colIndex * lda;
// debug printing
// printf("printing column %d\n", colIndex);
// for(int i = 0; i < rows; i++)
// printf("%f, ", col[i]);
// puts("");
// end debug printing
for(int i = 0; i < rows; i++) {
term = col[i];
term *= term;
sum += term;
}
// debug printing
// printf("norm %f\n", norm);
// end debug printing
colNorms[colIndex] = sum;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define NTHREADS 512
// Updates the column norms by subtracting the Hadamard-square of the
// Householder vector.
//
// N.B.: Overflow incurred in computing the square should already have
// been detected in the original norm construction.
__global__ void getColNorms(int rows, int cols, float * da, int lda, float * colNorms)
{
int colIndex = threadIdx.x + blockIdx.x * blockDim.x;
float
sum = 0.f, term,
* col;
if(colIndex >= cols)
return;
col = da + colIndex * lda;
// debug printing
// printf("printing column %d\n", colIndex);
// for(int i = 0; i < rows; i++)
// printf("%f, ", col[i]);
// puts("");
// end debug printing
for(int i = 0; i < rows; i++) {
term = col[i];
term *= term;
sum += term;
}
// debug printing
// printf("norm %f\n", norm);
// end debug printing
colNorms[colIndex] = sum;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11getColNormsiiPfiS_
.globl _Z11getColNormsiiPfiS_
.p2align 8
.type _Z11getColNormsiiPfiS_,@function
_Z11getColNormsiiPfiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_3:
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v4, v4
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11getColNormsiiPfiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11getColNormsiiPfiS_, .Lfunc_end0-_Z11getColNormsiiPfiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11getColNormsiiPfiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11getColNormsiiPfiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define NTHREADS 512
// Updates the column norms by subtracting the Hadamard-square of the
// Householder vector.
//
// N.B.: Overflow incurred in computing the square should already have
// been detected in the original norm construction.
__global__ void getColNorms(int rows, int cols, float * da, int lda, float * colNorms)
{
int colIndex = threadIdx.x + blockIdx.x * blockDim.x;
float
sum = 0.f, term,
* col;
if(colIndex >= cols)
return;
col = da + colIndex * lda;
// debug printing
// printf("printing column %d\n", colIndex);
// for(int i = 0; i < rows; i++)
// printf("%f, ", col[i]);
// puts("");
// end debug printing
for(int i = 0; i < rows; i++) {
term = col[i];
term *= term;
sum += term;
}
// debug printing
// printf("norm %f\n", norm);
// end debug printing
colNorms[colIndex] = sum;
} | .text
.file "getColNorms.hip"
.globl _Z26__device_stub__getColNormsiiPfiS_ # -- Begin function _Z26__device_stub__getColNormsiiPfiS_
.p2align 4, 0x90
.type _Z26__device_stub__getColNormsiiPfiS_,@function
_Z26__device_stub__getColNormsiiPfiS_: # @_Z26__device_stub__getColNormsiiPfiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11getColNormsiiPfiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__getColNormsiiPfiS_, .Lfunc_end0-_Z26__device_stub__getColNormsiiPfiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11getColNormsiiPfiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11getColNormsiiPfiS_,@object # @_Z11getColNormsiiPfiS_
.section .rodata,"a",@progbits
.globl _Z11getColNormsiiPfiS_
.p2align 3, 0x0
_Z11getColNormsiiPfiS_:
.quad _Z26__device_stub__getColNormsiiPfiS_
.size _Z11getColNormsiiPfiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11getColNormsiiPfiS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__getColNormsiiPfiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11getColNormsiiPfiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11getColNormsiiPfiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x164], PT ; /* 0x0000590004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fc600000001ff */
/*0090*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0x800 ; /* 0x0000075000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ IMAD R7, R4, c[0x0][0x170], RZ ; /* 0x00005c0004077a24 */
/* 0x000fe200078e02ff */
/*00d0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fe40000000f00 */
/*0110*/ SHF.R.S32.HI R8, RZ, 0x1f, R7 ; /* 0x0000001fff087819 */
/* 0x000fd20000011407 */
/*0120*/ @!P0 BRA 0x710 ; /* 0x000005e000008947 */
/* 0x000fea0003800000 */
/*0130*/ LEA R2, P0, R7.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0007027a11 */
/* 0x040fe200078010ff */
/*0140*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0150*/ IADD3 R9, -R0, c[0x0][0x160], RZ ; /* 0x0000580000097a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0170*/ LEA.HI.X R3, R7, c[0x0][0x16c], R8, 0x2, P0 ; /* 0x00005b0007037a11 */
/* 0x000fe400000f1408 */
/*0180*/ ISETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f04270 */
/*0190*/ IADD3 R2, P1, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fca0007f3e0ff */
/*01a0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fcc00008e0603 */
/*01b0*/ @!P0 BRA 0x610 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*01c0*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01e0*/ @!P1 BRA 0x460 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0200*/ LDG.E R22, [R2.64+-0x8] ; /* 0xfffff80402167981 */
/* 0x0000a8000c1e1900 */
/*0210*/ LDG.E R24, [R2.64+-0x4] ; /* 0xfffffc0402187981 */
/* 0x0000e8000c1e1900 */
/*0220*/ LDG.E R26, [R2.64] ; /* 0x00000004021a7981 */
/* 0x000128000c1e1900 */
/*0230*/ LDG.E R28, [R2.64+0x4] ; /* 0x00000404021c7981 */
/* 0x000168000c1e1900 */
/*0240*/ LDG.E R21, [R2.64+0x8] ; /* 0x0000080402157981 */
/* 0x000168000c1e1900 */
/*0250*/ LDG.E R20, [R2.64+0xc] ; /* 0x00000c0402147981 */
/* 0x000168000c1e1900 */
/*0260*/ LDG.E R19, [R2.64+0x10] ; /* 0x0000100402137981 */
/* 0x000168000c1e1900 */
/*0270*/ LDG.E R18, [R2.64+0x14] ; /* 0x0000140402127981 */
/* 0x000168000c1e1900 */
/*0280*/ LDG.E R17, [R2.64+0x18] ; /* 0x0000180402117981 */
/* 0x000168000c1e1900 */
/*0290*/ LDG.E R16, [R2.64+0x1c] ; /* 0x00001c0402107981 */
/* 0x000168000c1e1900 */
/*02a0*/ LDG.E R15, [R2.64+0x20] ; /* 0x00002004020f7981 */
/* 0x000168000c1e1900 */
/*02b0*/ LDG.E R14, [R2.64+0x24] ; /* 0x00002404020e7981 */
/* 0x000168000c1e1900 */
/*02c0*/ LDG.E R13, [R2.64+0x28] ; /* 0x00002804020d7981 */
/* 0x000168000c1e1900 */
/*02d0*/ LDG.E R12, [R2.64+0x2c] ; /* 0x00002c04020c7981 */
/* 0x000168000c1e1900 */
/*02e0*/ LDG.E R10, [R2.64+0x30] ; /* 0x00003004020a7981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R11, [R2.64+0x34] ; /* 0x00003404020b7981 */
/* 0x000162000c1e1900 */
/*0300*/ IADD3 R9, R9, -0x10, RZ ; /* 0xfffffff009097810 */
/* 0x000fc40007ffe0ff */
/*0310*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*0320*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*0330*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fc80007f5e0ff */
/*0340*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe200017fe4ff */
/*0350*/ FFMA R5, R22, R22, R5 ; /* 0x0000001616057223 */
/* 0x004fc80000000005 */
/*0360*/ FFMA R5, R24, R24, R5 ; /* 0x0000001818057223 */
/* 0x008fc80000000005 */
/*0370*/ FFMA R5, R26, R26, R5 ; /* 0x0000001a1a057223 */
/* 0x010fc80000000005 */
/*0380*/ FFMA R5, R28, R28, R5 ; /* 0x0000001c1c057223 */
/* 0x020fc80000000005 */
/*0390*/ FFMA R5, R21, R21, R5 ; /* 0x0000001515057223 */
/* 0x000fc80000000005 */
/*03a0*/ FFMA R20, R20, R20, R5 ; /* 0x0000001414147223 */
/* 0x000fc80000000005 */
/*03b0*/ FFMA R19, R19, R19, R20 ; /* 0x0000001313137223 */
/* 0x000fc80000000014 */
/*03c0*/ FFMA R18, R18, R18, R19 ; /* 0x0000001212127223 */
/* 0x000fc80000000013 */
/*03d0*/ FFMA R17, R17, R17, R18 ; /* 0x0000001111117223 */
/* 0x000fc80000000012 */
/*03e0*/ FFMA R16, R16, R16, R17 ; /* 0x0000001010107223 */
/* 0x000fc80000000011 */
/*03f0*/ FFMA R15, R15, R15, R16 ; /* 0x0000000f0f0f7223 */
/* 0x000fc80000000010 */
/*0400*/ FFMA R14, R14, R14, R15 ; /* 0x0000000e0e0e7223 */
/* 0x000fc8000000000f */
/*0410*/ FFMA R13, R13, R13, R14 ; /* 0x0000000d0d0d7223 */
/* 0x000fc8000000000e */
/*0420*/ FFMA R13, R12, R12, R13 ; /* 0x0000000c0c0d7223 */
/* 0x000fc8000000000d */
/*0430*/ FFMA R10, R10, R10, R13 ; /* 0x0000000a0a0a7223 */
/* 0x000fc8000000000d */
/*0440*/ FFMA R5, R11, R11, R10 ; /* 0x0000000b0b057223 */
/* 0x000fe2000000000a */
/*0450*/ @P1 BRA 0x200 ; /* 0xfffffda000001947 */
/* 0x000fea000383ffff */
/*0460*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f24270 */
/*0470*/ @!P1 BRA 0x5f0 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0480*/ LDG.E R10, [R2.64+-0x8] ; /* 0xfffff804020a7981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R12, [R2.64+-0x4] ; /* 0xfffffc04020c7981 */
/* 0x000ee8000c1e1900 */
/*04a0*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000128000c1e1900 */
/*04b0*/ LDG.E R16, [R2.64+0x4] ; /* 0x0000040402107981 */
/* 0x000168000c1e1900 */
/*04c0*/ LDG.E R18, [R2.64+0x8] ; /* 0x0000080402127981 */
/* 0x000168000c1e1900 */
/*04d0*/ LDG.E R20, [R2.64+0xc] ; /* 0x00000c0402147981 */
/* 0x000168000c1e1900 */
/*04e0*/ LDG.E R22, [R2.64+0x10] ; /* 0x0000100402167981 */
/* 0x000168000c1e1900 */
/*04f0*/ LDG.E R24, [R2.64+0x14] ; /* 0x0000140402187981 */
/* 0x000162000c1e1900 */
/*0500*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0510*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*0520*/ IADD3 R9, R9, -0x8, RZ ; /* 0xfffffff809097810 */
/* 0x000fe20007ffe0ff */
/*0530*/ FFMA R5, R10, R10, R5 ; /* 0x0000000a0a057223 */
/* 0x004fe20000000005 */
/*0540*/ IADD3 R10, P1, R2, 0x20, RZ ; /* 0x00000020020a7810 */
/* 0x000fc60007f3e0ff */
/*0550*/ FFMA R5, R12, R12, R5 ; /* 0x0000000c0c057223 */
/* 0x008fe20000000005 */
/*0560*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x001fe20000000f00 */
/*0570*/ IMAD.X R11, RZ, RZ, R3, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe400008e0603 */
/*0580*/ FFMA R5, R14, R14, R5 ; /* 0x0000000e0e057223 */
/* 0x010fe40000000005 */
/*0590*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*05a0*/ FFMA R5, R16, R16, R5 ; /* 0x0000001010057223 */
/* 0x020fc80000000005 */
/*05b0*/ FFMA R5, R18, R18, R5 ; /* 0x0000001212057223 */
/* 0x000fc80000000005 */
/*05c0*/ FFMA R5, R20, R20, R5 ; /* 0x0000001414057223 */
/* 0x000fc80000000005 */
/*05d0*/ FFMA R5, R22, R22, R5 ; /* 0x0000001616057223 */
/* 0x000fc80000000005 */
/*05e0*/ FFMA R5, R24, R24, R5 ; /* 0x0000001818057223 */
/* 0x000fe40000000005 */
/*05f0*/ ISETP.NE.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000705670 */
/*0600*/ @!P0 BRA 0x710 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0610*/ LDG.E R10, [R2.64+-0x8] ; /* 0xfffff804020a7981 */
/* 0x000ea8000c1e1900 */
/*0620*/ LDG.E R12, [R2.64+-0x4] ; /* 0xfffffc04020c7981 */
/* 0x000ee8000c1e1900 */
/*0630*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000128000c1e1900 */
/*0640*/ LDG.E R16, [R2.64+0x4] ; /* 0x0000040402107981 */
/* 0x000162000c1e1900 */
/*0650*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */
/* 0x000fc40007ffe0ff */
/*0660*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007ffe0ff */
/*0670*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*0680*/ FFMA R5, R10, R10, R5 ; /* 0x0000000a0a057223 */
/* 0x004fe20000000005 */
/*0690*/ IADD3 R10, P1, R2, 0x10, RZ ; /* 0x00000010020a7810 */
/* 0x000fc60007f3e0ff */
/*06a0*/ FFMA R5, R12, R12, R5 ; /* 0x0000000c0c057223 */
/* 0x008fe20000000005 */
/*06b0*/ IADD3.X R11, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0b7210 */
/* 0x000fe20000ffe4ff */
/*06c0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x001fe400078e000a */
/*06d0*/ FFMA R5, R14, R14, R5 ; /* 0x0000000e0e057223 */
/* 0x010fe20000000005 */
/*06e0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*06f0*/ FFMA R5, R16, R16, R5 ; /* 0x0000001010057223 */
/* 0x020fe20000000005 */
/*0700*/ @P0 BRA 0x610 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0710*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0720*/ @!P0 BRA 0x800 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0730*/ IADD3 R2, P0, R7, R6, RZ ; /* 0x0000000607027210 */
/* 0x000fc80007f1e0ff */
/*0740*/ LEA R7, P1, R2, c[0x0][0x168], 0x2 ; /* 0x00005a0002077a11 */
/* 0x000fe400078210ff */
/*0750*/ LEA.HI.X.SX32 R3, R6, R8, 0x1, P0 ; /* 0x0000000806037211 */
/* 0x000fc800000f0eff */
/*0760*/ LEA.HI.X R6, R2, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0002067a11 */
/* 0x000fc600008f1403 */
/*0770*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0007 */
/*0780*/ MOV R3, R6 ; /* 0x0000000600037202 */
/* 0x000fca0000000f00 */
/*0790*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*07a0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ IADD3 R7, P1, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007f3e0ff */
/*07c0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*07d0*/ IMAD.X R6, RZ, RZ, R6, P1 ; /* 0x000000ffff067224 */
/* 0x000fe400008e0606 */
/*07e0*/ FFMA R5, R2, R2, R5 ; /* 0x0000000202057223 */
/* 0x004fd00000000005 */
/*07f0*/ @P0 BRA 0x770 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0800*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0810*/ IMAD.WIDE R2, R4, R3, c[0x0][0x178] ; /* 0x00005e0004027625 */
/* 0x000fca00078e0203 */
/*0820*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0830*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0840*/ BRA 0x840; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11getColNormsiiPfiS_
.globl _Z11getColNormsiiPfiS_
.p2align 8
.type _Z11getColNormsiiPfiS_,@function
_Z11getColNormsiiPfiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_3:
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v4, v4
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11getColNormsiiPfiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11getColNormsiiPfiS_, .Lfunc_end0-_Z11getColNormsiiPfiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11getColNormsiiPfiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11getColNormsiiPfiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002dc36_00000000-6_getColNorms.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11getColNormsiiPfiS_iiPfiS_
.type _Z36__device_stub__Z11getColNormsiiPfiS_iiPfiS_, @function
_Z36__device_stub__Z11getColNormsiiPfiS_iiPfiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11getColNormsiiPfiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11getColNormsiiPfiS_iiPfiS_, .-_Z36__device_stub__Z11getColNormsiiPfiS_iiPfiS_
.globl _Z11getColNormsiiPfiS_
.type _Z11getColNormsiiPfiS_, @function
_Z11getColNormsiiPfiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11getColNormsiiPfiS_iiPfiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11getColNormsiiPfiS_, .-_Z11getColNormsiiPfiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11getColNormsiiPfiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11getColNormsiiPfiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "getColNorms.hip"
.globl _Z26__device_stub__getColNormsiiPfiS_ # -- Begin function _Z26__device_stub__getColNormsiiPfiS_
.p2align 4, 0x90
.type _Z26__device_stub__getColNormsiiPfiS_,@function
_Z26__device_stub__getColNormsiiPfiS_: # @_Z26__device_stub__getColNormsiiPfiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11getColNormsiiPfiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__getColNormsiiPfiS_, .Lfunc_end0-_Z26__device_stub__getColNormsiiPfiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11getColNormsiiPfiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11getColNormsiiPfiS_,@object # @_Z11getColNormsiiPfiS_
.section .rodata,"a",@progbits
.globl _Z11getColNormsiiPfiS_
.p2align 3, 0x0
_Z11getColNormsiiPfiS_:
.quad _Z26__device_stub__getColNormsiiPfiS_
.size _Z11getColNormsiiPfiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11getColNormsiiPfiS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__getColNormsiiPfiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11getColNormsiiPfiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include "cuda.h"
#define max(x,y) ((x) > (y)? (x) : (y))
#define min(x,y) ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)
void check_error (const char* message) {
cudaError_t error = cudaGetLastError ();
if (error != cudaSuccess) {
printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error));
exit(-1);
}
}
__global__ void j2d64pt (double * __restrict__ l_in, double * __restrict__ l_out, int N) {
//Determing the block's indices
int i0 = (int)(blockIdx.x)*(int)(blockDim.x) + 4;
int i = max(i0,4) + (int)(threadIdx.x);
int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y) + 4;
int j = max(j0,4) + 4*(int)(threadIdx.y);
double (*in)[8200] = (double (*)[8200]) l_in;
double (*out)[8200] = (double (*)[8200]) l_out;
if (i>=4 & j>=4 & i<=N-5 & j<=N-5) {
double _t_1_;
double _t_10_;
double outjc0ic0;
double _t_3_;
double _t_2_;
double _t_0_;
double _t_8_;
double _t_5_;
double _t_12_;
double _t_23_;
double _t_16_;
double _t_32_;
double _t_36_;
double outjp2ic0;
double _t_9_;
double _t_7_;
double _t_4_;
double _t_11_;
double _t_20_;
double _t_6_;
double _t_13_;
double _t_33_;
double _t_22_;
double _t_15_;
double _t_26_;
double _t_18_;
double _t_38_;
double _t_29_;
double _t_27_;
double outjp3ic0;
double _t_35_;
double outjp1ic0;
double _t_14_;
double _t_21_;
double _t_25_;
double _t_17_;
double _t_28_;
double _t_37_;
double _t_30_;
double _t_39_;
double _t_19_;
double _t_31_;
double _t_24_;
double _t_34_;
_t_1_ = -in[j-4][i-3];
_t_1_ += in[j-4][i+3];
_t_1_ -= in[j-3][i-4];
_t_10_ = in[j-3][i-4];
_t_1_ += in[j-3][i+4];
_t_10_ -= in[j-3][i+4];
_t_1_ += in[j+4][i-3];
_t_1_ -= in[j+4][i+3];
_t_1_ += in[j+3][i-4];
_t_1_ -= in[j+3][i+4];
outjc0ic0 = _t_1_ * 0.000136017;
_t_3_ = -in[j-4][i-1];
_t_3_ += in[j-4][i+1];
_t_3_ -= in[j-1][i-4];
_t_3_ += in[j-1][i+4];
_t_3_ += in[j+1][i-4];
_t_3_ -= in[j+1][i+4];
_t_3_ += in[j+4][i-1];
_t_3_ -= in[j+4][i+1];
outjc0ic0 += _t_3_ * 0.002856;
_t_2_ = in[j-4][i-2];
_t_2_ -= in[j-4][i+2];
_t_2_ -= in[j+4][i-2];
_t_2_ += in[j+4][i+2];
_t_2_ += in[j-2][i-4];
_t_2_ -= in[j-2][i+4];
_t_2_ -= in[j+2][i-4];
_t_2_ += in[j+2][i+4];
outjc0ic0 += _t_2_ * 0.000714;
_t_0_ = in[j-4][i-4];
_t_0_ -= in[j-4][i+4];
_t_0_ -= in[j+4][i-4];
_t_0_ += in[j+4][i+4];
outjc0ic0 += _t_0_ * 1.27449;
_t_8_ = -in[j-2][i-1];
_t_8_ += in[j-2][i+1];
_t_8_ -= in[j-1][i-2];
_t_8_ += in[j-1][i+2];
_t_8_ += in[j+2][i-1];
_t_8_ -= in[j+2][i+1];
_t_8_ += in[j+1][i-2];
_t_8_ -= in[j+1][i+2];
outjc0ic0 += _t_8_ * 0.16;
_t_5_ = in[j+2][i-3];
_t_5_ += -in[j-3][i-2];
_t_12_ = in[j-3][i-2];
_t_12_ += in[j-1][i-4];
_t_12_ -= in[j-1][i+4];
_t_12_ -= in[j+3][i-4];
_t_12_ += in[j+3][i+4];
_t_23_ = -in[j-2][i-1];
_t_23_ += in[j-2][i+1];
_t_23_ -= in[j+1][i-4];
_t_23_ += in[j+1][i+4];
_t_23_ += in[j+3][i-4];
_t_23_ -= in[j+3][i+4];
_t_16_ = in[j-2][i-1];
_t_16_ -= in[j-2][i+1];
_t_16_ -= in[j+2][i-3];
_t_16_ -= in[j+4][i-1];
_t_16_ += in[j+4][i+1];
_t_32_ = in[j-1][i-2];
_t_32_ -= in[j-1][i+2];
_t_32_ += in[j+1][i-4];
_t_32_ -= in[j+1][i+4];
_t_5_ += in[j-3][i+2];
_t_12_ -= in[j-3][i+2];
_t_36_ = in[j+2][i-3];
_t_36_ -= in[j+4][i-3];
_t_36_ += in[j+4][i+3];
_t_5_ -= in[j+2][i+3];
_t_16_ += in[j+2][i+3];
_t_36_ -= in[j+2][i+3];
_t_23_ += in[j+6][i-1];
_t_36_ -= in[j+6][i-1];
_t_23_ -= in[j+6][i+1];
_t_36_ += in[j+6][i+1];
_t_32_ -= in[j+7][i-2];
_t_32_ += in[j+7][i+2];
outjp2ic0 = _t_23_ * 0.002856;
_t_5_ += in[j+3][i-2];
_t_5_ -= in[j+3][i+2];
_t_5_ -= in[j-2][i-3];
_t_5_ += in[j-2][i+3];
outjc0ic0 += _t_5_ * 0.00762;
_t_9_ = in[j-1][i-1];
_t_9_ -= in[j-1][i+1];
_t_9_ -= in[j+1][i-1];
_t_9_ += in[j+1][i+1];
outjc0ic0 += _t_9_ * 0.64;
_t_7_ = -in[j+2][i-2];
_t_7_ += in[j+2][i+2];
_t_7_ += in[j-2][i-2];
_t_7_ -= in[j-2][i+2];
outjc0ic0 += _t_7_ * 0.04;
_t_4_ = -in[j+3][i-3];
_t_4_ += in[j-3][i-3];
_t_11_ = -in[j-3][i-3];
_t_11_ += in[j-2][i+4];
_t_11_ -= in[j-2][i-4];
_t_11_ += in[j+4][i-4];
_t_11_ -= in[j+4][i+4];
_t_20_ = in[j-2][i-4];
_t_20_ -= in[j-2][i+4];
_t_4_ -= in[j-3][i+3];
_t_11_ += in[j-3][i+3];
_t_4_ += in[j+3][i+3];
outjc0ic0 += _t_4_ * 0.00145161;
_t_6_ = in[j-1][i-3];
_t_6_ += in[j-3][i-1];
_t_13_ = -in[j-3][i-1];
_t_13_ += in[j+2][i-4];
_t_13_ -= in[j+2][i+4];
_t_33_ = -in[j-1][i-1];
_t_33_ += in[j-1][i+1];
_t_33_ -= in[j+2][i-4];
_t_33_ += in[j+2][i+4];
_t_33_ += in[j+4][i-4];
_t_33_ -= in[j+4][i+4];
_t_22_ = in[j-2][i-2];
_t_22_ -= in[j-2][i+2];
_t_22_ -= in[j+4][i-4];
_t_22_ += in[j+4][i+4];
_t_15_ = -in[j-2][i-2];
_t_15_ += in[j-2][i+2];
_t_15_ -= in[j-1][i-3];
_t_15_ += in[j+3][i-3];
_t_15_ -= in[j+3][i+3];
_t_15_ += in[j+4][i-2];
_t_15_ -= in[j+4][i+2];
_t_26_ = in[j-1][i-1];
_t_26_ -= in[j-1][i+1];
_t_26_ -= in[j+3][i-3];
_t_26_ += in[j+3][i+3];
_t_18_ = -in[j-1][i-1];
_t_18_ += in[j-1][i+1];
_t_18_ += in[j+2][i-2];
_t_18_ -= in[j+2][i+2];
_t_38_ = -in[j+1][i-1];
_t_38_ += in[j+1][i+1];
_t_38_ -= in[j+2][i-2];
_t_38_ += in[j+2][i+2];
_t_38_ += in[j+4][i-2];
_t_38_ -= in[j+4][i+2];
_t_29_ = in[j+1][i-1];
_t_29_ -= in[j+1][i+1];
_t_27_ = -in[j+4][i-2];
_t_27_ += in[j+4][i+2];
_t_6_ -= in[j+3][i-1];
_t_18_ += in[j+3][i-1];
_t_29_ -= in[j+3][i-1];
_t_6_ += in[j+3][i+1];
_t_18_ -= in[j+3][i+1];
_t_29_ += in[j+3][i+1];
outjp2ic0 += _t_29_ * 0.64;
_t_6_ -= in[j-3][i+1];
_t_13_ += in[j-3][i+1];
_t_13_ += in[j+5][i-1];
_t_26_ -= in[j+5][i-1];
_t_38_ += in[j+5][i-1];
_t_13_ -= in[j+5][i+1];
_t_26_ += in[j+5][i+1];
_t_38_ -= in[j+5][i+1];
outjp3ic0 = _t_38_ * 0.16;
_t_33_ += in[j+7][i-1];
_t_33_ -= in[j+7][i+1];
outjp3ic0 += _t_33_ * 0.002856;
_t_6_ -= in[j+1][i-3];
_t_26_ += in[j+1][i-3];
_t_35_ = -in[j+1][i-3];
_t_6_ += in[j+1][i+3];
_t_26_ -= in[j+1][i+3];
outjp2ic0 += _t_26_ * 0.03048;
_t_35_ += in[j+1][i+3];
_t_18_ -= in[j][i-2];
_t_27_ += in[j][i-2];
_t_35_ += -in[j][i-2];
_t_18_ += in[j][i+2];
_t_27_ -= in[j][i+2];
outjp2ic0 += _t_27_ * 0.04;
_t_35_ += in[j][i+2];
outjp1ic0 = _t_18_ * 0.16;
_t_22_ -= in[j+6][i-2];
_t_35_ += in[j+6][i-2];
_t_22_ += in[j+6][i+2];
_t_35_ -= in[j+6][i+2];
_t_6_ -= in[j-1][i+3];
outjc0ic0 += _t_6_ * 0.03048;
out[j][i] = outjc0ic0;
_t_15_ += in[j-1][i+3];
outjp1ic0 += _t_15_ * 0.00762;
_t_14_ = in[j-2][i-3];
_t_14_ -= in[j-2][i+3];
_t_14_ -= in[j+4][i-3];
_t_14_ += in[j+4][i+3];
outjp1ic0 += _t_14_ * 0.00145161;
_t_21_ = -in[j-2][i-3];
_t_21_ += in[j-2][i+3];
_t_21_ += in[j-1][i+4];
_t_21_ -= in[j-1][i-4];
_t_25_ = -in[j-1][i-2];
_t_25_ += in[j-1][i+2];
_t_25_ += in[j+4][i-3];
_t_25_ -= in[j+4][i+3];
_t_17_ = in[j-1][i-2];
_t_17_ -= in[j-1][i+2];
_t_17_ -= in[j+3][i-2];
_t_17_ += in[j+3][i+2];
outjp1ic0 += _t_17_ * 0.04;
_t_28_ = -in[j+1][i-2];
_t_28_ += in[j+1][i+2];
_t_28_ += in[j+3][i-2];
_t_28_ -= in[j+3][i+2];
_t_28_ += in[j+4][i-1];
_t_28_ -= in[j+4][i+1];
_t_37_ = in[j+1][i-2];
_t_37_ -= in[j+1][i+2];
_t_30_ = in[j-1][i-4];
_t_30_ -= in[j-1][i+4];
_t_39_ = in[j+2][i-1];
_t_39_ -= in[j+2][i+1];
_t_39_ -= in[j+4][i-1];
_t_39_ += in[j+4][i+1];
outjp3ic0 += _t_39_ * 0.64;
_t_19_ = -in[j+2][i-1];
_t_19_ += in[j+2][i+1];
_t_19_ += in[j][i-1];
_t_28_ += -in[j][i-1];
_t_36_ += in[j][i-1];
_t_19_ -= in[j][i+1];
outjp1ic0 += _t_19_ * 0.64;
_t_28_ += in[j][i+1];
outjp2ic0 += _t_28_ * 0.16;
_t_36_ -= in[j][i+1];
outjp3ic0 += _t_36_ * 0.03048;
_t_10_ -= in[j+5][i-4];
_t_21_ += in[j+5][i-4];
_t_32_ -= in[j+5][i-4];
_t_10_ += in[j+5][i+4];
outjp1ic0 += _t_10_ * 1.27449;
_t_21_ -= in[j+5][i+4];
_t_32_ += in[j+5][i+4];
outjp3ic0 += _t_32_ * 0.000714;
_t_12_ -= in[j+5][i-2];
_t_25_ += in[j+5][i-2];
_t_37_ -= in[j+5][i-2];
_t_12_ += in[j+5][i+2];
outjp1ic0 += _t_12_ * 0.000714;
_t_25_ -= in[j+5][i+2];
_t_37_ += in[j+5][i+2];
outjp3ic0 += _t_37_ * 0.04;
_t_30_ -= in[j+7][i-4];
_t_30_ += in[j+7][i+4];
outjp3ic0 += _t_30_ * 1.27449;
_t_13_ -= in[j][i-4];
_t_22_ += in[j][i-4];
_t_31_ = -in[j-1][i-3];
_t_31_ += in[j-1][i+3];
_t_31_ -= in[j][i-4];
_t_24_ = in[j-1][i-3];
_t_24_ -= in[j-1][i+3];
_t_13_ += in[j][i+4];
outjp1ic0 += _t_13_ * 0.002856;
_t_22_ -= in[j][i+4];
outjp2ic0 += _t_22_ * 0.000714;
_t_31_ += in[j][i+4];
_t_11_ += in[j+5][i-3];
_t_24_ -= in[j+5][i-3];
_t_35_ += in[j+5][i-3];
_t_11_ -= in[j+5][i+3];
outjp1ic0 += _t_11_ * 0.000136017;
_t_24_ += in[j+5][i+3];
outjp2ic0 += _t_24_ * 0.00145161;
_t_35_ -= in[j+5][i+3];
outjp3ic0 += _t_35_ * 0.00762;
_t_20_ -= in[j+6][i-4];
_t_31_ += in[j+6][i-4];
_t_20_ += in[j+6][i+4];
outjp2ic0 += _t_20_ * 1.27449;
_t_31_ -= in[j+6][i+4];
_t_31_ += in[j+7][i-3];
_t_31_ -= in[j+7][i+3];
outjp3ic0 += _t_31_ * 0.000136017;
_t_16_ += in[j][i-3];
_t_25_ -= in[j][i-3];
_t_34_ = in[j][i-3];
_t_16_ -= in[j][i+3];
outjp1ic0 += _t_16_ * 0.03048;
out[j+1][i] = outjp1ic0;
_t_25_ += in[j][i+3];
outjp2ic0 += _t_25_ * 0.00762;
_t_34_ -= in[j][i+3];
_t_21_ += in[j+6][i-3];
_t_34_ -= in[j+6][i-3];
_t_21_ -= in[j+6][i+3];
outjp2ic0 += _t_21_ * 0.000136017;
out[j+2][i] = outjp2ic0;
_t_34_ += in[j+6][i+3];
outjp3ic0 += _t_34_ * 0.00145161;
out[j+3][i] = outjp3ic0;
}
}
extern "C" void host_code (double *h_in, double *h_out, int N) {
double *in;
cudaMalloc (&in, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for in\n");
cudaMemcpy (in, h_in, sizeof(double)*N*N, cudaMemcpyHostToDevice);
double *out;
cudaMalloc (&out, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for out\n");
dim3 blockconfig (16, 8);
dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, 4*blockconfig.y));
j2d64pt<<<gridconfig, blockconfig>>> (in, out, N);
cudaMemcpy (h_out, out, sizeof(double)*N*N, cudaMemcpyDeviceToHost);
cudaFree (in);
cudaFree (out);
} | .file "tmpxft_001261cf_00000000-6_reordered-e.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error : %s, %s\n"
.text
.globl _Z11check_errorPKc
.type _Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11check_errorPKc, .-_Z11check_errorPKc
.globl _Z29__device_stub__Z7j2d64ptPdS_iPdS_i
.type _Z29__device_stub__Z7j2d64ptPdS_iPdS_i, @function
_Z29__device_stub__Z7j2d64ptPdS_iPdS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7j2d64ptPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z7j2d64ptPdS_iPdS_i, .-_Z29__device_stub__Z7j2d64ptPdS_iPdS_i
.globl _Z7j2d64ptPdS_i
.type _Z7j2d64ptPdS_i, @function
_Z7j2d64ptPdS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7j2d64ptPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7j2d64ptPdS_i, .-_Z7j2d64ptPdS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to allocate device memory for in\n"
.align 8
.LC2:
.string "Failed to allocate device memory for out\n"
.text
.globl host_code
.type host_code, @function
host_code:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r12
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movslq %edx, %rbx
imulq %rbx, %rbx
salq $3, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC1(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC2(%rip), %rdi
call _Z11check_errorPKc
movl $1, 24(%rsp)
testb $31, %bpl
jne .L16
movl %ebp, %eax
shrl $5, %eax
.L17:
movl %ebp, %edx
shrl $4, %edx
.L19:
movl %edx, 28(%rsp)
movl %eax, 32(%rsp)
movl $16, 16(%rsp)
movl $8, 20(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebp, %eax
shrl $5, %eax
addl $1, %eax
testb $15, %bpl
je .L17
movl %ebp, %edx
shrl $4, %edx
addl $1, %edx
jmp .L19
.L23:
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z7j2d64ptPdS_iPdS_i
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size host_code, .-host_code
.section .rodata.str1.1
.LC3:
.string "_Z7j2d64ptPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7j2d64ptPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include "cuda.h"
#define max(x,y) ((x) > (y)? (x) : (y))
#define min(x,y) ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)
void check_error (const char* message) {
cudaError_t error = cudaGetLastError ();
if (error != cudaSuccess) {
printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error));
exit(-1);
}
}
__global__ void j2d64pt (double * __restrict__ l_in, double * __restrict__ l_out, int N) {
//Determing the block's indices
int i0 = (int)(blockIdx.x)*(int)(blockDim.x) + 4;
int i = max(i0,4) + (int)(threadIdx.x);
int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y) + 4;
int j = max(j0,4) + 4*(int)(threadIdx.y);
double (*in)[8200] = (double (*)[8200]) l_in;
double (*out)[8200] = (double (*)[8200]) l_out;
if (i>=4 & j>=4 & i<=N-5 & j<=N-5) {
double _t_1_;
double _t_10_;
double outjc0ic0;
double _t_3_;
double _t_2_;
double _t_0_;
double _t_8_;
double _t_5_;
double _t_12_;
double _t_23_;
double _t_16_;
double _t_32_;
double _t_36_;
double outjp2ic0;
double _t_9_;
double _t_7_;
double _t_4_;
double _t_11_;
double _t_20_;
double _t_6_;
double _t_13_;
double _t_33_;
double _t_22_;
double _t_15_;
double _t_26_;
double _t_18_;
double _t_38_;
double _t_29_;
double _t_27_;
double outjp3ic0;
double _t_35_;
double outjp1ic0;
double _t_14_;
double _t_21_;
double _t_25_;
double _t_17_;
double _t_28_;
double _t_37_;
double _t_30_;
double _t_39_;
double _t_19_;
double _t_31_;
double _t_24_;
double _t_34_;
_t_1_ = -in[j-4][i-3];
_t_1_ += in[j-4][i+3];
_t_1_ -= in[j-3][i-4];
_t_10_ = in[j-3][i-4];
_t_1_ += in[j-3][i+4];
_t_10_ -= in[j-3][i+4];
_t_1_ += in[j+4][i-3];
_t_1_ -= in[j+4][i+3];
_t_1_ += in[j+3][i-4];
_t_1_ -= in[j+3][i+4];
outjc0ic0 = _t_1_ * 0.000136017;
_t_3_ = -in[j-4][i-1];
_t_3_ += in[j-4][i+1];
_t_3_ -= in[j-1][i-4];
_t_3_ += in[j-1][i+4];
_t_3_ += in[j+1][i-4];
_t_3_ -= in[j+1][i+4];
_t_3_ += in[j+4][i-1];
_t_3_ -= in[j+4][i+1];
outjc0ic0 += _t_3_ * 0.002856;
_t_2_ = in[j-4][i-2];
_t_2_ -= in[j-4][i+2];
_t_2_ -= in[j+4][i-2];
_t_2_ += in[j+4][i+2];
_t_2_ += in[j-2][i-4];
_t_2_ -= in[j-2][i+4];
_t_2_ -= in[j+2][i-4];
_t_2_ += in[j+2][i+4];
outjc0ic0 += _t_2_ * 0.000714;
_t_0_ = in[j-4][i-4];
_t_0_ -= in[j-4][i+4];
_t_0_ -= in[j+4][i-4];
_t_0_ += in[j+4][i+4];
outjc0ic0 += _t_0_ * 1.27449;
_t_8_ = -in[j-2][i-1];
_t_8_ += in[j-2][i+1];
_t_8_ -= in[j-1][i-2];
_t_8_ += in[j-1][i+2];
_t_8_ += in[j+2][i-1];
_t_8_ -= in[j+2][i+1];
_t_8_ += in[j+1][i-2];
_t_8_ -= in[j+1][i+2];
outjc0ic0 += _t_8_ * 0.16;
_t_5_ = in[j+2][i-3];
_t_5_ += -in[j-3][i-2];
_t_12_ = in[j-3][i-2];
_t_12_ += in[j-1][i-4];
_t_12_ -= in[j-1][i+4];
_t_12_ -= in[j+3][i-4];
_t_12_ += in[j+3][i+4];
_t_23_ = -in[j-2][i-1];
_t_23_ += in[j-2][i+1];
_t_23_ -= in[j+1][i-4];
_t_23_ += in[j+1][i+4];
_t_23_ += in[j+3][i-4];
_t_23_ -= in[j+3][i+4];
_t_16_ = in[j-2][i-1];
_t_16_ -= in[j-2][i+1];
_t_16_ -= in[j+2][i-3];
_t_16_ -= in[j+4][i-1];
_t_16_ += in[j+4][i+1];
_t_32_ = in[j-1][i-2];
_t_32_ -= in[j-1][i+2];
_t_32_ += in[j+1][i-4];
_t_32_ -= in[j+1][i+4];
_t_5_ += in[j-3][i+2];
_t_12_ -= in[j-3][i+2];
_t_36_ = in[j+2][i-3];
_t_36_ -= in[j+4][i-3];
_t_36_ += in[j+4][i+3];
_t_5_ -= in[j+2][i+3];
_t_16_ += in[j+2][i+3];
_t_36_ -= in[j+2][i+3];
_t_23_ += in[j+6][i-1];
_t_36_ -= in[j+6][i-1];
_t_23_ -= in[j+6][i+1];
_t_36_ += in[j+6][i+1];
_t_32_ -= in[j+7][i-2];
_t_32_ += in[j+7][i+2];
outjp2ic0 = _t_23_ * 0.002856;
_t_5_ += in[j+3][i-2];
_t_5_ -= in[j+3][i+2];
_t_5_ -= in[j-2][i-3];
_t_5_ += in[j-2][i+3];
outjc0ic0 += _t_5_ * 0.00762;
_t_9_ = in[j-1][i-1];
_t_9_ -= in[j-1][i+1];
_t_9_ -= in[j+1][i-1];
_t_9_ += in[j+1][i+1];
outjc0ic0 += _t_9_ * 0.64;
_t_7_ = -in[j+2][i-2];
_t_7_ += in[j+2][i+2];
_t_7_ += in[j-2][i-2];
_t_7_ -= in[j-2][i+2];
outjc0ic0 += _t_7_ * 0.04;
_t_4_ = -in[j+3][i-3];
_t_4_ += in[j-3][i-3];
_t_11_ = -in[j-3][i-3];
_t_11_ += in[j-2][i+4];
_t_11_ -= in[j-2][i-4];
_t_11_ += in[j+4][i-4];
_t_11_ -= in[j+4][i+4];
_t_20_ = in[j-2][i-4];
_t_20_ -= in[j-2][i+4];
_t_4_ -= in[j-3][i+3];
_t_11_ += in[j-3][i+3];
_t_4_ += in[j+3][i+3];
outjc0ic0 += _t_4_ * 0.00145161;
_t_6_ = in[j-1][i-3];
_t_6_ += in[j-3][i-1];
_t_13_ = -in[j-3][i-1];
_t_13_ += in[j+2][i-4];
_t_13_ -= in[j+2][i+4];
_t_33_ = -in[j-1][i-1];
_t_33_ += in[j-1][i+1];
_t_33_ -= in[j+2][i-4];
_t_33_ += in[j+2][i+4];
_t_33_ += in[j+4][i-4];
_t_33_ -= in[j+4][i+4];
_t_22_ = in[j-2][i-2];
_t_22_ -= in[j-2][i+2];
_t_22_ -= in[j+4][i-4];
_t_22_ += in[j+4][i+4];
_t_15_ = -in[j-2][i-2];
_t_15_ += in[j-2][i+2];
_t_15_ -= in[j-1][i-3];
_t_15_ += in[j+3][i-3];
_t_15_ -= in[j+3][i+3];
_t_15_ += in[j+4][i-2];
_t_15_ -= in[j+4][i+2];
_t_26_ = in[j-1][i-1];
_t_26_ -= in[j-1][i+1];
_t_26_ -= in[j+3][i-3];
_t_26_ += in[j+3][i+3];
_t_18_ = -in[j-1][i-1];
_t_18_ += in[j-1][i+1];
_t_18_ += in[j+2][i-2];
_t_18_ -= in[j+2][i+2];
_t_38_ = -in[j+1][i-1];
_t_38_ += in[j+1][i+1];
_t_38_ -= in[j+2][i-2];
_t_38_ += in[j+2][i+2];
_t_38_ += in[j+4][i-2];
_t_38_ -= in[j+4][i+2];
_t_29_ = in[j+1][i-1];
_t_29_ -= in[j+1][i+1];
_t_27_ = -in[j+4][i-2];
_t_27_ += in[j+4][i+2];
_t_6_ -= in[j+3][i-1];
_t_18_ += in[j+3][i-1];
_t_29_ -= in[j+3][i-1];
_t_6_ += in[j+3][i+1];
_t_18_ -= in[j+3][i+1];
_t_29_ += in[j+3][i+1];
outjp2ic0 += _t_29_ * 0.64;
_t_6_ -= in[j-3][i+1];
_t_13_ += in[j-3][i+1];
_t_13_ += in[j+5][i-1];
_t_26_ -= in[j+5][i-1];
_t_38_ += in[j+5][i-1];
_t_13_ -= in[j+5][i+1];
_t_26_ += in[j+5][i+1];
_t_38_ -= in[j+5][i+1];
outjp3ic0 = _t_38_ * 0.16;
_t_33_ += in[j+7][i-1];
_t_33_ -= in[j+7][i+1];
outjp3ic0 += _t_33_ * 0.002856;
_t_6_ -= in[j+1][i-3];
_t_26_ += in[j+1][i-3];
_t_35_ = -in[j+1][i-3];
_t_6_ += in[j+1][i+3];
_t_26_ -= in[j+1][i+3];
outjp2ic0 += _t_26_ * 0.03048;
_t_35_ += in[j+1][i+3];
_t_18_ -= in[j][i-2];
_t_27_ += in[j][i-2];
_t_35_ += -in[j][i-2];
_t_18_ += in[j][i+2];
_t_27_ -= in[j][i+2];
outjp2ic0 += _t_27_ * 0.04;
_t_35_ += in[j][i+2];
outjp1ic0 = _t_18_ * 0.16;
_t_22_ -= in[j+6][i-2];
_t_35_ += in[j+6][i-2];
_t_22_ += in[j+6][i+2];
_t_35_ -= in[j+6][i+2];
_t_6_ -= in[j-1][i+3];
outjc0ic0 += _t_6_ * 0.03048;
out[j][i] = outjc0ic0;
_t_15_ += in[j-1][i+3];
outjp1ic0 += _t_15_ * 0.00762;
_t_14_ = in[j-2][i-3];
_t_14_ -= in[j-2][i+3];
_t_14_ -= in[j+4][i-3];
_t_14_ += in[j+4][i+3];
outjp1ic0 += _t_14_ * 0.00145161;
_t_21_ = -in[j-2][i-3];
_t_21_ += in[j-2][i+3];
_t_21_ += in[j-1][i+4];
_t_21_ -= in[j-1][i-4];
_t_25_ = -in[j-1][i-2];
_t_25_ += in[j-1][i+2];
_t_25_ += in[j+4][i-3];
_t_25_ -= in[j+4][i+3];
_t_17_ = in[j-1][i-2];
_t_17_ -= in[j-1][i+2];
_t_17_ -= in[j+3][i-2];
_t_17_ += in[j+3][i+2];
outjp1ic0 += _t_17_ * 0.04;
_t_28_ = -in[j+1][i-2];
_t_28_ += in[j+1][i+2];
_t_28_ += in[j+3][i-2];
_t_28_ -= in[j+3][i+2];
_t_28_ += in[j+4][i-1];
_t_28_ -= in[j+4][i+1];
_t_37_ = in[j+1][i-2];
_t_37_ -= in[j+1][i+2];
_t_30_ = in[j-1][i-4];
_t_30_ -= in[j-1][i+4];
_t_39_ = in[j+2][i-1];
_t_39_ -= in[j+2][i+1];
_t_39_ -= in[j+4][i-1];
_t_39_ += in[j+4][i+1];
outjp3ic0 += _t_39_ * 0.64;
_t_19_ = -in[j+2][i-1];
_t_19_ += in[j+2][i+1];
_t_19_ += in[j][i-1];
_t_28_ += -in[j][i-1];
_t_36_ += in[j][i-1];
_t_19_ -= in[j][i+1];
outjp1ic0 += _t_19_ * 0.64;
_t_28_ += in[j][i+1];
outjp2ic0 += _t_28_ * 0.16;
_t_36_ -= in[j][i+1];
outjp3ic0 += _t_36_ * 0.03048;
_t_10_ -= in[j+5][i-4];
_t_21_ += in[j+5][i-4];
_t_32_ -= in[j+5][i-4];
_t_10_ += in[j+5][i+4];
outjp1ic0 += _t_10_ * 1.27449;
_t_21_ -= in[j+5][i+4];
_t_32_ += in[j+5][i+4];
outjp3ic0 += _t_32_ * 0.000714;
_t_12_ -= in[j+5][i-2];
_t_25_ += in[j+5][i-2];
_t_37_ -= in[j+5][i-2];
_t_12_ += in[j+5][i+2];
outjp1ic0 += _t_12_ * 0.000714;
_t_25_ -= in[j+5][i+2];
_t_37_ += in[j+5][i+2];
outjp3ic0 += _t_37_ * 0.04;
_t_30_ -= in[j+7][i-4];
_t_30_ += in[j+7][i+4];
outjp3ic0 += _t_30_ * 1.27449;
_t_13_ -= in[j][i-4];
_t_22_ += in[j][i-4];
_t_31_ = -in[j-1][i-3];
_t_31_ += in[j-1][i+3];
_t_31_ -= in[j][i-4];
_t_24_ = in[j-1][i-3];
_t_24_ -= in[j-1][i+3];
_t_13_ += in[j][i+4];
outjp1ic0 += _t_13_ * 0.002856;
_t_22_ -= in[j][i+4];
outjp2ic0 += _t_22_ * 0.000714;
_t_31_ += in[j][i+4];
_t_11_ += in[j+5][i-3];
_t_24_ -= in[j+5][i-3];
_t_35_ += in[j+5][i-3];
_t_11_ -= in[j+5][i+3];
outjp1ic0 += _t_11_ * 0.000136017;
_t_24_ += in[j+5][i+3];
outjp2ic0 += _t_24_ * 0.00145161;
_t_35_ -= in[j+5][i+3];
outjp3ic0 += _t_35_ * 0.00762;
_t_20_ -= in[j+6][i-4];
_t_31_ += in[j+6][i-4];
_t_20_ += in[j+6][i+4];
outjp2ic0 += _t_20_ * 1.27449;
_t_31_ -= in[j+6][i+4];
_t_31_ += in[j+7][i-3];
_t_31_ -= in[j+7][i+3];
outjp3ic0 += _t_31_ * 0.000136017;
_t_16_ += in[j][i-3];
_t_25_ -= in[j][i-3];
_t_34_ = in[j][i-3];
_t_16_ -= in[j][i+3];
outjp1ic0 += _t_16_ * 0.03048;
out[j+1][i] = outjp1ic0;
_t_25_ += in[j][i+3];
outjp2ic0 += _t_25_ * 0.00762;
_t_34_ -= in[j][i+3];
_t_21_ += in[j+6][i-3];
_t_34_ -= in[j+6][i-3];
_t_21_ -= in[j+6][i+3];
outjp2ic0 += _t_21_ * 0.000136017;
out[j+2][i] = outjp2ic0;
_t_34_ += in[j+6][i+3];
outjp3ic0 += _t_34_ * 0.00145161;
out[j+3][i] = outjp3ic0;
}
}
extern "C" void host_code (double *h_in, double *h_out, int N) {
double *in;
cudaMalloc (&in, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for in\n");
cudaMemcpy (in, h_in, sizeof(double)*N*N, cudaMemcpyHostToDevice);
double *out;
cudaMalloc (&out, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for out\n");
dim3 blockconfig (16, 8);
dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, 4*blockconfig.y));
j2d64pt<<<gridconfig, blockconfig>>> (in, out, N);
cudaMemcpy (h_out, out, sizeof(double)*N*N, cudaMemcpyDeviceToHost);
cudaFree (in);
cudaFree (out);
} | #include <stdio.h>
#include "hip/hip_runtime.h"
#define max(x,y) ((x) > (y)? (x) : (y))
#define min(x,y) ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)
void check_error (const char* message) {
hipError_t error = hipGetLastError ();
if (error != hipSuccess) {
printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error));
exit(-1);
}
}
__global__ void j2d64pt (double * __restrict__ l_in, double * __restrict__ l_out, int N) {
//Determing the block's indices
int i0 = (int)(blockIdx.x)*(int)(blockDim.x) + 4;
int i = max(i0,4) + (int)(threadIdx.x);
int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y) + 4;
int j = max(j0,4) + 4*(int)(threadIdx.y);
double (*in)[8200] = (double (*)[8200]) l_in;
double (*out)[8200] = (double (*)[8200]) l_out;
if (i>=4 & j>=4 & i<=N-5 & j<=N-5) {
double _t_1_;
double _t_10_;
double outjc0ic0;
double _t_3_;
double _t_2_;
double _t_0_;
double _t_8_;
double _t_5_;
double _t_12_;
double _t_23_;
double _t_16_;
double _t_32_;
double _t_36_;
double outjp2ic0;
double _t_9_;
double _t_7_;
double _t_4_;
double _t_11_;
double _t_20_;
double _t_6_;
double _t_13_;
double _t_33_;
double _t_22_;
double _t_15_;
double _t_26_;
double _t_18_;
double _t_38_;
double _t_29_;
double _t_27_;
double outjp3ic0;
double _t_35_;
double outjp1ic0;
double _t_14_;
double _t_21_;
double _t_25_;
double _t_17_;
double _t_28_;
double _t_37_;
double _t_30_;
double _t_39_;
double _t_19_;
double _t_31_;
double _t_24_;
double _t_34_;
_t_1_ = -in[j-4][i-3];
_t_1_ += in[j-4][i+3];
_t_1_ -= in[j-3][i-4];
_t_10_ = in[j-3][i-4];
_t_1_ += in[j-3][i+4];
_t_10_ -= in[j-3][i+4];
_t_1_ += in[j+4][i-3];
_t_1_ -= in[j+4][i+3];
_t_1_ += in[j+3][i-4];
_t_1_ -= in[j+3][i+4];
outjc0ic0 = _t_1_ * 0.000136017;
_t_3_ = -in[j-4][i-1];
_t_3_ += in[j-4][i+1];
_t_3_ -= in[j-1][i-4];
_t_3_ += in[j-1][i+4];
_t_3_ += in[j+1][i-4];
_t_3_ -= in[j+1][i+4];
_t_3_ += in[j+4][i-1];
_t_3_ -= in[j+4][i+1];
outjc0ic0 += _t_3_ * 0.002856;
_t_2_ = in[j-4][i-2];
_t_2_ -= in[j-4][i+2];
_t_2_ -= in[j+4][i-2];
_t_2_ += in[j+4][i+2];
_t_2_ += in[j-2][i-4];
_t_2_ -= in[j-2][i+4];
_t_2_ -= in[j+2][i-4];
_t_2_ += in[j+2][i+4];
outjc0ic0 += _t_2_ * 0.000714;
_t_0_ = in[j-4][i-4];
_t_0_ -= in[j-4][i+4];
_t_0_ -= in[j+4][i-4];
_t_0_ += in[j+4][i+4];
outjc0ic0 += _t_0_ * 1.27449;
_t_8_ = -in[j-2][i-1];
_t_8_ += in[j-2][i+1];
_t_8_ -= in[j-1][i-2];
_t_8_ += in[j-1][i+2];
_t_8_ += in[j+2][i-1];
_t_8_ -= in[j+2][i+1];
_t_8_ += in[j+1][i-2];
_t_8_ -= in[j+1][i+2];
outjc0ic0 += _t_8_ * 0.16;
_t_5_ = in[j+2][i-3];
_t_5_ += -in[j-3][i-2];
_t_12_ = in[j-3][i-2];
_t_12_ += in[j-1][i-4];
_t_12_ -= in[j-1][i+4];
_t_12_ -= in[j+3][i-4];
_t_12_ += in[j+3][i+4];
_t_23_ = -in[j-2][i-1];
_t_23_ += in[j-2][i+1];
_t_23_ -= in[j+1][i-4];
_t_23_ += in[j+1][i+4];
_t_23_ += in[j+3][i-4];
_t_23_ -= in[j+3][i+4];
_t_16_ = in[j-2][i-1];
_t_16_ -= in[j-2][i+1];
_t_16_ -= in[j+2][i-3];
_t_16_ -= in[j+4][i-1];
_t_16_ += in[j+4][i+1];
_t_32_ = in[j-1][i-2];
_t_32_ -= in[j-1][i+2];
_t_32_ += in[j+1][i-4];
_t_32_ -= in[j+1][i+4];
_t_5_ += in[j-3][i+2];
_t_12_ -= in[j-3][i+2];
_t_36_ = in[j+2][i-3];
_t_36_ -= in[j+4][i-3];
_t_36_ += in[j+4][i+3];
_t_5_ -= in[j+2][i+3];
_t_16_ += in[j+2][i+3];
_t_36_ -= in[j+2][i+3];
_t_23_ += in[j+6][i-1];
_t_36_ -= in[j+6][i-1];
_t_23_ -= in[j+6][i+1];
_t_36_ += in[j+6][i+1];
_t_32_ -= in[j+7][i-2];
_t_32_ += in[j+7][i+2];
outjp2ic0 = _t_23_ * 0.002856;
_t_5_ += in[j+3][i-2];
_t_5_ -= in[j+3][i+2];
_t_5_ -= in[j-2][i-3];
_t_5_ += in[j-2][i+3];
outjc0ic0 += _t_5_ * 0.00762;
_t_9_ = in[j-1][i-1];
_t_9_ -= in[j-1][i+1];
_t_9_ -= in[j+1][i-1];
_t_9_ += in[j+1][i+1];
outjc0ic0 += _t_9_ * 0.64;
_t_7_ = -in[j+2][i-2];
_t_7_ += in[j+2][i+2];
_t_7_ += in[j-2][i-2];
_t_7_ -= in[j-2][i+2];
outjc0ic0 += _t_7_ * 0.04;
_t_4_ = -in[j+3][i-3];
_t_4_ += in[j-3][i-3];
_t_11_ = -in[j-3][i-3];
_t_11_ += in[j-2][i+4];
_t_11_ -= in[j-2][i-4];
_t_11_ += in[j+4][i-4];
_t_11_ -= in[j+4][i+4];
_t_20_ = in[j-2][i-4];
_t_20_ -= in[j-2][i+4];
_t_4_ -= in[j-3][i+3];
_t_11_ += in[j-3][i+3];
_t_4_ += in[j+3][i+3];
outjc0ic0 += _t_4_ * 0.00145161;
_t_6_ = in[j-1][i-3];
_t_6_ += in[j-3][i-1];
_t_13_ = -in[j-3][i-1];
_t_13_ += in[j+2][i-4];
_t_13_ -= in[j+2][i+4];
_t_33_ = -in[j-1][i-1];
_t_33_ += in[j-1][i+1];
_t_33_ -= in[j+2][i-4];
_t_33_ += in[j+2][i+4];
_t_33_ += in[j+4][i-4];
_t_33_ -= in[j+4][i+4];
_t_22_ = in[j-2][i-2];
_t_22_ -= in[j-2][i+2];
_t_22_ -= in[j+4][i-4];
_t_22_ += in[j+4][i+4];
_t_15_ = -in[j-2][i-2];
_t_15_ += in[j-2][i+2];
_t_15_ -= in[j-1][i-3];
_t_15_ += in[j+3][i-3];
_t_15_ -= in[j+3][i+3];
_t_15_ += in[j+4][i-2];
_t_15_ -= in[j+4][i+2];
_t_26_ = in[j-1][i-1];
_t_26_ -= in[j-1][i+1];
_t_26_ -= in[j+3][i-3];
_t_26_ += in[j+3][i+3];
_t_18_ = -in[j-1][i-1];
_t_18_ += in[j-1][i+1];
_t_18_ += in[j+2][i-2];
_t_18_ -= in[j+2][i+2];
_t_38_ = -in[j+1][i-1];
_t_38_ += in[j+1][i+1];
_t_38_ -= in[j+2][i-2];
_t_38_ += in[j+2][i+2];
_t_38_ += in[j+4][i-2];
_t_38_ -= in[j+4][i+2];
_t_29_ = in[j+1][i-1];
_t_29_ -= in[j+1][i+1];
_t_27_ = -in[j+4][i-2];
_t_27_ += in[j+4][i+2];
_t_6_ -= in[j+3][i-1];
_t_18_ += in[j+3][i-1];
_t_29_ -= in[j+3][i-1];
_t_6_ += in[j+3][i+1];
_t_18_ -= in[j+3][i+1];
_t_29_ += in[j+3][i+1];
outjp2ic0 += _t_29_ * 0.64;
_t_6_ -= in[j-3][i+1];
_t_13_ += in[j-3][i+1];
_t_13_ += in[j+5][i-1];
_t_26_ -= in[j+5][i-1];
_t_38_ += in[j+5][i-1];
_t_13_ -= in[j+5][i+1];
_t_26_ += in[j+5][i+1];
_t_38_ -= in[j+5][i+1];
outjp3ic0 = _t_38_ * 0.16;
_t_33_ += in[j+7][i-1];
_t_33_ -= in[j+7][i+1];
outjp3ic0 += _t_33_ * 0.002856;
_t_6_ -= in[j+1][i-3];
_t_26_ += in[j+1][i-3];
_t_35_ = -in[j+1][i-3];
_t_6_ += in[j+1][i+3];
_t_26_ -= in[j+1][i+3];
outjp2ic0 += _t_26_ * 0.03048;
_t_35_ += in[j+1][i+3];
_t_18_ -= in[j][i-2];
_t_27_ += in[j][i-2];
_t_35_ += -in[j][i-2];
_t_18_ += in[j][i+2];
_t_27_ -= in[j][i+2];
outjp2ic0 += _t_27_ * 0.04;
_t_35_ += in[j][i+2];
outjp1ic0 = _t_18_ * 0.16;
_t_22_ -= in[j+6][i-2];
_t_35_ += in[j+6][i-2];
_t_22_ += in[j+6][i+2];
_t_35_ -= in[j+6][i+2];
_t_6_ -= in[j-1][i+3];
outjc0ic0 += _t_6_ * 0.03048;
out[j][i] = outjc0ic0;
_t_15_ += in[j-1][i+3];
outjp1ic0 += _t_15_ * 0.00762;
_t_14_ = in[j-2][i-3];
_t_14_ -= in[j-2][i+3];
_t_14_ -= in[j+4][i-3];
_t_14_ += in[j+4][i+3];
outjp1ic0 += _t_14_ * 0.00145161;
_t_21_ = -in[j-2][i-3];
_t_21_ += in[j-2][i+3];
_t_21_ += in[j-1][i+4];
_t_21_ -= in[j-1][i-4];
_t_25_ = -in[j-1][i-2];
_t_25_ += in[j-1][i+2];
_t_25_ += in[j+4][i-3];
_t_25_ -= in[j+4][i+3];
_t_17_ = in[j-1][i-2];
_t_17_ -= in[j-1][i+2];
_t_17_ -= in[j+3][i-2];
_t_17_ += in[j+3][i+2];
outjp1ic0 += _t_17_ * 0.04;
_t_28_ = -in[j+1][i-2];
_t_28_ += in[j+1][i+2];
_t_28_ += in[j+3][i-2];
_t_28_ -= in[j+3][i+2];
_t_28_ += in[j+4][i-1];
_t_28_ -= in[j+4][i+1];
_t_37_ = in[j+1][i-2];
_t_37_ -= in[j+1][i+2];
_t_30_ = in[j-1][i-4];
_t_30_ -= in[j-1][i+4];
_t_39_ = in[j+2][i-1];
_t_39_ -= in[j+2][i+1];
_t_39_ -= in[j+4][i-1];
_t_39_ += in[j+4][i+1];
outjp3ic0 += _t_39_ * 0.64;
_t_19_ = -in[j+2][i-1];
_t_19_ += in[j+2][i+1];
_t_19_ += in[j][i-1];
_t_28_ += -in[j][i-1];
_t_36_ += in[j][i-1];
_t_19_ -= in[j][i+1];
outjp1ic0 += _t_19_ * 0.64;
_t_28_ += in[j][i+1];
outjp2ic0 += _t_28_ * 0.16;
_t_36_ -= in[j][i+1];
outjp3ic0 += _t_36_ * 0.03048;
_t_10_ -= in[j+5][i-4];
_t_21_ += in[j+5][i-4];
_t_32_ -= in[j+5][i-4];
_t_10_ += in[j+5][i+4];
outjp1ic0 += _t_10_ * 1.27449;
_t_21_ -= in[j+5][i+4];
_t_32_ += in[j+5][i+4];
outjp3ic0 += _t_32_ * 0.000714;
_t_12_ -= in[j+5][i-2];
_t_25_ += in[j+5][i-2];
_t_37_ -= in[j+5][i-2];
_t_12_ += in[j+5][i+2];
outjp1ic0 += _t_12_ * 0.000714;
_t_25_ -= in[j+5][i+2];
_t_37_ += in[j+5][i+2];
outjp3ic0 += _t_37_ * 0.04;
_t_30_ -= in[j+7][i-4];
_t_30_ += in[j+7][i+4];
outjp3ic0 += _t_30_ * 1.27449;
_t_13_ -= in[j][i-4];
_t_22_ += in[j][i-4];
_t_31_ = -in[j-1][i-3];
_t_31_ += in[j-1][i+3];
_t_31_ -= in[j][i-4];
_t_24_ = in[j-1][i-3];
_t_24_ -= in[j-1][i+3];
_t_13_ += in[j][i+4];
outjp1ic0 += _t_13_ * 0.002856;
_t_22_ -= in[j][i+4];
outjp2ic0 += _t_22_ * 0.000714;
_t_31_ += in[j][i+4];
_t_11_ += in[j+5][i-3];
_t_24_ -= in[j+5][i-3];
_t_35_ += in[j+5][i-3];
_t_11_ -= in[j+5][i+3];
outjp1ic0 += _t_11_ * 0.000136017;
_t_24_ += in[j+5][i+3];
outjp2ic0 += _t_24_ * 0.00145161;
_t_35_ -= in[j+5][i+3];
outjp3ic0 += _t_35_ * 0.00762;
_t_20_ -= in[j+6][i-4];
_t_31_ += in[j+6][i-4];
_t_20_ += in[j+6][i+4];
outjp2ic0 += _t_20_ * 1.27449;
_t_31_ -= in[j+6][i+4];
_t_31_ += in[j+7][i-3];
_t_31_ -= in[j+7][i+3];
outjp3ic0 += _t_31_ * 0.000136017;
_t_16_ += in[j][i-3];
_t_25_ -= in[j][i-3];
_t_34_ = in[j][i-3];
_t_16_ -= in[j][i+3];
outjp1ic0 += _t_16_ * 0.03048;
out[j+1][i] = outjp1ic0;
_t_25_ += in[j][i+3];
outjp2ic0 += _t_25_ * 0.00762;
_t_34_ -= in[j][i+3];
_t_21_ += in[j+6][i-3];
_t_34_ -= in[j+6][i-3];
_t_21_ -= in[j+6][i+3];
outjp2ic0 += _t_21_ * 0.000136017;
out[j+2][i] = outjp2ic0;
_t_34_ += in[j+6][i+3];
outjp3ic0 += _t_34_ * 0.00145161;
out[j+3][i] = outjp3ic0;
}
}
extern "C" void host_code (double *h_in, double *h_out, int N) {
double *in;
hipMalloc (&in, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for in\n");
hipMemcpy (in, h_in, sizeof(double)*N*N, hipMemcpyHostToDevice);
double *out;
hipMalloc (&out, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for out\n");
dim3 blockconfig (16, 8);
dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, 4*blockconfig.y));
j2d64pt<<<gridconfig, blockconfig>>> (in, out, N);
hipMemcpy (h_out, out, sizeof(double)*N*N, hipMemcpyDeviceToHost);
hipFree (in);
hipFree (out);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include "hip/hip_runtime.h"
#define max(x,y) ((x) > (y)? (x) : (y))
#define min(x,y) ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)
void check_error (const char* message) {
hipError_t error = hipGetLastError ();
if (error != hipSuccess) {
printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error));
exit(-1);
}
}
__global__ void j2d64pt (double * __restrict__ l_in, double * __restrict__ l_out, int N) {
//Determing the block's indices
int i0 = (int)(blockIdx.x)*(int)(blockDim.x) + 4;
int i = max(i0,4) + (int)(threadIdx.x);
int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y) + 4;
int j = max(j0,4) + 4*(int)(threadIdx.y);
double (*in)[8200] = (double (*)[8200]) l_in;
double (*out)[8200] = (double (*)[8200]) l_out;
if (i>=4 & j>=4 & i<=N-5 & j<=N-5) {
double _t_1_;
double _t_10_;
double outjc0ic0;
double _t_3_;
double _t_2_;
double _t_0_;
double _t_8_;
double _t_5_;
double _t_12_;
double _t_23_;
double _t_16_;
double _t_32_;
double _t_36_;
double outjp2ic0;
double _t_9_;
double _t_7_;
double _t_4_;
double _t_11_;
double _t_20_;
double _t_6_;
double _t_13_;
double _t_33_;
double _t_22_;
double _t_15_;
double _t_26_;
double _t_18_;
double _t_38_;
double _t_29_;
double _t_27_;
double outjp3ic0;
double _t_35_;
double outjp1ic0;
double _t_14_;
double _t_21_;
double _t_25_;
double _t_17_;
double _t_28_;
double _t_37_;
double _t_30_;
double _t_39_;
double _t_19_;
double _t_31_;
double _t_24_;
double _t_34_;
_t_1_ = -in[j-4][i-3];
_t_1_ += in[j-4][i+3];
_t_1_ -= in[j-3][i-4];
_t_10_ = in[j-3][i-4];
_t_1_ += in[j-3][i+4];
_t_10_ -= in[j-3][i+4];
_t_1_ += in[j+4][i-3];
_t_1_ -= in[j+4][i+3];
_t_1_ += in[j+3][i-4];
_t_1_ -= in[j+3][i+4];
outjc0ic0 = _t_1_ * 0.000136017;
_t_3_ = -in[j-4][i-1];
_t_3_ += in[j-4][i+1];
_t_3_ -= in[j-1][i-4];
_t_3_ += in[j-1][i+4];
_t_3_ += in[j+1][i-4];
_t_3_ -= in[j+1][i+4];
_t_3_ += in[j+4][i-1];
_t_3_ -= in[j+4][i+1];
outjc0ic0 += _t_3_ * 0.002856;
_t_2_ = in[j-4][i-2];
_t_2_ -= in[j-4][i+2];
_t_2_ -= in[j+4][i-2];
_t_2_ += in[j+4][i+2];
_t_2_ += in[j-2][i-4];
_t_2_ -= in[j-2][i+4];
_t_2_ -= in[j+2][i-4];
_t_2_ += in[j+2][i+4];
outjc0ic0 += _t_2_ * 0.000714;
_t_0_ = in[j-4][i-4];
_t_0_ -= in[j-4][i+4];
_t_0_ -= in[j+4][i-4];
_t_0_ += in[j+4][i+4];
outjc0ic0 += _t_0_ * 1.27449;
_t_8_ = -in[j-2][i-1];
_t_8_ += in[j-2][i+1];
_t_8_ -= in[j-1][i-2];
_t_8_ += in[j-1][i+2];
_t_8_ += in[j+2][i-1];
_t_8_ -= in[j+2][i+1];
_t_8_ += in[j+1][i-2];
_t_8_ -= in[j+1][i+2];
outjc0ic0 += _t_8_ * 0.16;
_t_5_ = in[j+2][i-3];
_t_5_ += -in[j-3][i-2];
_t_12_ = in[j-3][i-2];
_t_12_ += in[j-1][i-4];
_t_12_ -= in[j-1][i+4];
_t_12_ -= in[j+3][i-4];
_t_12_ += in[j+3][i+4];
_t_23_ = -in[j-2][i-1];
_t_23_ += in[j-2][i+1];
_t_23_ -= in[j+1][i-4];
_t_23_ += in[j+1][i+4];
_t_23_ += in[j+3][i-4];
_t_23_ -= in[j+3][i+4];
_t_16_ = in[j-2][i-1];
_t_16_ -= in[j-2][i+1];
_t_16_ -= in[j+2][i-3];
_t_16_ -= in[j+4][i-1];
_t_16_ += in[j+4][i+1];
_t_32_ = in[j-1][i-2];
_t_32_ -= in[j-1][i+2];
_t_32_ += in[j+1][i-4];
_t_32_ -= in[j+1][i+4];
_t_5_ += in[j-3][i+2];
_t_12_ -= in[j-3][i+2];
_t_36_ = in[j+2][i-3];
_t_36_ -= in[j+4][i-3];
_t_36_ += in[j+4][i+3];
_t_5_ -= in[j+2][i+3];
_t_16_ += in[j+2][i+3];
_t_36_ -= in[j+2][i+3];
_t_23_ += in[j+6][i-1];
_t_36_ -= in[j+6][i-1];
_t_23_ -= in[j+6][i+1];
_t_36_ += in[j+6][i+1];
_t_32_ -= in[j+7][i-2];
_t_32_ += in[j+7][i+2];
outjp2ic0 = _t_23_ * 0.002856;
_t_5_ += in[j+3][i-2];
_t_5_ -= in[j+3][i+2];
_t_5_ -= in[j-2][i-3];
_t_5_ += in[j-2][i+3];
outjc0ic0 += _t_5_ * 0.00762;
_t_9_ = in[j-1][i-1];
_t_9_ -= in[j-1][i+1];
_t_9_ -= in[j+1][i-1];
_t_9_ += in[j+1][i+1];
outjc0ic0 += _t_9_ * 0.64;
_t_7_ = -in[j+2][i-2];
_t_7_ += in[j+2][i+2];
_t_7_ += in[j-2][i-2];
_t_7_ -= in[j-2][i+2];
outjc0ic0 += _t_7_ * 0.04;
_t_4_ = -in[j+3][i-3];
_t_4_ += in[j-3][i-3];
_t_11_ = -in[j-3][i-3];
_t_11_ += in[j-2][i+4];
_t_11_ -= in[j-2][i-4];
_t_11_ += in[j+4][i-4];
_t_11_ -= in[j+4][i+4];
_t_20_ = in[j-2][i-4];
_t_20_ -= in[j-2][i+4];
_t_4_ -= in[j-3][i+3];
_t_11_ += in[j-3][i+3];
_t_4_ += in[j+3][i+3];
outjc0ic0 += _t_4_ * 0.00145161;
_t_6_ = in[j-1][i-3];
_t_6_ += in[j-3][i-1];
_t_13_ = -in[j-3][i-1];
_t_13_ += in[j+2][i-4];
_t_13_ -= in[j+2][i+4];
_t_33_ = -in[j-1][i-1];
_t_33_ += in[j-1][i+1];
_t_33_ -= in[j+2][i-4];
_t_33_ += in[j+2][i+4];
_t_33_ += in[j+4][i-4];
_t_33_ -= in[j+4][i+4];
_t_22_ = in[j-2][i-2];
_t_22_ -= in[j-2][i+2];
_t_22_ -= in[j+4][i-4];
_t_22_ += in[j+4][i+4];
_t_15_ = -in[j-2][i-2];
_t_15_ += in[j-2][i+2];
_t_15_ -= in[j-1][i-3];
_t_15_ += in[j+3][i-3];
_t_15_ -= in[j+3][i+3];
_t_15_ += in[j+4][i-2];
_t_15_ -= in[j+4][i+2];
_t_26_ = in[j-1][i-1];
_t_26_ -= in[j-1][i+1];
_t_26_ -= in[j+3][i-3];
_t_26_ += in[j+3][i+3];
_t_18_ = -in[j-1][i-1];
_t_18_ += in[j-1][i+1];
_t_18_ += in[j+2][i-2];
_t_18_ -= in[j+2][i+2];
_t_38_ = -in[j+1][i-1];
_t_38_ += in[j+1][i+1];
_t_38_ -= in[j+2][i-2];
_t_38_ += in[j+2][i+2];
_t_38_ += in[j+4][i-2];
_t_38_ -= in[j+4][i+2];
_t_29_ = in[j+1][i-1];
_t_29_ -= in[j+1][i+1];
_t_27_ = -in[j+4][i-2];
_t_27_ += in[j+4][i+2];
_t_6_ -= in[j+3][i-1];
_t_18_ += in[j+3][i-1];
_t_29_ -= in[j+3][i-1];
_t_6_ += in[j+3][i+1];
_t_18_ -= in[j+3][i+1];
_t_29_ += in[j+3][i+1];
outjp2ic0 += _t_29_ * 0.64;
_t_6_ -= in[j-3][i+1];
_t_13_ += in[j-3][i+1];
_t_13_ += in[j+5][i-1];
_t_26_ -= in[j+5][i-1];
_t_38_ += in[j+5][i-1];
_t_13_ -= in[j+5][i+1];
_t_26_ += in[j+5][i+1];
_t_38_ -= in[j+5][i+1];
outjp3ic0 = _t_38_ * 0.16;
_t_33_ += in[j+7][i-1];
_t_33_ -= in[j+7][i+1];
outjp3ic0 += _t_33_ * 0.002856;
_t_6_ -= in[j+1][i-3];
_t_26_ += in[j+1][i-3];
_t_35_ = -in[j+1][i-3];
_t_6_ += in[j+1][i+3];
_t_26_ -= in[j+1][i+3];
outjp2ic0 += _t_26_ * 0.03048;
_t_35_ += in[j+1][i+3];
_t_18_ -= in[j][i-2];
_t_27_ += in[j][i-2];
_t_35_ += -in[j][i-2];
_t_18_ += in[j][i+2];
_t_27_ -= in[j][i+2];
outjp2ic0 += _t_27_ * 0.04;
_t_35_ += in[j][i+2];
outjp1ic0 = _t_18_ * 0.16;
_t_22_ -= in[j+6][i-2];
_t_35_ += in[j+6][i-2];
_t_22_ += in[j+6][i+2];
_t_35_ -= in[j+6][i+2];
_t_6_ -= in[j-1][i+3];
outjc0ic0 += _t_6_ * 0.03048;
out[j][i] = outjc0ic0;
_t_15_ += in[j-1][i+3];
outjp1ic0 += _t_15_ * 0.00762;
_t_14_ = in[j-2][i-3];
_t_14_ -= in[j-2][i+3];
_t_14_ -= in[j+4][i-3];
_t_14_ += in[j+4][i+3];
outjp1ic0 += _t_14_ * 0.00145161;
_t_21_ = -in[j-2][i-3];
_t_21_ += in[j-2][i+3];
_t_21_ += in[j-1][i+4];
_t_21_ -= in[j-1][i-4];
_t_25_ = -in[j-1][i-2];
_t_25_ += in[j-1][i+2];
_t_25_ += in[j+4][i-3];
_t_25_ -= in[j+4][i+3];
_t_17_ = in[j-1][i-2];
_t_17_ -= in[j-1][i+2];
_t_17_ -= in[j+3][i-2];
_t_17_ += in[j+3][i+2];
outjp1ic0 += _t_17_ * 0.04;
_t_28_ = -in[j+1][i-2];
_t_28_ += in[j+1][i+2];
_t_28_ += in[j+3][i-2];
_t_28_ -= in[j+3][i+2];
_t_28_ += in[j+4][i-1];
_t_28_ -= in[j+4][i+1];
_t_37_ = in[j+1][i-2];
_t_37_ -= in[j+1][i+2];
_t_30_ = in[j-1][i-4];
_t_30_ -= in[j-1][i+4];
_t_39_ = in[j+2][i-1];
_t_39_ -= in[j+2][i+1];
_t_39_ -= in[j+4][i-1];
_t_39_ += in[j+4][i+1];
outjp3ic0 += _t_39_ * 0.64;
_t_19_ = -in[j+2][i-1];
_t_19_ += in[j+2][i+1];
_t_19_ += in[j][i-1];
_t_28_ += -in[j][i-1];
_t_36_ += in[j][i-1];
_t_19_ -= in[j][i+1];
outjp1ic0 += _t_19_ * 0.64;
_t_28_ += in[j][i+1];
outjp2ic0 += _t_28_ * 0.16;
_t_36_ -= in[j][i+1];
outjp3ic0 += _t_36_ * 0.03048;
_t_10_ -= in[j+5][i-4];
_t_21_ += in[j+5][i-4];
_t_32_ -= in[j+5][i-4];
_t_10_ += in[j+5][i+4];
outjp1ic0 += _t_10_ * 1.27449;
_t_21_ -= in[j+5][i+4];
_t_32_ += in[j+5][i+4];
outjp3ic0 += _t_32_ * 0.000714;
_t_12_ -= in[j+5][i-2];
_t_25_ += in[j+5][i-2];
_t_37_ -= in[j+5][i-2];
_t_12_ += in[j+5][i+2];
outjp1ic0 += _t_12_ * 0.000714;
_t_25_ -= in[j+5][i+2];
_t_37_ += in[j+5][i+2];
outjp3ic0 += _t_37_ * 0.04;
_t_30_ -= in[j+7][i-4];
_t_30_ += in[j+7][i+4];
outjp3ic0 += _t_30_ * 1.27449;
_t_13_ -= in[j][i-4];
_t_22_ += in[j][i-4];
_t_31_ = -in[j-1][i-3];
_t_31_ += in[j-1][i+3];
_t_31_ -= in[j][i-4];
_t_24_ = in[j-1][i-3];
_t_24_ -= in[j-1][i+3];
_t_13_ += in[j][i+4];
outjp1ic0 += _t_13_ * 0.002856;
_t_22_ -= in[j][i+4];
outjp2ic0 += _t_22_ * 0.000714;
_t_31_ += in[j][i+4];
_t_11_ += in[j+5][i-3];
_t_24_ -= in[j+5][i-3];
_t_35_ += in[j+5][i-3];
_t_11_ -= in[j+5][i+3];
outjp1ic0 += _t_11_ * 0.000136017;
_t_24_ += in[j+5][i+3];
outjp2ic0 += _t_24_ * 0.00145161;
_t_35_ -= in[j+5][i+3];
outjp3ic0 += _t_35_ * 0.00762;
_t_20_ -= in[j+6][i-4];
_t_31_ += in[j+6][i-4];
_t_20_ += in[j+6][i+4];
outjp2ic0 += _t_20_ * 1.27449;
_t_31_ -= in[j+6][i+4];
_t_31_ += in[j+7][i-3];
_t_31_ -= in[j+7][i+3];
outjp3ic0 += _t_31_ * 0.000136017;
_t_16_ += in[j][i-3];
_t_25_ -= in[j][i-3];
_t_34_ = in[j][i-3];
_t_16_ -= in[j][i+3];
outjp1ic0 += _t_16_ * 0.03048;
out[j+1][i] = outjp1ic0;
_t_25_ += in[j][i+3];
outjp2ic0 += _t_25_ * 0.00762;
_t_34_ -= in[j][i+3];
_t_21_ += in[j+6][i-3];
_t_34_ -= in[j+6][i-3];
_t_21_ -= in[j+6][i+3];
outjp2ic0 += _t_21_ * 0.000136017;
out[j+2][i] = outjp2ic0;
_t_34_ += in[j+6][i+3];
outjp3ic0 += _t_34_ * 0.00145161;
out[j+3][i] = outjp3ic0;
}
}
extern "C" void host_code (double *h_in, double *h_out, int N) {
double *in;
hipMalloc (&in, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for in\n");
hipMemcpy (in, h_in, sizeof(double)*N*N, hipMemcpyHostToDevice);
double *out;
hipMalloc (&out, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for out\n");
dim3 blockconfig (16, 8);
dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, 4*blockconfig.y));
j2d64pt<<<gridconfig, blockconfig>>> (in, out, N);
hipMemcpy (h_out, out, sizeof(double)*N*N, hipMemcpyDeviceToHost);
hipFree (in);
hipFree (out);
} | .text
.file "reordered-e.hip"
.globl _Z11check_errorPKc # -- Begin function _Z11check_errorPKc
.p2align 4, 0x90
.type _Z11check_errorPKc,@function
_Z11check_errorPKc: # @_Z11check_errorPKc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rbx, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
.cfi_endproc
# -- End function
.globl _Z22__device_stub__j2d64ptPdS_i # -- Begin function _Z22__device_stub__j2d64ptPdS_i
.p2align 4, 0x90
.type _Z22__device_stub__j2d64ptPdS_i,@function
_Z22__device_stub__j2d64ptPdS_i: # @_Z22__device_stub__j2d64ptPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7j2d64ptPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__j2d64ptPdS_i, .Lfunc_end1-_Z22__device_stub__j2d64ptPdS_i
.cfi_endproc
# -- End function
.globl host_code # -- Begin function host_code
.p2align 4, 0x90
.type host_code,@function
host_code: # @host_code
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
movslq %edx, %rbx
imulq %rbx, %rbx
shlq $3, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z11check_errorPKc.exit
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_Z11check_errorPKc.exit23
movl %ebp, %eax
shrl $4, %eax
leal 1(%rax), %ecx
testb $15, %bpl
cmovel %eax, %ecx
movl %ebp, %eax
shrl $5, %eax
leal 1(%rax), %edi
testb $31, %bpl
cmovel %eax, %edi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $34359738384, %rdx # imm = 0x800000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7j2d64ptPdS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 160
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.2, %esi
.LBB2_2:
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size host_code, .Lfunc_end2-host_code
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7j2d64ptPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error : %s, %s\n"
.size .L.str, 21
.type _Z7j2d64ptPdS_i,@object # @_Z7j2d64ptPdS_i
.section .rodata,"a",@progbits
.globl _Z7j2d64ptPdS_i
.p2align 3, 0x0
_Z7j2d64ptPdS_i:
.quad _Z22__device_stub__j2d64ptPdS_i
.size _Z7j2d64ptPdS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Failed to allocate device memory for in\n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate device memory for out\n"
.size .L.str.2, 42
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7j2d64ptPdS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__j2d64ptPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7j2d64ptPdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001261cf_00000000-6_reordered-e.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error : %s, %s\n"
.text
.globl _Z11check_errorPKc
.type _Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11check_errorPKc, .-_Z11check_errorPKc
.globl _Z29__device_stub__Z7j2d64ptPdS_iPdS_i
.type _Z29__device_stub__Z7j2d64ptPdS_iPdS_i, @function
_Z29__device_stub__Z7j2d64ptPdS_iPdS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7j2d64ptPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z7j2d64ptPdS_iPdS_i, .-_Z29__device_stub__Z7j2d64ptPdS_iPdS_i
.globl _Z7j2d64ptPdS_i
.type _Z7j2d64ptPdS_i, @function
_Z7j2d64ptPdS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7j2d64ptPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7j2d64ptPdS_i, .-_Z7j2d64ptPdS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to allocate device memory for in\n"
.align 8
.LC2:
.string "Failed to allocate device memory for out\n"
.text
.globl host_code
.type host_code, @function
host_code:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r12
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movslq %edx, %rbx
imulq %rbx, %rbx
salq $3, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC1(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC2(%rip), %rdi
call _Z11check_errorPKc
movl $1, 24(%rsp)
testb $31, %bpl
jne .L16
movl %ebp, %eax
shrl $5, %eax
.L17:
movl %ebp, %edx
shrl $4, %edx
.L19:
movl %edx, 28(%rsp)
movl %eax, 32(%rsp)
movl $16, 16(%rsp)
movl $8, 20(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebp, %eax
shrl $5, %eax
addl $1, %eax
testb $15, %bpl
je .L17
movl %ebp, %edx
shrl $4, %edx
addl $1, %edx
jmp .L19
.L23:
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z7j2d64ptPdS_iPdS_i
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size host_code, .-host_code
.section .rodata.str1.1
.LC3:
.string "_Z7j2d64ptPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7j2d64ptPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reordered-e.hip"
.globl _Z11check_errorPKc # -- Begin function _Z11check_errorPKc
.p2align 4, 0x90
.type _Z11check_errorPKc,@function
_Z11check_errorPKc: # @_Z11check_errorPKc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rbx, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
.cfi_endproc
# -- End function
.globl _Z22__device_stub__j2d64ptPdS_i # -- Begin function _Z22__device_stub__j2d64ptPdS_i
.p2align 4, 0x90
.type _Z22__device_stub__j2d64ptPdS_i,@function
_Z22__device_stub__j2d64ptPdS_i: # @_Z22__device_stub__j2d64ptPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7j2d64ptPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__j2d64ptPdS_i, .Lfunc_end1-_Z22__device_stub__j2d64ptPdS_i
.cfi_endproc
# -- End function
.globl host_code # -- Begin function host_code
.p2align 4, 0x90
.type host_code,@function
host_code: # @host_code
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
movslq %edx, %rbx
imulq %rbx, %rbx
shlq $3, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z11check_errorPKc.exit
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_Z11check_errorPKc.exit23
movl %ebp, %eax
shrl $4, %eax
leal 1(%rax), %ecx
testb $15, %bpl
cmovel %eax, %ecx
movl %ebp, %eax
shrl $5, %eax
leal 1(%rax), %edi
testb $31, %bpl
cmovel %eax, %edi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $34359738384, %rdx # imm = 0x800000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7j2d64ptPdS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 160
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.2, %esi
.LBB2_2:
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size host_code, .Lfunc_end2-host_code
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7j2d64ptPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error : %s, %s\n"
.size .L.str, 21
.type _Z7j2d64ptPdS_i,@object # @_Z7j2d64ptPdS_i
.section .rodata,"a",@progbits
.globl _Z7j2d64ptPdS_i
.p2align 3, 0x0
_Z7j2d64ptPdS_i:
.quad _Z22__device_stub__j2d64ptPdS_i
.size _Z7j2d64ptPdS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Failed to allocate device memory for in\n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate device memory for out\n"
.size .L.str.2, 42
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7j2d64ptPdS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__j2d64ptPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7j2d64ptPdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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