system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define _USE_MATH_DEFINES
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
void print_arr(int*, int, int);
void print_arr(double*, int, int);
double determinant(double* A, int n);
void adjoint(double* A, double* adj, int n);
bool inverse(double* A, double* inverse, int n);
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main() {
//Nodal coordinates
//-----------------
const int x[] = { 0, 6, 12, 18, 24, 18, 12, 6 };
const int y[] = { 0, 0, 0, 0, 0, 6, 6, 6 };
//Element connectivity(ECM)
// -------------------------
const int ECM[2][13] = { {0, 1, 2, 3, 4, 5, 6, 0, 1, 1, 2, 3, 3},
{1, 2, 3, 4, 5, 6, 7, 7, 7, 6, 6, 6, 5} };
//Material properites
//--------------------
const long E = 200 * (1000000);
//Geomatric properties
//---------------------
const double CArea[] = { .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012 }; //cross section area
const double L[] = { 6, 6, 6, 6, 6 * sqrt(2), 6, 6, 6 * sqrt(2), 6, 6 * sqrt(2), 6, 6 * sqrt(2), 6 };
//Additional input parameters required for coding
//-----------------------------------------------
const int nn = 8; //number of nodes
const int nel = 13; //number of el ements
const int nen = 2; //number of nodes in an element
const int ndof = 2; //number of dof per node
int tdof = nn*ndof;
double Ang[] = { 0, 0, 0, 0, M_PI / 4 * 3, M_PI, M_PI, M_PI / 4 , M_PI / 2, M_PI / 4, M_PI / 2, M_PI / 4 * 3, M_PI / 2 };
int LCM[2 * ndof][nel] = {}; //Local Coo matrix
double K[nn*ndof][nn*ndof] = {}; //Global stiffness matrix
//Restrained DOF to Apply BC
//---------------------------
int BC[] = { 1, 2, 10 }; //restrained dof
//Local coordinate matrix(LCM)
// -----------------------------
int ind;
for (int j = 0; j < nen; j++) {
for (int e = 0; e < nel; e++) {
for (int m = 0; m < ndof; m++) {
ind = j*ndof + m;
LCM[ind][e] = ndof*ECM[j][e] + m;
}
}
}
printf("LCM\n");
print_arr((int *)LCM, 2 * ndof, nel);
//Element local stiffness matrix ke
//---------------------------------
for (int k = 0; k < nel; k++) {
double c = cos(Ang[k]);
double s = sin(Ang[k]);
double const_ = CArea[k] * E / L[k];
double ke[4][4] = { {c*c, c*s, -c*c, -c*s},
{c*s, s*s, -c*s, -s*s},
{-c*c, -c*s, c*c, c*s},
{-c*s, -s*s, c*s, s*s} };
for (int i = 0; i < 4; i++)
for (int j = 0; j < 4; j++)
ke[i][j] = ke[i][j] * const_;
print_arr((double*)ke, 4, 4);
// Structure Global stiffenss matrix
// ---------------------------------
for (int loop1 = 0; loop1 < nen*ndof; loop1++) {
int i = LCM[loop1][k];
for (int loop2 = 0; loop2 < nen*ndof; loop2++) {
int j = LCM[loop2][k];
K[i][j] = K[i][j] + ke[loop1][loop2];
}
}
}
printf("K\n");
print_arr((double*)K, nn*ndof, nn*ndof);
//correct upto here
double Kf[nn*ndof][nn*ndof] = {};
for (int i = 0; i < nn*ndof; i++){
for (int j = 0; j < nn*ndof; j++) {
Kf[i][j] = K[i][j];
}
}
//int Kf[][] = K;
//Applying Boundary conditions
//----------------------------
for (int p = 0; p < sizeof(BC) / sizeof(BC[0]); p++) {
for (int q = 0; q < tdof; q++) {
K[BC[p]][ q] = 0;
}
K[BC[p]][ BC[p]] = 1;
}
//Force vector
//------------
double f[] = { 0, 0, 0, -200, 0, -100, 0, -100, 0, 0, 0, 0, 0, 0, 0, 0 };
//Displacement vector
//-------------------
const int z = 16;
double inv[z][z];
double tt[z][z];
for (int i = 0; i < z; i++) {
for (int j = 0; j < z; j++) {
tt[i][j] = (10 * ((float)rand() / RAND_MAX));
}
}
inverse((double*)tt, (double*)inv, z);
printf("inv\n");
print_arr((double*)inv, z,z);
//mat_mul(inv,f);
//d = K\f
//Reaction forces
//---------------
//mat_mul(Kf,d);
//fr = Kf*d
//Axial forces
//------------
/*
for (int e = 0; e < nel; e++) {
de = d[LCM[:, e]]; //displacement of the current element
const_ = CArea[e] * E / L[e]; //constant parameter with in the elementt
p = Ang[e];
c = cos(e);
force[e] = const_*{ -c, -s, c, s } *de;
}*/
/*
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
// Add vectors in parallel.
cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}*/
scanf("%d", &ind);
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
}
// Function to get cofactor of A[p][q] in temp[][]. n is current dimension of A[][]
void getCofactor(double* A, double* temp, int p, int q, int n){
int i = 0, j = 0;
// Looping for each element of the matrix
for (int row = 0; row < n; row++){
for (int col = 0; col < n; col++){
// Copying into temporary matrix only those element
// which are not in given row and column
if (row != p && col != q){
temp[i*n + j] = A[row*n + col];
j++;
// Row is filled, so increase row index and
// reset col index
if (j == n - 1){
j = 0;
i++;
}
}
}
}
}
/* Recursive function for finding determinant of matrix.
n is current dimension of A[][]. */
double determinant(double* A, int n){
double D = 0; // Initialize result
// Base case : if matrix contains single element
if (n == 1)
return A[0];
double* temp =(double*) malloc(sizeof(double)*n*n); // To store cofactors
int sign = 1; // To store sign multiplier
// Iterate for each element of first row
for (int f = 0; f < n; f++){
// Getting Cofactor of A[0][f]
getCofactor(A, temp, 0, f, n);
D += sign * A[0*n + f] * determinant(temp, n - 1);
// terms are to be added with alternate sign
sign = -sign;
}
free(temp);
return D;
}
// Function to get adjoint of A[N][N] in adj[N][N].
void adjoint(double* A, double* adj, int n){
if (n == 1){
adj[0] = 1;
return;
}
// temp is used to store cofactors of A[][]
int sign = 1;
double *temp = (double*) malloc(sizeof(double)*n*n);
for (int i = 0; i<n; i++){
for (int j = 0; j<n; j++){
// Get cofactor of A[i][j]
getCofactor(A, temp, i, j, n);
// sign of adj[j][i] positive if sum of row
// and column indexes is even.
sign = ((i + j) % 2 == 0) ? 1 : -1;
// Interchanging rows and columns to get the
// transpose of the cofactor matrix
adj[j*n + i] = (sign)*(determinant(temp, n - 1));
}
}
free(temp);
}
// Function to calculate and store inverse, returns false if
// matrix is singular
bool inverse(double* A, double* inverse, int n){
// Find determinant of A[][]
double det = determinant(A, n);
printf("%lf\n", det);
if (det < (double)1e-6 && det > -(double)1e-6){
//cout << "Singular matrix, can't find its inverse";
return false;
}
// Find adjoint
double* adj = (double*)malloc(sizeof(double)*n*n);
adjoint(A, adj,n);
// Find Inverse using formula "inverse(A) = adj(A)/det(A)"
for (int i = 0; i<n; i++)
for (int j = 0; j<n; j++)
inverse[i*n + j] = adj[i*n + j] / double(det);
free(adj);
return true;
}
void print_arr(int *arr, int m, int n) {
int i, j;
for (i = 0; i < m; i++) {
for (j = 0; j < n; j++)
printf("%d ", *((arr + i*n) + j));
printf("\n");
}
}
void print_arr(double *arr, int m, int n) {
int i, j;
for (i = 0; i < m; i++) {
for (j = 0; j < n; j++)
printf("%lf ", *((arr + i*n) + j));
printf("\n");
}
} | code for sm_80
Function : _Z9addKernelPiPKiS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define _USE_MATH_DEFINES
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
void print_arr(int*, int, int);
void print_arr(double*, int, int);
double determinant(double* A, int n);
void adjoint(double* A, double* adj, int n);
bool inverse(double* A, double* inverse, int n);
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main() {
//Nodal coordinates
//-----------------
const int x[] = { 0, 6, 12, 18, 24, 18, 12, 6 };
const int y[] = { 0, 0, 0, 0, 0, 6, 6, 6 };
//Element connectivity(ECM)
// -------------------------
const int ECM[2][13] = { {0, 1, 2, 3, 4, 5, 6, 0, 1, 1, 2, 3, 3},
{1, 2, 3, 4, 5, 6, 7, 7, 7, 6, 6, 6, 5} };
//Material properites
//--------------------
const long E = 200 * (1000000);
//Geomatric properties
//---------------------
const double CArea[] = { .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012 }; //cross section area
const double L[] = { 6, 6, 6, 6, 6 * sqrt(2), 6, 6, 6 * sqrt(2), 6, 6 * sqrt(2), 6, 6 * sqrt(2), 6 };
//Additional input parameters required for coding
//-----------------------------------------------
const int nn = 8; //number of nodes
const int nel = 13; //number of el ements
const int nen = 2; //number of nodes in an element
const int ndof = 2; //number of dof per node
int tdof = nn*ndof;
double Ang[] = { 0, 0, 0, 0, M_PI / 4 * 3, M_PI, M_PI, M_PI / 4 , M_PI / 2, M_PI / 4, M_PI / 2, M_PI / 4 * 3, M_PI / 2 };
int LCM[2 * ndof][nel] = {}; //Local Coo matrix
double K[nn*ndof][nn*ndof] = {}; //Global stiffness matrix
//Restrained DOF to Apply BC
//---------------------------
int BC[] = { 1, 2, 10 }; //restrained dof
//Local coordinate matrix(LCM)
// -----------------------------
int ind;
for (int j = 0; j < nen; j++) {
for (int e = 0; e < nel; e++) {
for (int m = 0; m < ndof; m++) {
ind = j*ndof + m;
LCM[ind][e] = ndof*ECM[j][e] + m;
}
}
}
printf("LCM\n");
print_arr((int *)LCM, 2 * ndof, nel);
//Element local stiffness matrix ke
//---------------------------------
for (int k = 0; k < nel; k++) {
double c = cos(Ang[k]);
double s = sin(Ang[k]);
double const_ = CArea[k] * E / L[k];
double ke[4][4] = { {c*c, c*s, -c*c, -c*s},
{c*s, s*s, -c*s, -s*s},
{-c*c, -c*s, c*c, c*s},
{-c*s, -s*s, c*s, s*s} };
for (int i = 0; i < 4; i++)
for (int j = 0; j < 4; j++)
ke[i][j] = ke[i][j] * const_;
print_arr((double*)ke, 4, 4);
// Structure Global stiffenss matrix
// ---------------------------------
for (int loop1 = 0; loop1 < nen*ndof; loop1++) {
int i = LCM[loop1][k];
for (int loop2 = 0; loop2 < nen*ndof; loop2++) {
int j = LCM[loop2][k];
K[i][j] = K[i][j] + ke[loop1][loop2];
}
}
}
printf("K\n");
print_arr((double*)K, nn*ndof, nn*ndof);
//correct upto here
double Kf[nn*ndof][nn*ndof] = {};
for (int i = 0; i < nn*ndof; i++){
for (int j = 0; j < nn*ndof; j++) {
Kf[i][j] = K[i][j];
}
}
//int Kf[][] = K;
//Applying Boundary conditions
//----------------------------
for (int p = 0; p < sizeof(BC) / sizeof(BC[0]); p++) {
for (int q = 0; q < tdof; q++) {
K[BC[p]][ q] = 0;
}
K[BC[p]][ BC[p]] = 1;
}
//Force vector
//------------
double f[] = { 0, 0, 0, -200, 0, -100, 0, -100, 0, 0, 0, 0, 0, 0, 0, 0 };
//Displacement vector
//-------------------
const int z = 16;
double inv[z][z];
double tt[z][z];
for (int i = 0; i < z; i++) {
for (int j = 0; j < z; j++) {
tt[i][j] = (10 * ((float)rand() / RAND_MAX));
}
}
inverse((double*)tt, (double*)inv, z);
printf("inv\n");
print_arr((double*)inv, z,z);
//mat_mul(inv,f);
//d = K\f
//Reaction forces
//---------------
//mat_mul(Kf,d);
//fr = Kf*d
//Axial forces
//------------
/*
for (int e = 0; e < nel; e++) {
de = d[LCM[:, e]]; //displacement of the current element
const_ = CArea[e] * E / L[e]; //constant parameter with in the elementt
p = Ang[e];
c = cos(e);
force[e] = const_*{ -c, -s, c, s } *de;
}*/
/*
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
// Add vectors in parallel.
cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}*/
scanf("%d", &ind);
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
}
// Function to get cofactor of A[p][q] in temp[][]. n is current dimension of A[][]
void getCofactor(double* A, double* temp, int p, int q, int n){
int i = 0, j = 0;
// Looping for each element of the matrix
for (int row = 0; row < n; row++){
for (int col = 0; col < n; col++){
// Copying into temporary matrix only those element
// which are not in given row and column
if (row != p && col != q){
temp[i*n + j] = A[row*n + col];
j++;
// Row is filled, so increase row index and
// reset col index
if (j == n - 1){
j = 0;
i++;
}
}
}
}
}
/* Recursive function for finding determinant of matrix.
n is current dimension of A[][]. */
double determinant(double* A, int n){
double D = 0; // Initialize result
// Base case : if matrix contains single element
if (n == 1)
return A[0];
double* temp =(double*) malloc(sizeof(double)*n*n); // To store cofactors
int sign = 1; // To store sign multiplier
// Iterate for each element of first row
for (int f = 0; f < n; f++){
// Getting Cofactor of A[0][f]
getCofactor(A, temp, 0, f, n);
D += sign * A[0*n + f] * determinant(temp, n - 1);
// terms are to be added with alternate sign
sign = -sign;
}
free(temp);
return D;
}
// Function to get adjoint of A[N][N] in adj[N][N].
void adjoint(double* A, double* adj, int n){
if (n == 1){
adj[0] = 1;
return;
}
// temp is used to store cofactors of A[][]
int sign = 1;
double *temp = (double*) malloc(sizeof(double)*n*n);
for (int i = 0; i<n; i++){
for (int j = 0; j<n; j++){
// Get cofactor of A[i][j]
getCofactor(A, temp, i, j, n);
// sign of adj[j][i] positive if sum of row
// and column indexes is even.
sign = ((i + j) % 2 == 0) ? 1 : -1;
// Interchanging rows and columns to get the
// transpose of the cofactor matrix
adj[j*n + i] = (sign)*(determinant(temp, n - 1));
}
}
free(temp);
}
// Function to calculate and store inverse, returns false if
// matrix is singular
bool inverse(double* A, double* inverse, int n){
// Find determinant of A[][]
double det = determinant(A, n);
printf("%lf\n", det);
if (det < (double)1e-6 && det > -(double)1e-6){
//cout << "Singular matrix, can't find its inverse";
return false;
}
// Find adjoint
double* adj = (double*)malloc(sizeof(double)*n*n);
adjoint(A, adj,n);
// Find Inverse using formula "inverse(A) = adj(A)/det(A)"
for (int i = 0; i<n; i++)
for (int j = 0; j<n; j++)
inverse[i*n + j] = adj[i*n + j] / double(det);
free(adj);
return true;
}
void print_arr(int *arr, int m, int n) {
int i, j;
for (i = 0; i < m; i++) {
for (j = 0; j < n; j++)
printf("%d ", *((arr + i*n) + j));
printf("\n");
}
}
void print_arr(double *arr, int m, int n) {
int i, j;
for (i = 0; i < m; i++) {
for (j = 0; j < n; j++)
printf("%lf ", *((arr + i*n) + j));
printf("\n");
}
} | .file "tmpxft_000ae7ae_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3680:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3680:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11getCofactorPdS_iii
.type _Z11getCofactorPdS_iii, @function
_Z11getCofactorPdS_iii:
.LFB3672:
.cfi_startproc
endbr64
testl %r8d, %r8d
jle .L10
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %r11
movq %rsi, %rbx
movl %edx, %edi
movl %ecx, %r10d
movl $0, %ebp
movl $0, %esi
movl $0, %ecx
movl $0, %r9d
movl $0, %r13d
leal -1(%r8), %r12d
jmp .L5
.L6:
leal 1(%rax), %edx
cmpl %edx, %r8d
je .L13
movl %edx, %eax
.L7:
cmpl %esi, %edi
je .L6
cmpl %eax, %r10d
je .L6
leal (%rax,%rbp), %edx
movslq %edx, %rdx
movsd (%r11,%rdx,8), %xmm0
movl %r8d, %edx
imull %r9d, %edx
addl %ecx, %edx
movslq %edx, %rdx
movsd %xmm0, (%rbx,%rdx,8)
addl $1, %ecx
cmpl %ecx, %r12d
jne .L6
addl $1, %r9d
movl $0, %ecx
jmp .L6
.L13:
leal 1(%rsi), %edx
addl %r8d, %ebp
cmpl %eax, %esi
je .L3
movl %edx, %esi
.L5:
movl %r13d, %eax
jmp .L7
.L3:
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE3672:
.size _Z11getCofactorPdS_iii, .-_Z11getCofactorPdS_iii
.globl _Z11determinantPdi
.type _Z11determinantPdi, @function
_Z11determinantPdi:
.LFB3673:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
cmpl $1, %esi
je .L22
movl %esi, %ebp
movslq %esi, %r15
movq %r15, %rdi
imulq %r15, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %r14
movq $0x000000000, 8(%rsp)
testl %ebp, %ebp
jle .L17
movl $0, %ebx
movl $1, %r13d
leal -1(%rbp), %eax
movl %eax, 28(%rsp)
.L18:
movl %ebp, %r8d
movl %ebx, %ecx
movl $0, %edx
movq %r14, %rsi
movq %r12, %rdi
call _Z11getCofactorPdS_iii
pxor %xmm0, %xmm0
cvtsi2sdl %r13d, %xmm0
mulsd (%r12,%rbx,8), %xmm0
movsd %xmm0, 16(%rsp)
movl 28(%rsp), %esi
movq %r14, %rdi
call _Z11determinantPdi
mulsd 16(%rsp), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
negl %r13d
addq $1, %rbx
cmpq %rbx, %r15
jne .L18
.L17:
movq %r14, %rdi
call free@PLT
.L14:
movsd 8(%rsp), %xmm0
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movsd (%rdi), %xmm3
movsd %xmm3, 8(%rsp)
jmp .L14
.cfi_endproc
.LFE3673:
.size _Z11determinantPdi, .-_Z11determinantPdi
.globl _Z7adjointPdS_i
.type _Z7adjointPdS_i, @function
_Z7adjointPdS_i:
.LFB3674:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 16(%rsp)
movq %rsi, 48(%rsp)
cmpl $1, %edx
je .L34
movl %edx, %r12d
movslq %edx, %rdi
movq %rdi, %rbx
movq %rdi, 56(%rsp)
imulq %rdi, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %r13
testl %r12d, %r12d
jle .L26
leaq 0(,%rbx,8), %rax
movq %rax, 24(%rsp)
movl $0, %edx
leal -1(%r12), %eax
movl %eax, 36(%rsp)
.L27:
movl %edx, %r15d
movl %edx, %r14d
movq 48(%rsp), %rax
leaq (%rax,%rdx,8), %rbp
movl $0, %ebx
movq %rdx, 40(%rsp)
.L29:
movl %r12d, %r8d
movl %ebx, %ecx
movl %r14d, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call _Z11getCofactorPdS_iii
leal (%rbx,%r15), %eax
andl $1, %eax
negl %eax
sbbl %eax, %eax
orl $1, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd %xmm1, 8(%rsp)
movl 36(%rsp), %esi
movq %r13, %rdi
call _Z11determinantPdi
mulsd 8(%rsp), %xmm0
movsd %xmm0, 0(%rbp)
addl $1, %ebx
movq 24(%rsp), %rax
addq %rax, %rbp
cmpl %ebx, %r12d
jne .L29
movq 40(%rsp), %rdx
addq $1, %rdx
cmpq %rdx, 56(%rsp)
jne .L27
.L26:
movq %r13, %rdi
call free@PLT
.L23:
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq .LC1(%rip), %rcx
movq %rcx, (%rsi)
jmp .L23
.cfi_endproc
.LFE3674:
.size _Z7adjointPdS_i, .-_Z7adjointPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%lf\n"
.text
.globl _Z7inversePdS_i
.type _Z7inversePdS_i, @function
_Z7inversePdS_i:
.LFB3675:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r14
movq %rsi, %rbp
movl %edx, %r12d
movl %edx, %esi
call _Z11determinantPdi
movsd %xmm0, 8(%rsp)
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC3(%rip), %xmm0
movsd 8(%rsp), %xmm2
comisd %xmm2, %xmm0
jbe .L36
movl $0, %eax
comisd .LC4(%rip), %xmm2
ja .L35
.L36:
movslq %r12d, %r13
movq %r13, %rdi
imulq %r13, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %rbx
movl %r12d, %edx
movq %rax, %rsi
movq %r14, %rdi
call _Z7adjointPdS_i
testl %r12d, %r12d
jle .L39
leaq 0(,%r13,8), %rdi
negq %r13
leaq 0(,%r13,8), %rsi
movq %rdi, %rdx
movl $0, %ecx
.L40:
leaq (%rdx,%rsi), %rax
.L41:
movsd (%rbx,%rax), %xmm0
divsd 8(%rsp), %xmm0
movsd %xmm0, 0(%rbp,%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L41
addl $1, %ecx
addq %rdi, %rdx
cmpl %ecx, %r12d
jne .L40
.L39:
movq %rbx, %rdi
call free@PLT
movl $1, %eax
.L35:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _Z7inversePdS_i, .-_Z7inversePdS_i
.section .rodata.str1.1
.LC5:
.string "%d "
.LC6:
.string "\n"
.text
.globl _Z9print_arrPiii
.type _Z9print_arrPiii, @function
_Z9print_arrPiii:
.LFB3676:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L46
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC5(%rip), %r12
jmp .L48
.L50:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rsi
addq %rsi, %rax
leaq (%rcx,%rax,4), %rbp
.L49:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L49
.L51:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L46
.L48:
testl %r15d, %r15d
jg .L50
jmp .L51
.L46:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _Z9print_arrPiii, .-_Z9print_arrPiii
.section .rodata.str1.1
.LC7:
.string "%lf "
.text
.globl _Z9print_arrPdii
.type _Z9print_arrPdii, @function
_Z9print_arrPdii:
.LFB3677:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L54
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC7(%rip), %r12
jmp .L56
.L58:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,8), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,8), %rbp
.L57:
movsd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L57
.L59:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L54
.L56:
testl %r15d, %r15d
jg .L58
jmp .L59
.L54:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _Z9print_arrPdii, .-_Z9print_arrPdii
.section .rodata.str1.1
.LC15:
.string "LCM\n"
.LC18:
.string "K\n"
.LC21:
.string "inv\n"
.LC22:
.string "%d"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $4096, %rsp
.cfi_def_cfa_offset 4152
orq $0, (%rsp)
subq $2760, %rsp
.cfi_def_cfa_offset 6912
movq %fs:40, %rax
movq %rax, 6840(%rsp)
xorl %eax, %eax
movl $0, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 40(%rsp)
movl $3, 44(%rsp)
movl $4, 48(%rsp)
movl $5, 52(%rsp)
movl $6, 56(%rsp)
movl $0, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $2, 72(%rsp)
movl $3, 76(%rsp)
movl $3, 80(%rsp)
movl $1, 84(%rsp)
movl $2, 88(%rsp)
movl $3, 92(%rsp)
movl $4, 96(%rsp)
movl $5, 100(%rsp)
movl $6, 104(%rsp)
movl $7, 108(%rsp)
movl $7, 112(%rsp)
movl $7, 116(%rsp)
movl $6, 120(%rsp)
movl $6, 124(%rsp)
movl $6, 128(%rsp)
movl $5, 132(%rsp)
movsd .LC8(%rip), %xmm0
movsd %xmm0, 144(%rsp)
movsd %xmm0, 152(%rsp)
movsd %xmm0, 160(%rsp)
movsd %xmm0, 168(%rsp)
movsd %xmm0, 176(%rsp)
movsd %xmm0, 184(%rsp)
movsd %xmm0, 192(%rsp)
movsd %xmm0, 200(%rsp)
movsd %xmm0, 208(%rsp)
movsd %xmm0, 216(%rsp)
movsd %xmm0, 224(%rsp)
movsd %xmm0, 232(%rsp)
movsd %xmm0, 240(%rsp)
movsd .LC9(%rip), %xmm0
movsd %xmm0, 256(%rsp)
movsd %xmm0, 264(%rsp)
movsd %xmm0, 272(%rsp)
movsd %xmm0, 280(%rsp)
movsd .LC10(%rip), %xmm1
movsd %xmm1, 288(%rsp)
movsd %xmm0, 296(%rsp)
movsd %xmm0, 304(%rsp)
movsd %xmm1, 312(%rsp)
movsd %xmm0, 320(%rsp)
movsd %xmm1, 328(%rsp)
movsd %xmm0, 336(%rsp)
movsd %xmm1, 344(%rsp)
movsd %xmm0, 352(%rsp)
movq $0x000000000, 368(%rsp)
movq $0x000000000, 376(%rsp)
movq $0x000000000, 384(%rsp)
movq $0x000000000, 392(%rsp)
movsd .LC11(%rip), %xmm1
movsd %xmm1, 400(%rsp)
movsd .LC12(%rip), %xmm0
movsd %xmm0, 408(%rsp)
movsd %xmm0, 416(%rsp)
movsd .LC13(%rip), %xmm2
movsd %xmm2, 424(%rsp)
movsd .LC14(%rip), %xmm0
movsd %xmm0, 432(%rsp)
movsd %xmm2, 440(%rsp)
movsd %xmm0, 448(%rsp)
movsd %xmm1, 456(%rsp)
movsd %xmm0, 464(%rsp)
leaq 480(%rsp), %rdi
movl $26, %ecx
rep stosq
leaq 688(%rsp), %rdi
movl $256, %ecx
rep stosq
movl $1, 20(%rsp)
movl $2, 24(%rsp)
movl $10, 28(%rsp)
leaq 32(%rsp), %rcx
leaq 532(%rsp), %rdx
leaq 84(%rsp), %rsi
.L63:
movl (%rcx), %eax
addl %eax, %eax
movl %eax, -52(%rdx)
addl $1, %eax
movl %eax, (%rdx)
addq $4, %rcx
addq $4, %rdx
cmpq %rsi, %rcx
jne .L63
leaq 84(%rsp), %rcx
leaq 480(%rsp), %r13
leaq 636(%rsp), %rdx
leaq 688(%rsp), %rbx
.L64:
movl (%rcx), %eax
addl %eax, %eax
movl %eax, -52(%rdx)
addl $1, %eax
movl %eax, (%rdx)
addq $4, %rcx
addq $4, %rdx
cmpq %rbx, %rdx
jne .L64
movl $3, 16(%rsp)
movl %eax, 684(%rsp)
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 480(%rsp), %rdi
movl $13, %edx
movl $4, %esi
call _Z9print_arrPiii
addq $260, %r13
movl $0, %r12d
leaq 8(%rsp), %r15
movq %rsp, %r14
jmp .L70
.L88:
addq $4, %rbx
addq $8, %r12
cmpq %rbx, %r13
je .L87
.L70:
movsd 368(%rsp,%r12), %xmm0
movq %r14, %rsi
movq %r15, %rdi
call sincos@PLT
movsd (%rsp), %xmm0
movsd 8(%rsp), %xmm2
movsd .LC16(%rip), %xmm1
mulsd 144(%rsp,%r12), %xmm1
divsd 256(%rsp,%r12), %xmm1
movapd %xmm0, %xmm4
mulsd %xmm0, %xmm4
movsd %xmm4, 4784(%rsp)
mulsd %xmm2, %xmm0
movsd %xmm0, 4792(%rsp)
movapd %xmm4, %xmm6
xorpd .LC17(%rip), %xmm6
movsd %xmm6, 4800(%rsp)
movapd %xmm0, %xmm3
xorpd .LC17(%rip), %xmm3
movsd %xmm3, 4808(%rsp)
movsd %xmm0, 4816(%rsp)
mulsd %xmm2, %xmm2
movsd %xmm2, 4824(%rsp)
movsd %xmm3, 4832(%rsp)
movapd %xmm2, %xmm5
xorpd .LC17(%rip), %xmm5
movsd %xmm5, 4840(%rsp)
movsd %xmm6, 4848(%rsp)
movsd %xmm3, 4856(%rsp)
movsd %xmm4, 4864(%rsp)
movsd %xmm0, 4872(%rsp)
movsd %xmm3, 4880(%rsp)
movsd %xmm5, 4888(%rsp)
movsd %xmm0, 4896(%rsp)
movsd %xmm2, 4904(%rsp)
leaq 4784(%rsp), %rbp
leaq 4816(%rsp), %rdx
leaq 4944(%rsp), %rcx
.L65:
leaq -32(%rdx), %rax
.L66:
movapd %xmm1, %xmm0
mulsd (%rax), %xmm0
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rax, %rdx
jne .L66
addq $32, %rdx
cmpq %rdx, %rcx
jne .L65
leaq 4784(%rsp), %rdi
movl $4, %edx
movl $4, %esi
call _Z9print_arrPdii
leaq -208(%rbx), %r8
leaq 128(%rbp), %r9
movq %r8, %rdi
.L69:
movq %rbp, %rcx
movq %r8, %rdx
movslq (%rdi), %rsi
salq $4, %rsi
.L68:
movslq (%rdx), %rax
addq %rsi, %rax
movsd 688(%rsp,%rax,8), %xmm0
addsd (%rcx), %xmm0
movsd %xmm0, 688(%rsp,%rax,8)
addq $52, %rdx
addq $8, %rcx
cmpq %rdx, %rbx
jne .L68
addq $52, %rdi
addq $32, %rbp
cmpq %rbp, %r9
jne .L69
jmp .L88
.L87:
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 688(%rsp), %rdi
movl $16, %edx
movl $16, %esi
call _Z9print_arrPdii
leaq 20(%rsp), %rsi
leaq 32(%rsp), %r9
leaq 688(%rsp), %r8
leaq 816(%rsp), %rdi
movsd .LC1(%rip), %xmm0
.L71:
movl (%rsi), %ecx
movslq %ecx, %rdx
salq $7, %rdx
leaq (%r8,%rdx), %rax
addq %rdi, %rdx
.L72:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rax, %rdx
jne .L72
movslq %ecx, %rcx
movq %rcx, %rax
salq $4, %rax
addq %rcx, %rax
movsd %xmm0, 688(%rsp,%rax,8)
addq $4, %rsi
cmpq %rsi, %r9
jne .L71
leaq 4912(%rsp), %rbp
leaq 6960(%rsp), %r12
.L73:
leaq -128(%rbp), %rbx
.L74:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC19(%rip), %xmm0
mulss .LC20(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L74
subq $-128, %rbp
cmpq %rbp, %r12
jne .L73
leaq 2736(%rsp), %rbx
leaq 4784(%rsp), %rdi
movl $16, %edx
movq %rbx, %rsi
call _Z7inversePdS_i
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %edx
movl $16, %esi
movq %rbx, %rdi
call _Z9print_arrPdii
leaq 16(%rsp), %rsi
leaq .LC22(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq 6840(%rsp), %rax
subq %fs:40, %rax
jne .L89
movl $0, %eax
addq $6856, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L89:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.globl _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.type _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, @function
_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_:
.LFB3702:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L94
.L90:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L95
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L94:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiPKiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L90
.L95:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, .-_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.globl _Z9addKernelPiPKiS1_
.type _Z9addKernelPiPKiS1_, @function
_Z9addKernelPiPKiS1_:
.LFB3703:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _Z9addKernelPiPKiS1_, .-_Z9addKernelPiPKiS1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC23:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1
.LC24:
.string "cudaMalloc failed!"
.LC25:
.string "cudaMemcpy failed!"
.LC26:
.string "addKernel launch failed: %s\n"
.section .rodata.str1.8
.align 8
.LC27:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.text
.globl _Z11addWithCudaPiPKiS1_j
.type _Z11addWithCudaPiPKiS1_j, @function
_Z11addWithCudaPiPKiS1_j:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L111
movl %ebp, %r15d
salq $2, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L112
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L113
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L114
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L115
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L116
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L117
.L106:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L118
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L119
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L100
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L100
.L111:
movl %eax, %ebx
leaq .LC23(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L100:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L120
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L112:
.cfi_restore_state
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L100
.L113:
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L100
.L114:
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L100
.L115:
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L100
.L116:
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L100
.L117:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
jmp .L106
.L118:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC26(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L100
.L119:
movl %eax, %ecx
leaq .LC27(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L100
.L120:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size _Z11addWithCudaPiPKiS1_j, .-_Z11addWithCudaPiPKiS1_j
.section .rodata.str1.1
.LC28:
.string "_Z9addKernelPiPKiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3705:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKiS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC3:
.long -1598689907
.long 1051772663
.align 8
.LC4:
.long -1598689907
.long -1095710985
.align 8
.LC8:
.long 810889825
.long 1062447402
.align 8
.LC9:
.long 0
.long 1075314688
.align 8
.LC10:
.long -857772838
.long 1075902582
.align 8
.LC11:
.long 2134057426
.long 1073928572
.align 8
.LC12:
.long 1413754136
.long 1074340347
.align 8
.LC13:
.long 1413754136
.long 1072243195
.align 8
.LC14:
.long 1413754136
.long 1073291771
.align 8
.LC16:
.long 0
.long 1101518724
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC17:
.long 0
.long -2147483648
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC19:
.long 805306368
.align 4
.LC20:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define _USE_MATH_DEFINES
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
void print_arr(int*, int, int);
void print_arr(double*, int, int);
double determinant(double* A, int n);
void adjoint(double* A, double* adj, int n);
bool inverse(double* A, double* inverse, int n);
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main() {
//Nodal coordinates
//-----------------
const int x[] = { 0, 6, 12, 18, 24, 18, 12, 6 };
const int y[] = { 0, 0, 0, 0, 0, 6, 6, 6 };
//Element connectivity(ECM)
// -------------------------
const int ECM[2][13] = { {0, 1, 2, 3, 4, 5, 6, 0, 1, 1, 2, 3, 3},
{1, 2, 3, 4, 5, 6, 7, 7, 7, 6, 6, 6, 5} };
//Material properites
//--------------------
const long E = 200 * (1000000);
//Geomatric properties
//---------------------
const double CArea[] = { .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012 }; //cross section area
const double L[] = { 6, 6, 6, 6, 6 * sqrt(2), 6, 6, 6 * sqrt(2), 6, 6 * sqrt(2), 6, 6 * sqrt(2), 6 };
//Additional input parameters required for coding
//-----------------------------------------------
const int nn = 8; //number of nodes
const int nel = 13; //number of el ements
const int nen = 2; //number of nodes in an element
const int ndof = 2; //number of dof per node
int tdof = nn*ndof;
double Ang[] = { 0, 0, 0, 0, M_PI / 4 * 3, M_PI, M_PI, M_PI / 4 , M_PI / 2, M_PI / 4, M_PI / 2, M_PI / 4 * 3, M_PI / 2 };
int LCM[2 * ndof][nel] = {}; //Local Coo matrix
double K[nn*ndof][nn*ndof] = {}; //Global stiffness matrix
//Restrained DOF to Apply BC
//---------------------------
int BC[] = { 1, 2, 10 }; //restrained dof
//Local coordinate matrix(LCM)
// -----------------------------
int ind;
for (int j = 0; j < nen; j++) {
for (int e = 0; e < nel; e++) {
for (int m = 0; m < ndof; m++) {
ind = j*ndof + m;
LCM[ind][e] = ndof*ECM[j][e] + m;
}
}
}
printf("LCM\n");
print_arr((int *)LCM, 2 * ndof, nel);
//Element local stiffness matrix ke
//---------------------------------
for (int k = 0; k < nel; k++) {
double c = cos(Ang[k]);
double s = sin(Ang[k]);
double const_ = CArea[k] * E / L[k];
double ke[4][4] = { {c*c, c*s, -c*c, -c*s},
{c*s, s*s, -c*s, -s*s},
{-c*c, -c*s, c*c, c*s},
{-c*s, -s*s, c*s, s*s} };
for (int i = 0; i < 4; i++)
for (int j = 0; j < 4; j++)
ke[i][j] = ke[i][j] * const_;
print_arr((double*)ke, 4, 4);
// Structure Global stiffenss matrix
// ---------------------------------
for (int loop1 = 0; loop1 < nen*ndof; loop1++) {
int i = LCM[loop1][k];
for (int loop2 = 0; loop2 < nen*ndof; loop2++) {
int j = LCM[loop2][k];
K[i][j] = K[i][j] + ke[loop1][loop2];
}
}
}
printf("K\n");
print_arr((double*)K, nn*ndof, nn*ndof);
//correct upto here
double Kf[nn*ndof][nn*ndof] = {};
for (int i = 0; i < nn*ndof; i++){
for (int j = 0; j < nn*ndof; j++) {
Kf[i][j] = K[i][j];
}
}
//int Kf[][] = K;
//Applying Boundary conditions
//----------------------------
for (int p = 0; p < sizeof(BC) / sizeof(BC[0]); p++) {
for (int q = 0; q < tdof; q++) {
K[BC[p]][ q] = 0;
}
K[BC[p]][ BC[p]] = 1;
}
//Force vector
//------------
double f[] = { 0, 0, 0, -200, 0, -100, 0, -100, 0, 0, 0, 0, 0, 0, 0, 0 };
//Displacement vector
//-------------------
const int z = 16;
double inv[z][z];
double tt[z][z];
for (int i = 0; i < z; i++) {
for (int j = 0; j < z; j++) {
tt[i][j] = (10 * ((float)rand() / RAND_MAX));
}
}
inverse((double*)tt, (double*)inv, z);
printf("inv\n");
print_arr((double*)inv, z,z);
//mat_mul(inv,f);
//d = K\f
//Reaction forces
//---------------
//mat_mul(Kf,d);
//fr = Kf*d
//Axial forces
//------------
/*
for (int e = 0; e < nel; e++) {
de = d[LCM[:, e]]; //displacement of the current element
const_ = CArea[e] * E / L[e]; //constant parameter with in the elementt
p = Ang[e];
c = cos(e);
force[e] = const_*{ -c, -s, c, s } *de;
}*/
/*
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
// Add vectors in parallel.
cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}*/
scanf("%d", &ind);
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
}
// Function to get cofactor of A[p][q] in temp[][]. n is current dimension of A[][]
void getCofactor(double* A, double* temp, int p, int q, int n){
int i = 0, j = 0;
// Looping for each element of the matrix
for (int row = 0; row < n; row++){
for (int col = 0; col < n; col++){
// Copying into temporary matrix only those element
// which are not in given row and column
if (row != p && col != q){
temp[i*n + j] = A[row*n + col];
j++;
// Row is filled, so increase row index and
// reset col index
if (j == n - 1){
j = 0;
i++;
}
}
}
}
}
/* Recursive function for finding determinant of matrix.
n is current dimension of A[][]. */
double determinant(double* A, int n){
double D = 0; // Initialize result
// Base case : if matrix contains single element
if (n == 1)
return A[0];
double* temp =(double*) malloc(sizeof(double)*n*n); // To store cofactors
int sign = 1; // To store sign multiplier
// Iterate for each element of first row
for (int f = 0; f < n; f++){
// Getting Cofactor of A[0][f]
getCofactor(A, temp, 0, f, n);
D += sign * A[0*n + f] * determinant(temp, n - 1);
// terms are to be added with alternate sign
sign = -sign;
}
free(temp);
return D;
}
// Function to get adjoint of A[N][N] in adj[N][N].
void adjoint(double* A, double* adj, int n){
if (n == 1){
adj[0] = 1;
return;
}
// temp is used to store cofactors of A[][]
int sign = 1;
double *temp = (double*) malloc(sizeof(double)*n*n);
for (int i = 0; i<n; i++){
for (int j = 0; j<n; j++){
// Get cofactor of A[i][j]
getCofactor(A, temp, i, j, n);
// sign of adj[j][i] positive if sum of row
// and column indexes is even.
sign = ((i + j) % 2 == 0) ? 1 : -1;
// Interchanging rows and columns to get the
// transpose of the cofactor matrix
adj[j*n + i] = (sign)*(determinant(temp, n - 1));
}
}
free(temp);
}
// Function to calculate and store inverse, returns false if
// matrix is singular
bool inverse(double* A, double* inverse, int n){
// Find determinant of A[][]
double det = determinant(A, n);
printf("%lf\n", det);
if (det < (double)1e-6 && det > -(double)1e-6){
//cout << "Singular matrix, can't find its inverse";
return false;
}
// Find adjoint
double* adj = (double*)malloc(sizeof(double)*n*n);
adjoint(A, adj,n);
// Find Inverse using formula "inverse(A) = adj(A)/det(A)"
for (int i = 0; i<n; i++)
for (int j = 0; j<n; j++)
inverse[i*n + j] = adj[i*n + j] / double(det);
free(adj);
return true;
}
void print_arr(int *arr, int m, int n) {
int i, j;
for (i = 0; i < m; i++) {
for (j = 0; j < n; j++)
printf("%d ", *((arr + i*n) + j));
printf("\n");
}
}
void print_arr(double *arr, int m, int n) {
int i, j;
for (i = 0; i < m; i++) {
for (j = 0; j < n; j++)
printf("%lf ", *((arr + i*n) + j));
printf("\n");
}
} | #define _USE_MATH_DEFINES
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
void print_arr(int*, int, int);
void print_arr(double*, int, int);
double determinant(double* A, int n);
void adjoint(double* A, double* adj, int n);
bool inverse(double* A, double* inverse, int n);
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main() {
//Nodal coordinates
//-----------------
const int x[] = { 0, 6, 12, 18, 24, 18, 12, 6 };
const int y[] = { 0, 0, 0, 0, 0, 6, 6, 6 };
//Element connectivity(ECM)
// -------------------------
const int ECM[2][13] = { {0, 1, 2, 3, 4, 5, 6, 0, 1, 1, 2, 3, 3},
{1, 2, 3, 4, 5, 6, 7, 7, 7, 6, 6, 6, 5} };
//Material properites
//--------------------
const long E = 200 * (1000000);
//Geomatric properties
//---------------------
const double CArea[] = { .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012 }; //cross section area
const double L[] = { 6, 6, 6, 6, 6 * sqrt(2), 6, 6, 6 * sqrt(2), 6, 6 * sqrt(2), 6, 6 * sqrt(2), 6 };
//Additional input parameters required for coding
//-----------------------------------------------
const int nn = 8; //number of nodes
const int nel = 13; //number of el ements
const int nen = 2; //number of nodes in an element
const int ndof = 2; //number of dof per node
int tdof = nn*ndof;
double Ang[] = { 0, 0, 0, 0, M_PI / 4 * 3, M_PI, M_PI, M_PI / 4 , M_PI / 2, M_PI / 4, M_PI / 2, M_PI / 4 * 3, M_PI / 2 };
int LCM[2 * ndof][nel] = {}; //Local Coo matrix
double K[nn*ndof][nn*ndof] = {}; //Global stiffness matrix
//Restrained DOF to Apply BC
//---------------------------
int BC[] = { 1, 2, 10 }; //restrained dof
//Local coordinate matrix(LCM)
// -----------------------------
int ind;
for (int j = 0; j < nen; j++) {
for (int e = 0; e < nel; e++) {
for (int m = 0; m < ndof; m++) {
ind = j*ndof + m;
LCM[ind][e] = ndof*ECM[j][e] + m;
}
}
}
printf("LCM\n");
print_arr((int *)LCM, 2 * ndof, nel);
//Element local stiffness matrix ke
//---------------------------------
for (int k = 0; k < nel; k++) {
double c = cos(Ang[k]);
double s = sin(Ang[k]);
double const_ = CArea[k] * E / L[k];
double ke[4][4] = { {c*c, c*s, -c*c, -c*s},
{c*s, s*s, -c*s, -s*s},
{-c*c, -c*s, c*c, c*s},
{-c*s, -s*s, c*s, s*s} };
for (int i = 0; i < 4; i++)
for (int j = 0; j < 4; j++)
ke[i][j] = ke[i][j] * const_;
print_arr((double*)ke, 4, 4);
// Structure Global stiffenss matrix
// ---------------------------------
for (int loop1 = 0; loop1 < nen*ndof; loop1++) {
int i = LCM[loop1][k];
for (int loop2 = 0; loop2 < nen*ndof; loop2++) {
int j = LCM[loop2][k];
K[i][j] = K[i][j] + ke[loop1][loop2];
}
}
}
printf("K\n");
print_arr((double*)K, nn*ndof, nn*ndof);
//correct upto here
double Kf[nn*ndof][nn*ndof] = {};
for (int i = 0; i < nn*ndof; i++){
for (int j = 0; j < nn*ndof; j++) {
Kf[i][j] = K[i][j];
}
}
//int Kf[][] = K;
//Applying Boundary conditions
//----------------------------
for (int p = 0; p < sizeof(BC) / sizeof(BC[0]); p++) {
for (int q = 0; q < tdof; q++) {
K[BC[p]][ q] = 0;
}
K[BC[p]][ BC[p]] = 1;
}
//Force vector
//------------
double f[] = { 0, 0, 0, -200, 0, -100, 0, -100, 0, 0, 0, 0, 0, 0, 0, 0 };
//Displacement vector
//-------------------
const int z = 16;
double inv[z][z];
double tt[z][z];
for (int i = 0; i < z; i++) {
for (int j = 0; j < z; j++) {
tt[i][j] = (10 * ((float)rand() / RAND_MAX));
}
}
inverse((double*)tt, (double*)inv, z);
printf("inv\n");
print_arr((double*)inv, z,z);
//mat_mul(inv,f);
//d = K\f
//Reaction forces
//---------------
//mat_mul(Kf,d);
//fr = Kf*d
//Axial forces
//------------
/*
for (int e = 0; e < nel; e++) {
de = d[LCM[:, e]]; //displacement of the current element
const_ = CArea[e] * E / L[e]; //constant parameter with in the elementt
p = Ang[e];
c = cos(e);
force[e] = const_*{ -c, -s, c, s } *de;
}*/
/*
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
// Add vectors in parallel.
cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}*/
scanf("%d", &ind);
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
}
// Function to get cofactor of A[p][q] in temp[][]. n is current dimension of A[][]
void getCofactor(double* A, double* temp, int p, int q, int n){
int i = 0, j = 0;
// Looping for each element of the matrix
for (int row = 0; row < n; row++){
for (int col = 0; col < n; col++){
// Copying into temporary matrix only those element
// which are not in given row and column
if (row != p && col != q){
temp[i*n + j] = A[row*n + col];
j++;
// Row is filled, so increase row index and
// reset col index
if (j == n - 1){
j = 0;
i++;
}
}
}
}
}
/* Recursive function for finding determinant of matrix.
n is current dimension of A[][]. */
double determinant(double* A, int n){
double D = 0; // Initialize result
// Base case : if matrix contains single element
if (n == 1)
return A[0];
double* temp =(double*) malloc(sizeof(double)*n*n); // To store cofactors
int sign = 1; // To store sign multiplier
// Iterate for each element of first row
for (int f = 0; f < n; f++){
// Getting Cofactor of A[0][f]
getCofactor(A, temp, 0, f, n);
D += sign * A[0*n + f] * determinant(temp, n - 1);
// terms are to be added with alternate sign
sign = -sign;
}
free(temp);
return D;
}
// Function to get adjoint of A[N][N] in adj[N][N].
void adjoint(double* A, double* adj, int n){
if (n == 1){
adj[0] = 1;
return;
}
// temp is used to store cofactors of A[][]
int sign = 1;
double *temp = (double*) malloc(sizeof(double)*n*n);
for (int i = 0; i<n; i++){
for (int j = 0; j<n; j++){
// Get cofactor of A[i][j]
getCofactor(A, temp, i, j, n);
// sign of adj[j][i] positive if sum of row
// and column indexes is even.
sign = ((i + j) % 2 == 0) ? 1 : -1;
// Interchanging rows and columns to get the
// transpose of the cofactor matrix
adj[j*n + i] = (sign)*(determinant(temp, n - 1));
}
}
free(temp);
}
// Function to calculate and store inverse, returns false if
// matrix is singular
bool inverse(double* A, double* inverse, int n){
// Find determinant of A[][]
double det = determinant(A, n);
printf("%lf\n", det);
if (det < (double)1e-6 && det > -(double)1e-6){
//cout << "Singular matrix, can't find its inverse";
return false;
}
// Find adjoint
double* adj = (double*)malloc(sizeof(double)*n*n);
adjoint(A, adj,n);
// Find Inverse using formula "inverse(A) = adj(A)/det(A)"
for (int i = 0; i<n; i++)
for (int j = 0; j<n; j++)
inverse[i*n + j] = adj[i*n + j] / double(det);
free(adj);
return true;
}
void print_arr(int *arr, int m, int n) {
int i, j;
for (i = 0; i < m; i++) {
for (j = 0; j < n; j++)
printf("%d ", *((arr + i*n) + j));
printf("\n");
}
}
void print_arr(double *arr, int m, int n) {
int i, j;
for (i = 0; i < m; i++) {
for (j = 0; j < n; j++)
printf("%lf ", *((arr + i*n) + j));
printf("\n");
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #define _USE_MATH_DEFINES
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
void print_arr(int*, int, int);
void print_arr(double*, int, int);
double determinant(double* A, int n);
void adjoint(double* A, double* adj, int n);
bool inverse(double* A, double* inverse, int n);
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main() {
//Nodal coordinates
//-----------------
const int x[] = { 0, 6, 12, 18, 24, 18, 12, 6 };
const int y[] = { 0, 0, 0, 0, 0, 6, 6, 6 };
//Element connectivity(ECM)
// -------------------------
const int ECM[2][13] = { {0, 1, 2, 3, 4, 5, 6, 0, 1, 1, 2, 3, 3},
{1, 2, 3, 4, 5, 6, 7, 7, 7, 6, 6, 6, 5} };
//Material properites
//--------------------
const long E = 200 * (1000000);
//Geomatric properties
//---------------------
const double CArea[] = { .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012, .0012 }; //cross section area
const double L[] = { 6, 6, 6, 6, 6 * sqrt(2), 6, 6, 6 * sqrt(2), 6, 6 * sqrt(2), 6, 6 * sqrt(2), 6 };
//Additional input parameters required for coding
//-----------------------------------------------
const int nn = 8; //number of nodes
const int nel = 13; //number of el ements
const int nen = 2; //number of nodes in an element
const int ndof = 2; //number of dof per node
int tdof = nn*ndof;
double Ang[] = { 0, 0, 0, 0, M_PI / 4 * 3, M_PI, M_PI, M_PI / 4 , M_PI / 2, M_PI / 4, M_PI / 2, M_PI / 4 * 3, M_PI / 2 };
int LCM[2 * ndof][nel] = {}; //Local Coo matrix
double K[nn*ndof][nn*ndof] = {}; //Global stiffness matrix
//Restrained DOF to Apply BC
//---------------------------
int BC[] = { 1, 2, 10 }; //restrained dof
//Local coordinate matrix(LCM)
// -----------------------------
int ind;
for (int j = 0; j < nen; j++) {
for (int e = 0; e < nel; e++) {
for (int m = 0; m < ndof; m++) {
ind = j*ndof + m;
LCM[ind][e] = ndof*ECM[j][e] + m;
}
}
}
printf("LCM\n");
print_arr((int *)LCM, 2 * ndof, nel);
//Element local stiffness matrix ke
//---------------------------------
for (int k = 0; k < nel; k++) {
double c = cos(Ang[k]);
double s = sin(Ang[k]);
double const_ = CArea[k] * E / L[k];
double ke[4][4] = { {c*c, c*s, -c*c, -c*s},
{c*s, s*s, -c*s, -s*s},
{-c*c, -c*s, c*c, c*s},
{-c*s, -s*s, c*s, s*s} };
for (int i = 0; i < 4; i++)
for (int j = 0; j < 4; j++)
ke[i][j] = ke[i][j] * const_;
print_arr((double*)ke, 4, 4);
// Structure Global stiffenss matrix
// ---------------------------------
for (int loop1 = 0; loop1 < nen*ndof; loop1++) {
int i = LCM[loop1][k];
for (int loop2 = 0; loop2 < nen*ndof; loop2++) {
int j = LCM[loop2][k];
K[i][j] = K[i][j] + ke[loop1][loop2];
}
}
}
printf("K\n");
print_arr((double*)K, nn*ndof, nn*ndof);
//correct upto here
double Kf[nn*ndof][nn*ndof] = {};
for (int i = 0; i < nn*ndof; i++){
for (int j = 0; j < nn*ndof; j++) {
Kf[i][j] = K[i][j];
}
}
//int Kf[][] = K;
//Applying Boundary conditions
//----------------------------
for (int p = 0; p < sizeof(BC) / sizeof(BC[0]); p++) {
for (int q = 0; q < tdof; q++) {
K[BC[p]][ q] = 0;
}
K[BC[p]][ BC[p]] = 1;
}
//Force vector
//------------
double f[] = { 0, 0, 0, -200, 0, -100, 0, -100, 0, 0, 0, 0, 0, 0, 0, 0 };
//Displacement vector
//-------------------
const int z = 16;
double inv[z][z];
double tt[z][z];
for (int i = 0; i < z; i++) {
for (int j = 0; j < z; j++) {
tt[i][j] = (10 * ((float)rand() / RAND_MAX));
}
}
inverse((double*)tt, (double*)inv, z);
printf("inv\n");
print_arr((double*)inv, z,z);
//mat_mul(inv,f);
//d = K\f
//Reaction forces
//---------------
//mat_mul(Kf,d);
//fr = Kf*d
//Axial forces
//------------
/*
for (int e = 0; e < nel; e++) {
de = d[LCM[:, e]]; //displacement of the current element
const_ = CArea[e] * E / L[e]; //constant parameter with in the elementt
p = Ang[e];
c = cos(e);
force[e] = const_*{ -c, -s, c, s } *de;
}*/
/*
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
// Add vectors in parallel.
cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}*/
scanf("%d", &ind);
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
}
// Function to get cofactor of A[p][q] in temp[][]. n is current dimension of A[][]
void getCofactor(double* A, double* temp, int p, int q, int n){
int i = 0, j = 0;
// Looping for each element of the matrix
for (int row = 0; row < n; row++){
for (int col = 0; col < n; col++){
// Copying into temporary matrix only those element
// which are not in given row and column
if (row != p && col != q){
temp[i*n + j] = A[row*n + col];
j++;
// Row is filled, so increase row index and
// reset col index
if (j == n - 1){
j = 0;
i++;
}
}
}
}
}
/* Recursive function for finding determinant of matrix.
n is current dimension of A[][]. */
double determinant(double* A, int n){
double D = 0; // Initialize result
// Base case : if matrix contains single element
if (n == 1)
return A[0];
double* temp =(double*) malloc(sizeof(double)*n*n); // To store cofactors
int sign = 1; // To store sign multiplier
// Iterate for each element of first row
for (int f = 0; f < n; f++){
// Getting Cofactor of A[0][f]
getCofactor(A, temp, 0, f, n);
D += sign * A[0*n + f] * determinant(temp, n - 1);
// terms are to be added with alternate sign
sign = -sign;
}
free(temp);
return D;
}
// Function to get adjoint of A[N][N] in adj[N][N].
void adjoint(double* A, double* adj, int n){
if (n == 1){
adj[0] = 1;
return;
}
// temp is used to store cofactors of A[][]
int sign = 1;
double *temp = (double*) malloc(sizeof(double)*n*n);
for (int i = 0; i<n; i++){
for (int j = 0; j<n; j++){
// Get cofactor of A[i][j]
getCofactor(A, temp, i, j, n);
// sign of adj[j][i] positive if sum of row
// and column indexes is even.
sign = ((i + j) % 2 == 0) ? 1 : -1;
// Interchanging rows and columns to get the
// transpose of the cofactor matrix
adj[j*n + i] = (sign)*(determinant(temp, n - 1));
}
}
free(temp);
}
// Function to calculate and store inverse, returns false if
// matrix is singular
bool inverse(double* A, double* inverse, int n){
// Find determinant of A[][]
double det = determinant(A, n);
printf("%lf\n", det);
if (det < (double)1e-6 && det > -(double)1e-6){
//cout << "Singular matrix, can't find its inverse";
return false;
}
// Find adjoint
double* adj = (double*)malloc(sizeof(double)*n*n);
adjoint(A, adj,n);
// Find Inverse using formula "inverse(A) = adj(A)/det(A)"
for (int i = 0; i<n; i++)
for (int j = 0; j<n; j++)
inverse[i*n + j] = adj[i*n + j] / double(det);
free(adj);
return true;
}
void print_arr(int *arr, int m, int n) {
int i, j;
for (i = 0; i < m; i++) {
for (j = 0; j < n; j++)
printf("%d ", *((arr + i*n) + j));
printf("\n");
}
}
void print_arr(double *arr, int m, int n) {
int i, j;
for (i = 0; i < m; i++) {
for (j = 0; j < n; j++)
printf("%lf ", *((arr + i*n) + j));
printf("\n");
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiPKiS1_
.globl _Z9addKernelPiPKiS1_
.p2align 8
.type _Z9addKernelPiPKiS1_,@function
_Z9addKernelPiPKiS1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiPKiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiPKiS1_, .Lfunc_end0-_Z9addKernelPiPKiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiPKiS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiPKiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addKernelPiPKiS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiPKiS1_
.globl _Z9addKernelPiPKiS1_
.p2align 8
.type _Z9addKernelPiPKiS1_,@function
_Z9addKernelPiPKiS1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiPKiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiPKiS1_, .Lfunc_end0-_Z9addKernelPiPKiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiPKiS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiPKiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
//-----------------------------------------------------------------------------
// TheKernel: basic kernel containing a print statement.
//-----------------------------------------------------------------------------
__global__ void TheKernel()
{
// Give the kernel something to keep its (single) thread occupied
int i, j, k;
k = 0;
for (i = 0; i < 1000; i++) {
for (j = 0; j < 1000; j++) {
k += i;
if (k > 2000) {
k -= 4*j;
}
else {
k += j;
}
}
}
printf("This is the kernel saying hello world, from the GPU.\n");
}
//-----------------------------------------------------------------------------
// main
//-----------------------------------------------------------------------------
int main()
{
printf("This is the C layer saying hello world, from the host.\n");
TheKernel<<<1, 1>>>();
// Add a print statement immediately after the kernel launch
printf("LOOK: the host keeps on running once the kernel is launched.\n");
// It appears essential to call for synchronization before finally
// exiting, lest you risk the program crashing your machine!
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z9TheKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
//-----------------------------------------------------------------------------
// TheKernel: basic kernel containing a print statement.
//-----------------------------------------------------------------------------
__global__ void TheKernel()
{
// Give the kernel something to keep its (single) thread occupied
int i, j, k;
k = 0;
for (i = 0; i < 1000; i++) {
for (j = 0; j < 1000; j++) {
k += i;
if (k > 2000) {
k -= 4*j;
}
else {
k += j;
}
}
}
printf("This is the kernel saying hello world, from the GPU.\n");
}
//-----------------------------------------------------------------------------
// main
//-----------------------------------------------------------------------------
int main()
{
printf("This is the C layer saying hello world, from the host.\n");
TheKernel<<<1, 1>>>();
// Add a print statement immediately after the kernel launch
printf("LOOK: the host keeps on running once the kernel is launched.\n");
// It appears essential to call for synchronization before finally
// exiting, lest you risk the program crashing your machine!
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000c04d3_00000000-6_program_ib.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9TheKernelvv
.type _Z27__device_stub__Z9TheKernelvv, @function
_Z27__device_stub__Z9TheKernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9TheKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9TheKernelvv, .-_Z27__device_stub__Z9TheKernelvv
.globl _Z9TheKernelv
.type _Z9TheKernelv, @function
_Z9TheKernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9TheKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9TheKernelv, .-_Z9TheKernelv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "This is the C layer saying hello world, from the host.\n"
.align 8
.LC1:
.string "LOOK: the host keeps on running once the kernel is launched.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z27__device_stub__Z9TheKernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z9TheKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9TheKernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
//-----------------------------------------------------------------------------
// TheKernel: basic kernel containing a print statement.
//-----------------------------------------------------------------------------
__global__ void TheKernel()
{
// Give the kernel something to keep its (single) thread occupied
int i, j, k;
k = 0;
for (i = 0; i < 1000; i++) {
for (j = 0; j < 1000; j++) {
k += i;
if (k > 2000) {
k -= 4*j;
}
else {
k += j;
}
}
}
printf("This is the kernel saying hello world, from the GPU.\n");
}
//-----------------------------------------------------------------------------
// main
//-----------------------------------------------------------------------------
int main()
{
printf("This is the C layer saying hello world, from the host.\n");
TheKernel<<<1, 1>>>();
// Add a print statement immediately after the kernel launch
printf("LOOK: the host keeps on running once the kernel is launched.\n");
// It appears essential to call for synchronization before finally
// exiting, lest you risk the program crashing your machine!
cudaDeviceSynchronize();
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
//-----------------------------------------------------------------------------
// TheKernel: basic kernel containing a print statement.
//-----------------------------------------------------------------------------
__global__ void TheKernel()
{
// Give the kernel something to keep its (single) thread occupied
int i, j, k;
k = 0;
for (i = 0; i < 1000; i++) {
for (j = 0; j < 1000; j++) {
k += i;
if (k > 2000) {
k -= 4*j;
}
else {
k += j;
}
}
}
printf("This is the kernel saying hello world, from the GPU.\n");
}
//-----------------------------------------------------------------------------
// main
//-----------------------------------------------------------------------------
int main()
{
printf("This is the C layer saying hello world, from the host.\n");
TheKernel<<<1, 1>>>();
// Add a print statement immediately after the kernel launch
printf("LOOK: the host keeps on running once the kernel is launched.\n");
// It appears essential to call for synchronization before finally
// exiting, lest you risk the program crashing your machine!
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
//-----------------------------------------------------------------------------
// TheKernel: basic kernel containing a print statement.
//-----------------------------------------------------------------------------
__global__ void TheKernel()
{
// Give the kernel something to keep its (single) thread occupied
int i, j, k;
k = 0;
for (i = 0; i < 1000; i++) {
for (j = 0; j < 1000; j++) {
k += i;
if (k > 2000) {
k -= 4*j;
}
else {
k += j;
}
}
}
printf("This is the kernel saying hello world, from the GPU.\n");
}
//-----------------------------------------------------------------------------
// main
//-----------------------------------------------------------------------------
int main()
{
printf("This is the C layer saying hello world, from the host.\n");
TheKernel<<<1, 1>>>();
// Add a print statement immediately after the kernel launch
printf("LOOK: the host keeps on running once the kernel is launched.\n");
// It appears essential to call for synchronization before finally
// exiting, lest you risk the program crashing your machine!
hipDeviceSynchronize();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9TheKernelv
.globl _Z9TheKernelv
.p2align 8
.type _Z9TheKernelv,@function
_Z9TheKernelv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 54
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9TheKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9TheKernelv, .Lfunc_end0-_Z9TheKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "This is the kernel saying hello world, from the GPU.\n"
.size .str, 54
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9TheKernelv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z9TheKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
//-----------------------------------------------------------------------------
// TheKernel: basic kernel containing a print statement.
//-----------------------------------------------------------------------------
__global__ void TheKernel()
{
// Give the kernel something to keep its (single) thread occupied
int i, j, k;
k = 0;
for (i = 0; i < 1000; i++) {
for (j = 0; j < 1000; j++) {
k += i;
if (k > 2000) {
k -= 4*j;
}
else {
k += j;
}
}
}
printf("This is the kernel saying hello world, from the GPU.\n");
}
//-----------------------------------------------------------------------------
// main
//-----------------------------------------------------------------------------
int main()
{
printf("This is the C layer saying hello world, from the host.\n");
TheKernel<<<1, 1>>>();
// Add a print statement immediately after the kernel launch
printf("LOOK: the host keeps on running once the kernel is launched.\n");
// It appears essential to call for synchronization before finally
// exiting, lest you risk the program crashing your machine!
hipDeviceSynchronize();
return 0;
} | .text
.file "program_ib.hip"
.globl _Z24__device_stub__TheKernelv # -- Begin function _Z24__device_stub__TheKernelv
.p2align 4, 0x90
.type _Z24__device_stub__TheKernelv,@function
_Z24__device_stub__TheKernelv: # @_Z24__device_stub__TheKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9TheKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__TheKernelv, .Lfunc_end0-_Z24__device_stub__TheKernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9TheKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr.1, %edi
callq puts@PLT
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9TheKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9TheKernelv,@object # @_Z9TheKernelv
.section .rodata,"a",@progbits
.globl _Z9TheKernelv
.p2align 3, 0x0
_Z9TheKernelv:
.quad _Z24__device_stub__TheKernelv
.size _Z9TheKernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9TheKernelv"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "This is the C layer saying hello world, from the host."
.size .Lstr, 55
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "LOOK: the host keeps on running once the kernel is launched."
.size .Lstr.1, 61
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__TheKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9TheKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9TheKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9TheKernelv
.globl _Z9TheKernelv
.p2align 8
.type _Z9TheKernelv,@function
_Z9TheKernelv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 54
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9TheKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9TheKernelv, .Lfunc_end0-_Z9TheKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "This is the kernel saying hello world, from the GPU.\n"
.size .str, 54
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9TheKernelv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z9TheKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c04d3_00000000-6_program_ib.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9TheKernelvv
.type _Z27__device_stub__Z9TheKernelvv, @function
_Z27__device_stub__Z9TheKernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9TheKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9TheKernelvv, .-_Z27__device_stub__Z9TheKernelvv
.globl _Z9TheKernelv
.type _Z9TheKernelv, @function
_Z9TheKernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9TheKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9TheKernelv, .-_Z9TheKernelv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "This is the C layer saying hello world, from the host.\n"
.align 8
.LC1:
.string "LOOK: the host keeps on running once the kernel is launched.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z27__device_stub__Z9TheKernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z9TheKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9TheKernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "program_ib.hip"
.globl _Z24__device_stub__TheKernelv # -- Begin function _Z24__device_stub__TheKernelv
.p2align 4, 0x90
.type _Z24__device_stub__TheKernelv,@function
_Z24__device_stub__TheKernelv: # @_Z24__device_stub__TheKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9TheKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__TheKernelv, .Lfunc_end0-_Z24__device_stub__TheKernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9TheKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr.1, %edi
callq puts@PLT
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9TheKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9TheKernelv,@object # @_Z9TheKernelv
.section .rodata,"a",@progbits
.globl _Z9TheKernelv
.p2align 3, 0x0
_Z9TheKernelv:
.quad _Z24__device_stub__TheKernelv
.size _Z9TheKernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9TheKernelv"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "This is the C layer saying hello world, from the host."
.size .Lstr, 55
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "LOOK: the host keeps on running once the kernel is launched."
.size .Lstr.1, 61
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__TheKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9TheKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void check_for_neuron_spikes_kernel(float *d_membrane_potentials_v, float *d_thresholds_for_action_potential_spikes, float *d_resting_potentials, float* d_last_spike_time_of_each_neuron, unsigned char* d_bitarray_of_neuron_spikes, int bitarray_length, int bitarray_maximum_axonal_delay_in_timesteps, float current_time_in_seconds, float timestep, size_t total_number_of_neurons, bool high_fidelity_spike_flag) {
// Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
if (d_membrane_potentials_v[idx] >= d_thresholds_for_action_potential_spikes[idx]) {
// Set current time as last spike time of neuron
d_last_spike_time_of_each_neuron[idx] = current_time_in_seconds;
// Reset membrane potential
d_membrane_potentials_v[idx] = d_resting_potentials[idx];
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = idx * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte |= (1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
} else {
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = idx * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte &= ~(1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | code for sm_80
Function : _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ BSSY B0, 0x890 ; /* 0x0000086000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x198], PT ; /* 0x0000660000007a0c */
/* 0x000fe40003f06070 */
/*0060*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011400 */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x19c], PT, P0 ; /* 0x0000670005007a0c */
/* 0x000fda0003f06100 */
/*0080*/ @P0 BRA 0x880 ; /* 0x000007f000000947 */
/* 0x000fea0003800000 */
/*0090*/ MUFU.RCP R2, c[0x0][0x194] ; /* 0x0000650000027b08 */
/* 0x000e220000001000 */
/*00a0*/ ULDC UR4, c[0x0][0x190] ; /* 0x0000640000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff077624 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.U32 R6, RZ, RZ, UR4 ; /* 0x00000004ff067e24 */
/* 0x000fe2000f8e00ff */
/*00d0*/ ULDC.S8 UR4, c[0x0][0x1a0] ; /* 0x0000680000047ab9 */
/* 0x000fe40000000200 */
/*00e0*/ ISETP.NE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf45270 */
/*00f0*/ FCHK P0, R6, c[0x0][0x194] ; /* 0x0000650006007b02 */
/* 0x000e620000000000 */
/*0100*/ FFMA R3, R2, -R7, 1 ; /* 0x3f80000002037423 */
/* 0x001fc80000000807 */
/*0110*/ FFMA R3, R2, R3, R2 ; /* 0x0000000302037223 */
/* 0x000fc80000000002 */
/*0120*/ FFMA R2, R3, c[0x0][0x190], RZ ; /* 0x0000640003027a23 */
/* 0x000fc800000000ff */
/*0130*/ FFMA R4, R2, -R7, c[0x0][0x190] ; /* 0x0000640002047623 */
/* 0x000fc80000000807 */
/*0140*/ FFMA R4, R3, R4, R2 ; /* 0x0000000403047223 */
/* 0x000fe40000000002 */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0005 */
/*0160*/ IMAD.MOV.U32 R3, RZ, RZ, R0 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0000 */
/*0170*/ @!P0 BRA 0x1b0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0180*/ MOV R4, 0x1a0 ; /* 0x000001a000047802 */
/* 0x000fe40000000f00 */
/*0190*/ CALL.REL.NOINC 0x8b0 ; /* 0x0000071000007944 */
/* 0x000fea0003c00000 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*01b0*/ @!P2 BRA 0x6f0 ; /* 0x000005300000a947 */
/* 0x000fea0003800000 */
/*01c0*/ IABS R9, c[0x0][0x18c] ; /* 0x0000630000097a13 */
/* 0x000fe40000000000 */
/*01d0*/ LOP3.LUT R6, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004067812 */
/* 0x000fe400078ec0ff */
/*01e0*/ I2F.RP R7, R9 ; /* 0x0000000900077306 */
/* 0x000e240000209400 */
/*01f0*/ LOP3.LUT R11, R6, 0x3f000000, RZ, 0xfc, !PT ; /* 0x3f000000060b7812 */
/* 0x000fca00078efcff */
/*0200*/ FADD.RZ R4, R11, R4 ; /* 0x000000040b047221 */
/* 0x000fc8000000c000 */
/*0210*/ F2I.TRUNC.NTZ R6, R4 ; /* 0x0000000400067305 */
/* 0x0002b0000020f100 */
/*0220*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e220000001000 */
/*0230*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x002fe200078e00ff */
/*0240*/ ISETP.GE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fc40003f46270 */
/*0250*/ IADD3 R5, R7, 0xffffffe, RZ ; /* 0x0ffffffe07057810 */
/* 0x001fcc0007ffe0ff */
/*0260*/ F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e24000021f000 */
/*0270*/ IMAD.MOV R8, RZ, RZ, -R5 ; /* 0x000000ffff087224 */
/* 0x001fc800078e0a05 */
/*0280*/ IMAD R11, R8, R9, RZ ; /* 0x00000009080b7224 */
/* 0x000fe200078e02ff */
/*0290*/ IABS R8, R6 ; /* 0x0000000600087213 */
/* 0x000fc60000000000 */
/*02a0*/ IMAD.HI.U32 R7, R5, R11, R4 ; /* 0x0000000b05077227 */
/* 0x000fcc00078e0004 */
/*02b0*/ IMAD.HI.U32 R7, R7, R8, RZ ; /* 0x0000000807077227 */
/* 0x000fc800078e00ff */
/*02c0*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a07 */
/*02d0*/ IMAD R4, R9, R7, R8 ; /* 0x0000000709047224 */
/* 0x000fca00078e0208 */
/*02e0*/ ISETP.GT.U32.AND P0, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x000fda0003f04070 */
/*02f0*/ @!P0 IMAD.IADD R4, R4, 0x1, -R9 ; /* 0x0000000104048824 */
/* 0x000fe200078e0a09 */
/*0300*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x18c], PT ; /* 0x00006300ff007a0c */
/* 0x000fc80003f05270 */
/*0310*/ ISETP.GT.U32.AND P1, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x000fda0003f24070 */
/*0320*/ @!P1 IMAD.IADD R4, R4, 0x1, -R9 ; /* 0x0000000104049824 */
/* 0x000fc800078e0a09 */
/*0330*/ @!P2 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e0a04 */
/*0340*/ @!P0 LOP3.LUT R4, RZ, c[0x0][0x18c], RZ, 0x33, !PT ; /* 0x00006300ff048a12 */
/* 0x000fe400078e33ff */
/*0350*/ IMAD.SHL.U32 R10, R3.reuse, 0x4, RZ ; /* 0x00000004030a7824 */
/* 0x040fe200078e00ff */
/*0360*/ SHF.L.U64.HI R11, R3, 0x2, R2 ; /* 0x00000002030b7819 */
/* 0x000fe20000010202 */
/*0370*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0380*/ IADD3 R6, P0, R10.reuse, c[0x0][0x168], RZ ; /* 0x00005a000a067a10 */
/* 0x040fe40007f1e0ff */
/*0390*/ IADD3 R2, P1, R10, c[0x0][0x160], RZ ; /* 0x000058000a027a10 */
/* 0x000fe40007f3e0ff */
/*03a0*/ IADD3.X R7, R11.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000b077a10 */
/* 0x040fe400007fe4ff */
/*03b0*/ IADD3.X R3, R11, c[0x0][0x164], RZ, P1, !PT ; /* 0x000059000b037a10 */
/* 0x000fc60000ffe4ff */
/*03c0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ BSSY B1, 0x670 ; /* 0x0000028000017945 */
/* 0x000fe20003800000 */
/*03f0*/ FSETP.GE.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x004fda0003f06000 */
/*0400*/ @!P0 BRA 0x580 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0410*/ IADD3 R8, P0, R10.reuse, c[0x0][0x178], RZ ; /* 0x00005e000a087a10 */
/* 0x040fe20007f1e0ff */
/*0420*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0d7624 */
/* 0x000fe200078e00ff */
/*0430*/ IADD3 R10, P1, R10, c[0x0][0x170], RZ ; /* 0x00005c000a0a7a10 */
/* 0x000fe20007f3e0ff */
/*0440*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0450*/ IADD3.X R9, R11.reuse, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000b097a10 */
/* 0x040fe400007fe4ff */
/*0460*/ IADD3.X R11, R11, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d000b0b7a10 */
/* 0x000fc60000ffe4ff */
/*0470*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x0001e8000c101904 */
/*0480*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea2000c1e1900 */
/*0490*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fc80000011404 */
/*04a0*/ LEA.HI R5, R5, R4, RZ, 0x3 ; /* 0x0000000405057211 */
/* 0x000fc800078f18ff */
/*04b0*/ SHF.R.S32.HI R7, RZ, 0x3, R5 ; /* 0x00000003ff077819 */
/* 0x000fca0000011405 */
/*04c0*/ IMAD R7, R0, c[0x0][0x188], R7 ; /* 0x0000620000077a24 */
/* 0x000fca00078e0207 */
/*04d0*/ IADD3 R6, P0, R7, c[0x0][0x180], RZ ; /* 0x0000600007067a10 */
/* 0x000fc80007f1e0ff */
/*04e0*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x184], 0x1, P0 ; /* 0x0000610007077a11 */
/* 0x000fe200000f0eff */
/*04f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0043e8000c101904 */
/*0500*/ LDG.E.U8 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea2000c1e1100 */
/*0510*/ LOP3.LUT R5, R5, 0xfffffff8, RZ, 0xc0, !PT ; /* 0xfffffff805057812 */
/* 0x000fe200078ec0ff */
/*0520*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x001fc800078e00ff */
/*0530*/ IMAD.IADD R5, R4, 0x1, -R5 ; /* 0x0000000104057824 */
/* 0x000fca00078e0a05 */
/*0540*/ SHF.L.U32 R5, R8, R5, RZ ; /* 0x0000000508057219 */
/* 0x000fc800000006ff */
/*0550*/ LOP3.LUT R5, R12, R5, RZ, 0xfc, !PT ; /* 0x000000050c057212 */
/* 0x004fca00078efcff */
/*0560*/ STG.E.U8 [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0003e2000c101104 */
/*0570*/ BRA 0x660 ; /* 0x000000e000007947 */
/* 0x000fea0003800000 */
/*0580*/ SHF.R.S32.HI R3, RZ, 0x1f, R4 ; /* 0x0000001fff037819 */
/* 0x000fe20000011404 */
/*0590*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*05a0*/ LEA.HI R6, R3, R4, RZ, 0x3 ; /* 0x0000000403067211 */
/* 0x000fc800078f18ff */
/*05b0*/ SHF.R.S32.HI R3, RZ, 0x3, R6 ; /* 0x00000003ff037819 */
/* 0x000fca0000011406 */
/*05c0*/ IMAD R3, R0, c[0x0][0x188], R3 ; /* 0x0000620000037a24 */
/* 0x000fca00078e0203 */
/*05d0*/ IADD3 R2, P0, R3, c[0x0][0x180], RZ ; /* 0x0000600003027a10 */
/* 0x000fc80007f1e0ff */
/*05e0*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x184], 0x1, P0 ; /* 0x0000610003037a11 */
/* 0x000fca00000f0eff */
/*05f0*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1100 */
/*0600*/ LOP3.LUT R7, R6, 0xfffffff8, RZ, 0xc0, !PT ; /* 0xfffffff806077812 */
/* 0x000fe200078ec0ff */
/*0610*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fc800078e00ff */
/*0620*/ IMAD.IADD R7, R4, 0x1, -R7 ; /* 0x0000000104077824 */
/* 0x000fca00078e0a07 */
/*0630*/ SHF.L.U32 R6, R6, R7, RZ ; /* 0x0000000706067219 */
/* 0x000fc800000006ff */
/*0640*/ LOP3.LUT R5, R5, R6, RZ, 0x30, !PT ; /* 0x0000000605057212 */
/* 0x004fca00078e30ff */
/*0650*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101104 */
/*0660*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0670*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x003fc800078e00ff */
/*0680*/ IMAD R3, R3, c[0x0][0xc], R0 ; /* 0x0000030003037a24 */
/* 0x000fc800078e0200 */
/*0690*/ IMAD.MOV.U32 R0, RZ, RZ, R3.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e0003 */
/*06a0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x198], PT ; /* 0x0000660003007a0c */
/* 0x000fe40003f06070 */
/*06b0*/ SHF.R.S32.HI R2, RZ, 0x1f, R3 ; /* 0x0000001fff027819 */
/* 0x000fc80000011403 */
/*06c0*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x19c], PT, P0 ; /* 0x0000670002007a0c */
/* 0x000fda0003f06100 */
/*06d0*/ @!P0 BRA 0x350 ; /* 0xfffffc7000008947 */
/* 0x000fea000383ffff */
/*06e0*/ BRA 0x880 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*06f0*/ IMAD.SHL.U32 R6, R3.reuse, 0x4, RZ ; /* 0x0000000403067824 */
/* 0x040fe200078e00ff */
/*0700*/ SHF.L.U64.HI R7, R3, 0x2, R2 ; /* 0x0000000203077819 */
/* 0x000fe20000010202 */
/*0710*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0720*/ IADD3 R2, P0, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x040fe40007f1e0ff */
/*0730*/ IADD3 R8, P1, R6, c[0x0][0x160], RZ ; /* 0x0000580006087a10 */
/* 0x000fe40007f3e0ff */
/*0740*/ IADD3.X R3, R7.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0007037a10 */
/* 0x040fe400007fe4ff */
/*0750*/ IADD3.X R9, R7, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590007097a10 */
/* 0x000fc60000ffe4ff */
/*0760*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x000ea4000c1e1900 */
/*0780*/ FSETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720b */
/* 0x004fda0003f06000 */
/*0790*/ @P0 IADD3 R4, P1, R6.reuse, c[0x0][0x178], RZ ; /* 0x00005e0006040a10 */
/* 0x040fe20007f3e0ff */
/*07a0*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0b0624 */
/* 0x000fe200078e00ff */
/*07b0*/ @P0 IADD3 R6, P2, R6, c[0x0][0x170], RZ ; /* 0x00005c0006060a10 */
/* 0x000fe40007f5e0ff */
/*07c0*/ @P0 IADD3.X R5, R7.reuse, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f0007050a10 */
/* 0x040fe40000ffe4ff */
/*07d0*/ @P0 IADD3.X R7, R7, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0007070a10 */
/* 0x000fc600017fe4ff */
/*07e0*/ @P0 STG.E [R4.64], R11 ; /* 0x0000000b04000986 */
/* 0x0001e8000c101904 */
/*07f0*/ @P0 LDG.E R7, [R6.64] ; /* 0x0000000406070981 */
/* 0x000ea2000c1e1900 */
/*0800*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0d7624 */
/* 0x000fc800078e00ff */
/*0810*/ IMAD R3, R13, c[0x0][0xc], R0 ; /* 0x000003000d037a24 */
/* 0x000fc800078e0200 */
/*0820*/ IMAD.MOV.U32 R0, RZ, RZ, R3.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e0003 */
/*0830*/ SHF.R.S32.HI R2, RZ, 0x1f, R3 ; /* 0x0000001fff027819 */
/* 0x000fe20000011403 */
/*0840*/ @P0 STG.E [R8.64], R7 ; /* 0x0000000708000986 */
/* 0x0041e2000c101904 */
/*0850*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x198], PT ; /* 0x0000660003007a0c */
/* 0x000fc80003f06070 */
/*0860*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x19c], PT, P0 ; /* 0x0000670002007a0c */
/* 0x000fda0003f06100 */
/*0870*/ @!P0 BRA 0x6f0 ; /* 0xfffffe7000008947 */
/* 0x001fea000383ffff */
/*0880*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0890*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08b0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff0d7624 */
/* 0x000fe400078e00ff */
/*08c0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0a7624 */
/* 0x000fe400078e00ff */
/*08d0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff077624 */
/* 0x000fe200078e00ff */
/*08e0*/ SHF.R.U32.HI R6, RZ, 0x17, R13 ; /* 0x00000017ff067819 */
/* 0x000fe2000001160d */
/*08f0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff087624 */
/* 0x000fe200078e00ff */
/*0900*/ SHF.R.U32.HI R5, RZ, 0x17, R10 ; /* 0x00000017ff057819 */
/* 0x000fc4000001160a */
/*0910*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe400078ec0ff */
/*0920*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0930*/ IADD3 R12, R6, -0x1, RZ ; /* 0xffffffff060c7810 */
/* 0x000fe40007ffe0ff */
/*0940*/ IADD3 R11, R5, -0x1, RZ ; /* 0xffffffff050b7810 */
/* 0x000fe40007ffe0ff */
/*0950*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0960*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0970*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0980*/ @!P0 BRA 0xb00 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0990*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe40003f1c200 */
/*09a0*/ FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fc80003f3c200 */
/*09b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*09c0*/ @P0 BRA 0xee0 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*09d0*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*09e0*/ @!P0 BRA 0xec0 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*09f0*/ FSETP.NEU.FTZ.AND P3, PT, |R10|.reuse, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x040fe40003f7d200 */
/*0a00*/ FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3d200 */
/*0a10*/ FSETP.NEU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fd60003f1d200 */
/*0a20*/ @!P1 BRA !P3, 0xec0 ; /* 0x0000049000009947 */
/* 0x000fea0005800000 */
/*0a30*/ LOP3.LUT P3, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000786c0ff */
/*0a40*/ PLOP3.LUT P1, PT, P1, P3, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f26572 */
/*0a50*/ @P1 BRA 0xea0 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*0a60*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0a70*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0a80*/ @P0 BRA 0xe70 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0a90*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0aa0*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0ab0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0ac0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0ad0*/ @!P0 FFMA R7, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a078823 */
/* 0x000fe400000000ff */
/*0ae0*/ @!P1 FFMA R8, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d089823 */
/* 0x000fe200000000ff */
/*0af0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0b00*/ LEA R11, R6, 0xc0800000, 0x17 ; /* 0xc0800000060b7811 */
/* 0x000fca00078eb8ff */
/*0b10*/ IMAD.IADD R11, R8, 0x1, -R11 ; /* 0x00000001080b7824 */
/* 0x000fe200078e0a0b */
/*0b20*/ IADD3 R8, R5, -0x7f, RZ ; /* 0xffffff8105087810 */
/* 0x000fc60007ffe0ff */
/*0b30*/ MUFU.RCP R10, R11 ; /* 0x0000000b000a7308 */
/* 0x000e220000001000 */
/*0b40*/ FADD.FTZ R12, -R11, -RZ ; /* 0x800000ff0b0c7221 */
/* 0x000fe40000010100 */
/*0b50*/ IMAD R7, R8.reuse, -0x800000, R7 ; /* 0xff80000008077824 */
/* 0x040fe200078e0207 */
/*0b60*/ IADD3 R8, R8, 0x7f, -R6 ; /* 0x0000007f08087810 */
/* 0x000fca0007ffe806 */
/*0b70*/ IMAD.IADD R8, R8, 0x1, R9 ; /* 0x0000000108087824 */
/* 0x000fe400078e0209 */
/*0b80*/ FFMA R5, R10, R12, 1 ; /* 0x3f8000000a057423 */
/* 0x001fc8000000000c */
/*0b90*/ FFMA R14, R10, R5, R10 ; /* 0x000000050a0e7223 */
/* 0x000fc8000000000a */
/*0ba0*/ FFMA R5, R7, R14, RZ ; /* 0x0000000e07057223 */
/* 0x000fc800000000ff */
/*0bb0*/ FFMA R10, R12, R5, R7 ; /* 0x000000050c0a7223 */
/* 0x000fc80000000007 */
/*0bc0*/ FFMA R13, R14, R10, R5 ; /* 0x0000000a0e0d7223 */
/* 0x000fc80000000005 */
/*0bd0*/ FFMA R7, R12, R13, R7 ; /* 0x0000000d0c077223 */
/* 0x000fc80000000007 */
/*0be0*/ FFMA R5, R14, R7, R13 ; /* 0x000000070e057223 */
/* 0x000fca000000000d */
/*0bf0*/ SHF.R.U32.HI R6, RZ, 0x17, R5 ; /* 0x00000017ff067819 */
/* 0x000fc80000011605 */
/*0c00*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fca00078ec0ff */
/*0c10*/ IMAD.IADD R10, R6, 0x1, R8 ; /* 0x00000001060a7824 */
/* 0x000fca00078e0208 */
/*0c20*/ IADD3 R6, R10, -0x1, RZ ; /* 0xffffffff0a067810 */
/* 0x000fc80007ffe0ff */
/*0c30*/ ISETP.GE.U32.AND P0, PT, R6, 0xfe, PT ; /* 0x000000fe0600780c */
/* 0x000fda0003f06070 */
/*0c40*/ @!P0 BRA 0xe50 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0c50*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*0c60*/ @P0 BRA 0xe20 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0c70*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*0c80*/ @P0 BRA 0xef0 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0c90*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*0ca0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0cb0*/ @!P0 BRA 0xef0 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0cc0*/ FFMA.RZ R6, R14, R7.reuse, R13.reuse ; /* 0x000000070e067223 */
/* 0x180fe2000000c00d */
/*0cd0*/ IADD3 R9, R10.reuse, 0x20, RZ ; /* 0x000000200a097810 */
/* 0x040fe40007ffe0ff */
/*0ce0*/ ISETP.NE.AND P3, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f65270 */
/*0cf0*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*0d00*/ FFMA.RP R6, R14, R7.reuse, R13.reuse ; /* 0x000000070e067223 */
/* 0x180fe2000000800d */
/*0d10*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*0d20*/ FFMA.RM R7, R14, R7, R13 ; /* 0x000000070e077223 */
/* 0x000fe2000000400d */
/*0d30*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe200078efcff */
/*0d40*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e0a0a */
/*0d50*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0d60*/ FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x000fe40003f1d000 */
/*0d70*/ SEL R7, R10, RZ, P3 ; /* 0x000000ff0a077207 */
/* 0x000fe40001800000 */
/*0d80*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0d90*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*0da0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0db0*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fe40000011607 */
/*0dc0*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fc80004000000 */
/*0dd0*/ LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ef809 */
/*0de0*/ LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ; /* 0x0000000706067212 */
/* 0x000fca00078ec0ff */
/*0df0*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fca00078e0206 */
/*0e00*/ LOP3.LUT R5, R6, R5, RZ, 0xfc, !PT ; /* 0x0000000506057212 */
/* 0x000fe200078efcff */
/*0e10*/ BRA 0xef0 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0e20*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*0e30*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0e40*/ BRA 0xef0 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0e50*/ IMAD R5, R8, 0x800000, R5 ; /* 0x0080000008057824 */
/* 0x000fe200078e0205 */
/*0e60*/ BRA 0xef0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0e70*/ LOP3.LUT R5, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fc800078e4807 */
/*0e80*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0e90*/ BRA 0xef0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0ea0*/ LOP3.LUT R5, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fe200078e4807 */
/*0eb0*/ BRA 0xef0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0ec0*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0ed0*/ BRA 0xef0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ee0*/ FADD.FTZ R5, R10, c[0x0][0x194] ; /* 0x000065000a057621 */
/* 0x000fc80000010000 */
/*0ef0*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0005 */
/*0f00*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0f10*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff0e004007950 */
/* 0x000fea0003c3ffff */
/*0f20*/ BRA 0xf20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void check_for_neuron_spikes_kernel(float *d_membrane_potentials_v, float *d_thresholds_for_action_potential_spikes, float *d_resting_potentials, float* d_last_spike_time_of_each_neuron, unsigned char* d_bitarray_of_neuron_spikes, int bitarray_length, int bitarray_maximum_axonal_delay_in_timesteps, float current_time_in_seconds, float timestep, size_t total_number_of_neurons, bool high_fidelity_spike_flag) {
// Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
if (d_membrane_potentials_v[idx] >= d_thresholds_for_action_potential_spikes[idx]) {
// Set current time as last spike time of neuron
d_last_spike_time_of_each_neuron[idx] = current_time_in_seconds;
// Reset membrane potential
d_membrane_potentials_v[idx] = d_resting_potentials[idx];
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = idx * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte |= (1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
} else {
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = idx * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte &= ~(1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | .file "tmpxft_0018d115_00000000-6_check_for_neuron_spikes_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z64__device_stub__Z30check_for_neuron_spikes_kernelPfS_S_S_PhiiffmbPfS_S_S_Phiiffmb
.type _Z64__device_stub__Z30check_for_neuron_spikes_kernelPfS_S_S_PhiiffmbPfS_S_S_Phiiffmb, @function
_Z64__device_stub__Z30check_for_neuron_spikes_kernelPfS_S_S_PhiiffmbPfS_S_S_Phiiffmb:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movl %r9d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movl 256(%rsp), %eax
movb %al, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 248(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z64__device_stub__Z30check_for_neuron_spikes_kernelPfS_S_S_PhiiffmbPfS_S_S_Phiiffmb, .-_Z64__device_stub__Z30check_for_neuron_spikes_kernelPfS_S_S_PhiiffmbPfS_S_S_Phiiffmb
.globl _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.type _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb, @function
_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movzbl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z64__device_stub__Z30check_for_neuron_spikes_kernelPfS_S_S_PhiiffmbPfS_S_S_Phiiffmb
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb, .-_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void check_for_neuron_spikes_kernel(float *d_membrane_potentials_v, float *d_thresholds_for_action_potential_spikes, float *d_resting_potentials, float* d_last_spike_time_of_each_neuron, unsigned char* d_bitarray_of_neuron_spikes, int bitarray_length, int bitarray_maximum_axonal_delay_in_timesteps, float current_time_in_seconds, float timestep, size_t total_number_of_neurons, bool high_fidelity_spike_flag) {
// Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
if (d_membrane_potentials_v[idx] >= d_thresholds_for_action_potential_spikes[idx]) {
// Set current time as last spike time of neuron
d_last_spike_time_of_each_neuron[idx] = current_time_in_seconds;
// Reset membrane potential
d_membrane_potentials_v[idx] = d_resting_potentials[idx];
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = idx * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte |= (1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
} else {
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = idx * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte &= ~(1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void check_for_neuron_spikes_kernel(float *d_membrane_potentials_v, float *d_thresholds_for_action_potential_spikes, float *d_resting_potentials, float* d_last_spike_time_of_each_neuron, unsigned char* d_bitarray_of_neuron_spikes, int bitarray_length, int bitarray_maximum_axonal_delay_in_timesteps, float current_time_in_seconds, float timestep, size_t total_number_of_neurons, bool high_fidelity_spike_flag) {
// Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
if (d_membrane_potentials_v[idx] >= d_thresholds_for_action_potential_spikes[idx]) {
// Set current time as last spike time of neuron
d_last_spike_time_of_each_neuron[idx] = current_time_in_seconds;
// Reset membrane potential
d_membrane_potentials_v[idx] = d_resting_potentials[idx];
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = idx * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte |= (1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
} else {
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = idx * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte &= ~(1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void check_for_neuron_spikes_kernel(float *d_membrane_potentials_v, float *d_thresholds_for_action_potential_spikes, float *d_resting_potentials, float* d_last_spike_time_of_each_neuron, unsigned char* d_bitarray_of_neuron_spikes, int bitarray_length, int bitarray_maximum_axonal_delay_in_timesteps, float current_time_in_seconds, float timestep, size_t total_number_of_neurons, bool high_fidelity_spike_flag) {
// Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
if (d_membrane_potentials_v[idx] >= d_thresholds_for_action_potential_spikes[idx]) {
// Set current time as last spike time of neuron
d_last_spike_time_of_each_neuron[idx] = current_time_in_seconds;
// Reset membrane potential
d_membrane_potentials_v[idx] = d_resting_potentials[idx];
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = idx * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte |= (1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
} else {
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = idx * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte &= ~(1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.globl _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.p2align 8
.type _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb,@function
_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x54
s_load_b64 s[12:13], s[0:1], 0x38
s_add_u32 s2, s0, 0x48
s_addc_u32 s3, s1, 0
s_mov_b32 s14, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s20, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s20, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[12:13], v[3:4]
s_cbranch_execz .LBB0_9
s_clause 0x2
s_load_b64 s[16:17], s[0:1], 0x30
s_load_b32 s4, s[0:1], 0x40
s_load_b128 s[8:11], s[0:1], 0x20
s_load_b32 s21, s[2:3], 0x0
s_mov_b32 s18, 0
s_waitcnt lgkmcnt(0)
s_bitcmp1_b32 s4, 0
v_div_scale_f32 v1, null, s17, s17, s16
v_div_scale_f32 v6, vcc_lo, s16, s17, s16
s_mul_i32 s19, s21, s20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v1, v2, 1.0
v_fmac_f32_e32 v2, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v6, v2
v_fma_f32 v7, -v1, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v7, v2
v_fma_f32 v1, -v1, v5, v6
v_mul_lo_u32 v6, s10, v3
s_mul_i32 s10, s19, s10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v1, v1, v2, v5
v_div_fixup_f32 v1, v1, s17, s16
s_cselect_b32 s17, -1, 0
s_ashr_i32 s2, s11, 31
s_add_i32 s15, s15, s21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f32_e32 v2, v1
v_sub_f32_e32 v5, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s3, |v5|, 0.5
v_cndmask_b32_e64 v5, 0, 1.0, s3
s_add_i32 s3, s11, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_xor_b32 s11, s3, s2
s_load_b256 s[0:7], s[0:1], 0x0
v_bfi_b32 v1, 0x7fffffff, v5, v1
v_cvt_f32_u32_e32 v5, s11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v1, v2, v1
v_rcp_iflag_f32_e32 v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v1, v1
v_readfirstlane_b32 s21, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v2
v_mad_u64_u32 v[1:2], null, s15, s20, v[0:1]
s_ashr_i32 s15, s21, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_u32_f32_e32 v0, v5
s_add_i32 s21, s21, s15
s_xor_b32 s20, s21, s15
s_sub_i32 s21, 0, s11
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s22
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v6, s10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_cmp_le_u64_e32 vcc_lo, s[12:13], v[1:2]
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
v_add_nc_u32_e32 v1, s19, v1
s_or_b32 s18, vcc_lo, s18
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execz .LBB0_9
.LBB0_3:
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_mov_b32 s22, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v5, vcc_lo
global_load_b32 v9, v[2:3], off
global_load_b32 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_ge_f32_e32 v9, v7
s_xor_b32 s22, exec_lo, s22
s_cbranch_execz .LBB0_6
v_add_co_u32 v7, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_mov_b32_e32 v9, s16
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s17
global_store_b32 v[7:8], v9, off
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v4, off
s_cbranch_vccnz .LBB0_6
v_readfirstlane_b32 s23, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s24, s21, s23
s_mul_hi_u32 s24, s23, s24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s23, s23, s24
s_mul_hi_u32 s23, s20, s23
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s23, s23, s11
s_sub_i32 s23, s20, s23
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s24, s23, s11
s_cmp_ge_u32 s23, s11
s_cselect_b32 s23, s24, s23
s_sub_i32 s24, s23, s11
s_cmp_ge_u32 s23, s11
s_cselect_b32 s23, s24, s23
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s23, s23, s15
s_sub_i32 s23, s23, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s24, s23, 31
s_lshr_b32 s24, s24, 29
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s24, s23, s24
s_ashr_i32 s25, s24, 3
s_and_b32 s24, s24, -8
v_add_nc_u32_e32 v2, s25, v6
s_sub_i32 s23, s23, s24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b32 s23, 1, s23
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v2, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_u8 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_or_b32_e32 v4, s23, v4
global_store_b8 v[2:3], v4, off
.LBB0_6:
s_and_not1_saveexec_b32 s22, s22
s_cbranch_execz .LBB0_2
s_and_not1_b32 vcc_lo, exec_lo, s17
s_cbranch_vccnz .LBB0_2
v_readfirstlane_b32 s23, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s24, s21, s23
s_mul_hi_u32 s24, s23, s24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s23, s23, s24
s_mul_hi_u32 s23, s20, s23
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s23, s23, s11
s_sub_i32 s23, s20, s23
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s24, s23, s11
s_cmp_ge_u32 s23, s11
s_cselect_b32 s23, s24, s23
s_sub_i32 s24, s23, s11
s_cmp_ge_u32 s23, s11
s_cselect_b32 s23, s24, s23
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s23, s23, s15
s_sub_i32 s23, s23, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s24, s23, 31
s_lshr_b32 s24, s24, 29
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s24, s23, s24
s_ashr_i32 s25, s24, 3
s_and_b32 s24, s24, -8
v_add_nc_u32_e32 v2, s25, v6
s_sub_i32 s23, s23, s24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s23, 1, s23
v_xor_b32_e64 v5, s23, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_u8 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v4, v4, v5
global_store_b8 v[2:3], v4, off
s_branch .LBB0_2
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 26
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb, .Lfunc_end0-_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
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.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
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.size: 2
.value_kind: hidden_remainder_x
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.size: 8
.value_kind: hidden_global_offset_x
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.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.private_segment_fixed_size: 0
.sgpr_count: 28
.sgpr_spill_count: 0
.symbol: _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void check_for_neuron_spikes_kernel(float *d_membrane_potentials_v, float *d_thresholds_for_action_potential_spikes, float *d_resting_potentials, float* d_last_spike_time_of_each_neuron, unsigned char* d_bitarray_of_neuron_spikes, int bitarray_length, int bitarray_maximum_axonal_delay_in_timesteps, float current_time_in_seconds, float timestep, size_t total_number_of_neurons, bool high_fidelity_spike_flag) {
// Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
if (d_membrane_potentials_v[idx] >= d_thresholds_for_action_potential_spikes[idx]) {
// Set current time as last spike time of neuron
d_last_spike_time_of_each_neuron[idx] = current_time_in_seconds;
// Reset membrane potential
d_membrane_potentials_v[idx] = d_resting_potentials[idx];
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = idx * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte |= (1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
} else {
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = idx * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte &= ~(1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | .text
.file "check_for_neuron_spikes_kernel.hip"
.globl _Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb # -- Begin function _Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.p2align 4, 0x90
.type _Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb,@function
_Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb: # @_Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movzbl 224(%rsp), %eax
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movb %al, 11(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 216(%rsp), %rax
movq %rax, 184(%rsp)
leaq 11(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb, .Lfunc_end0-_Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb,@object # @_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.section .rodata,"a",@progbits
.globl _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.p2align 3, 0x0
_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb:
.quad _Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.size _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb"
.size .L__unnamed_1, 51
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018d115_00000000-6_check_for_neuron_spikes_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z64__device_stub__Z30check_for_neuron_spikes_kernelPfS_S_S_PhiiffmbPfS_S_S_Phiiffmb
.type _Z64__device_stub__Z30check_for_neuron_spikes_kernelPfS_S_S_PhiiffmbPfS_S_S_Phiiffmb, @function
_Z64__device_stub__Z30check_for_neuron_spikes_kernelPfS_S_S_PhiiffmbPfS_S_S_Phiiffmb:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movl %r9d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movl 256(%rsp), %eax
movb %al, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 248(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z64__device_stub__Z30check_for_neuron_spikes_kernelPfS_S_S_PhiiffmbPfS_S_S_Phiiffmb, .-_Z64__device_stub__Z30check_for_neuron_spikes_kernelPfS_S_S_PhiiffmbPfS_S_S_Phiiffmb
.globl _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.type _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb, @function
_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movzbl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z64__device_stub__Z30check_for_neuron_spikes_kernelPfS_S_S_PhiiffmbPfS_S_S_Phiiffmb
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb, .-_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "check_for_neuron_spikes_kernel.hip"
.globl _Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb # -- Begin function _Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.p2align 4, 0x90
.type _Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb,@function
_Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb: # @_Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movzbl 224(%rsp), %eax
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movb %al, 11(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 216(%rsp), %rax
movq %rax, 184(%rsp)
leaq 11(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb, .Lfunc_end0-_Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb,@object # @_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.section .rodata,"a",@progbits
.globl _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.p2align 3, 0x0
_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb:
.quad _Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.size _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb"
.size .L__unnamed_1, 51
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z45__device_stub__check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z30check_for_neuron_spikes_kernelPfS_S_S_Phiiffmb
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<math.h>
#include<cuda.h>
#define TWW 32 // Setting TileWidth
/*----------Kernel Function------------*/
__global__ void matMul(double *d_a,double *d_b,double *d_c, int M, int N, int K){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col= blockIdx.x * blockDim.x + threadIdx.x;
__shared__ double ds_a[TWW][TWW];
__shared__ double ds_b[TWW][TWW];
double cval=0.0;
for(int t=0;t<N/TWW;t++){
// Loading data from Global meomory to Shared memory
ds_a[threadIdx.y][threadIdx.x]=d_a[row*N+t*TWW+threadIdx.x];
ds_b[threadIdx.y][threadIdx.x]=d_b[(t*TWW+threadIdx.y)*K+col];
__syncthreads();
for(int k=0;k<TWW;k++){
cval+=ds_a[threadIdx.y][k]*ds_b[k][threadIdx.x];
}
__syncthreads();
}
d_c[row*K + col]=cval;
}
/*------------------------------*/
int main(int argc, char const *argv[]) {
/*Matrix A size = M X N and Matrix B size = N X K*/
int N=800, M=N,K=N;
double h_a[M][N],h_b[N][K],h_c[M][K];
double *d_a,*d_b,*d_c;
cudaEvent_t start,stop;
float ms;
//Generatig matrix
for(int i=0;i<M;i++){
for(int j=0;j<N;j++){
h_a[i][j]=rand()%100;
}
}
for(int i=0;i<N;i++){
for(int j=0;j<K;j++){
h_b[i][j]=rand()%100;
}
}
/*printf("\n A Matrix\n" );
for(int i=0;i<M;i++){
for(int j=0;j<N;j++){
printf("%0.1f ",h_a[i][j] );
}
printf("\n" );
}
printf("\n B Matrix\n" );
for(int i=0;i<N;i++){
for(int j=0;j<K;j++){
printf("%0.1f ",h_b[i][j] );
}
printf("\n" );
}*/
// taking block diamension as TWW X TWW
dim3 dimBlock(TWW,TWW);
dim3 dimGrid(K/TWW,M/TWW );
// allocating device memory
cudaMalloc(&d_a, M*N*sizeof(double));
cudaMalloc(&d_b, N*K*sizeof(double));
cudaMalloc(&d_c, M*K*sizeof(double));
// copying data in device memory
cudaMemcpy( d_a, h_a, M*N*sizeof(double), cudaMemcpyHostToDevice );
cudaMemcpy( d_b, h_b, N*K*sizeof(double), cudaMemcpyHostToDevice );
//Creating timestamp event
cudaEventCreate(&start);
cudaEventCreate(&stop);
//Recording Kernel start time
cudaEventRecord(start, 0);
//calling kernel function
matMul<<<dimGrid,dimBlock>>>(d_a,d_b,d_c,M,N,K);
//Recording Kernel stop time
cudaEventRecord(stop, 0);
cudaMemcpy(h_c, d_c, M*K*sizeof(double), cudaMemcpyDeviceToHost );
cudaEventSynchronize(stop);
cudaEventElapsedTime(&ms, start, stop);
printf("\nTime:%f ",ms );
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(h_c, d_c, M*K*sizeof(double), cudaMemcpyDeviceToHost );
/*printf("\n Multiplication of A and B Matrix using Tiling:\n" );
for(int i=0;i<M;i++){
for(int j=0;j<K;j++){
printf("%0.1f ",h_c[i][j] );
}
printf("\n" );
}*/
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z6matMulPdS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ HFMA2.MMA R17, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff117435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002200 */
/*0060*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*0070*/ ISETP.GE.AND P0, PT, R4, 0x20, PT ; /* 0x000000200400780c */
/* 0x000fe40003f06270 */
/*0080*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0090*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*00a0*/ IMAD R3, R3, c[0x0][0x4], R7 ; /* 0x0000010003037a24 */
/* 0x001fc400078e0207 */
/*00b0*/ IMAD R2, R5, c[0x0][0x0], R0 ; /* 0x0000000005027a24 */
/* 0x002fc800078e0200 */
/*00c0*/ IMAD R16, R3, c[0x0][0x180], R2 ; /* 0x0000600003107a24 */
/* 0x000fc800078e0202 */
/*00d0*/ IMAD.WIDE R16, R16, R17, c[0x0][0x170] ; /* 0x00005c0010107625 */
/* 0x000fe200078e0211 */
/*00e0*/ @!P0 BRA 0x770 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*00f0*/ SHF.R.S32.HI R4, RZ, 0x1f, R4 ; /* 0x0000001fff047819 */
/* 0x000fe20000011404 */
/*0100*/ IMAD R2, R7.reuse, c[0x0][0x180], R2 ; /* 0x0000600007027a24 */
/* 0x040fe200078e0202 */
/*0110*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*0120*/ IMAD.SHL.U32 R7, R7, 0x100, RZ ; /* 0x0000010007077824 */
/* 0x000fe200078e00ff */
/*0130*/ LEA.HI R4, R4, c[0x0][0x17c], RZ, 0x5 ; /* 0x00005f0004047a11 */
/* 0x000fe200078f28ff */
/*0140*/ IMAD R3, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003037a24 */
/* 0x000fe200078e0200 */
/*0150*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0160*/ LEA R5, R0, R7, 0x3 ; /* 0x0000000700057211 */
/* 0x000fe400078e18ff */
/*0170*/ SHF.R.S32.HI R4, RZ, 0x5, R4 ; /* 0x00000005ff047819 */
/* 0x000fc40000011404 */
/*0180*/ IMAD.MOV.U32 R8, RZ, RZ, 0x8 ; /* 0x00000008ff087424 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE.U32 R28, R3, R8, c[0x0][0x160] ; /* 0x00005800031c7625 */
/* 0x000fc800078e0008 */
/*01a0*/ IMAD.WIDE.U32 R8, R2, R8, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fe400078e0008 */
/*01b0*/ LDG.E.64 R28, [R28.64] ; /* 0x000000061c1c7981 */
/* 0x000ea8000c1e1b00 */
/*01c0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ee2000c1e1b00 */
/*01d0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*01e0*/ IADD3 R3, R3, 0x20, RZ ; /* 0x0000002003037810 */
/* 0x000fca0007ffe0ff */
/*01f0*/ ISETP.LE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fe2000bf03270 */
/*0200*/ STS.64 [R5], R28 ; /* 0x0000001c05007388 */
/* 0x004fe80000000a00 */
/*0210*/ STS.64 [R5+0x2000], R8 ; /* 0x0020000805007388 */
/* 0x008fe80000000a00 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0230*/ LDS.64 R22, [R0.X8+0x2000] ; /* 0x0020000000167984 */
/* 0x000fe80000008a00 */
/*0240*/ LDS.128 R12, [R7] ; /* 0x00000000070c7984 */
/* 0x000e280000000c00 */
/*0250*/ LDS.64 R18, [R0.X8+0x2100] ; /* 0x0021000000127984 */
/* 0x000e680000008a00 */
/*0260*/ LDS.64 R20, [R0.X8+0x2200] ; /* 0x0022000000147984 */
/* 0x000fe80000008a00 */
/*0270*/ LDS.128 R8, [R7+0x10] ; /* 0x0000100007087984 */
/* 0x000ea80000000c00 */
/*0280*/ LDS.64 R26, [R0.X8+0x2300] ; /* 0x00230000001a7984 */
/* 0x000ee20000008a00 */
/*0290*/ DFMA R22, R22, R12, R24 ; /* 0x0000000c1616722b */
/* 0x0010460000000018 */
/*02a0*/ LDS.64 R24, [R0.X8+0x2700] ; /* 0x0027000000187984 */
/* 0x001fe60000008a00 */
/*02b0*/ DFMA R22, R18, R14, R22 ; /* 0x0000000e1216722b */
/* 0x0020a40000000016 */
/*02c0*/ LDS.64 R18, [R0.X8+0x2400] ; /* 0x0024000000127984 */
/* 0x001fe80000008a00 */
/*02d0*/ LDS.128 R12, [R7+0x20] ; /* 0x00002000070c7984 */
/* 0x000e220000000c00 */
/*02e0*/ DFMA R8, R20, R8, R22 ; /* 0x000000081408722b */
/* 0x0042c60000000016 */
/*02f0*/ LDS.64 R22, [R0.X8+0x2500] ; /* 0x0025000000167984 */
/* 0x002e660000008a00 */
/*0300*/ DFMA R26, R26, R10, R8 ; /* 0x0000000a1a1a722b */
/* 0x0084220000000008 */
/*0310*/ LDS.64 R20, [R0.X8+0x2600] ; /* 0x0026000000147984 */
/* 0x000fe80000008a00 */
/*0320*/ LDS.128 R8, [R7+0x30] ; /* 0x0000300007087984 */
/* 0x004ea20000000c00 */
/*0330*/ DFMA R12, R18, R12, R26 ; /* 0x0000000c120c722b */
/* 0x001046000000001a */
/*0340*/ LDS.64 R18, [R0.X8+0x2800] ; /* 0x0028000000127984 */
/* 0x001fe60000008a00 */
/*0350*/ DFMA R22, R22, R14, R12 ; /* 0x0000000e1616722b */
/* 0x0020a2000000000c */
/*0360*/ LDS.64 R26, [R0.X8+0x2b00] ; /* 0x002b0000001a7984 */
/* 0x000fe80000008a00 */
/*0370*/ LDS.128 R12, [R7+0x40] ; /* 0x00004000070c7984 */
/* 0x001e220000000c00 */
/*0380*/ DFMA R8, R20, R8, R22 ; /* 0x000000081408722b */
/* 0x0042860000000016 */
/*0390*/ LDS.64 R20, [R0.X8+0x2a00] ; /* 0x002a000000147984 */
/* 0x002fe60000008a00 */
/*03a0*/ DFMA R24, R24, R10, R8 ; /* 0x0000000a1818722b */
/* 0x0042220000000008 */
/*03b0*/ LDS.64 R22, [R0.X8+0x2900] ; /* 0x0029000000167984 */
/* 0x000ea80000008a00 */
/*03c0*/ LDS.128 R8, [R7+0x50] ; /* 0x0000500007087984 */
/* 0x002e620000000c00 */
/*03d0*/ DFMA R12, R18, R12, R24 ; /* 0x0000000c120c722b */
/* 0x0010860000000018 */
/*03e0*/ LDS.64 R18, [R0.X8+0x2c00] ; /* 0x002c000000127984 */
/* 0x001fe80000008a00 */
/*03f0*/ LDS.64 R24, [R0.X8+0x2f00] ; /* 0x002f000000187984 */
/* 0x000fe20000008a00 */
/*0400*/ DFMA R22, R22, R14, R12 ; /* 0x0000000e1616722b */
/* 0x004046000000000c */
/*0410*/ LDS.128 R12, [R7+0x60] ; /* 0x00006000070c7984 */
/* 0x001e260000000c00 */
/*0420*/ DFMA R8, R20, R8, R22 ; /* 0x000000081408722b */
/* 0x0022a40000000016 */
/*0430*/ LDS.64 R20, [R0.X8+0x2e00] ; /* 0x002e000000147984 */
/* 0x002fe80000008a00 */
/*0440*/ LDS.64 R22, [R0.X8+0x2d00] ; /* 0x002d000000167984 */
/* 0x000e620000008a00 */
/*0450*/ DFMA R26, R26, R10, R8 ; /* 0x0000000a1a1a722b */
/* 0x0044060000000008 */
/*0460*/ LDS.128 R8, [R7+0x70] ; /* 0x0000700007087984 */
/* 0x004ea60000000c00 */
/*0470*/ DFMA R12, R18, R12, R26 ; /* 0x0000000c120c722b */
/* 0x001064000000001a */
/*0480*/ LDS.64 R18, [R0.X8+0x3000] ; /* 0x0030000000127984 */
/* 0x001fe80000008a00 */
/*0490*/ LDS.64 R26, [R0.X8+0x3300] ; /* 0x00330000001a7984 */
/* 0x000fe20000008a00 */
/*04a0*/ DFMA R22, R22, R14, R12 ; /* 0x0000000e1616722b */
/* 0x002086000000000c */
/*04b0*/ LDS.128 R12, [R7+0x80] ; /* 0x00008000070c7984 */
/* 0x001e260000000c00 */
/*04c0*/ DFMA R8, R20, R8, R22 ; /* 0x000000081408722b */
/* 0x0042a40000000016 */
/*04d0*/ LDS.64 R20, [R0.X8+0x3200] ; /* 0x0032000000147984 */
/* 0x002fe80000008a00 */
/*04e0*/ LDS.64 R22, [R0.X8+0x3100] ; /* 0x0031000000167984 */
/* 0x000e620000008a00 */
/*04f0*/ DFMA R24, R24, R10, R8 ; /* 0x0000000a1818722b */
/* 0x0044060000000008 */
/*0500*/ LDS.128 R8, [R7+0x90] ; /* 0x0000900007087984 */
/* 0x004ea60000000c00 */
/*0510*/ DFMA R12, R18, R12, R24 ; /* 0x0000000c120c722b */
/* 0x0010640000000018 */
/*0520*/ LDS.64 R18, [R0.X8+0x3400] ; /* 0x0034000000127984 */
/* 0x001fe80000008a00 */
/*0530*/ LDS.64 R24, [R0.X8+0x3700] ; /* 0x0037000000187984 */
/* 0x000fe20000008a00 */
/*0540*/ DFMA R22, R22, R14, R12 ; /* 0x0000000e1616722b */
/* 0x002086000000000c */
/*0550*/ LDS.128 R12, [R7+0xa0] ; /* 0x0000a000070c7984 */
/* 0x001e260000000c00 */
/*0560*/ DFMA R8, R20, R8, R22 ; /* 0x000000081408722b */
/* 0x0042a40000000016 */
/*0570*/ LDS.64 R20, [R0.X8+0x3600] ; /* 0x0036000000147984 */
/* 0x002fe80000008a00 */
/*0580*/ LDS.64 R22, [R0.X8+0x3500] ; /* 0x0035000000167984 */
/* 0x000e620000008a00 */
/*0590*/ DFMA R26, R26, R10, R8 ; /* 0x0000000a1a1a722b */
/* 0x0044060000000008 */
/*05a0*/ LDS.128 R8, [R7+0xb0] ; /* 0x0000b00007087984 */
/* 0x004ea60000000c00 */
/*05b0*/ DFMA R12, R18, R12, R26 ; /* 0x0000000c120c722b */
/* 0x001064000000001a */
/*05c0*/ LDS.64 R18, [R0.X8+0x3800] ; /* 0x0038000000127984 */
/* 0x001fe80000008a00 */
/*05d0*/ LDS.64 R26, [R0.X8+0x3b00] ; /* 0x003b0000001a7984 */
/* 0x000fe20000008a00 */
/*05e0*/ DFMA R22, R22, R14, R12 ; /* 0x0000000e1616722b */
/* 0x002086000000000c */
/*05f0*/ LDS.128 R12, [R7+0xc0] ; /* 0x0000c000070c7984 */
/* 0x001e260000000c00 */
/*0600*/ DFMA R8, R20, R8, R22 ; /* 0x000000081408722b */
/* 0x0042a40000000016 */
/*0610*/ LDS.64 R20, [R0.X8+0x3a00] ; /* 0x003a000000147984 */
/* 0x002fe80000008a00 */
/*0620*/ LDS.64 R22, [R0.X8+0x3900] ; /* 0x0039000000167984 */
/* 0x000e620000008a00 */
/*0630*/ DFMA R24, R24, R10, R8 ; /* 0x0000000a1818722b */
/* 0x0044060000000008 */
/*0640*/ LDS.128 R8, [R7+0xd0] ; /* 0x0000d00007087984 */
/* 0x004ea60000000c00 */
/*0650*/ DFMA R12, R18, R12, R24 ; /* 0x0000000c120c722b */
/* 0x0010640000000018 */
/*0660*/ LDS.64 R18, [R0.X8+0x3c00] ; /* 0x003c000000127984 */
/* 0x001fe80000008a00 */
/*0670*/ LDS.64 R24, [R0.X8+0x3e00] ; /* 0x003e000000187984 */
/* 0x000fe20000008a00 */
/*0680*/ DFMA R22, R22, R14, R12 ; /* 0x0000000e1616722b */
/* 0x002086000000000c */
/*0690*/ LDS.128 R12, [R7+0xe0] ; /* 0x0000e000070c7984 */
/* 0x001e260000000c00 */
/*06a0*/ DFMA R8, R20, R8, R22 ; /* 0x000000081408722b */
/* 0x0042a40000000016 */
/*06b0*/ LDS.64 R20, [R0.X8+0x3d00] ; /* 0x003d000000147984 */
/* 0x002e680000008a00 */
/*06c0*/ DFMA R26, R26, R10, R8 ; /* 0x0000000a1a1a722b */
/* 0x0044220000000008 */
/*06d0*/ LDS.64 R22, [R0.X8+0x3f00] ; /* 0x003f000000167984 */
/* 0x000fe80000008a00 */
/*06e0*/ LDS.128 R8, [R7+0xf0] ; /* 0x0000f00007087984 */
/* 0x004ea20000000c00 */
/*06f0*/ DFMA R12, R18, R12, R26 ; /* 0x0000000c120c722b */
/* 0x001e4c000000001a */
/*0700*/ DFMA R12, R20, R14, R12 ; /* 0x0000000e140c722b */
/* 0x002e8c000000000c */
/*0710*/ DFMA R24, R24, R8, R12 ; /* 0x000000081818722b */
/* 0x004064000000000c */
/*0720*/ MOV R9, c[0x0][0x180] ; /* 0x0000600000097a02 */
/* 0x001fc80000000f00 */
/*0730*/ DFMA R24, R22, R10, R24 ; /* 0x0000000a1618722b */
/* 0x0020620000000018 */
/*0740*/ LEA R2, R9, R2, 0x5 ; /* 0x0000000209027211 */
/* 0x000fe200078e28ff */
/*0750*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0760*/ @!P0 BRA 0x180 ; /* 0xfffffa1000008947 */
/* 0x003fea000383ffff */
/*0770*/ STG.E.64 [R16.64], R24 ; /* 0x0000001810007986 */
/* 0x000fe2000c101b06 */
/*0780*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0790*/ BRA 0x790; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<math.h>
#include<cuda.h>
#define TWW 32 // Setting TileWidth
/*----------Kernel Function------------*/
__global__ void matMul(double *d_a,double *d_b,double *d_c, int M, int N, int K){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col= blockIdx.x * blockDim.x + threadIdx.x;
__shared__ double ds_a[TWW][TWW];
__shared__ double ds_b[TWW][TWW];
double cval=0.0;
for(int t=0;t<N/TWW;t++){
// Loading data from Global meomory to Shared memory
ds_a[threadIdx.y][threadIdx.x]=d_a[row*N+t*TWW+threadIdx.x];
ds_b[threadIdx.y][threadIdx.x]=d_b[(t*TWW+threadIdx.y)*K+col];
__syncthreads();
for(int k=0;k<TWW;k++){
cval+=ds_a[threadIdx.y][k]*ds_b[k][threadIdx.x];
}
__syncthreads();
}
d_c[row*K + col]=cval;
}
/*------------------------------*/
int main(int argc, char const *argv[]) {
/*Matrix A size = M X N and Matrix B size = N X K*/
int N=800, M=N,K=N;
double h_a[M][N],h_b[N][K],h_c[M][K];
double *d_a,*d_b,*d_c;
cudaEvent_t start,stop;
float ms;
//Generatig matrix
for(int i=0;i<M;i++){
for(int j=0;j<N;j++){
h_a[i][j]=rand()%100;
}
}
for(int i=0;i<N;i++){
for(int j=0;j<K;j++){
h_b[i][j]=rand()%100;
}
}
/*printf("\n A Matrix\n" );
for(int i=0;i<M;i++){
for(int j=0;j<N;j++){
printf("%0.1f ",h_a[i][j] );
}
printf("\n" );
}
printf("\n B Matrix\n" );
for(int i=0;i<N;i++){
for(int j=0;j<K;j++){
printf("%0.1f ",h_b[i][j] );
}
printf("\n" );
}*/
// taking block diamension as TWW X TWW
dim3 dimBlock(TWW,TWW);
dim3 dimGrid(K/TWW,M/TWW );
// allocating device memory
cudaMalloc(&d_a, M*N*sizeof(double));
cudaMalloc(&d_b, N*K*sizeof(double));
cudaMalloc(&d_c, M*K*sizeof(double));
// copying data in device memory
cudaMemcpy( d_a, h_a, M*N*sizeof(double), cudaMemcpyHostToDevice );
cudaMemcpy( d_b, h_b, N*K*sizeof(double), cudaMemcpyHostToDevice );
//Creating timestamp event
cudaEventCreate(&start);
cudaEventCreate(&stop);
//Recording Kernel start time
cudaEventRecord(start, 0);
//calling kernel function
matMul<<<dimGrid,dimBlock>>>(d_a,d_b,d_c,M,N,K);
//Recording Kernel stop time
cudaEventRecord(stop, 0);
cudaMemcpy(h_c, d_c, M*K*sizeof(double), cudaMemcpyDeviceToHost );
cudaEventSynchronize(stop);
cudaEventElapsedTime(&ms, start, stop);
printf("\nTime:%f ",ms );
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(h_c, d_c, M*K*sizeof(double), cudaMemcpyDeviceToHost );
/*printf("\n Multiplication of A and B Matrix using Tiling:\n" );
for(int i=0;i<M;i++){
for(int j=0;j<K;j++){
printf("%0.1f ",h_c[i][j] );
}
printf("\n" );
}*/
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_0001a19e_00000000-6_Tiled_Mat_Mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6matMulPdS_S_iiiPdS_S_iii
.type _Z32__device_stub__Z6matMulPdS_S_iiiPdS_S_iii, @function
_Z32__device_stub__Z6matMulPdS_S_iiiPdS_S_iii:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6matMulPdS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z6matMulPdS_S_iiiPdS_S_iii, .-_Z32__device_stub__Z6matMulPdS_S_iiiPdS_S_iii
.globl _Z6matMulPdS_S_iii
.type _Z6matMulPdS_S_iii, @function
_Z6matMulPdS_S_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6matMulPdS_S_iiiPdS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6matMulPdS_S_iii, .-_Z6matMulPdS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\nTime:%f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $104, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq -5120000(%rsp), %rax
.L12:
cmpq %rax, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rsp, %r14
leaq -5120000(%rsp), %rax
.L15:
cmpq %rax, %rsp
je .L16
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L15
.L16:
movq %rsp, %r13
leaq -5120000(%rsp), %rax
.L18:
cmpq %rax, %rsp
je .L19
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L18
.L19:
movq %rsp, -136(%rbp)
leaq 6400(%r14), %r12
leaq 5126400(%r14), %r15
.L21:
leaq -6400(%r12), %rbx
.L22:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L22
addq $6400, %r12
cmpq %r15, %r12
jne .L21
leaq 6400(%r13), %r12
leaq 5126400(%r13), %r15
.L23:
leaq -6400(%r12), %rbx
.L24:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L24
addq $6400, %r12
cmpq %r15, %r12
jne .L23
movl $32, -80(%rbp)
movl $32, -76(%rbp)
movl $1, -72(%rbp)
movl $25, -68(%rbp)
movl $25, -64(%rbp)
movl $1, -60(%rbp)
leaq -120(%rbp), %rdi
movl $5120000, %esi
call cudaMalloc@PLT
leaq -112(%rbp), %rdi
movl $5120000, %esi
call cudaMalloc@PLT
leaq -104(%rbp), %rdi
movl $5120000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $5120000, %edx
movq %r14, %rsi
movq -120(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $5120000, %edx
movq %r13, %rsi
movq -112(%rbp), %rdi
call cudaMemcpy@PLT
leaq -96(%rbp), %rdi
call cudaEventCreate@PLT
leaq -88(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -96(%rbp), %rdi
call cudaEventRecord@PLT
movl -72(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -80(%rbp), %rdx
movq -68(%rbp), %rdi
movl -60(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L26:
movl $0, %esi
movq -88(%rbp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $5120000, %edx
movq -104(%rbp), %rsi
movq -136(%rbp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq -88(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -124(%rbp), %rdi
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd -124(%rbp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -96(%rbp), %rdi
call cudaEventDestroy@PLT
movq -88(%rbp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $5120000, %edx
movq -104(%rbp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq -120(%rbp), %rdi
call cudaFree@PLT
movq -112(%rbp), %rdi
call cudaFree@PLT
movq -104(%rbp), %rdi
call cudaFree@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L32:
.cfi_restore_state
movl $800, %r9d
movl $800, %r8d
movl $800, %ecx
movq -104(%rbp), %rdx
movq -112(%rbp), %rsi
movq -120(%rbp), %rdi
call _Z32__device_stub__Z6matMulPdS_S_iiiPdS_S_iii
jmp .L26
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6matMulPdS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matMulPdS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<math.h>
#include<cuda.h>
#define TWW 32 // Setting TileWidth
/*----------Kernel Function------------*/
__global__ void matMul(double *d_a,double *d_b,double *d_c, int M, int N, int K){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col= blockIdx.x * blockDim.x + threadIdx.x;
__shared__ double ds_a[TWW][TWW];
__shared__ double ds_b[TWW][TWW];
double cval=0.0;
for(int t=0;t<N/TWW;t++){
// Loading data from Global meomory to Shared memory
ds_a[threadIdx.y][threadIdx.x]=d_a[row*N+t*TWW+threadIdx.x];
ds_b[threadIdx.y][threadIdx.x]=d_b[(t*TWW+threadIdx.y)*K+col];
__syncthreads();
for(int k=0;k<TWW;k++){
cval+=ds_a[threadIdx.y][k]*ds_b[k][threadIdx.x];
}
__syncthreads();
}
d_c[row*K + col]=cval;
}
/*------------------------------*/
int main(int argc, char const *argv[]) {
/*Matrix A size = M X N and Matrix B size = N X K*/
int N=800, M=N,K=N;
double h_a[M][N],h_b[N][K],h_c[M][K];
double *d_a,*d_b,*d_c;
cudaEvent_t start,stop;
float ms;
//Generatig matrix
for(int i=0;i<M;i++){
for(int j=0;j<N;j++){
h_a[i][j]=rand()%100;
}
}
for(int i=0;i<N;i++){
for(int j=0;j<K;j++){
h_b[i][j]=rand()%100;
}
}
/*printf("\n A Matrix\n" );
for(int i=0;i<M;i++){
for(int j=0;j<N;j++){
printf("%0.1f ",h_a[i][j] );
}
printf("\n" );
}
printf("\n B Matrix\n" );
for(int i=0;i<N;i++){
for(int j=0;j<K;j++){
printf("%0.1f ",h_b[i][j] );
}
printf("\n" );
}*/
// taking block diamension as TWW X TWW
dim3 dimBlock(TWW,TWW);
dim3 dimGrid(K/TWW,M/TWW );
// allocating device memory
cudaMalloc(&d_a, M*N*sizeof(double));
cudaMalloc(&d_b, N*K*sizeof(double));
cudaMalloc(&d_c, M*K*sizeof(double));
// copying data in device memory
cudaMemcpy( d_a, h_a, M*N*sizeof(double), cudaMemcpyHostToDevice );
cudaMemcpy( d_b, h_b, N*K*sizeof(double), cudaMemcpyHostToDevice );
//Creating timestamp event
cudaEventCreate(&start);
cudaEventCreate(&stop);
//Recording Kernel start time
cudaEventRecord(start, 0);
//calling kernel function
matMul<<<dimGrid,dimBlock>>>(d_a,d_b,d_c,M,N,K);
//Recording Kernel stop time
cudaEventRecord(stop, 0);
cudaMemcpy(h_c, d_c, M*K*sizeof(double), cudaMemcpyDeviceToHost );
cudaEventSynchronize(stop);
cudaEventElapsedTime(&ms, start, stop);
printf("\nTime:%f ",ms );
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(h_c, d_c, M*K*sizeof(double), cudaMemcpyDeviceToHost );
/*printf("\n Multiplication of A and B Matrix using Tiling:\n" );
for(int i=0;i<M;i++){
for(int j=0;j<K;j++){
printf("%0.1f ",h_c[i][j] );
}
printf("\n" );
}*/
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include<stdio.h>
#include<math.h>
#include<hip/hip_runtime.h>
#define TWW 32 // Setting TileWidth
/*----------Kernel Function------------*/
__global__ void matMul(double *d_a,double *d_b,double *d_c, int M, int N, int K){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col= blockIdx.x * blockDim.x + threadIdx.x;
__shared__ double ds_a[TWW][TWW];
__shared__ double ds_b[TWW][TWW];
double cval=0.0;
for(int t=0;t<N/TWW;t++){
// Loading data from Global meomory to Shared memory
ds_a[threadIdx.y][threadIdx.x]=d_a[row*N+t*TWW+threadIdx.x];
ds_b[threadIdx.y][threadIdx.x]=d_b[(t*TWW+threadIdx.y)*K+col];
__syncthreads();
for(int k=0;k<TWW;k++){
cval+=ds_a[threadIdx.y][k]*ds_b[k][threadIdx.x];
}
__syncthreads();
}
d_c[row*K + col]=cval;
}
/*------------------------------*/
int main(int argc, char const *argv[]) {
/*Matrix A size = M X N and Matrix B size = N X K*/
int N=800, M=N,K=N;
double h_a[M][N],h_b[N][K],h_c[M][K];
double *d_a,*d_b,*d_c;
hipEvent_t start,stop;
float ms;
//Generatig matrix
for(int i=0;i<M;i++){
for(int j=0;j<N;j++){
h_a[i][j]=rand()%100;
}
}
for(int i=0;i<N;i++){
for(int j=0;j<K;j++){
h_b[i][j]=rand()%100;
}
}
/*printf("\n A Matrix\n" );
for(int i=0;i<M;i++){
for(int j=0;j<N;j++){
printf("%0.1f ",h_a[i][j] );
}
printf("\n" );
}
printf("\n B Matrix\n" );
for(int i=0;i<N;i++){
for(int j=0;j<K;j++){
printf("%0.1f ",h_b[i][j] );
}
printf("\n" );
}*/
// taking block diamension as TWW X TWW
dim3 dimBlock(TWW,TWW);
dim3 dimGrid(K/TWW,M/TWW );
// allocating device memory
hipMalloc(&d_a, M*N*sizeof(double));
hipMalloc(&d_b, N*K*sizeof(double));
hipMalloc(&d_c, M*K*sizeof(double));
// copying data in device memory
hipMemcpy( d_a, h_a, M*N*sizeof(double), hipMemcpyHostToDevice );
hipMemcpy( d_b, h_b, N*K*sizeof(double), hipMemcpyHostToDevice );
//Creating timestamp event
hipEventCreate(&start);
hipEventCreate(&stop);
//Recording Kernel start time
hipEventRecord(start, 0);
//calling kernel function
matMul<<<dimGrid,dimBlock>>>(d_a,d_b,d_c,M,N,K);
//Recording Kernel stop time
hipEventRecord(stop, 0);
hipMemcpy(h_c, d_c, M*K*sizeof(double), hipMemcpyDeviceToHost );
hipEventSynchronize(stop);
hipEventElapsedTime(&ms, start, stop);
printf("\nTime:%f ",ms );
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(h_c, d_c, M*K*sizeof(double), hipMemcpyDeviceToHost );
/*printf("\n Multiplication of A and B Matrix using Tiling:\n" );
for(int i=0;i<M;i++){
for(int j=0;j<K;j++){
printf("%0.1f ",h_c[i][j] );
}
printf("\n" );
}*/
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<math.h>
#include<hip/hip_runtime.h>
#define TWW 32 // Setting TileWidth
/*----------Kernel Function------------*/
__global__ void matMul(double *d_a,double *d_b,double *d_c, int M, int N, int K){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col= blockIdx.x * blockDim.x + threadIdx.x;
__shared__ double ds_a[TWW][TWW];
__shared__ double ds_b[TWW][TWW];
double cval=0.0;
for(int t=0;t<N/TWW;t++){
// Loading data from Global meomory to Shared memory
ds_a[threadIdx.y][threadIdx.x]=d_a[row*N+t*TWW+threadIdx.x];
ds_b[threadIdx.y][threadIdx.x]=d_b[(t*TWW+threadIdx.y)*K+col];
__syncthreads();
for(int k=0;k<TWW;k++){
cval+=ds_a[threadIdx.y][k]*ds_b[k][threadIdx.x];
}
__syncthreads();
}
d_c[row*K + col]=cval;
}
/*------------------------------*/
int main(int argc, char const *argv[]) {
/*Matrix A size = M X N and Matrix B size = N X K*/
int N=800, M=N,K=N;
double h_a[M][N],h_b[N][K],h_c[M][K];
double *d_a,*d_b,*d_c;
hipEvent_t start,stop;
float ms;
//Generatig matrix
for(int i=0;i<M;i++){
for(int j=0;j<N;j++){
h_a[i][j]=rand()%100;
}
}
for(int i=0;i<N;i++){
for(int j=0;j<K;j++){
h_b[i][j]=rand()%100;
}
}
/*printf("\n A Matrix\n" );
for(int i=0;i<M;i++){
for(int j=0;j<N;j++){
printf("%0.1f ",h_a[i][j] );
}
printf("\n" );
}
printf("\n B Matrix\n" );
for(int i=0;i<N;i++){
for(int j=0;j<K;j++){
printf("%0.1f ",h_b[i][j] );
}
printf("\n" );
}*/
// taking block diamension as TWW X TWW
dim3 dimBlock(TWW,TWW);
dim3 dimGrid(K/TWW,M/TWW );
// allocating device memory
hipMalloc(&d_a, M*N*sizeof(double));
hipMalloc(&d_b, N*K*sizeof(double));
hipMalloc(&d_c, M*K*sizeof(double));
// copying data in device memory
hipMemcpy( d_a, h_a, M*N*sizeof(double), hipMemcpyHostToDevice );
hipMemcpy( d_b, h_b, N*K*sizeof(double), hipMemcpyHostToDevice );
//Creating timestamp event
hipEventCreate(&start);
hipEventCreate(&stop);
//Recording Kernel start time
hipEventRecord(start, 0);
//calling kernel function
matMul<<<dimGrid,dimBlock>>>(d_a,d_b,d_c,M,N,K);
//Recording Kernel stop time
hipEventRecord(stop, 0);
hipMemcpy(h_c, d_c, M*K*sizeof(double), hipMemcpyDeviceToHost );
hipEventSynchronize(stop);
hipEventElapsedTime(&ms, start, stop);
printf("\nTime:%f ",ms );
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(h_c, d_c, M*K*sizeof(double), hipMemcpyDeviceToHost );
/*printf("\n Multiplication of A and B Matrix using Tiling:\n" );
for(int i=0;i<M;i++){
for(int j=0;j<K;j++){
printf("%0.1f ",h_c[i][j] );
}
printf("\n" );
}*/
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matMulPdS_S_iii
.globl _Z6matMulPdS_S_iii
.p2align 8
.type _Z6matMulPdS_S_iii,@function
_Z6matMulPdS_S_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x1c
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v8, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s5, v[3:4]
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_mad_u64_u32 v[1:2], null, s14, s4, v[8:9]
s_cmp_lt_i32 s2, 32
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 3, v8
v_lshlrev_b32_e32 v2, 8, v3
s_ashr_i32 s8, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_lshr_b32 s8, s8, 27
v_or_b32_e32 v9, 0x2000, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v10, v2, v4
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_add_i32 s8, s2, s8
v_mad_u64_u32 v[6:7], null, v0, s2, v[8:9]
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v11, v9, v2
s_ashr_i32 s2, s8, 5
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s9, s8, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v14, s9, v3
v_add_nc_u32_e32 v7, s9, v6
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[12:13], null, v14, s3, v[1:2]
v_mov_b32_e32 v13, v8
v_lshlrev_b64 v[14:15], 3, v[7:8]
v_mov_b32_e32 v7, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[12:13], 3, v[12:13]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v14, vcc_lo, s4, v14
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
v_add_co_u32 v12, vcc_lo, s6, v12
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
global_load_b64 v[14:15], v[14:15], off
global_load_b64 v[12:13], v[12:13], off
s_waitcnt vmcnt(1)
ds_store_b64 v10, v[14:15]
s_waitcnt vmcnt(0)
ds_store_b64 v11, v[12:13]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v14, s9, v2
s_add_i32 s9, s9, 8
ds_load_b64 v[12:13], v7
ds_load_b64 v[14:15], v14
v_add_nc_u32_e32 v7, 0x100, v7
s_cmpk_eq_i32 s9, 0x100
s_waitcnt lgkmcnt(0)
v_fma_f64 v[4:5], v[14:15], v[12:13], v[4:5]
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[4:5], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matMulPdS_S_iii
.amdhsa_group_segment_fixed_size 16384
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matMulPdS_S_iii, .Lfunc_end0-_Z6matMulPdS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 16384
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matMulPdS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matMulPdS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<math.h>
#include<hip/hip_runtime.h>
#define TWW 32 // Setting TileWidth
/*----------Kernel Function------------*/
__global__ void matMul(double *d_a,double *d_b,double *d_c, int M, int N, int K){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col= blockIdx.x * blockDim.x + threadIdx.x;
__shared__ double ds_a[TWW][TWW];
__shared__ double ds_b[TWW][TWW];
double cval=0.0;
for(int t=0;t<N/TWW;t++){
// Loading data from Global meomory to Shared memory
ds_a[threadIdx.y][threadIdx.x]=d_a[row*N+t*TWW+threadIdx.x];
ds_b[threadIdx.y][threadIdx.x]=d_b[(t*TWW+threadIdx.y)*K+col];
__syncthreads();
for(int k=0;k<TWW;k++){
cval+=ds_a[threadIdx.y][k]*ds_b[k][threadIdx.x];
}
__syncthreads();
}
d_c[row*K + col]=cval;
}
/*------------------------------*/
int main(int argc, char const *argv[]) {
/*Matrix A size = M X N and Matrix B size = N X K*/
int N=800, M=N,K=N;
double h_a[M][N],h_b[N][K],h_c[M][K];
double *d_a,*d_b,*d_c;
hipEvent_t start,stop;
float ms;
//Generatig matrix
for(int i=0;i<M;i++){
for(int j=0;j<N;j++){
h_a[i][j]=rand()%100;
}
}
for(int i=0;i<N;i++){
for(int j=0;j<K;j++){
h_b[i][j]=rand()%100;
}
}
/*printf("\n A Matrix\n" );
for(int i=0;i<M;i++){
for(int j=0;j<N;j++){
printf("%0.1f ",h_a[i][j] );
}
printf("\n" );
}
printf("\n B Matrix\n" );
for(int i=0;i<N;i++){
for(int j=0;j<K;j++){
printf("%0.1f ",h_b[i][j] );
}
printf("\n" );
}*/
// taking block diamension as TWW X TWW
dim3 dimBlock(TWW,TWW);
dim3 dimGrid(K/TWW,M/TWW );
// allocating device memory
hipMalloc(&d_a, M*N*sizeof(double));
hipMalloc(&d_b, N*K*sizeof(double));
hipMalloc(&d_c, M*K*sizeof(double));
// copying data in device memory
hipMemcpy( d_a, h_a, M*N*sizeof(double), hipMemcpyHostToDevice );
hipMemcpy( d_b, h_b, N*K*sizeof(double), hipMemcpyHostToDevice );
//Creating timestamp event
hipEventCreate(&start);
hipEventCreate(&stop);
//Recording Kernel start time
hipEventRecord(start, 0);
//calling kernel function
matMul<<<dimGrid,dimBlock>>>(d_a,d_b,d_c,M,N,K);
//Recording Kernel stop time
hipEventRecord(stop, 0);
hipMemcpy(h_c, d_c, M*K*sizeof(double), hipMemcpyDeviceToHost );
hipEventSynchronize(stop);
hipEventElapsedTime(&ms, start, stop);
printf("\nTime:%f ",ms );
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(h_c, d_c, M*K*sizeof(double), hipMemcpyDeviceToHost );
/*printf("\n Multiplication of A and B Matrix using Tiling:\n" );
for(int i=0;i<M;i++){
for(int j=0;j<K;j++){
printf("%0.1f ",h_c[i][j] );
}
printf("\n" );
}*/
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "Tiled_Mat_Mul.hip"
.globl _Z21__device_stub__matMulPdS_S_iii # -- Begin function _Z21__device_stub__matMulPdS_S_iii
.p2align 4, 0x90
.type _Z21__device_stub__matMulPdS_S_iii,@function
_Z21__device_stub__matMulPdS_S_iii: # @_Z21__device_stub__matMulPdS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6matMulPdS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z21__device_stub__matMulPdS_S_iii, .Lfunc_end0-_Z21__device_stub__matMulPdS_S_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $15360176, %rsp # imm = 0xEA60B0
.cfi_def_cfa_offset 15360208
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 5120176(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # %.preheader57
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%r15,8)
incq %r15
cmpq $800, %r15 # imm = 0x320
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r14
addq $6400, %rbx # imm = 0x1900
cmpq $800, %r14 # imm = 0x320
jne .LBB1_1
# %bb.4: # %.preheader.preheader
leaq 176(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%r15,8)
incq %r15
cmpq $800, %r15 # imm = 0x320
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
incq %r14
addq $6400, %rbx # imm = 0x1900
cmpq $800, %r14 # imm = 0x320
jne .LBB1_5
# %bb.8:
leaq 32(%rsp), %rdi
movl $5120000, %esi # imm = 0x4E2000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $5120000, %esi # imm = 0x4E2000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $5120000, %esi # imm = 0x4E2000
callq hipMalloc
movq 32(%rsp), %rdi
leaq 5120176(%rsp), %rsi
movl $5120000, %edx # imm = 0x4E2000
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $5120000, %edx # imm = 0x4E2000
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $107374182425, %rdi # imm = 0x1900000019
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $800, 52(%rsp) # imm = 0x320
movl $800, 48(%rsp) # imm = 0x320
movl $800, 44(%rsp) # imm = 0x320
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z6matMulPdS_S_iii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
leaq 10240176(%rsp), %rbx
movl $5120000, %edx # imm = 0x4E2000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rsi
movl $5120000, %edx # imm = 0x4E2000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $15360176, %rsp # imm = 0xEA60B0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matMulPdS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matMulPdS_S_iii,@object # @_Z6matMulPdS_S_iii
.section .rodata,"a",@progbits
.globl _Z6matMulPdS_S_iii
.p2align 3, 0x0
_Z6matMulPdS_S_iii:
.quad _Z21__device_stub__matMulPdS_S_iii
.size _Z6matMulPdS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nTime:%f "
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matMulPdS_S_iii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matMulPdS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matMulPdS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6matMulPdS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ HFMA2.MMA R17, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff117435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002200 */
/*0060*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*0070*/ ISETP.GE.AND P0, PT, R4, 0x20, PT ; /* 0x000000200400780c */
/* 0x000fe40003f06270 */
/*0080*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0090*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*00a0*/ IMAD R3, R3, c[0x0][0x4], R7 ; /* 0x0000010003037a24 */
/* 0x001fc400078e0207 */
/*00b0*/ IMAD R2, R5, c[0x0][0x0], R0 ; /* 0x0000000005027a24 */
/* 0x002fc800078e0200 */
/*00c0*/ IMAD R16, R3, c[0x0][0x180], R2 ; /* 0x0000600003107a24 */
/* 0x000fc800078e0202 */
/*00d0*/ IMAD.WIDE R16, R16, R17, c[0x0][0x170] ; /* 0x00005c0010107625 */
/* 0x000fe200078e0211 */
/*00e0*/ @!P0 BRA 0x770 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*00f0*/ SHF.R.S32.HI R4, RZ, 0x1f, R4 ; /* 0x0000001fff047819 */
/* 0x000fe20000011404 */
/*0100*/ IMAD R2, R7.reuse, c[0x0][0x180], R2 ; /* 0x0000600007027a24 */
/* 0x040fe200078e0202 */
/*0110*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*0120*/ IMAD.SHL.U32 R7, R7, 0x100, RZ ; /* 0x0000010007077824 */
/* 0x000fe200078e00ff */
/*0130*/ LEA.HI R4, R4, c[0x0][0x17c], RZ, 0x5 ; /* 0x00005f0004047a11 */
/* 0x000fe200078f28ff */
/*0140*/ IMAD R3, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003037a24 */
/* 0x000fe200078e0200 */
/*0150*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0160*/ LEA R5, R0, R7, 0x3 ; /* 0x0000000700057211 */
/* 0x000fe400078e18ff */
/*0170*/ SHF.R.S32.HI R4, RZ, 0x5, R4 ; /* 0x00000005ff047819 */
/* 0x000fc40000011404 */
/*0180*/ IMAD.MOV.U32 R8, RZ, RZ, 0x8 ; /* 0x00000008ff087424 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE.U32 R28, R3, R8, c[0x0][0x160] ; /* 0x00005800031c7625 */
/* 0x000fc800078e0008 */
/*01a0*/ IMAD.WIDE.U32 R8, R2, R8, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fe400078e0008 */
/*01b0*/ LDG.E.64 R28, [R28.64] ; /* 0x000000061c1c7981 */
/* 0x000ea8000c1e1b00 */
/*01c0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ee2000c1e1b00 */
/*01d0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*01e0*/ IADD3 R3, R3, 0x20, RZ ; /* 0x0000002003037810 */
/* 0x000fca0007ffe0ff */
/*01f0*/ ISETP.LE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fe2000bf03270 */
/*0200*/ STS.64 [R5], R28 ; /* 0x0000001c05007388 */
/* 0x004fe80000000a00 */
/*0210*/ STS.64 [R5+0x2000], R8 ; /* 0x0020000805007388 */
/* 0x008fe80000000a00 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0230*/ LDS.64 R22, [R0.X8+0x2000] ; /* 0x0020000000167984 */
/* 0x000fe80000008a00 */
/*0240*/ LDS.128 R12, [R7] ; /* 0x00000000070c7984 */
/* 0x000e280000000c00 */
/*0250*/ LDS.64 R18, [R0.X8+0x2100] ; /* 0x0021000000127984 */
/* 0x000e680000008a00 */
/*0260*/ LDS.64 R20, [R0.X8+0x2200] ; /* 0x0022000000147984 */
/* 0x000fe80000008a00 */
/*0270*/ LDS.128 R8, [R7+0x10] ; /* 0x0000100007087984 */
/* 0x000ea80000000c00 */
/*0280*/ LDS.64 R26, [R0.X8+0x2300] ; /* 0x00230000001a7984 */
/* 0x000ee20000008a00 */
/*0290*/ DFMA R22, R22, R12, R24 ; /* 0x0000000c1616722b */
/* 0x0010460000000018 */
/*02a0*/ LDS.64 R24, [R0.X8+0x2700] ; /* 0x0027000000187984 */
/* 0x001fe60000008a00 */
/*02b0*/ DFMA R22, R18, R14, R22 ; /* 0x0000000e1216722b */
/* 0x0020a40000000016 */
/*02c0*/ LDS.64 R18, [R0.X8+0x2400] ; /* 0x0024000000127984 */
/* 0x001fe80000008a00 */
/*02d0*/ LDS.128 R12, [R7+0x20] ; /* 0x00002000070c7984 */
/* 0x000e220000000c00 */
/*02e0*/ DFMA R8, R20, R8, R22 ; /* 0x000000081408722b */
/* 0x0042c60000000016 */
/*02f0*/ LDS.64 R22, [R0.X8+0x2500] ; /* 0x0025000000167984 */
/* 0x002e660000008a00 */
/*0300*/ DFMA R26, R26, R10, R8 ; /* 0x0000000a1a1a722b */
/* 0x0084220000000008 */
/*0310*/ LDS.64 R20, [R0.X8+0x2600] ; /* 0x0026000000147984 */
/* 0x000fe80000008a00 */
/*0320*/ LDS.128 R8, [R7+0x30] ; /* 0x0000300007087984 */
/* 0x004ea20000000c00 */
/*0330*/ DFMA R12, R18, R12, R26 ; /* 0x0000000c120c722b */
/* 0x001046000000001a */
/*0340*/ LDS.64 R18, [R0.X8+0x2800] ; /* 0x0028000000127984 */
/* 0x001fe60000008a00 */
/*0350*/ DFMA R22, R22, R14, R12 ; /* 0x0000000e1616722b */
/* 0x0020a2000000000c */
/*0360*/ LDS.64 R26, [R0.X8+0x2b00] ; /* 0x002b0000001a7984 */
/* 0x000fe80000008a00 */
/*0370*/ LDS.128 R12, [R7+0x40] ; /* 0x00004000070c7984 */
/* 0x001e220000000c00 */
/*0380*/ DFMA R8, R20, R8, R22 ; /* 0x000000081408722b */
/* 0x0042860000000016 */
/*0390*/ LDS.64 R20, [R0.X8+0x2a00] ; /* 0x002a000000147984 */
/* 0x002fe60000008a00 */
/*03a0*/ DFMA R24, R24, R10, R8 ; /* 0x0000000a1818722b */
/* 0x0042220000000008 */
/*03b0*/ LDS.64 R22, [R0.X8+0x2900] ; /* 0x0029000000167984 */
/* 0x000ea80000008a00 */
/*03c0*/ LDS.128 R8, [R7+0x50] ; /* 0x0000500007087984 */
/* 0x002e620000000c00 */
/*03d0*/ DFMA R12, R18, R12, R24 ; /* 0x0000000c120c722b */
/* 0x0010860000000018 */
/*03e0*/ LDS.64 R18, [R0.X8+0x2c00] ; /* 0x002c000000127984 */
/* 0x001fe80000008a00 */
/*03f0*/ LDS.64 R24, [R0.X8+0x2f00] ; /* 0x002f000000187984 */
/* 0x000fe20000008a00 */
/*0400*/ DFMA R22, R22, R14, R12 ; /* 0x0000000e1616722b */
/* 0x004046000000000c */
/*0410*/ LDS.128 R12, [R7+0x60] ; /* 0x00006000070c7984 */
/* 0x001e260000000c00 */
/*0420*/ DFMA R8, R20, R8, R22 ; /* 0x000000081408722b */
/* 0x0022a40000000016 */
/*0430*/ LDS.64 R20, [R0.X8+0x2e00] ; /* 0x002e000000147984 */
/* 0x002fe80000008a00 */
/*0440*/ LDS.64 R22, [R0.X8+0x2d00] ; /* 0x002d000000167984 */
/* 0x000e620000008a00 */
/*0450*/ DFMA R26, R26, R10, R8 ; /* 0x0000000a1a1a722b */
/* 0x0044060000000008 */
/*0460*/ LDS.128 R8, [R7+0x70] ; /* 0x0000700007087984 */
/* 0x004ea60000000c00 */
/*0470*/ DFMA R12, R18, R12, R26 ; /* 0x0000000c120c722b */
/* 0x001064000000001a */
/*0480*/ LDS.64 R18, [R0.X8+0x3000] ; /* 0x0030000000127984 */
/* 0x001fe80000008a00 */
/*0490*/ LDS.64 R26, [R0.X8+0x3300] ; /* 0x00330000001a7984 */
/* 0x000fe20000008a00 */
/*04a0*/ DFMA R22, R22, R14, R12 ; /* 0x0000000e1616722b */
/* 0x002086000000000c */
/*04b0*/ LDS.128 R12, [R7+0x80] ; /* 0x00008000070c7984 */
/* 0x001e260000000c00 */
/*04c0*/ DFMA R8, R20, R8, R22 ; /* 0x000000081408722b */
/* 0x0042a40000000016 */
/*04d0*/ LDS.64 R20, [R0.X8+0x3200] ; /* 0x0032000000147984 */
/* 0x002fe80000008a00 */
/*04e0*/ LDS.64 R22, [R0.X8+0x3100] ; /* 0x0031000000167984 */
/* 0x000e620000008a00 */
/*04f0*/ DFMA R24, R24, R10, R8 ; /* 0x0000000a1818722b */
/* 0x0044060000000008 */
/*0500*/ LDS.128 R8, [R7+0x90] ; /* 0x0000900007087984 */
/* 0x004ea60000000c00 */
/*0510*/ DFMA R12, R18, R12, R24 ; /* 0x0000000c120c722b */
/* 0x0010640000000018 */
/*0520*/ LDS.64 R18, [R0.X8+0x3400] ; /* 0x0034000000127984 */
/* 0x001fe80000008a00 */
/*0530*/ LDS.64 R24, [R0.X8+0x3700] ; /* 0x0037000000187984 */
/* 0x000fe20000008a00 */
/*0540*/ DFMA R22, R22, R14, R12 ; /* 0x0000000e1616722b */
/* 0x002086000000000c */
/*0550*/ LDS.128 R12, [R7+0xa0] ; /* 0x0000a000070c7984 */
/* 0x001e260000000c00 */
/*0560*/ DFMA R8, R20, R8, R22 ; /* 0x000000081408722b */
/* 0x0042a40000000016 */
/*0570*/ LDS.64 R20, [R0.X8+0x3600] ; /* 0x0036000000147984 */
/* 0x002fe80000008a00 */
/*0580*/ LDS.64 R22, [R0.X8+0x3500] ; /* 0x0035000000167984 */
/* 0x000e620000008a00 */
/*0590*/ DFMA R26, R26, R10, R8 ; /* 0x0000000a1a1a722b */
/* 0x0044060000000008 */
/*05a0*/ LDS.128 R8, [R7+0xb0] ; /* 0x0000b00007087984 */
/* 0x004ea60000000c00 */
/*05b0*/ DFMA R12, R18, R12, R26 ; /* 0x0000000c120c722b */
/* 0x001064000000001a */
/*05c0*/ LDS.64 R18, [R0.X8+0x3800] ; /* 0x0038000000127984 */
/* 0x001fe80000008a00 */
/*05d0*/ LDS.64 R26, [R0.X8+0x3b00] ; /* 0x003b0000001a7984 */
/* 0x000fe20000008a00 */
/*05e0*/ DFMA R22, R22, R14, R12 ; /* 0x0000000e1616722b */
/* 0x002086000000000c */
/*05f0*/ LDS.128 R12, [R7+0xc0] ; /* 0x0000c000070c7984 */
/* 0x001e260000000c00 */
/*0600*/ DFMA R8, R20, R8, R22 ; /* 0x000000081408722b */
/* 0x0042a40000000016 */
/*0610*/ LDS.64 R20, [R0.X8+0x3a00] ; /* 0x003a000000147984 */
/* 0x002fe80000008a00 */
/*0620*/ LDS.64 R22, [R0.X8+0x3900] ; /* 0x0039000000167984 */
/* 0x000e620000008a00 */
/*0630*/ DFMA R24, R24, R10, R8 ; /* 0x0000000a1818722b */
/* 0x0044060000000008 */
/*0640*/ LDS.128 R8, [R7+0xd0] ; /* 0x0000d00007087984 */
/* 0x004ea60000000c00 */
/*0650*/ DFMA R12, R18, R12, R24 ; /* 0x0000000c120c722b */
/* 0x0010640000000018 */
/*0660*/ LDS.64 R18, [R0.X8+0x3c00] ; /* 0x003c000000127984 */
/* 0x001fe80000008a00 */
/*0670*/ LDS.64 R24, [R0.X8+0x3e00] ; /* 0x003e000000187984 */
/* 0x000fe20000008a00 */
/*0680*/ DFMA R22, R22, R14, R12 ; /* 0x0000000e1616722b */
/* 0x002086000000000c */
/*0690*/ LDS.128 R12, [R7+0xe0] ; /* 0x0000e000070c7984 */
/* 0x001e260000000c00 */
/*06a0*/ DFMA R8, R20, R8, R22 ; /* 0x000000081408722b */
/* 0x0042a40000000016 */
/*06b0*/ LDS.64 R20, [R0.X8+0x3d00] ; /* 0x003d000000147984 */
/* 0x002e680000008a00 */
/*06c0*/ DFMA R26, R26, R10, R8 ; /* 0x0000000a1a1a722b */
/* 0x0044220000000008 */
/*06d0*/ LDS.64 R22, [R0.X8+0x3f00] ; /* 0x003f000000167984 */
/* 0x000fe80000008a00 */
/*06e0*/ LDS.128 R8, [R7+0xf0] ; /* 0x0000f00007087984 */
/* 0x004ea20000000c00 */
/*06f0*/ DFMA R12, R18, R12, R26 ; /* 0x0000000c120c722b */
/* 0x001e4c000000001a */
/*0700*/ DFMA R12, R20, R14, R12 ; /* 0x0000000e140c722b */
/* 0x002e8c000000000c */
/*0710*/ DFMA R24, R24, R8, R12 ; /* 0x000000081818722b */
/* 0x004064000000000c */
/*0720*/ MOV R9, c[0x0][0x180] ; /* 0x0000600000097a02 */
/* 0x001fc80000000f00 */
/*0730*/ DFMA R24, R22, R10, R24 ; /* 0x0000000a1618722b */
/* 0x0020620000000018 */
/*0740*/ LEA R2, R9, R2, 0x5 ; /* 0x0000000209027211 */
/* 0x000fe200078e28ff */
/*0750*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0760*/ @!P0 BRA 0x180 ; /* 0xfffffa1000008947 */
/* 0x003fea000383ffff */
/*0770*/ STG.E.64 [R16.64], R24 ; /* 0x0000001810007986 */
/* 0x000fe2000c101b06 */
/*0780*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0790*/ BRA 0x790; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matMulPdS_S_iii
.globl _Z6matMulPdS_S_iii
.p2align 8
.type _Z6matMulPdS_S_iii,@function
_Z6matMulPdS_S_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x1c
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v8, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s5, v[3:4]
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_mad_u64_u32 v[1:2], null, s14, s4, v[8:9]
s_cmp_lt_i32 s2, 32
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 3, v8
v_lshlrev_b32_e32 v2, 8, v3
s_ashr_i32 s8, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_lshr_b32 s8, s8, 27
v_or_b32_e32 v9, 0x2000, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v10, v2, v4
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_add_i32 s8, s2, s8
v_mad_u64_u32 v[6:7], null, v0, s2, v[8:9]
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v11, v9, v2
s_ashr_i32 s2, s8, 5
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s9, s8, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v14, s9, v3
v_add_nc_u32_e32 v7, s9, v6
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[12:13], null, v14, s3, v[1:2]
v_mov_b32_e32 v13, v8
v_lshlrev_b64 v[14:15], 3, v[7:8]
v_mov_b32_e32 v7, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[12:13], 3, v[12:13]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v14, vcc_lo, s4, v14
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
v_add_co_u32 v12, vcc_lo, s6, v12
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
global_load_b64 v[14:15], v[14:15], off
global_load_b64 v[12:13], v[12:13], off
s_waitcnt vmcnt(1)
ds_store_b64 v10, v[14:15]
s_waitcnt vmcnt(0)
ds_store_b64 v11, v[12:13]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v14, s9, v2
s_add_i32 s9, s9, 8
ds_load_b64 v[12:13], v7
ds_load_b64 v[14:15], v14
v_add_nc_u32_e32 v7, 0x100, v7
s_cmpk_eq_i32 s9, 0x100
s_waitcnt lgkmcnt(0)
v_fma_f64 v[4:5], v[14:15], v[12:13], v[4:5]
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[4:5], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matMulPdS_S_iii
.amdhsa_group_segment_fixed_size 16384
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matMulPdS_S_iii, .Lfunc_end0-_Z6matMulPdS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 16384
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matMulPdS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matMulPdS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001a19e_00000000-6_Tiled_Mat_Mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6matMulPdS_S_iiiPdS_S_iii
.type _Z32__device_stub__Z6matMulPdS_S_iiiPdS_S_iii, @function
_Z32__device_stub__Z6matMulPdS_S_iiiPdS_S_iii:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6matMulPdS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z6matMulPdS_S_iiiPdS_S_iii, .-_Z32__device_stub__Z6matMulPdS_S_iiiPdS_S_iii
.globl _Z6matMulPdS_S_iii
.type _Z6matMulPdS_S_iii, @function
_Z6matMulPdS_S_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6matMulPdS_S_iiiPdS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6matMulPdS_S_iii, .-_Z6matMulPdS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\nTime:%f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $104, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq -5120000(%rsp), %rax
.L12:
cmpq %rax, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rsp, %r14
leaq -5120000(%rsp), %rax
.L15:
cmpq %rax, %rsp
je .L16
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L15
.L16:
movq %rsp, %r13
leaq -5120000(%rsp), %rax
.L18:
cmpq %rax, %rsp
je .L19
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L18
.L19:
movq %rsp, -136(%rbp)
leaq 6400(%r14), %r12
leaq 5126400(%r14), %r15
.L21:
leaq -6400(%r12), %rbx
.L22:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L22
addq $6400, %r12
cmpq %r15, %r12
jne .L21
leaq 6400(%r13), %r12
leaq 5126400(%r13), %r15
.L23:
leaq -6400(%r12), %rbx
.L24:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L24
addq $6400, %r12
cmpq %r15, %r12
jne .L23
movl $32, -80(%rbp)
movl $32, -76(%rbp)
movl $1, -72(%rbp)
movl $25, -68(%rbp)
movl $25, -64(%rbp)
movl $1, -60(%rbp)
leaq -120(%rbp), %rdi
movl $5120000, %esi
call cudaMalloc@PLT
leaq -112(%rbp), %rdi
movl $5120000, %esi
call cudaMalloc@PLT
leaq -104(%rbp), %rdi
movl $5120000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $5120000, %edx
movq %r14, %rsi
movq -120(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $5120000, %edx
movq %r13, %rsi
movq -112(%rbp), %rdi
call cudaMemcpy@PLT
leaq -96(%rbp), %rdi
call cudaEventCreate@PLT
leaq -88(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -96(%rbp), %rdi
call cudaEventRecord@PLT
movl -72(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -80(%rbp), %rdx
movq -68(%rbp), %rdi
movl -60(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L26:
movl $0, %esi
movq -88(%rbp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $5120000, %edx
movq -104(%rbp), %rsi
movq -136(%rbp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq -88(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -124(%rbp), %rdi
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd -124(%rbp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -96(%rbp), %rdi
call cudaEventDestroy@PLT
movq -88(%rbp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $5120000, %edx
movq -104(%rbp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq -120(%rbp), %rdi
call cudaFree@PLT
movq -112(%rbp), %rdi
call cudaFree@PLT
movq -104(%rbp), %rdi
call cudaFree@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L32:
.cfi_restore_state
movl $800, %r9d
movl $800, %r8d
movl $800, %ecx
movq -104(%rbp), %rdx
movq -112(%rbp), %rsi
movq -120(%rbp), %rdi
call _Z32__device_stub__Z6matMulPdS_S_iiiPdS_S_iii
jmp .L26
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6matMulPdS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matMulPdS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Tiled_Mat_Mul.hip"
.globl _Z21__device_stub__matMulPdS_S_iii # -- Begin function _Z21__device_stub__matMulPdS_S_iii
.p2align 4, 0x90
.type _Z21__device_stub__matMulPdS_S_iii,@function
_Z21__device_stub__matMulPdS_S_iii: # @_Z21__device_stub__matMulPdS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6matMulPdS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z21__device_stub__matMulPdS_S_iii, .Lfunc_end0-_Z21__device_stub__matMulPdS_S_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $15360176, %rsp # imm = 0xEA60B0
.cfi_def_cfa_offset 15360208
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 5120176(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # %.preheader57
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%r15,8)
incq %r15
cmpq $800, %r15 # imm = 0x320
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r14
addq $6400, %rbx # imm = 0x1900
cmpq $800, %r14 # imm = 0x320
jne .LBB1_1
# %bb.4: # %.preheader.preheader
leaq 176(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%r15,8)
incq %r15
cmpq $800, %r15 # imm = 0x320
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
incq %r14
addq $6400, %rbx # imm = 0x1900
cmpq $800, %r14 # imm = 0x320
jne .LBB1_5
# %bb.8:
leaq 32(%rsp), %rdi
movl $5120000, %esi # imm = 0x4E2000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $5120000, %esi # imm = 0x4E2000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $5120000, %esi # imm = 0x4E2000
callq hipMalloc
movq 32(%rsp), %rdi
leaq 5120176(%rsp), %rsi
movl $5120000, %edx # imm = 0x4E2000
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $5120000, %edx # imm = 0x4E2000
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $107374182425, %rdi # imm = 0x1900000019
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $800, 52(%rsp) # imm = 0x320
movl $800, 48(%rsp) # imm = 0x320
movl $800, 44(%rsp) # imm = 0x320
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z6matMulPdS_S_iii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
leaq 10240176(%rsp), %rbx
movl $5120000, %edx # imm = 0x4E2000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rsi
movl $5120000, %edx # imm = 0x4E2000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $15360176, %rsp # imm = 0xEA60B0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matMulPdS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matMulPdS_S_iii,@object # @_Z6matMulPdS_S_iii
.section .rodata,"a",@progbits
.globl _Z6matMulPdS_S_iii
.p2align 3, 0x0
_Z6matMulPdS_S_iii:
.quad _Z21__device_stub__matMulPdS_S_iii
.size _Z6matMulPdS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nTime:%f "
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matMulPdS_S_iii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matMulPdS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matMulPdS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C" void cuda_add_vector( float* a, float* b, float *c, int size );
__global__ void VectorAdd( float* arrayA, float* arrayB, float* output )
{
int idx = threadIdx.x;
output[idx] = arrayA[idx] + arrayB[idx];
}
void cuda_add_vector( float* a, float* b, float *c, int size )
{
int data_size = size * sizeof(float);
// part1, allocate data on device
float *dev_A, *dev_B, *dev_C;
cudaMalloc( (void**)&dev_A, data_size );
cudaMalloc( (void**)&dev_B, data_size );
cudaMalloc( (void**)&dev_C, data_size );
// part2, copy memory to device
cudaMemcpy( dev_A, a, data_size, cudaMemcpyHostToDevice );
cudaMemcpy( dev_B, b, data_size, cudaMemcpyHostToDevice );
// part3, run kernel
VectorAdd<<< 1, size >>>( dev_A, dev_B, dev_C );
// part4, copy data from device
cudaMemcpy( c, dev_C, data_size, cudaMemcpyDeviceToHost );
// part5, release data
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_C);
} | code for sm_80
Function : _Z9VectorAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" void cuda_add_vector( float* a, float* b, float *c, int size );
__global__ void VectorAdd( float* arrayA, float* arrayB, float* output )
{
int idx = threadIdx.x;
output[idx] = arrayA[idx] + arrayB[idx];
}
void cuda_add_vector( float* a, float* b, float *c, int size )
{
int data_size = size * sizeof(float);
// part1, allocate data on device
float *dev_A, *dev_B, *dev_C;
cudaMalloc( (void**)&dev_A, data_size );
cudaMalloc( (void**)&dev_B, data_size );
cudaMalloc( (void**)&dev_C, data_size );
// part2, copy memory to device
cudaMemcpy( dev_A, a, data_size, cudaMemcpyHostToDevice );
cudaMemcpy( dev_B, b, data_size, cudaMemcpyHostToDevice );
// part3, run kernel
VectorAdd<<< 1, size >>>( dev_A, dev_B, dev_C );
// part4, copy data from device
cudaMemcpy( c, dev_C, data_size, cudaMemcpyDeviceToHost );
// part5, release data
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_C);
} | .file "tmpxft_001232be_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_
.type _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_, @function
_Z32__device_stub__Z9VectorAddPfS_S_PfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9VectorAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_, .-_Z32__device_stub__Z9VectorAddPfS_S_PfS_S_
.globl _Z9VectorAddPfS_S_
.type _Z9VectorAddPfS_S_, @function
_Z9VectorAddPfS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z9VectorAddPfS_S_, .-_Z9VectorAddPfS_S_
.globl cuda_add_vector
.type cuda_add_vector, @function
cuda_add_vector:
.LFB2027:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rcx,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size cuda_add_vector, .-cuda_add_vector
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9VectorAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9VectorAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" void cuda_add_vector( float* a, float* b, float *c, int size );
__global__ void VectorAdd( float* arrayA, float* arrayB, float* output )
{
int idx = threadIdx.x;
output[idx] = arrayA[idx] + arrayB[idx];
}
void cuda_add_vector( float* a, float* b, float *c, int size )
{
int data_size = size * sizeof(float);
// part1, allocate data on device
float *dev_A, *dev_B, *dev_C;
cudaMalloc( (void**)&dev_A, data_size );
cudaMalloc( (void**)&dev_B, data_size );
cudaMalloc( (void**)&dev_C, data_size );
// part2, copy memory to device
cudaMemcpy( dev_A, a, data_size, cudaMemcpyHostToDevice );
cudaMemcpy( dev_B, b, data_size, cudaMemcpyHostToDevice );
// part3, run kernel
VectorAdd<<< 1, size >>>( dev_A, dev_B, dev_C );
// part4, copy data from device
cudaMemcpy( c, dev_C, data_size, cudaMemcpyDeviceToHost );
// part5, release data
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_C);
} | #include <hip/hip_runtime.h>
extern "C" void cuda_add_vector( float* a, float* b, float *c, int size );
__global__ void VectorAdd( float* arrayA, float* arrayB, float* output )
{
int idx = threadIdx.x;
output[idx] = arrayA[idx] + arrayB[idx];
}
void cuda_add_vector( float* a, float* b, float *c, int size )
{
int data_size = size * sizeof(float);
// part1, allocate data on device
float *dev_A, *dev_B, *dev_C;
hipMalloc( (void**)&dev_A, data_size );
hipMalloc( (void**)&dev_B, data_size );
hipMalloc( (void**)&dev_C, data_size );
// part2, copy memory to device
hipMemcpy( dev_A, a, data_size, hipMemcpyHostToDevice );
hipMemcpy( dev_B, b, data_size, hipMemcpyHostToDevice );
// part3, run kernel
VectorAdd<<< 1, size >>>( dev_A, dev_B, dev_C );
// part4, copy data from device
hipMemcpy( c, dev_C, data_size, hipMemcpyDeviceToHost );
// part5, release data
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" void cuda_add_vector( float* a, float* b, float *c, int size );
__global__ void VectorAdd( float* arrayA, float* arrayB, float* output )
{
int idx = threadIdx.x;
output[idx] = arrayA[idx] + arrayB[idx];
}
void cuda_add_vector( float* a, float* b, float *c, int size )
{
int data_size = size * sizeof(float);
// part1, allocate data on device
float *dev_A, *dev_B, *dev_C;
hipMalloc( (void**)&dev_A, data_size );
hipMalloc( (void**)&dev_B, data_size );
hipMalloc( (void**)&dev_C, data_size );
// part2, copy memory to device
hipMemcpy( dev_A, a, data_size, hipMemcpyHostToDevice );
hipMemcpy( dev_B, b, data_size, hipMemcpyHostToDevice );
// part3, run kernel
VectorAdd<<< 1, size >>>( dev_A, dev_B, dev_C );
// part4, copy data from device
hipMemcpy( c, dev_C, data_size, hipMemcpyDeviceToHost );
// part5, release data
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_C);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9VectorAddPfS_S_
.globl _Z9VectorAddPfS_S_
.p2align 8
.type _Z9VectorAddPfS_S_,@function
_Z9VectorAddPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9VectorAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9VectorAddPfS_S_, .Lfunc_end0-_Z9VectorAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9VectorAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9VectorAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" void cuda_add_vector( float* a, float* b, float *c, int size );
__global__ void VectorAdd( float* arrayA, float* arrayB, float* output )
{
int idx = threadIdx.x;
output[idx] = arrayA[idx] + arrayB[idx];
}
void cuda_add_vector( float* a, float* b, float *c, int size )
{
int data_size = size * sizeof(float);
// part1, allocate data on device
float *dev_A, *dev_B, *dev_C;
hipMalloc( (void**)&dev_A, data_size );
hipMalloc( (void**)&dev_B, data_size );
hipMalloc( (void**)&dev_C, data_size );
// part2, copy memory to device
hipMemcpy( dev_A, a, data_size, hipMemcpyHostToDevice );
hipMemcpy( dev_B, b, data_size, hipMemcpyHostToDevice );
// part3, run kernel
VectorAdd<<< 1, size >>>( dev_A, dev_B, dev_C );
// part4, copy data from device
hipMemcpy( c, dev_C, data_size, hipMemcpyDeviceToHost );
// part5, release data
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_C);
} | .text
.file "vector_add.hip"
.globl _Z24__device_stub__VectorAddPfS_S_ # -- Begin function _Z24__device_stub__VectorAddPfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__VectorAddPfS_S_,@function
_Z24__device_stub__VectorAddPfS_S_: # @_Z24__device_stub__VectorAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9VectorAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__VectorAddPfS_S_, .Lfunc_end0-_Z24__device_stub__VectorAddPfS_S_
.cfi_endproc
# -- End function
.globl cuda_add_vector # -- Begin function cuda_add_vector
.p2align 4, 0x90
.type cuda_add_vector,@function
cuda_add_vector: # @cuda_add_vector
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r15d, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9VectorAddPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size cuda_add_vector, .Lfunc_end1-cuda_add_vector
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9VectorAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9VectorAddPfS_S_,@object # @_Z9VectorAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z9VectorAddPfS_S_
.p2align 3, 0x0
_Z9VectorAddPfS_S_:
.quad _Z24__device_stub__VectorAddPfS_S_
.size _Z9VectorAddPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9VectorAddPfS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__VectorAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9VectorAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9VectorAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9VectorAddPfS_S_
.globl _Z9VectorAddPfS_S_
.p2align 8
.type _Z9VectorAddPfS_S_,@function
_Z9VectorAddPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9VectorAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9VectorAddPfS_S_, .Lfunc_end0-_Z9VectorAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9VectorAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9VectorAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001232be_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_
.type _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_, @function
_Z32__device_stub__Z9VectorAddPfS_S_PfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9VectorAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_, .-_Z32__device_stub__Z9VectorAddPfS_S_PfS_S_
.globl _Z9VectorAddPfS_S_
.type _Z9VectorAddPfS_S_, @function
_Z9VectorAddPfS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z9VectorAddPfS_S_, .-_Z9VectorAddPfS_S_
.globl cuda_add_vector
.type cuda_add_vector, @function
cuda_add_vector:
.LFB2027:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rcx,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size cuda_add_vector, .-cuda_add_vector
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9VectorAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9VectorAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_add.hip"
.globl _Z24__device_stub__VectorAddPfS_S_ # -- Begin function _Z24__device_stub__VectorAddPfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__VectorAddPfS_S_,@function
_Z24__device_stub__VectorAddPfS_S_: # @_Z24__device_stub__VectorAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9VectorAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__VectorAddPfS_S_, .Lfunc_end0-_Z24__device_stub__VectorAddPfS_S_
.cfi_endproc
# -- End function
.globl cuda_add_vector # -- Begin function cuda_add_vector
.p2align 4, 0x90
.type cuda_add_vector,@function
cuda_add_vector: # @cuda_add_vector
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r15d, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9VectorAddPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size cuda_add_vector, .Lfunc_end1-cuda_add_vector
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9VectorAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9VectorAddPfS_S_,@object # @_Z9VectorAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z9VectorAddPfS_S_
.p2align 3, 0x0
_Z9VectorAddPfS_S_:
.quad _Z24__device_stub__VectorAddPfS_S_
.size _Z9VectorAddPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9VectorAddPfS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__VectorAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9VectorAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
struct SharedMemory
{
__device__ inline operator float *()
{
extern __shared__ int __smem[];
return (float *)__smem;
}
__device__ inline operator const float *() const
{
extern __shared__ int __smem[];
return (float *)__smem;
}
};
__global__ void
reduce3(float *g_idata, float *g_odata, unsigned int n)
{
float *sdata = SharedMemory();
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockDim.x*2) + threadIdx.x;
float mySum = (i < n) ? g_idata[i] : 0;
if (i + blockDim.x < n)
mySum += g_idata[i+blockDim.x];
sdata[tid] = mySum;
__syncthreads();
// do reduction in shared mem
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (tid < s)
{
sdata[tid] = mySum = mySum + sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = mySum;
}
int main(int argc, char* argv[]) {
return 0;
} | code for sm_80
Function : _Z7reduce3PfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0040*/ USHF.L.U32 UR5, UR4, 0x1, URZ ; /* 0x0000000104057899 */
/* 0x000fe2000800063f */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ IMAD R2, R6, UR5, R8 ; /* 0x0000000506027c24 */
/* 0x001fca000f8e0208 */
/*0080*/ IADD3 R4, R2.reuse, c[0x0][0x0], RZ ; /* 0x0000000002047a10 */
/* 0x040fe40007ffe0ff */
/*0090*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f26070 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fd60003f06070 */
/*00b0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */
/* 0x000fe400078e00ff */
/*00c0*/ @!P0 MOV R5, 0x4 ; /* 0x0000000400058802 */
/* 0x000fe40000000f00 */
/*00d0*/ @!P1 IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002029625 */
/* 0x000fc800078e0003 */
/*00e0*/ @!P0 IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004048625 */
/* 0x000fe200078e0005 */
/*00f0*/ @!P1 LDG.E R7, [R2.64] ; /* 0x0000000602079981 */
/* 0x000eaa000c1e1900 */
/*0100*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000604048981 */
/* 0x000ea2000c1e1900 */
/*0110*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0120*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fca0003f25270 */
/*0130*/ ISETP.NE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf45270 */
/*0140*/ @!P0 FADD R7, R7, R4 ; /* 0x0000000407078221 */
/* 0x004fca0000000000 */
/*0150*/ STS [R8.X4], R7 ; /* 0x0000000708007388 */
/* 0x0001e80000004800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ @!P2 BRA 0x230 ; /* 0x000000b00000a947 */
/* 0x000fea0003800000 */
/*0180*/ SHF.L.U32 R0, R8, 0x2, RZ ; /* 0x0000000208007819 */
/* 0x001fe200000006ff */
/*0190*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f06070 */
/*01b0*/ @!P0 LEA R2, R3, R0, 0x2 ; /* 0x0000000003028211 */
/* 0x000fe400078e10ff */
/*01c0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc80000011603 */
/*01d0*/ @!P0 LDS R2, [R2] ; /* 0x0000000002028984 */
/* 0x000e240000000800 */
/*01e0*/ @!P0 FADD R7, R7, R2 ; /* 0x0000000207078221 */
/* 0x001fca0000000000 */
/*01f0*/ @!P0 STS [R8.X4], R7 ; /* 0x0000000708008388 */
/* 0x0001e80000004800 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0210*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0220*/ @P0 BRA 0x1a0 ; /* 0xffffff7000000947 */
/* 0x001fea000383ffff */
/*0230*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x001fea0003800000 */
/*0240*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0250*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0260*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
struct SharedMemory
{
__device__ inline operator float *()
{
extern __shared__ int __smem[];
return (float *)__smem;
}
__device__ inline operator const float *() const
{
extern __shared__ int __smem[];
return (float *)__smem;
}
};
__global__ void
reduce3(float *g_idata, float *g_odata, unsigned int n)
{
float *sdata = SharedMemory();
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockDim.x*2) + threadIdx.x;
float mySum = (i < n) ? g_idata[i] : 0;
if (i + blockDim.x < n)
mySum += g_idata[i+blockDim.x];
sdata[tid] = mySum;
__syncthreads();
// do reduction in shared mem
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (tid < s)
{
sdata[tid] = mySum = mySum + sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = mySum;
}
int main(int argc, char* argv[]) {
return 0;
} | .file "tmpxft_00150ef0_00000000-6_sum_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE3671:
.size main, .-main
.globl _Z29__device_stub__Z7reduce3PfS_jPfS_j
.type _Z29__device_stub__Z7reduce3PfS_jPfS_j, @function
_Z29__device_stub__Z7reduce3PfS_jPfS_j:
.LFB3696:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7reduce3PfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z29__device_stub__Z7reduce3PfS_jPfS_j, .-_Z29__device_stub__Z7reduce3PfS_jPfS_j
.globl _Z7reduce3PfS_j
.type _Z7reduce3PfS_j, @function
_Z7reduce3PfS_j:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7reduce3PfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z7reduce3PfS_j, .-_Z7reduce3PfS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7reduce3PfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce3PfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
struct SharedMemory
{
__device__ inline operator float *()
{
extern __shared__ int __smem[];
return (float *)__smem;
}
__device__ inline operator const float *() const
{
extern __shared__ int __smem[];
return (float *)__smem;
}
};
__global__ void
reduce3(float *g_idata, float *g_odata, unsigned int n)
{
float *sdata = SharedMemory();
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockDim.x*2) + threadIdx.x;
float mySum = (i < n) ? g_idata[i] : 0;
if (i + blockDim.x < n)
mySum += g_idata[i+blockDim.x];
sdata[tid] = mySum;
__syncthreads();
// do reduction in shared mem
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (tid < s)
{
sdata[tid] = mySum = mySum + sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = mySum;
}
int main(int argc, char* argv[]) {
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
struct SharedMemory
{
__device__ inline operator float *()
{
extern __shared__ int __smem[];
return (float *)__smem;
}
__device__ inline operator const float *() const
{
extern __shared__ int __smem[];
return (float *)__smem;
}
};
__global__ void
reduce3(float *g_idata, float *g_odata, unsigned int n)
{
float *sdata = SharedMemory();
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockDim.x*2) + threadIdx.x;
float mySum = (i < n) ? g_idata[i] : 0;
if (i + blockDim.x < n)
mySum += g_idata[i+blockDim.x];
sdata[tid] = mySum;
__syncthreads();
// do reduction in shared mem
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (tid < s)
{
sdata[tid] = mySum = mySum + sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = mySum;
}
int main(int argc, char* argv[]) {
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
struct SharedMemory
{
__device__ inline operator float *()
{
extern __shared__ int __smem[];
return (float *)__smem;
}
__device__ inline operator const float *() const
{
extern __shared__ int __smem[];
return (float *)__smem;
}
};
__global__ void
reduce3(float *g_idata, float *g_odata, unsigned int n)
{
float *sdata = SharedMemory();
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockDim.x*2) + threadIdx.x;
float mySum = (i < n) ? g_idata[i] : 0;
if (i + blockDim.x < n)
mySum += g_idata[i+blockDim.x];
sdata[tid] = mySum;
__syncthreads();
// do reduction in shared mem
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (tid < s)
{
sdata[tid] = mySum = mySum + sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = mySum;
}
int main(int argc, char* argv[]) {
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7reduce3PfS_j
.globl _Z7reduce3PfS_j
.p2align 8
.type _Z7reduce3PfS_j,@function
_Z7reduce3PfS_j:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s15, s3
v_lshl_add_u32 v1, s7, 1, v0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s6, v1
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s6, v1
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v1
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
.p2align 6
.LBB0_5:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_7
v_lshl_add_u32 v2, s4, 2, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
ds_store_b32 v1, v3
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_lt_u32 s3, 4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
s_mov_b32 s3, s4
s_branch .LBB0_5
.LBB0_9:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v3, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce3PfS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7reduce3PfS_j, .Lfunc_end0-_Z7reduce3PfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce3PfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce3PfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
struct SharedMemory
{
__device__ inline operator float *()
{
extern __shared__ int __smem[];
return (float *)__smem;
}
__device__ inline operator const float *() const
{
extern __shared__ int __smem[];
return (float *)__smem;
}
};
__global__ void
reduce3(float *g_idata, float *g_odata, unsigned int n)
{
float *sdata = SharedMemory();
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockDim.x*2) + threadIdx.x;
float mySum = (i < n) ? g_idata[i] : 0;
if (i + blockDim.x < n)
mySum += g_idata[i+blockDim.x];
sdata[tid] = mySum;
__syncthreads();
// do reduction in shared mem
for (unsigned int s=blockDim.x/2; s>0; s>>=1)
{
if (tid < s)
{
sdata[tid] = mySum = mySum + sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid == 0) g_odata[blockIdx.x] = mySum;
}
int main(int argc, char* argv[]) {
return 0;
} | .text
.file "sum_kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__reduce3PfS_j # -- Begin function _Z22__device_stub__reduce3PfS_j
.p2align 4, 0x90
.type _Z22__device_stub__reduce3PfS_j,@function
_Z22__device_stub__reduce3PfS_j: # @_Z22__device_stub__reduce3PfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7reduce3PfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__reduce3PfS_j, .Lfunc_end0-_Z22__device_stub__reduce3PfS_j
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce3PfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7reduce3PfS_j,@object # @_Z7reduce3PfS_j
.section .rodata,"a",@progbits
.globl _Z7reduce3PfS_j
.p2align 3, 0x0
_Z7reduce3PfS_j:
.quad _Z22__device_stub__reduce3PfS_j
.size _Z7reduce3PfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7reduce3PfS_j"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reduce3PfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reduce3PfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7reduce3PfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0040*/ USHF.L.U32 UR5, UR4, 0x1, URZ ; /* 0x0000000104057899 */
/* 0x000fe2000800063f */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ IMAD R2, R6, UR5, R8 ; /* 0x0000000506027c24 */
/* 0x001fca000f8e0208 */
/*0080*/ IADD3 R4, R2.reuse, c[0x0][0x0], RZ ; /* 0x0000000002047a10 */
/* 0x040fe40007ffe0ff */
/*0090*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f26070 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fd60003f06070 */
/*00b0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */
/* 0x000fe400078e00ff */
/*00c0*/ @!P0 MOV R5, 0x4 ; /* 0x0000000400058802 */
/* 0x000fe40000000f00 */
/*00d0*/ @!P1 IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002029625 */
/* 0x000fc800078e0003 */
/*00e0*/ @!P0 IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004048625 */
/* 0x000fe200078e0005 */
/*00f0*/ @!P1 LDG.E R7, [R2.64] ; /* 0x0000000602079981 */
/* 0x000eaa000c1e1900 */
/*0100*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000604048981 */
/* 0x000ea2000c1e1900 */
/*0110*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0120*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fca0003f25270 */
/*0130*/ ISETP.NE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf45270 */
/*0140*/ @!P0 FADD R7, R7, R4 ; /* 0x0000000407078221 */
/* 0x004fca0000000000 */
/*0150*/ STS [R8.X4], R7 ; /* 0x0000000708007388 */
/* 0x0001e80000004800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ @!P2 BRA 0x230 ; /* 0x000000b00000a947 */
/* 0x000fea0003800000 */
/*0180*/ SHF.L.U32 R0, R8, 0x2, RZ ; /* 0x0000000208007819 */
/* 0x001fe200000006ff */
/*0190*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f06070 */
/*01b0*/ @!P0 LEA R2, R3, R0, 0x2 ; /* 0x0000000003028211 */
/* 0x000fe400078e10ff */
/*01c0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc80000011603 */
/*01d0*/ @!P0 LDS R2, [R2] ; /* 0x0000000002028984 */
/* 0x000e240000000800 */
/*01e0*/ @!P0 FADD R7, R7, R2 ; /* 0x0000000207078221 */
/* 0x001fca0000000000 */
/*01f0*/ @!P0 STS [R8.X4], R7 ; /* 0x0000000708008388 */
/* 0x0001e80000004800 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0210*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0220*/ @P0 BRA 0x1a0 ; /* 0xffffff7000000947 */
/* 0x001fea000383ffff */
/*0230*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x001fea0003800000 */
/*0240*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0250*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0260*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7reduce3PfS_j
.globl _Z7reduce3PfS_j
.p2align 8
.type _Z7reduce3PfS_j,@function
_Z7reduce3PfS_j:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s15, s3
v_lshl_add_u32 v1, s7, 1, v0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s6, v1
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s6, v1
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v1
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
.p2align 6
.LBB0_5:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_7
v_lshl_add_u32 v2, s4, 2, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
ds_store_b32 v1, v3
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_lt_u32 s3, 4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
s_mov_b32 s3, s4
s_branch .LBB0_5
.LBB0_9:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v3, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce3PfS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7reduce3PfS_j, .Lfunc_end0-_Z7reduce3PfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce3PfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce3PfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00150ef0_00000000-6_sum_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE3671:
.size main, .-main
.globl _Z29__device_stub__Z7reduce3PfS_jPfS_j
.type _Z29__device_stub__Z7reduce3PfS_jPfS_j, @function
_Z29__device_stub__Z7reduce3PfS_jPfS_j:
.LFB3696:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7reduce3PfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z29__device_stub__Z7reduce3PfS_jPfS_j, .-_Z29__device_stub__Z7reduce3PfS_jPfS_j
.globl _Z7reduce3PfS_j
.type _Z7reduce3PfS_j, @function
_Z7reduce3PfS_j:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7reduce3PfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z7reduce3PfS_j, .-_Z7reduce3PfS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7reduce3PfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce3PfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sum_kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__reduce3PfS_j # -- Begin function _Z22__device_stub__reduce3PfS_j
.p2align 4, 0x90
.type _Z22__device_stub__reduce3PfS_j,@function
_Z22__device_stub__reduce3PfS_j: # @_Z22__device_stub__reduce3PfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7reduce3PfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__reduce3PfS_j, .Lfunc_end0-_Z22__device_stub__reduce3PfS_j
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce3PfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7reduce3PfS_j,@object # @_Z7reduce3PfS_j
.section .rodata,"a",@progbits
.globl _Z7reduce3PfS_j
.p2align 3, 0x0
_Z7reduce3PfS_j:
.quad _Z22__device_stub__reduce3PfS_j
.size _Z7reduce3PfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7reduce3PfS_j"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reduce3PfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reduce3PfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
__device__ int memr[2048];
__device__ int memg[2048];
__device__ int memb[2048];
__shared__ int mem_out[2048];
__global__ void func() {
int i = blockIdx.x * 256 + threadIdx.x;
// This line is different from the line in our presentation,
// but it works similarly and yields similar results.
mem_out[i] = memr[(i*4 + 1) % 2048] * memr[i*4 % 2048]
+ memg[i*4 % 2048] + memb[i*4 % 2048];
}
int main() {
for (int i = 0; i < 1000000; i++) {
func<<<8, 256>>>();
cudaDeviceSynchronize();
}
return 0;
} | code for sm_80
Function : _Z4funcv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
__device__ int memr[2048];
__device__ int memg[2048];
__device__ int memb[2048];
__shared__ int mem_out[2048];
__global__ void func() {
int i = blockIdx.x * 256 + threadIdx.x;
// This line is different from the line in our presentation,
// but it works similarly and yields similar results.
mem_out[i] = memr[(i*4 + 1) % 2048] * memr[i*4 % 2048]
+ memg[i*4 % 2048] + memb[i*4 % 2048];
}
int main() {
for (int i = 0; i < 1000000; i++) {
func<<<8, 256>>>();
cudaDeviceSynchronize();
}
return 0;
} | .file "tmpxft_0005b81b_00000000-6_memco.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4funcvv
.type _Z22__device_stub__Z4funcvv, @function
_Z22__device_stub__Z4funcvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4funcv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z22__device_stub__Z4funcvv, .-_Z22__device_stub__Z4funcvv
.globl _Z4funcv
.type _Z4funcv, @function
_Z4funcv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4funcvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z4funcv, .-_Z4funcv
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movl $1000000, %ebx
jmp .L13
.L12:
call cudaDeviceSynchronize@PLT
subl $1, %ebx
je .L16
.L13:
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $8, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
call _Z22__device_stub__Z4funcvv
jmp .L12
.L16:
movl $0, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4funcv"
.LC1:
.string "memr"
.LC2:
.string "memg"
.LC3:
.string "memb"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4funcv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8192, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4memr(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8192, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4memg(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8192, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4memb(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL4memb
.comm _ZL4memb,8192,32
.local _ZL4memg
.comm _ZL4memg,8192,32
.local _ZL4memr
.comm _ZL4memr,8192,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
__device__ int memr[2048];
__device__ int memg[2048];
__device__ int memb[2048];
__shared__ int mem_out[2048];
__global__ void func() {
int i = blockIdx.x * 256 + threadIdx.x;
// This line is different from the line in our presentation,
// but it works similarly and yields similar results.
mem_out[i] = memr[(i*4 + 1) % 2048] * memr[i*4 % 2048]
+ memg[i*4 % 2048] + memb[i*4 % 2048];
}
int main() {
for (int i = 0; i < 1000000; i++) {
func<<<8, 256>>>();
cudaDeviceSynchronize();
}
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
__device__ int memr[2048];
__device__ int memg[2048];
__device__ int memb[2048];
__shared__ int mem_out[2048];
__global__ void func() {
int i = blockIdx.x * 256 + threadIdx.x;
// This line is different from the line in our presentation,
// but it works similarly and yields similar results.
mem_out[i] = memr[(i*4 + 1) % 2048] * memr[i*4 % 2048]
+ memg[i*4 % 2048] + memb[i*4 % 2048];
}
int main() {
for (int i = 0; i < 1000000; i++) {
func<<<8, 256>>>();
hipDeviceSynchronize();
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__device__ int memr[2048];
__device__ int memg[2048];
__device__ int memb[2048];
__shared__ int mem_out[2048];
__global__ void func() {
int i = blockIdx.x * 256 + threadIdx.x;
// This line is different from the line in our presentation,
// but it works similarly and yields similar results.
mem_out[i] = memr[(i*4 + 1) % 2048] * memr[i*4 % 2048]
+ memg[i*4 % 2048] + memb[i*4 % 2048];
}
int main() {
for (int i = 0; i < 1000000; i++) {
func<<<8, 256>>>();
hipDeviceSynchronize();
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4funcv
.globl _Z4funcv
.p2align 8
.type _Z4funcv,@function
_Z4funcv:
v_lshl_add_u32 v0, s15, 8, v0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, memr@rel32@lo+4
s_addc_u32 s1, s1, memr@rel32@hi+12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, memg@rel32@lo+4
s_addc_u32 s3, s3, memg@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, memb@rel32@lo+4
s_addc_u32 s5, s5, memb@rel32@hi+12
v_lshlrev_b32_e32 v8, 2, v0
v_bfe_i32 v0, v0, 29, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v1, 1, v8
v_lshrrev_b32_e32 v0, 21, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v1, v0
v_add_nc_u32_e32 v0, v8, v0
v_and_b32_e32 v2, 0xfffff800, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v3, 0xfffff800, v0
v_sub_nc_u32_e32 v0, v1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v8, v3
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, v0, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, v2, s0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, v2, s2
s_clause 0x1
global_load_b32 v9, v[0:1], off
global_load_b32 v4, v[4:5], off
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[6:7], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(2)
v_mul_lo_u32 v1, v4, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v1, v2, v0
ds_store_b32 v8, v0
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4funcv
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4funcv, .Lfunc_end0-_Z4funcv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected memr
.type memr,@object
.section .bss,"aw",@nobits
.globl memr
.p2align 4, 0x0
memr:
.zero 8192
.size memr, 8192
.protected memg
.type memg,@object
.globl memg
.p2align 4, 0x0
memg:
.zero 8192
.size memg, 8192
.protected memb
.type memb,@object
.globl memb
.p2align 4, 0x0
memb:
.zero 8192
.size memb, 8192
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym memr
.addrsig_sym memg
.addrsig_sym memb
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 8192
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4funcv
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4funcv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__device__ int memr[2048];
__device__ int memg[2048];
__device__ int memb[2048];
__shared__ int mem_out[2048];
__global__ void func() {
int i = blockIdx.x * 256 + threadIdx.x;
// This line is different from the line in our presentation,
// but it works similarly and yields similar results.
mem_out[i] = memr[(i*4 + 1) % 2048] * memr[i*4 % 2048]
+ memg[i*4 % 2048] + memb[i*4 % 2048];
}
int main() {
for (int i = 0; i < 1000000; i++) {
func<<<8, 256>>>();
hipDeviceSynchronize();
}
return 0;
} | .text
.file "memco.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__funcv # -- Begin function _Z19__device_stub__funcv
.p2align 4, 0x90
.type _Z19__device_stub__funcv,@function
_Z19__device_stub__funcv: # @_Z19__device_stub__funcv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4funcv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__funcv, .Lfunc_end0-_Z19__device_stub__funcv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967304, %rbx # imm = 0x100000008
movl $1000000, %r12d # imm = 0xF4240
leaq 248(%rbx), %r14
leaq 8(%rsp), %r13
movq %rsp, %rbp
leaq 48(%rsp), %r15
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
callq hipDeviceSynchronize
decl %r12d
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z4funcv, %edi
movq %r15, %r9
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_3
.LBB1_4:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4funcv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $memr, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8192, %r9d # imm = 0x2000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $memg, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $8192, %r9d # imm = 0x2000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $memb, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $8192, %r9d # imm = 0x2000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type memr,@object # @memr
.local memr
.comm memr,8192,16
.type memg,@object # @memg
.local memg
.comm memg,8192,16
.type memb,@object # @memb
.local memb
.comm memb,8192,16
.type _Z4funcv,@object # @_Z4funcv
.section .rodata,"a",@progbits
.globl _Z4funcv
.p2align 3, 0x0
_Z4funcv:
.quad _Z19__device_stub__funcv
.size _Z4funcv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4funcv"
.size .L__unnamed_1, 9
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "memr"
.size .L__unnamed_2, 5
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "memg"
.size .L__unnamed_3, 5
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "memb"
.size .L__unnamed_4, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__funcv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym memr
.addrsig_sym memg
.addrsig_sym memb
.addrsig_sym _Z4funcv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4funcv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4funcv
.globl _Z4funcv
.p2align 8
.type _Z4funcv,@function
_Z4funcv:
v_lshl_add_u32 v0, s15, 8, v0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, memr@rel32@lo+4
s_addc_u32 s1, s1, memr@rel32@hi+12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, memg@rel32@lo+4
s_addc_u32 s3, s3, memg@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, memb@rel32@lo+4
s_addc_u32 s5, s5, memb@rel32@hi+12
v_lshlrev_b32_e32 v8, 2, v0
v_bfe_i32 v0, v0, 29, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v1, 1, v8
v_lshrrev_b32_e32 v0, 21, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v1, v0
v_add_nc_u32_e32 v0, v8, v0
v_and_b32_e32 v2, 0xfffff800, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v3, 0xfffff800, v0
v_sub_nc_u32_e32 v0, v1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v8, v3
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, v0, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, v2, s0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, v2, s2
s_clause 0x1
global_load_b32 v9, v[0:1], off
global_load_b32 v4, v[4:5], off
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[6:7], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(2)
v_mul_lo_u32 v1, v4, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v1, v2, v0
ds_store_b32 v8, v0
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4funcv
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4funcv, .Lfunc_end0-_Z4funcv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected memr
.type memr,@object
.section .bss,"aw",@nobits
.globl memr
.p2align 4, 0x0
memr:
.zero 8192
.size memr, 8192
.protected memg
.type memg,@object
.globl memg
.p2align 4, 0x0
memg:
.zero 8192
.size memg, 8192
.protected memb
.type memb,@object
.globl memb
.p2align 4, 0x0
memb:
.zero 8192
.size memb, 8192
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym memr
.addrsig_sym memg
.addrsig_sym memb
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 8192
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4funcv
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4funcv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005b81b_00000000-6_memco.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4funcvv
.type _Z22__device_stub__Z4funcvv, @function
_Z22__device_stub__Z4funcvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4funcv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z22__device_stub__Z4funcvv, .-_Z22__device_stub__Z4funcvv
.globl _Z4funcv
.type _Z4funcv, @function
_Z4funcv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4funcvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z4funcv, .-_Z4funcv
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movl $1000000, %ebx
jmp .L13
.L12:
call cudaDeviceSynchronize@PLT
subl $1, %ebx
je .L16
.L13:
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $8, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
call _Z22__device_stub__Z4funcvv
jmp .L12
.L16:
movl $0, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4funcv"
.LC1:
.string "memr"
.LC2:
.string "memg"
.LC3:
.string "memb"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4funcv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8192, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4memr(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8192, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4memg(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8192, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4memb(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL4memb
.comm _ZL4memb,8192,32
.local _ZL4memg
.comm _ZL4memg,8192,32
.local _ZL4memr
.comm _ZL4memr,8192,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "memco.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__funcv # -- Begin function _Z19__device_stub__funcv
.p2align 4, 0x90
.type _Z19__device_stub__funcv,@function
_Z19__device_stub__funcv: # @_Z19__device_stub__funcv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4funcv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__funcv, .Lfunc_end0-_Z19__device_stub__funcv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967304, %rbx # imm = 0x100000008
movl $1000000, %r12d # imm = 0xF4240
leaq 248(%rbx), %r14
leaq 8(%rsp), %r13
movq %rsp, %rbp
leaq 48(%rsp), %r15
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
callq hipDeviceSynchronize
decl %r12d
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z4funcv, %edi
movq %r15, %r9
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_3
.LBB1_4:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4funcv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $memr, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8192, %r9d # imm = 0x2000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $memg, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $8192, %r9d # imm = 0x2000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $memb, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $8192, %r9d # imm = 0x2000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type memr,@object # @memr
.local memr
.comm memr,8192,16
.type memg,@object # @memg
.local memg
.comm memg,8192,16
.type memb,@object # @memb
.local memb
.comm memb,8192,16
.type _Z4funcv,@object # @_Z4funcv
.section .rodata,"a",@progbits
.globl _Z4funcv
.p2align 3, 0x0
_Z4funcv:
.quad _Z19__device_stub__funcv
.size _Z4funcv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4funcv"
.size .L__unnamed_1, 9
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "memr"
.size .L__unnamed_2, 5
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "memg"
.size .L__unnamed_3, 5
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "memb"
.size .L__unnamed_4, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__funcv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym memr
.addrsig_sym memg
.addrsig_sym memb
.addrsig_sym _Z4funcv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void magnitudeCopy(float *mag_vec, float *vec, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if (xIndex < n) { mag_vec[xIndex] = abs(vec[xIndex]); }
} | code for sm_80
Function : _Z13magnitudeCopyPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0005 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0005 */
/*00b0*/ FADD R7, |R2|, -RZ ; /* 0x800000ff02077221 */
/* 0x004fca0000000200 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void magnitudeCopy(float *mag_vec, float *vec, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if (xIndex < n) { mag_vec[xIndex] = abs(vec[xIndex]); }
} | .file "tmpxft_00126ca4_00000000-6_magnitudeCopy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13magnitudeCopyPfS_iPfS_i
.type _Z36__device_stub__Z13magnitudeCopyPfS_iPfS_i, @function
_Z36__device_stub__Z13magnitudeCopyPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13magnitudeCopyPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z13magnitudeCopyPfS_iPfS_i, .-_Z36__device_stub__Z13magnitudeCopyPfS_iPfS_i
.globl _Z13magnitudeCopyPfS_i
.type _Z13magnitudeCopyPfS_i, @function
_Z13magnitudeCopyPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13magnitudeCopyPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13magnitudeCopyPfS_i, .-_Z13magnitudeCopyPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13magnitudeCopyPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13magnitudeCopyPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void magnitudeCopy(float *mag_vec, float *vec, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if (xIndex < n) { mag_vec[xIndex] = abs(vec[xIndex]); }
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void magnitudeCopy(float *mag_vec, float *vec, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if (xIndex < n) { mag_vec[xIndex] = abs(vec[xIndex]); }
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void magnitudeCopy(float *mag_vec, float *vec, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if (xIndex < n) { mag_vec[xIndex] = abs(vec[xIndex]); }
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13magnitudeCopyPfS_i
.globl _Z13magnitudeCopyPfS_i
.p2align 8
.type _Z13magnitudeCopyPfS_i,@function
_Z13magnitudeCopyPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, 0x7fffffff, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13magnitudeCopyPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13magnitudeCopyPfS_i, .Lfunc_end0-_Z13magnitudeCopyPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13magnitudeCopyPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13magnitudeCopyPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void magnitudeCopy(float *mag_vec, float *vec, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if (xIndex < n) { mag_vec[xIndex] = abs(vec[xIndex]); }
} | .text
.file "magnitudeCopy.hip"
.globl _Z28__device_stub__magnitudeCopyPfS_i # -- Begin function _Z28__device_stub__magnitudeCopyPfS_i
.p2align 4, 0x90
.type _Z28__device_stub__magnitudeCopyPfS_i,@function
_Z28__device_stub__magnitudeCopyPfS_i: # @_Z28__device_stub__magnitudeCopyPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13magnitudeCopyPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__magnitudeCopyPfS_i, .Lfunc_end0-_Z28__device_stub__magnitudeCopyPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13magnitudeCopyPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13magnitudeCopyPfS_i,@object # @_Z13magnitudeCopyPfS_i
.section .rodata,"a",@progbits
.globl _Z13magnitudeCopyPfS_i
.p2align 3, 0x0
_Z13magnitudeCopyPfS_i:
.quad _Z28__device_stub__magnitudeCopyPfS_i
.size _Z13magnitudeCopyPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13magnitudeCopyPfS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__magnitudeCopyPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13magnitudeCopyPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13magnitudeCopyPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0005 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0005 */
/*00b0*/ FADD R7, |R2|, -RZ ; /* 0x800000ff02077221 */
/* 0x004fca0000000200 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13magnitudeCopyPfS_i
.globl _Z13magnitudeCopyPfS_i
.p2align 8
.type _Z13magnitudeCopyPfS_i,@function
_Z13magnitudeCopyPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, 0x7fffffff, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13magnitudeCopyPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13magnitudeCopyPfS_i, .Lfunc_end0-_Z13magnitudeCopyPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13magnitudeCopyPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13magnitudeCopyPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00126ca4_00000000-6_magnitudeCopy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13magnitudeCopyPfS_iPfS_i
.type _Z36__device_stub__Z13magnitudeCopyPfS_iPfS_i, @function
_Z36__device_stub__Z13magnitudeCopyPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13magnitudeCopyPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z13magnitudeCopyPfS_iPfS_i, .-_Z36__device_stub__Z13magnitudeCopyPfS_iPfS_i
.globl _Z13magnitudeCopyPfS_i
.type _Z13magnitudeCopyPfS_i, @function
_Z13magnitudeCopyPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13magnitudeCopyPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13magnitudeCopyPfS_i, .-_Z13magnitudeCopyPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13magnitudeCopyPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13magnitudeCopyPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "magnitudeCopy.hip"
.globl _Z28__device_stub__magnitudeCopyPfS_i # -- Begin function _Z28__device_stub__magnitudeCopyPfS_i
.p2align 4, 0x90
.type _Z28__device_stub__magnitudeCopyPfS_i,@function
_Z28__device_stub__magnitudeCopyPfS_i: # @_Z28__device_stub__magnitudeCopyPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13magnitudeCopyPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__magnitudeCopyPfS_i, .Lfunc_end0-_Z28__device_stub__magnitudeCopyPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13magnitudeCopyPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13magnitudeCopyPfS_i,@object # @_Z13magnitudeCopyPfS_i
.section .rodata,"a",@progbits
.globl _Z13magnitudeCopyPfS_i
.p2align 3, 0x0
_Z13magnitudeCopyPfS_i:
.quad _Z28__device_stub__magnitudeCopyPfS_i
.size _Z13magnitudeCopyPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13magnitudeCopyPfS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__magnitudeCopyPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13magnitudeCopyPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define THREADS 16384
#define BLOCKS 65536
#define NUM_VALS THREADS*BLOCKS
void rand_nums(int *values, unsigned long length) {
int i;
for (i = 0; i < length; ++i) {
values[i] = rand() % INT_MAX + 1;;
}
}
__global__ void bitonicMinorSort(int *innerValues, int j, int k) {
unsigned int i, ixj;
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i ^ j;
if ((ixj) > i) {
if ((i & k) == 0) {
if (innerValues[i] > innerValues[ixj]) {
int temp = innerValues[i];
innerValues[i] = innerValues[ixj];
innerValues[ixj] = temp;
}
}
if ((i & k) != 0) {
if (innerValues[i] < innerValues[ixj]) {
int temp = innerValues[i];
innerValues[i] = innerValues[ixj];
innerValues[ixj] = temp;
}
}
}
}
void bitonicSort(int *values, unsigned long n) {
int *innerValues;
size_t size = n * sizeof(int);
cudaMalloc((void **) &innerValues, size);
cudaMemcpy(innerValues, values, size, cudaMemcpyHostToDevice);
int blockSize;
if(n < THREADS) {
blockSize = 1;
} else {
blockSize = ceil(n/THREADS);
}
dim3 blocks(blockSize, 1);
dim3 threads(THREADS, 1);
int j, k;
for (k = 2; k <= n; k <<= 1) {
for (j = k >> 1; j > 0; j = j >> 1) {
bitonicMinorSort<<<blocks, threads>>> (innerValues, j, k);
}
}
cudaMemcpy(values, innerValues, size, cudaMemcpyDeviceToHost);
cudaFree(innerValues);
}
int main(int argc, char *argv[]) {
int k = 10;
if(argc==2)
k = atoi(argv[1]);
int *values = (int *) malloc(NUM_VALS * sizeof(int));
int *origValues = (int *) malloc(NUM_VALS * sizeof(int));
unsigned long n;
double time_spent;
clock_t begin, end;
n = pow(2,k);
printf("\nk = %d, n = %ld\n", k, n);
rand_nums(values, n);
for (unsigned long i = 0; i < n; i++)
origValues[i] = values[i];
time_spent = 0.0;
begin = clock();
bitonicSort(values, n);
end = clock();
time_spent += (double)(end-begin) / CLOCKS_PER_SEC;
printf("\tElapsed time: %f seconds\n", time_spent);
free(values);
free(origValues);
} | code for sm_80
Function : _Z16bitonicMinorSortPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ LOP3.LUT R5, R0, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0000057a12 */
/* 0x000fc800078e3cff */
/*0050*/ ISETP.GT.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f04070 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R0, R4, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0004 */
/*00a0*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0004 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000168000c1e1900 */
/*00c0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000162000c1e1900 */
/*00d0*/ LOP3.LUT P0, RZ, R0, c[0x0][0x16c], RZ, 0xc0, !PT ; /* 0x00005b0000ff7a12 */
/* 0x000fda000780c0ff */
/*00e0*/ @!P0 BRA 0x140 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*00f0*/ ISETP.GE.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f06270 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101904 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f04270 */
/*0150*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0160*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101904 */
/*0170*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define THREADS 16384
#define BLOCKS 65536
#define NUM_VALS THREADS*BLOCKS
void rand_nums(int *values, unsigned long length) {
int i;
for (i = 0; i < length; ++i) {
values[i] = rand() % INT_MAX + 1;;
}
}
__global__ void bitonicMinorSort(int *innerValues, int j, int k) {
unsigned int i, ixj;
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i ^ j;
if ((ixj) > i) {
if ((i & k) == 0) {
if (innerValues[i] > innerValues[ixj]) {
int temp = innerValues[i];
innerValues[i] = innerValues[ixj];
innerValues[ixj] = temp;
}
}
if ((i & k) != 0) {
if (innerValues[i] < innerValues[ixj]) {
int temp = innerValues[i];
innerValues[i] = innerValues[ixj];
innerValues[ixj] = temp;
}
}
}
}
void bitonicSort(int *values, unsigned long n) {
int *innerValues;
size_t size = n * sizeof(int);
cudaMalloc((void **) &innerValues, size);
cudaMemcpy(innerValues, values, size, cudaMemcpyHostToDevice);
int blockSize;
if(n < THREADS) {
blockSize = 1;
} else {
blockSize = ceil(n/THREADS);
}
dim3 blocks(blockSize, 1);
dim3 threads(THREADS, 1);
int j, k;
for (k = 2; k <= n; k <<= 1) {
for (j = k >> 1; j > 0; j = j >> 1) {
bitonicMinorSort<<<blocks, threads>>> (innerValues, j, k);
}
}
cudaMemcpy(values, innerValues, size, cudaMemcpyDeviceToHost);
cudaFree(innerValues);
}
int main(int argc, char *argv[]) {
int k = 10;
if(argc==2)
k = atoi(argv[1]);
int *values = (int *) malloc(NUM_VALS * sizeof(int));
int *origValues = (int *) malloc(NUM_VALS * sizeof(int));
unsigned long n;
double time_spent;
clock_t begin, end;
n = pow(2,k);
printf("\nk = %d, n = %ld\n", k, n);
rand_nums(values, n);
for (unsigned long i = 0; i < n; i++)
origValues[i] = values[i];
time_spent = 0.0;
begin = clock();
bitonicSort(values, n);
end = clock();
time_spent += (double)(end-begin) / CLOCKS_PER_SEC;
printf("\tElapsed time: %f seconds\n", time_spent);
free(values);
free(origValues);
} | .file "tmpxft_0001c3f7_00000000-6_bitonicCudaSorting.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9rand_numsPim
.type _Z9rand_numsPim, @function
_Z9rand_numsPim:
.LFB2057:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L8
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq %rsi, %rbp
movl $0, %ebx
.L5:
call rand@PLT
movslq %eax, %rcx
movq %rcx, %rdx
salq $30, %rdx
addq %rcx, %rdx
sarq $61, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
movl %edx, %ecx
sall $31, %ecx
subl %edx, %ecx
subl %ecx, %eax
addl $1, %eax
movl %eax, (%r12,%rbx,4)
addq $1, %rbx
cmpq %rbx, %rbp
jne .L5
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2057:
.size _Z9rand_numsPim, .-_Z9rand_numsPim
.globl _Z38__device_stub__Z16bitonicMinorSortPiiiPiii
.type _Z38__device_stub__Z16bitonicMinorSortPiiiPiii, @function
_Z38__device_stub__Z16bitonicMinorSortPiiiPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16bitonicMinorSortPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z16bitonicMinorSortPiiiPiii, .-_Z38__device_stub__Z16bitonicMinorSortPiiiPiii
.globl _Z16bitonicMinorSortPiii
.type _Z16bitonicMinorSortPiii, @function
_Z16bitonicMinorSortPiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16bitonicMinorSortPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16bitonicMinorSortPiii, .-_Z16bitonicMinorSortPiii
.globl _Z11bitonicSortPim
.type _Z11bitonicSortPim, @function
_Z11bitonicSortPim:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 0(,%rsi,4), %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
cmpq $16383, %r12
jbe .L20
movq %r12, %rax
shrq $14, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
cvttsd2sil %xmm0, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $16384, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
.L23:
movl $2, %ebp
jmp .L28
.L20:
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $16384, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
cmpq $1, %r12
ja .L23
.L24:
movl $2, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
sarl %ebx
testl %ebx, %ebx
jle .L25
.L27:
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L26
movl %ebp, %edx
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z16bitonicMinorSortPiiiPiii
jmp .L26
.L25:
addl %ebp, %ebp
movslq %ebp, %rax
cmpq %rax, %r12
jb .L24
.L28:
movl %ebp, %ebx
sarl %ebx
testl %ebx, %ebx
jg .L27
jmp .L25
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z11bitonicSortPim, .-_Z11bitonicSortPim
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\nk = %d, n = %ld\n"
.LC5:
.string "\tElapsed time: %f seconds\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
cmpl $2, %edi
je .L44
movabsq $4294967296, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbp
movl $1024, %ecx
movl $10, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, %esi
movq %rbx, %rdi
call _Z9rand_numsPim
movl $1024, %r12d
.L40:
movl $0, %eax
.L39:
movl (%rbx,%rax,4), %edx
movl %edx, 0(%rbp,%rax,4)
addq $1, %rax
cmpq %r12, %rax
jne .L39
.L38:
call clock@PLT
movq %rax, %r13
movq %r12, %rsi
movq %rbx, %rdi
call _Z11bitonicSortPim
call clock@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC3(%rip), %xmm0
pxor %xmm1, %xmm1
addsd %xmm1, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %r13d
movabsq $4294967296, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbp
pxor %xmm1, %xmm1
cvtsi2sdl %r12d, %xmm1
movsd .LC0(%rip), %xmm0
call pow@PLT
comisd .LC1(%rip), %xmm0
jnb .L36
cvttsd2siq %xmm0, %r12
.L37:
movq %r12, %rcx
movl %r13d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movq %rbx, %rdi
call _Z9rand_numsPim
testq %r12, %r12
je .L38
jmp .L40
.L36:
subsd .LC1(%rip), %xmm0
cvttsd2siq %xmm0, %r12
btcq $63, %r12
jmp .L37
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z16bitonicMinorSortPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z16bitonicMinorSortPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1073741824
.align 8
.LC1:
.long 0
.long 1138753536
.align 8
.LC3:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define THREADS 16384
#define BLOCKS 65536
#define NUM_VALS THREADS*BLOCKS
void rand_nums(int *values, unsigned long length) {
int i;
for (i = 0; i < length; ++i) {
values[i] = rand() % INT_MAX + 1;;
}
}
__global__ void bitonicMinorSort(int *innerValues, int j, int k) {
unsigned int i, ixj;
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i ^ j;
if ((ixj) > i) {
if ((i & k) == 0) {
if (innerValues[i] > innerValues[ixj]) {
int temp = innerValues[i];
innerValues[i] = innerValues[ixj];
innerValues[ixj] = temp;
}
}
if ((i & k) != 0) {
if (innerValues[i] < innerValues[ixj]) {
int temp = innerValues[i];
innerValues[i] = innerValues[ixj];
innerValues[ixj] = temp;
}
}
}
}
void bitonicSort(int *values, unsigned long n) {
int *innerValues;
size_t size = n * sizeof(int);
cudaMalloc((void **) &innerValues, size);
cudaMemcpy(innerValues, values, size, cudaMemcpyHostToDevice);
int blockSize;
if(n < THREADS) {
blockSize = 1;
} else {
blockSize = ceil(n/THREADS);
}
dim3 blocks(blockSize, 1);
dim3 threads(THREADS, 1);
int j, k;
for (k = 2; k <= n; k <<= 1) {
for (j = k >> 1; j > 0; j = j >> 1) {
bitonicMinorSort<<<blocks, threads>>> (innerValues, j, k);
}
}
cudaMemcpy(values, innerValues, size, cudaMemcpyDeviceToHost);
cudaFree(innerValues);
}
int main(int argc, char *argv[]) {
int k = 10;
if(argc==2)
k = atoi(argv[1]);
int *values = (int *) malloc(NUM_VALS * sizeof(int));
int *origValues = (int *) malloc(NUM_VALS * sizeof(int));
unsigned long n;
double time_spent;
clock_t begin, end;
n = pow(2,k);
printf("\nk = %d, n = %ld\n", k, n);
rand_nums(values, n);
for (unsigned long i = 0; i < n; i++)
origValues[i] = values[i];
time_spent = 0.0;
begin = clock();
bitonicSort(values, n);
end = clock();
time_spent += (double)(end-begin) / CLOCKS_PER_SEC;
printf("\tElapsed time: %f seconds\n", time_spent);
free(values);
free(origValues);
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define THREADS 16384
#define BLOCKS 65536
#define NUM_VALS THREADS*BLOCKS
void rand_nums(int *values, unsigned long length) {
int i;
for (i = 0; i < length; ++i) {
values[i] = rand() % INT_MAX + 1;;
}
}
__global__ void bitonicMinorSort(int *innerValues, int j, int k) {
unsigned int i, ixj;
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i ^ j;
if ((ixj) > i) {
if ((i & k) == 0) {
if (innerValues[i] > innerValues[ixj]) {
int temp = innerValues[i];
innerValues[i] = innerValues[ixj];
innerValues[ixj] = temp;
}
}
if ((i & k) != 0) {
if (innerValues[i] < innerValues[ixj]) {
int temp = innerValues[i];
innerValues[i] = innerValues[ixj];
innerValues[ixj] = temp;
}
}
}
}
void bitonicSort(int *values, unsigned long n) {
int *innerValues;
size_t size = n * sizeof(int);
hipMalloc((void **) &innerValues, size);
hipMemcpy(innerValues, values, size, hipMemcpyHostToDevice);
int blockSize;
if(n < THREADS) {
blockSize = 1;
} else {
blockSize = ceil(n/THREADS);
}
dim3 blocks(blockSize, 1);
dim3 threads(THREADS, 1);
int j, k;
for (k = 2; k <= n; k <<= 1) {
for (j = k >> 1; j > 0; j = j >> 1) {
bitonicMinorSort<<<blocks, threads>>> (innerValues, j, k);
}
}
hipMemcpy(values, innerValues, size, hipMemcpyDeviceToHost);
hipFree(innerValues);
}
int main(int argc, char *argv[]) {
int k = 10;
if(argc==2)
k = atoi(argv[1]);
int *values = (int *) malloc(NUM_VALS * sizeof(int));
int *origValues = (int *) malloc(NUM_VALS * sizeof(int));
unsigned long n;
double time_spent;
clock_t begin, end;
n = pow(2,k);
printf("\nk = %d, n = %ld\n", k, n);
rand_nums(values, n);
for (unsigned long i = 0; i < n; i++)
origValues[i] = values[i];
time_spent = 0.0;
begin = clock();
bitonicSort(values, n);
end = clock();
time_spent += (double)(end-begin) / CLOCKS_PER_SEC;
printf("\tElapsed time: %f seconds\n", time_spent);
free(values);
free(origValues);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define THREADS 16384
#define BLOCKS 65536
#define NUM_VALS THREADS*BLOCKS
void rand_nums(int *values, unsigned long length) {
int i;
for (i = 0; i < length; ++i) {
values[i] = rand() % INT_MAX + 1;;
}
}
__global__ void bitonicMinorSort(int *innerValues, int j, int k) {
unsigned int i, ixj;
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i ^ j;
if ((ixj) > i) {
if ((i & k) == 0) {
if (innerValues[i] > innerValues[ixj]) {
int temp = innerValues[i];
innerValues[i] = innerValues[ixj];
innerValues[ixj] = temp;
}
}
if ((i & k) != 0) {
if (innerValues[i] < innerValues[ixj]) {
int temp = innerValues[i];
innerValues[i] = innerValues[ixj];
innerValues[ixj] = temp;
}
}
}
}
void bitonicSort(int *values, unsigned long n) {
int *innerValues;
size_t size = n * sizeof(int);
hipMalloc((void **) &innerValues, size);
hipMemcpy(innerValues, values, size, hipMemcpyHostToDevice);
int blockSize;
if(n < THREADS) {
blockSize = 1;
} else {
blockSize = ceil(n/THREADS);
}
dim3 blocks(blockSize, 1);
dim3 threads(THREADS, 1);
int j, k;
for (k = 2; k <= n; k <<= 1) {
for (j = k >> 1; j > 0; j = j >> 1) {
bitonicMinorSort<<<blocks, threads>>> (innerValues, j, k);
}
}
hipMemcpy(values, innerValues, size, hipMemcpyDeviceToHost);
hipFree(innerValues);
}
int main(int argc, char *argv[]) {
int k = 10;
if(argc==2)
k = atoi(argv[1]);
int *values = (int *) malloc(NUM_VALS * sizeof(int));
int *origValues = (int *) malloc(NUM_VALS * sizeof(int));
unsigned long n;
double time_spent;
clock_t begin, end;
n = pow(2,k);
printf("\nk = %d, n = %ld\n", k, n);
rand_nums(values, n);
for (unsigned long i = 0; i < n; i++)
origValues[i] = values[i];
time_spent = 0.0;
begin = clock();
bitonicSort(values, n);
end = clock();
time_spent += (double)(end-begin) / CLOCKS_PER_SEC;
printf("\tElapsed time: %f seconds\n", time_spent);
free(values);
free(origValues);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16bitonicMinorSortPiii
.globl _Z16bitonicMinorSortPiii
.p2align 8
.type _Z16bitonicMinorSortPiii,@function
_Z16bitonicMinorSortPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_xor_b32_e32 v0, s3, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 v0, v4
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0xc
v_mov_b32_e32 v5, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, v5 :: v_dual_and_b32 v4, s0, v4
s_mov_b32 s0, 0
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v5, v[0:1], off
global_load_b32 v6, v[2:3], off
v_cmpx_ne_u32_e32 0, v4
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_3
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v5, v6
s_and_b32 s0, vcc_lo, exec_lo
.LBB0_3:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB0_5
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v5, v6
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s2, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, s2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v5, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16bitonicMinorSortPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16bitonicMinorSortPiii, .Lfunc_end0-_Z16bitonicMinorSortPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16bitonicMinorSortPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16bitonicMinorSortPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define THREADS 16384
#define BLOCKS 65536
#define NUM_VALS THREADS*BLOCKS
void rand_nums(int *values, unsigned long length) {
int i;
for (i = 0; i < length; ++i) {
values[i] = rand() % INT_MAX + 1;;
}
}
__global__ void bitonicMinorSort(int *innerValues, int j, int k) {
unsigned int i, ixj;
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i ^ j;
if ((ixj) > i) {
if ((i & k) == 0) {
if (innerValues[i] > innerValues[ixj]) {
int temp = innerValues[i];
innerValues[i] = innerValues[ixj];
innerValues[ixj] = temp;
}
}
if ((i & k) != 0) {
if (innerValues[i] < innerValues[ixj]) {
int temp = innerValues[i];
innerValues[i] = innerValues[ixj];
innerValues[ixj] = temp;
}
}
}
}
void bitonicSort(int *values, unsigned long n) {
int *innerValues;
size_t size = n * sizeof(int);
hipMalloc((void **) &innerValues, size);
hipMemcpy(innerValues, values, size, hipMemcpyHostToDevice);
int blockSize;
if(n < THREADS) {
blockSize = 1;
} else {
blockSize = ceil(n/THREADS);
}
dim3 blocks(blockSize, 1);
dim3 threads(THREADS, 1);
int j, k;
for (k = 2; k <= n; k <<= 1) {
for (j = k >> 1; j > 0; j = j >> 1) {
bitonicMinorSort<<<blocks, threads>>> (innerValues, j, k);
}
}
hipMemcpy(values, innerValues, size, hipMemcpyDeviceToHost);
hipFree(innerValues);
}
int main(int argc, char *argv[]) {
int k = 10;
if(argc==2)
k = atoi(argv[1]);
int *values = (int *) malloc(NUM_VALS * sizeof(int));
int *origValues = (int *) malloc(NUM_VALS * sizeof(int));
unsigned long n;
double time_spent;
clock_t begin, end;
n = pow(2,k);
printf("\nk = %d, n = %ld\n", k, n);
rand_nums(values, n);
for (unsigned long i = 0; i < n; i++)
origValues[i] = values[i];
time_spent = 0.0;
begin = clock();
bitonicSort(values, n);
end = clock();
time_spent += (double)(end-begin) / CLOCKS_PER_SEC;
printf("\tElapsed time: %f seconds\n", time_spent);
free(values);
free(origValues);
} | .text
.file "bitonicCudaSorting.hip"
.globl _Z9rand_numsPim # -- Begin function _Z9rand_numsPim
.p2align 4, 0x90
.type _Z9rand_numsPim,@function
_Z9rand_numsPim: # @_Z9rand_numsPim
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
movq %rax, %rcx
shlq $30, %rcx
addq %rax, %rcx
movq %rcx, %rdx
shrq $63, %rdx
sarq $61, %rcx
addl %edx, %ecx
movl %ecx, %edx
shll $31, %edx
addl %ecx, %edx
addl %edx, %eax
incl %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq %r15, %rbx
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z9rand_numsPim, .Lfunc_end0-_Z9rand_numsPim
.cfi_endproc
# -- End function
.globl _Z31__device_stub__bitonicMinorSortPiii # -- Begin function _Z31__device_stub__bitonicMinorSortPiii
.p2align 4, 0x90
.type _Z31__device_stub__bitonicMinorSortPiii,@function
_Z31__device_stub__bitonicMinorSortPiii: # @_Z31__device_stub__bitonicMinorSortPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16bitonicMinorSortPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z31__device_stub__bitonicMinorSortPiii, .Lfunc_end1-_Z31__device_stub__bitonicMinorSortPiii
.cfi_endproc
# -- End function
.globl _Z11bitonicSortPim # -- Begin function _Z11bitonicSortPim
.p2align 4, 0x90
.type _Z11bitonicSortPim,@function
_Z11bitonicSortPim: # @_Z11bitonicSortPim
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq %rdi, %r14
movabsq $4294967296, %r12 # imm = 0x100000000
leaq (,%rsi,4), %rbx
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
movq (%rsp), %rdi
movq %r14, 16(%rsp) # 8-byte Spill
movq %r14, %rsi
movq %rbx, 24(%rsp) # 8-byte Spill
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, %rax
shrq $14, %rax
movl %eax, %eax
orq %r12, %rax
leaq 1(%r12), %r13
cmpq $16384, %r15 # imm = 0x4000
cmovaeq %rax, %r13
movq %r15, 32(%rsp) # 8-byte Spill
cmpq $2, %r15
jae .LBB2_1
.LBB2_7: # %._crit_edge33
movq (%rsp), %rsi
movq 16(%rsp), %rdi # 8-byte Reload
movq 24(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1: # %.lr.ph32
.cfi_def_cfa_offset 176
movl $2, %ebx
addq $16384, %r12 # imm = 0x4000
leaq 40(%rsp), %r15
leaq 96(%rsp), %rbp
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_6: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
addl %ebx, %ebx
movslq %ebx, %rax
cmpq 32(%rsp), %rax # 8-byte Folded Reload
ja .LBB2_7
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %ebx, %r14d
sarl %r14d
testl %r14d, %r14d
jg .LBB2_3
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=2
movl %r14d, %eax
shrl %eax
cmpl $1, %r14d
movl %eax, %r14d
jbe .LBB2_6
.LBB2_3: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=2
movq (%rsp), %rax
movq %rax, 88(%rsp)
movl %r14d, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
movq %r15, %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z16bitonicMinorSortPiii, %edi
movq %rbp, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_5
.Lfunc_end2:
.size _Z11bitonicSortPim, .Lfunc_end2-_Z11bitonicSortPim
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3ff0000000000000 # double 1
.LCPI3_1:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.LCPI3_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $10, %r15d
cmpl $2, %edi
jne .LBB3_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
.LBB3_2:
movabsq $4294967296, %rdi # imm = 0x100000000
callq malloc
movq %rax, %rbx
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %r15d, %edi
callq ldexp@PLT
cvttsd2si %xmm0, %rax
movq %rax, %rcx
sarq $63, %rcx
subsd .LCPI3_1(%rip), %xmm0
cvttsd2si %xmm0, %r14
andq %rcx, %r14
orq %rax, %r14
movl $.L.str, %edi
movl %r15d, %esi
movq %r14, %rdx
xorl %eax, %eax
callq printf
testq %r14, %r14
je .LBB3_5
# %bb.3: # %.lr.ph.i.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
movq %rax, %rcx
shlq $30, %rcx
addq %rax, %rcx
movq %rcx, %rdx
shrq $63, %rdx
sarq $61, %rcx
addl %edx, %ecx
movl %ecx, %edx
shll $31, %edx
addl %ecx, %edx
addl %edx, %eax
incl %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB3_4
.LBB3_5: # %_Z9rand_numsPim.exit
callq clock
movq %rax, %r15
movq %rbx, %rdi
movq %r14, %rsi
callq _Z11bitonicSortPim
callq clock
subq %r15, %rax
cvtsi2sd %rax, %xmm1
divsd .LCPI3_2(%rip), %xmm1
xorpd %xmm0, %xmm0
addsd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16bitonicMinorSortPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16bitonicMinorSortPiii,@object # @_Z16bitonicMinorSortPiii
.section .rodata,"a",@progbits
.globl _Z16bitonicMinorSortPiii
.p2align 3, 0x0
_Z16bitonicMinorSortPiii:
.quad _Z31__device_stub__bitonicMinorSortPiii
.size _Z16bitonicMinorSortPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nk = %d, n = %ld\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\tElapsed time: %f seconds\n"
.size .L.str.1, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16bitonicMinorSortPiii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__bitonicMinorSortPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16bitonicMinorSortPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16bitonicMinorSortPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ LOP3.LUT R5, R0, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0000057a12 */
/* 0x000fc800078e3cff */
/*0050*/ ISETP.GT.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f04070 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R0, R4, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0004 */
/*00a0*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0004 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000168000c1e1900 */
/*00c0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000162000c1e1900 */
/*00d0*/ LOP3.LUT P0, RZ, R0, c[0x0][0x16c], RZ, 0xc0, !PT ; /* 0x00005b0000ff7a12 */
/* 0x000fda000780c0ff */
/*00e0*/ @!P0 BRA 0x140 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*00f0*/ ISETP.GE.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f06270 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101904 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f04270 */
/*0150*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0160*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101904 */
/*0170*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16bitonicMinorSortPiii
.globl _Z16bitonicMinorSortPiii
.p2align 8
.type _Z16bitonicMinorSortPiii,@function
_Z16bitonicMinorSortPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_xor_b32_e32 v0, s3, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 v0, v4
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0xc
v_mov_b32_e32 v5, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, v5 :: v_dual_and_b32 v4, s0, v4
s_mov_b32 s0, 0
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v5, v[0:1], off
global_load_b32 v6, v[2:3], off
v_cmpx_ne_u32_e32 0, v4
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_3
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v5, v6
s_and_b32 s0, vcc_lo, exec_lo
.LBB0_3:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB0_5
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v5, v6
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s2, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, s2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v5, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16bitonicMinorSortPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16bitonicMinorSortPiii, .Lfunc_end0-_Z16bitonicMinorSortPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16bitonicMinorSortPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16bitonicMinorSortPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001c3f7_00000000-6_bitonicCudaSorting.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9rand_numsPim
.type _Z9rand_numsPim, @function
_Z9rand_numsPim:
.LFB2057:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L8
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq %rsi, %rbp
movl $0, %ebx
.L5:
call rand@PLT
movslq %eax, %rcx
movq %rcx, %rdx
salq $30, %rdx
addq %rcx, %rdx
sarq $61, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
movl %edx, %ecx
sall $31, %ecx
subl %edx, %ecx
subl %ecx, %eax
addl $1, %eax
movl %eax, (%r12,%rbx,4)
addq $1, %rbx
cmpq %rbx, %rbp
jne .L5
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2057:
.size _Z9rand_numsPim, .-_Z9rand_numsPim
.globl _Z38__device_stub__Z16bitonicMinorSortPiiiPiii
.type _Z38__device_stub__Z16bitonicMinorSortPiiiPiii, @function
_Z38__device_stub__Z16bitonicMinorSortPiiiPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16bitonicMinorSortPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z16bitonicMinorSortPiiiPiii, .-_Z38__device_stub__Z16bitonicMinorSortPiiiPiii
.globl _Z16bitonicMinorSortPiii
.type _Z16bitonicMinorSortPiii, @function
_Z16bitonicMinorSortPiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16bitonicMinorSortPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16bitonicMinorSortPiii, .-_Z16bitonicMinorSortPiii
.globl _Z11bitonicSortPim
.type _Z11bitonicSortPim, @function
_Z11bitonicSortPim:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 0(,%rsi,4), %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
cmpq $16383, %r12
jbe .L20
movq %r12, %rax
shrq $14, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
cvttsd2sil %xmm0, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $16384, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
.L23:
movl $2, %ebp
jmp .L28
.L20:
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $16384, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
cmpq $1, %r12
ja .L23
.L24:
movl $2, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
sarl %ebx
testl %ebx, %ebx
jle .L25
.L27:
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L26
movl %ebp, %edx
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z16bitonicMinorSortPiiiPiii
jmp .L26
.L25:
addl %ebp, %ebp
movslq %ebp, %rax
cmpq %rax, %r12
jb .L24
.L28:
movl %ebp, %ebx
sarl %ebx
testl %ebx, %ebx
jg .L27
jmp .L25
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z11bitonicSortPim, .-_Z11bitonicSortPim
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\nk = %d, n = %ld\n"
.LC5:
.string "\tElapsed time: %f seconds\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
cmpl $2, %edi
je .L44
movabsq $4294967296, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbp
movl $1024, %ecx
movl $10, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, %esi
movq %rbx, %rdi
call _Z9rand_numsPim
movl $1024, %r12d
.L40:
movl $0, %eax
.L39:
movl (%rbx,%rax,4), %edx
movl %edx, 0(%rbp,%rax,4)
addq $1, %rax
cmpq %r12, %rax
jne .L39
.L38:
call clock@PLT
movq %rax, %r13
movq %r12, %rsi
movq %rbx, %rdi
call _Z11bitonicSortPim
call clock@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC3(%rip), %xmm0
pxor %xmm1, %xmm1
addsd %xmm1, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %r13d
movabsq $4294967296, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbp
pxor %xmm1, %xmm1
cvtsi2sdl %r12d, %xmm1
movsd .LC0(%rip), %xmm0
call pow@PLT
comisd .LC1(%rip), %xmm0
jnb .L36
cvttsd2siq %xmm0, %r12
.L37:
movq %r12, %rcx
movl %r13d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movq %rbx, %rdi
call _Z9rand_numsPim
testq %r12, %r12
je .L38
jmp .L40
.L36:
subsd .LC1(%rip), %xmm0
cvttsd2siq %xmm0, %r12
btcq $63, %r12
jmp .L37
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z16bitonicMinorSortPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z16bitonicMinorSortPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1073741824
.align 8
.LC1:
.long 0
.long 1138753536
.align 8
.LC3:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bitonicCudaSorting.hip"
.globl _Z9rand_numsPim # -- Begin function _Z9rand_numsPim
.p2align 4, 0x90
.type _Z9rand_numsPim,@function
_Z9rand_numsPim: # @_Z9rand_numsPim
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
movq %rax, %rcx
shlq $30, %rcx
addq %rax, %rcx
movq %rcx, %rdx
shrq $63, %rdx
sarq $61, %rcx
addl %edx, %ecx
movl %ecx, %edx
shll $31, %edx
addl %ecx, %edx
addl %edx, %eax
incl %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq %r15, %rbx
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z9rand_numsPim, .Lfunc_end0-_Z9rand_numsPim
.cfi_endproc
# -- End function
.globl _Z31__device_stub__bitonicMinorSortPiii # -- Begin function _Z31__device_stub__bitonicMinorSortPiii
.p2align 4, 0x90
.type _Z31__device_stub__bitonicMinorSortPiii,@function
_Z31__device_stub__bitonicMinorSortPiii: # @_Z31__device_stub__bitonicMinorSortPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16bitonicMinorSortPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z31__device_stub__bitonicMinorSortPiii, .Lfunc_end1-_Z31__device_stub__bitonicMinorSortPiii
.cfi_endproc
# -- End function
.globl _Z11bitonicSortPim # -- Begin function _Z11bitonicSortPim
.p2align 4, 0x90
.type _Z11bitonicSortPim,@function
_Z11bitonicSortPim: # @_Z11bitonicSortPim
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq %rdi, %r14
movabsq $4294967296, %r12 # imm = 0x100000000
leaq (,%rsi,4), %rbx
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
movq (%rsp), %rdi
movq %r14, 16(%rsp) # 8-byte Spill
movq %r14, %rsi
movq %rbx, 24(%rsp) # 8-byte Spill
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, %rax
shrq $14, %rax
movl %eax, %eax
orq %r12, %rax
leaq 1(%r12), %r13
cmpq $16384, %r15 # imm = 0x4000
cmovaeq %rax, %r13
movq %r15, 32(%rsp) # 8-byte Spill
cmpq $2, %r15
jae .LBB2_1
.LBB2_7: # %._crit_edge33
movq (%rsp), %rsi
movq 16(%rsp), %rdi # 8-byte Reload
movq 24(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1: # %.lr.ph32
.cfi_def_cfa_offset 176
movl $2, %ebx
addq $16384, %r12 # imm = 0x4000
leaq 40(%rsp), %r15
leaq 96(%rsp), %rbp
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_6: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
addl %ebx, %ebx
movslq %ebx, %rax
cmpq 32(%rsp), %rax # 8-byte Folded Reload
ja .LBB2_7
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %ebx, %r14d
sarl %r14d
testl %r14d, %r14d
jg .LBB2_3
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=2
movl %r14d, %eax
shrl %eax
cmpl $1, %r14d
movl %eax, %r14d
jbe .LBB2_6
.LBB2_3: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=2
movq (%rsp), %rax
movq %rax, 88(%rsp)
movl %r14d, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
movq %r15, %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z16bitonicMinorSortPiii, %edi
movq %rbp, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_5
.Lfunc_end2:
.size _Z11bitonicSortPim, .Lfunc_end2-_Z11bitonicSortPim
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3ff0000000000000 # double 1
.LCPI3_1:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.LCPI3_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $10, %r15d
cmpl $2, %edi
jne .LBB3_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
.LBB3_2:
movabsq $4294967296, %rdi # imm = 0x100000000
callq malloc
movq %rax, %rbx
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %r15d, %edi
callq ldexp@PLT
cvttsd2si %xmm0, %rax
movq %rax, %rcx
sarq $63, %rcx
subsd .LCPI3_1(%rip), %xmm0
cvttsd2si %xmm0, %r14
andq %rcx, %r14
orq %rax, %r14
movl $.L.str, %edi
movl %r15d, %esi
movq %r14, %rdx
xorl %eax, %eax
callq printf
testq %r14, %r14
je .LBB3_5
# %bb.3: # %.lr.ph.i.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
movq %rax, %rcx
shlq $30, %rcx
addq %rax, %rcx
movq %rcx, %rdx
shrq $63, %rdx
sarq $61, %rcx
addl %edx, %ecx
movl %ecx, %edx
shll $31, %edx
addl %ecx, %edx
addl %edx, %eax
incl %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB3_4
.LBB3_5: # %_Z9rand_numsPim.exit
callq clock
movq %rax, %r15
movq %rbx, %rdi
movq %r14, %rsi
callq _Z11bitonicSortPim
callq clock
subq %r15, %rax
cvtsi2sd %rax, %xmm1
divsd .LCPI3_2(%rip), %xmm1
xorpd %xmm0, %xmm0
addsd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16bitonicMinorSortPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16bitonicMinorSortPiii,@object # @_Z16bitonicMinorSortPiii
.section .rodata,"a",@progbits
.globl _Z16bitonicMinorSortPiii
.p2align 3, 0x0
_Z16bitonicMinorSortPiii:
.quad _Z31__device_stub__bitonicMinorSortPiii
.size _Z16bitonicMinorSortPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nk = %d, n = %ld\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\tElapsed time: %f seconds\n"
.size .L.str.1, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16bitonicMinorSortPiii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__bitonicMinorSortPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16bitonicMinorSortPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
int main() {
// Get number of GPUs
int deviceCount;
cudaGetDeviceCount(&deviceCount);
printf("Number of GPU devices: %i\n", deviceCount);
// Get CUDA driver and runtime version
int driverVersion;
int runtimeVersion;
cudaDriverGetVersion(&driverVersion);
cudaRuntimeGetVersion(&runtimeVersion);
printf("CUDA Driver Version / Runtime Version: %d.%d / %d.%d\n", driverVersion/1000, (driverVersion%100)/10, runtimeVersion/1000, (runtimeVersion%100)/10);
// Get device properties
cudaDeviceProp deviceProperties;
for (int i = 0; i < deviceCount; i++) {
cudaGetDeviceProperties(&deviceProperties, i);
printf("Name: %s\n", deviceProperties.name);
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
int main() {
// Get number of GPUs
int deviceCount;
cudaGetDeviceCount(&deviceCount);
printf("Number of GPU devices: %i\n", deviceCount);
// Get CUDA driver and runtime version
int driverVersion;
int runtimeVersion;
cudaDriverGetVersion(&driverVersion);
cudaRuntimeGetVersion(&runtimeVersion);
printf("CUDA Driver Version / Runtime Version: %d.%d / %d.%d\n", driverVersion/1000, (driverVersion%100)/10, runtimeVersion/1000, (runtimeVersion%100)/10);
// Get device properties
cudaDeviceProp deviceProperties;
for (int i = 0; i < deviceCount; i++) {
cudaGetDeviceProperties(&deviceProperties, i);
printf("Name: %s\n", deviceProperties.name);
}
return 0;
} | .file "tmpxft_0016d378_00000000-6_deviceProps.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Number of GPU devices: %i\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "CUDA Driver Version / Runtime Version: %d.%d / %d.%d\n"
.section .rodata.str1.1
.LC2:
.string "Name: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1056, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
call cudaDriverGetVersion@PLT
leaq 12(%rsp), %rdi
call cudaRuntimeGetVersion@PLT
movl 12(%rsp), %esi
movl 8(%rsp), %edx
movslq %esi, %r8
imulq $1374389535, %r8, %rax
sarq $37, %rax
movl %esi, %edi
sarl $31, %edi
subl %edi, %eax
imull $100, %eax, %eax
subl %eax, %esi
movslq %esi, %r9
imulq $1717986919, %r9, %r9
sarq $34, %r9
sarl $31, %esi
imulq $274877907, %r8, %r8
sarq $38, %r8
movslq %edx, %rax
imulq $1374389535, %rax, %rcx
sarq $37, %rcx
movl %edx, %r10d
sarl $31, %r10d
subl %r10d, %ecx
imull $100, %ecx, %ecx
subl %ecx, %edx
movslq %edx, %rcx
imulq $1717986919, %rcx, %rcx
sarq $34, %rcx
sarl $31, %edx
subl %edx, %ecx
imulq $274877907, %rax, %rdx
sarq $38, %rdx
subl %r10d, %edx
subl %esi, %r9d
subl %edi, %r8d
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 4(%rsp)
jle .L4
movl $0, %ebx
leaq .LC2(%rip), %r12
.L5:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 4(%rsp)
jg .L5
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L9
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
int main() {
// Get number of GPUs
int deviceCount;
cudaGetDeviceCount(&deviceCount);
printf("Number of GPU devices: %i\n", deviceCount);
// Get CUDA driver and runtime version
int driverVersion;
int runtimeVersion;
cudaDriverGetVersion(&driverVersion);
cudaRuntimeGetVersion(&runtimeVersion);
printf("CUDA Driver Version / Runtime Version: %d.%d / %d.%d\n", driverVersion/1000, (driverVersion%100)/10, runtimeVersion/1000, (runtimeVersion%100)/10);
// Get device properties
cudaDeviceProp deviceProperties;
for (int i = 0; i < deviceCount; i++) {
cudaGetDeviceProperties(&deviceProperties, i);
printf("Name: %s\n", deviceProperties.name);
}
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
int main() {
// Get number of GPUs
int deviceCount;
hipGetDeviceCount(&deviceCount);
printf("Number of GPU devices: %i\n", deviceCount);
// Get CUDA driver and runtime version
int driverVersion;
int runtimeVersion;
hipDriverGetVersion(&driverVersion);
hipRuntimeGetVersion(&runtimeVersion);
printf("CUDA Driver Version / Runtime Version: %d.%d / %d.%d\n", driverVersion/1000, (driverVersion%100)/10, runtimeVersion/1000, (runtimeVersion%100)/10);
// Get device properties
hipDeviceProp_t deviceProperties;
for (int i = 0; i < deviceCount; i++) {
hipGetDeviceProperties(&deviceProperties, i);
printf("Name: %s\n", deviceProperties.name);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
int main() {
// Get number of GPUs
int deviceCount;
hipGetDeviceCount(&deviceCount);
printf("Number of GPU devices: %i\n", deviceCount);
// Get CUDA driver and runtime version
int driverVersion;
int runtimeVersion;
hipDriverGetVersion(&driverVersion);
hipRuntimeGetVersion(&runtimeVersion);
printf("CUDA Driver Version / Runtime Version: %d.%d / %d.%d\n", driverVersion/1000, (driverVersion%100)/10, runtimeVersion/1000, (runtimeVersion%100)/10);
// Get device properties
hipDeviceProp_t deviceProperties;
for (int i = 0; i < deviceCount; i++) {
hipGetDeviceProperties(&deviceProperties, i);
printf("Name: %s\n", deviceProperties.name);
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
int main() {
// Get number of GPUs
int deviceCount;
hipGetDeviceCount(&deviceCount);
printf("Number of GPU devices: %i\n", deviceCount);
// Get CUDA driver and runtime version
int driverVersion;
int runtimeVersion;
hipDriverGetVersion(&driverVersion);
hipRuntimeGetVersion(&runtimeVersion);
printf("CUDA Driver Version / Runtime Version: %d.%d / %d.%d\n", driverVersion/1000, (driverVersion%100)/10, runtimeVersion/1000, (runtimeVersion%100)/10);
// Get device properties
hipDeviceProp_t deviceProperties;
for (int i = 0; i < deviceCount; i++) {
hipGetDeviceProperties(&deviceProperties, i);
printf("Name: %s\n", deviceProperties.name);
}
return 0;
} | .text
.file "deviceProps.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl 12(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 20(%rsp), %rdi
callq hipDriverGetVersion
leaq 16(%rsp), %rdi
callq hipRuntimeGetVersion
movslq 20(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rcx
shrq $63, %rcx
sarq $38, %rsi
addl %ecx, %esi
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
cltq
imulq $1717986919, %rax, %rdx # imm = 0x66666667
movq %rdx, %rax
shrq $63, %rax
sarq $34, %rdx
addl %eax, %edx
movslq 16(%rsp), %rax
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdi
shrq $63, %rdi
sarq $38, %rcx
addl %edi, %ecx
imulq $1374389535, %rax, %rdi # imm = 0x51EB851F
movq %rdi, %r8
shrq $63, %r8
sarq $37, %rdi
addl %r8d, %edi
imull $100, %edi, %edi
subl %edi, %eax
cltq
imulq $1717986919, %rax, %r8 # imm = 0x66666667
movq %r8, %rax
shrq $63, %rax
sarq $34, %r8
addl %eax, %r8d
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
# kill: def $ecx killed $ecx killed $rcx
# kill: def $r8d killed $r8d killed $r8
xorl %eax, %eax
callq printf
cmpl $0, 12(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
leaq 24(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB0_2
.LBB0_3: # %._crit_edge
xorl %eax, %eax
addq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of GPU devices: %i\n"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA Driver Version / Runtime Version: %d.%d / %d.%d\n"
.size .L.str.1, 54
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Name: %s\n"
.size .L.str.2, 10
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016d378_00000000-6_deviceProps.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Number of GPU devices: %i\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "CUDA Driver Version / Runtime Version: %d.%d / %d.%d\n"
.section .rodata.str1.1
.LC2:
.string "Name: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1056, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
call cudaDriverGetVersion@PLT
leaq 12(%rsp), %rdi
call cudaRuntimeGetVersion@PLT
movl 12(%rsp), %esi
movl 8(%rsp), %edx
movslq %esi, %r8
imulq $1374389535, %r8, %rax
sarq $37, %rax
movl %esi, %edi
sarl $31, %edi
subl %edi, %eax
imull $100, %eax, %eax
subl %eax, %esi
movslq %esi, %r9
imulq $1717986919, %r9, %r9
sarq $34, %r9
sarl $31, %esi
imulq $274877907, %r8, %r8
sarq $38, %r8
movslq %edx, %rax
imulq $1374389535, %rax, %rcx
sarq $37, %rcx
movl %edx, %r10d
sarl $31, %r10d
subl %r10d, %ecx
imull $100, %ecx, %ecx
subl %ecx, %edx
movslq %edx, %rcx
imulq $1717986919, %rcx, %rcx
sarq $34, %rcx
sarl $31, %edx
subl %edx, %ecx
imulq $274877907, %rax, %rdx
sarq $38, %rdx
subl %r10d, %edx
subl %esi, %r9d
subl %edi, %r8d
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 4(%rsp)
jle .L4
movl $0, %ebx
leaq .LC2(%rip), %r12
.L5:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 4(%rsp)
jg .L5
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L9
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "deviceProps.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl 12(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 20(%rsp), %rdi
callq hipDriverGetVersion
leaq 16(%rsp), %rdi
callq hipRuntimeGetVersion
movslq 20(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rcx
shrq $63, %rcx
sarq $38, %rsi
addl %ecx, %esi
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
cltq
imulq $1717986919, %rax, %rdx # imm = 0x66666667
movq %rdx, %rax
shrq $63, %rax
sarq $34, %rdx
addl %eax, %edx
movslq 16(%rsp), %rax
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdi
shrq $63, %rdi
sarq $38, %rcx
addl %edi, %ecx
imulq $1374389535, %rax, %rdi # imm = 0x51EB851F
movq %rdi, %r8
shrq $63, %r8
sarq $37, %rdi
addl %r8d, %edi
imull $100, %edi, %edi
subl %edi, %eax
cltq
imulq $1717986919, %rax, %r8 # imm = 0x66666667
movq %r8, %rax
shrq $63, %rax
sarq $34, %r8
addl %eax, %r8d
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
# kill: def $ecx killed $ecx killed $rcx
# kill: def $r8d killed $r8d killed $r8
xorl %eax, %eax
callq printf
cmpl $0, 12(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
leaq 24(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB0_2
.LBB0_3: # %._crit_edge
xorl %eax, %eax
addq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of GPU devices: %i\n"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA Driver Version / Runtime Version: %d.%d / %d.%d\n"
.size .L.str.1, 54
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Name: %s\n"
.size .L.str.2, 10
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void countRest(int *bin, int *bin_counters, const int num_bins, const int maxBin, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) & (bin[xIndex]<num_bins) )
if (bin[xIndex]>= maxBin) atomicAdd(bin_counters+bin[xIndex],1);
} | code for sm_80
Function : _Z9countRestPiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0005 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0090*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */
/* 0x004fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R2, c[0x0][0x174], P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0205 */
/*00d0*/ MOV R5, 0x1 ; /* 0x0000000100057802 */
/* 0x000fca0000000f00 */
/*00e0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void countRest(int *bin, int *bin_counters, const int num_bins, const int maxBin, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) & (bin[xIndex]<num_bins) )
if (bin[xIndex]>= maxBin) atomicAdd(bin_counters+bin[xIndex],1);
} | .file "tmpxft_00171a67_00000000-6_countRest.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9countRestPiS_iiiPiS_iii
.type _Z33__device_stub__Z9countRestPiS_iiiPiS_iii, @function
_Z33__device_stub__Z9countRestPiS_iiiPiS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9countRestPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9countRestPiS_iiiPiS_iii, .-_Z33__device_stub__Z9countRestPiS_iiiPiS_iii
.globl _Z9countRestPiS_iii
.type _Z9countRestPiS_iii, @function
_Z9countRestPiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9countRestPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9countRestPiS_iii, .-_Z9countRestPiS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9countRestPiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9countRestPiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void countRest(int *bin, int *bin_counters, const int num_bins, const int maxBin, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) & (bin[xIndex]<num_bins) )
if (bin[xIndex]>= maxBin) atomicAdd(bin_counters+bin[xIndex],1);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void countRest(int *bin, int *bin_counters, const int num_bins, const int maxBin, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) & (bin[xIndex]<num_bins) )
if (bin[xIndex]>= maxBin) atomicAdd(bin_counters+bin[xIndex],1);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void countRest(int *bin, int *bin_counters, const int num_bins, const int maxBin, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) & (bin[xIndex]<num_bins) )
if (bin[xIndex]>= maxBin) atomicAdd(bin_counters+bin[xIndex],1);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9countRestPiS_iii
.globl _Z9countRestPiS_iii
.p2align 8
.type _Z9countRestPiS_iii,@function
_Z9countRestPiS_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x18
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s6, v1
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e64 s2, s4, v0
v_cmp_le_i32_e64 s3, s5, v0
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9countRestPiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9countRestPiS_iii, .Lfunc_end0-_Z9countRestPiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9countRestPiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9countRestPiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void countRest(int *bin, int *bin_counters, const int num_bins, const int maxBin, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( (xIndex < n) & (bin[xIndex]<num_bins) )
if (bin[xIndex]>= maxBin) atomicAdd(bin_counters+bin[xIndex],1);
} | .text
.file "countRest.hip"
.globl _Z24__device_stub__countRestPiS_iii # -- Begin function _Z24__device_stub__countRestPiS_iii
.p2align 4, 0x90
.type _Z24__device_stub__countRestPiS_iii,@function
_Z24__device_stub__countRestPiS_iii: # @_Z24__device_stub__countRestPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9countRestPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__countRestPiS_iii, .Lfunc_end0-_Z24__device_stub__countRestPiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9countRestPiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9countRestPiS_iii,@object # @_Z9countRestPiS_iii
.section .rodata,"a",@progbits
.globl _Z9countRestPiS_iii
.p2align 3, 0x0
_Z9countRestPiS_iii:
.quad _Z24__device_stub__countRestPiS_iii
.size _Z9countRestPiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9countRestPiS_iii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__countRestPiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9countRestPiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9countRestPiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0005 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0090*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */
/* 0x004fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R2, c[0x0][0x174], P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0205 */
/*00d0*/ MOV R5, 0x1 ; /* 0x0000000100057802 */
/* 0x000fca0000000f00 */
/*00e0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9countRestPiS_iii
.globl _Z9countRestPiS_iii
.p2align 8
.type _Z9countRestPiS_iii,@function
_Z9countRestPiS_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x18
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s6, v1
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e64 s2, s4, v0
v_cmp_le_i32_e64 s3, s5, v0
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9countRestPiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9countRestPiS_iii, .Lfunc_end0-_Z9countRestPiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9countRestPiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9countRestPiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00171a67_00000000-6_countRest.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9countRestPiS_iiiPiS_iii
.type _Z33__device_stub__Z9countRestPiS_iiiPiS_iii, @function
_Z33__device_stub__Z9countRestPiS_iiiPiS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9countRestPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9countRestPiS_iiiPiS_iii, .-_Z33__device_stub__Z9countRestPiS_iiiPiS_iii
.globl _Z9countRestPiS_iii
.type _Z9countRestPiS_iii, @function
_Z9countRestPiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9countRestPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9countRestPiS_iii, .-_Z9countRestPiS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9countRestPiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9countRestPiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "countRest.hip"
.globl _Z24__device_stub__countRestPiS_iii # -- Begin function _Z24__device_stub__countRestPiS_iii
.p2align 4, 0x90
.type _Z24__device_stub__countRestPiS_iii,@function
_Z24__device_stub__countRestPiS_iii: # @_Z24__device_stub__countRestPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9countRestPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__countRestPiS_iii, .Lfunc_end0-_Z24__device_stub__countRestPiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9countRestPiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9countRestPiS_iii,@object # @_Z9countRestPiS_iii
.section .rodata,"a",@progbits
.globl _Z9countRestPiS_iii
.p2align 3, 0x0
_Z9countRestPiS_iii:
.quad _Z24__device_stub__countRestPiS_iii
.size _Z9countRestPiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9countRestPiS_iii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__countRestPiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9countRestPiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
#include <cuda.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <curand.h>
#include <curand_kernel.h>
#define ALIVE 1
#define DEAD 0
# define CUDA_SAFE_CALL( call) { \
cudaError err = call; \
if( cudaSuccess != err) { \
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n", \
__FILE__, __LINE__, cudaGetErrorString( err) ); \
exit(EXIT_FAILURE); \
} }
int termCheck(int *prev, int *next, int N, int M, int gen);
__global__ void kernel_update(int* t,int* t1,int N,int M);
__global__ void initdat(int *t, int *t1, int N, int M, time_t clock);
int main(int argc, char *argv[]) {
int N, /* rows of the grid */
M, /* columns of the grid */
Gens, /* amount of generations. */
perGens; /* checks termination per perGens generations. if perGens zero no termination check */
int *grid, *grid1;
int *gpu_grid, *gpu_grid1, *gpu_temp;
if ( argc != 5) {
printf("Error! Missing mandatory argument.\n");
return 1;
}
N = atoi(argv[1]); /* Getting rows amount */
M = atoi(argv[2]); /* Getting columns amount */
Gens = atoi(argv[3]); /* Getting Gens */
perGens = atoi(argv[4]);
if (Gens <= 0 || N < 0 || M < 0 || perGens < 0) {
printf("Please give positive values for rows/cols and Generations\n");
return 1;
}
int blockSize = 512;
int numBlocks = (N*M + blockSize - 1) / blockSize;
grid = (int*)malloc(sizeof(int)*N*M);
grid1 = (int*)malloc(sizeof(int)*N*M);
CUDA_SAFE_CALL(cudaMalloc(&gpu_grid, N*M*sizeof(int)));
CUDA_SAFE_CALL(cudaMalloc(&gpu_grid1, N*M*sizeof(int)));
/* Initialize random data */
initdat<<<numBlocks,blockSize>>>(gpu_grid, gpu_grid1, N, M, time(NULL));
CUDA_SAFE_CALL(cudaDeviceSynchronize());
for (int k = 1; k <= Gens; k++) {
kernel_update<<<numBlocks,blockSize>>>(gpu_grid,gpu_grid1,N,M);
CUDA_SAFE_CALL(cudaDeviceSynchronize());
if ( perGens ) {
CUDA_SAFE_CALL(cudaMemcpy(grid, gpu_grid, N*M*sizeof(int), cudaMemcpyDeviceToHost));
CUDA_SAFE_CALL(cudaMemcpy(grid1, gpu_grid1, N*M*sizeof(int), cudaMemcpyDeviceToHost));
if ( k % perGens == 0) {
if (termCheck(grid, grid1, N, M, k)) {
cudaFree(gpu_grid1);
cudaFree(gpu_grid);
free(grid);
free(grid1);
return 0;
}
}
}
gpu_temp = gpu_grid;
gpu_grid = gpu_grid1;
gpu_grid1 = gpu_temp;
}
printf("Reached requested generations %d\n",Gens );
cudaFree(gpu_grid1);
cudaFree(gpu_grid);
free(grid);
free(grid1);
return 0;
}
int termCheck(int *prev, int *next, int N, int M, int gen){
int allDiff = 0;
int sum = 0;
for (int i = 0; i < N; i++) {
for (int j = 0; j < M; j++) {
if (prev[i*M+j] != next[i*M+j]) {
allDiff = 1;
}
sum += next[i*M+j];
}
}
if (!sum) {
printf("All cells are dead at generation %d\n", gen);
return 1;
}
else if (!allDiff) {
printf("Generation %d is the same with generation %d\n", gen, gen-1);
return 1;
}
return 0;
}
__global__ void kernel_update(int* t,int* t1,int N,int M){
int x = blockIdx.x * blockDim.x + threadIdx.x;
/*update starts*/
if (0 <= x && x < N*M ){ //if not out of bounds then..
int i,j,neighbours;
i = x / M;
j = x % M;
if (i+1 > N-1) {
if (j-1 < 0) {
/* eimai o bot_left */
neighbours = t[(i-1)*M+M-1] + t[(i-1)*M+j] + t[(i-1)*M+j+1] + t[i*M+j+1] + t[0*M+j+1] + t[0*M+j] + t[0*M+M-1] + t[i*M+M-1];
}
else if (j+1 > M-1) {
/* eimai o bot_right */
neighbours = t[(i-1)*M+j-1] + t[(i-1)*M+j] + t[(i-1)*M+0] + t[i*M+0] + t[0*M+0] + t[0*M+j] + t[0*M+j-1] + t[i*M+j-1];
}
else{
/* eimai aplos bot */
neighbours = t[(i-1)*M+j-1] + t[(i-1)*M+j] + t[(i-1)*M+j+1] + t[i*M+j+1] + t[0*M+j+1] + t[0*M+j] + t[0*M+j-1] + t[i*M+j-1];
}
}
else if (i-1 < 0) {
if (j-1 < 0) {
/* eimai o top_left */
neighbours = t[(N-1)*M+M-1] + t[(N-1)*M+j] + t[(N-1)*M+j+1] + t[i*M+j+1] + t[(i+1)*M+j+1] + t[(i+1)*M+j] + t[(i+1)*M+M-1] + t[i*M+M-1];
}
else if (j+1 > M-1) {
/* eimai o top_right */
neighbours = t[(N-1)*M+j-1] + t[(N-1)*M+j] + t[(N-1)*M+0] + t[i*M+0] + t[(i+1)*M+0] + t[(i+1)*M+j] + t[(i+1)*M+j-1] + t[i*M+j-1];
}
else{
/* eimai aplos top */
neighbours = t[(N-1)*M+j-1] + t[(N-1)*M+j] + t[(N-1)*M+j+1] + t[i*M+j+1] + t[(i+1)*M+j+1] + t[(i+1)*M+j] + t[(i+1)*M+j-1] + t[i*M+j-1];
}
}
else if (j-1 < 0) {
/* eimai aplos left */
neighbours = t[(i-1)*M+M-1] + t[(i-1)*M+j] + t[(i-1)*M+j+1] + t[i*M+j+1] + t[(i+1)*M+j+1] + t[(i+1)*M+j] + t[(i+1)*M+M-1] + t[i*M+M-1];
}
else if (j+1 > M-1) {
/* eimai aplos right */
neighbours = t[(i-1)*M+j-1] + t[(i-1)*M+j] + t[(i-1)*M+0] + t[i*M+0] + t[(i+1)*M+0] + t[(i+1)*M+j] + t[(i+1)*M+j-1] + t[i*M+j-1];
}
else{
/* oi geitones mou den peftoun eksw */
neighbours = t[(i-1)*M+j-1] + t[(i-1)*M+j] + t[(i-1)*M+j+1] + t[i*M+j+1] + t[(i+1)*M+j+1] + t[(i+1)*M+j] + t[(i+1)*M+j-1] + t[i*M+j-1];
}
/* kanones paixnidiou edw */
if (t[x] == ALIVE) {
if (neighbours <= 1 || neighbours >= 4) {
t1[x] = DEAD;
}
else{
t1[x] = ALIVE;
}
}
else if (t[x] == DEAD && neighbours == 3) {
t1[x] = ALIVE;
}
else{
t1[x] = DEAD;
}
}
}
__global__ void initdat(int *t, int *t1, int N, int M, time_t clock){
int x = blockIdx.x * blockDim.x + threadIdx.x;
curandState_t state;
curand_init(clock,x,0,&state);
if (0 <= x && x < N*M ){
t[x] = (curand(&state) % 4) ? DEAD : ALIVE;
t1[x] = DEAD;
}
} | .file "tmpxft_0013aa6c_00000000-6_cuda_gameoflife.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2275:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2275:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "All cells are dead at generation %d\n"
.align 8
.LC1:
.string "Generation %d is the same with generation %d\n"
.text
.globl _Z9termCheckPiS_iii
.type _Z9termCheckPiS_iii, @function
_Z9termCheckPiS_iii:
.LFB2272:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %r8d, %r13d
testl %edx, %edx
jle .L4
movq %rdi, %r9
movq %rsi, %r10
movl %edx, %r12d
movl %ecx, %ebp
movl $0, %ebx
movl $0, %r8d
movl $0, %ecx
movl $0, %esi
movslq %ebp, %r14
movl $1, %r11d
jmp .L5
.L9:
movslq %ebx, %rdi
leaq 0(,%rdi,4), %rax
addq %r14, %rdi
salq $2, %rdi
.L7:
movl (%r10,%rax), %edx
cmpl %edx, (%r9,%rax)
cmovne %r11d, %esi
addl %edx, %ecx
addq $4, %rax
cmpq %rdi, %rax
jne .L7
.L10:
addl $1, %r8d
addl %ebp, %ebx
cmpl %r8d, %r12d
je .L8
.L5:
testl %ebp, %ebp
jg .L9
jmp .L10
.L8:
testl %ecx, %ecx
je .L4
movl $0, %eax
testl %esi, %esi
je .L17
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
movl %r13d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L3
.L17:
leal -1(%r13), %ecx
movl %r13d, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
jmp .L3
.cfi_endproc
.LFE2272:
.size _Z9termCheckPiS_iii, .-_Z9termCheckPiS_iii
.globl _Z37__device_stub__Z13kernel_updatePiS_iiPiS_ii
.type _Z37__device_stub__Z13kernel_updatePiS_iiPiS_ii, @function
_Z37__device_stub__Z13kernel_updatePiS_iiPiS_ii:
.LFB2297:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kernel_updatePiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2297:
.size _Z37__device_stub__Z13kernel_updatePiS_iiPiS_ii, .-_Z37__device_stub__Z13kernel_updatePiS_iiPiS_ii
.globl _Z13kernel_updatePiS_ii
.type _Z13kernel_updatePiS_ii, @function
_Z13kernel_updatePiS_ii:
.LFB2298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13kernel_updatePiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size _Z13kernel_updatePiS_ii, .-_Z13kernel_updatePiS_ii
.globl _Z31__device_stub__Z7initdatPiS_iilPiS_iil
.type _Z31__device_stub__Z7initdatPiS_iilPiS_iil, @function
_Z31__device_stub__Z7initdatPiS_iilPiS_iil:
.LFB2299:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7initdatPiS_iil(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2299:
.size _Z31__device_stub__Z7initdatPiS_iilPiS_iil, .-_Z31__device_stub__Z7initdatPiS_iilPiS_iil
.globl _Z7initdatPiS_iil
.type _Z7initdatPiS_iil, @function
_Z7initdatPiS_iil:
.LFB2300:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7initdatPiS_iilPiS_iil
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2300:
.size _Z7initdatPiS_iil, .-_Z7initdatPiS_iil
.section .rodata.str1.8
.align 8
.LC2:
.string "Error! Missing mandatory argument.\n"
.align 8
.LC3:
.string "Please give positive values for rows/cols and Generations\n"
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/patric94/Parallel-Programming/master/CUDA/cuda_gameoflife.cu"
.align 8
.LC5:
.string "Cuda error in file '%s' in line %i : %s.\n"
.align 8
.LC6:
.string "Reached requested generations %d\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $5, %edi
je .L35
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, 12(%rsp)
.L34:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl 12(%rsp), %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 20(%rsp)
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, 16(%rsp)
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %r14d
movq 32(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
testl %r12d, %r12d
jle .L37
movl %ebx, %edx
orl %r15d, %edx
orl %eax, %edx
jns .L38
.L37:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 12(%rsp)
jmp .L34
.L38:
movl %ebx, %eax
imull %r15d, %eax
addl $511, %eax
movl $512, %ecx
cltd
idivl %ecx
movl %eax, %r13d
movslq %ebx, %rbx
movslq %r15d, %r15
imulq %r15, %rbx
leaq 0(,%rbx,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r15
movq %r12, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L54
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L55
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %r13d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L41:
call cudaDeviceSynchronize@PLT
movl $1, %ebx
testl %eax, %eax
je .L42
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $58, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $53, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $54, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
movl $0, %edi
call time@PLT
movq %rax, %r8
movl 16(%rsp), %ecx
movl 20(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z31__device_stub__Z7initdatPiS_iilPiS_iil
jmp .L41
.L58:
movl 16(%rsp), %ecx
movl 20(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z37__device_stub__Z13kernel_updatePiS_iiPiS_ii
jmp .L43
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $63, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $66, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $67, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L45:
movq 32(%rsp), %rax
movq 40(%rsp), %rdx
movq %rdx, 32(%rsp)
movq %rax, 40(%rsp)
addl $1, %ebx
cmpl %r14d, %ebx
jg .L57
.L42:
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %r13d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L43:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L59
testl %ebp, %ebp
je .L45
movl $2, %ecx
movq %r12, %rdx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L60
movl $2, %ecx
movq %r12, %rdx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L61
movl %ebx, %eax
cltd
idivl %ebp
movl %edx, 12(%rsp)
testl %edx, %edx
jne .L45
movl %ebx, %r8d
movl 16(%rsp), %ecx
movl 20(%rsp), %edx
movq 24(%rsp), %rsi
movq %r15, %rdi
call _Z9termCheckPiS_iii
testl %eax, %eax
je .L45
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
jmp .L34
.L57:
movl %r14d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movl $0, 12(%rsp)
jmp .L34
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "_Z7initdatPiS_iil"
.LC8:
.string "_Z13kernel_updatePiS_ii"
.LC9:
.string "precalc_xorwow_matrix"
.LC10:
.string "precalc_xorwow_offset_matrix"
.LC11:
.string "mrg32k3aM1"
.LC12:
.string "mrg32k3aM2"
.LC13:
.string "mrg32k3aM1SubSeq"
.LC14:
.string "mrg32k3aM2SubSeq"
.LC15:
.string "mrg32k3aM1Seq"
.LC16:
.string "mrg32k3aM2Seq"
.LC17:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2302:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7initdatPiS_iil(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_updatePiS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2302:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
#include <cuda.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <curand.h>
#include <curand_kernel.h>
#define ALIVE 1
#define DEAD 0
# define CUDA_SAFE_CALL( call) { \
cudaError err = call; \
if( cudaSuccess != err) { \
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n", \
__FILE__, __LINE__, cudaGetErrorString( err) ); \
exit(EXIT_FAILURE); \
} }
int termCheck(int *prev, int *next, int N, int M, int gen);
__global__ void kernel_update(int* t,int* t1,int N,int M);
__global__ void initdat(int *t, int *t1, int N, int M, time_t clock);
int main(int argc, char *argv[]) {
int N, /* rows of the grid */
M, /* columns of the grid */
Gens, /* amount of generations. */
perGens; /* checks termination per perGens generations. if perGens zero no termination check */
int *grid, *grid1;
int *gpu_grid, *gpu_grid1, *gpu_temp;
if ( argc != 5) {
printf("Error! Missing mandatory argument.\n");
return 1;
}
N = atoi(argv[1]); /* Getting rows amount */
M = atoi(argv[2]); /* Getting columns amount */
Gens = atoi(argv[3]); /* Getting Gens */
perGens = atoi(argv[4]);
if (Gens <= 0 || N < 0 || M < 0 || perGens < 0) {
printf("Please give positive values for rows/cols and Generations\n");
return 1;
}
int blockSize = 512;
int numBlocks = (N*M + blockSize - 1) / blockSize;
grid = (int*)malloc(sizeof(int)*N*M);
grid1 = (int*)malloc(sizeof(int)*N*M);
CUDA_SAFE_CALL(cudaMalloc(&gpu_grid, N*M*sizeof(int)));
CUDA_SAFE_CALL(cudaMalloc(&gpu_grid1, N*M*sizeof(int)));
/* Initialize random data */
initdat<<<numBlocks,blockSize>>>(gpu_grid, gpu_grid1, N, M, time(NULL));
CUDA_SAFE_CALL(cudaDeviceSynchronize());
for (int k = 1; k <= Gens; k++) {
kernel_update<<<numBlocks,blockSize>>>(gpu_grid,gpu_grid1,N,M);
CUDA_SAFE_CALL(cudaDeviceSynchronize());
if ( perGens ) {
CUDA_SAFE_CALL(cudaMemcpy(grid, gpu_grid, N*M*sizeof(int), cudaMemcpyDeviceToHost));
CUDA_SAFE_CALL(cudaMemcpy(grid1, gpu_grid1, N*M*sizeof(int), cudaMemcpyDeviceToHost));
if ( k % perGens == 0) {
if (termCheck(grid, grid1, N, M, k)) {
cudaFree(gpu_grid1);
cudaFree(gpu_grid);
free(grid);
free(grid1);
return 0;
}
}
}
gpu_temp = gpu_grid;
gpu_grid = gpu_grid1;
gpu_grid1 = gpu_temp;
}
printf("Reached requested generations %d\n",Gens );
cudaFree(gpu_grid1);
cudaFree(gpu_grid);
free(grid);
free(grid1);
return 0;
}
int termCheck(int *prev, int *next, int N, int M, int gen){
int allDiff = 0;
int sum = 0;
for (int i = 0; i < N; i++) {
for (int j = 0; j < M; j++) {
if (prev[i*M+j] != next[i*M+j]) {
allDiff = 1;
}
sum += next[i*M+j];
}
}
if (!sum) {
printf("All cells are dead at generation %d\n", gen);
return 1;
}
else if (!allDiff) {
printf("Generation %d is the same with generation %d\n", gen, gen-1);
return 1;
}
return 0;
}
__global__ void kernel_update(int* t,int* t1,int N,int M){
int x = blockIdx.x * blockDim.x + threadIdx.x;
/*update starts*/
if (0 <= x && x < N*M ){ //if not out of bounds then..
int i,j,neighbours;
i = x / M;
j = x % M;
if (i+1 > N-1) {
if (j-1 < 0) {
/* eimai o bot_left */
neighbours = t[(i-1)*M+M-1] + t[(i-1)*M+j] + t[(i-1)*M+j+1] + t[i*M+j+1] + t[0*M+j+1] + t[0*M+j] + t[0*M+M-1] + t[i*M+M-1];
}
else if (j+1 > M-1) {
/* eimai o bot_right */
neighbours = t[(i-1)*M+j-1] + t[(i-1)*M+j] + t[(i-1)*M+0] + t[i*M+0] + t[0*M+0] + t[0*M+j] + t[0*M+j-1] + t[i*M+j-1];
}
else{
/* eimai aplos bot */
neighbours = t[(i-1)*M+j-1] + t[(i-1)*M+j] + t[(i-1)*M+j+1] + t[i*M+j+1] + t[0*M+j+1] + t[0*M+j] + t[0*M+j-1] + t[i*M+j-1];
}
}
else if (i-1 < 0) {
if (j-1 < 0) {
/* eimai o top_left */
neighbours = t[(N-1)*M+M-1] + t[(N-1)*M+j] + t[(N-1)*M+j+1] + t[i*M+j+1] + t[(i+1)*M+j+1] + t[(i+1)*M+j] + t[(i+1)*M+M-1] + t[i*M+M-1];
}
else if (j+1 > M-1) {
/* eimai o top_right */
neighbours = t[(N-1)*M+j-1] + t[(N-1)*M+j] + t[(N-1)*M+0] + t[i*M+0] + t[(i+1)*M+0] + t[(i+1)*M+j] + t[(i+1)*M+j-1] + t[i*M+j-1];
}
else{
/* eimai aplos top */
neighbours = t[(N-1)*M+j-1] + t[(N-1)*M+j] + t[(N-1)*M+j+1] + t[i*M+j+1] + t[(i+1)*M+j+1] + t[(i+1)*M+j] + t[(i+1)*M+j-1] + t[i*M+j-1];
}
}
else if (j-1 < 0) {
/* eimai aplos left */
neighbours = t[(i-1)*M+M-1] + t[(i-1)*M+j] + t[(i-1)*M+j+1] + t[i*M+j+1] + t[(i+1)*M+j+1] + t[(i+1)*M+j] + t[(i+1)*M+M-1] + t[i*M+M-1];
}
else if (j+1 > M-1) {
/* eimai aplos right */
neighbours = t[(i-1)*M+j-1] + t[(i-1)*M+j] + t[(i-1)*M+0] + t[i*M+0] + t[(i+1)*M+0] + t[(i+1)*M+j] + t[(i+1)*M+j-1] + t[i*M+j-1];
}
else{
/* oi geitones mou den peftoun eksw */
neighbours = t[(i-1)*M+j-1] + t[(i-1)*M+j] + t[(i-1)*M+j+1] + t[i*M+j+1] + t[(i+1)*M+j+1] + t[(i+1)*M+j] + t[(i+1)*M+j-1] + t[i*M+j-1];
}
/* kanones paixnidiou edw */
if (t[x] == ALIVE) {
if (neighbours <= 1 || neighbours >= 4) {
t1[x] = DEAD;
}
else{
t1[x] = ALIVE;
}
}
else if (t[x] == DEAD && neighbours == 3) {
t1[x] = ALIVE;
}
else{
t1[x] = DEAD;
}
}
}
__global__ void initdat(int *t, int *t1, int N, int M, time_t clock){
int x = blockIdx.x * blockDim.x + threadIdx.x;
curandState_t state;
curand_init(clock,x,0,&state);
if (0 <= x && x < N*M ){
t[x] = (curand(&state) % 4) ? DEAD : ALIVE;
t1[x] = DEAD;
}
} | #include <stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define ALIVE 1
#define DEAD 0
# define CUDA_SAFE_CALL( call) { \
hipError_t err = call; \
if( hipSuccess != err) { \
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n", \
__FILE__, __LINE__, hipGetErrorString( err) ); \
exit(EXIT_FAILURE); \
} }
int termCheck(int *prev, int *next, int N, int M, int gen);
__global__ void kernel_update(int* t,int* t1,int N,int M);
__global__ void initdat(int *t, int *t1, int N, int M, time_t clock);
int main(int argc, char *argv[]) {
int N, /* rows of the grid */
M, /* columns of the grid */
Gens, /* amount of generations. */
perGens; /* checks termination per perGens generations. if perGens zero no termination check */
int *grid, *grid1;
int *gpu_grid, *gpu_grid1, *gpu_temp;
if ( argc != 5) {
printf("Error! Missing mandatory argument.\n");
return 1;
}
N = atoi(argv[1]); /* Getting rows amount */
M = atoi(argv[2]); /* Getting columns amount */
Gens = atoi(argv[3]); /* Getting Gens */
perGens = atoi(argv[4]);
if (Gens <= 0 || N < 0 || M < 0 || perGens < 0) {
printf("Please give positive values for rows/cols and Generations\n");
return 1;
}
int blockSize = 512;
int numBlocks = (N*M + blockSize - 1) / blockSize;
grid = (int*)malloc(sizeof(int)*N*M);
grid1 = (int*)malloc(sizeof(int)*N*M);
CUDA_SAFE_CALL(hipMalloc(&gpu_grid, N*M*sizeof(int)));
CUDA_SAFE_CALL(hipMalloc(&gpu_grid1, N*M*sizeof(int)));
/* Initialize random data */
initdat<<<numBlocks,blockSize>>>(gpu_grid, gpu_grid1, N, M, time(NULL));
CUDA_SAFE_CALL(hipDeviceSynchronize());
for (int k = 1; k <= Gens; k++) {
kernel_update<<<numBlocks,blockSize>>>(gpu_grid,gpu_grid1,N,M);
CUDA_SAFE_CALL(hipDeviceSynchronize());
if ( perGens ) {
CUDA_SAFE_CALL(hipMemcpy(grid, gpu_grid, N*M*sizeof(int), hipMemcpyDeviceToHost));
CUDA_SAFE_CALL(hipMemcpy(grid1, gpu_grid1, N*M*sizeof(int), hipMemcpyDeviceToHost));
if ( k % perGens == 0) {
if (termCheck(grid, grid1, N, M, k)) {
hipFree(gpu_grid1);
hipFree(gpu_grid);
free(grid);
free(grid1);
return 0;
}
}
}
gpu_temp = gpu_grid;
gpu_grid = gpu_grid1;
gpu_grid1 = gpu_temp;
}
printf("Reached requested generations %d\n",Gens );
hipFree(gpu_grid1);
hipFree(gpu_grid);
free(grid);
free(grid1);
return 0;
}
int termCheck(int *prev, int *next, int N, int M, int gen){
int allDiff = 0;
int sum = 0;
for (int i = 0; i < N; i++) {
for (int j = 0; j < M; j++) {
if (prev[i*M+j] != next[i*M+j]) {
allDiff = 1;
}
sum += next[i*M+j];
}
}
if (!sum) {
printf("All cells are dead at generation %d\n", gen);
return 1;
}
else if (!allDiff) {
printf("Generation %d is the same with generation %d\n", gen, gen-1);
return 1;
}
return 0;
}
__global__ void kernel_update(int* t,int* t1,int N,int M){
int x = blockIdx.x * blockDim.x + threadIdx.x;
/*update starts*/
if (0 <= x && x < N*M ){ //if not out of bounds then..
int i,j,neighbours;
i = x / M;
j = x % M;
if (i+1 > N-1) {
if (j-1 < 0) {
/* eimai o bot_left */
neighbours = t[(i-1)*M+M-1] + t[(i-1)*M+j] + t[(i-1)*M+j+1] + t[i*M+j+1] + t[0*M+j+1] + t[0*M+j] + t[0*M+M-1] + t[i*M+M-1];
}
else if (j+1 > M-1) {
/* eimai o bot_right */
neighbours = t[(i-1)*M+j-1] + t[(i-1)*M+j] + t[(i-1)*M+0] + t[i*M+0] + t[0*M+0] + t[0*M+j] + t[0*M+j-1] + t[i*M+j-1];
}
else{
/* eimai aplos bot */
neighbours = t[(i-1)*M+j-1] + t[(i-1)*M+j] + t[(i-1)*M+j+1] + t[i*M+j+1] + t[0*M+j+1] + t[0*M+j] + t[0*M+j-1] + t[i*M+j-1];
}
}
else if (i-1 < 0) {
if (j-1 < 0) {
/* eimai o top_left */
neighbours = t[(N-1)*M+M-1] + t[(N-1)*M+j] + t[(N-1)*M+j+1] + t[i*M+j+1] + t[(i+1)*M+j+1] + t[(i+1)*M+j] + t[(i+1)*M+M-1] + t[i*M+M-1];
}
else if (j+1 > M-1) {
/* eimai o top_right */
neighbours = t[(N-1)*M+j-1] + t[(N-1)*M+j] + t[(N-1)*M+0] + t[i*M+0] + t[(i+1)*M+0] + t[(i+1)*M+j] + t[(i+1)*M+j-1] + t[i*M+j-1];
}
else{
/* eimai aplos top */
neighbours = t[(N-1)*M+j-1] + t[(N-1)*M+j] + t[(N-1)*M+j+1] + t[i*M+j+1] + t[(i+1)*M+j+1] + t[(i+1)*M+j] + t[(i+1)*M+j-1] + t[i*M+j-1];
}
}
else if (j-1 < 0) {
/* eimai aplos left */
neighbours = t[(i-1)*M+M-1] + t[(i-1)*M+j] + t[(i-1)*M+j+1] + t[i*M+j+1] + t[(i+1)*M+j+1] + t[(i+1)*M+j] + t[(i+1)*M+M-1] + t[i*M+M-1];
}
else if (j+1 > M-1) {
/* eimai aplos right */
neighbours = t[(i-1)*M+j-1] + t[(i-1)*M+j] + t[(i-1)*M+0] + t[i*M+0] + t[(i+1)*M+0] + t[(i+1)*M+j] + t[(i+1)*M+j-1] + t[i*M+j-1];
}
else{
/* oi geitones mou den peftoun eksw */
neighbours = t[(i-1)*M+j-1] + t[(i-1)*M+j] + t[(i-1)*M+j+1] + t[i*M+j+1] + t[(i+1)*M+j+1] + t[(i+1)*M+j] + t[(i+1)*M+j-1] + t[i*M+j-1];
}
/* kanones paixnidiou edw */
if (t[x] == ALIVE) {
if (neighbours <= 1 || neighbours >= 4) {
t1[x] = DEAD;
}
else{
t1[x] = ALIVE;
}
}
else if (t[x] == DEAD && neighbours == 3) {
t1[x] = ALIVE;
}
else{
t1[x] = DEAD;
}
}
}
__global__ void initdat(int *t, int *t1, int N, int M, time_t clock){
int x = blockIdx.x * blockDim.x + threadIdx.x;
hiprandState_t state;
hiprand_init(clock,x,0,&state);
if (0 <= x && x < N*M ){
t[x] = (hiprand(&state) % 4) ? DEAD : ALIVE;
t1[x] = DEAD;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define ALIVE 1
#define DEAD 0
# define CUDA_SAFE_CALL( call) { \
hipError_t err = call; \
if( hipSuccess != err) { \
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n", \
__FILE__, __LINE__, hipGetErrorString( err) ); \
exit(EXIT_FAILURE); \
} }
int termCheck(int *prev, int *next, int N, int M, int gen);
__global__ void kernel_update(int* t,int* t1,int N,int M);
__global__ void initdat(int *t, int *t1, int N, int M, time_t clock);
int main(int argc, char *argv[]) {
int N, /* rows of the grid */
M, /* columns of the grid */
Gens, /* amount of generations. */
perGens; /* checks termination per perGens generations. if perGens zero no termination check */
int *grid, *grid1;
int *gpu_grid, *gpu_grid1, *gpu_temp;
if ( argc != 5) {
printf("Error! Missing mandatory argument.\n");
return 1;
}
N = atoi(argv[1]); /* Getting rows amount */
M = atoi(argv[2]); /* Getting columns amount */
Gens = atoi(argv[3]); /* Getting Gens */
perGens = atoi(argv[4]);
if (Gens <= 0 || N < 0 || M < 0 || perGens < 0) {
printf("Please give positive values for rows/cols and Generations\n");
return 1;
}
int blockSize = 512;
int numBlocks = (N*M + blockSize - 1) / blockSize;
grid = (int*)malloc(sizeof(int)*N*M);
grid1 = (int*)malloc(sizeof(int)*N*M);
CUDA_SAFE_CALL(hipMalloc(&gpu_grid, N*M*sizeof(int)));
CUDA_SAFE_CALL(hipMalloc(&gpu_grid1, N*M*sizeof(int)));
/* Initialize random data */
initdat<<<numBlocks,blockSize>>>(gpu_grid, gpu_grid1, N, M, time(NULL));
CUDA_SAFE_CALL(hipDeviceSynchronize());
for (int k = 1; k <= Gens; k++) {
kernel_update<<<numBlocks,blockSize>>>(gpu_grid,gpu_grid1,N,M);
CUDA_SAFE_CALL(hipDeviceSynchronize());
if ( perGens ) {
CUDA_SAFE_CALL(hipMemcpy(grid, gpu_grid, N*M*sizeof(int), hipMemcpyDeviceToHost));
CUDA_SAFE_CALL(hipMemcpy(grid1, gpu_grid1, N*M*sizeof(int), hipMemcpyDeviceToHost));
if ( k % perGens == 0) {
if (termCheck(grid, grid1, N, M, k)) {
hipFree(gpu_grid1);
hipFree(gpu_grid);
free(grid);
free(grid1);
return 0;
}
}
}
gpu_temp = gpu_grid;
gpu_grid = gpu_grid1;
gpu_grid1 = gpu_temp;
}
printf("Reached requested generations %d\n",Gens );
hipFree(gpu_grid1);
hipFree(gpu_grid);
free(grid);
free(grid1);
return 0;
}
int termCheck(int *prev, int *next, int N, int M, int gen){
int allDiff = 0;
int sum = 0;
for (int i = 0; i < N; i++) {
for (int j = 0; j < M; j++) {
if (prev[i*M+j] != next[i*M+j]) {
allDiff = 1;
}
sum += next[i*M+j];
}
}
if (!sum) {
printf("All cells are dead at generation %d\n", gen);
return 1;
}
else if (!allDiff) {
printf("Generation %d is the same with generation %d\n", gen, gen-1);
return 1;
}
return 0;
}
__global__ void kernel_update(int* t,int* t1,int N,int M){
int x = blockIdx.x * blockDim.x + threadIdx.x;
/*update starts*/
if (0 <= x && x < N*M ){ //if not out of bounds then..
int i,j,neighbours;
i = x / M;
j = x % M;
if (i+1 > N-1) {
if (j-1 < 0) {
/* eimai o bot_left */
neighbours = t[(i-1)*M+M-1] + t[(i-1)*M+j] + t[(i-1)*M+j+1] + t[i*M+j+1] + t[0*M+j+1] + t[0*M+j] + t[0*M+M-1] + t[i*M+M-1];
}
else if (j+1 > M-1) {
/* eimai o bot_right */
neighbours = t[(i-1)*M+j-1] + t[(i-1)*M+j] + t[(i-1)*M+0] + t[i*M+0] + t[0*M+0] + t[0*M+j] + t[0*M+j-1] + t[i*M+j-1];
}
else{
/* eimai aplos bot */
neighbours = t[(i-1)*M+j-1] + t[(i-1)*M+j] + t[(i-1)*M+j+1] + t[i*M+j+1] + t[0*M+j+1] + t[0*M+j] + t[0*M+j-1] + t[i*M+j-1];
}
}
else if (i-1 < 0) {
if (j-1 < 0) {
/* eimai o top_left */
neighbours = t[(N-1)*M+M-1] + t[(N-1)*M+j] + t[(N-1)*M+j+1] + t[i*M+j+1] + t[(i+1)*M+j+1] + t[(i+1)*M+j] + t[(i+1)*M+M-1] + t[i*M+M-1];
}
else if (j+1 > M-1) {
/* eimai o top_right */
neighbours = t[(N-1)*M+j-1] + t[(N-1)*M+j] + t[(N-1)*M+0] + t[i*M+0] + t[(i+1)*M+0] + t[(i+1)*M+j] + t[(i+1)*M+j-1] + t[i*M+j-1];
}
else{
/* eimai aplos top */
neighbours = t[(N-1)*M+j-1] + t[(N-1)*M+j] + t[(N-1)*M+j+1] + t[i*M+j+1] + t[(i+1)*M+j+1] + t[(i+1)*M+j] + t[(i+1)*M+j-1] + t[i*M+j-1];
}
}
else if (j-1 < 0) {
/* eimai aplos left */
neighbours = t[(i-1)*M+M-1] + t[(i-1)*M+j] + t[(i-1)*M+j+1] + t[i*M+j+1] + t[(i+1)*M+j+1] + t[(i+1)*M+j] + t[(i+1)*M+M-1] + t[i*M+M-1];
}
else if (j+1 > M-1) {
/* eimai aplos right */
neighbours = t[(i-1)*M+j-1] + t[(i-1)*M+j] + t[(i-1)*M+0] + t[i*M+0] + t[(i+1)*M+0] + t[(i+1)*M+j] + t[(i+1)*M+j-1] + t[i*M+j-1];
}
else{
/* oi geitones mou den peftoun eksw */
neighbours = t[(i-1)*M+j-1] + t[(i-1)*M+j] + t[(i-1)*M+j+1] + t[i*M+j+1] + t[(i+1)*M+j+1] + t[(i+1)*M+j] + t[(i+1)*M+j-1] + t[i*M+j-1];
}
/* kanones paixnidiou edw */
if (t[x] == ALIVE) {
if (neighbours <= 1 || neighbours >= 4) {
t1[x] = DEAD;
}
else{
t1[x] = ALIVE;
}
}
else if (t[x] == DEAD && neighbours == 3) {
t1[x] = ALIVE;
}
else{
t1[x] = DEAD;
}
}
}
__global__ void initdat(int *t, int *t1, int N, int M, time_t clock){
int x = blockIdx.x * blockDim.x + threadIdx.x;
hiprandState_t state;
hiprand_init(clock,x,0,&state);
if (0 <= x && x < N*M ){
t[x] = (hiprand(&state) % 4) ? DEAD : ALIVE;
t1[x] = DEAD;
}
} | .text
.file "cuda_gameoflife.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $5, %edi
jne .LBB0_1
# %bb.3:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 24(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 32(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 56(%rsp) # 8-byte Spill
movq %r15, 48(%rsp) # 8-byte Spill
testl %r15d, %r15d
jle .LBB0_7
# %bb.4:
cmpl $0, 24(%rsp) # 4-byte Folded Reload
js .LBB0_7
# %bb.5:
testl %r14d, %r14d
js .LBB0_7
# %bb.6:
cmpl $0, 56(%rsp) # 4-byte Folded Reload
js .LBB0_7
# %bb.8:
movl %r14d, %r12d
movq 24(%rsp), %rcx # 8-byte Reload
imull %ecx, %r12d
leal 511(%r12), %eax
leal 1022(%r12), %edx
testl %eax, %eax
cmovnsl %eax, %edx
movl %edx, 40(%rsp) # 4-byte Spill
movl %ecx, %ebp
movl %r14d, %r15d
movq %rbp, %rbx
imulq %r15, %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r13
movq %rbx, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movslq %r12d, %rbx
shlq $2, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_9
# %bb.11:
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_12
# %bb.13:
movl 40(%rsp), %eax # 4-byte Reload
sarl $9, %eax
movabsq $4294967808, %rdx # imm = 0x100000200
movl %eax, %eax
leaq (%rax,%rdx), %rdi
addq $-512, %rdi # imm = 0xFE00
movq %rdi, 40(%rsp) # 8-byte Spill
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq %rbx, 192(%rsp) # 8-byte Spill
jne .LBB0_15
# %bb.14:
movq 8(%rsp), %rbx
movq (%rsp), %r12
xorl %edi, %edi
callq time
movq %rbx, 128(%rsp)
movq %r12, 120(%rsp)
movq 24(%rsp), %rcx # 8-byte Reload
movl %ecx, 20(%rsp)
movl %r14d, 140(%rsp)
movq %rax, 80(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 120(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 140(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z7initdatPiS_iil, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_15:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_45
# %bb.16: # %.preheader
cmpl $0, 48(%rsp) # 4-byte Folded Reload
jle .LBB0_41
# %bb.17: # %.lr.ph
movl $1, %ebx
movl $1, %r12d
movq %r14, 184(%rsp) # 8-byte Spill
jmp .LBB0_18
.p2align 4, 0x90
.LBB0_40: # %_Z9termCheckPiS_iii.exit
# in Loop: Header=BB0_18 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, (%rsp)
leal 1(%r12), %eax
cmpl 48(%rsp), %r12d # 4-byte Folded Reload
movl %eax, %r12d
je .LBB0_41
.LBB0_18: # =>This Loop Header: Depth=1
# Child Loop BB0_31 Depth 2
# Child Loop BB0_33 Depth 3
movq 40(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $4294967808, %rdx # imm = 0x100000200
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_20
# %bb.19: # in Loop: Header=BB0_18 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq 24(%rsp), %rax # 8-byte Reload
movl %eax, 64(%rsp)
movl %r14d, 20(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 120(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z13kernel_updatePiS_ii, %edi
leaq 144(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_20: # in Loop: Header=BB0_18 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_21
# %bb.22: # in Loop: Header=BB0_18 Depth=1
cmpl $0, 56(%rsp) # 4-byte Folded Reload
je .LBB0_40
# %bb.23: # in Loop: Header=BB0_18 Depth=1
movq %rbp, %r14
movq 8(%rsp), %rsi
movq %r13, %rbp
movq %r13, %rdi
movq 192(%rsp), %r13 # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_24
# %bb.25: # in Loop: Header=BB0_18 Depth=1
movq (%rsp), %rsi
movq 32(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_26
# %bb.27: # in Loop: Header=BB0_18 Depth=1
movl %r12d, %eax
cltd
idivl 56(%rsp) # 4-byte Folded Reload
testl %edx, %edx
movq %rbp, %r13
movq %r14, %rbp
movq 184(%rsp), %r14 # 8-byte Reload
jne .LBB0_40
# %bb.28: # in Loop: Header=BB0_18 Depth=1
cmpl $0, 24(%rsp) # 4-byte Folded Reload
jle .LBB0_29
# %bb.30: # %.preheader.i.preheader
# in Loop: Header=BB0_18 Depth=1
xorl %eax, %eax
xorl %esi, %esi
xorl %edx, %edx
xorl %ecx, %ecx
movq 32(%rsp), %r11 # 8-byte Reload
jmp .LBB0_31
.p2align 4, 0x90
.LBB0_34: # %._crit_edge.i
# in Loop: Header=BB0_31 Depth=2
incq %rsi
addl %r14d, %eax
cmpq %rbp, %rsi
je .LBB0_35
.LBB0_31: # %.preheader.i
# Parent Loop BB0_18 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_33 Depth 3
testl %r14d, %r14d
jle .LBB0_34
# %bb.32: # %.lr.ph.i
# in Loop: Header=BB0_31 Depth=2
movl %eax, %r8d
leaq (%r11,%r8,4), %rdi
leaq (,%r8,4), %r8
addq %r13, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_33: # Parent Loop BB0_18 Depth=1
# Parent Loop BB0_31 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rdi,%r9,4), %r10d
cmpl %r10d, (%r8,%r9,4)
cmovnel %ebx, %ecx
addl %r10d, %edx
incq %r9
cmpq %r9, %r15
jne .LBB0_33
jmp .LBB0_34
.LBB0_35: # %._crit_edge39.loopexit.i
# in Loop: Header=BB0_18 Depth=1
testl %edx, %edx
sete %dl
testl %ecx, %ecx
sete %al
testb %dl, %dl
je .LBB0_38
jmp .LBB0_37
.LBB0_29: # in Loop: Header=BB0_18 Depth=1
movb $1, %al
movb $1, %dl
testb %dl, %dl
jne .LBB0_37
.LBB0_38: # in Loop: Header=BB0_18 Depth=1
testb %al, %al
je .LBB0_40
# %bb.39:
leal -1(%r12), %edx
movl $.L.str.6, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
jmp .LBB0_43
.LBB0_1:
movl $.Lstr.1, %edi
jmp .LBB0_2
.LBB0_7:
movl $.Lstr, %edi
.LBB0_2:
callq puts@PLT
movl $1, %eax
jmp .LBB0_44
.LBB0_41: # %.critedge
movl $.L.str.4, %edi
movq 48(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
.LBB0_42:
xorl %eax, %eax
callq printf
.LBB0_43:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r13, %rdi
callq free
movq 32(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
.LBB0_44:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_37:
.cfi_def_cfa_offset 256
movl $.L.str.5, %edi
movl %r12d, %esi
jmp .LBB0_42
.LBB0_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $63, %ecx
jmp .LBB0_10
.LBB0_24:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $66, %ecx
jmp .LBB0_10
.LBB0_26:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $67, %ecx
.LBB0_10:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB0_9:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $53, %ecx
jmp .LBB0_10
.LBB0_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $54, %ecx
jmp .LBB0_10
.LBB0_45:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $58, %ecx
jmp .LBB0_10
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z22__device_stub__initdatPiS_iil # -- Begin function _Z22__device_stub__initdatPiS_iil
.p2align 4, 0x90
.type _Z22__device_stub__initdatPiS_iil,@function
_Z22__device_stub__initdatPiS_iil: # @_Z22__device_stub__initdatPiS_iil
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7initdatPiS_iil, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z22__device_stub__initdatPiS_iil, .Lfunc_end1-_Z22__device_stub__initdatPiS_iil
.cfi_endproc
# -- End function
.globl _Z28__device_stub__kernel_updatePiS_ii # -- Begin function _Z28__device_stub__kernel_updatePiS_ii
.p2align 4, 0x90
.type _Z28__device_stub__kernel_updatePiS_ii,@function
_Z28__device_stub__kernel_updatePiS_ii: # @_Z28__device_stub__kernel_updatePiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kernel_updatePiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z28__device_stub__kernel_updatePiS_ii, .Lfunc_end2-_Z28__device_stub__kernel_updatePiS_ii
.cfi_endproc
# -- End function
.globl _Z9termCheckPiS_iii # -- Begin function _Z9termCheckPiS_iii
.p2align 4, 0x90
.type _Z9termCheckPiS_iii,@function
_Z9termCheckPiS_iii: # @_Z9termCheckPiS_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $r8d killed $r8d def $r8
testl %edx, %edx
jle .LBB3_1
# %bb.2: # %.preheader.lr.ph
movl %edx, %eax
movl %ecx, %edx
xorl %r9d, %r9d
movl $1, %r10d
xorl %r14d, %r14d
xorl %ebx, %ebx
xorl %r11d, %r11d
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_6: # %._crit_edge
# in Loop: Header=BB3_3 Depth=1
incq %r14
addl %ecx, %r9d
cmpq %rax, %r14
je .LBB3_7
.LBB3_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
testl %ecx, %ecx
jle .LBB3_6
# %bb.4: # %.lr.ph
# in Loop: Header=BB3_3 Depth=1
movl %r9d, %r12d
leaq (%rsi,%r12,4), %r15
leaq (%rdi,%r12,4), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_5: # Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r13,4), %ebp
cmpl %ebp, (%r12,%r13,4)
cmovnel %r10d, %r11d
addl %ebp, %ebx
incq %r13
cmpq %r13, %rdx
jne .LBB3_5
jmp .LBB3_6
.LBB3_7: # %._crit_edge39.loopexit
testl %ebx, %ebx
sete %al
testl %r11d, %r11d
sete %cl
testb %al, %al
je .LBB3_10
.LBB3_9:
movl $.L.str.5, %edi
movl %r8d, %esi
xorl %eax, %eax
callq printf
jmp .LBB3_12
.LBB3_1:
movb $1, %cl
movb $1, %al
testb %al, %al
jne .LBB3_9
.LBB3_10:
xorl %eax, %eax
testb %cl, %cl
je .LBB3_13
# %bb.11:
leal -1(%r8), %edx
movl $.L.str.6, %edi
movl %r8d, %esi
xorl %eax, %eax
callq printf
.LBB3_12:
movl $1, %eax
.LBB3_13:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z9termCheckPiS_iii, .Lfunc_end3-_Z9termCheckPiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_updatePiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7initdatPiS_iil, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Cuda error in file '%s' in line %i : %s.\n"
.size .L.str.2, 42
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/patric94/Parallel-Programming/master/CUDA/cuda_gameoflife.hip"
.size .L.str.3, 119
.type _Z7initdatPiS_iil,@object # @_Z7initdatPiS_iil
.section .rodata,"a",@progbits
.globl _Z7initdatPiS_iil
.p2align 3, 0x0
_Z7initdatPiS_iil:
.quad _Z22__device_stub__initdatPiS_iil
.size _Z7initdatPiS_iil, 8
.type _Z13kernel_updatePiS_ii,@object # @_Z13kernel_updatePiS_ii
.globl _Z13kernel_updatePiS_ii
.p2align 3, 0x0
_Z13kernel_updatePiS_ii:
.quad _Z28__device_stub__kernel_updatePiS_ii
.size _Z13kernel_updatePiS_ii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Reached requested generations %d\n"
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "All cells are dead at generation %d\n"
.size .L.str.5, 37
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Generation %d is the same with generation %d\n"
.size .L.str.6, 46
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13kernel_updatePiS_ii"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7initdatPiS_iil"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Please give positive values for rows/cols and Generations"
.size .Lstr, 58
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error! Missing mandatory argument."
.size .Lstr.1, 35
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__initdatPiS_iil
.addrsig_sym _Z28__device_stub__kernel_updatePiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7initdatPiS_iil
.addrsig_sym _Z13kernel_updatePiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013aa6c_00000000-6_cuda_gameoflife.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2275:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2275:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "All cells are dead at generation %d\n"
.align 8
.LC1:
.string "Generation %d is the same with generation %d\n"
.text
.globl _Z9termCheckPiS_iii
.type _Z9termCheckPiS_iii, @function
_Z9termCheckPiS_iii:
.LFB2272:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %r8d, %r13d
testl %edx, %edx
jle .L4
movq %rdi, %r9
movq %rsi, %r10
movl %edx, %r12d
movl %ecx, %ebp
movl $0, %ebx
movl $0, %r8d
movl $0, %ecx
movl $0, %esi
movslq %ebp, %r14
movl $1, %r11d
jmp .L5
.L9:
movslq %ebx, %rdi
leaq 0(,%rdi,4), %rax
addq %r14, %rdi
salq $2, %rdi
.L7:
movl (%r10,%rax), %edx
cmpl %edx, (%r9,%rax)
cmovne %r11d, %esi
addl %edx, %ecx
addq $4, %rax
cmpq %rdi, %rax
jne .L7
.L10:
addl $1, %r8d
addl %ebp, %ebx
cmpl %r8d, %r12d
je .L8
.L5:
testl %ebp, %ebp
jg .L9
jmp .L10
.L8:
testl %ecx, %ecx
je .L4
movl $0, %eax
testl %esi, %esi
je .L17
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
movl %r13d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L3
.L17:
leal -1(%r13), %ecx
movl %r13d, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
jmp .L3
.cfi_endproc
.LFE2272:
.size _Z9termCheckPiS_iii, .-_Z9termCheckPiS_iii
.globl _Z37__device_stub__Z13kernel_updatePiS_iiPiS_ii
.type _Z37__device_stub__Z13kernel_updatePiS_iiPiS_ii, @function
_Z37__device_stub__Z13kernel_updatePiS_iiPiS_ii:
.LFB2297:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kernel_updatePiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2297:
.size _Z37__device_stub__Z13kernel_updatePiS_iiPiS_ii, .-_Z37__device_stub__Z13kernel_updatePiS_iiPiS_ii
.globl _Z13kernel_updatePiS_ii
.type _Z13kernel_updatePiS_ii, @function
_Z13kernel_updatePiS_ii:
.LFB2298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13kernel_updatePiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size _Z13kernel_updatePiS_ii, .-_Z13kernel_updatePiS_ii
.globl _Z31__device_stub__Z7initdatPiS_iilPiS_iil
.type _Z31__device_stub__Z7initdatPiS_iilPiS_iil, @function
_Z31__device_stub__Z7initdatPiS_iilPiS_iil:
.LFB2299:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7initdatPiS_iil(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2299:
.size _Z31__device_stub__Z7initdatPiS_iilPiS_iil, .-_Z31__device_stub__Z7initdatPiS_iilPiS_iil
.globl _Z7initdatPiS_iil
.type _Z7initdatPiS_iil, @function
_Z7initdatPiS_iil:
.LFB2300:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7initdatPiS_iilPiS_iil
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2300:
.size _Z7initdatPiS_iil, .-_Z7initdatPiS_iil
.section .rodata.str1.8
.align 8
.LC2:
.string "Error! Missing mandatory argument.\n"
.align 8
.LC3:
.string "Please give positive values for rows/cols and Generations\n"
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/patric94/Parallel-Programming/master/CUDA/cuda_gameoflife.cu"
.align 8
.LC5:
.string "Cuda error in file '%s' in line %i : %s.\n"
.align 8
.LC6:
.string "Reached requested generations %d\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $5, %edi
je .L35
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, 12(%rsp)
.L34:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl 12(%rsp), %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 20(%rsp)
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, 16(%rsp)
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %r14d
movq 32(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
testl %r12d, %r12d
jle .L37
movl %ebx, %edx
orl %r15d, %edx
orl %eax, %edx
jns .L38
.L37:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 12(%rsp)
jmp .L34
.L38:
movl %ebx, %eax
imull %r15d, %eax
addl $511, %eax
movl $512, %ecx
cltd
idivl %ecx
movl %eax, %r13d
movslq %ebx, %rbx
movslq %r15d, %r15
imulq %r15, %rbx
leaq 0(,%rbx,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r15
movq %r12, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L54
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L55
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %r13d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L41:
call cudaDeviceSynchronize@PLT
movl $1, %ebx
testl %eax, %eax
je .L42
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $58, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $53, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $54, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
movl $0, %edi
call time@PLT
movq %rax, %r8
movl 16(%rsp), %ecx
movl 20(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z31__device_stub__Z7initdatPiS_iilPiS_iil
jmp .L41
.L58:
movl 16(%rsp), %ecx
movl 20(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z37__device_stub__Z13kernel_updatePiS_iiPiS_ii
jmp .L43
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $63, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $66, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $67, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L45:
movq 32(%rsp), %rax
movq 40(%rsp), %rdx
movq %rdx, 32(%rsp)
movq %rax, 40(%rsp)
addl $1, %ebx
cmpl %r14d, %ebx
jg .L57
.L42:
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %r13d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L43:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L59
testl %ebp, %ebp
je .L45
movl $2, %ecx
movq %r12, %rdx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L60
movl $2, %ecx
movq %r12, %rdx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L61
movl %ebx, %eax
cltd
idivl %ebp
movl %edx, 12(%rsp)
testl %edx, %edx
jne .L45
movl %ebx, %r8d
movl 16(%rsp), %ecx
movl 20(%rsp), %edx
movq 24(%rsp), %rsi
movq %r15, %rdi
call _Z9termCheckPiS_iii
testl %eax, %eax
je .L45
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
jmp .L34
.L57:
movl %r14d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movl $0, 12(%rsp)
jmp .L34
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "_Z7initdatPiS_iil"
.LC8:
.string "_Z13kernel_updatePiS_ii"
.LC9:
.string "precalc_xorwow_matrix"
.LC10:
.string "precalc_xorwow_offset_matrix"
.LC11:
.string "mrg32k3aM1"
.LC12:
.string "mrg32k3aM2"
.LC13:
.string "mrg32k3aM1SubSeq"
.LC14:
.string "mrg32k3aM2SubSeq"
.LC15:
.string "mrg32k3aM1Seq"
.LC16:
.string "mrg32k3aM2Seq"
.LC17:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2302:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7initdatPiS_iil(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_updatePiS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2302:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_gameoflife.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $5, %edi
jne .LBB0_1
# %bb.3:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 24(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 32(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 56(%rsp) # 8-byte Spill
movq %r15, 48(%rsp) # 8-byte Spill
testl %r15d, %r15d
jle .LBB0_7
# %bb.4:
cmpl $0, 24(%rsp) # 4-byte Folded Reload
js .LBB0_7
# %bb.5:
testl %r14d, %r14d
js .LBB0_7
# %bb.6:
cmpl $0, 56(%rsp) # 4-byte Folded Reload
js .LBB0_7
# %bb.8:
movl %r14d, %r12d
movq 24(%rsp), %rcx # 8-byte Reload
imull %ecx, %r12d
leal 511(%r12), %eax
leal 1022(%r12), %edx
testl %eax, %eax
cmovnsl %eax, %edx
movl %edx, 40(%rsp) # 4-byte Spill
movl %ecx, %ebp
movl %r14d, %r15d
movq %rbp, %rbx
imulq %r15, %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r13
movq %rbx, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movslq %r12d, %rbx
shlq $2, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_9
# %bb.11:
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_12
# %bb.13:
movl 40(%rsp), %eax # 4-byte Reload
sarl $9, %eax
movabsq $4294967808, %rdx # imm = 0x100000200
movl %eax, %eax
leaq (%rax,%rdx), %rdi
addq $-512, %rdi # imm = 0xFE00
movq %rdi, 40(%rsp) # 8-byte Spill
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq %rbx, 192(%rsp) # 8-byte Spill
jne .LBB0_15
# %bb.14:
movq 8(%rsp), %rbx
movq (%rsp), %r12
xorl %edi, %edi
callq time
movq %rbx, 128(%rsp)
movq %r12, 120(%rsp)
movq 24(%rsp), %rcx # 8-byte Reload
movl %ecx, 20(%rsp)
movl %r14d, 140(%rsp)
movq %rax, 80(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 120(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 140(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z7initdatPiS_iil, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_15:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_45
# %bb.16: # %.preheader
cmpl $0, 48(%rsp) # 4-byte Folded Reload
jle .LBB0_41
# %bb.17: # %.lr.ph
movl $1, %ebx
movl $1, %r12d
movq %r14, 184(%rsp) # 8-byte Spill
jmp .LBB0_18
.p2align 4, 0x90
.LBB0_40: # %_Z9termCheckPiS_iii.exit
# in Loop: Header=BB0_18 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, (%rsp)
leal 1(%r12), %eax
cmpl 48(%rsp), %r12d # 4-byte Folded Reload
movl %eax, %r12d
je .LBB0_41
.LBB0_18: # =>This Loop Header: Depth=1
# Child Loop BB0_31 Depth 2
# Child Loop BB0_33 Depth 3
movq 40(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $4294967808, %rdx # imm = 0x100000200
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_20
# %bb.19: # in Loop: Header=BB0_18 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq 24(%rsp), %rax # 8-byte Reload
movl %eax, 64(%rsp)
movl %r14d, 20(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 120(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z13kernel_updatePiS_ii, %edi
leaq 144(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_20: # in Loop: Header=BB0_18 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_21
# %bb.22: # in Loop: Header=BB0_18 Depth=1
cmpl $0, 56(%rsp) # 4-byte Folded Reload
je .LBB0_40
# %bb.23: # in Loop: Header=BB0_18 Depth=1
movq %rbp, %r14
movq 8(%rsp), %rsi
movq %r13, %rbp
movq %r13, %rdi
movq 192(%rsp), %r13 # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_24
# %bb.25: # in Loop: Header=BB0_18 Depth=1
movq (%rsp), %rsi
movq 32(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_26
# %bb.27: # in Loop: Header=BB0_18 Depth=1
movl %r12d, %eax
cltd
idivl 56(%rsp) # 4-byte Folded Reload
testl %edx, %edx
movq %rbp, %r13
movq %r14, %rbp
movq 184(%rsp), %r14 # 8-byte Reload
jne .LBB0_40
# %bb.28: # in Loop: Header=BB0_18 Depth=1
cmpl $0, 24(%rsp) # 4-byte Folded Reload
jle .LBB0_29
# %bb.30: # %.preheader.i.preheader
# in Loop: Header=BB0_18 Depth=1
xorl %eax, %eax
xorl %esi, %esi
xorl %edx, %edx
xorl %ecx, %ecx
movq 32(%rsp), %r11 # 8-byte Reload
jmp .LBB0_31
.p2align 4, 0x90
.LBB0_34: # %._crit_edge.i
# in Loop: Header=BB0_31 Depth=2
incq %rsi
addl %r14d, %eax
cmpq %rbp, %rsi
je .LBB0_35
.LBB0_31: # %.preheader.i
# Parent Loop BB0_18 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_33 Depth 3
testl %r14d, %r14d
jle .LBB0_34
# %bb.32: # %.lr.ph.i
# in Loop: Header=BB0_31 Depth=2
movl %eax, %r8d
leaq (%r11,%r8,4), %rdi
leaq (,%r8,4), %r8
addq %r13, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_33: # Parent Loop BB0_18 Depth=1
# Parent Loop BB0_31 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rdi,%r9,4), %r10d
cmpl %r10d, (%r8,%r9,4)
cmovnel %ebx, %ecx
addl %r10d, %edx
incq %r9
cmpq %r9, %r15
jne .LBB0_33
jmp .LBB0_34
.LBB0_35: # %._crit_edge39.loopexit.i
# in Loop: Header=BB0_18 Depth=1
testl %edx, %edx
sete %dl
testl %ecx, %ecx
sete %al
testb %dl, %dl
je .LBB0_38
jmp .LBB0_37
.LBB0_29: # in Loop: Header=BB0_18 Depth=1
movb $1, %al
movb $1, %dl
testb %dl, %dl
jne .LBB0_37
.LBB0_38: # in Loop: Header=BB0_18 Depth=1
testb %al, %al
je .LBB0_40
# %bb.39:
leal -1(%r12), %edx
movl $.L.str.6, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
jmp .LBB0_43
.LBB0_1:
movl $.Lstr.1, %edi
jmp .LBB0_2
.LBB0_7:
movl $.Lstr, %edi
.LBB0_2:
callq puts@PLT
movl $1, %eax
jmp .LBB0_44
.LBB0_41: # %.critedge
movl $.L.str.4, %edi
movq 48(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
.LBB0_42:
xorl %eax, %eax
callq printf
.LBB0_43:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r13, %rdi
callq free
movq 32(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
.LBB0_44:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_37:
.cfi_def_cfa_offset 256
movl $.L.str.5, %edi
movl %r12d, %esi
jmp .LBB0_42
.LBB0_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $63, %ecx
jmp .LBB0_10
.LBB0_24:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $66, %ecx
jmp .LBB0_10
.LBB0_26:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $67, %ecx
.LBB0_10:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB0_9:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $53, %ecx
jmp .LBB0_10
.LBB0_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $54, %ecx
jmp .LBB0_10
.LBB0_45:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movl $58, %ecx
jmp .LBB0_10
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z22__device_stub__initdatPiS_iil # -- Begin function _Z22__device_stub__initdatPiS_iil
.p2align 4, 0x90
.type _Z22__device_stub__initdatPiS_iil,@function
_Z22__device_stub__initdatPiS_iil: # @_Z22__device_stub__initdatPiS_iil
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7initdatPiS_iil, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z22__device_stub__initdatPiS_iil, .Lfunc_end1-_Z22__device_stub__initdatPiS_iil
.cfi_endproc
# -- End function
.globl _Z28__device_stub__kernel_updatePiS_ii # -- Begin function _Z28__device_stub__kernel_updatePiS_ii
.p2align 4, 0x90
.type _Z28__device_stub__kernel_updatePiS_ii,@function
_Z28__device_stub__kernel_updatePiS_ii: # @_Z28__device_stub__kernel_updatePiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kernel_updatePiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z28__device_stub__kernel_updatePiS_ii, .Lfunc_end2-_Z28__device_stub__kernel_updatePiS_ii
.cfi_endproc
# -- End function
.globl _Z9termCheckPiS_iii # -- Begin function _Z9termCheckPiS_iii
.p2align 4, 0x90
.type _Z9termCheckPiS_iii,@function
_Z9termCheckPiS_iii: # @_Z9termCheckPiS_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $r8d killed $r8d def $r8
testl %edx, %edx
jle .LBB3_1
# %bb.2: # %.preheader.lr.ph
movl %edx, %eax
movl %ecx, %edx
xorl %r9d, %r9d
movl $1, %r10d
xorl %r14d, %r14d
xorl %ebx, %ebx
xorl %r11d, %r11d
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_6: # %._crit_edge
# in Loop: Header=BB3_3 Depth=1
incq %r14
addl %ecx, %r9d
cmpq %rax, %r14
je .LBB3_7
.LBB3_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
testl %ecx, %ecx
jle .LBB3_6
# %bb.4: # %.lr.ph
# in Loop: Header=BB3_3 Depth=1
movl %r9d, %r12d
leaq (%rsi,%r12,4), %r15
leaq (%rdi,%r12,4), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_5: # Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r13,4), %ebp
cmpl %ebp, (%r12,%r13,4)
cmovnel %r10d, %r11d
addl %ebp, %ebx
incq %r13
cmpq %r13, %rdx
jne .LBB3_5
jmp .LBB3_6
.LBB3_7: # %._crit_edge39.loopexit
testl %ebx, %ebx
sete %al
testl %r11d, %r11d
sete %cl
testb %al, %al
je .LBB3_10
.LBB3_9:
movl $.L.str.5, %edi
movl %r8d, %esi
xorl %eax, %eax
callq printf
jmp .LBB3_12
.LBB3_1:
movb $1, %cl
movb $1, %al
testb %al, %al
jne .LBB3_9
.LBB3_10:
xorl %eax, %eax
testb %cl, %cl
je .LBB3_13
# %bb.11:
leal -1(%r8), %edx
movl $.L.str.6, %edi
movl %r8d, %esi
xorl %eax, %eax
callq printf
.LBB3_12:
movl $1, %eax
.LBB3_13:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z9termCheckPiS_iii, .Lfunc_end3-_Z9termCheckPiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_updatePiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7initdatPiS_iil, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Cuda error in file '%s' in line %i : %s.\n"
.size .L.str.2, 42
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/patric94/Parallel-Programming/master/CUDA/cuda_gameoflife.hip"
.size .L.str.3, 119
.type _Z7initdatPiS_iil,@object # @_Z7initdatPiS_iil
.section .rodata,"a",@progbits
.globl _Z7initdatPiS_iil
.p2align 3, 0x0
_Z7initdatPiS_iil:
.quad _Z22__device_stub__initdatPiS_iil
.size _Z7initdatPiS_iil, 8
.type _Z13kernel_updatePiS_ii,@object # @_Z13kernel_updatePiS_ii
.globl _Z13kernel_updatePiS_ii
.p2align 3, 0x0
_Z13kernel_updatePiS_ii:
.quad _Z28__device_stub__kernel_updatePiS_ii
.size _Z13kernel_updatePiS_ii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Reached requested generations %d\n"
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "All cells are dead at generation %d\n"
.size .L.str.5, 37
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Generation %d is the same with generation %d\n"
.size .L.str.6, 46
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13kernel_updatePiS_ii"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7initdatPiS_iil"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Please give positive values for rows/cols and Generations"
.size .Lstr, 58
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error! Missing mandatory argument."
.size .Lstr.1, 35
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__initdatPiS_iil
.addrsig_sym _Z28__device_stub__kernel_updatePiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7initdatPiS_iil
.addrsig_sym _Z13kernel_updatePiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define N 10000000
__global__ void c_code(void){
} | code for sm_80
Function : _Z6c_codev
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define N 10000000
__global__ void c_code(void){
} | .file "tmpxft_000ff328_00000000-6_c_code.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6c_codevv
.type _Z24__device_stub__Z6c_codevv, @function
_Z24__device_stub__Z6c_codevv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6c_codev(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z24__device_stub__Z6c_codevv, .-_Z24__device_stub__Z6c_codevv
.globl _Z6c_codev
.type _Z6c_codev, @function
_Z6c_codev:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6c_codevv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6c_codev, .-_Z6c_codev
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6c_codev"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6c_codev(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define N 10000000
__global__ void c_code(void){
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 10000000
__global__ void c_code(void){
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 10000000
__global__ void c_code(void){
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6c_codev
.globl _Z6c_codev
.p2align 8
.type _Z6c_codev,@function
_Z6c_codev:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6c_codev
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6c_codev, .Lfunc_end0-_Z6c_codev
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6c_codev
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6c_codev.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 10000000
__global__ void c_code(void){
} | .text
.file "c_code.hip"
.globl _Z21__device_stub__c_codev # -- Begin function _Z21__device_stub__c_codev
.p2align 4, 0x90
.type _Z21__device_stub__c_codev,@function
_Z21__device_stub__c_codev: # @_Z21__device_stub__c_codev
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6c_codev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__c_codev, .Lfunc_end0-_Z21__device_stub__c_codev
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6c_codev, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6c_codev,@object # @_Z6c_codev
.section .rodata,"a",@progbits
.globl _Z6c_codev
.p2align 3, 0x0
_Z6c_codev:
.quad _Z21__device_stub__c_codev
.size _Z6c_codev, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6c_codev"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__c_codev
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6c_codev
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6c_codev
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6c_codev
.globl _Z6c_codev
.p2align 8
.type _Z6c_codev,@function
_Z6c_codev:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6c_codev
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6c_codev, .Lfunc_end0-_Z6c_codev
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6c_codev
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6c_codev.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ff328_00000000-6_c_code.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6c_codevv
.type _Z24__device_stub__Z6c_codevv, @function
_Z24__device_stub__Z6c_codevv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6c_codev(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z24__device_stub__Z6c_codevv, .-_Z24__device_stub__Z6c_codevv
.globl _Z6c_codev
.type _Z6c_codev, @function
_Z6c_codev:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6c_codevv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6c_codev, .-_Z6c_codev
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6c_codev"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6c_codev(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "c_code.hip"
.globl _Z21__device_stub__c_codev # -- Begin function _Z21__device_stub__c_codev
.p2align 4, 0x90
.type _Z21__device_stub__c_codev,@function
_Z21__device_stub__c_codev: # @_Z21__device_stub__c_codev
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6c_codev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__c_codev, .Lfunc_end0-_Z21__device_stub__c_codev
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6c_codev, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6c_codev,@object # @_Z6c_codev
.section .rodata,"a",@progbits
.globl _Z6c_codev
.p2align 3, 0x0
_Z6c_codev:
.quad _Z21__device_stub__c_codev
.size _Z6c_codev, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6c_codev"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__c_codev
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6c_codev
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ static float disp_absolute_residual(float Xd, float Yd, float Zd, float Xm, float Ym, float Zm, float nx, float ny, float nz, float T0, float T1, float T2, float R0, float R1, float R2, float fx, float b) {
float r = -Xd * nx + Xm * nx - Yd * ny + Ym * ny - Zd * nz + Zm * nz +
nx * T0 + ny * T1 + nz * T2 + Xm * ny * R2 - Xm * nz * R1 -
Ym * nx * R2 + Ym * nz * R0 + Zm * nx * R1 - Zm * ny * R0;
// weight to convert distance units to pixels
r *= fx * b / (Zm * Zm);
return fabsf(r);
}
__global__ void normal_eqs_disparity_weighted_GPU( float *d_CD, const float *d_disparity_compact, const float4 *d_Zbuffer_normals_compact, const int *d_ind_disparity_Zbuffer, float fx, float fy, float ox, float oy, float b, int n_cols, const int *d_n_values_disparity, const int *d_start_ind_disparity, const float *d_abs_res_scales, float w_disp, const float *d_dTR) {
int n_val_accum =
gridDim.x * blockDim.x; // n_val_accum may not be multiple of blocksize
int n_disparity = d_n_values_disparity[blockIdx.y];
int n_accum = (int)ceilf((float)n_disparity / (float)n_val_accum);
int start_ind = d_start_ind_disparity[blockIdx.y];
// initialize accumulators
float A0 = 0.0f, A1 = 0.0f, A2 = 0.0f, A3 = 0.0f, A4 = 0.0f, A5 = 0.0f,
A6 = 0.0f, A7 = 0.0f, A8 = 0.0f, A9 = 0.0f, A10 = 0.0f, A11 = 0.0f,
A12 = 0.0f, A13 = 0.0f, A14 = 0.0f, A15 = 0.0f, A16 = 0.0f, A17 = 0.0f,
A18 = 0.0f, A19 = 0.0f, A20 = 0.0f, A21 = 0.0f, A22 = 0.0f, A23 = 0.0f,
A24 = 0.0f, A25 = 0.0f, A26 = 0.0f;
for (int in_ind = blockDim.x * blockIdx.x * n_accum + threadIdx.x;
in_ind < blockDim.x * (blockIdx.x + 1) * n_accum; in_ind += blockDim.x) {
if (in_ind < n_disparity) { // is this a valid sample?
// fetch disparity, Zbuffer and normal from global memory
float disp = d_disparity_compact[in_ind + start_ind];
float4 tmp = d_Zbuffer_normals_compact[in_ind + start_ind];
float Zbuffer = tmp.x;
float nx = tmp.y;
float ny = tmp.z;
float nz = tmp.w;
// compute coordinates
int pixel_ind = d_ind_disparity_Zbuffer[in_ind + start_ind];
float y = floorf(__fdividef((float)pixel_ind, n_cols));
float x = (float)pixel_ind - y * n_cols;
x = __fdividef((x - ox), fx);
y = __fdividef((y - oy), fy);
// reconstruct 3D point from disparity
float Zd = -(fx * b) / disp; // arbitrary use of fx
float Xd = x * Zd;
float Yd = y * Zd;
// reconstruct 3D point from model
float Zm = Zbuffer;
float Xm = x * Zm;
float Ym = y * Zm;
// determine M-estimation weight
// disparity residual weighed by rel. importance disp vs flow
int s6 = blockIdx.y * 6;
float w = w_disp * disp_absolute_residual(
Xd, Yd, Zd, Xm, Ym, Zm, nx, ny, nz, d_dTR[s6],
d_dTR[s6 + 1], d_dTR[s6 + 2], d_dTR[s6 + 3],
d_dTR[s6 + 4], d_dTR[s6 + 5], fx, b);
w /= d_abs_res_scales[blockIdx.y];
w = (w > 1) ? 0 : (1.0f - 2.0f * w * w + w * w * w * w);
// multiply m estimation weight with distance->pixel conversion weight
// (squared)
w *= (fx * fx * b * b) / (Zm * Zm * Zm * Zm);
/************************/
/* evaluate constraints */
/************************/
// unique values A-matrix
A0 += w * (nx * nx);
A1 += w * (nx * ny);
A2 += w * (nx * nz);
A3 += w * (Ym * nx * nz - Zm * nx * ny);
A4 += w * (Zm * (nx * nx) - Xm * nx * nz);
A5 += w * (-Ym * (nx * nx) + Xm * nx * ny);
A6 += w * (ny * ny);
A7 += w * (ny * nz);
A8 += w * (-Zm * (ny * ny) + Ym * ny * nz);
A9 += w * (-Xm * ny * nz + Zm * nx * ny);
A10 += w * (Xm * (ny * ny) - Ym * nx * ny);
A11 += w * (nz * nz);
A12 += w * (Ym * (nz * nz) - Zm * ny * nz);
A13 += w * (-Xm * (nz * nz) + Zm * nx * nz);
A14 += w * (Xm * ny * nz - Ym * nx * nz);
A15 += w * ((Ym * Ym) * (nz * nz) + (Zm * Zm) * (ny * ny) -
Ym * Zm * ny * nz * 2.0f);
A16 += w * (-Xm * Ym * (nz * nz) - (Zm * Zm) * nx * ny +
Xm * Zm * ny * nz + Ym * Zm * nx * nz);
A17 += w * (-Xm * Zm * (ny * ny) - (Ym * Ym) * nx * nz +
Xm * Ym * ny * nz + Ym * Zm * nx * ny);
A18 += w * ((Xm * Xm) * (nz * nz) + (Zm * Zm) * (nx * nx) -
Xm * Zm * nx * nz * 2.0f);
A19 += w * (-Ym * Zm * (nx * nx) - (Xm * Xm) * ny * nz +
Xm * Ym * nx * nz + Xm * Zm * nx * ny);
A20 += w * ((Xm * Xm) * (ny * ny) + (Ym * Ym) * (nx * nx) -
Xm * Ym * nx * ny * 2.0f);
// B-vector
A21 += w * (Xd * (nx * nx) - Xm * (nx * nx) + Yd * nx * ny -
Ym * nx * ny + Zd * nx * nz - Zm * nx * nz);
A22 += w * (Yd * (ny * ny) - Ym * (ny * ny) + Xd * nx * ny -
Xm * nx * ny + Zd * ny * nz - Zm * ny * nz);
A23 += w * (Zd * (nz * nz) - Zm * (nz * nz) + Xd * nx * nz -
Xm * nx * nz + Yd * ny * nz - Ym * ny * nz);
A24 += w *
(-Yd * Zm * (ny * ny) + Ym * Zd * (nz * nz) + Ym * Zm * (ny * ny) -
Ym * Zm * (nz * nz) - (Ym * Ym) * ny * nz + (Zm * Zm) * ny * nz +
Xd * Ym * nx * nz - Xm * Ym * nx * nz - Xd * Zm * nx * ny +
Yd * Ym * ny * nz + Xm * Zm * nx * ny - Zd * Zm * ny * nz);
A25 +=
w * (Xd * Zm * (nx * nx) - Xm * Zd * (nz * nz) - Xm * Zm * (nx * nx) +
Xm * Zm * (nz * nz) + (Xm * Xm) * nx * nz - (Zm * Zm) * nx * nz -
Xd * Xm * nx * nz - Xm * Yd * ny * nz + Xm * Ym * ny * nz +
Yd * Zm * nx * ny - Ym * Zm * nx * ny + Zd * Zm * nx * nz);
A26 += w *
(-Xd * Ym * (nx * nx) + Xm * Yd * (ny * ny) + Xm * Ym * (nx * nx) -
Xm * Ym * (ny * ny) - (Xm * Xm) * nx * ny + (Ym * Ym) * nx * ny +
Xd * Xm * nx * ny - Yd * Ym * nx * ny + Xm * Zd * ny * nz -
Xm * Zm * ny * nz - Ym * Zd * nx * nz + Ym * Zm * nx * nz);
}
}
/**************************/
/* write out accumulators */
/**************************/
int out_ind =
27 * n_val_accum * blockIdx.y + blockDim.x * blockIdx.x + threadIdx.x;
w_disp *= w_disp; // weight relative to flow
d_CD[out_ind] = w_disp * A0;
d_CD[out_ind + n_val_accum] = w_disp * A1;
d_CD[out_ind + 2 * n_val_accum] = w_disp * A2;
d_CD[out_ind + 3 * n_val_accum] = w_disp * A3;
d_CD[out_ind + 4 * n_val_accum] = w_disp * A4;
d_CD[out_ind + 5 * n_val_accum] = w_disp * A5;
d_CD[out_ind + 6 * n_val_accum] = w_disp * A6;
d_CD[out_ind + 7 * n_val_accum] = w_disp * A7;
d_CD[out_ind + 8 * n_val_accum] = w_disp * A8;
d_CD[out_ind + 9 * n_val_accum] = w_disp * A9;
d_CD[out_ind + 10 * n_val_accum] = w_disp * A10;
d_CD[out_ind + 11 * n_val_accum] = w_disp * A11;
d_CD[out_ind + 12 * n_val_accum] = w_disp * A12;
d_CD[out_ind + 13 * n_val_accum] = w_disp * A13;
d_CD[out_ind + 14 * n_val_accum] = w_disp * A14;
d_CD[out_ind + 15 * n_val_accum] = w_disp * A15;
d_CD[out_ind + 16 * n_val_accum] = w_disp * A16;
d_CD[out_ind + 17 * n_val_accum] = w_disp * A17;
d_CD[out_ind + 18 * n_val_accum] = w_disp * A18;
d_CD[out_ind + 19 * n_val_accum] = w_disp * A19;
d_CD[out_ind + 20 * n_val_accum] = w_disp * A20;
d_CD[out_ind + 21 * n_val_accum] = w_disp * A21;
d_CD[out_ind + 22 * n_val_accum] = w_disp * A22;
d_CD[out_ind + 23 * n_val_accum] = w_disp * A23;
d_CD[out_ind + 24 * n_val_accum] = w_disp * A24;
d_CD[out_ind + 25 * n_val_accum] = w_disp * A25;
d_CD[out_ind + 26 * n_val_accum] = w_disp * A26;
} | .file "tmpxft_001416fa_00000000-6_normal_eqs_disparity_weighted_GPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z87__device_stub__Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_PfPKfPK6float4PKifffffiS6_S6_S1_fS1_
.type _Z87__device_stub__Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_PfPKfPK6float4PKifffffiS6_S6_S1_fS1_, @function
_Z87__device_stub__Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_PfPKfPK6float4PKifffffiS6_S6_S1_fS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 60(%rsp)
movss %xmm1, 56(%rsp)
movss %xmm2, 52(%rsp)
movss %xmm3, 48(%rsp)
movss %xmm4, 44(%rsp)
movl %r8d, 40(%rsp)
movq %r9, 32(%rsp)
movss %xmm5, 12(%rsp)
movq 304(%rsp), %rax
movq %rax, 24(%rsp)
movq 312(%rsp), %rax
movq %rax, 16(%rsp)
movq 320(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 60(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rax
movq %rax, 200(%rsp)
leaq 52(%rsp), %rax
movq %rax, 208(%rsp)
leaq 48(%rsp), %rax
movq %rax, 216(%rsp)
leaq 44(%rsp), %rax
movq %rax, 224(%rsp)
leaq 40(%rsp), %rax
movq %rax, 232(%rsp)
leaq 32(%rsp), %rax
movq %rax, 240(%rsp)
leaq 24(%rsp), %rax
movq %rax, 248(%rsp)
leaq 16(%rsp), %rax
movq %rax, 256(%rsp)
leaq 12(%rsp), %rax
movq %rax, 264(%rsp)
movq %rsp, %rax
movq %rax, 272(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 312
pushq 104(%rsp)
.cfi_def_cfa_offset 320
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z87__device_stub__Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_PfPKfPK6float4PKifffffiS6_S6_S1_fS1_, .-_Z87__device_stub__Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_PfPKfPK6float4PKifffffiS6_S6_S1_fS1_
.globl _Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_
.type _Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_, @function
_Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z87__device_stub__Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_PfPKfPK6float4PKifffffiS6_S6_S1_fS1_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_, .-_Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ static float disp_absolute_residual(float Xd, float Yd, float Zd, float Xm, float Ym, float Zm, float nx, float ny, float nz, float T0, float T1, float T2, float R0, float R1, float R2, float fx, float b) {
float r = -Xd * nx + Xm * nx - Yd * ny + Ym * ny - Zd * nz + Zm * nz +
nx * T0 + ny * T1 + nz * T2 + Xm * ny * R2 - Xm * nz * R1 -
Ym * nx * R2 + Ym * nz * R0 + Zm * nx * R1 - Zm * ny * R0;
// weight to convert distance units to pixels
r *= fx * b / (Zm * Zm);
return fabsf(r);
}
__global__ void normal_eqs_disparity_weighted_GPU( float *d_CD, const float *d_disparity_compact, const float4 *d_Zbuffer_normals_compact, const int *d_ind_disparity_Zbuffer, float fx, float fy, float ox, float oy, float b, int n_cols, const int *d_n_values_disparity, const int *d_start_ind_disparity, const float *d_abs_res_scales, float w_disp, const float *d_dTR) {
int n_val_accum =
gridDim.x * blockDim.x; // n_val_accum may not be multiple of blocksize
int n_disparity = d_n_values_disparity[blockIdx.y];
int n_accum = (int)ceilf((float)n_disparity / (float)n_val_accum);
int start_ind = d_start_ind_disparity[blockIdx.y];
// initialize accumulators
float A0 = 0.0f, A1 = 0.0f, A2 = 0.0f, A3 = 0.0f, A4 = 0.0f, A5 = 0.0f,
A6 = 0.0f, A7 = 0.0f, A8 = 0.0f, A9 = 0.0f, A10 = 0.0f, A11 = 0.0f,
A12 = 0.0f, A13 = 0.0f, A14 = 0.0f, A15 = 0.0f, A16 = 0.0f, A17 = 0.0f,
A18 = 0.0f, A19 = 0.0f, A20 = 0.0f, A21 = 0.0f, A22 = 0.0f, A23 = 0.0f,
A24 = 0.0f, A25 = 0.0f, A26 = 0.0f;
for (int in_ind = blockDim.x * blockIdx.x * n_accum + threadIdx.x;
in_ind < blockDim.x * (blockIdx.x + 1) * n_accum; in_ind += blockDim.x) {
if (in_ind < n_disparity) { // is this a valid sample?
// fetch disparity, Zbuffer and normal from global memory
float disp = d_disparity_compact[in_ind + start_ind];
float4 tmp = d_Zbuffer_normals_compact[in_ind + start_ind];
float Zbuffer = tmp.x;
float nx = tmp.y;
float ny = tmp.z;
float nz = tmp.w;
// compute coordinates
int pixel_ind = d_ind_disparity_Zbuffer[in_ind + start_ind];
float y = floorf(__fdividef((float)pixel_ind, n_cols));
float x = (float)pixel_ind - y * n_cols;
x = __fdividef((x - ox), fx);
y = __fdividef((y - oy), fy);
// reconstruct 3D point from disparity
float Zd = -(fx * b) / disp; // arbitrary use of fx
float Xd = x * Zd;
float Yd = y * Zd;
// reconstruct 3D point from model
float Zm = Zbuffer;
float Xm = x * Zm;
float Ym = y * Zm;
// determine M-estimation weight
// disparity residual weighed by rel. importance disp vs flow
int s6 = blockIdx.y * 6;
float w = w_disp * disp_absolute_residual(
Xd, Yd, Zd, Xm, Ym, Zm, nx, ny, nz, d_dTR[s6],
d_dTR[s6 + 1], d_dTR[s6 + 2], d_dTR[s6 + 3],
d_dTR[s6 + 4], d_dTR[s6 + 5], fx, b);
w /= d_abs_res_scales[blockIdx.y];
w = (w > 1) ? 0 : (1.0f - 2.0f * w * w + w * w * w * w);
// multiply m estimation weight with distance->pixel conversion weight
// (squared)
w *= (fx * fx * b * b) / (Zm * Zm * Zm * Zm);
/************************/
/* evaluate constraints */
/************************/
// unique values A-matrix
A0 += w * (nx * nx);
A1 += w * (nx * ny);
A2 += w * (nx * nz);
A3 += w * (Ym * nx * nz - Zm * nx * ny);
A4 += w * (Zm * (nx * nx) - Xm * nx * nz);
A5 += w * (-Ym * (nx * nx) + Xm * nx * ny);
A6 += w * (ny * ny);
A7 += w * (ny * nz);
A8 += w * (-Zm * (ny * ny) + Ym * ny * nz);
A9 += w * (-Xm * ny * nz + Zm * nx * ny);
A10 += w * (Xm * (ny * ny) - Ym * nx * ny);
A11 += w * (nz * nz);
A12 += w * (Ym * (nz * nz) - Zm * ny * nz);
A13 += w * (-Xm * (nz * nz) + Zm * nx * nz);
A14 += w * (Xm * ny * nz - Ym * nx * nz);
A15 += w * ((Ym * Ym) * (nz * nz) + (Zm * Zm) * (ny * ny) -
Ym * Zm * ny * nz * 2.0f);
A16 += w * (-Xm * Ym * (nz * nz) - (Zm * Zm) * nx * ny +
Xm * Zm * ny * nz + Ym * Zm * nx * nz);
A17 += w * (-Xm * Zm * (ny * ny) - (Ym * Ym) * nx * nz +
Xm * Ym * ny * nz + Ym * Zm * nx * ny);
A18 += w * ((Xm * Xm) * (nz * nz) + (Zm * Zm) * (nx * nx) -
Xm * Zm * nx * nz * 2.0f);
A19 += w * (-Ym * Zm * (nx * nx) - (Xm * Xm) * ny * nz +
Xm * Ym * nx * nz + Xm * Zm * nx * ny);
A20 += w * ((Xm * Xm) * (ny * ny) + (Ym * Ym) * (nx * nx) -
Xm * Ym * nx * ny * 2.0f);
// B-vector
A21 += w * (Xd * (nx * nx) - Xm * (nx * nx) + Yd * nx * ny -
Ym * nx * ny + Zd * nx * nz - Zm * nx * nz);
A22 += w * (Yd * (ny * ny) - Ym * (ny * ny) + Xd * nx * ny -
Xm * nx * ny + Zd * ny * nz - Zm * ny * nz);
A23 += w * (Zd * (nz * nz) - Zm * (nz * nz) + Xd * nx * nz -
Xm * nx * nz + Yd * ny * nz - Ym * ny * nz);
A24 += w *
(-Yd * Zm * (ny * ny) + Ym * Zd * (nz * nz) + Ym * Zm * (ny * ny) -
Ym * Zm * (nz * nz) - (Ym * Ym) * ny * nz + (Zm * Zm) * ny * nz +
Xd * Ym * nx * nz - Xm * Ym * nx * nz - Xd * Zm * nx * ny +
Yd * Ym * ny * nz + Xm * Zm * nx * ny - Zd * Zm * ny * nz);
A25 +=
w * (Xd * Zm * (nx * nx) - Xm * Zd * (nz * nz) - Xm * Zm * (nx * nx) +
Xm * Zm * (nz * nz) + (Xm * Xm) * nx * nz - (Zm * Zm) * nx * nz -
Xd * Xm * nx * nz - Xm * Yd * ny * nz + Xm * Ym * ny * nz +
Yd * Zm * nx * ny - Ym * Zm * nx * ny + Zd * Zm * nx * nz);
A26 += w *
(-Xd * Ym * (nx * nx) + Xm * Yd * (ny * ny) + Xm * Ym * (nx * nx) -
Xm * Ym * (ny * ny) - (Xm * Xm) * nx * ny + (Ym * Ym) * nx * ny +
Xd * Xm * nx * ny - Yd * Ym * nx * ny + Xm * Zd * ny * nz -
Xm * Zm * ny * nz - Ym * Zd * nx * nz + Ym * Zm * nx * nz);
}
}
/**************************/
/* write out accumulators */
/**************************/
int out_ind =
27 * n_val_accum * blockIdx.y + blockDim.x * blockIdx.x + threadIdx.x;
w_disp *= w_disp; // weight relative to flow
d_CD[out_ind] = w_disp * A0;
d_CD[out_ind + n_val_accum] = w_disp * A1;
d_CD[out_ind + 2 * n_val_accum] = w_disp * A2;
d_CD[out_ind + 3 * n_val_accum] = w_disp * A3;
d_CD[out_ind + 4 * n_val_accum] = w_disp * A4;
d_CD[out_ind + 5 * n_val_accum] = w_disp * A5;
d_CD[out_ind + 6 * n_val_accum] = w_disp * A6;
d_CD[out_ind + 7 * n_val_accum] = w_disp * A7;
d_CD[out_ind + 8 * n_val_accum] = w_disp * A8;
d_CD[out_ind + 9 * n_val_accum] = w_disp * A9;
d_CD[out_ind + 10 * n_val_accum] = w_disp * A10;
d_CD[out_ind + 11 * n_val_accum] = w_disp * A11;
d_CD[out_ind + 12 * n_val_accum] = w_disp * A12;
d_CD[out_ind + 13 * n_val_accum] = w_disp * A13;
d_CD[out_ind + 14 * n_val_accum] = w_disp * A14;
d_CD[out_ind + 15 * n_val_accum] = w_disp * A15;
d_CD[out_ind + 16 * n_val_accum] = w_disp * A16;
d_CD[out_ind + 17 * n_val_accum] = w_disp * A17;
d_CD[out_ind + 18 * n_val_accum] = w_disp * A18;
d_CD[out_ind + 19 * n_val_accum] = w_disp * A19;
d_CD[out_ind + 20 * n_val_accum] = w_disp * A20;
d_CD[out_ind + 21 * n_val_accum] = w_disp * A21;
d_CD[out_ind + 22 * n_val_accum] = w_disp * A22;
d_CD[out_ind + 23 * n_val_accum] = w_disp * A23;
d_CD[out_ind + 24 * n_val_accum] = w_disp * A24;
d_CD[out_ind + 25 * n_val_accum] = w_disp * A25;
d_CD[out_ind + 26 * n_val_accum] = w_disp * A26;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ static float disp_absolute_residual(float Xd, float Yd, float Zd, float Xm, float Ym, float Zm, float nx, float ny, float nz, float T0, float T1, float T2, float R0, float R1, float R2, float fx, float b) {
float r = -Xd * nx + Xm * nx - Yd * ny + Ym * ny - Zd * nz + Zm * nz +
nx * T0 + ny * T1 + nz * T2 + Xm * ny * R2 - Xm * nz * R1 -
Ym * nx * R2 + Ym * nz * R0 + Zm * nx * R1 - Zm * ny * R0;
// weight to convert distance units to pixels
r *= fx * b / (Zm * Zm);
return fabsf(r);
}
__global__ void normal_eqs_disparity_weighted_GPU( float *d_CD, const float *d_disparity_compact, const float4 *d_Zbuffer_normals_compact, const int *d_ind_disparity_Zbuffer, float fx, float fy, float ox, float oy, float b, int n_cols, const int *d_n_values_disparity, const int *d_start_ind_disparity, const float *d_abs_res_scales, float w_disp, const float *d_dTR) {
int n_val_accum =
gridDim.x * blockDim.x; // n_val_accum may not be multiple of blocksize
int n_disparity = d_n_values_disparity[blockIdx.y];
int n_accum = (int)ceilf((float)n_disparity / (float)n_val_accum);
int start_ind = d_start_ind_disparity[blockIdx.y];
// initialize accumulators
float A0 = 0.0f, A1 = 0.0f, A2 = 0.0f, A3 = 0.0f, A4 = 0.0f, A5 = 0.0f,
A6 = 0.0f, A7 = 0.0f, A8 = 0.0f, A9 = 0.0f, A10 = 0.0f, A11 = 0.0f,
A12 = 0.0f, A13 = 0.0f, A14 = 0.0f, A15 = 0.0f, A16 = 0.0f, A17 = 0.0f,
A18 = 0.0f, A19 = 0.0f, A20 = 0.0f, A21 = 0.0f, A22 = 0.0f, A23 = 0.0f,
A24 = 0.0f, A25 = 0.0f, A26 = 0.0f;
for (int in_ind = blockDim.x * blockIdx.x * n_accum + threadIdx.x;
in_ind < blockDim.x * (blockIdx.x + 1) * n_accum; in_ind += blockDim.x) {
if (in_ind < n_disparity) { // is this a valid sample?
// fetch disparity, Zbuffer and normal from global memory
float disp = d_disparity_compact[in_ind + start_ind];
float4 tmp = d_Zbuffer_normals_compact[in_ind + start_ind];
float Zbuffer = tmp.x;
float nx = tmp.y;
float ny = tmp.z;
float nz = tmp.w;
// compute coordinates
int pixel_ind = d_ind_disparity_Zbuffer[in_ind + start_ind];
float y = floorf(__fdividef((float)pixel_ind, n_cols));
float x = (float)pixel_ind - y * n_cols;
x = __fdividef((x - ox), fx);
y = __fdividef((y - oy), fy);
// reconstruct 3D point from disparity
float Zd = -(fx * b) / disp; // arbitrary use of fx
float Xd = x * Zd;
float Yd = y * Zd;
// reconstruct 3D point from model
float Zm = Zbuffer;
float Xm = x * Zm;
float Ym = y * Zm;
// determine M-estimation weight
// disparity residual weighed by rel. importance disp vs flow
int s6 = blockIdx.y * 6;
float w = w_disp * disp_absolute_residual(
Xd, Yd, Zd, Xm, Ym, Zm, nx, ny, nz, d_dTR[s6],
d_dTR[s6 + 1], d_dTR[s6 + 2], d_dTR[s6 + 3],
d_dTR[s6 + 4], d_dTR[s6 + 5], fx, b);
w /= d_abs_res_scales[blockIdx.y];
w = (w > 1) ? 0 : (1.0f - 2.0f * w * w + w * w * w * w);
// multiply m estimation weight with distance->pixel conversion weight
// (squared)
w *= (fx * fx * b * b) / (Zm * Zm * Zm * Zm);
/************************/
/* evaluate constraints */
/************************/
// unique values A-matrix
A0 += w * (nx * nx);
A1 += w * (nx * ny);
A2 += w * (nx * nz);
A3 += w * (Ym * nx * nz - Zm * nx * ny);
A4 += w * (Zm * (nx * nx) - Xm * nx * nz);
A5 += w * (-Ym * (nx * nx) + Xm * nx * ny);
A6 += w * (ny * ny);
A7 += w * (ny * nz);
A8 += w * (-Zm * (ny * ny) + Ym * ny * nz);
A9 += w * (-Xm * ny * nz + Zm * nx * ny);
A10 += w * (Xm * (ny * ny) - Ym * nx * ny);
A11 += w * (nz * nz);
A12 += w * (Ym * (nz * nz) - Zm * ny * nz);
A13 += w * (-Xm * (nz * nz) + Zm * nx * nz);
A14 += w * (Xm * ny * nz - Ym * nx * nz);
A15 += w * ((Ym * Ym) * (nz * nz) + (Zm * Zm) * (ny * ny) -
Ym * Zm * ny * nz * 2.0f);
A16 += w * (-Xm * Ym * (nz * nz) - (Zm * Zm) * nx * ny +
Xm * Zm * ny * nz + Ym * Zm * nx * nz);
A17 += w * (-Xm * Zm * (ny * ny) - (Ym * Ym) * nx * nz +
Xm * Ym * ny * nz + Ym * Zm * nx * ny);
A18 += w * ((Xm * Xm) * (nz * nz) + (Zm * Zm) * (nx * nx) -
Xm * Zm * nx * nz * 2.0f);
A19 += w * (-Ym * Zm * (nx * nx) - (Xm * Xm) * ny * nz +
Xm * Ym * nx * nz + Xm * Zm * nx * ny);
A20 += w * ((Xm * Xm) * (ny * ny) + (Ym * Ym) * (nx * nx) -
Xm * Ym * nx * ny * 2.0f);
// B-vector
A21 += w * (Xd * (nx * nx) - Xm * (nx * nx) + Yd * nx * ny -
Ym * nx * ny + Zd * nx * nz - Zm * nx * nz);
A22 += w * (Yd * (ny * ny) - Ym * (ny * ny) + Xd * nx * ny -
Xm * nx * ny + Zd * ny * nz - Zm * ny * nz);
A23 += w * (Zd * (nz * nz) - Zm * (nz * nz) + Xd * nx * nz -
Xm * nx * nz + Yd * ny * nz - Ym * ny * nz);
A24 += w *
(-Yd * Zm * (ny * ny) + Ym * Zd * (nz * nz) + Ym * Zm * (ny * ny) -
Ym * Zm * (nz * nz) - (Ym * Ym) * ny * nz + (Zm * Zm) * ny * nz +
Xd * Ym * nx * nz - Xm * Ym * nx * nz - Xd * Zm * nx * ny +
Yd * Ym * ny * nz + Xm * Zm * nx * ny - Zd * Zm * ny * nz);
A25 +=
w * (Xd * Zm * (nx * nx) - Xm * Zd * (nz * nz) - Xm * Zm * (nx * nx) +
Xm * Zm * (nz * nz) + (Xm * Xm) * nx * nz - (Zm * Zm) * nx * nz -
Xd * Xm * nx * nz - Xm * Yd * ny * nz + Xm * Ym * ny * nz +
Yd * Zm * nx * ny - Ym * Zm * nx * ny + Zd * Zm * nx * nz);
A26 += w *
(-Xd * Ym * (nx * nx) + Xm * Yd * (ny * ny) + Xm * Ym * (nx * nx) -
Xm * Ym * (ny * ny) - (Xm * Xm) * nx * ny + (Ym * Ym) * nx * ny +
Xd * Xm * nx * ny - Yd * Ym * nx * ny + Xm * Zd * ny * nz -
Xm * Zm * ny * nz - Ym * Zd * nx * nz + Ym * Zm * nx * nz);
}
}
/**************************/
/* write out accumulators */
/**************************/
int out_ind =
27 * n_val_accum * blockIdx.y + blockDim.x * blockIdx.x + threadIdx.x;
w_disp *= w_disp; // weight relative to flow
d_CD[out_ind] = w_disp * A0;
d_CD[out_ind + n_val_accum] = w_disp * A1;
d_CD[out_ind + 2 * n_val_accum] = w_disp * A2;
d_CD[out_ind + 3 * n_val_accum] = w_disp * A3;
d_CD[out_ind + 4 * n_val_accum] = w_disp * A4;
d_CD[out_ind + 5 * n_val_accum] = w_disp * A5;
d_CD[out_ind + 6 * n_val_accum] = w_disp * A6;
d_CD[out_ind + 7 * n_val_accum] = w_disp * A7;
d_CD[out_ind + 8 * n_val_accum] = w_disp * A8;
d_CD[out_ind + 9 * n_val_accum] = w_disp * A9;
d_CD[out_ind + 10 * n_val_accum] = w_disp * A10;
d_CD[out_ind + 11 * n_val_accum] = w_disp * A11;
d_CD[out_ind + 12 * n_val_accum] = w_disp * A12;
d_CD[out_ind + 13 * n_val_accum] = w_disp * A13;
d_CD[out_ind + 14 * n_val_accum] = w_disp * A14;
d_CD[out_ind + 15 * n_val_accum] = w_disp * A15;
d_CD[out_ind + 16 * n_val_accum] = w_disp * A16;
d_CD[out_ind + 17 * n_val_accum] = w_disp * A17;
d_CD[out_ind + 18 * n_val_accum] = w_disp * A18;
d_CD[out_ind + 19 * n_val_accum] = w_disp * A19;
d_CD[out_ind + 20 * n_val_accum] = w_disp * A20;
d_CD[out_ind + 21 * n_val_accum] = w_disp * A21;
d_CD[out_ind + 22 * n_val_accum] = w_disp * A22;
d_CD[out_ind + 23 * n_val_accum] = w_disp * A23;
d_CD[out_ind + 24 * n_val_accum] = w_disp * A24;
d_CD[out_ind + 25 * n_val_accum] = w_disp * A25;
d_CD[out_ind + 26 * n_val_accum] = w_disp * A26;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ static float disp_absolute_residual(float Xd, float Yd, float Zd, float Xm, float Ym, float Zm, float nx, float ny, float nz, float T0, float T1, float T2, float R0, float R1, float R2, float fx, float b) {
float r = -Xd * nx + Xm * nx - Yd * ny + Ym * ny - Zd * nz + Zm * nz +
nx * T0 + ny * T1 + nz * T2 + Xm * ny * R2 - Xm * nz * R1 -
Ym * nx * R2 + Ym * nz * R0 + Zm * nx * R1 - Zm * ny * R0;
// weight to convert distance units to pixels
r *= fx * b / (Zm * Zm);
return fabsf(r);
}
__global__ void normal_eqs_disparity_weighted_GPU( float *d_CD, const float *d_disparity_compact, const float4 *d_Zbuffer_normals_compact, const int *d_ind_disparity_Zbuffer, float fx, float fy, float ox, float oy, float b, int n_cols, const int *d_n_values_disparity, const int *d_start_ind_disparity, const float *d_abs_res_scales, float w_disp, const float *d_dTR) {
int n_val_accum =
gridDim.x * blockDim.x; // n_val_accum may not be multiple of blocksize
int n_disparity = d_n_values_disparity[blockIdx.y];
int n_accum = (int)ceilf((float)n_disparity / (float)n_val_accum);
int start_ind = d_start_ind_disparity[blockIdx.y];
// initialize accumulators
float A0 = 0.0f, A1 = 0.0f, A2 = 0.0f, A3 = 0.0f, A4 = 0.0f, A5 = 0.0f,
A6 = 0.0f, A7 = 0.0f, A8 = 0.0f, A9 = 0.0f, A10 = 0.0f, A11 = 0.0f,
A12 = 0.0f, A13 = 0.0f, A14 = 0.0f, A15 = 0.0f, A16 = 0.0f, A17 = 0.0f,
A18 = 0.0f, A19 = 0.0f, A20 = 0.0f, A21 = 0.0f, A22 = 0.0f, A23 = 0.0f,
A24 = 0.0f, A25 = 0.0f, A26 = 0.0f;
for (int in_ind = blockDim.x * blockIdx.x * n_accum + threadIdx.x;
in_ind < blockDim.x * (blockIdx.x + 1) * n_accum; in_ind += blockDim.x) {
if (in_ind < n_disparity) { // is this a valid sample?
// fetch disparity, Zbuffer and normal from global memory
float disp = d_disparity_compact[in_ind + start_ind];
float4 tmp = d_Zbuffer_normals_compact[in_ind + start_ind];
float Zbuffer = tmp.x;
float nx = tmp.y;
float ny = tmp.z;
float nz = tmp.w;
// compute coordinates
int pixel_ind = d_ind_disparity_Zbuffer[in_ind + start_ind];
float y = floorf(__fdividef((float)pixel_ind, n_cols));
float x = (float)pixel_ind - y * n_cols;
x = __fdividef((x - ox), fx);
y = __fdividef((y - oy), fy);
// reconstruct 3D point from disparity
float Zd = -(fx * b) / disp; // arbitrary use of fx
float Xd = x * Zd;
float Yd = y * Zd;
// reconstruct 3D point from model
float Zm = Zbuffer;
float Xm = x * Zm;
float Ym = y * Zm;
// determine M-estimation weight
// disparity residual weighed by rel. importance disp vs flow
int s6 = blockIdx.y * 6;
float w = w_disp * disp_absolute_residual(
Xd, Yd, Zd, Xm, Ym, Zm, nx, ny, nz, d_dTR[s6],
d_dTR[s6 + 1], d_dTR[s6 + 2], d_dTR[s6 + 3],
d_dTR[s6 + 4], d_dTR[s6 + 5], fx, b);
w /= d_abs_res_scales[blockIdx.y];
w = (w > 1) ? 0 : (1.0f - 2.0f * w * w + w * w * w * w);
// multiply m estimation weight with distance->pixel conversion weight
// (squared)
w *= (fx * fx * b * b) / (Zm * Zm * Zm * Zm);
/************************/
/* evaluate constraints */
/************************/
// unique values A-matrix
A0 += w * (nx * nx);
A1 += w * (nx * ny);
A2 += w * (nx * nz);
A3 += w * (Ym * nx * nz - Zm * nx * ny);
A4 += w * (Zm * (nx * nx) - Xm * nx * nz);
A5 += w * (-Ym * (nx * nx) + Xm * nx * ny);
A6 += w * (ny * ny);
A7 += w * (ny * nz);
A8 += w * (-Zm * (ny * ny) + Ym * ny * nz);
A9 += w * (-Xm * ny * nz + Zm * nx * ny);
A10 += w * (Xm * (ny * ny) - Ym * nx * ny);
A11 += w * (nz * nz);
A12 += w * (Ym * (nz * nz) - Zm * ny * nz);
A13 += w * (-Xm * (nz * nz) + Zm * nx * nz);
A14 += w * (Xm * ny * nz - Ym * nx * nz);
A15 += w * ((Ym * Ym) * (nz * nz) + (Zm * Zm) * (ny * ny) -
Ym * Zm * ny * nz * 2.0f);
A16 += w * (-Xm * Ym * (nz * nz) - (Zm * Zm) * nx * ny +
Xm * Zm * ny * nz + Ym * Zm * nx * nz);
A17 += w * (-Xm * Zm * (ny * ny) - (Ym * Ym) * nx * nz +
Xm * Ym * ny * nz + Ym * Zm * nx * ny);
A18 += w * ((Xm * Xm) * (nz * nz) + (Zm * Zm) * (nx * nx) -
Xm * Zm * nx * nz * 2.0f);
A19 += w * (-Ym * Zm * (nx * nx) - (Xm * Xm) * ny * nz +
Xm * Ym * nx * nz + Xm * Zm * nx * ny);
A20 += w * ((Xm * Xm) * (ny * ny) + (Ym * Ym) * (nx * nx) -
Xm * Ym * nx * ny * 2.0f);
// B-vector
A21 += w * (Xd * (nx * nx) - Xm * (nx * nx) + Yd * nx * ny -
Ym * nx * ny + Zd * nx * nz - Zm * nx * nz);
A22 += w * (Yd * (ny * ny) - Ym * (ny * ny) + Xd * nx * ny -
Xm * nx * ny + Zd * ny * nz - Zm * ny * nz);
A23 += w * (Zd * (nz * nz) - Zm * (nz * nz) + Xd * nx * nz -
Xm * nx * nz + Yd * ny * nz - Ym * ny * nz);
A24 += w *
(-Yd * Zm * (ny * ny) + Ym * Zd * (nz * nz) + Ym * Zm * (ny * ny) -
Ym * Zm * (nz * nz) - (Ym * Ym) * ny * nz + (Zm * Zm) * ny * nz +
Xd * Ym * nx * nz - Xm * Ym * nx * nz - Xd * Zm * nx * ny +
Yd * Ym * ny * nz + Xm * Zm * nx * ny - Zd * Zm * ny * nz);
A25 +=
w * (Xd * Zm * (nx * nx) - Xm * Zd * (nz * nz) - Xm * Zm * (nx * nx) +
Xm * Zm * (nz * nz) + (Xm * Xm) * nx * nz - (Zm * Zm) * nx * nz -
Xd * Xm * nx * nz - Xm * Yd * ny * nz + Xm * Ym * ny * nz +
Yd * Zm * nx * ny - Ym * Zm * nx * ny + Zd * Zm * nx * nz);
A26 += w *
(-Xd * Ym * (nx * nx) + Xm * Yd * (ny * ny) + Xm * Ym * (nx * nx) -
Xm * Ym * (ny * ny) - (Xm * Xm) * nx * ny + (Ym * Ym) * nx * ny +
Xd * Xm * nx * ny - Yd * Ym * nx * ny + Xm * Zd * ny * nz -
Xm * Zm * ny * nz - Ym * Zd * nx * nz + Ym * Zm * nx * nz);
}
}
/**************************/
/* write out accumulators */
/**************************/
int out_ind =
27 * n_val_accum * blockIdx.y + blockDim.x * blockIdx.x + threadIdx.x;
w_disp *= w_disp; // weight relative to flow
d_CD[out_ind] = w_disp * A0;
d_CD[out_ind + n_val_accum] = w_disp * A1;
d_CD[out_ind + 2 * n_val_accum] = w_disp * A2;
d_CD[out_ind + 3 * n_val_accum] = w_disp * A3;
d_CD[out_ind + 4 * n_val_accum] = w_disp * A4;
d_CD[out_ind + 5 * n_val_accum] = w_disp * A5;
d_CD[out_ind + 6 * n_val_accum] = w_disp * A6;
d_CD[out_ind + 7 * n_val_accum] = w_disp * A7;
d_CD[out_ind + 8 * n_val_accum] = w_disp * A8;
d_CD[out_ind + 9 * n_val_accum] = w_disp * A9;
d_CD[out_ind + 10 * n_val_accum] = w_disp * A10;
d_CD[out_ind + 11 * n_val_accum] = w_disp * A11;
d_CD[out_ind + 12 * n_val_accum] = w_disp * A12;
d_CD[out_ind + 13 * n_val_accum] = w_disp * A13;
d_CD[out_ind + 14 * n_val_accum] = w_disp * A14;
d_CD[out_ind + 15 * n_val_accum] = w_disp * A15;
d_CD[out_ind + 16 * n_val_accum] = w_disp * A16;
d_CD[out_ind + 17 * n_val_accum] = w_disp * A17;
d_CD[out_ind + 18 * n_val_accum] = w_disp * A18;
d_CD[out_ind + 19 * n_val_accum] = w_disp * A19;
d_CD[out_ind + 20 * n_val_accum] = w_disp * A20;
d_CD[out_ind + 21 * n_val_accum] = w_disp * A21;
d_CD[out_ind + 22 * n_val_accum] = w_disp * A22;
d_CD[out_ind + 23 * n_val_accum] = w_disp * A23;
d_CD[out_ind + 24 * n_val_accum] = w_disp * A24;
d_CD[out_ind + 25 * n_val_accum] = w_disp * A25;
d_CD[out_ind + 26 * n_val_accum] = w_disp * A26;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.globl _Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.p2align 8
.type _Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_,@function
_Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x6c
s_load_b64 s[4:5], s[0:1], 0x38
s_mov_b32 s20, s15
s_mov_b32 s21, 0
s_clause 0x1
s_load_b32 s22, s[0:1], 0x50
s_load_b32 s7, s[0:1], 0x60
s_lshl_b64 s[2:3], s[20:21], 2
v_dual_mov_b32 v29, 0 :: v_dual_mov_b32 v28, 0
v_dual_mov_b32 v27, 0 :: v_dual_mov_b32 v26, 0
v_dual_mov_b32 v25, 0 :: v_dual_mov_b32 v24, 0
v_dual_mov_b32 v23, 0 :: v_dual_mov_b32 v22, 0
v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v20, 0
v_dual_mov_b32 v19, 0 :: v_dual_mov_b32 v18, 0
v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v16, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s24, s6, 0xffff
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_mul_i32 s23, s14, s24
s_load_b32 s25, s[4:5], 0x0
s_mul_i32 s21, s7, s24
s_add_i32 s4, s14, 1
v_cvt_f32_i32_e32 v1, s21
s_mul_i32 s4, s4, s24
v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v14, 0
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, 0
v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, 0
s_mov_b32 s26, exec_lo
v_dual_mov_b32 v31, 0 :: v_dual_mov_b32 v32, 0
v_mov_b32_e32 v30, 0
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v2, s25
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, v1, v1, v2
v_div_scale_f32 v6, vcc_lo, v2, v1, v2
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v1, v3, v1, v2
v_ceil_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v1, v1
v_mad_u64_u32 v[5:6], null, s23, v1, v[0:1]
v_mul_lo_u32 v33, s4, v1
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_lt_u32_e64 v5, v33
s_cbranch_execz .LBB0_8
s_clause 0x3
s_load_b128 s[16:19], s[0:1], 0x40
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b128 s[12:15], s[0:1], 0x28
s_load_b64 s[28:29], s[0:1], 0x58
s_mul_i32 s30, s20, 6
v_dual_mov_b32 v31, 0 :: v_dual_mov_b32 v32, 0
v_dual_mov_b32 v30, 0 :: v_dual_mov_b32 v29, 0
v_dual_mov_b32 v28, 0 :: v_dual_mov_b32 v27, 0
v_dual_mov_b32 v26, 0 :: v_dual_mov_b32 v25, 0
v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v23, 0
v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v22, 0
v_dual_mov_b32 v19, 0 :: v_dual_mov_b32 v16, 0
v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v14, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s34, s16, s2
s_addc_u32 s35, s17, s3
s_ashr_i32 s31, s30, 31
s_load_b32 s27, s[34:35], 0x0
v_mul_f32_e64 v1, s10, s10
s_lshl_b64 s[16:17], s[30:31], 2
v_cvt_f32_i32_e32 v34, s15
s_add_u32 s16, s28, s16
s_addc_u32 s17, s29, s17
s_or_b32 s30, s30, 1
v_dual_mul_f32 v1, s14, v1 :: v_dual_mov_b32 v20, 0
s_ashr_i32 s31, s30, 31
v_mul_f32_e64 v35, -s10, s14
s_lshl_b64 s[30:31], s[30:31], 2
v_mul_f32_e64 v36, s10, s14
v_dual_mul_f32 v37, s14, v1 :: v_dual_mov_b32 v18, 0
s_add_u32 s14, s28, s30
v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v6, 0
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, 0
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, 0
v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, 0
v_mov_b32_e32 v13, 0
s_addc_u32 s15, s29, s31
s_add_u32 s18, s18, s2
s_addc_u32 s19, s19, s3
s_mov_b32 s28, 0
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_dual_mul_f32 v50, v1, v45 :: v_dual_mul_f32 v53, v2, v40
v_dual_mul_f32 v56, v2, v2 :: v_dual_mul_f32 v61, v3, v3
v_dual_mul_f32 v64, v3, v47 :: v_dual_mul_f32 v67, v42, v42
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_mul_f32 v50, v1, v50 :: v_dual_mul_f32 v57, v2, v3
v_dual_mul_f32 v68, v1, v42 :: v_dual_mul_f32 v75, v42, v40
v_mul_f32_e64 v70, v42, -v40
v_div_scale_f32 v51, null, v50, v50, v37
v_div_scale_f32 v65, vcc_lo, v37, v50, v37
v_dual_mul_f32 v72, v1, v40 :: v_dual_mul_f32 v77, v4, v53
s_delay_alu instid0(VALU_DEP_3)
v_rcp_f32_e32 v52, v51
v_dual_mul_f32 v54, v3, v41 :: v_dual_mul_f32 v59, v4, v47
v_dual_mul_f32 v55, v3, v42 :: v_dual_mul_f32 v58, v2, v4
v_dual_mul_f32 v60, v46, v3 :: v_dual_mul_f32 v63, v3, v4
v_mul_f32_e64 v73, v1, -v40
v_fma_f32 v64, v61, v40, -v64
v_mul_f32_e32 v71, v45, v2
s_delay_alu instid0(TRANS32_DEP_1)
v_fma_f32 v62, -v51, v52, 1.0
v_fma_f32 v76, v4, v47, -v60
v_fma_f32 v60, -v4, v48, v60
v_fma_f32 v48, v4, v48, -v59
v_mul_f32_e32 v78, v56, v42
v_fmac_f32_e32 v52, v62, v52
v_dual_mul_f32 v62, v4, v4 :: v_dual_mul_f32 v81, v2, v67
v_mul_f32_e32 v59, v2, v72
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v69, v65, v52
v_fma_f32 v74, -v51, v69, v65
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v69, v74, v52 :: v_dual_mul_f32 v74, v1, v61
v_fma_f32 v51, -v51, v69, v65
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v74, v4, v55, -v74
v_div_fmas_f32 v51, v51, v52, v69
v_mul_f32_e32 v52, v3, v68
v_dual_mul_f32 v69, v71, v3 :: v_dual_mul_f32 v66, v44, v4
v_mul_f32_e32 v79, v62, v67
s_delay_alu instid0(VALU_DEP_4)
v_div_fixup_f32 v50, v51, v50, v37
v_mul_f32_e32 v80, v3, v72
v_fma_f32 v51, v1, v56, -v77
v_fma_f32 v77, v3, v53, -v78
v_fmac_f32_e32 v79, v45, v61
v_dual_mul_f32 v49, v50, v49 :: v_dual_mul_f32 v50, v4, v52
v_mul_f32_e32 v65, v62, v40
v_fma_f32 v52, v62, v70, -v69
v_mul_f32_e32 v69, v4, v81
s_delay_alu instid0(VALU_DEP_4)
v_fmac_f32_e32 v32, v57, v49
v_dual_fmac_f32 v28, v51, v49 :: v_dual_mul_f32 v51, v2, v68
v_fma_f32 v65, v46, v4, -v65
v_dual_fmac_f32 v27, v77, v49 :: v_dual_fmac_f32 v52, v4, v80
v_dual_fmac_f32 v30, v58, v49 :: v_dual_fmac_f32 v79, -2.0, v50
v_fmac_f32_e32 v25, v63, v49
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_fmac_f32 v19, v65, v49 :: v_dual_mul_f32 v50, v40, v40
v_fmac_f32_e32 v52, v4, v51
v_fmac_f32_e32 v31, v56, v49
v_dual_fmac_f32 v29, v76, v49 :: v_dual_mul_f32 v58, v3, v75
v_fma_f32 v57, v61, v73, -v69
v_fmac_f32_e32 v18, v48, v49
v_fmac_f32_e32 v17, v79, v49
v_fmac_f32_e32 v16, v52, v49
v_mul_f32_e32 v48, v3, v50
v_dual_mul_f32 v52, v62, v50 :: v_dual_fmac_f32 v23, v60, v49
v_mul_f32_e32 v60, v56, v40
v_dual_fmac_f32 v26, v61, v49 :: v_dual_fmac_f32 v57, v4, v58
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mul_f32 v48, v4, v48 :: v_dual_mul_f32 v65, v2, v41
v_fma_f32 v60, v56, v39, -v60
v_fma_f32 v66, v62, v42, -v66
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_dual_fmac_f32 v24, v74, v49 :: v_dual_fmac_f32 v57, v3, v51
v_fmac_f32_e32 v21, v64, v49
v_mul_f32_e64 v63, v1, -v42
v_fmac_f32_e32 v52, v45, v56
v_dual_mul_f32 v64, v4, v59 :: v_dual_fmac_f32 v15, v57, v49
v_dual_fmac_f32 v60, v3, v65 :: v_dual_mul_f32 v65, v1, v39
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v48, v56, v63, -v48
v_dual_mul_f32 v63, v2, v75 :: v_dual_fmac_f32 v52, -2.0, v64
s_delay_alu instid0(VALU_DEP_3)
v_fma_f32 v47, -v3, v47, v60
v_mul_f32_e32 v64, v38, v2
v_fmac_f32_e32 v20, v66, v49
v_mul_f32_e32 v66, v61, v50
v_dual_fmac_f32 v22, v62, v49 :: v_dual_mul_f32 v57, v3, v63
v_dual_mul_f32 v45, v45, v3 :: v_dual_mul_f32 v50, v2, v50
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v66, v56, v67
v_mul_f32_e32 v67, v3, v67
v_dual_fmac_f32 v47, v64, v4 :: v_dual_mul_f32 v64, v42, v39
v_dual_mul_f32 v39, v39, v40 :: v_dual_fmac_f32 v66, -2.0, v57
v_dual_mul_f32 v57, v1, v41 :: v_dual_fmac_f32 v48, v4, v63
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v46, -v46, v4, v47
v_mul_f32_e32 v73, v56, v64
v_dual_fmac_f32 v14, v52, v49 :: v_dual_mul_f32 v69, v38, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_dual_mul_f32 v47, v61, v57 :: v_dual_fmac_f32 v48, v3, v59
v_mul_f32_e32 v60, v61, v42
v_fmac_f32_e32 v12, v66, v49
v_dual_mul_f32 v70, v41, v40 :: v_dual_mul_f32 v39, v2, v39
v_fmac_f32_e32 v13, v48, v49
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f32 v52, v61, v41, -v60
v_mul_f32_e32 v60, v38, v42
v_dual_mul_f32 v48, v38, v40 :: v_dual_mul_f32 v41, v41, v42
v_dual_fmac_f32 v11, v46, v49 :: v_dual_fmac_f32 v52, v3, v43
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v47, v62, v60, -v47
v_mul_f32_e32 v66, v62, v48
v_fma_f32 v46, v61, v70, -v73
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v52, -v3, v53, v52
v_fmac_f32_e32 v47, v61, v68
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v66, v56, v65, -v66
v_fmac_f32_e32 v46, v56, v75
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v52, v69, v4
v_fma_f32 v47, -v62, v68, v47
v_mul_f32_e32 v68, v1, v62
v_fma_f32 v66, -v56, v72, v66
v_mul_f32_e32 v1, v38, v1
v_fma_f32 v46, -v61, v75, v46
v_fma_f32 v47, -v4, v67, v47
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v40, -v3, v50, v46
v_fmac_f32_e32 v47, v45, v4
v_mul_f32_e32 v45, v2, v64
v_fma_f32 v56, v38, v62, -v68
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v40, v3, v81
v_fmac_f32_e32 v47, v4, v45
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v56, v4, v43 :: v_dual_mul_f32 v43, v3, v70
v_fma_f32 v45, -v4, v63, v47
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v47, -v4, v53, v56
v_dual_fmac_f32 v66, v62, v72 :: v_dual_fmac_f32 v47, v4, v54
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v66, v4, v50
v_fma_f32 v46, -v71, v4, v66
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v42, -v4, v39, v46
v_mul_f32_e32 v46, v2, v65
v_fma_f32 v42, -v4, v43, v42
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f32 v43, -v3, v46, v45
v_dual_fmac_f32 v40, v3, v39 :: v_dual_mul_f32 v39, v2, v41
v_mul_f32_e32 v41, v3, v41
v_mul_f32_e32 v45, v2, v57
v_fmac_f32_e32 v43, v4, v41
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v39, -v3, v39, v40
v_mul_f32_e32 v40, v3, v48
v_fmac_f32_e32 v43, v3, v59
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v39, v4, v40 :: v_dual_mul_f32 v40, v1, v3
v_mul_f32_e32 v1, v1, v2
v_fmac_f32_e32 v42, v4, v58
v_fma_f32 v38, -v4, v80, v39
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v39, v2, v60 :: v_dual_fmac_f32 v42, v3, v45
v_fma_f32 v2, -v4, v39, v38
v_fma_f32 v39, -v4, v55, v47
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v3, -v3, v51, v42
v_fma_f32 v38, -v44, v4, v52
v_fmac_f32_e32 v9, v39, v49
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v3, v1, v4
v_fma_f32 v40, -v40, v4, v43
v_fmac_f32_e32 v2, v4, v51
v_fmac_f32_e32 v10, v38, v49
v_fmac_f32_e32 v7, v3, v49
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v8, v40, v49
v_fmac_f32_e32 v6, v2, v49
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s29
v_add_nc_u32_e32 v5, s24, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_u32_e32 vcc_lo, v5, v33
s_or_b32 s28, vcc_lo, s28
s_and_not1_b32 exec_lo, exec_lo, s28
s_cbranch_execz .LBB0_7
.LBB0_4:
s_mov_b32 s29, exec_lo
v_cmpx_gt_i32_e64 s25, v5
s_cbranch_execz .LBB0_3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, s27, v5
s_load_b128 s[36:39], s[16:17], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_lshlrev_b64 v[1:2], 4, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v38, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v39, vcc_lo, s9, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v38, v[38:39], off
v_add_co_u32 v1, vcc_lo, s6, v1
global_load_b32 v39, v[3:4], off
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b128 v[1:4], v[1:2], off
s_waitcnt vmcnt(2)
v_cvt_f32_i32_e32 v38, v38
s_waitcnt vmcnt(1)
v_div_scale_f32 v48, s2, v35, v39, v35
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v40, null, v34, v34, v38
v_div_scale_f32 v43, vcc_lo, v38, v34, v38
v_rcp_f32_e32 v41, v40
s_waitcnt_depctr 0xfff
v_fma_f32 v42, -v40, v41, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v41, v42, v41
v_mul_f32_e32 v42, v43, v41
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v44, -v40, v42, v43
v_fmac_f32_e32 v42, v44, v41
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v40, -v40, v42, v43
v_div_fmas_f32 v40, v40, v41, v42
v_div_scale_f32 v41, null, v39, v39, v35
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v40, v40, v34, v38
v_rcp_f32_e32 v42, v41
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v40, v40
v_fma_f32 v38, -v40, v34, v38
v_subrev_f32_e32 v40, s13, v40
s_waitcnt_depctr 0xfff
v_fma_f32 v47, -v41, v42, 1.0
v_subrev_f32_e32 v38, s12, v38
v_div_scale_f32 v44, null, s11, s11, v40
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v43, null, s10, s10, v38
v_rcp_f32_e32 v46, v44
v_div_scale_f32 v50, vcc_lo, v38, s10, v38
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_rcp_f32_e32 v45, v43
s_waitcnt_depctr 0xfff
v_fma_f32 v49, -v43, v45, 1.0
v_fmac_f32_e32 v42, v47, v42
v_fma_f32 v47, -v44, v46, 1.0
v_fmac_f32_e32 v45, v49, v45
v_div_scale_f32 v49, s3, v40, s11, v40
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v46, v47, v46 :: v_dual_mul_f32 v47, v50, v45
v_mul_f32_e32 v52, v49, v46
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v53, -v43, v47, v50
v_fma_f32 v55, -v44, v52, v49
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v47, v53, v45 :: v_dual_fmac_f32 v52, v55, v46
v_fma_f32 v43, -v43, v47, v50
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v44, -v44, v52, v49
v_div_fmas_f32 v43, v43, v45, v47
s_mov_b32 vcc_lo, s3
s_load_b32 s3, s[14:15], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_div_fmas_f32 v44, v44, v46, v52
s_mov_b32 vcc_lo, s2
s_load_b32 s2, s[16:17], 0x0
v_div_fixup_f32 v44, v44, s11, v40
v_mul_f32_e32 v51, v48, v42
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v54, -v41, v51, v48
v_fmac_f32_e32 v51, v54, v42
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v41, -v41, v51, v48
v_div_fmas_f32 v41, v41, v42, v51
v_div_fixup_f32 v42, v43, s10, v38
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f32 v38, v41, v39, v35
s_waitcnt vmcnt(0)
v_mul_f32_e32 v40, v1, v42
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_f32_e32 v39, v38, v42
v_mul_f32_e32 v41, v38, v44
v_mul_f32_e32 v42, v1, v44
v_dual_mul_f32 v48, v3, v40 :: v_dual_mul_f32 v43, v2, v39
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v47, v2, v42
v_fma_f32 v45, v2, v40, -v43
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v44, -v3, v41, v45
v_dual_mul_f32 v45, v1, v1 :: v_dual_fmac_f32 v44, v3, v42
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f32 v49, null, v45, v45, v36
v_div_scale_f32 v51, vcc_lo, v36, v45, v36
v_fma_f32 v44, -v38, v4, v44
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v50, v49
v_fmac_f32_e32 v44, v1, v4
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v44, s2, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v46, -v49, v50, 1.0
s_load_b32 s2, s[18:19], 0x0
v_fmac_f32_e32 v44, s3, v3
v_fmac_f32_e32 v50, v46, v50
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v44, s36, v4
v_mul_f32_e32 v52, v51, v50
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v53, -v49, v52, v51
v_fmac_f32_e32 v52, v53, v50
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v53, v4, v42 :: v_dual_fmac_f32 v44, s39, v48
v_fma_f32 v49, -v49, v52, v51
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v49, v49, v50, v52
v_div_fixup_f32 v49, v49, v45, v36
v_mul_f32_e32 v46, v4, v40
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v44, -s38, v46, v44
v_mul_f32_e32 v46, v1, v2
v_fma_f32 v54, -s39, v47, v44
v_mul_f32_e32 v44, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v54, s37, v53
v_fmac_f32_e32 v54, s38, v46
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v50, -v44, s37, v54
v_mul_f32_e32 v49, v49, v50
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e64 v49, |v49|, s22
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v50, null, s2, s2, v49
v_div_scale_f32 v53, vcc_lo, v49, s2, v49
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v51, v50
s_waitcnt_depctr 0xfff
v_fma_f32 v52, -v50, v51, 1.0
v_fmac_f32_e32 v51, v52, v51
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v52, v53, v51
v_fma_f32 v54, -v50, v52, v53
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v52, v54, v51
v_fma_f32 v50, -v50, v52, v53
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v50, v50, v51, v52
v_div_fixup_f32 v50, v50, s2, v49
v_mov_b32_e32 v49, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_nlt_f32_e32 1.0, v50
s_cbranch_execz .LBB0_2
v_add_f32_e32 v49, v50, v50
v_mul_f32_e32 v51, v50, v50
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v49, -v50, v49, 1.0
v_mul_f32_e32 v51, v50, v51
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v49, v50, v51
s_branch .LBB0_2
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s28
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s26
s_mul_i32 s2, s20, s21
s_load_b64 s[0:1], s[0:1], 0x0
s_mul_i32 s2, s2, 27
v_mul_f32_e64 v2, s22, s22
v_add3_u32 v0, s2, s23, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v5, v2, v31
v_add_nc_u32_e32 v3, s21, v0
v_ashrrev_i32_e32 v1, 31, v0
v_lshl_add_u32 v33, s21, 1, v0
v_mul_f32_e32 v43, v2, v32
v_mul_f32_e32 v29, v2, v29
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[31:32], 2, v[0:1]
v_mad_u64_u32 v[35:36], null, s21, 3, v[0:1]
v_ashrrev_i32_e32 v34, 31, v33
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_mul_f32_e32 v1, v2, v30
s_waitcnt lgkmcnt(0)
v_add_co_u32 v30, vcc_lo, s0, v31
v_lshlrev_b64 v[33:34], 2, v[33:34]
v_add_co_ci_u32_e32 v31, vcc_lo, s1, v32, vcc_lo
v_ashrrev_i32_e32 v36, 31, v35
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v32, vcc_lo, s0, v33
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[35:36], 2, v[35:36]
v_add_co_ci_u32_e32 v33, vcc_lo, s1, v34, vcc_lo
v_lshl_add_u32 v34, s21, 2, v0
v_mad_u64_u32 v[39:40], null, s21, 5, v[0:1]
v_add_co_u32 v37, vcc_lo, s0, v35
s_delay_alu instid0(VALU_DEP_3)
v_ashrrev_i32_e32 v35, 31, v34
v_add_co_ci_u32_e32 v38, vcc_lo, s1, v36, vcc_lo
v_mul_f32_e32 v36, v2, v26
v_mad_u64_u32 v[41:42], null, s21, 6, v[0:1]
s_clause 0x2
global_store_b32 v[30:31], v5, off
global_store_b32 v[3:4], v43, off
global_store_b32 v[32:33], v1, off
v_lshlrev_b64 v[3:4], 2, v[34:35]
v_mul_f32_e32 v1, v2, v28
v_ashrrev_i32_e32 v40, 31, v39
global_store_b32 v[37:38], v29, off
v_mul_f32_e32 v5, v2, v27
v_ashrrev_i32_e32 v42, 31, v41
v_mad_u64_u32 v[32:33], null, s21, 7, v[0:1]
v_lshlrev_b64 v[28:29], 2, v[39:40]
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_mad_u64_u32 v[34:35], null, s21, 9, v[0:1]
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v27, vcc_lo, s0, v28
v_add_co_ci_u32_e32 v28, vcc_lo, s1, v29, vcc_lo
v_ashrrev_i32_e32 v33, 31, v32
global_store_b32 v[3:4], v1, off
v_lshl_add_u32 v3, s21, 3, v0
v_lshlrev_b64 v[30:31], 2, v[41:42]
global_store_b32 v[27:28], v5, off
v_lshlrev_b64 v[26:27], 2, v[32:33]
v_ashrrev_i32_e32 v35, 31, v34
v_ashrrev_i32_e32 v4, 31, v3
v_mul_f32_e32 v1, v2, v25
v_add_co_u32 v29, vcc_lo, s0, v30
v_add_co_ci_u32_e32 v30, vcc_lo, s1, v31, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v25, vcc_lo, s0, v26
v_add_co_ci_u32_e32 v26, vcc_lo, s1, v27, vcc_lo
v_lshlrev_b64 v[27:28], 2, v[34:35]
global_store_b32 v[29:30], v36, off
v_mad_u64_u32 v[29:30], null, s21, 10, v[0:1]
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_mul_f32_e32 v31, v2, v23
v_add_co_u32 v23, vcc_lo, s0, v27
v_mul_f32_e32 v5, v2, v24
v_add_co_ci_u32_e32 v24, vcc_lo, s1, v28, vcc_lo
v_ashrrev_i32_e32 v30, 31, v29
v_mad_u64_u32 v[27:28], null, s21, 11, v[0:1]
s_clause 0x2
global_store_b32 v[25:26], v1, off
global_store_b32 v[3:4], v5, off
global_store_b32 v[23:24], v31, off
v_mul_f32_e32 v1, v2, v21
v_lshlrev_b64 v[3:4], 2, v[29:30]
v_mul_f32_e32 v5, v2, v22
v_mul_f32_e32 v14, v2, v14
v_mul_f32_e32 v11, v2, v11
v_mad_u64_u32 v[23:24], null, s21, 12, v[0:1]
v_ashrrev_i32_e32 v28, 31, v27
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[25:26], 2, v[27:28]
v_ashrrev_i32_e32 v24, 31, v23
v_mad_u64_u32 v[21:22], null, s21, 13, v[0:1]
global_store_b32 v[3:4], v1, off
v_mul_f32_e32 v28, v2, v17
v_lshlrev_b64 v[3:4], 2, v[23:24]
v_mad_u64_u32 v[23:24], null, s21, 14, v[0:1]
v_add_co_u32 v25, vcc_lo, s0, v25
v_add_co_ci_u32_e32 v26, vcc_lo, s1, v26, vcc_lo
v_mul_f32_e32 v1, v2, v20
v_ashrrev_i32_e32 v22, 31, v21
v_ashrrev_i32_e32 v24, 31, v23
global_store_b32 v[25:26], v5, off
v_add_co_u32 v3, vcc_lo, s0, v3
v_mad_u64_u32 v[25:26], null, s21, 15, v[0:1]
v_lshlrev_b64 v[20:21], 2, v[21:22]
v_lshlrev_b64 v[22:23], 2, v[23:24]
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_mul_f32_e32 v5, v2, v19
v_lshl_add_u32 v17, s21, 4, v0
v_add_co_u32 v19, vcc_lo, s0, v20
v_ashrrev_i32_e32 v26, 31, v25
v_add_co_ci_u32_e32 v20, vcc_lo, s1, v21, vcc_lo
v_add_co_u32 v21, vcc_lo, s0, v22
v_add_co_ci_u32_e32 v22, vcc_lo, s1, v23, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[23:24], 2, v[25:26]
v_mad_u64_u32 v[25:26], null, s21, 17, v[0:1]
v_mul_f32_e32 v27, v2, v18
v_ashrrev_i32_e32 v18, 31, v17
global_store_b32 v[3:4], v1, off
v_add_co_u32 v23, vcc_lo, s0, v23
v_add_co_ci_u32_e32 v24, vcc_lo, s1, v24, vcc_lo
v_ashrrev_i32_e32 v26, 31, v25
v_lshlrev_b64 v[3:4], 2, v[17:18]
v_mad_u64_u32 v[17:18], null, s21, 18, v[0:1]
s_clause 0x2
global_store_b32 v[19:20], v5, off
global_store_b32 v[21:22], v27, off
global_store_b32 v[23:24], v28, off
v_lshlrev_b64 v[19:20], 2, v[25:26]
v_mul_f32_e32 v1, v2, v16
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_mul_f32_e32 v5, v2, v15
v_ashrrev_i32_e32 v18, 31, v17
v_add_co_u32 v15, vcc_lo, s0, v19
v_add_co_ci_u32_e32 v16, vcc_lo, s1, v20, vcc_lo
v_mad_u64_u32 v[19:20], null, s21, 19, v[0:1]
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[17:18], 2, v[17:18]
v_mad_u64_u32 v[21:22], null, s21, 20, v[0:1]
v_mad_u64_u32 v[23:24], null, s21, 21, v[0:1]
global_store_b32 v[3:4], v1, off
v_ashrrev_i32_e32 v20, 31, v19
v_add_co_u32 v17, vcc_lo, s0, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s1, v18, vcc_lo
v_ashrrev_i32_e32 v22, 31, v21
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[3:4], 2, v[19:20]
v_ashrrev_i32_e32 v24, 31, v23
v_mul_f32_e32 v1, v2, v13
s_clause 0x1
global_store_b32 v[15:16], v5, off
global_store_b32 v[17:18], v14, off
v_lshlrev_b64 v[13:14], 2, v[21:22]
v_add_co_u32 v3, vcc_lo, s0, v3
v_lshlrev_b64 v[15:16], 2, v[23:24]
v_mad_u64_u32 v[17:18], null, s21, 22, v[0:1]
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_mul_f32_e32 v5, v2, v12
v_add_co_u32 v12, vcc_lo, s0, v13
v_add_co_ci_u32_e32 v13, vcc_lo, s1, v14, vcc_lo
v_mad_u64_u32 v[19:20], null, s21, 23, v[0:1]
v_add_co_u32 v14, vcc_lo, s0, v15
v_add_co_ci_u32_e32 v15, vcc_lo, s1, v16, vcc_lo
v_mad_u64_u32 v[21:22], null, s21, 24, v[0:1]
v_ashrrev_i32_e32 v18, 31, v17
s_clause 0x2
global_store_b32 v[3:4], v1, off
global_store_b32 v[12:13], v5, off
global_store_b32 v[14:15], v11, off
v_mul_f32_e32 v23, v2, v10
v_mad_u64_u32 v[10:11], null, s21, 25, v[0:1]
v_ashrrev_i32_e32 v20, 31, v19
v_lshlrev_b64 v[3:4], 2, v[17:18]
v_mad_u64_u32 v[16:17], null, s21, 26, v[0:1]
v_ashrrev_i32_e32 v22, 31, v21
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[12:13], 2, v[19:20]
v_ashrrev_i32_e32 v11, 31, v10
v_add_co_u32 v3, vcc_lo, s0, v3
v_lshlrev_b64 v[14:15], 2, v[21:22]
v_ashrrev_i32_e32 v17, 31, v16
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_mul_f32_e32 v18, v2, v9
v_add_co_u32 v0, vcc_lo, s0, v12
v_mul_f32_e32 v19, v2, v8
v_lshlrev_b64 v[8:9], 2, v[10:11]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v13, vcc_lo
v_add_co_u32 v10, vcc_lo, s0, v14
v_lshlrev_b64 v[12:13], 2, v[16:17]
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v15, vcc_lo
v_mul_f32_e32 v14, v2, v7
v_add_co_u32 v7, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v9, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v12
v_mul_f32_e32 v2, v2, v6
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v13, vcc_lo
s_clause 0x4
global_store_b32 v[3:4], v23, off
global_store_b32 v[0:1], v18, off
global_store_b32 v[10:11], v19, off
global_store_b32 v[7:8], v14, off
global_store_b32 v[5:6], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 352
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 82
.amdhsa_next_free_sgpr 40
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_, .Lfunc_end0-_Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .offset: 96
.size: 4
.value_kind: hidden_block_count_x
- .offset: 100
.size: 4
.value_kind: hidden_block_count_y
- .offset: 104
.size: 4
.value_kind: hidden_block_count_z
- .offset: 108
.size: 2
.value_kind: hidden_group_size_x
- .offset: 110
.size: 2
.value_kind: hidden_group_size_y
- .offset: 112
.size: 2
.value_kind: hidden_group_size_z
- .offset: 114
.size: 2
.value_kind: hidden_remainder_x
- .offset: 116
.size: 2
.value_kind: hidden_remainder_y
- .offset: 118
.size: 2
.value_kind: hidden_remainder_z
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 160
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 352
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.private_segment_fixed_size: 0
.sgpr_count: 42
.sgpr_spill_count: 0
.symbol: _Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 82
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ static float disp_absolute_residual(float Xd, float Yd, float Zd, float Xm, float Ym, float Zm, float nx, float ny, float nz, float T0, float T1, float T2, float R0, float R1, float R2, float fx, float b) {
float r = -Xd * nx + Xm * nx - Yd * ny + Ym * ny - Zd * nz + Zm * nz +
nx * T0 + ny * T1 + nz * T2 + Xm * ny * R2 - Xm * nz * R1 -
Ym * nx * R2 + Ym * nz * R0 + Zm * nx * R1 - Zm * ny * R0;
// weight to convert distance units to pixels
r *= fx * b / (Zm * Zm);
return fabsf(r);
}
__global__ void normal_eqs_disparity_weighted_GPU( float *d_CD, const float *d_disparity_compact, const float4 *d_Zbuffer_normals_compact, const int *d_ind_disparity_Zbuffer, float fx, float fy, float ox, float oy, float b, int n_cols, const int *d_n_values_disparity, const int *d_start_ind_disparity, const float *d_abs_res_scales, float w_disp, const float *d_dTR) {
int n_val_accum =
gridDim.x * blockDim.x; // n_val_accum may not be multiple of blocksize
int n_disparity = d_n_values_disparity[blockIdx.y];
int n_accum = (int)ceilf((float)n_disparity / (float)n_val_accum);
int start_ind = d_start_ind_disparity[blockIdx.y];
// initialize accumulators
float A0 = 0.0f, A1 = 0.0f, A2 = 0.0f, A3 = 0.0f, A4 = 0.0f, A5 = 0.0f,
A6 = 0.0f, A7 = 0.0f, A8 = 0.0f, A9 = 0.0f, A10 = 0.0f, A11 = 0.0f,
A12 = 0.0f, A13 = 0.0f, A14 = 0.0f, A15 = 0.0f, A16 = 0.0f, A17 = 0.0f,
A18 = 0.0f, A19 = 0.0f, A20 = 0.0f, A21 = 0.0f, A22 = 0.0f, A23 = 0.0f,
A24 = 0.0f, A25 = 0.0f, A26 = 0.0f;
for (int in_ind = blockDim.x * blockIdx.x * n_accum + threadIdx.x;
in_ind < blockDim.x * (blockIdx.x + 1) * n_accum; in_ind += blockDim.x) {
if (in_ind < n_disparity) { // is this a valid sample?
// fetch disparity, Zbuffer and normal from global memory
float disp = d_disparity_compact[in_ind + start_ind];
float4 tmp = d_Zbuffer_normals_compact[in_ind + start_ind];
float Zbuffer = tmp.x;
float nx = tmp.y;
float ny = tmp.z;
float nz = tmp.w;
// compute coordinates
int pixel_ind = d_ind_disparity_Zbuffer[in_ind + start_ind];
float y = floorf(__fdividef((float)pixel_ind, n_cols));
float x = (float)pixel_ind - y * n_cols;
x = __fdividef((x - ox), fx);
y = __fdividef((y - oy), fy);
// reconstruct 3D point from disparity
float Zd = -(fx * b) / disp; // arbitrary use of fx
float Xd = x * Zd;
float Yd = y * Zd;
// reconstruct 3D point from model
float Zm = Zbuffer;
float Xm = x * Zm;
float Ym = y * Zm;
// determine M-estimation weight
// disparity residual weighed by rel. importance disp vs flow
int s6 = blockIdx.y * 6;
float w = w_disp * disp_absolute_residual(
Xd, Yd, Zd, Xm, Ym, Zm, nx, ny, nz, d_dTR[s6],
d_dTR[s6 + 1], d_dTR[s6 + 2], d_dTR[s6 + 3],
d_dTR[s6 + 4], d_dTR[s6 + 5], fx, b);
w /= d_abs_res_scales[blockIdx.y];
w = (w > 1) ? 0 : (1.0f - 2.0f * w * w + w * w * w * w);
// multiply m estimation weight with distance->pixel conversion weight
// (squared)
w *= (fx * fx * b * b) / (Zm * Zm * Zm * Zm);
/************************/
/* evaluate constraints */
/************************/
// unique values A-matrix
A0 += w * (nx * nx);
A1 += w * (nx * ny);
A2 += w * (nx * nz);
A3 += w * (Ym * nx * nz - Zm * nx * ny);
A4 += w * (Zm * (nx * nx) - Xm * nx * nz);
A5 += w * (-Ym * (nx * nx) + Xm * nx * ny);
A6 += w * (ny * ny);
A7 += w * (ny * nz);
A8 += w * (-Zm * (ny * ny) + Ym * ny * nz);
A9 += w * (-Xm * ny * nz + Zm * nx * ny);
A10 += w * (Xm * (ny * ny) - Ym * nx * ny);
A11 += w * (nz * nz);
A12 += w * (Ym * (nz * nz) - Zm * ny * nz);
A13 += w * (-Xm * (nz * nz) + Zm * nx * nz);
A14 += w * (Xm * ny * nz - Ym * nx * nz);
A15 += w * ((Ym * Ym) * (nz * nz) + (Zm * Zm) * (ny * ny) -
Ym * Zm * ny * nz * 2.0f);
A16 += w * (-Xm * Ym * (nz * nz) - (Zm * Zm) * nx * ny +
Xm * Zm * ny * nz + Ym * Zm * nx * nz);
A17 += w * (-Xm * Zm * (ny * ny) - (Ym * Ym) * nx * nz +
Xm * Ym * ny * nz + Ym * Zm * nx * ny);
A18 += w * ((Xm * Xm) * (nz * nz) + (Zm * Zm) * (nx * nx) -
Xm * Zm * nx * nz * 2.0f);
A19 += w * (-Ym * Zm * (nx * nx) - (Xm * Xm) * ny * nz +
Xm * Ym * nx * nz + Xm * Zm * nx * ny);
A20 += w * ((Xm * Xm) * (ny * ny) + (Ym * Ym) * (nx * nx) -
Xm * Ym * nx * ny * 2.0f);
// B-vector
A21 += w * (Xd * (nx * nx) - Xm * (nx * nx) + Yd * nx * ny -
Ym * nx * ny + Zd * nx * nz - Zm * nx * nz);
A22 += w * (Yd * (ny * ny) - Ym * (ny * ny) + Xd * nx * ny -
Xm * nx * ny + Zd * ny * nz - Zm * ny * nz);
A23 += w * (Zd * (nz * nz) - Zm * (nz * nz) + Xd * nx * nz -
Xm * nx * nz + Yd * ny * nz - Ym * ny * nz);
A24 += w *
(-Yd * Zm * (ny * ny) + Ym * Zd * (nz * nz) + Ym * Zm * (ny * ny) -
Ym * Zm * (nz * nz) - (Ym * Ym) * ny * nz + (Zm * Zm) * ny * nz +
Xd * Ym * nx * nz - Xm * Ym * nx * nz - Xd * Zm * nx * ny +
Yd * Ym * ny * nz + Xm * Zm * nx * ny - Zd * Zm * ny * nz);
A25 +=
w * (Xd * Zm * (nx * nx) - Xm * Zd * (nz * nz) - Xm * Zm * (nx * nx) +
Xm * Zm * (nz * nz) + (Xm * Xm) * nx * nz - (Zm * Zm) * nx * nz -
Xd * Xm * nx * nz - Xm * Yd * ny * nz + Xm * Ym * ny * nz +
Yd * Zm * nx * ny - Ym * Zm * nx * ny + Zd * Zm * nx * nz);
A26 += w *
(-Xd * Ym * (nx * nx) + Xm * Yd * (ny * ny) + Xm * Ym * (nx * nx) -
Xm * Ym * (ny * ny) - (Xm * Xm) * nx * ny + (Ym * Ym) * nx * ny +
Xd * Xm * nx * ny - Yd * Ym * nx * ny + Xm * Zd * ny * nz -
Xm * Zm * ny * nz - Ym * Zd * nx * nz + Ym * Zm * nx * nz);
}
}
/**************************/
/* write out accumulators */
/**************************/
int out_ind =
27 * n_val_accum * blockIdx.y + blockDim.x * blockIdx.x + threadIdx.x;
w_disp *= w_disp; // weight relative to flow
d_CD[out_ind] = w_disp * A0;
d_CD[out_ind + n_val_accum] = w_disp * A1;
d_CD[out_ind + 2 * n_val_accum] = w_disp * A2;
d_CD[out_ind + 3 * n_val_accum] = w_disp * A3;
d_CD[out_ind + 4 * n_val_accum] = w_disp * A4;
d_CD[out_ind + 5 * n_val_accum] = w_disp * A5;
d_CD[out_ind + 6 * n_val_accum] = w_disp * A6;
d_CD[out_ind + 7 * n_val_accum] = w_disp * A7;
d_CD[out_ind + 8 * n_val_accum] = w_disp * A8;
d_CD[out_ind + 9 * n_val_accum] = w_disp * A9;
d_CD[out_ind + 10 * n_val_accum] = w_disp * A10;
d_CD[out_ind + 11 * n_val_accum] = w_disp * A11;
d_CD[out_ind + 12 * n_val_accum] = w_disp * A12;
d_CD[out_ind + 13 * n_val_accum] = w_disp * A13;
d_CD[out_ind + 14 * n_val_accum] = w_disp * A14;
d_CD[out_ind + 15 * n_val_accum] = w_disp * A15;
d_CD[out_ind + 16 * n_val_accum] = w_disp * A16;
d_CD[out_ind + 17 * n_val_accum] = w_disp * A17;
d_CD[out_ind + 18 * n_val_accum] = w_disp * A18;
d_CD[out_ind + 19 * n_val_accum] = w_disp * A19;
d_CD[out_ind + 20 * n_val_accum] = w_disp * A20;
d_CD[out_ind + 21 * n_val_accum] = w_disp * A21;
d_CD[out_ind + 22 * n_val_accum] = w_disp * A22;
d_CD[out_ind + 23 * n_val_accum] = w_disp * A23;
d_CD[out_ind + 24 * n_val_accum] = w_disp * A24;
d_CD[out_ind + 25 * n_val_accum] = w_disp * A25;
d_CD[out_ind + 26 * n_val_accum] = w_disp * A26;
} | .text
.file "normal_eqs_disparity_weighted_GPU.hip"
.globl _Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_ # -- Begin function _Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.p2align 4, 0x90
.type _Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_,@function
_Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_: # @_Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm4, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 88(%rsp)
movss %xmm5, 12(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 28(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 20(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 88(%rsp), %rax
movq %rax, 208(%rsp)
leaq 256(%rsp), %rax
movq %rax, 216(%rsp)
leaq 264(%rsp), %rax
movq %rax, 224(%rsp)
leaq 12(%rsp), %rax
movq %rax, 232(%rsp)
leaq 272(%rsp), %rax
movq %rax, 240(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_, .Lfunc_end0-_Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_,@object # @_Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.section .rodata,"a",@progbits
.globl _Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.p2align 3, 0x0
_Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_:
.quad _Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.size _Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_"
.size .L__unnamed_1, 91
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001416fa_00000000-6_normal_eqs_disparity_weighted_GPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z87__device_stub__Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_PfPKfPK6float4PKifffffiS6_S6_S1_fS1_
.type _Z87__device_stub__Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_PfPKfPK6float4PKifffffiS6_S6_S1_fS1_, @function
_Z87__device_stub__Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_PfPKfPK6float4PKifffffiS6_S6_S1_fS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 60(%rsp)
movss %xmm1, 56(%rsp)
movss %xmm2, 52(%rsp)
movss %xmm3, 48(%rsp)
movss %xmm4, 44(%rsp)
movl %r8d, 40(%rsp)
movq %r9, 32(%rsp)
movss %xmm5, 12(%rsp)
movq 304(%rsp), %rax
movq %rax, 24(%rsp)
movq 312(%rsp), %rax
movq %rax, 16(%rsp)
movq 320(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 60(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rax
movq %rax, 200(%rsp)
leaq 52(%rsp), %rax
movq %rax, 208(%rsp)
leaq 48(%rsp), %rax
movq %rax, 216(%rsp)
leaq 44(%rsp), %rax
movq %rax, 224(%rsp)
leaq 40(%rsp), %rax
movq %rax, 232(%rsp)
leaq 32(%rsp), %rax
movq %rax, 240(%rsp)
leaq 24(%rsp), %rax
movq %rax, 248(%rsp)
leaq 16(%rsp), %rax
movq %rax, 256(%rsp)
leaq 12(%rsp), %rax
movq %rax, 264(%rsp)
movq %rsp, %rax
movq %rax, 272(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 312
pushq 104(%rsp)
.cfi_def_cfa_offset 320
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z87__device_stub__Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_PfPKfPK6float4PKifffffiS6_S6_S1_fS1_, .-_Z87__device_stub__Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_PfPKfPK6float4PKifffffiS6_S6_S1_fS1_
.globl _Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_
.type _Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_, @function
_Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z87__device_stub__Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_PfPKfPK6float4PKifffffiS6_S6_S1_fS1_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_, .-_Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z33normal_eqs_disparity_weighted_GPUPfPKfPK6float4PKifffffiS6_S6_S1_fS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "normal_eqs_disparity_weighted_GPU.hip"
.globl _Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_ # -- Begin function _Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.p2align 4, 0x90
.type _Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_,@function
_Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_: # @_Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm4, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 88(%rsp)
movss %xmm5, 12(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 28(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 20(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 88(%rsp), %rax
movq %rax, 208(%rsp)
leaq 256(%rsp), %rax
movq %rax, 216(%rsp)
leaq 264(%rsp), %rax
movq %rax, 224(%rsp)
leaq 12(%rsp), %rax
movq %rax, 232(%rsp)
leaq 272(%rsp), %rax
movq %rax, 240(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_, .Lfunc_end0-_Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_,@object # @_Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.section .rodata,"a",@progbits
.globl _Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.p2align 3, 0x0
_Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_:
.quad _Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.size _Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_"
.size .L__unnamed_1, 91
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z48__device_stub__normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z33normal_eqs_disparity_weighted_GPUPfPKfPK15HIP_vector_typeIfLj4EEPKifffffiS7_S7_S1_fS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <unistd.h>
#include <sys/time.h>
/* Problem size. */
#define NX 5000
#define NY 5000
#ifndef M_PI
#define M_PI 3.14159
#endif
const unsigned int THREADS_PER_BLOCK = 32;
void init_array(double *x, double *A)
{
int i, j;
for (i = 0; i < NX; i++) {
for (j = 0; j < NY; j++) {
A[i*NY + j] = ((double) i*(j)) / NX;
}
}
for (i = 0; i < NY; i++) {
x[i] = i * M_PI;
}
}
void trans_norm_vector(double* A, double* x, double* y, double* tmp)
{
int i,j;
for (i= 0; i < NY; i++) {
y[i] = 0;
}
for (i = 0; i < NX; i++) {
tmp[i] = 0;
for (j = 0; j < NY; j++) {
tmp[i] = tmp[i] + A[i*NY + j] * x[j];
}
for (j = 0; j < NY; j++) {
y[j] = y[j] + A[i*NY + j] * tmp[i];
}
}
}
__global__ void trans_norm_vector_kernel(double* A, double* x, double* y, int transpose)
{
if(transpose == 0){
int i = threadIdx.y + blockDim.y * blockIdx.y;
if(i<NX){
y[i] = 0;
double tmp = 0;
for (int j = 0; j < NY; j++)
tmp = tmp + A[i*NY + j] * x[j];
y[i] = tmp;
}
}else{
int j = threadIdx.y + blockDim.y * blockIdx.y;
if(j<NY){
y[j] = 0;
double tmp = 0;
for (int i = 0; i < NX; i++)
tmp = tmp + A[j + i*NY] * x[i];
y[j] = tmp;
}
}
}
__global__ void trans_norm_vector_shared(double* A, double* x, double* y, int transpose)
{
if(transpose == 0){
int i = threadIdx.y + blockDim.y * blockIdx.y;
y[i] = 0;
__shared__ double xs[THREADS_PER_BLOCK];
double tmp = 0;
for(int step=0;step<ceil((double)NY/THREADS_PER_BLOCK);step++){
if(threadIdx.y+step*THREADS_PER_BLOCK>=NY)
xs[threadIdx.y]=0;
else
xs[threadIdx.y]=x[threadIdx.y+step*THREADS_PER_BLOCK];
__syncthreads();
for (int j = 0; j < THREADS_PER_BLOCK; j++)
tmp = tmp + A[i*NY + j + step*THREADS_PER_BLOCK] * xs[j];
__syncthreads();
}
y[i] = tmp;
}else{
int j = threadIdx.y + blockDim.y * blockIdx.y;
if(j<NY){
y[j] = 0;
double tmp = 0;
for (int i = 0; i < NX; i++)
tmp = tmp + A[j + i*NY] * x[i];
y[j] = tmp;
}
}
}
int main(int argc, char *argv[])
{
//Serial program variables
double *y;
//Host and Device variables for CUDA
double *A_h;
double *x_h;
double *y_h;
double *tmp_h;
double *A_d;
double *x_d;
double *y_d;
double *tmp_d;
struct timeval start, end;
//Variables for shared memory implementation
double *A_s;
double *x_s;
double *y_s;
double *tmp_s;
A_h = (double*)malloc(NX*NY*sizeof(double));
x_h = (double*)malloc(NY*sizeof(double));
y_h = (double*)malloc(NY*sizeof(double));
tmp_h = (double*)malloc(NX*sizeof(double));
y = (double*)malloc(NY*sizeof(double));
init_array(x_h, A_h);
cudaMalloc((void**)&A_d, NX*NY*sizeof(double));
cudaMalloc((void**)&x_d, NY*sizeof(double));
cudaMalloc((void**)&y_d, NY*sizeof(double));
cudaMalloc((void**)&tmp_d, NX*sizeof(double));
cudaMalloc((void**)&A_s, NX*NY*sizeof(double));
cudaMalloc((void**)&x_s, NY*sizeof(double));
cudaMalloc((void**)&y_s, NY*sizeof(double));
cudaMalloc((void**)&tmp_s, NX*sizeof(double));
fprintf(stdout, "NX: %d NY: %d\n", NX, NY);
const unsigned int numBlocksInCol= ceil((double)NX/THREADS_PER_BLOCK);
const unsigned int numBlocksInRow= ceil((double)NY/THREADS_PER_BLOCK);
dim3 gridDim(1, numBlocksInCol, 1), blockDim(1, THREADS_PER_BLOCK, 1);
dim3 gridDimT(1, numBlocksInRow, 1);
//Start of CUDA code
gettimeofday(&start, NULL);
cudaMemcpy(A_d, A_h, NX*NY*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(x_d, x_h, NY*sizeof(double), cudaMemcpyHostToDevice);
trans_norm_vector_kernel <<< gridDim, blockDim >>>(A_d, x_d, tmp_d, 0);
trans_norm_vector_kernel <<< gridDimT, blockDim >>>(A_d, tmp_d, y_d, 1);
cudaMemcpy(y_h, y_d , sizeof(double)*NY, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
gettimeofday(&end, NULL);
fprintf(stdout, "GPU Runtime :%0.6lfs\n", ((end.tv_sec - start.tv_sec) * 1000000.0 + (end.tv_usec - start.tv_usec)) / 1000000.0);
//Start of CUDA shared code
gettimeofday(&start, NULL);
cudaMemcpy(A_s, A_h, NX*NY*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(x_s, x_h, NY*sizeof(double), cudaMemcpyHostToDevice);
trans_norm_vector_shared <<< gridDim, blockDim >>>(A_s, x_s, tmp_s, 0);
trans_norm_vector_shared <<< gridDimT, blockDim >>>(A_s, tmp_s, y_s, 1);
cudaMemcpy(y_h, y_s , sizeof(double)*NY, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
gettimeofday(&end, NULL);
fprintf(stdout, "GPU Shared Runtime :%0.6lfs\n", ((end.tv_sec - start.tv_sec) * 1000000.0 + (end.tv_usec - start.tv_usec)) / 1000000.0);
//Start of Serial code
gettimeofday(&start, NULL);
trans_norm_vector(A_h, x_h, y, tmp_h);
gettimeofday(&end, NULL);
fprintf(stdout, "CPU Runtime :%0.6lfs\n", ((end.tv_sec - start.tv_sec) * 1000000.0 + (end.tv_usec - start.tv_usec)) / 1000000.0);
//Error checking CUDA results according to Serial results
int errors = 0;
for (int i = 0; i < NY; ++i) {
double error=fabs((y[i] -y_h[i])/y[i]);
if(error>pow(10,-14)){
printf("Error %.20f in (%d)\n",error,i);
errors++;
}
}
printf("Vector\n\tTotal Results: %d\n\tError count: %d\n",NX*NY,errors);
free(A_h);
free(x_h);
free(y_h);
free(tmp_h);
cudaFree(A_s);
cudaFree(x_s);
cudaFree(y_s);
cudaFree(tmp_s);
return 0;
} | .file "tmpxft_0003ccb2_00000000-6_TransNormVector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10init_arrayPdS_
.type _Z10init_arrayPdS_, @function
_Z10init_arrayPdS_:
.LFB2070:
.cfi_startproc
endbr64
movq %rsi, %rdx
movl $0, %ecx
movsd .LC0(%rip), %xmm2
.L4:
movl $0, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %ecx, %xmm1
.L5:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm1, %xmm0
divsd %xmm2, %xmm0
movsd %xmm0, (%rdx,%rax,8)
addq $1, %rax
cmpq $5000, %rax
jne .L5
addl $1, %ecx
addq $40000, %rdx
cmpl $5000, %ecx
jne .L4
movl $0, %eax
movsd .LC1(%rip), %xmm1
.L6:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm1, %xmm0
movsd %xmm0, (%rdi,%rax,8)
addq $1, %rax
cmpq $5000, %rax
jne .L6
ret
.cfi_endproc
.LFE2070:
.size _Z10init_arrayPdS_, .-_Z10init_arrayPdS_
.globl _Z17trans_norm_vectorPdS_S_S_
.type _Z17trans_norm_vectorPdS_S_S_, @function
_Z17trans_norm_vectorPdS_S_S_:
.LFB2071:
.cfi_startproc
endbr64
movq %rdi, %rax
movq %rsi, %r8
movq %rdx, %rsi
movq %rcx, %r9
leaq 40000(%rdx), %rcx
.L11:
movq $0x000000000, (%rdx)
addq $8, %rdx
cmpq %rcx, %rdx
jne .L11
movq %rax, %rcx
movl $0, %r10d
.L14:
movq %r9, %rdx
movq $0x000000000, (%r9)
movl $0, %eax
movq %rcx, %rdi
.L12:
movsd (%rcx,%rax), %xmm0
mulsd (%r8,%rax), %xmm0
addsd (%rdx), %xmm0
movsd %xmm0, (%rdx)
addq $8, %rax
cmpq $40000, %rax
jne .L12
movl $0, %eax
.L13:
movsd (%rdi,%rax), %xmm0
mulsd (%rdx), %xmm0
addsd (%rsi,%rax), %xmm0
movsd %xmm0, (%rsi,%rax)
addq $8, %rax
cmpq $40000, %rax
jne .L13
addq $8, %r9
addl $5000, %r10d
addq $40000, %rcx
cmpl $25000000, %r10d
jne .L14
ret
.cfi_endproc
.LFE2071:
.size _Z17trans_norm_vectorPdS_S_S_, .-_Z17trans_norm_vectorPdS_S_S_
.globl _Z49__device_stub__Z24trans_norm_vector_kernelPdS_S_iPdS_S_i
.type _Z49__device_stub__Z24trans_norm_vector_kernelPdS_S_iPdS_S_i, @function
_Z49__device_stub__Z24trans_norm_vector_kernelPdS_S_iPdS_S_i:
.LFB2098:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24trans_norm_vector_kernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z49__device_stub__Z24trans_norm_vector_kernelPdS_S_iPdS_S_i, .-_Z49__device_stub__Z24trans_norm_vector_kernelPdS_S_iPdS_S_i
.globl _Z24trans_norm_vector_kernelPdS_S_i
.type _Z24trans_norm_vector_kernelPdS_S_i, @function
_Z24trans_norm_vector_kernelPdS_S_i:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z24trans_norm_vector_kernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z24trans_norm_vector_kernelPdS_S_i, .-_Z24trans_norm_vector_kernelPdS_S_i
.globl _Z49__device_stub__Z24trans_norm_vector_sharedPdS_S_iPdS_S_i
.type _Z49__device_stub__Z24trans_norm_vector_sharedPdS_S_iPdS_S_i, @function
_Z49__device_stub__Z24trans_norm_vector_sharedPdS_S_iPdS_S_i:
.LFB2100:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24trans_norm_vector_sharedPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z49__device_stub__Z24trans_norm_vector_sharedPdS_S_iPdS_S_i, .-_Z49__device_stub__Z24trans_norm_vector_sharedPdS_S_iPdS_S_i
.globl _Z24trans_norm_vector_sharedPdS_S_i
.type _Z24trans_norm_vector_sharedPdS_S_i, @function
_Z24trans_norm_vector_sharedPdS_S_i:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z24trans_norm_vector_sharedPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z24trans_norm_vector_sharedPdS_S_i, .-_Z24trans_norm_vector_sharedPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "NX: %d NY: %d\n"
.LC5:
.string "GPU Runtime :%0.6lfs\n"
.LC6:
.string "GPU Shared Runtime :%0.6lfs\n"
.LC7:
.string "CPU Runtime :%0.6lfs\n"
.LC10:
.string "Error %.20f in (%d)\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "Vector\n\tTotal Results: %d\n\tError count: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2072:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movl $200000000, %edi
call malloc@PLT
movq %rax, %r15
movl $40000, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, (%rsp)
movl $40000, %edi
call malloc@PLT
movq %rax, %rbp
movl $40000, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $40000, %edi
call malloc@PLT
movq %rax, %r12
movq %r15, %rsi
movq %rbx, %rdi
call _Z10init_arrayPdS_
leaq 24(%rsp), %rdi
movl $200000000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $200000000, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $5000, %r8d
movl $5000, %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, 92(%rsp)
movl $157, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $32, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $157, 120(%rsp)
movl $1, 124(%rsp)
leaq 128(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1, %ecx
movl $200000000, %edx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl 112(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 104(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L36:
movl 112(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 104(%rsp), %rdx
movq 116(%rsp), %rdi
movl 124(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L37:
movl $2, %ecx
movl $40000, %edx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
leaq 144(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 144(%rsp), %rax
subq 128(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC4(%rip), %xmm1
mulsd %xmm1, %xmm0
movq 152(%rsp), %rax
subq 136(%rsp), %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
addsd %xmm2, %xmm0
divsd %xmm1, %xmm0
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
leaq 128(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1, %ecx
movl $200000000, %edx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000, %edx
movq (%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl 112(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 104(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L38:
movl 112(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 104(%rsp), %rdx
movq 116(%rsp), %rdi
movl 124(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L39:
movl $2, %ecx
movl $40000, %edx
movq 72(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
leaq 144(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
movq 144(%rsp), %rax
subq 128(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC4(%rip), %xmm0
movq 152(%rsp), %rax
subq 136(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
divsd .LC4(%rip), %xmm0
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
leaq 128(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 8(%rsp), %rcx
movq %r12, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call _Z17trans_norm_vectorPdS_S_S_
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
movq 144(%rsp), %rax
subq 128(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC4(%rip), %xmm0
movq 152(%rsp), %rax
subq 136(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
divsd .LC4(%rip), %xmm0
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl $0, %ebx
movl $0, %r13d
leaq .LC10(%rip), %r14
jmp .L42
.L47:
movl $0, %ecx
movq 48(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z49__device_stub__Z24trans_norm_vector_kernelPdS_S_iPdS_S_i
jmp .L36
.L48:
movl $1, %ecx
movq 40(%rsp), %rdx
movq 48(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z49__device_stub__Z24trans_norm_vector_kernelPdS_S_iPdS_S_i
jmp .L37
.L49:
movl $0, %ecx
movq 80(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z49__device_stub__Z24trans_norm_vector_sharedPdS_S_iPdS_S_i
jmp .L38
.L50:
movl $1, %ecx
movq 72(%rsp), %rdx
movq 80(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z49__device_stub__Z24trans_norm_vector_sharedPdS_S_iPdS_S_i
jmp .L39
.L40:
addq $1, %rbx
cmpq $5000, %rbx
je .L51
.L42:
movsd (%r12,%rbx,8), %xmm1
movapd %xmm1, %xmm0
subsd 0(%rbp,%rbx,8), %xmm0
divsd %xmm1, %xmm0
andpd .LC8(%rip), %xmm0
comisd .LC9(%rip), %xmm0
jbe .L40
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %r13d
jmp .L40
.L51:
movl %r13d, %ecx
movl $25000000, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2072:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC12:
.string "_Z24trans_norm_vector_sharedPdS_S_i"
.align 8
.LC13:
.string "_Z24trans_norm_vector_kernelPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2103:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z24trans_norm_vector_sharedPdS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z24trans_norm_vector_kernelPdS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1085507584
.align 8
.LC1:
.long 1413754136
.long 1074340347
.align 8
.LC4:
.long 0
.long 1093567616
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC8:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC9:
.long -2036257893
.long 1023837339
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <unistd.h>
#include <sys/time.h>
/* Problem size. */
#define NX 5000
#define NY 5000
#ifndef M_PI
#define M_PI 3.14159
#endif
const unsigned int THREADS_PER_BLOCK = 32;
void init_array(double *x, double *A)
{
int i, j;
for (i = 0; i < NX; i++) {
for (j = 0; j < NY; j++) {
A[i*NY + j] = ((double) i*(j)) / NX;
}
}
for (i = 0; i < NY; i++) {
x[i] = i * M_PI;
}
}
void trans_norm_vector(double* A, double* x, double* y, double* tmp)
{
int i,j;
for (i= 0; i < NY; i++) {
y[i] = 0;
}
for (i = 0; i < NX; i++) {
tmp[i] = 0;
for (j = 0; j < NY; j++) {
tmp[i] = tmp[i] + A[i*NY + j] * x[j];
}
for (j = 0; j < NY; j++) {
y[j] = y[j] + A[i*NY + j] * tmp[i];
}
}
}
__global__ void trans_norm_vector_kernel(double* A, double* x, double* y, int transpose)
{
if(transpose == 0){
int i = threadIdx.y + blockDim.y * blockIdx.y;
if(i<NX){
y[i] = 0;
double tmp = 0;
for (int j = 0; j < NY; j++)
tmp = tmp + A[i*NY + j] * x[j];
y[i] = tmp;
}
}else{
int j = threadIdx.y + blockDim.y * blockIdx.y;
if(j<NY){
y[j] = 0;
double tmp = 0;
for (int i = 0; i < NX; i++)
tmp = tmp + A[j + i*NY] * x[i];
y[j] = tmp;
}
}
}
__global__ void trans_norm_vector_shared(double* A, double* x, double* y, int transpose)
{
if(transpose == 0){
int i = threadIdx.y + blockDim.y * blockIdx.y;
y[i] = 0;
__shared__ double xs[THREADS_PER_BLOCK];
double tmp = 0;
for(int step=0;step<ceil((double)NY/THREADS_PER_BLOCK);step++){
if(threadIdx.y+step*THREADS_PER_BLOCK>=NY)
xs[threadIdx.y]=0;
else
xs[threadIdx.y]=x[threadIdx.y+step*THREADS_PER_BLOCK];
__syncthreads();
for (int j = 0; j < THREADS_PER_BLOCK; j++)
tmp = tmp + A[i*NY + j + step*THREADS_PER_BLOCK] * xs[j];
__syncthreads();
}
y[i] = tmp;
}else{
int j = threadIdx.y + blockDim.y * blockIdx.y;
if(j<NY){
y[j] = 0;
double tmp = 0;
for (int i = 0; i < NX; i++)
tmp = tmp + A[j + i*NY] * x[i];
y[j] = tmp;
}
}
}
int main(int argc, char *argv[])
{
//Serial program variables
double *y;
//Host and Device variables for CUDA
double *A_h;
double *x_h;
double *y_h;
double *tmp_h;
double *A_d;
double *x_d;
double *y_d;
double *tmp_d;
struct timeval start, end;
//Variables for shared memory implementation
double *A_s;
double *x_s;
double *y_s;
double *tmp_s;
A_h = (double*)malloc(NX*NY*sizeof(double));
x_h = (double*)malloc(NY*sizeof(double));
y_h = (double*)malloc(NY*sizeof(double));
tmp_h = (double*)malloc(NX*sizeof(double));
y = (double*)malloc(NY*sizeof(double));
init_array(x_h, A_h);
cudaMalloc((void**)&A_d, NX*NY*sizeof(double));
cudaMalloc((void**)&x_d, NY*sizeof(double));
cudaMalloc((void**)&y_d, NY*sizeof(double));
cudaMalloc((void**)&tmp_d, NX*sizeof(double));
cudaMalloc((void**)&A_s, NX*NY*sizeof(double));
cudaMalloc((void**)&x_s, NY*sizeof(double));
cudaMalloc((void**)&y_s, NY*sizeof(double));
cudaMalloc((void**)&tmp_s, NX*sizeof(double));
fprintf(stdout, "NX: %d NY: %d\n", NX, NY);
const unsigned int numBlocksInCol= ceil((double)NX/THREADS_PER_BLOCK);
const unsigned int numBlocksInRow= ceil((double)NY/THREADS_PER_BLOCK);
dim3 gridDim(1, numBlocksInCol, 1), blockDim(1, THREADS_PER_BLOCK, 1);
dim3 gridDimT(1, numBlocksInRow, 1);
//Start of CUDA code
gettimeofday(&start, NULL);
cudaMemcpy(A_d, A_h, NX*NY*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(x_d, x_h, NY*sizeof(double), cudaMemcpyHostToDevice);
trans_norm_vector_kernel <<< gridDim, blockDim >>>(A_d, x_d, tmp_d, 0);
trans_norm_vector_kernel <<< gridDimT, blockDim >>>(A_d, tmp_d, y_d, 1);
cudaMemcpy(y_h, y_d , sizeof(double)*NY, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
gettimeofday(&end, NULL);
fprintf(stdout, "GPU Runtime :%0.6lfs\n", ((end.tv_sec - start.tv_sec) * 1000000.0 + (end.tv_usec - start.tv_usec)) / 1000000.0);
//Start of CUDA shared code
gettimeofday(&start, NULL);
cudaMemcpy(A_s, A_h, NX*NY*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(x_s, x_h, NY*sizeof(double), cudaMemcpyHostToDevice);
trans_norm_vector_shared <<< gridDim, blockDim >>>(A_s, x_s, tmp_s, 0);
trans_norm_vector_shared <<< gridDimT, blockDim >>>(A_s, tmp_s, y_s, 1);
cudaMemcpy(y_h, y_s , sizeof(double)*NY, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
gettimeofday(&end, NULL);
fprintf(stdout, "GPU Shared Runtime :%0.6lfs\n", ((end.tv_sec - start.tv_sec) * 1000000.0 + (end.tv_usec - start.tv_usec)) / 1000000.0);
//Start of Serial code
gettimeofday(&start, NULL);
trans_norm_vector(A_h, x_h, y, tmp_h);
gettimeofday(&end, NULL);
fprintf(stdout, "CPU Runtime :%0.6lfs\n", ((end.tv_sec - start.tv_sec) * 1000000.0 + (end.tv_usec - start.tv_usec)) / 1000000.0);
//Error checking CUDA results according to Serial results
int errors = 0;
for (int i = 0; i < NY; ++i) {
double error=fabs((y[i] -y_h[i])/y[i]);
if(error>pow(10,-14)){
printf("Error %.20f in (%d)\n",error,i);
errors++;
}
}
printf("Vector\n\tTotal Results: %d\n\tError count: %d\n",NX*NY,errors);
free(A_h);
free(x_h);
free(y_h);
free(tmp_h);
cudaFree(A_s);
cudaFree(x_s);
cudaFree(y_s);
cudaFree(tmp_s);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <unistd.h>
#include <sys/time.h>
/* Problem size. */
#define NX 5000
#define NY 5000
#ifndef M_PI
#define M_PI 3.14159
#endif
const unsigned int THREADS_PER_BLOCK = 32;
void init_array(double *x, double *A)
{
int i, j;
for (i = 0; i < NX; i++) {
for (j = 0; j < NY; j++) {
A[i*NY + j] = ((double) i*(j)) / NX;
}
}
for (i = 0; i < NY; i++) {
x[i] = i * M_PI;
}
}
void trans_norm_vector(double* A, double* x, double* y, double* tmp)
{
int i,j;
for (i= 0; i < NY; i++) {
y[i] = 0;
}
for (i = 0; i < NX; i++) {
tmp[i] = 0;
for (j = 0; j < NY; j++) {
tmp[i] = tmp[i] + A[i*NY + j] * x[j];
}
for (j = 0; j < NY; j++) {
y[j] = y[j] + A[i*NY + j] * tmp[i];
}
}
}
__global__ void trans_norm_vector_kernel(double* A, double* x, double* y, int transpose)
{
if(transpose == 0){
int i = threadIdx.y + blockDim.y * blockIdx.y;
if(i<NX){
y[i] = 0;
double tmp = 0;
for (int j = 0; j < NY; j++)
tmp = tmp + A[i*NY + j] * x[j];
y[i] = tmp;
}
}else{
int j = threadIdx.y + blockDim.y * blockIdx.y;
if(j<NY){
y[j] = 0;
double tmp = 0;
for (int i = 0; i < NX; i++)
tmp = tmp + A[j + i*NY] * x[i];
y[j] = tmp;
}
}
}
__global__ void trans_norm_vector_shared(double* A, double* x, double* y, int transpose)
{
if(transpose == 0){
int i = threadIdx.y + blockDim.y * blockIdx.y;
y[i] = 0;
__shared__ double xs[THREADS_PER_BLOCK];
double tmp = 0;
for(int step=0;step<ceil((double)NY/THREADS_PER_BLOCK);step++){
if(threadIdx.y+step*THREADS_PER_BLOCK>=NY)
xs[threadIdx.y]=0;
else
xs[threadIdx.y]=x[threadIdx.y+step*THREADS_PER_BLOCK];
__syncthreads();
for (int j = 0; j < THREADS_PER_BLOCK; j++)
tmp = tmp + A[i*NY + j + step*THREADS_PER_BLOCK] * xs[j];
__syncthreads();
}
y[i] = tmp;
}else{
int j = threadIdx.y + blockDim.y * blockIdx.y;
if(j<NY){
y[j] = 0;
double tmp = 0;
for (int i = 0; i < NX; i++)
tmp = tmp + A[j + i*NY] * x[i];
y[j] = tmp;
}
}
}
int main(int argc, char *argv[])
{
//Serial program variables
double *y;
//Host and Device variables for CUDA
double *A_h;
double *x_h;
double *y_h;
double *tmp_h;
double *A_d;
double *x_d;
double *y_d;
double *tmp_d;
struct timeval start, end;
//Variables for shared memory implementation
double *A_s;
double *x_s;
double *y_s;
double *tmp_s;
A_h = (double*)malloc(NX*NY*sizeof(double));
x_h = (double*)malloc(NY*sizeof(double));
y_h = (double*)malloc(NY*sizeof(double));
tmp_h = (double*)malloc(NX*sizeof(double));
y = (double*)malloc(NY*sizeof(double));
init_array(x_h, A_h);
hipMalloc((void**)&A_d, NX*NY*sizeof(double));
hipMalloc((void**)&x_d, NY*sizeof(double));
hipMalloc((void**)&y_d, NY*sizeof(double));
hipMalloc((void**)&tmp_d, NX*sizeof(double));
hipMalloc((void**)&A_s, NX*NY*sizeof(double));
hipMalloc((void**)&x_s, NY*sizeof(double));
hipMalloc((void**)&y_s, NY*sizeof(double));
hipMalloc((void**)&tmp_s, NX*sizeof(double));
fprintf(stdout, "NX: %d NY: %d\n", NX, NY);
const unsigned int numBlocksInCol= ceil((double)NX/THREADS_PER_BLOCK);
const unsigned int numBlocksInRow= ceil((double)NY/THREADS_PER_BLOCK);
dim3 gridDim(1, numBlocksInCol, 1), blockDim(1, THREADS_PER_BLOCK, 1);
dim3 gridDimT(1, numBlocksInRow, 1);
//Start of CUDA code
gettimeofday(&start, NULL);
hipMemcpy(A_d, A_h, NX*NY*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(x_d, x_h, NY*sizeof(double), hipMemcpyHostToDevice);
trans_norm_vector_kernel <<< gridDim, blockDim >>>(A_d, x_d, tmp_d, 0);
trans_norm_vector_kernel <<< gridDimT, blockDim >>>(A_d, tmp_d, y_d, 1);
hipMemcpy(y_h, y_d , sizeof(double)*NY, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
gettimeofday(&end, NULL);
fprintf(stdout, "GPU Runtime :%0.6lfs\n", ((end.tv_sec - start.tv_sec) * 1000000.0 + (end.tv_usec - start.tv_usec)) / 1000000.0);
//Start of CUDA shared code
gettimeofday(&start, NULL);
hipMemcpy(A_s, A_h, NX*NY*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(x_s, x_h, NY*sizeof(double), hipMemcpyHostToDevice);
trans_norm_vector_shared <<< gridDim, blockDim >>>(A_s, x_s, tmp_s, 0);
trans_norm_vector_shared <<< gridDimT, blockDim >>>(A_s, tmp_s, y_s, 1);
hipMemcpy(y_h, y_s , sizeof(double)*NY, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
gettimeofday(&end, NULL);
fprintf(stdout, "GPU Shared Runtime :%0.6lfs\n", ((end.tv_sec - start.tv_sec) * 1000000.0 + (end.tv_usec - start.tv_usec)) / 1000000.0);
//Start of Serial code
gettimeofday(&start, NULL);
trans_norm_vector(A_h, x_h, y, tmp_h);
gettimeofday(&end, NULL);
fprintf(stdout, "CPU Runtime :%0.6lfs\n", ((end.tv_sec - start.tv_sec) * 1000000.0 + (end.tv_usec - start.tv_usec)) / 1000000.0);
//Error checking CUDA results according to Serial results
int errors = 0;
for (int i = 0; i < NY; ++i) {
double error=fabs((y[i] -y_h[i])/y[i]);
if(error>pow(10,-14)){
printf("Error %.20f in (%d)\n",error,i);
errors++;
}
}
printf("Vector\n\tTotal Results: %d\n\tError count: %d\n",NX*NY,errors);
free(A_h);
free(x_h);
free(y_h);
free(tmp_h);
hipFree(A_s);
hipFree(x_s);
hipFree(y_s);
hipFree(tmp_s);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <unistd.h>
#include <sys/time.h>
/* Problem size. */
#define NX 5000
#define NY 5000
#ifndef M_PI
#define M_PI 3.14159
#endif
const unsigned int THREADS_PER_BLOCK = 32;
void init_array(double *x, double *A)
{
int i, j;
for (i = 0; i < NX; i++) {
for (j = 0; j < NY; j++) {
A[i*NY + j] = ((double) i*(j)) / NX;
}
}
for (i = 0; i < NY; i++) {
x[i] = i * M_PI;
}
}
void trans_norm_vector(double* A, double* x, double* y, double* tmp)
{
int i,j;
for (i= 0; i < NY; i++) {
y[i] = 0;
}
for (i = 0; i < NX; i++) {
tmp[i] = 0;
for (j = 0; j < NY; j++) {
tmp[i] = tmp[i] + A[i*NY + j] * x[j];
}
for (j = 0; j < NY; j++) {
y[j] = y[j] + A[i*NY + j] * tmp[i];
}
}
}
__global__ void trans_norm_vector_kernel(double* A, double* x, double* y, int transpose)
{
if(transpose == 0){
int i = threadIdx.y + blockDim.y * blockIdx.y;
if(i<NX){
y[i] = 0;
double tmp = 0;
for (int j = 0; j < NY; j++)
tmp = tmp + A[i*NY + j] * x[j];
y[i] = tmp;
}
}else{
int j = threadIdx.y + blockDim.y * blockIdx.y;
if(j<NY){
y[j] = 0;
double tmp = 0;
for (int i = 0; i < NX; i++)
tmp = tmp + A[j + i*NY] * x[i];
y[j] = tmp;
}
}
}
__global__ void trans_norm_vector_shared(double* A, double* x, double* y, int transpose)
{
if(transpose == 0){
int i = threadIdx.y + blockDim.y * blockIdx.y;
y[i] = 0;
__shared__ double xs[THREADS_PER_BLOCK];
double tmp = 0;
for(int step=0;step<ceil((double)NY/THREADS_PER_BLOCK);step++){
if(threadIdx.y+step*THREADS_PER_BLOCK>=NY)
xs[threadIdx.y]=0;
else
xs[threadIdx.y]=x[threadIdx.y+step*THREADS_PER_BLOCK];
__syncthreads();
for (int j = 0; j < THREADS_PER_BLOCK; j++)
tmp = tmp + A[i*NY + j + step*THREADS_PER_BLOCK] * xs[j];
__syncthreads();
}
y[i] = tmp;
}else{
int j = threadIdx.y + blockDim.y * blockIdx.y;
if(j<NY){
y[j] = 0;
double tmp = 0;
for (int i = 0; i < NX; i++)
tmp = tmp + A[j + i*NY] * x[i];
y[j] = tmp;
}
}
}
int main(int argc, char *argv[])
{
//Serial program variables
double *y;
//Host and Device variables for CUDA
double *A_h;
double *x_h;
double *y_h;
double *tmp_h;
double *A_d;
double *x_d;
double *y_d;
double *tmp_d;
struct timeval start, end;
//Variables for shared memory implementation
double *A_s;
double *x_s;
double *y_s;
double *tmp_s;
A_h = (double*)malloc(NX*NY*sizeof(double));
x_h = (double*)malloc(NY*sizeof(double));
y_h = (double*)malloc(NY*sizeof(double));
tmp_h = (double*)malloc(NX*sizeof(double));
y = (double*)malloc(NY*sizeof(double));
init_array(x_h, A_h);
hipMalloc((void**)&A_d, NX*NY*sizeof(double));
hipMalloc((void**)&x_d, NY*sizeof(double));
hipMalloc((void**)&y_d, NY*sizeof(double));
hipMalloc((void**)&tmp_d, NX*sizeof(double));
hipMalloc((void**)&A_s, NX*NY*sizeof(double));
hipMalloc((void**)&x_s, NY*sizeof(double));
hipMalloc((void**)&y_s, NY*sizeof(double));
hipMalloc((void**)&tmp_s, NX*sizeof(double));
fprintf(stdout, "NX: %d NY: %d\n", NX, NY);
const unsigned int numBlocksInCol= ceil((double)NX/THREADS_PER_BLOCK);
const unsigned int numBlocksInRow= ceil((double)NY/THREADS_PER_BLOCK);
dim3 gridDim(1, numBlocksInCol, 1), blockDim(1, THREADS_PER_BLOCK, 1);
dim3 gridDimT(1, numBlocksInRow, 1);
//Start of CUDA code
gettimeofday(&start, NULL);
hipMemcpy(A_d, A_h, NX*NY*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(x_d, x_h, NY*sizeof(double), hipMemcpyHostToDevice);
trans_norm_vector_kernel <<< gridDim, blockDim >>>(A_d, x_d, tmp_d, 0);
trans_norm_vector_kernel <<< gridDimT, blockDim >>>(A_d, tmp_d, y_d, 1);
hipMemcpy(y_h, y_d , sizeof(double)*NY, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
gettimeofday(&end, NULL);
fprintf(stdout, "GPU Runtime :%0.6lfs\n", ((end.tv_sec - start.tv_sec) * 1000000.0 + (end.tv_usec - start.tv_usec)) / 1000000.0);
//Start of CUDA shared code
gettimeofday(&start, NULL);
hipMemcpy(A_s, A_h, NX*NY*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(x_s, x_h, NY*sizeof(double), hipMemcpyHostToDevice);
trans_norm_vector_shared <<< gridDim, blockDim >>>(A_s, x_s, tmp_s, 0);
trans_norm_vector_shared <<< gridDimT, blockDim >>>(A_s, tmp_s, y_s, 1);
hipMemcpy(y_h, y_s , sizeof(double)*NY, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
gettimeofday(&end, NULL);
fprintf(stdout, "GPU Shared Runtime :%0.6lfs\n", ((end.tv_sec - start.tv_sec) * 1000000.0 + (end.tv_usec - start.tv_usec)) / 1000000.0);
//Start of Serial code
gettimeofday(&start, NULL);
trans_norm_vector(A_h, x_h, y, tmp_h);
gettimeofday(&end, NULL);
fprintf(stdout, "CPU Runtime :%0.6lfs\n", ((end.tv_sec - start.tv_sec) * 1000000.0 + (end.tv_usec - start.tv_usec)) / 1000000.0);
//Error checking CUDA results according to Serial results
int errors = 0;
for (int i = 0; i < NY; ++i) {
double error=fabs((y[i] -y_h[i])/y[i]);
if(error>pow(10,-14)){
printf("Error %.20f in (%d)\n",error,i);
errors++;
}
}
printf("Vector\n\tTotal Results: %d\n\tError count: %d\n",NX*NY,errors);
free(A_h);
free(x_h);
free(y_h);
free(tmp_h);
hipFree(A_s);
hipFree(x_s);
hipFree(y_s);
hipFree(tmp_s);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24trans_norm_vector_kernelPdS_S_i
.globl _Z24trans_norm_vector_kernelPdS_S_i
.p2align 8
.type _Z24trans_norm_vector_kernelPdS_S_i,@function
_Z24trans_norm_vector_kernelPdS_S_i:
s_clause 0x3
s_load_b32 s8, s[0:1], 0x2c
s_load_b32 s9, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s8, 16
s_cmp_lg_u32 s9, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s0, v[2:3]
v_cmp_gt_i32_e64 s0, 0x1388, v0
s_cbranch_scc0 .LBB0_7
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v1, 31, v0
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v7, 0
v_mov_b32_e32 v5, v0
s_mov_b64 s[8:9], 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 3, v[0:1]
v_mov_b32_e32 v1, 0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v9, v8
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_b64 v[3:4], v[8:9], off
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v6, 31, v5
s_add_u32 s10, s6, s8
s_addc_u32 s11, s7, s9
s_add_u32 s8, s8, 8
s_addc_u32 s9, s9, 0
v_lshlrev_b64 v[8:9], 3, v[5:6]
v_add_nc_u32_e32 v5, 0x1388, v5
s_cmpk_eq_u32 s8, 0x9c40
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b64 v[10:11], v7, s[10:11]
global_load_b64 v[8:9], v[8:9], off
s_waitcnt vmcnt(0)
v_fma_f64 v[1:2], v[8:9], v[10:11], v[1:2]
s_cbranch_scc0 .LBB0_3
global_store_b64 v[3:4], v[1:2], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_8
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_7:
.LBB0_8:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mul_lo_u32 v2, v0, 0x1388
v_ashrrev_i32_e32 v1, 31, v0
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v6, 0
s_mov_b64 s[0:1], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 3, v[0:1]
v_mov_b32_e32 v0, 0
v_ashrrev_i32_e32 v3, 31, v2
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v8, v7
v_lshlrev_b64 v[9:10], 3, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v10, vcc_lo
global_store_b64 v[2:3], v[7:8], off
.LBB0_10:
v_add_co_u32 v7, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v5, vcc_lo
s_add_u32 s2, s6, s0
s_addc_u32 s3, s7, s1
global_load_b64 v[9:10], v6, s[2:3]
global_load_b64 v[7:8], v[7:8], off
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
s_cmpk_eq_u32 s0, 0x9c40
s_waitcnt vmcnt(0)
v_fma_f64 v[0:1], v[7:8], v[9:10], v[0:1]
s_cbranch_scc0 .LBB0_10
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24trans_norm_vector_kernelPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24trans_norm_vector_kernelPdS_S_i, .Lfunc_end0-_Z24trans_norm_vector_kernelPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z24trans_norm_vector_sharedPdS_S_i
.globl _Z24trans_norm_vector_sharedPdS_S_i
.p2align 8
.type _Z24trans_norm_vector_sharedPdS_S_i,@function
_Z24trans_norm_vector_sharedPdS_S_i:
s_clause 0x3
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_cbranch_scc0 .LBB1_7
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x1388, v2
s_cbranch_execz .LBB1_5
v_ashrrev_i32_e32 v3, 31, v2
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v1, 0
v_mov_b32_e32 v7, v2
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 3, v[2:3]
v_mov_b32_e32 v3, 0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v9, v8
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_store_b64 v[5:6], v[8:9], off
.p2align 6
.LBB1_3:
v_ashrrev_i32_e32 v8, 31, v7
s_add_u32 s10, s6, s2
s_addc_u32 s11, s7, s3
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
v_lshlrev_b64 v[8:9], 3, v[7:8]
v_add_nc_u32_e32 v7, 0x1388, v7
s_cmpk_eq_u32 s2, 0x9c40
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b64 v[10:11], v1, s[10:11]
global_load_b64 v[8:9], v[8:9], off
s_waitcnt vmcnt(0)
v_fma_f64 v[3:4], v[8:9], v[10:11], v[3:4]
s_cbranch_scc0 .LBB1_3
global_store_b64 v[5:6], v[3:4], off
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB1_8
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB1_7:
.LBB1_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v10, 3, v0
v_mul_lo_u32 v9, v2, 0x1388
v_mov_b32_e32 v8, 0
v_lshlrev_b64 v[3:4], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v5, 0
v_mov_b32_e32 v6, 0
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_mov_b32 s0, 0
global_store_b64 v[3:4], v[1:2], off
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_9:
v_lshl_add_u32 v7, s0, 5, v0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0x1388, v7
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB1_11
v_lshlrev_b64 v[11:12], 3, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b64 v[11:12], v[11:12], off
s_waitcnt vmcnt(0)
ds_store_b64 v10, v[11:12]
.LBB1_11:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB1_13
v_mov_b32_e32 v2, v1
ds_store_b64 v10, v[1:2]
.LBB1_13:
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v7, v9
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB1_14:
v_lshlrev_b64 v[11:12], 3, v[7:8]
v_dual_mov_b32 v2, s1 :: v_dual_add_nc_u32 v7, 1, v7
s_add_i32 s1, s1, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmpk_eq_i32 s1, 0x100
v_add_co_u32 v11, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
ds_load_b64 v[13:14], v2
global_load_b64 v[11:12], v[11:12], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[5:6], v[11:12], v[13:14], v[5:6]
s_cbranch_scc0 .LBB1_14
v_add_nc_u32_e32 v9, 32, v9
s_add_i32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s0, 0x9d
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_9
s_set_inst_prefetch_distance 0x2
global_store_b64 v[3:4], v[5:6], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24trans_norm_vector_sharedPdS_S_i
.amdhsa_group_segment_fixed_size 256
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z24trans_norm_vector_sharedPdS_S_i, .Lfunc_end1-_Z24trans_norm_vector_sharedPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24trans_norm_vector_kernelPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24trans_norm_vector_kernelPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 256
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24trans_norm_vector_sharedPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24trans_norm_vector_sharedPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <unistd.h>
#include <sys/time.h>
/* Problem size. */
#define NX 5000
#define NY 5000
#ifndef M_PI
#define M_PI 3.14159
#endif
const unsigned int THREADS_PER_BLOCK = 32;
void init_array(double *x, double *A)
{
int i, j;
for (i = 0; i < NX; i++) {
for (j = 0; j < NY; j++) {
A[i*NY + j] = ((double) i*(j)) / NX;
}
}
for (i = 0; i < NY; i++) {
x[i] = i * M_PI;
}
}
void trans_norm_vector(double* A, double* x, double* y, double* tmp)
{
int i,j;
for (i= 0; i < NY; i++) {
y[i] = 0;
}
for (i = 0; i < NX; i++) {
tmp[i] = 0;
for (j = 0; j < NY; j++) {
tmp[i] = tmp[i] + A[i*NY + j] * x[j];
}
for (j = 0; j < NY; j++) {
y[j] = y[j] + A[i*NY + j] * tmp[i];
}
}
}
__global__ void trans_norm_vector_kernel(double* A, double* x, double* y, int transpose)
{
if(transpose == 0){
int i = threadIdx.y + blockDim.y * blockIdx.y;
if(i<NX){
y[i] = 0;
double tmp = 0;
for (int j = 0; j < NY; j++)
tmp = tmp + A[i*NY + j] * x[j];
y[i] = tmp;
}
}else{
int j = threadIdx.y + blockDim.y * blockIdx.y;
if(j<NY){
y[j] = 0;
double tmp = 0;
for (int i = 0; i < NX; i++)
tmp = tmp + A[j + i*NY] * x[i];
y[j] = tmp;
}
}
}
__global__ void trans_norm_vector_shared(double* A, double* x, double* y, int transpose)
{
if(transpose == 0){
int i = threadIdx.y + blockDim.y * blockIdx.y;
y[i] = 0;
__shared__ double xs[THREADS_PER_BLOCK];
double tmp = 0;
for(int step=0;step<ceil((double)NY/THREADS_PER_BLOCK);step++){
if(threadIdx.y+step*THREADS_PER_BLOCK>=NY)
xs[threadIdx.y]=0;
else
xs[threadIdx.y]=x[threadIdx.y+step*THREADS_PER_BLOCK];
__syncthreads();
for (int j = 0; j < THREADS_PER_BLOCK; j++)
tmp = tmp + A[i*NY + j + step*THREADS_PER_BLOCK] * xs[j];
__syncthreads();
}
y[i] = tmp;
}else{
int j = threadIdx.y + blockDim.y * blockIdx.y;
if(j<NY){
y[j] = 0;
double tmp = 0;
for (int i = 0; i < NX; i++)
tmp = tmp + A[j + i*NY] * x[i];
y[j] = tmp;
}
}
}
int main(int argc, char *argv[])
{
//Serial program variables
double *y;
//Host and Device variables for CUDA
double *A_h;
double *x_h;
double *y_h;
double *tmp_h;
double *A_d;
double *x_d;
double *y_d;
double *tmp_d;
struct timeval start, end;
//Variables for shared memory implementation
double *A_s;
double *x_s;
double *y_s;
double *tmp_s;
A_h = (double*)malloc(NX*NY*sizeof(double));
x_h = (double*)malloc(NY*sizeof(double));
y_h = (double*)malloc(NY*sizeof(double));
tmp_h = (double*)malloc(NX*sizeof(double));
y = (double*)malloc(NY*sizeof(double));
init_array(x_h, A_h);
hipMalloc((void**)&A_d, NX*NY*sizeof(double));
hipMalloc((void**)&x_d, NY*sizeof(double));
hipMalloc((void**)&y_d, NY*sizeof(double));
hipMalloc((void**)&tmp_d, NX*sizeof(double));
hipMalloc((void**)&A_s, NX*NY*sizeof(double));
hipMalloc((void**)&x_s, NY*sizeof(double));
hipMalloc((void**)&y_s, NY*sizeof(double));
hipMalloc((void**)&tmp_s, NX*sizeof(double));
fprintf(stdout, "NX: %d NY: %d\n", NX, NY);
const unsigned int numBlocksInCol= ceil((double)NX/THREADS_PER_BLOCK);
const unsigned int numBlocksInRow= ceil((double)NY/THREADS_PER_BLOCK);
dim3 gridDim(1, numBlocksInCol, 1), blockDim(1, THREADS_PER_BLOCK, 1);
dim3 gridDimT(1, numBlocksInRow, 1);
//Start of CUDA code
gettimeofday(&start, NULL);
hipMemcpy(A_d, A_h, NX*NY*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(x_d, x_h, NY*sizeof(double), hipMemcpyHostToDevice);
trans_norm_vector_kernel <<< gridDim, blockDim >>>(A_d, x_d, tmp_d, 0);
trans_norm_vector_kernel <<< gridDimT, blockDim >>>(A_d, tmp_d, y_d, 1);
hipMemcpy(y_h, y_d , sizeof(double)*NY, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
gettimeofday(&end, NULL);
fprintf(stdout, "GPU Runtime :%0.6lfs\n", ((end.tv_sec - start.tv_sec) * 1000000.0 + (end.tv_usec - start.tv_usec)) / 1000000.0);
//Start of CUDA shared code
gettimeofday(&start, NULL);
hipMemcpy(A_s, A_h, NX*NY*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(x_s, x_h, NY*sizeof(double), hipMemcpyHostToDevice);
trans_norm_vector_shared <<< gridDim, blockDim >>>(A_s, x_s, tmp_s, 0);
trans_norm_vector_shared <<< gridDimT, blockDim >>>(A_s, tmp_s, y_s, 1);
hipMemcpy(y_h, y_s , sizeof(double)*NY, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
gettimeofday(&end, NULL);
fprintf(stdout, "GPU Shared Runtime :%0.6lfs\n", ((end.tv_sec - start.tv_sec) * 1000000.0 + (end.tv_usec - start.tv_usec)) / 1000000.0);
//Start of Serial code
gettimeofday(&start, NULL);
trans_norm_vector(A_h, x_h, y, tmp_h);
gettimeofday(&end, NULL);
fprintf(stdout, "CPU Runtime :%0.6lfs\n", ((end.tv_sec - start.tv_sec) * 1000000.0 + (end.tv_usec - start.tv_usec)) / 1000000.0);
//Error checking CUDA results according to Serial results
int errors = 0;
for (int i = 0; i < NY; ++i) {
double error=fabs((y[i] -y_h[i])/y[i]);
if(error>pow(10,-14)){
printf("Error %.20f in (%d)\n",error,i);
errors++;
}
}
printf("Vector\n\tTotal Results: %d\n\tError count: %d\n",NX*NY,errors);
free(A_h);
free(x_h);
free(y_h);
free(tmp_h);
hipFree(A_s);
hipFree(x_s);
hipFree(y_s);
hipFree(tmp_s);
return 0;
} | .text
.file "TransNormVector.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10init_arrayPdS_
.LCPI0_0:
.quad 0x40b3880000000000 # double 5000
.LCPI0_1:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.text
.globl _Z10init_arrayPdS_
.p2align 4, 0x90
.type _Z10init_arrayPdS_,@function
_Z10init_arrayPdS_: # @_Z10init_arrayPdS_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB0_1: # %.preheader14
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm2, %xmm2
cvtsi2sd %ecx, %xmm2
mulsd %xmm1, %xmm2
divsd %xmm0, %xmm2
movsd %xmm2, (%rsi,%rcx,8)
incq %rcx
cmpq $5000, %rcx # imm = 0x1388
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rax
addq $40000, %rsi # imm = 0x9C40
cmpq $5000, %rax # imm = 0x1388
jne .LBB0_1
# %bb.4: # %.preheader.preheader
xorl %eax, %eax
movsd .LCPI0_1(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB0_5: # %.preheader
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm0, %xmm1
movsd %xmm1, (%rdi,%rax,8)
incq %rax
cmpq $5000, %rax # imm = 0x1388
jne .LBB0_5
# %bb.6:
retq
.Lfunc_end0:
.size _Z10init_arrayPdS_, .Lfunc_end0-_Z10init_arrayPdS_
.cfi_endproc
# -- End function
.globl _Z17trans_norm_vectorPdS_S_S_ # -- Begin function _Z17trans_norm_vectorPdS_S_S_
.p2align 4, 0x90
.type _Z17trans_norm_vectorPdS_S_S_,@function
_Z17trans_norm_vectorPdS_S_S_: # @_Z17trans_norm_vectorPdS_S_S_
.cfi_startproc
# %bb.0: # %.preheader31.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
xorl %r13d, %r13d
movl $40000, %edx # imm = 0x9C40
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # %.preheader31
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
# Child Loop BB1_4 Depth 2
movq $0, (%rbx,%r13,8)
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r12,%rax,8), %xmm1 # xmm1 = mem[0],zero
mulsd (%r15,%rax,8), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, (%rbx,%r13,8)
incq %rax
cmpq $5000, %rax # imm = 0x1388
jne .LBB1_2
# %bb.3: # %.preheader
# in Loop: Header=BB1_1 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r12,%rax,8), %xmm0 # xmm0 = mem[0],zero
mulsd (%rbx,%r13,8), %xmm0
addsd (%r14,%rax,8), %xmm0
movsd %xmm0, (%r14,%rax,8)
incq %rax
cmpq $5000, %rax # imm = 0x1388
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_1 Depth=1
incq %r13
addq $40000, %r12 # imm = 0x9C40
cmpq $5000, %r13 # imm = 0x1388
jne .LBB1_1
# %bb.6:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z17trans_norm_vectorPdS_S_S_, .Lfunc_end1-_Z17trans_norm_vectorPdS_S_S_
.cfi_endproc
# -- End function
.globl _Z39__device_stub__trans_norm_vector_kernelPdS_S_i # -- Begin function _Z39__device_stub__trans_norm_vector_kernelPdS_S_i
.p2align 4, 0x90
.type _Z39__device_stub__trans_norm_vector_kernelPdS_S_i,@function
_Z39__device_stub__trans_norm_vector_kernelPdS_S_i: # @_Z39__device_stub__trans_norm_vector_kernelPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24trans_norm_vector_kernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z39__device_stub__trans_norm_vector_kernelPdS_S_i, .Lfunc_end2-_Z39__device_stub__trans_norm_vector_kernelPdS_S_i
.cfi_endproc
# -- End function
.globl _Z39__device_stub__trans_norm_vector_sharedPdS_S_i # -- Begin function _Z39__device_stub__trans_norm_vector_sharedPdS_S_i
.p2align 4, 0x90
.type _Z39__device_stub__trans_norm_vector_sharedPdS_S_i,@function
_Z39__device_stub__trans_norm_vector_sharedPdS_S_i: # @_Z39__device_stub__trans_norm_vector_sharedPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24trans_norm_vector_sharedPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z39__device_stub__trans_norm_vector_sharedPdS_S_i, .Lfunc_end3-_Z39__device_stub__trans_norm_vector_sharedPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x40b3880000000000 # double 5000
.LCPI4_1:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI4_2:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI4_4:
.quad 0x3d06849b86a12b9b # double 9.9999999999999999E-15
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI4_3:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $200000000, %edi # imm = 0xBEBC200
callq malloc
movq %rax, %rbx
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r14
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r15
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r12
xorl %eax, %eax
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
movq %rbx, %rcx
.p2align 4, 0x90
.LBB4_1: # %.preheader14.i
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm2, %xmm2
cvtsi2sd %edx, %xmm2
mulsd %xmm1, %xmm2
divsd %xmm0, %xmm2
movsd %xmm2, (%rcx,%rdx,8)
incq %rdx
cmpq $5000, %rdx # imm = 0x1388
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %rax
addq $40000, %rcx # imm = 0x9C40
cmpq $5000, %rax # imm = 0x1388
jne .LBB4_1
# %bb.4: # %.preheader.i.preheader
xorl %eax, %eax
movsd .LCPI4_1(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB4_5: # %.preheader.i
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm0, %xmm1
movsd %xmm1, (%r14,%rax,8)
incq %rax
cmpq $5000, %rax # imm = 0x1388
jne .LBB4_5
# %bb.6: # %_Z10init_arrayPdS_.exit
movabsq $674309865473, %rbp # imm = 0x9D00000001
movabsq $137438953473, %r13 # imm = 0x2000000001
leaq 184(%rsp), %rdi
movl $200000000, %esi # imm = 0xBEBC200
callq hipMalloc
leaq 208(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 200(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 192(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 136(%rsp), %rdi
movl $200000000, %esi # imm = 0xBEBC200
callq hipMalloc
leaq 176(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 168(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 160(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq stdout(%rip), %rdi
movl $.L.str, %esi
movl $5000, %edx # imm = 0x1388
movl $5000, %ecx # imm = 0x1388
xorl %eax, %eax
callq fprintf
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 184(%rsp), %rdi
movl $200000000, %edx # imm = 0xBEBC200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 208(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 184(%rsp), %rax
movq 208(%rsp), %rcx
movq 192(%rsp), %rdx
movq %rax, 80(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 40(%rsp)
movl $0, (%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24trans_norm_vector_kernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_10
# %bb.9:
movq 184(%rsp), %rax
movq 192(%rsp), %rcx
movq 200(%rsp), %rdx
movq %rax, 80(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 40(%rsp)
movl $1, (%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24trans_norm_vector_kernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_10:
movq 200(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq stdout(%rip), %rdi
movq 64(%rsp), %rax
movq 72(%rsp), %rcx
subq 144(%rsp), %rax
cvtsi2sd %rax, %xmm1
movsd .LCPI4_2(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
subq 152(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
addsd %xmm1, %xmm0
divsd %xmm2, %xmm0
movl $.L.str.1, %esi
movb $1, %al
callq fprintf
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 136(%rsp), %rdi
movl $200000000, %edx # imm = 0xBEBC200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 176(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_12
# %bb.11:
movq 136(%rsp), %rax
movq 176(%rsp), %rcx
movq 160(%rsp), %rdx
movq %rax, 48(%rsp)
movq %rcx, 40(%rsp)
movq %rdx, 32(%rsp)
movl $0, 60(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 60(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24trans_norm_vector_sharedPdS_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_12:
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_14
# %bb.13:
movq 136(%rsp), %rax
movq 160(%rsp), %rcx
movq 168(%rsp), %rdx
movq %rax, 48(%rsp)
movq %rcx, 40(%rsp)
movq %rdx, 32(%rsp)
movl $1, 60(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 60(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24trans_norm_vector_sharedPdS_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_14:
movq 168(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
xorl %r13d, %r13d
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq stdout(%rip), %rdi
movq 64(%rsp), %rax
subq 144(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
movq 72(%rsp), %rax
movsd .LCPI4_2(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
subq 152(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm1, %xmm0
divsd %xmm2, %xmm0
movl $.L.str.2, %esi
movb $1, %al
callq fprintf
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $40000, %edx # imm = 0x9C40
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
movq %rbx, %rax
.p2align 4, 0x90
.LBB4_15: # %.preheader31.i
# =>This Loop Header: Depth=1
# Child Loop BB4_16 Depth 2
# Child Loop BB4_18 Depth 2
xorpd %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_16: # Parent Loop BB4_15 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rax,%rcx,8), %xmm1 # xmm1 = mem[0],zero
mulsd (%r14,%rcx,8), %xmm1
addsd %xmm1, %xmm0
incq %rcx
cmpq $5000, %rcx # imm = 0x1388
jne .LBB4_16
# %bb.17: # %.preheader.i86.preheader
# in Loop: Header=BB4_15 Depth=1
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_18: # %.preheader.i86
# Parent Loop BB4_15 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rax,%rcx,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
addsd (%r12,%rcx,8), %xmm1
movsd %xmm1, (%r12,%rcx,8)
incq %rcx
cmpq $5000, %rcx # imm = 0x1388
jne .LBB4_18
# %bb.19: # in Loop: Header=BB4_15 Depth=1
incq %r13
addq $40000, %rax # imm = 0x9C40
cmpq $5000, %r13 # imm = 0x1388
jne .LBB4_15
# %bb.20: # %_Z17trans_norm_vectorPdS_S_S_.exit
xorl %r13d, %r13d
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq stdout(%rip), %rdi
movq 64(%rsp), %rax
subq 144(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
movq 72(%rsp), %rax
movsd .LCPI4_2(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
subq 152(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm1, %xmm0
divsd %xmm2, %xmm0
movl $.L.str.3, %esi
movb $1, %al
callq fprintf
movapd .LCPI4_3(%rip), %xmm2 # xmm2 = [NaN,NaN]
movsd .LCPI4_4(%rip), %xmm3 # xmm3 = mem[0],zero
xorl %ebp, %ebp
jmp .LBB4_21
.p2align 4, 0x90
.LBB4_23: # in Loop: Header=BB4_21 Depth=1
incq %r13
cmpq $5000, %r13 # imm = 0x1388
je .LBB4_24
.LBB4_21: # =>This Inner Loop Header: Depth=1
movsd (%r12,%r13,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm1, %xmm0
subsd (%r15,%r13,8), %xmm0
divsd %xmm1, %xmm0
andpd %xmm2, %xmm0
ucomisd %xmm3, %xmm0
jbe .LBB4_23
# %bb.22: # in Loop: Header=BB4_21 Depth=1
movl $.L.str.4, %edi
movl %r13d, %esi
movb $1, %al
callq printf
movsd .LCPI4_4(%rip), %xmm3 # xmm3 = mem[0],zero
movapd .LCPI4_3(%rip), %xmm2 # xmm2 = [NaN,NaN]
incl %ebp
jmp .LBB4_23
.LBB4_24:
movl $.L.str.5, %edi
movl $25000000, %esi # imm = 0x17D7840
movl %ebp, %edx
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 136(%rsp), %rdi
callq hipFree
movq 176(%rsp), %rdi
callq hipFree
movq 168(%rsp), %rdi
callq hipFree
movq 160(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24trans_norm_vector_kernelPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24trans_norm_vector_sharedPdS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24trans_norm_vector_kernelPdS_S_i,@object # @_Z24trans_norm_vector_kernelPdS_S_i
.section .rodata,"a",@progbits
.globl _Z24trans_norm_vector_kernelPdS_S_i
.p2align 3, 0x0
_Z24trans_norm_vector_kernelPdS_S_i:
.quad _Z39__device_stub__trans_norm_vector_kernelPdS_S_i
.size _Z24trans_norm_vector_kernelPdS_S_i, 8
.type _Z24trans_norm_vector_sharedPdS_S_i,@object # @_Z24trans_norm_vector_sharedPdS_S_i
.globl _Z24trans_norm_vector_sharedPdS_S_i
.p2align 3, 0x0
_Z24trans_norm_vector_sharedPdS_S_i:
.quad _Z39__device_stub__trans_norm_vector_sharedPdS_S_i
.size _Z24trans_norm_vector_sharedPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "NX: %d NY: %d\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU Runtime :%0.6lfs\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPU Shared Runtime :%0.6lfs\n"
.size .L.str.2, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CPU Runtime :%0.6lfs\n"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error %.20f in (%d)\n"
.size .L.str.4, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Vector\n\tTotal Results: %d\n\tError count: %d\n"
.size .L.str.5, 44
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24trans_norm_vector_kernelPdS_S_i"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z24trans_norm_vector_sharedPdS_S_i"
.size .L__unnamed_2, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__trans_norm_vector_kernelPdS_S_i
.addrsig_sym _Z39__device_stub__trans_norm_vector_sharedPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24trans_norm_vector_kernelPdS_S_i
.addrsig_sym _Z24trans_norm_vector_sharedPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003ccb2_00000000-6_TransNormVector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10init_arrayPdS_
.type _Z10init_arrayPdS_, @function
_Z10init_arrayPdS_:
.LFB2070:
.cfi_startproc
endbr64
movq %rsi, %rdx
movl $0, %ecx
movsd .LC0(%rip), %xmm2
.L4:
movl $0, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %ecx, %xmm1
.L5:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm1, %xmm0
divsd %xmm2, %xmm0
movsd %xmm0, (%rdx,%rax,8)
addq $1, %rax
cmpq $5000, %rax
jne .L5
addl $1, %ecx
addq $40000, %rdx
cmpl $5000, %ecx
jne .L4
movl $0, %eax
movsd .LC1(%rip), %xmm1
.L6:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm1, %xmm0
movsd %xmm0, (%rdi,%rax,8)
addq $1, %rax
cmpq $5000, %rax
jne .L6
ret
.cfi_endproc
.LFE2070:
.size _Z10init_arrayPdS_, .-_Z10init_arrayPdS_
.globl _Z17trans_norm_vectorPdS_S_S_
.type _Z17trans_norm_vectorPdS_S_S_, @function
_Z17trans_norm_vectorPdS_S_S_:
.LFB2071:
.cfi_startproc
endbr64
movq %rdi, %rax
movq %rsi, %r8
movq %rdx, %rsi
movq %rcx, %r9
leaq 40000(%rdx), %rcx
.L11:
movq $0x000000000, (%rdx)
addq $8, %rdx
cmpq %rcx, %rdx
jne .L11
movq %rax, %rcx
movl $0, %r10d
.L14:
movq %r9, %rdx
movq $0x000000000, (%r9)
movl $0, %eax
movq %rcx, %rdi
.L12:
movsd (%rcx,%rax), %xmm0
mulsd (%r8,%rax), %xmm0
addsd (%rdx), %xmm0
movsd %xmm0, (%rdx)
addq $8, %rax
cmpq $40000, %rax
jne .L12
movl $0, %eax
.L13:
movsd (%rdi,%rax), %xmm0
mulsd (%rdx), %xmm0
addsd (%rsi,%rax), %xmm0
movsd %xmm0, (%rsi,%rax)
addq $8, %rax
cmpq $40000, %rax
jne .L13
addq $8, %r9
addl $5000, %r10d
addq $40000, %rcx
cmpl $25000000, %r10d
jne .L14
ret
.cfi_endproc
.LFE2071:
.size _Z17trans_norm_vectorPdS_S_S_, .-_Z17trans_norm_vectorPdS_S_S_
.globl _Z49__device_stub__Z24trans_norm_vector_kernelPdS_S_iPdS_S_i
.type _Z49__device_stub__Z24trans_norm_vector_kernelPdS_S_iPdS_S_i, @function
_Z49__device_stub__Z24trans_norm_vector_kernelPdS_S_iPdS_S_i:
.LFB2098:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24trans_norm_vector_kernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z49__device_stub__Z24trans_norm_vector_kernelPdS_S_iPdS_S_i, .-_Z49__device_stub__Z24trans_norm_vector_kernelPdS_S_iPdS_S_i
.globl _Z24trans_norm_vector_kernelPdS_S_i
.type _Z24trans_norm_vector_kernelPdS_S_i, @function
_Z24trans_norm_vector_kernelPdS_S_i:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z24trans_norm_vector_kernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z24trans_norm_vector_kernelPdS_S_i, .-_Z24trans_norm_vector_kernelPdS_S_i
.globl _Z49__device_stub__Z24trans_norm_vector_sharedPdS_S_iPdS_S_i
.type _Z49__device_stub__Z24trans_norm_vector_sharedPdS_S_iPdS_S_i, @function
_Z49__device_stub__Z24trans_norm_vector_sharedPdS_S_iPdS_S_i:
.LFB2100:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24trans_norm_vector_sharedPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z49__device_stub__Z24trans_norm_vector_sharedPdS_S_iPdS_S_i, .-_Z49__device_stub__Z24trans_norm_vector_sharedPdS_S_iPdS_S_i
.globl _Z24trans_norm_vector_sharedPdS_S_i
.type _Z24trans_norm_vector_sharedPdS_S_i, @function
_Z24trans_norm_vector_sharedPdS_S_i:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z24trans_norm_vector_sharedPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z24trans_norm_vector_sharedPdS_S_i, .-_Z24trans_norm_vector_sharedPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "NX: %d NY: %d\n"
.LC5:
.string "GPU Runtime :%0.6lfs\n"
.LC6:
.string "GPU Shared Runtime :%0.6lfs\n"
.LC7:
.string "CPU Runtime :%0.6lfs\n"
.LC10:
.string "Error %.20f in (%d)\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "Vector\n\tTotal Results: %d\n\tError count: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2072:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movl $200000000, %edi
call malloc@PLT
movq %rax, %r15
movl $40000, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, (%rsp)
movl $40000, %edi
call malloc@PLT
movq %rax, %rbp
movl $40000, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $40000, %edi
call malloc@PLT
movq %rax, %r12
movq %r15, %rsi
movq %rbx, %rdi
call _Z10init_arrayPdS_
leaq 24(%rsp), %rdi
movl $200000000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $200000000, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $5000, %r8d
movl $5000, %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, 92(%rsp)
movl $157, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $32, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $157, 120(%rsp)
movl $1, 124(%rsp)
leaq 128(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1, %ecx
movl $200000000, %edx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl 112(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 104(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L36:
movl 112(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 104(%rsp), %rdx
movq 116(%rsp), %rdi
movl 124(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L37:
movl $2, %ecx
movl $40000, %edx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
leaq 144(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 144(%rsp), %rax
subq 128(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC4(%rip), %xmm1
mulsd %xmm1, %xmm0
movq 152(%rsp), %rax
subq 136(%rsp), %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
addsd %xmm2, %xmm0
divsd %xmm1, %xmm0
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
leaq 128(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1, %ecx
movl $200000000, %edx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000, %edx
movq (%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl 112(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 104(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L38:
movl 112(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 104(%rsp), %rdx
movq 116(%rsp), %rdi
movl 124(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L39:
movl $2, %ecx
movl $40000, %edx
movq 72(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
leaq 144(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
movq 144(%rsp), %rax
subq 128(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC4(%rip), %xmm0
movq 152(%rsp), %rax
subq 136(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
divsd .LC4(%rip), %xmm0
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
leaq 128(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 8(%rsp), %rcx
movq %r12, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call _Z17trans_norm_vectorPdS_S_S_
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
movq 144(%rsp), %rax
subq 128(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC4(%rip), %xmm0
movq 152(%rsp), %rax
subq 136(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
divsd .LC4(%rip), %xmm0
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl $0, %ebx
movl $0, %r13d
leaq .LC10(%rip), %r14
jmp .L42
.L47:
movl $0, %ecx
movq 48(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z49__device_stub__Z24trans_norm_vector_kernelPdS_S_iPdS_S_i
jmp .L36
.L48:
movl $1, %ecx
movq 40(%rsp), %rdx
movq 48(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z49__device_stub__Z24trans_norm_vector_kernelPdS_S_iPdS_S_i
jmp .L37
.L49:
movl $0, %ecx
movq 80(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z49__device_stub__Z24trans_norm_vector_sharedPdS_S_iPdS_S_i
jmp .L38
.L50:
movl $1, %ecx
movq 72(%rsp), %rdx
movq 80(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z49__device_stub__Z24trans_norm_vector_sharedPdS_S_iPdS_S_i
jmp .L39
.L40:
addq $1, %rbx
cmpq $5000, %rbx
je .L51
.L42:
movsd (%r12,%rbx,8), %xmm1
movapd %xmm1, %xmm0
subsd 0(%rbp,%rbx,8), %xmm0
divsd %xmm1, %xmm0
andpd .LC8(%rip), %xmm0
comisd .LC9(%rip), %xmm0
jbe .L40
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %r13d
jmp .L40
.L51:
movl %r13d, %ecx
movl $25000000, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2072:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC12:
.string "_Z24trans_norm_vector_sharedPdS_S_i"
.align 8
.LC13:
.string "_Z24trans_norm_vector_kernelPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2103:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z24trans_norm_vector_sharedPdS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z24trans_norm_vector_kernelPdS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1085507584
.align 8
.LC1:
.long 1413754136
.long 1074340347
.align 8
.LC4:
.long 0
.long 1093567616
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC8:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC9:
.long -2036257893
.long 1023837339
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "TransNormVector.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10init_arrayPdS_
.LCPI0_0:
.quad 0x40b3880000000000 # double 5000
.LCPI0_1:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.text
.globl _Z10init_arrayPdS_
.p2align 4, 0x90
.type _Z10init_arrayPdS_,@function
_Z10init_arrayPdS_: # @_Z10init_arrayPdS_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB0_1: # %.preheader14
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm2, %xmm2
cvtsi2sd %ecx, %xmm2
mulsd %xmm1, %xmm2
divsd %xmm0, %xmm2
movsd %xmm2, (%rsi,%rcx,8)
incq %rcx
cmpq $5000, %rcx # imm = 0x1388
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rax
addq $40000, %rsi # imm = 0x9C40
cmpq $5000, %rax # imm = 0x1388
jne .LBB0_1
# %bb.4: # %.preheader.preheader
xorl %eax, %eax
movsd .LCPI0_1(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB0_5: # %.preheader
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm0, %xmm1
movsd %xmm1, (%rdi,%rax,8)
incq %rax
cmpq $5000, %rax # imm = 0x1388
jne .LBB0_5
# %bb.6:
retq
.Lfunc_end0:
.size _Z10init_arrayPdS_, .Lfunc_end0-_Z10init_arrayPdS_
.cfi_endproc
# -- End function
.globl _Z17trans_norm_vectorPdS_S_S_ # -- Begin function _Z17trans_norm_vectorPdS_S_S_
.p2align 4, 0x90
.type _Z17trans_norm_vectorPdS_S_S_,@function
_Z17trans_norm_vectorPdS_S_S_: # @_Z17trans_norm_vectorPdS_S_S_
.cfi_startproc
# %bb.0: # %.preheader31.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
xorl %r13d, %r13d
movl $40000, %edx # imm = 0x9C40
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # %.preheader31
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
# Child Loop BB1_4 Depth 2
movq $0, (%rbx,%r13,8)
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r12,%rax,8), %xmm1 # xmm1 = mem[0],zero
mulsd (%r15,%rax,8), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, (%rbx,%r13,8)
incq %rax
cmpq $5000, %rax # imm = 0x1388
jne .LBB1_2
# %bb.3: # %.preheader
# in Loop: Header=BB1_1 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r12,%rax,8), %xmm0 # xmm0 = mem[0],zero
mulsd (%rbx,%r13,8), %xmm0
addsd (%r14,%rax,8), %xmm0
movsd %xmm0, (%r14,%rax,8)
incq %rax
cmpq $5000, %rax # imm = 0x1388
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_1 Depth=1
incq %r13
addq $40000, %r12 # imm = 0x9C40
cmpq $5000, %r13 # imm = 0x1388
jne .LBB1_1
# %bb.6:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z17trans_norm_vectorPdS_S_S_, .Lfunc_end1-_Z17trans_norm_vectorPdS_S_S_
.cfi_endproc
# -- End function
.globl _Z39__device_stub__trans_norm_vector_kernelPdS_S_i # -- Begin function _Z39__device_stub__trans_norm_vector_kernelPdS_S_i
.p2align 4, 0x90
.type _Z39__device_stub__trans_norm_vector_kernelPdS_S_i,@function
_Z39__device_stub__trans_norm_vector_kernelPdS_S_i: # @_Z39__device_stub__trans_norm_vector_kernelPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24trans_norm_vector_kernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z39__device_stub__trans_norm_vector_kernelPdS_S_i, .Lfunc_end2-_Z39__device_stub__trans_norm_vector_kernelPdS_S_i
.cfi_endproc
# -- End function
.globl _Z39__device_stub__trans_norm_vector_sharedPdS_S_i # -- Begin function _Z39__device_stub__trans_norm_vector_sharedPdS_S_i
.p2align 4, 0x90
.type _Z39__device_stub__trans_norm_vector_sharedPdS_S_i,@function
_Z39__device_stub__trans_norm_vector_sharedPdS_S_i: # @_Z39__device_stub__trans_norm_vector_sharedPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24trans_norm_vector_sharedPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z39__device_stub__trans_norm_vector_sharedPdS_S_i, .Lfunc_end3-_Z39__device_stub__trans_norm_vector_sharedPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x40b3880000000000 # double 5000
.LCPI4_1:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI4_2:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI4_4:
.quad 0x3d06849b86a12b9b # double 9.9999999999999999E-15
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI4_3:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $200000000, %edi # imm = 0xBEBC200
callq malloc
movq %rax, %rbx
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r14
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r15
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r12
xorl %eax, %eax
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
movq %rbx, %rcx
.p2align 4, 0x90
.LBB4_1: # %.preheader14.i
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm2, %xmm2
cvtsi2sd %edx, %xmm2
mulsd %xmm1, %xmm2
divsd %xmm0, %xmm2
movsd %xmm2, (%rcx,%rdx,8)
incq %rdx
cmpq $5000, %rdx # imm = 0x1388
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %rax
addq $40000, %rcx # imm = 0x9C40
cmpq $5000, %rax # imm = 0x1388
jne .LBB4_1
# %bb.4: # %.preheader.i.preheader
xorl %eax, %eax
movsd .LCPI4_1(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB4_5: # %.preheader.i
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm0, %xmm1
movsd %xmm1, (%r14,%rax,8)
incq %rax
cmpq $5000, %rax # imm = 0x1388
jne .LBB4_5
# %bb.6: # %_Z10init_arrayPdS_.exit
movabsq $674309865473, %rbp # imm = 0x9D00000001
movabsq $137438953473, %r13 # imm = 0x2000000001
leaq 184(%rsp), %rdi
movl $200000000, %esi # imm = 0xBEBC200
callq hipMalloc
leaq 208(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 200(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 192(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 136(%rsp), %rdi
movl $200000000, %esi # imm = 0xBEBC200
callq hipMalloc
leaq 176(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 168(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 160(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq stdout(%rip), %rdi
movl $.L.str, %esi
movl $5000, %edx # imm = 0x1388
movl $5000, %ecx # imm = 0x1388
xorl %eax, %eax
callq fprintf
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 184(%rsp), %rdi
movl $200000000, %edx # imm = 0xBEBC200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 208(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 184(%rsp), %rax
movq 208(%rsp), %rcx
movq 192(%rsp), %rdx
movq %rax, 80(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 40(%rsp)
movl $0, (%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24trans_norm_vector_kernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_10
# %bb.9:
movq 184(%rsp), %rax
movq 192(%rsp), %rcx
movq 200(%rsp), %rdx
movq %rax, 80(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 40(%rsp)
movl $1, (%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24trans_norm_vector_kernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_10:
movq 200(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq stdout(%rip), %rdi
movq 64(%rsp), %rax
movq 72(%rsp), %rcx
subq 144(%rsp), %rax
cvtsi2sd %rax, %xmm1
movsd .LCPI4_2(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
subq 152(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
addsd %xmm1, %xmm0
divsd %xmm2, %xmm0
movl $.L.str.1, %esi
movb $1, %al
callq fprintf
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 136(%rsp), %rdi
movl $200000000, %edx # imm = 0xBEBC200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 176(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_12
# %bb.11:
movq 136(%rsp), %rax
movq 176(%rsp), %rcx
movq 160(%rsp), %rdx
movq %rax, 48(%rsp)
movq %rcx, 40(%rsp)
movq %rdx, 32(%rsp)
movl $0, 60(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 60(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24trans_norm_vector_sharedPdS_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_12:
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_14
# %bb.13:
movq 136(%rsp), %rax
movq 160(%rsp), %rcx
movq 168(%rsp), %rdx
movq %rax, 48(%rsp)
movq %rcx, 40(%rsp)
movq %rdx, 32(%rsp)
movl $1, 60(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 60(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24trans_norm_vector_sharedPdS_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_14:
movq 168(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
xorl %r13d, %r13d
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq stdout(%rip), %rdi
movq 64(%rsp), %rax
subq 144(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
movq 72(%rsp), %rax
movsd .LCPI4_2(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
subq 152(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm1, %xmm0
divsd %xmm2, %xmm0
movl $.L.str.2, %esi
movb $1, %al
callq fprintf
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $40000, %edx # imm = 0x9C40
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
movq %rbx, %rax
.p2align 4, 0x90
.LBB4_15: # %.preheader31.i
# =>This Loop Header: Depth=1
# Child Loop BB4_16 Depth 2
# Child Loop BB4_18 Depth 2
xorpd %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_16: # Parent Loop BB4_15 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rax,%rcx,8), %xmm1 # xmm1 = mem[0],zero
mulsd (%r14,%rcx,8), %xmm1
addsd %xmm1, %xmm0
incq %rcx
cmpq $5000, %rcx # imm = 0x1388
jne .LBB4_16
# %bb.17: # %.preheader.i86.preheader
# in Loop: Header=BB4_15 Depth=1
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_18: # %.preheader.i86
# Parent Loop BB4_15 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rax,%rcx,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
addsd (%r12,%rcx,8), %xmm1
movsd %xmm1, (%r12,%rcx,8)
incq %rcx
cmpq $5000, %rcx # imm = 0x1388
jne .LBB4_18
# %bb.19: # in Loop: Header=BB4_15 Depth=1
incq %r13
addq $40000, %rax # imm = 0x9C40
cmpq $5000, %r13 # imm = 0x1388
jne .LBB4_15
# %bb.20: # %_Z17trans_norm_vectorPdS_S_S_.exit
xorl %r13d, %r13d
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq stdout(%rip), %rdi
movq 64(%rsp), %rax
subq 144(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
movq 72(%rsp), %rax
movsd .LCPI4_2(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
subq 152(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm1, %xmm0
divsd %xmm2, %xmm0
movl $.L.str.3, %esi
movb $1, %al
callq fprintf
movapd .LCPI4_3(%rip), %xmm2 # xmm2 = [NaN,NaN]
movsd .LCPI4_4(%rip), %xmm3 # xmm3 = mem[0],zero
xorl %ebp, %ebp
jmp .LBB4_21
.p2align 4, 0x90
.LBB4_23: # in Loop: Header=BB4_21 Depth=1
incq %r13
cmpq $5000, %r13 # imm = 0x1388
je .LBB4_24
.LBB4_21: # =>This Inner Loop Header: Depth=1
movsd (%r12,%r13,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm1, %xmm0
subsd (%r15,%r13,8), %xmm0
divsd %xmm1, %xmm0
andpd %xmm2, %xmm0
ucomisd %xmm3, %xmm0
jbe .LBB4_23
# %bb.22: # in Loop: Header=BB4_21 Depth=1
movl $.L.str.4, %edi
movl %r13d, %esi
movb $1, %al
callq printf
movsd .LCPI4_4(%rip), %xmm3 # xmm3 = mem[0],zero
movapd .LCPI4_3(%rip), %xmm2 # xmm2 = [NaN,NaN]
incl %ebp
jmp .LBB4_23
.LBB4_24:
movl $.L.str.5, %edi
movl $25000000, %esi # imm = 0x17D7840
movl %ebp, %edx
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 136(%rsp), %rdi
callq hipFree
movq 176(%rsp), %rdi
callq hipFree
movq 168(%rsp), %rdi
callq hipFree
movq 160(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24trans_norm_vector_kernelPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24trans_norm_vector_sharedPdS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24trans_norm_vector_kernelPdS_S_i,@object # @_Z24trans_norm_vector_kernelPdS_S_i
.section .rodata,"a",@progbits
.globl _Z24trans_norm_vector_kernelPdS_S_i
.p2align 3, 0x0
_Z24trans_norm_vector_kernelPdS_S_i:
.quad _Z39__device_stub__trans_norm_vector_kernelPdS_S_i
.size _Z24trans_norm_vector_kernelPdS_S_i, 8
.type _Z24trans_norm_vector_sharedPdS_S_i,@object # @_Z24trans_norm_vector_sharedPdS_S_i
.globl _Z24trans_norm_vector_sharedPdS_S_i
.p2align 3, 0x0
_Z24trans_norm_vector_sharedPdS_S_i:
.quad _Z39__device_stub__trans_norm_vector_sharedPdS_S_i
.size _Z24trans_norm_vector_sharedPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "NX: %d NY: %d\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU Runtime :%0.6lfs\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPU Shared Runtime :%0.6lfs\n"
.size .L.str.2, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CPU Runtime :%0.6lfs\n"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error %.20f in (%d)\n"
.size .L.str.4, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Vector\n\tTotal Results: %d\n\tError count: %d\n"
.size .L.str.5, 44
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24trans_norm_vector_kernelPdS_S_i"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z24trans_norm_vector_sharedPdS_S_i"
.size .L__unnamed_2, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__trans_norm_vector_kernelPdS_S_i
.addrsig_sym _Z39__device_stub__trans_norm_vector_sharedPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24trans_norm_vector_kernelPdS_S_i
.addrsig_sym _Z24trans_norm_vector_sharedPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <cuda.h>
#include <device_functions.h>
#include <cuda_runtime_api.h>
#include<iostream>
#define imin(a,b) (a<b?a:b)
#define sum_squares(x) (x*(x+1)*(2*x+1)/6)
const int N = 33 * 1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);
__global__
void dot(float* a, float* b, float* c)
{
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp = 0;
while (tid < N)
{
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = temp;
// sync between All the threads in a Block
__syncthreads();
int i = blockDim.x / 2;
while (i != 0)
{
if (cacheIndex < i)
{
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads(); // Also incorrect
}
//__syncthreads(); // incorrect
i /= 2;
}
if (cacheIndex == 0)
{
c[blockIdx.x] = cache[0];
}
}
int main(void)
{
float c;
float* a, * b, * partial_c;
float* dev_a, * dev_b, * dev_partial_c;
a = (float*)malloc(sizeof(float) * N);
b = (float*)malloc(sizeof(float) * N);
partial_c = (float*)malloc(sizeof(float) * blocksPerGrid);
cudaMalloc((void**)&dev_a, sizeof(float) * N);
cudaMalloc((void**)&dev_b, sizeof(float) * N);
cudaMalloc((void**)&dev_partial_c, sizeof(float) * blocksPerGrid);
for (int i = 0; i < N; i++)
{
a[i] = i;
b[i] = i * 2;
}
cudaMemcpy(dev_a, a, sizeof(float) * N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, sizeof(float) * N, cudaMemcpyHostToDevice);
dot <<<blocksPerGrid, threadsPerBlock>>> (dev_a, dev_b, dev_partial_c);
cudaMemcpy(partial_c, dev_partial_c, sizeof(float) * blocksPerGrid, cudaMemcpyDeviceToHost);
c = 0;
for (int i = 0; i < blocksPerGrid; i++)
{
c += partial_c[i];
}
printf("Does GPU value %.6g = %.6g?\n", c, sum_squares((float)(N - 1)));
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_partial_c);
free(a);
free(b);
free(partial_c);
return 0;
} | code for sm_80
Function : _Z3dotPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x150 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0040*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x0], R8 ; /* 0x0000000007007a24 */
/* 0x001fca00078e0208 */
/*0070*/ ISETP.GT.AND P0, PT, R0, 0x83ff, PT ; /* 0x000083ff0000780c */
/* 0x000fda0003f04270 */
/*0080*/ @P0 BRA 0x140 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*00a0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*00b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e0205 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.AND P0, PT, R0, 0x8400, PT ; /* 0x000084000000780c */
/* 0x000fe20003f06270 */
/*0120*/ FFMA R6, R5, R2, R6 ; /* 0x0000000205067223 */
/* 0x004fd80000000006 */
/*0130*/ @!P0 BRA 0xa0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0160*/ STS [R8.X4], R6 ; /* 0x0000000608007388 */
/* 0x0001e20000004800 */
/*0170*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*01a0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*01b0*/ @!P1 BRA 0x2d0 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*01c0*/ BSSY B0, 0x2d0 ; /* 0x0000010000007945 */
/* 0x001fe20003800000 */
/*01d0*/ SHF.L.U32 R0, R8, 0x2, RZ ; /* 0x0000000208007819 */
/* 0x000fe200000006ff */
/*01e0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01f0*/ ISETP.GE.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f26270 */
/*0200*/ @!P1 LEA R2, R3.reuse, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x040fe200078e10ff */
/*0210*/ @!P1 LDS R4, [R8.X4] ; /* 0x0000000008049984 */
/* 0x000fe20000004800 */
/*0220*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe60003800000 */
/*0230*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0240*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fe20000000000 */
/*0250*/ IADD3 R5, R3.reuse, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x040fe40007ffe0ff */
/*0260*/ LEA.HI R3, R3, R3, RZ, 0x1 ; /* 0x0000000303037211 */
/* 0x000fc400078f08ff */
/*0270*/ @!P1 STS [R8.X4], R4 ; /* 0x0000000408009388 */
/* 0x0001e40000004800 */
/*0280*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fe40000011403 */
/*0290*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fe20000010000 */
/*02a0*/ ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fda0003f24070 */
/*02b0*/ @P1 BRA 0x1f0 ; /* 0xffffff3000001947 */
/* 0x001fea000383ffff */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*02e0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02f0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0300*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fca00078e0002 */
/*0310*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <cuda.h>
#include <device_functions.h>
#include <cuda_runtime_api.h>
#include<iostream>
#define imin(a,b) (a<b?a:b)
#define sum_squares(x) (x*(x+1)*(2*x+1)/6)
const int N = 33 * 1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);
__global__
void dot(float* a, float* b, float* c)
{
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp = 0;
while (tid < N)
{
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = temp;
// sync between All the threads in a Block
__syncthreads();
int i = blockDim.x / 2;
while (i != 0)
{
if (cacheIndex < i)
{
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads(); // Also incorrect
}
//__syncthreads(); // incorrect
i /= 2;
}
if (cacheIndex == 0)
{
c[blockIdx.x] = cache[0];
}
}
int main(void)
{
float c;
float* a, * b, * partial_c;
float* dev_a, * dev_b, * dev_partial_c;
a = (float*)malloc(sizeof(float) * N);
b = (float*)malloc(sizeof(float) * N);
partial_c = (float*)malloc(sizeof(float) * blocksPerGrid);
cudaMalloc((void**)&dev_a, sizeof(float) * N);
cudaMalloc((void**)&dev_b, sizeof(float) * N);
cudaMalloc((void**)&dev_partial_c, sizeof(float) * blocksPerGrid);
for (int i = 0; i < N; i++)
{
a[i] = i;
b[i] = i * 2;
}
cudaMemcpy(dev_a, a, sizeof(float) * N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, sizeof(float) * N, cudaMemcpyHostToDevice);
dot <<<blocksPerGrid, threadsPerBlock>>> (dev_a, dev_b, dev_partial_c);
cudaMemcpy(partial_c, dev_partial_c, sizeof(float) * blocksPerGrid, cudaMemcpyDeviceToHost);
c = 0;
for (int i = 0; i < blocksPerGrid; i++)
{
c += partial_c[i];
}
printf("Does GPU value %.6g = %.6g?\n", c, sum_squares((float)(N - 1)));
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_partial_c);
free(a);
free(b);
free(partial_c);
return 0;
} | .file "tmpxft_0015727d_00000000-6_File6_Dot_SharedMemory.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3dotPfS_S_PfS_S_
.type _Z26__device_stub__Z3dotPfS_S_PfS_S_, @function
_Z26__device_stub__Z3dotPfS_S_PfS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3dotPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z3dotPfS_S_PfS_S_, .-_Z26__device_stub__Z3dotPfS_S_PfS_S_
.globl _Z3dotPfS_S_
.type _Z3dotPfS_S_, @function
_Z3dotPfS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3dotPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3dotPfS_S_, .-_Z3dotPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Does GPU value %.6g = %.6g?\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $135168, %edi
call malloc@PLT
movq %rax, %rbp
movl $135168, %edi
call malloc@PLT
movq %rax, %rbx
movl $128, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $135168, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $135168, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
leal (%rax,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $33792, %rax
jne .L12
movl $1, %ecx
movl $135168, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $135168, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $32, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, %rax
leaq 128(%r12), %rdx
pxor %xmm0, %xmm0
.L14:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L14
cvtss2sd %xmm0, %xmm0
movsd .LC1(%rip), %xmm1
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3dotPfS_S_PfS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3dotPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1118266684
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <cuda.h>
#include <device_functions.h>
#include <cuda_runtime_api.h>
#include<iostream>
#define imin(a,b) (a<b?a:b)
#define sum_squares(x) (x*(x+1)*(2*x+1)/6)
const int N = 33 * 1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);
__global__
void dot(float* a, float* b, float* c)
{
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp = 0;
while (tid < N)
{
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = temp;
// sync between All the threads in a Block
__syncthreads();
int i = blockDim.x / 2;
while (i != 0)
{
if (cacheIndex < i)
{
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads(); // Also incorrect
}
//__syncthreads(); // incorrect
i /= 2;
}
if (cacheIndex == 0)
{
c[blockIdx.x] = cache[0];
}
}
int main(void)
{
float c;
float* a, * b, * partial_c;
float* dev_a, * dev_b, * dev_partial_c;
a = (float*)malloc(sizeof(float) * N);
b = (float*)malloc(sizeof(float) * N);
partial_c = (float*)malloc(sizeof(float) * blocksPerGrid);
cudaMalloc((void**)&dev_a, sizeof(float) * N);
cudaMalloc((void**)&dev_b, sizeof(float) * N);
cudaMalloc((void**)&dev_partial_c, sizeof(float) * blocksPerGrid);
for (int i = 0; i < N; i++)
{
a[i] = i;
b[i] = i * 2;
}
cudaMemcpy(dev_a, a, sizeof(float) * N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, sizeof(float) * N, cudaMemcpyHostToDevice);
dot <<<blocksPerGrid, threadsPerBlock>>> (dev_a, dev_b, dev_partial_c);
cudaMemcpy(partial_c, dev_partial_c, sizeof(float) * blocksPerGrid, cudaMemcpyDeviceToHost);
c = 0;
for (int i = 0; i < blocksPerGrid; i++)
{
c += partial_c[i];
}
printf("Does GPU value %.6g = %.6g?\n", c, sum_squares((float)(N - 1)));
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_partial_c);
free(a);
free(b);
free(partial_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <hip/device_functions.h>
#include <hip/hip_runtime_api.h>
#include<iostream>
#define imin(a,b) (a<b?a:b)
#define sum_squares(x) (x*(x+1)*(2*x+1)/6)
const int N = 33 * 1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);
__global__
void dot(float* a, float* b, float* c)
{
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp = 0;
while (tid < N)
{
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = temp;
// sync between All the threads in a Block
__syncthreads();
int i = blockDim.x / 2;
while (i != 0)
{
if (cacheIndex < i)
{
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads(); // Also incorrect
}
//__syncthreads(); // incorrect
i /= 2;
}
if (cacheIndex == 0)
{
c[blockIdx.x] = cache[0];
}
}
int main(void)
{
float c;
float* a, * b, * partial_c;
float* dev_a, * dev_b, * dev_partial_c;
a = (float*)malloc(sizeof(float) * N);
b = (float*)malloc(sizeof(float) * N);
partial_c = (float*)malloc(sizeof(float) * blocksPerGrid);
hipMalloc((void**)&dev_a, sizeof(float) * N);
hipMalloc((void**)&dev_b, sizeof(float) * N);
hipMalloc((void**)&dev_partial_c, sizeof(float) * blocksPerGrid);
for (int i = 0; i < N; i++)
{
a[i] = i;
b[i] = i * 2;
}
hipMemcpy(dev_a, a, sizeof(float) * N, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, sizeof(float) * N, hipMemcpyHostToDevice);
dot <<<blocksPerGrid, threadsPerBlock>>> (dev_a, dev_b, dev_partial_c);
hipMemcpy(partial_c, dev_partial_c, sizeof(float) * blocksPerGrid, hipMemcpyDeviceToHost);
c = 0;
for (int i = 0; i < blocksPerGrid; i++)
{
c += partial_c[i];
}
printf("Does GPU value %.6g = %.6g?\n", c, sum_squares((float)(N - 1)));
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_partial_c);
free(a);
free(b);
free(partial_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/device_functions.h>
#include <hip/hip_runtime_api.h>
#include<iostream>
#define imin(a,b) (a<b?a:b)
#define sum_squares(x) (x*(x+1)*(2*x+1)/6)
const int N = 33 * 1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);
__global__
void dot(float* a, float* b, float* c)
{
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp = 0;
while (tid < N)
{
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = temp;
// sync between All the threads in a Block
__syncthreads();
int i = blockDim.x / 2;
while (i != 0)
{
if (cacheIndex < i)
{
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads(); // Also incorrect
}
//__syncthreads(); // incorrect
i /= 2;
}
if (cacheIndex == 0)
{
c[blockIdx.x] = cache[0];
}
}
int main(void)
{
float c;
float* a, * b, * partial_c;
float* dev_a, * dev_b, * dev_partial_c;
a = (float*)malloc(sizeof(float) * N);
b = (float*)malloc(sizeof(float) * N);
partial_c = (float*)malloc(sizeof(float) * blocksPerGrid);
hipMalloc((void**)&dev_a, sizeof(float) * N);
hipMalloc((void**)&dev_b, sizeof(float) * N);
hipMalloc((void**)&dev_partial_c, sizeof(float) * blocksPerGrid);
for (int i = 0; i < N; i++)
{
a[i] = i;
b[i] = i * 2;
}
hipMemcpy(dev_a, a, sizeof(float) * N, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, sizeof(float) * N, hipMemcpyHostToDevice);
dot <<<blocksPerGrid, threadsPerBlock>>> (dev_a, dev_b, dev_partial_c);
hipMemcpy(partial_c, dev_partial_c, sizeof(float) * blocksPerGrid, hipMemcpyDeviceToHost);
c = 0;
for (int i = 0; i < blocksPerGrid; i++)
{
c += partial_c[i];
}
printf("Does GPU value %.6g = %.6g?\n", c, sum_squares((float)(N - 1)));
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_partial_c);
free(a);
free(b);
free(partial_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3dotPfS_S_
.globl _Z3dotPfS_S_
.p2align 8
.type _Z3dotPfS_S_,@function
_Z3dotPfS_S_:
s_load_b32 s3, s[0:1], 0x24
s_add_u32 s4, s0, 24
s_mov_b32 s2, s15
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmpx_gt_i32_e32 0x8400, v1
s_cbranch_execz .LBB0_4
s_load_b32 s10, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s10, s3
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s10, v1
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x83ff, v1
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v2, v4
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s9
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_9
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_cbranch_scc0 .LBB0_5
.LBB0_9:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_8
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_8
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotPfS_S_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3dotPfS_S_, .Lfunc_end0-_Z3dotPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3dotPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/device_functions.h>
#include <hip/hip_runtime_api.h>
#include<iostream>
#define imin(a,b) (a<b?a:b)
#define sum_squares(x) (x*(x+1)*(2*x+1)/6)
const int N = 33 * 1024;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);
__global__
void dot(float* a, float* b, float* c)
{
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
float temp = 0;
while (tid < N)
{
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = temp;
// sync between All the threads in a Block
__syncthreads();
int i = blockDim.x / 2;
while (i != 0)
{
if (cacheIndex < i)
{
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads(); // Also incorrect
}
//__syncthreads(); // incorrect
i /= 2;
}
if (cacheIndex == 0)
{
c[blockIdx.x] = cache[0];
}
}
int main(void)
{
float c;
float* a, * b, * partial_c;
float* dev_a, * dev_b, * dev_partial_c;
a = (float*)malloc(sizeof(float) * N);
b = (float*)malloc(sizeof(float) * N);
partial_c = (float*)malloc(sizeof(float) * blocksPerGrid);
hipMalloc((void**)&dev_a, sizeof(float) * N);
hipMalloc((void**)&dev_b, sizeof(float) * N);
hipMalloc((void**)&dev_partial_c, sizeof(float) * blocksPerGrid);
for (int i = 0; i < N; i++)
{
a[i] = i;
b[i] = i * 2;
}
hipMemcpy(dev_a, a, sizeof(float) * N, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, sizeof(float) * N, hipMemcpyHostToDevice);
dot <<<blocksPerGrid, threadsPerBlock>>> (dev_a, dev_b, dev_partial_c);
hipMemcpy(partial_c, dev_partial_c, sizeof(float) * blocksPerGrid, hipMemcpyDeviceToHost);
c = 0;
for (int i = 0; i < blocksPerGrid; i++)
{
c += partial_c[i];
}
printf("Does GPU value %.6g = %.6g?\n", c, sum_squares((float)(N - 1)));
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_partial_c);
free(a);
free(b);
free(partial_c);
return 0;
} | .text
.file "File6_Dot_SharedMemory.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__dotPfS_S_ # -- Begin function _Z18__device_stub__dotPfS_S_
.p2align 4, 0x90
.type _Z18__device_stub__dotPfS_S_,@function
_Z18__device_stub__dotPfS_S_: # @_Z18__device_stub__dotPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3dotPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__dotPfS_S_, .Lfunc_end0-_Z18__device_stub__dotPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x42a7653c00000000 # double 12861782884352
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $135168, %edi # imm = 0x21000
callq malloc
movq %rax, %rbx
movl $135168, %edi # imm = 0x21000
callq malloc
movq %rax, %r14
movl $128, %edi
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $135168, %esi # imm = 0x21000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $135168, %esi # imm = 0x21000
callq hipMalloc
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rcx,4)
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rcx,4)
incq %rcx
addl $2, %eax
cmpq $33792, %rcx # imm = 0x8400
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $135168, %edx # imm = 0x21000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $135168, %edx # imm = 0x21000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 224(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3dotPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $128, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
addss (%r15,%rax,4), %xmm0
incq %rax
cmpq $32, %rax
jne .LBB1_5
# %bb.6:
cvtss2sd %xmm0, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
movl $.L.str, %edi
movb $2, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3dotPfS_S_,@object # @_Z3dotPfS_S_
.section .rodata,"a",@progbits
.globl _Z3dotPfS_S_
.p2align 3, 0x0
_Z3dotPfS_S_:
.quad _Z18__device_stub__dotPfS_S_
.size _Z3dotPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Does GPU value %.6g = %.6g?\n"
.size .L.str, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3dotPfS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3dotPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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